[linux-2.6-block.git] / drivers / usb / gadget / udc / atmel_usba_udc.h

/*
 * Driver for the Atmel USBA high speed USB device controller
 *
 * Copyright (C) 2005-2007 Atmel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef __LINUX_USB_GADGET_USBA_UDC_H__
#define __LINUX_USB_GADGET_USBA_UDC_H__

/* USB register offsets */
#define USBA_CTRL				0x0000
#define USBA_FNUM				0x0004
#define USBA_INT_ENB				0x0010
#define USBA_INT_STA				0x0014
#define USBA_INT_CLR				0x0018
#define USBA_EPT_RST				0x001c
#define USBA_TST				0x00e0

/* USB endpoint register offsets */
#define USBA_EPT_CFG				0x0000
#define USBA_EPT_CTL_ENB			0x0004
#define USBA_EPT_CTL_DIS			0x0008
#define USBA_EPT_CTL				0x000c
#define USBA_EPT_SET_STA			0x0014
#define USBA_EPT_CLR_STA			0x0018
#define USBA_EPT_STA				0x001c

/* USB DMA register offsets */
#define USBA_DMA_NXT_DSC			0x0000
#define USBA_DMA_ADDRESS			0x0004
#define USBA_DMA_CONTROL			0x0008
#define USBA_DMA_STATUS				0x000c

/* Bitfields in CTRL */
#define USBA_DEV_ADDR_OFFSET			0
#define USBA_DEV_ADDR_SIZE			7
#define USBA_FADDR_EN				(1 <<  7)
#define USBA_EN_USBA				(1 <<  8)
#define USBA_DETACH				(1 <<  9)
#define USBA_REMOTE_WAKE_UP			(1 << 10)
#define USBA_PULLD_DIS				(1 << 11)

#if defined(CONFIG_AVR32)
#define USBA_ENABLE_MASK			USBA_EN_USBA
#define USBA_DISABLE_MASK			0
#elif defined(CONFIG_ARCH_AT91)
#define USBA_ENABLE_MASK			(USBA_EN_USBA | USBA_PULLD_DIS)
#define USBA_DISABLE_MASK			USBA_DETACH
#endif /* CONFIG_ARCH_AT91 */

/* Bitfields in FNUM */
#define USBA_MICRO_FRAME_NUM_OFFSET		0
#define USBA_MICRO_FRAME_NUM_SIZE		3
#define USBA_FRAME_NUMBER_OFFSET		3
#define USBA_FRAME_NUMBER_SIZE			11
#define USBA_FRAME_NUM_ERROR			(1 << 31)

/* Bitfields in INT_ENB/INT_STA/INT_CLR */
#define USBA_HIGH_SPEED				(1 <<  0)
#define USBA_DET_SUSPEND			(1 <<  1)
#define USBA_MICRO_SOF				(1 <<  2)
#define USBA_SOF				(1 <<  3)
#define USBA_END_OF_RESET			(1 <<  4)
#define USBA_WAKE_UP				(1 <<  5)
#define USBA_END_OF_RESUME			(1 <<  6)
#define USBA_UPSTREAM_RESUME			(1 <<  7)
#define USBA_EPT_INT_OFFSET			8
#define USBA_EPT_INT_SIZE			16
#define USBA_DMA_INT_OFFSET			24
#define USBA_DMA_INT_SIZE			8

/* Bitfields in EPT_RST */
#define USBA_RST_OFFSET				0
#define USBA_RST_SIZE				16

/* Bitfields in USBA_TST */
#define USBA_SPEED_CFG_OFFSET			0
#define USBA_SPEED_CFG_SIZE			2
#define USBA_TST_J_MODE				(1 <<  2)
#define USBA_TST_K_MODE				(1 <<  3)
#define USBA_TST_PKT_MODE			(1 <<  4)
#define USBA_OPMODE2				(1 <<  5)

/* Bitfields in EPT_CFG */
#define USBA_EPT_SIZE_OFFSET			0
#define USBA_EPT_SIZE_SIZE			3
#define USBA_EPT_DIR_IN				(1 <<  3)
#define USBA_EPT_TYPE_OFFSET			4
#define USBA_EPT_TYPE_SIZE			2
#define USBA_BK_NUMBER_OFFSET			6
#define USBA_BK_NUMBER_SIZE			2
#define USBA_NB_TRANS_OFFSET			8
#define USBA_NB_TRANS_SIZE			2
#define USBA_EPT_MAPPED				(1 << 31)

/* Bitfields in EPT_CTL/EPT_CTL_ENB/EPT_CTL_DIS */
#define USBA_EPT_ENABLE				(1 <<  0)
#define USBA_AUTO_VALID				(1 <<  1)
#define USBA_INTDIS_DMA				(1 <<  3)
#define USBA_NYET_DIS				(1 <<  4)
#define USBA_DATAX_RX				(1 <<  6)
#define USBA_MDATA_RX				(1 <<  7)
/* Bits 8-15 and 31 enable interrupts for respective bits in EPT_STA */
#define USBA_BUSY_BANK_IE			(1 << 18)

/* Bitfields in EPT_SET_STA/EPT_CLR_STA/EPT_STA */
#define USBA_FORCE_STALL			(1 <<  5)
#define USBA_TOGGLE_CLR				(1 <<  6)
#define USBA_TOGGLE_SEQ_OFFSET			6
#define USBA_TOGGLE_SEQ_SIZE			2
#define USBA_ERR_OVFLW				(1 <<  8)
#define USBA_RX_BK_RDY				(1 <<  9)
#define USBA_KILL_BANK				(1 <<  9)
#define USBA_TX_COMPLETE			(1 << 10)
#define USBA_TX_PK_RDY				(1 << 11)
#define USBA_ISO_ERR_TRANS			(1 << 11)
#define USBA_RX_SETUP				(1 << 12)
#define USBA_ISO_ERR_FLOW			(1 << 12)
#define USBA_STALL_SENT				(1 << 13)
#define USBA_ISO_ERR_CRC			(1 << 13)
#define USBA_ISO_ERR_NBTRANS			(1 << 13)
#define USBA_NAK_IN				(1 << 14)
#define USBA_ISO_ERR_FLUSH			(1 << 14)
#define USBA_NAK_OUT				(1 << 15)
#define USBA_CURRENT_BANK_OFFSET		16
#define USBA_CURRENT_BANK_SIZE			2
#define USBA_BUSY_BANKS_OFFSET			18
#define USBA_BUSY_BANKS_SIZE			2
#define USBA_BYTE_COUNT_OFFSET			20
#define USBA_BYTE_COUNT_SIZE			11
#define USBA_SHORT_PACKET			(1 << 31)

/* Bitfields in DMA_CONTROL */
#define USBA_DMA_CH_EN				(1 <<  0)
#define USBA_DMA_LINK				(1 <<  1)
#define USBA_DMA_END_TR_EN			(1 <<  2)
#define USBA_DMA_END_BUF_EN			(1 <<  3)
#define USBA_DMA_END_TR_IE			(1 <<  4)
#define USBA_DMA_END_BUF_IE			(1 <<  5)
#define USBA_DMA_DESC_LOAD_IE			(1 <<  6)
#define USBA_DMA_BURST_LOCK			(1 <<  7)
#define USBA_DMA_BUF_LEN_OFFSET			16
#define USBA_DMA_BUF_LEN_SIZE			16

/* Bitfields in DMA_STATUS */
#define USBA_DMA_CH_ACTIVE			(1 <<  1)
#define USBA_DMA_END_TR_ST			(1 <<  4)
#define USBA_DMA_END_BUF_ST			(1 <<  5)
#define USBA_DMA_DESC_LOAD_ST			(1 <<  6)

/* Constants for SPEED_CFG */
#define USBA_SPEED_CFG_NORMAL			0
#define USBA_SPEED_CFG_FORCE_HIGH		2
#define USBA_SPEED_CFG_FORCE_FULL		3

/* Constants for EPT_SIZE */
#define USBA_EPT_SIZE_8				0
#define USBA_EPT_SIZE_16			1
#define USBA_EPT_SIZE_32			2
#define USBA_EPT_SIZE_64			3
#define USBA_EPT_SIZE_128			4
#define USBA_EPT_SIZE_256			5
#define USBA_EPT_SIZE_512			6
#define USBA_EPT_SIZE_1024			7

/* Constants for EPT_TYPE */
#define USBA_EPT_TYPE_CONTROL			0
#define USBA_EPT_TYPE_ISO			1
#define USBA_EPT_TYPE_BULK			2
#define USBA_EPT_TYPE_INT			3

/* Constants for BK_NUMBER */
#define USBA_BK_NUMBER_ZERO			0
#define USBA_BK_NUMBER_ONE			1
#define USBA_BK_NUMBER_DOUBLE			2
#define USBA_BK_NUMBER_TRIPLE			3

/* Bit manipulation macros */
#define USBA_BF(name, value)					\
	(((value) & ((1 << USBA_##name##_SIZE) - 1))		\
	 << USBA_##name##_OFFSET)
#define USBA_BFEXT(name, value)					\
	(((value) >> USBA_##name##_OFFSET)			\
	 & ((1 << USBA_##name##_SIZE) - 1))
#define USBA_BFINS(name, value, old)				\
	(((old) & ~(((1 << USBA_##name##_SIZE) - 1)		\
		    << USBA_##name##_OFFSET))			\
	 | USBA_BF(name, value))

/* Register access macros */
#ifdef CONFIG_AVR32
#define usba_io_readl	__raw_readl
#define usba_io_writel	__raw_writel
#define usba_io_writew	__raw_writew
#else
#define usba_io_readl	readl_relaxed
#define usba_io_writel	writel_relaxed
#define usba_io_writew	writew_relaxed
#endif

#define usba_readl(udc, reg)					\
	usba_io_readl((udc)->regs + USBA_##reg)
#define usba_writel(udc, reg, value)				\
	usba_io_writel((value), (udc)->regs + USBA_##reg)
#define usba_ep_readl(ep, reg)					\
	usba_io_readl((ep)->ep_regs + USBA_EPT_##reg)
#define usba_ep_writel(ep, reg, value)				\
	usba_io_writel((value), (ep)->ep_regs + USBA_EPT_##reg)
#define usba_dma_readl(ep, reg)					\
	usba_io_readl((ep)->dma_regs + USBA_DMA_##reg)
#define usba_dma_writel(ep, reg, value)				\
	usba_io_writel((value), (ep)->dma_regs + USBA_DMA_##reg)

/* Calculate base address for a given endpoint or DMA controller */
#define USBA_EPT_BASE(x)	(0x100 + (x) * 0x20)
#define USBA_DMA_BASE(x)	(0x300 + (x) * 0x10)
#define USBA_FIFO_BASE(x)	((x) << 16)

/* Synth parameters */
#define USBA_NR_DMAS		7

#define EP0_FIFO_SIZE		64
#define EP0_EPT_SIZE		USBA_EPT_SIZE_64
#define EP0_NR_BANKS		1

#define FIFO_IOMEM_ID	0
#define CTRL_IOMEM_ID	1

#define DBG_ERR		0x0001	/* report all error returns */
#define DBG_HW		0x0002	/* debug hardware initialization */
#define DBG_GADGET	0x0004	/* calls to/from gadget driver */
#define DBG_INT		0x0008	/* interrupts */
#define DBG_BUS		0x0010	/* report changes in bus state */
#define DBG_QUEUE	0x0020  /* debug request queue processing */
#define DBG_FIFO	0x0040  /* debug FIFO contents */
#define DBG_DMA		0x0080  /* debug DMA handling */
#define DBG_REQ		0x0100	/* print out queued request length */
#define DBG_ALL		0xffff
#define DBG_NONE	0x0000

#define DEBUG_LEVEL	(DBG_ERR)

#define DBG(level, fmt, ...)					\
	do {							\
		if ((level) & DEBUG_LEVEL)			\
			pr_debug("udc: " fmt, ## __VA_ARGS__);	\
	} while (0)

enum usba_ctrl_state {
	WAIT_FOR_SETUP,
	DATA_STAGE_IN,
	DATA_STAGE_OUT,
	STATUS_STAGE_IN,
	STATUS_STAGE_OUT,
	STATUS_STAGE_ADDR,
	STATUS_STAGE_TEST,
};
/*
  EP_STATE_IDLE,
  EP_STATE_SETUP,
  EP_STATE_IN_DATA,
  EP_STATE_OUT_DATA,
  EP_STATE_SET_ADDR_STATUS,
  EP_STATE_RX_STATUS,
  EP_STATE_TX_STATUS,
  EP_STATE_HALT,
*/

struct usba_dma_desc {
	dma_addr_t next;
	dma_addr_t addr;
	u32 ctrl;
};

struct usba_fifo_cfg {
	u8			hw_ep_num;
	u16			fifo_size;
	u8			nr_banks;
};

struct usba_ep {
	int					state;
	void __iomem				*ep_regs;
	void __iomem				*dma_regs;
	void __iomem				*fifo;
	struct usb_ep				ep;
	struct usba_udc				*udc;

	struct list_head			queue;

	u16					fifo_size;
	u8					nr_banks;
	u8					index;
	unsigned int				can_dma:1;
	unsigned int				can_isoc:1;
	unsigned int				is_isoc:1;
	unsigned int				is_in:1;
	unsigned long				ept_cfg;
#ifdef CONFIG_USB_GADGET_DEBUG_FS
	u32					last_dma_status;
	struct dentry				*debugfs_dir;
	struct dentry				*debugfs_queue;
	struct dentry				*debugfs_dma_status;
	struct dentry				*debugfs_state;
#endif
};

struct usba_request {
	struct usb_request			req;
	struct list_head			queue;

	u32					ctrl;

	unsigned int				submitted:1;
	unsigned int				last_transaction:1;
	unsigned int				using_dma:1;
	unsigned int				mapped:1;
};

struct usba_udc_errata {
	void (*toggle_bias)(struct usba_udc *udc, int is_on);
	void (*pulse_bias)(struct usba_udc *udc);
};

struct usba_udc {
	/* Protect hw registers from concurrent modifications */
	spinlock_t lock;

	/* Mutex to prevent concurrent start or stop */
	struct mutex vbus_mutex;

	void __iomem *regs;
	void __iomem *fifo;

	struct usb_gadget gadget;
	struct usb_gadget_driver *driver;
	struct platform_device *pdev;
	const struct usba_udc_errata *errata;
	int irq;
	int vbus_pin;
	int vbus_pin_inverted;
	int num_ep;
	int configured_ep;
	struct usba_fifo_cfg *fifo_cfg;
	struct clk *pclk;
	struct clk *hclk;
	struct usba_ep *usba_ep;
	bool bias_pulse_needed;
	bool clocked;

	u16 devstatus;

	u16 test_mode;
	int vbus_prev;

	u32 int_enb_cache;

#ifdef CONFIG_USB_GADGET_DEBUG_FS
	struct dentry *debugfs_root;
	struct dentry *debugfs_regs;
#endif

	struct regmap *pmc;
};

static inline struct usba_ep *to_usba_ep(struct usb_ep *ep)
{
	return container_of(ep, struct usba_ep, ep);
}

static inline struct usba_request *to_usba_req(struct usb_request *req)
{
	return container_of(req, struct usba_request, req);
}

static inline struct usba_udc *to_usba_udc(struct usb_gadget *gadget)
{
	return container_of(gadget, struct usba_udc, gadget);
}

#define ep_is_control(ep)	((ep)->index == 0)
#define ep_is_idle(ep)		((ep)->state == EP_STATE_IDLE)

#endif /* __LINUX_USB_GADGET_USBA_UDC_H */
Commit	Line	Data
914a3f3b HS	1	/*
	2	* Driver for the Atmel USBA high speed USB device controller
	3	*
	4	* Copyright (C) 2005-2007 Atmel Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#ifndef __LINUX_USB_GADGET_USBA_UDC_H__
	11	#define __LINUX_USB_GADGET_USBA_UDC_H__
	12
	13	/* USB register offsets */
	14	#define USBA_CTRL 0x0000
	15	#define USBA_FNUM 0x0004
	16	#define USBA_INT_ENB 0x0010
	17	#define USBA_INT_STA 0x0014
	18	#define USBA_INT_CLR 0x0018
	19	#define USBA_EPT_RST 0x001c
	20	#define USBA_TST 0x00e0
	21
	22	/* USB endpoint register offsets */
	23	#define USBA_EPT_CFG 0x0000
	24	#define USBA_EPT_CTL_ENB 0x0004
	25	#define USBA_EPT_CTL_DIS 0x0008
	26	#define USBA_EPT_CTL 0x000c
	27	#define USBA_EPT_SET_STA 0x0014
	28	#define USBA_EPT_CLR_STA 0x0018
	29	#define USBA_EPT_STA 0x001c
	30
	31	/* USB DMA register offsets */
	32	#define USBA_DMA_NXT_DSC 0x0000
	33	#define USBA_DMA_ADDRESS 0x0004
	34	#define USBA_DMA_CONTROL 0x0008
	35	#define USBA_DMA_STATUS 0x000c
	36
	37	/* Bitfields in CTRL */
	38	#define USBA_DEV_ADDR_OFFSET 0
	39	#define USBA_DEV_ADDR_SIZE 7
	40	#define USBA_FADDR_EN (1 << 7)
	41	#define USBA_EN_USBA (1 << 8)
	42	#define USBA_DETACH (1 << 9)
	43	#define USBA_REMOTE_WAKE_UP (1 << 10)
16a45bc8 SP	44	#define USBA_PULLD_DIS (1 << 11)
	45
	46	#if defined(CONFIG_AVR32)
	47	#define USBA_ENABLE_MASK USBA_EN_USBA
	48	#define USBA_DISABLE_MASK 0
	49	#elif defined(CONFIG_ARCH_AT91)
	50	#define USBA_ENABLE_MASK (USBA_EN_USBA \| USBA_PULLD_DIS)
	51	#define USBA_DISABLE_MASK USBA_DETACH
	52	#endif /* CONFIG_ARCH_AT91 */
914a3f3b HS	53
	54	/* Bitfields in FNUM */
	55	#define USBA_MICRO_FRAME_NUM_OFFSET 0
	56	#define USBA_MICRO_FRAME_NUM_SIZE 3
	57	#define USBA_FRAME_NUMBER_OFFSET 3
	58	#define USBA_FRAME_NUMBER_SIZE 11
	59	#define USBA_FRAME_NUM_ERROR (1 << 31)
	60
	61	/* Bitfields in INT_ENB/INT_STA/INT_CLR */
	62	#define USBA_HIGH_SPEED (1 << 0)
	63	#define USBA_DET_SUSPEND (1 << 1)
	64	#define USBA_MICRO_SOF (1 << 2)
	65	#define USBA_SOF (1 << 3)
	66	#define USBA_END_OF_RESET (1 << 4)
	67	#define USBA_WAKE_UP (1 << 5)
	68	#define USBA_END_OF_RESUME (1 << 6)
	69	#define USBA_UPSTREAM_RESUME (1 << 7)
	70	#define USBA_EPT_INT_OFFSET 8
	71	#define USBA_EPT_INT_SIZE 16
	72	#define USBA_DMA_INT_OFFSET 24
	73	#define USBA_DMA_INT_SIZE 8
	74
	75	/* Bitfields in EPT_RST */
	76	#define USBA_RST_OFFSET 0
	77	#define USBA_RST_SIZE 16
	78
	79	/* Bitfields in USBA_TST */
	80	#define USBA_SPEED_CFG_OFFSET 0
	81	#define USBA_SPEED_CFG_SIZE 2
	82	#define USBA_TST_J_MODE (1 << 2)
	83	#define USBA_TST_K_MODE (1 << 3)
	84	#define USBA_TST_PKT_MODE (1 << 4)
	85	#define USBA_OPMODE2 (1 << 5)
	86
	87	/* Bitfields in EPT_CFG */
	88	#define USBA_EPT_SIZE_OFFSET 0
	89	#define USBA_EPT_SIZE_SIZE 3
	90	#define USBA_EPT_DIR_IN (1 << 3)
	91	#define USBA_EPT_TYPE_OFFSET 4
	92	#define USBA_EPT_TYPE_SIZE 2
	93	#define USBA_BK_NUMBER_OFFSET 6
	94	#define USBA_BK_NUMBER_SIZE 2
	95	#define USBA_NB_TRANS_OFFSET 8
	96	#define USBA_NB_TRANS_SIZE 2
	97	#define USBA_EPT_MAPPED (1 << 31)
	98
	99	/* Bitfields in EPT_CTL/EPT_CTL_ENB/EPT_CTL_DIS */
	100	#define USBA_EPT_ENABLE (1 << 0)
	101	#define USBA_AUTO_VALID (1 << 1)
	102	#define USBA_INTDIS_DMA (1 << 3)
	103	#define USBA_NYET_DIS (1 << 4)
	104	#define USBA_DATAX_RX (1 << 6)
	105	#define USBA_MDATA_RX (1 << 7)
	106	/* Bits 8-15 and 31 enable interrupts for respective bits in EPT_STA */
	107	#define USBA_BUSY_BANK_IE (1 << 18)
	108
	109	/* Bitfields in EPT_SET_STA/EPT_CLR_STA/EPT_STA */
	110	#define USBA_FORCE_STALL (1 << 5)
	111	#define USBA_TOGGLE_CLR (1 << 6)
	112	#define USBA_TOGGLE_SEQ_OFFSET 6
	113	#define USBA_TOGGLE_SEQ_SIZE 2
	114	#define USBA_ERR_OVFLW (1 << 8)
	115	#define USBA_RX_BK_RDY (1 << 9)
	116	#define USBA_KILL_BANK (1 << 9)
117	#define USBA_TX_COMPLETE (1 << 10)
118	#define USBA_TX_PK_RDY (1 << 11)
119	#define USBA_ISO_ERR_TRANS (1 << 11)
120	#define USBA_RX_SETUP (1 << 12)
121	#define USBA_ISO_ERR_FLOW (1 << 12)
122	#define USBA_STALL_SENT (1 << 13)
123	#define USBA_ISO_ERR_CRC (1 << 13)
124	#define USBA_ISO_ERR_NBTRANS (1 << 13)
125	#define USBA_NAK_IN (1 << 14)
126	#define USBA_ISO_ERR_FLUSH (1 << 14)
127	#define USBA_NAK_OUT (1 << 15)
128	#define USBA_CURRENT_BANK_OFFSET 16
129	#define USBA_CURRENT_BANK_SIZE 2
130	#define USBA_BUSY_BANKS_OFFSET 18
131	#define USBA_BUSY_BANKS_SIZE 2
132	#define USBA_BYTE_COUNT_OFFSET 20
133	#define USBA_BYTE_COUNT_SIZE 11
134	#define USBA_SHORT_PACKET (1 << 31)
135
136	/* Bitfields in DMA_CONTROL */
137	#define USBA_DMA_CH_EN (1 << 0)
138	#define USBA_DMA_LINK (1 << 1)
139	#define USBA_DMA_END_TR_EN (1 << 2)
140	#define USBA_DMA_END_BUF_EN (1 << 3)
141	#define USBA_DMA_END_TR_IE (1 << 4)
142	#define USBA_DMA_END_BUF_IE (1 << 5)
143	#define USBA_DMA_DESC_LOAD_IE (1 << 6)
144	#define USBA_DMA_BURST_LOCK (1 << 7)
145	#define USBA_DMA_BUF_LEN_OFFSET 16
146	#define USBA_DMA_BUF_LEN_SIZE 16
147
148	/* Bitfields in DMA_STATUS */
149	#define USBA_DMA_CH_ACTIVE (1 << 1)
150	#define USBA_DMA_END_TR_ST (1 << 4)
151	#define USBA_DMA_END_BUF_ST (1 << 5)
152	#define USBA_DMA_DESC_LOAD_ST (1 << 6)
153
154	/* Constants for SPEED_CFG */
155	#define USBA_SPEED_CFG_NORMAL 0
156	#define USBA_SPEED_CFG_FORCE_HIGH 2
157	#define USBA_SPEED_CFG_FORCE_FULL 3
158
159	/* Constants for EPT_SIZE */
160	#define USBA_EPT_SIZE_8 0
161	#define USBA_EPT_SIZE_16 1
162	#define USBA_EPT_SIZE_32 2
163	#define USBA_EPT_SIZE_64 3
164	#define USBA_EPT_SIZE_128 4
165	#define USBA_EPT_SIZE_256 5
166	#define USBA_EPT_SIZE_512 6
167	#define USBA_EPT_SIZE_1024 7
168
169	/* Constants for EPT_TYPE */
170	#define USBA_EPT_TYPE_CONTROL 0
171	#define USBA_EPT_TYPE_ISO 1
172	#define USBA_EPT_TYPE_BULK 2
173	#define USBA_EPT_TYPE_INT 3
174
175	/* Constants for BK_NUMBER */
176	#define USBA_BK_NUMBER_ZERO 0
177	#define USBA_BK_NUMBER_ONE 1
178	#define USBA_BK_NUMBER_DOUBLE 2
179	#define USBA_BK_NUMBER_TRIPLE 3
180
181	/* Bit manipulation macros */
182	#define USBA_BF(name, value) \
183	(((value) & ((1 << USBA_##name##_SIZE) - 1)) \
184	<< USBA_##name##_OFFSET)
185	#define USBA_BFEXT(name, value) \
186	(((value) >> USBA_##name##_OFFSET) \
187	& ((1 << USBA_##name##_SIZE) - 1))
188	#define USBA_BFINS(name, value, old) \
189	(((old) & ~(((1 << USBA_##name##_SIZE) - 1) \
190	<< USBA_##name##_OFFSET)) \
191	\| USBA_BF(name, value))
192
193	/* Register access macros */
a3dd3bef BD	194	#ifdef CONFIG_AVR32
	195	#define usba_io_readl __raw_readl
	196	#define usba_io_writel __raw_writel
	197	#define usba_io_writew __raw_writew
	198	#else
	199	#define usba_io_readl readl_relaxed
	200	#define usba_io_writel writel_relaxed
	201	#define usba_io_writew writew_relaxed
	202	#endif
	203
914a3f3b	204	#define usba_readl(udc, reg) \
a3dd3bef	205	usba_io_readl((udc)->regs + USBA_##reg)
914a3f3b	206	#define usba_writel(udc, reg, value) \
a3dd3bef	207	usba_io_writel((value), (udc)->regs + USBA_##reg)
914a3f3b	208	#define usba_ep_readl(ep, reg) \
a3dd3bef	209	usba_io_readl((ep)->ep_regs + USBA_EPT_##reg)
914a3f3b	210	#define usba_ep_writel(ep, reg, value) \
a3dd3bef	211	usba_io_writel((value), (ep)->ep_regs + USBA_EPT_##reg)
914a3f3b	212	#define usba_dma_readl(ep, reg) \
a3dd3bef	213	usba_io_readl((ep)->dma_regs + USBA_DMA_##reg)
914a3f3b	214	#define usba_dma_writel(ep, reg, value) \
a3dd3bef	215	usba_io_writel((value), (ep)->dma_regs + USBA_DMA_##reg)
914a3f3b HS	216
	217	/* Calculate base address for a given endpoint or DMA controller */
	218	#define USBA_EPT_BASE(x) (0x100 + (x) * 0x20)
	219	#define USBA_DMA_BASE(x) (0x300 + (x) * 0x10)
	220	#define USBA_FIFO_BASE(x) ((x) << 16)
	221
	222	/* Synth parameters */
3fcba0d8	223	#define USBA_NR_DMAS 7
914a3f3b HS	224
	225	#define EP0_FIFO_SIZE 64
	226	#define EP0_EPT_SIZE USBA_EPT_SIZE_64
	227	#define EP0_NR_BANKS 1
	228
914a3f3b HS	229	#define FIFO_IOMEM_ID 0
	230	#define CTRL_IOMEM_ID 1
	231
914a3f3b HS	232	#define DBG_ERR 0x0001 /* report all error returns */
	233	#define DBG_HW 0x0002 /* debug hardware initialization */
	234	#define DBG_GADGET 0x0004 /* calls to/from gadget driver */
	235	#define DBG_INT 0x0008 /* interrupts */
	236	#define DBG_BUS 0x0010 /* report changes in bus state */
	237	#define DBG_QUEUE 0x0020 /* debug request queue processing */
	238	#define DBG_FIFO 0x0040 /* debug FIFO contents */
	239	#define DBG_DMA 0x0080 /* debug DMA handling */
	240	#define DBG_REQ 0x0100 /* print out queued request length */
	241	#define DBG_ALL 0xffff
	242	#define DBG_NONE 0x0000
	243
	244	#define DEBUG_LEVEL (DBG_ERR)
00274921	245
914a3f3b HS	246	#define DBG(level, fmt, ...) \
	247	do { \
	248	if ((level) & DEBUG_LEVEL) \
00274921	249	pr_debug("udc: " fmt, ## __VA_ARGS__); \
914a3f3b	250	} while (0)
914a3f3b HS	251
	252	enum usba_ctrl_state {
	253	WAIT_FOR_SETUP,
	254	DATA_STAGE_IN,
	255	DATA_STAGE_OUT,
	256	STATUS_STAGE_IN,
	257	STATUS_STAGE_OUT,
	258	STATUS_STAGE_ADDR,
	259	STATUS_STAGE_TEST,
	260	};
	261	/*
	262	EP_STATE_IDLE,
	263	EP_STATE_SETUP,
	264	EP_STATE_IN_DATA,
	265	EP_STATE_OUT_DATA,
	266	EP_STATE_SET_ADDR_STATUS,
	267	EP_STATE_RX_STATUS,
	268	EP_STATE_TX_STATUS,
	269	EP_STATE_HALT,
	270	*/
	271
	272	struct usba_dma_desc {
	273	dma_addr_t next;
	274	dma_addr_t addr;
	275	u32 ctrl;
	276	};
	277
741d2558 CB	278	struct usba_fifo_cfg {
	279	u8 hw_ep_num;
	280	u16 fifo_size;
	281	u8 nr_banks;
	282	};
	283
914a3f3b HS	284	struct usba_ep {
	285	int state;
	286	void __iomem *ep_regs;
	287	void __iomem *dma_regs;
	288	void __iomem *fifo;
	289	struct usb_ep ep;
	290	struct usba_udc *udc;
	291
	292	struct list_head queue;
914a3f3b HS	293
	294	u16 fifo_size;
	295	u8 nr_banks;
	296	u8 index;
	297	unsigned int can_dma:1;
	298	unsigned int can_isoc:1;
	299	unsigned int is_isoc:1;
	300	unsigned int is_in:1;
741d2558	301	unsigned long ept_cfg;
914a3f3b HS	302	#ifdef CONFIG_USB_GADGET_DEBUG_FS
	303	u32 last_dma_status;
	304	struct dentry *debugfs_dir;
	305	struct dentry *debugfs_queue;
	306	struct dentry *debugfs_dma_status;
	307	struct dentry *debugfs_state;
	308	#endif
	309	};
	310
	311	struct usba_request {
	312	struct usb_request req;
	313	struct list_head queue;
	314
	315	u32 ctrl;
	316
	317	unsigned int submitted:1;
	318	unsigned int last_transaction:1;
	319	unsigned int using_dma:1;
	320	unsigned int mapped:1;
	321	};
	322
3280e675 BB	323	struct usba_udc_errata {
3280e675 BB	324	void (toggle_bias)(struct usba_udc udc, int is_on);
258e2ddd	325	void (pulse_bias)(struct usba_udc udc);
3280e675 BB	326	};
3280e675 BB	327
914a3f3b HS	328	struct usba_udc {
	329	/* Protect hw registers from concurrent modifications */
	330	spinlock_t lock;
	331
a64ef71d SR	332	/* Mutex to prevent concurrent start or stop */
	333	struct mutex vbus_mutex;
	334
914a3f3b HS	335	void __iomem *regs;
	336	void __iomem *fifo;
	337
	338	struct usb_gadget gadget;
	339	struct usb_gadget_driver *driver;
	340	struct platform_device *pdev;
3280e675	341	const struct usba_udc_errata *errata;
914a3f3b HS	342	int irq;
914a3f3b HS	343	int vbus_pin;
640e95ab	344	int vbus_pin_inverted;
4a3ae932	345	int num_ep;
741d2558 CB	346	int configured_ep;
741d2558 CB	347	struct usba_fifo_cfg *fifo_cfg;
914a3f3b HS	348	struct clk *pclk;
914a3f3b HS	349	struct clk *hclk;
68522de7	350	struct usba_ep *usba_ep;
258e2ddd	351	bool bias_pulse_needed;
a64ef71d	352	bool clocked;
914a3f3b	353
58ed7b94 HS	354	u16 devstatus;
	355
	356	u16 test_mode;
914a3f3b HS	357	int vbus_prev;
914a3f3b HS	358
e3a912a1 BB	359	u32 int_enb_cache;
e3a912a1 BB	360
914a3f3b HS	361	#ifdef CONFIG_USB_GADGET_DEBUG_FS
	362	struct dentry *debugfs_root;
	363	struct dentry *debugfs_regs;
	364	#endif
4747639f AB	365
4747639f AB	366	struct regmap *pmc;
914a3f3b HS	367	};
	368
	369	static inline struct usba_ep to_usba_ep(struct usb_ep ep)
	370	{
	371	return container_of(ep, struct usba_ep, ep);
	372	}
	373
	374	static inline struct usba_request to_usba_req(struct usb_request req)
	375	{
	376	return container_of(req, struct usba_request, req);
	377	}
	378
	379	static inline struct usba_udc to_usba_udc(struct usb_gadget gadget)
	380	{
	381	return container_of(gadget, struct usba_udc, gadget);
	382	}
	383
	384	#define ep_is_control(ep) ((ep)->index == 0)
	385	#define ep_is_idle(ep) ((ep)->state == EP_STATE_IDLE)
	386
	387	#endif /* __LINUX_USB_GADGET_USBA_UDC_H */