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usb: gadget: udc: renesas_usb3: add support for usb role swap
[linux-2.6-block.git] / drivers / usb / gadget / udc / amd5536udc.c
CommitLineData
55d402d8
TD		 1/*
2 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
3 *
4 * Copyright (C) 2005-2007 AMD (http://www.amd.com)
5 * Author: Thomas Dahlmann
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
55d402d8
TD		 11 */
12
13/*
14 * The AMD5536 UDC is part of the x86 southbridge AMD Geode CS5536.
15 * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
16 * provides 4 IN and 4 OUT endpoints (bulk or interrupt type).
17 *
18 * Make sure that UDC is assigned to port 4 by BIOS settings (port can also
19 * be used as host port) and UOC bits PAD_EN and APU are set (should be done
20 * by BIOS init).
21 *
22 * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
23 * work without updating NET_IP_ALIGN. Or PIO mode (module param "use_dma=0")
24 * can be used with gadget ether.
25 */
26
27/* debug control */
28/* #define UDC_VERBOSE */
29
30/* Driver strings */
31#define UDC_MOD_DESCRIPTION "AMD 5536 UDC - USB Device Controller"
c15e03e1 32#define UDC_DRIVER_VERSION_STRING "01.00.0206"
55d402d8
TD		 33
34/* system */
35#include <linux/module.h>
36#include <linux/pci.h>
37#include <linux/kernel.h>
55d402d8
TD		 38#include <linux/delay.h>
39#include <linux/ioport.h>
40#include <linux/sched.h>
41#include <linux/slab.h>
55d402d8 42#include <linux/errno.h>
55d402d8
TD		 43#include <linux/timer.h>
44#include <linux/list.h>
45#include <linux/interrupt.h>
46#include <linux/ioctl.h>
47#include <linux/fs.h>
48#include <linux/dmapool.h>
49#include <linux/moduleparam.h>
50#include <linux/device.h>
51#include <linux/io.h>
52#include <linux/irq.h>
b38b03b3 53#include <linux/prefetch.h>
55d402d8
TD		 54
55#include <asm/byteorder.h>
55d402d8
TD		 56#include <asm/unaligned.h>
57
58/* gadget stack */
59#include <linux/usb/ch9.h>
9454a57a 60#include <linux/usb/gadget.h>
55d402d8
TD		 61
62/* udc specific */
63#include "amd5536udc.h"
64
65
66static void udc_tasklet_disconnect(unsigned long);
67static void empty_req_queue(struct udc_ep *);
55d402d8
TD		 68static void udc_setup_endpoints(struct udc *dev);
69static void udc_soft_reset(struct udc *dev);
70static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep);
71static void udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq);
55d402d8
TD		 72
73/* description */
74static const char mod_desc[] = UDC_MOD_DESCRIPTION;
75static const char name[] = "amd5536udc";
76
77/* structure to hold endpoint function pointers */
78static const struct usb_ep_ops udc_ep_ops;
79
80/* received setup data */
81static union udc_setup_data setup_data;
82
83/* pointer to device object */
84static struct udc *udc;
85
86/* irq spin lock for soft reset */
87static DEFINE_SPINLOCK(udc_irq_spinlock);
88/* stall spin lock */
89static DEFINE_SPINLOCK(udc_stall_spinlock);
90
91/*
92* slave mode: pending bytes in rx fifo after nyet,
93* used if EPIN irq came but no req was available
94*/
95static unsigned int udc_rxfifo_pending;
96
97/* count soft resets after suspend to avoid loop */
98static int soft_reset_occured;
99static int soft_reset_after_usbreset_occured;
100
101/* timer */
102static struct timer_list udc_timer;
103static int stop_timer;
104
105/* set_rde -- Is used to control enabling of RX DMA. Problem is
106 * that UDC has only one bit (RDE) to enable/disable RX DMA for
107 * all OUT endpoints. So we have to handle race conditions like
108 * when OUT data reaches the fifo but no request was queued yet.
109 * This cannot be solved by letting the RX DMA disabled until a
110 * request gets queued because there may be other OUT packets
111 * in the FIFO (important for not blocking control traffic).
112 * The value of set_rde controls the correspondig timer.
113 *
114 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
115 * set_rde 0 == do not touch RDE, do no start the RDE timer
116 * set_rde 1 == timer function will look whether FIFO has data
117 * set_rde 2 == set by timer function to enable RX DMA on next call
118 */
119static int set_rde = -1;
120
121static DECLARE_COMPLETION(on_exit);
122static struct timer_list udc_pollstall_timer;
123static int stop_pollstall_timer;
124static DECLARE_COMPLETION(on_pollstall_exit);
125
126/* tasklet for usb disconnect */
127static DECLARE_TASKLET(disconnect_tasklet, udc_tasklet_disconnect,
128 (unsigned long) &udc);
129
130
131/* endpoint names used for print */
132static const char ep0_string[] = "ep0in";
6f02ac5a
RB		 133static const struct {
134 const char *name;
135 const struct usb_ep_caps caps;
136} ep_info[] = {
137#define EP_INFO(_name, _caps) \
138 { \
139 .name = _name, \
140 .caps = _caps, \
141 }
142
143 EP_INFO(ep0_string,
144 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_IN)),
145 EP_INFO("ep1in-int",
146 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
147 EP_INFO("ep2in-bulk",
148 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
149 EP_INFO("ep3in-bulk",
150 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
151 EP_INFO("ep4in-bulk",
152 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
153 EP_INFO("ep5in-bulk",
154 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
155 EP_INFO("ep6in-bulk",
156 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
157 EP_INFO("ep7in-bulk",
158 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
159 EP_INFO("ep8in-bulk",
160 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
161 EP_INFO("ep9in-bulk",
162 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
163 EP_INFO("ep10in-bulk",
164 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
165 EP_INFO("ep11in-bulk",
166 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
167 EP_INFO("ep12in-bulk",
168 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
169 EP_INFO("ep13in-bulk",
170 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
171 EP_INFO("ep14in-bulk",
172 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
173 EP_INFO("ep15in-bulk",
174 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
175 EP_INFO("ep0out",
176 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_OUT)),
177 EP_INFO("ep1out-bulk",
178 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
179 EP_INFO("ep2out-bulk",
180 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
181 EP_INFO("ep3out-bulk",
182 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
183 EP_INFO("ep4out-bulk",
184 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
185 EP_INFO("ep5out-bulk",
186 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
187 EP_INFO("ep6out-bulk",
188 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
189 EP_INFO("ep7out-bulk",
190 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
191 EP_INFO("ep8out-bulk",
192 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
193 EP_INFO("ep9out-bulk",
194 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
195 EP_INFO("ep10out-bulk",
196 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
197 EP_INFO("ep11out-bulk",
198 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
199 EP_INFO("ep12out-bulk",
200 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
201 EP_INFO("ep13out-bulk",
202 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
203 EP_INFO("ep14out-bulk",
204 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
205 EP_INFO("ep15out-bulk",
206 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
207
208#undef EP_INFO
55d402d8
TD		 209};
210
211/* DMA usage flag */
90ab5ee9 212static bool use_dma = 1;
55d402d8 213/* packet per buffer dma */
90ab5ee9 214static bool use_dma_ppb = 1;
55d402d8 215/* with per descr. update */
90ab5ee9 216static bool use_dma_ppb_du;
55d402d8
TD		 217/* buffer fill mode */
218static int use_dma_bufferfill_mode;
219/* full speed only mode */
90ab5ee9 220static bool use_fullspeed;
55d402d8
TD		 221/* tx buffer size for high speed */
222static unsigned long hs_tx_buf = UDC_EPIN_BUFF_SIZE;
223
224/* module parameters */
225module_param(use_dma, bool, S_IRUGO);
226MODULE_PARM_DESC(use_dma, "true for DMA");
227module_param(use_dma_ppb, bool, S_IRUGO);
228MODULE_PARM_DESC(use_dma_ppb, "true for DMA in packet per buffer mode");
229module_param(use_dma_ppb_du, bool, S_IRUGO);
230MODULE_PARM_DESC(use_dma_ppb_du,
231 "true for DMA in packet per buffer mode with descriptor update");
232module_param(use_fullspeed, bool, S_IRUGO);
233MODULE_PARM_DESC(use_fullspeed, "true for fullspeed only");
234
235/*---------------------------------------------------------------------------*/
236/* Prints UDC device registers and endpoint irq registers */
237static void print_regs(struct udc *dev)
238{
239 DBG(dev, "------- Device registers -------\n");
240 DBG(dev, "dev config = %08x\n", readl(&dev->regs->cfg));
241 DBG(dev, "dev control = %08x\n", readl(&dev->regs->ctl));
242 DBG(dev, "dev status = %08x\n", readl(&dev->regs->sts));
243 DBG(dev, "\n");
244 DBG(dev, "dev int's = %08x\n", readl(&dev->regs->irqsts));
245 DBG(dev, "dev intmask = %08x\n", readl(&dev->regs->irqmsk));
246 DBG(dev, "\n");
247 DBG(dev, "dev ep int's = %08x\n", readl(&dev->regs->ep_irqsts));
248 DBG(dev, "dev ep intmask = %08x\n", readl(&dev->regs->ep_irqmsk));
249 DBG(dev, "\n");
250 DBG(dev, "USE DMA = %d\n", use_dma);
251 if (use_dma && use_dma_ppb && !use_dma_ppb_du) {
252 DBG(dev, "DMA mode = PPBNDU (packet per buffer "
253 "WITHOUT desc. update)\n");
254 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBNDU");
0cf7a633 255 } else if (use_dma && use_dma_ppb && use_dma_ppb_du) {
55d402d8
TD		 256 DBG(dev, "DMA mode = PPBDU (packet per buffer "
257 "WITH desc. update)\n");
258 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBDU");
259 }
260 if (use_dma && use_dma_bufferfill_mode) {
261 DBG(dev, "DMA mode = BF (buffer fill mode)\n");
262 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "BF");
263 }
170b778f 264 if (!use_dma)
55d402d8 265 dev_info(&dev->pdev->dev, "FIFO mode\n");
55d402d8
TD		 266 DBG(dev, "-------------------------------------------------------\n");
267}
268
269/* Masks unused interrupts */
270static int udc_mask_unused_interrupts(struct udc *dev)
271{
272 u32 tmp;
273
274 /* mask all dev interrupts */
275 tmp = AMD_BIT(UDC_DEVINT_SVC) |
276 AMD_BIT(UDC_DEVINT_ENUM) |
277 AMD_BIT(UDC_DEVINT_US) |
278 AMD_BIT(UDC_DEVINT_UR) |
279 AMD_BIT(UDC_DEVINT_ES) |
280 AMD_BIT(UDC_DEVINT_SI) |
281 AMD_BIT(UDC_DEVINT_SOF)|
282 AMD_BIT(UDC_DEVINT_SC);
283 writel(tmp, &dev->regs->irqmsk);
284
285 /* mask all ep interrupts */
286 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk);
287
288 return 0;
289}
290
291/* Enables endpoint 0 interrupts */
292static int udc_enable_ep0_interrupts(struct udc *dev)
293{
294 u32 tmp;
295
296 DBG(dev, "udc_enable_ep0_interrupts()\n");
297
298 /* read irq mask */
299 tmp = readl(&dev->regs->ep_irqmsk);
300 /* enable ep0 irq's */
301 tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0)
302 & AMD_UNMASK_BIT(UDC_EPINT_OUT_EP0);
303 writel(tmp, &dev->regs->ep_irqmsk);
304
305 return 0;
306}
307
308/* Enables device interrupts for SET_INTF and SET_CONFIG */
309static int udc_enable_dev_setup_interrupts(struct udc *dev)
310{
311 u32 tmp;
312
313 DBG(dev, "enable device interrupts for setup data\n");
314
315 /* read irq mask */
316 tmp = readl(&dev->regs->irqmsk);
317
318 /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
319 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI)
320 & AMD_UNMASK_BIT(UDC_DEVINT_SC)
321 & AMD_UNMASK_BIT(UDC_DEVINT_UR)
322 & AMD_UNMASK_BIT(UDC_DEVINT_SVC)
323 & AMD_UNMASK_BIT(UDC_DEVINT_ENUM);
324 writel(tmp, &dev->regs->irqmsk);
325
326 return 0;
327}
328
25985edc 329/* Calculates fifo start of endpoint based on preceding endpoints */
55d402d8
TD		 330static int udc_set_txfifo_addr(struct udc_ep *ep)
331{
332 struct udc *dev;
333 u32 tmp;
334 int i;
335
336 if (!ep || !(ep->in))
337 return -EINVAL;
338
339 dev = ep->dev;
340 ep->txfifo = dev->txfifo;
341
342 /* traverse ep's */
343 for (i = 0; i < ep->num; i++) {
344 if (dev->ep[i].regs) {
345 /* read fifo size */
346 tmp = readl(&dev->ep[i].regs->bufin_framenum);
347 tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE);
348 ep->txfifo += tmp;
349 }
350 }
351 return 0;
352}
353
354/* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
355static u32 cnak_pending;
356
357static void UDC_QUEUE_CNAK(struct udc_ep *ep, unsigned num)
358{
359 if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) {
360 DBG(ep->dev, "NAK could not be cleared for ep%d\n", num);
361 cnak_pending |= 1 << (num);
362 ep->naking = 1;
363 } else
364 cnak_pending = cnak_pending & (~(1 << (num)));
365}
366
367
368/* Enables endpoint, is called by gadget driver */
369static int
370udc_ep_enable(struct usb_ep *usbep, const struct usb_endpoint_descriptor *desc)
371{
372 struct udc_ep *ep;
373 struct udc *dev;
374 u32 tmp;
375 unsigned long iflags;
376 u8 udc_csr_epix;
fd05e720 377 unsigned maxpacket;
55d402d8
TD		 378
379 if (!usbep
380 || usbep->name == ep0_string
381 || !desc
382 || desc->bDescriptorType != USB_DT_ENDPOINT)
383 return -EINVAL;
384
385 ep = container_of(usbep, struct udc_ep, ep);
386 dev = ep->dev;
387
388 DBG(dev, "udc_ep_enable() ep %d\n", ep->num);
389
390 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
391 return -ESHUTDOWN;
392
393 spin_lock_irqsave(&dev->lock, iflags);
ef20a72b 394 ep->ep.desc = desc;
55d402d8
TD		 395
396 ep->halted = 0;
397
398 /* set traffic type */
399 tmp = readl(&dev->ep[ep->num].regs->ctl);
400 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET);
401 writel(tmp, &dev->ep[ep->num].regs->ctl);
402
403 /* set max packet size */
29cc8897 404 maxpacket = usb_endpoint_maxp(desc);
55d402d8 405 tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt);
fd05e720
AV		 406 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE);
407 ep->ep.maxpacket = maxpacket;
55d402d8
TD		 408 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt);
409
410 /* IN ep */
411 if (ep->in) {
412
413 /* ep ix in UDC CSR register space */
414 udc_csr_epix = ep->num;
415
416 /* set buffer size (tx fifo entries) */
417 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum);
418 /* double buffering: fifo size = 2 x max packet size */
419 tmp = AMD_ADDBITS(
420 tmp,
fd05e720
AV		 421 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
422 / UDC_DWORD_BYTES,
55d402d8
TD		 423 UDC_EPIN_BUFF_SIZE);
424 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum);
425
426 /* calc. tx fifo base addr */
427 udc_set_txfifo_addr(ep);
428
429 /* flush fifo */
430 tmp = readl(&ep->regs->ctl);
431 tmp |= AMD_BIT(UDC_EPCTL_F);
432 writel(tmp, &ep->regs->ctl);
433
434 /* OUT ep */
435 } else {
436 /* ep ix in UDC CSR register space */
437 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
438
439 /* set max packet size UDC CSR */
440 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
fd05e720 441 tmp = AMD_ADDBITS(tmp, maxpacket,
55d402d8
TD		 442 UDC_CSR_NE_MAX_PKT);
443 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
444
445 if (use_dma && !ep->in) {
446 /* alloc and init BNA dummy request */
447 ep->bna_dummy_req = udc_alloc_bna_dummy(ep);
448 ep->bna_occurred = 0;
449 }
450
451 if (ep->num != UDC_EP0OUT_IX)
452 dev->data_ep_enabled = 1;
453 }
454
455 /* set ep values */
456 tmp = readl(&dev->csr->ne[udc_csr_epix]);
457 /* max packet */
fd05e720 458 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT);
55d402d8
TD		 459 /* ep number */
460 tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM);
461 /* ep direction */
462 tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR);
463 /* ep type */
464 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE);
465 /* ep config */
466 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG);
467 /* ep interface */
468 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF);
469 /* ep alt */
470 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT);
471 /* write reg */
472 writel(tmp, &dev->csr->ne[udc_csr_epix]);
473
474 /* enable ep irq */
475 tmp = readl(&dev->regs->ep_irqmsk);
476 tmp &= AMD_UNMASK_BIT(ep->num);
477 writel(tmp, &dev->regs->ep_irqmsk);
478
479 /*
480 * clear NAK by writing CNAK
481 * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
482 */
483 if (!use_dma || ep->in) {
484 tmp = readl(&ep->regs->ctl);
485 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
486 writel(tmp, &ep->regs->ctl);
487 ep->naking = 0;
488 UDC_QUEUE_CNAK(ep, ep->num);
489 }
490 tmp = desc->bEndpointAddress;
491 DBG(dev, "%s enabled\n", usbep->name);
492
493 spin_unlock_irqrestore(&dev->lock, iflags);
494 return 0;
495}
496
497/* Resets endpoint */
498static void ep_init(struct udc_regs __iomem *regs, struct udc_ep *ep)
499{
500 u32 tmp;
501
502 VDBG(ep->dev, "ep-%d reset\n", ep->num);
f9c56cdd 503 ep->ep.desc = NULL;
55d402d8
TD		 504 ep->ep.ops = &udc_ep_ops;
505 INIT_LIST_HEAD(&ep->queue);
506
e117e742 507 usb_ep_set_maxpacket_limit(&ep->ep,(u16) ~0);
55d402d8
TD		 508 /* set NAK */
509 tmp = readl(&ep->regs->ctl);
510 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
511 writel(tmp, &ep->regs->ctl);
512 ep->naking = 1;
513
514 /* disable interrupt */
515 tmp = readl(&regs->ep_irqmsk);
516 tmp |= AMD_BIT(ep->num);
517 writel(tmp, &regs->ep_irqmsk);
518
519 if (ep->in) {
520 /* unset P and IN bit of potential former DMA */
521 tmp = readl(&ep->regs->ctl);
522 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P);
523 writel(tmp, &ep->regs->ctl);
524
525 tmp = readl(&ep->regs->sts);
526 tmp |= AMD_BIT(UDC_EPSTS_IN);
527 writel(tmp, &ep->regs->sts);
528
529 /* flush the fifo */
530 tmp = readl(&ep->regs->ctl);
531 tmp |= AMD_BIT(UDC_EPCTL_F);
532 writel(tmp, &ep->regs->ctl);
533
534 }
535 /* reset desc pointer */
536 writel(0, &ep->regs->desptr);
537}
538
539/* Disables endpoint, is called by gadget driver */
540static int udc_ep_disable(struct usb_ep *usbep)
541{
542 struct udc_ep *ep = NULL;
543 unsigned long iflags;
544
545 if (!usbep)
546 return -EINVAL;
547
548 ep = container_of(usbep, struct udc_ep, ep);
ef20a72b 549 if (usbep->name == ep0_string || !ep->ep.desc)
55d402d8
TD		 550 return -EINVAL;
551
552 DBG(ep->dev, "Disable ep-%d\n", ep->num);
553
554 spin_lock_irqsave(&ep->dev->lock, iflags);
555 udc_free_request(&ep->ep, &ep->bna_dummy_req->req);
556 empty_req_queue(ep);
557 ep_init(ep->dev->regs, ep);
558 spin_unlock_irqrestore(&ep->dev->lock, iflags);
559
560 return 0;
561}
562
563/* Allocates request packet, called by gadget driver */
564static struct usb_request *
565udc_alloc_request(struct usb_ep *usbep, gfp_t gfp)
566{
567 struct udc_request *req;
568 struct udc_data_dma *dma_desc;
569 struct udc_ep *ep;
570
571 if (!usbep)
572 return NULL;
573
574 ep = container_of(usbep, struct udc_ep, ep);
575
576 VDBG(ep->dev, "udc_alloc_req(): ep%d\n", ep->num);
577 req = kzalloc(sizeof(struct udc_request), gfp);
578 if (!req)
579 return NULL;
580
581 req->req.dma = DMA_DONT_USE;
582 INIT_LIST_HEAD(&req->queue);
583
584 if (ep->dma) {
585 /* ep0 in requests are allocated from data pool here */
586 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
587 &req->td_phys);
588 if (!dma_desc) {
589 kfree(req);
590 return NULL;
591 }
592
593 VDBG(ep->dev, "udc_alloc_req: req = %p dma_desc = %p, "
594 "td_phys = %lx\n",
595 req, dma_desc,
596 (unsigned long)req->td_phys);
597 /* prevent from using desc. - set HOST BUSY */
598 dma_desc->status = AMD_ADDBITS(dma_desc->status,
599 UDC_DMA_STP_STS_BS_HOST_BUSY,
600 UDC_DMA_STP_STS_BS);
551509d2 601 dma_desc->bufptr = cpu_to_le32(DMA_DONT_USE);
55d402d8
TD		 602 req->td_data = dma_desc;
603 req->td_data_last = NULL;
604 req->chain_len = 1;
605 }
606
607 return &req->req;
608}
609
3719b9bd 610/* frees pci pool descriptors of a DMA chain */
f87599a0 611static void udc_free_dma_chain(struct udc *dev, struct udc_request *req)
3719b9bd 612{
71ef322d 613 struct udc_data_dma *td = req->td_data;
3719b9bd
SM		 614 unsigned int i;
615
71ef322d
GS		 616 dma_addr_t addr_next = 0x00;
617 dma_addr_t addr = (dma_addr_t)td->next;
618
3719b9bd
SM		 619 DBG(dev, "free chain req = %p\n", req);
620
621 /* do not free first desc., will be done by free for request */
3719b9bd 622 for (i = 1; i < req->chain_len; i++) {
71ef322d
GS		 623 td = phys_to_virt(addr);
624 addr_next = (dma_addr_t)td->next;
625 pci_pool_free(dev->data_requests, td, addr);
626 addr = addr_next;
3719b9bd 627 }
3719b9bd
SM		 628}
629
55d402d8
TD		 630/* Frees request packet, called by gadget driver */
631static void
632udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq)
633{
634 struct udc_ep *ep;
635 struct udc_request *req;
636
637 if (!usbep || !usbreq)
638 return;
639
640 ep = container_of(usbep, struct udc_ep, ep);
641 req = container_of(usbreq, struct udc_request, req);
642 VDBG(ep->dev, "free_req req=%p\n", req);
643 BUG_ON(!list_empty(&req->queue));
644 if (req->td_data) {
645 VDBG(ep->dev, "req->td_data=%p\n", req->td_data);
646
647 /* free dma chain if created */
170b778f 648 if (req->chain_len > 1)
55d402d8 649 udc_free_dma_chain(ep->dev, req);
55d402d8
TD		 650
651 pci_pool_free(ep->dev->data_requests, req->td_data,
652 req->td_phys);
653 }
654 kfree(req);
655}
656
657/* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
658static void udc_init_bna_dummy(struct udc_request *req)
659{
660 if (req) {
661 /* set last bit */
662 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
663 /* set next pointer to itself */
664 req->td_data->next = req->td_phys;
665 /* set HOST BUSY */
666 req->td_data->status
667 = AMD_ADDBITS(req->td_data->status,
668 UDC_DMA_STP_STS_BS_DMA_DONE,
669 UDC_DMA_STP_STS_BS);
670#ifdef UDC_VERBOSE
671 pr_debug("bna desc = %p, sts = %08x\n",
672 req->td_data, req->td_data->status);
673#endif
674 }
675}
676
677/* Allocate BNA dummy descriptor */
678static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep)
679{
680 struct udc_request *req = NULL;
681 struct usb_request *_req = NULL;
682
683 /* alloc the dummy request */
684 _req = udc_alloc_request(&ep->ep, GFP_ATOMIC);
685 if (_req) {
686 req = container_of(_req, struct udc_request, req);
687 ep->bna_dummy_req = req;
688 udc_init_bna_dummy(req);
689 }
690 return req;
691}
692
693/* Write data to TX fifo for IN packets */
694static void
695udc_txfifo_write(struct udc_ep *ep, struct usb_request *req)
696{
697 u8 *req_buf;
698 u32 *buf;
699 int i, j;
700 unsigned bytes = 0;
701 unsigned remaining = 0;
702
703 if (!req || !ep)
704 return;
705
706 req_buf = req->buf + req->actual;
707 prefetch(req_buf);
708 remaining = req->length - req->actual;
709
710 buf = (u32 *) req_buf;
711
712 bytes = ep->ep.maxpacket;
713 if (bytes > remaining)
714 bytes = remaining;
715
716 /* dwords first */
170b778f 717 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
55d402d8 718 writel(*(buf + i), ep->txfifo);
55d402d8
TD		 719
720 /* remaining bytes must be written by byte access */
721 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
722 writeb((u8)(*(buf + i) >> (j << UDC_BITS_PER_BYTE_SHIFT)),
723 ep->txfifo);
724 }
725
726 /* dummy write confirm */
727 writel(0, &ep->regs->confirm);
728}
729
730/* Read dwords from RX fifo for OUT transfers */
731static int udc_rxfifo_read_dwords(struct udc *dev, u32 *buf, int dwords)
732{
733 int i;
734
735 VDBG(dev, "udc_read_dwords(): %d dwords\n", dwords);
736
170b778f 737 for (i = 0; i < dwords; i++)
55d402d8 738 *(buf + i) = readl(dev->rxfifo);
55d402d8
TD		 739 return 0;
740}
741
742/* Read bytes from RX fifo for OUT transfers */
743static int udc_rxfifo_read_bytes(struct udc *dev, u8 *buf, int bytes)
744{
745 int i, j;
746 u32 tmp;
747
748 VDBG(dev, "udc_read_bytes(): %d bytes\n", bytes);
749
750 /* dwords first */
170b778f 751 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
55d402d8 752 *((u32 *)(buf + (i<<2))) = readl(dev->rxfifo);
55d402d8
TD		 753
754 /* remaining bytes must be read by byte access */
755 if (bytes % UDC_DWORD_BYTES) {
756 tmp = readl(dev->rxfifo);
757 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
758 *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK);
759 tmp = tmp >> UDC_BITS_PER_BYTE;
760 }
761 }
762
763 return 0;
764}
765
766/* Read data from RX fifo for OUT transfers */
767static int
768udc_rxfifo_read(struct udc_ep *ep, struct udc_request *req)
769{
770 u8 *buf;
771 unsigned buf_space;
772 unsigned bytes = 0;
773 unsigned finished = 0;
774
775 /* received number bytes */
776 bytes = readl(&ep->regs->sts);
777 bytes = AMD_GETBITS(bytes, UDC_EPSTS_RX_PKT_SIZE);
778
779 buf_space = req->req.length - req->req.actual;
780 buf = req->req.buf + req->req.actual;
781 if (bytes > buf_space) {
782 if ((buf_space % ep->ep.maxpacket) != 0) {
783 DBG(ep->dev,
784 "%s: rx %d bytes, rx-buf space = %d bytesn\n",
785 ep->ep.name, bytes, buf_space);
786 req->req.status = -EOVERFLOW;
787 }
788 bytes = buf_space;
789 }
790 req->req.actual += bytes;
791
792 /* last packet ? */
793 if (((bytes % ep->ep.maxpacket) != 0) || (!bytes)
794 || ((req->req.actual == req->req.length) && !req->req.zero))
795 finished = 1;
796
797 /* read rx fifo bytes */
798 VDBG(ep->dev, "ep %s: rxfifo read %d bytes\n", ep->ep.name, bytes);
799 udc_rxfifo_read_bytes(ep->dev, buf, bytes);
800
801 return finished;
802}
803
c9760ad8
SM		 804/* Creates or re-inits a DMA chain */
805static int udc_create_dma_chain(
806 struct udc_ep *ep,
807 struct udc_request *req,
808 unsigned long buf_len, gfp_t gfp_flags
809)
810{
811 unsigned long bytes = req->req.length;
812 unsigned int i;
813 dma_addr_t dma_addr;
814 struct udc_data_dma *td = NULL;
815 struct udc_data_dma *last = NULL;
816 unsigned long txbytes;
817 unsigned create_new_chain = 0;
818 unsigned len;
819
820 VDBG(ep->dev, "udc_create_dma_chain: bytes=%ld buf_len=%ld\n",
821 bytes, buf_len);
822 dma_addr = DMA_DONT_USE;
823
824 /* unset L bit in first desc for OUT */
825 if (!ep->in)
826 req->td_data->status &= AMD_CLEAR_BIT(UDC_DMA_IN_STS_L);
827
828 /* alloc only new desc's if not already available */
829 len = req->req.length / ep->ep.maxpacket;
830 if (req->req.length % ep->ep.maxpacket)
831 len++;
832
833 if (len > req->chain_len) {
834 /* shorter chain already allocated before */
835 if (req->chain_len > 1)
836 udc_free_dma_chain(ep->dev, req);
837 req->chain_len = len;
838 create_new_chain = 1;
839 }
840
841 td = req->td_data;
842 /* gen. required number of descriptors and buffers */
843 for (i = buf_len; i < bytes; i += buf_len) {
844 /* create or determine next desc. */
845 if (create_new_chain) {
846 td = pci_pool_alloc(ep->dev->data_requests,
847 gfp_flags, &dma_addr);
848 if (!td)
849 return -ENOMEM;
850
851 td->status = 0;
852 } else if (i == buf_len) {
853 /* first td */
854 td = (struct udc_data_dma *)phys_to_virt(
855 req->td_data->next);
856 td->status = 0;
857 } else {
858 td = (struct udc_data_dma *)phys_to_virt(last->next);
859 td->status = 0;
860 }
861
862 if (td)
863 td->bufptr = req->req.dma + i; /* assign buffer */
864 else
865 break;
866
867 /* short packet ? */
868 if ((bytes - i) >= buf_len) {
869 txbytes = buf_len;
870 } else {
871 /* short packet */
872 txbytes = bytes - i;
873 }
874
875 /* link td and assign tx bytes */
876 if (i == buf_len) {
877 if (create_new_chain)
878 req->td_data->next = dma_addr;
879 /*
880 * else
881 * req->td_data->next = virt_to_phys(td);
882 */
883 /* write tx bytes */
884 if (ep->in) {
885 /* first desc */
886 req->td_data->status =
887 AMD_ADDBITS(req->td_data->status,
888 ep->ep.maxpacket,
889 UDC_DMA_IN_STS_TXBYTES);
890 /* second desc */
891 td->status = AMD_ADDBITS(td->status,
892 txbytes,
893 UDC_DMA_IN_STS_TXBYTES);
894 }
895 } else {
896 if (create_new_chain)
897 last->next = dma_addr;
898 /*
899 * else
900 * last->next = virt_to_phys(td);
901 */
902 if (ep->in) {
903 /* write tx bytes */
904 td->status = AMD_ADDBITS(td->status,
905 txbytes,
906 UDC_DMA_IN_STS_TXBYTES);
907 }
908 }
909 last = td;
910 }
911 /* set last bit */
912 if (td) {
913 td->status |= AMD_BIT(UDC_DMA_IN_STS_L);
914 /* last desc. points to itself */
915 req->td_data_last = td;
916 }
917
918 return 0;
919}
920
55d402d8
TD		 921/* create/re-init a DMA descriptor or a DMA descriptor chain */
922static int prep_dma(struct udc_ep *ep, struct udc_request *req, gfp_t gfp)
923{
924 int retval = 0;
925 u32 tmp;
926
927 VDBG(ep->dev, "prep_dma\n");
928 VDBG(ep->dev, "prep_dma ep%d req->td_data=%p\n",
929 ep->num, req->td_data);
930
931 /* set buffer pointer */
932 req->td_data->bufptr = req->req.dma;
933
934 /* set last bit */
935 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
936
937 /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
938 if (use_dma_ppb) {
939
940 retval = udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
941 if (retval != 0) {
942 if (retval == -ENOMEM)
943 DBG(ep->dev, "Out of DMA memory\n");
944 return retval;
945 }
946 if (ep->in) {
947 if (req->req.length == ep->ep.maxpacket) {
948 /* write tx bytes */
949 req->td_data->status =
950 AMD_ADDBITS(req->td_data->status,
951 ep->ep.maxpacket,
952 UDC_DMA_IN_STS_TXBYTES);
953
954 }
955 }
956
957 }
958
959 if (ep->in) {
960 VDBG(ep->dev, "IN: use_dma_ppb=%d req->req.len=%d "
961 "maxpacket=%d ep%d\n",
962 use_dma_ppb, req->req.length,
963 ep->ep.maxpacket, ep->num);
964 /*
965 * if bytes < max packet then tx bytes must
966 * be written in packet per buffer mode
967 */
968 if (!use_dma_ppb || req->req.length < ep->ep.maxpacket
969 || ep->num == UDC_EP0OUT_IX
970 || ep->num == UDC_EP0IN_IX) {
971 /* write tx bytes */
972 req->td_data->status =
973 AMD_ADDBITS(req->td_data->status,
974 req->req.length,
975 UDC_DMA_IN_STS_TXBYTES);
976 /* reset frame num */
977 req->td_data->status =
978 AMD_ADDBITS(req->td_data->status,
979 0,
980 UDC_DMA_IN_STS_FRAMENUM);
981 }
982 /* set HOST BUSY */
983 req->td_data->status =
984 AMD_ADDBITS(req->td_data->status,
985 UDC_DMA_STP_STS_BS_HOST_BUSY,
986 UDC_DMA_STP_STS_BS);
987 } else {
988 VDBG(ep->dev, "OUT set host ready\n");
989 /* set HOST READY */
990 req->td_data->status =
991 AMD_ADDBITS(req->td_data->status,
992 UDC_DMA_STP_STS_BS_HOST_READY,
993 UDC_DMA_STP_STS_BS);
994
995
996 /* clear NAK by writing CNAK */
997 if (ep->naking) {
998 tmp = readl(&ep->regs->ctl);
999 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1000 writel(tmp, &ep->regs->ctl);
1001 ep->naking = 0;
1002 UDC_QUEUE_CNAK(ep, ep->num);
1003 }
1004
1005 }
1006
1007 return retval;
1008}
1009
1010/* Completes request packet ... caller MUST hold lock */
1011static void
1012complete_req(struct udc_ep *ep, struct udc_request *req, int sts)
1013__releases(ep->dev->lock)
1014__acquires(ep->dev->lock)
1015{
1016 struct udc *dev;
1017 unsigned halted;
1018
1019 VDBG(ep->dev, "complete_req(): ep%d\n", ep->num);
1020
1021 dev = ep->dev;
1022 /* unmap DMA */
220e8600
FB		 1023 if (ep->dma)
1024 usb_gadget_unmap_request(&dev->gadget, &req->req, ep->in);
55d402d8
TD		 1025
1026 halted = ep->halted;
1027 ep->halted = 1;
1028
1029 /* set new status if pending */
1030 if (req->req.status == -EINPROGRESS)
1031 req->req.status = sts;
1032
1033 /* remove from ep queue */
1034 list_del_init(&req->queue);
1035
1036 VDBG(ep->dev, "req %p => complete %d bytes at %s with sts %d\n",
1037 &req->req, req->req.length, ep->ep.name, sts);
1038
1039 spin_unlock(&dev->lock);
304f7e5e 1040 usb_gadget_giveback_request(&ep->ep, &req->req);
55d402d8
TD		 1041 spin_lock(&dev->lock);
1042 ep->halted = halted;
1043}
1044
55d402d8
TD		 1045/* Iterates to the end of a DMA chain and returns last descriptor */
1046static struct udc_data_dma *udc_get_last_dma_desc(struct udc_request *req)
1047{
1048 struct udc_data_dma *td;
1049
1050 td = req->td_data;
170b778f 1051 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L)))
55d402d8 1052 td = phys_to_virt(td->next);
55d402d8
TD		 1053
1054 return td;
1055
1056}
1057
1058/* Iterates to the end of a DMA chain and counts bytes received */
1059static u32 udc_get_ppbdu_rxbytes(struct udc_request *req)
1060{
1061 struct udc_data_dma *td;
1062 u32 count;
1063
1064 td = req->td_data;
1065 /* received number bytes */
1066 count = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES);
1067
1068 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
1069 td = phys_to_virt(td->next);
1070 /* received number bytes */
1071 if (td) {
1072 count += AMD_GETBITS(td->status,
1073 UDC_DMA_OUT_STS_RXBYTES);
1074 }
1075 }
1076
1077 return count;
1078
1079}
1080
55d402d8
TD		 1081/* Enabling RX DMA */
1082static void udc_set_rde(struct udc *dev)
1083{
1084 u32 tmp;
1085
1086 VDBG(dev, "udc_set_rde()\n");
1087 /* stop RDE timer */
1088 if (timer_pending(&udc_timer)) {
1089 set_rde = 0;
1090 mod_timer(&udc_timer, jiffies - 1);
1091 }
1092 /* set RDE */
1093 tmp = readl(&dev->regs->ctl);
1094 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1095 writel(tmp, &dev->regs->ctl);
1096}
1097
1098/* Queues a request packet, called by gadget driver */
1099static int
1100udc_queue(struct usb_ep *usbep, struct usb_request *usbreq, gfp_t gfp)
1101{
1102 int retval = 0;
1103 u8 open_rxfifo = 0;
1104 unsigned long iflags;
1105 struct udc_ep *ep;
1106 struct udc_request *req;
1107 struct udc *dev;
1108 u32 tmp;
1109
1110 /* check the inputs */
1111 req = container_of(usbreq, struct udc_request, req);
1112
1113 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf
1114 || !list_empty(&req->queue))
1115 return -EINVAL;
1116
1117 ep = container_of(usbep, struct udc_ep, ep);
ef20a72b 1118 if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
55d402d8
TD		 1119 return -EINVAL;
1120
1121 VDBG(ep->dev, "udc_queue(): ep%d-in=%d\n", ep->num, ep->in);
1122 dev = ep->dev;
1123
1124 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1125 return -ESHUTDOWN;
1126
1127 /* map dma (usually done before) */
220e8600 1128 if (ep->dma) {
55d402d8 1129 VDBG(dev, "DMA map req %p\n", req);
220e8600
FB		 1130 retval = usb_gadget_map_request(&udc->gadget, usbreq, ep->in);
1131 if (retval)
1132 return retval;
55d402d8
TD		 1133 }
1134
1135 VDBG(dev, "%s queue req %p, len %d req->td_data=%p buf %p\n",
1136 usbep->name, usbreq, usbreq->length,
1137 req->td_data, usbreq->buf);
1138
1139 spin_lock_irqsave(&dev->lock, iflags);
1140 usbreq->actual = 0;
1141 usbreq->status = -EINPROGRESS;
1142 req->dma_done = 0;
1143
1144 /* on empty queue just do first transfer */
1145 if (list_empty(&ep->queue)) {
1146 /* zlp */
1147 if (usbreq->length == 0) {
1148 /* IN zlp's are handled by hardware */
1149 complete_req(ep, req, 0);
1150 VDBG(dev, "%s: zlp\n", ep->ep.name);
1151 /*
1152 * if set_config or set_intf is waiting for ack by zlp
1153 * then set CSR_DONE
1154 */
1155 if (dev->set_cfg_not_acked) {
1156 tmp = readl(&dev->regs->ctl);
1157 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE);
1158 writel(tmp, &dev->regs->ctl);
1159 dev->set_cfg_not_acked = 0;
1160 }
1161 /* setup command is ACK'ed now by zlp */
1162 if (dev->waiting_zlp_ack_ep0in) {
1163 /* clear NAK by writing CNAK in EP0_IN */
1164 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1165 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1166 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1167 dev->ep[UDC_EP0IN_IX].naking = 0;
1168 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX],
1169 UDC_EP0IN_IX);
1170 dev->waiting_zlp_ack_ep0in = 0;
1171 }
1172 goto finished;
1173 }
1174 if (ep->dma) {
ffcba5a5 1175 retval = prep_dma(ep, req, GFP_ATOMIC);
55d402d8
TD		 1176 if (retval != 0)
1177 goto finished;
1178 /* write desc pointer to enable DMA */
1179 if (ep->in) {
1180 /* set HOST READY */
1181 req->td_data->status =
1182 AMD_ADDBITS(req->td_data->status,
1183 UDC_DMA_IN_STS_BS_HOST_READY,
1184 UDC_DMA_IN_STS_BS);
1185 }
1186
1187 /* disabled rx dma while descriptor update */
1188 if (!ep->in) {
1189 /* stop RDE timer */
1190 if (timer_pending(&udc_timer)) {
1191 set_rde = 0;
1192 mod_timer(&udc_timer, jiffies - 1);
1193 }
1194 /* clear RDE */
1195 tmp = readl(&dev->regs->ctl);
1196 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1197 writel(tmp, &dev->regs->ctl);
1198 open_rxfifo = 1;
1199
1200 /*
1201 * if BNA occurred then let BNA dummy desc.
1202 * point to current desc.
1203 */
1204 if (ep->bna_occurred) {
1205 VDBG(dev, "copy to BNA dummy desc.\n");
1206 memcpy(ep->bna_dummy_req->td_data,
1207 req->td_data,
1208 sizeof(struct udc_data_dma));
1209 }
1210 }
1211 /* write desc pointer */
1212 writel(req->td_phys, &ep->regs->desptr);
1213
1214 /* clear NAK by writing CNAK */
1215 if (ep->naking) {
1216 tmp = readl(&ep->regs->ctl);
1217 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1218 writel(tmp, &ep->regs->ctl);
1219 ep->naking = 0;
1220 UDC_QUEUE_CNAK(ep, ep->num);
1221 }
1222
1223 if (ep->in) {
1224 /* enable ep irq */
1225 tmp = readl(&dev->regs->ep_irqmsk);
1226 tmp &= AMD_UNMASK_BIT(ep->num);
1227 writel(tmp, &dev->regs->ep_irqmsk);
1228 }
c5deb832
TD		 1229 } else if (ep->in) {
1230 /* enable ep irq */
1231 tmp = readl(&dev->regs->ep_irqmsk);
1232 tmp &= AMD_UNMASK_BIT(ep->num);
1233 writel(tmp, &dev->regs->ep_irqmsk);
1234 }
55d402d8
TD		 1235
1236 } else if (ep->dma) {
1237
1238 /*
1239 * prep_dma not used for OUT ep's, this is not possible
1240 * for PPB modes, because of chain creation reasons
1241 */
1242 if (ep->in) {
ffcba5a5 1243 retval = prep_dma(ep, req, GFP_ATOMIC);
55d402d8
TD		 1244 if (retval != 0)
1245 goto finished;
1246 }
1247 }
1248 VDBG(dev, "list_add\n");
1249 /* add request to ep queue */
1250 if (req) {
1251
1252 list_add_tail(&req->queue, &ep->queue);
1253
1254 /* open rxfifo if out data queued */
1255 if (open_rxfifo) {
1256 /* enable DMA */
1257 req->dma_going = 1;
1258 udc_set_rde(dev);
1259 if (ep->num != UDC_EP0OUT_IX)
1260 dev->data_ep_queued = 1;
1261 }
1262 /* stop OUT naking */
1263 if (!ep->in) {
1264 if (!use_dma && udc_rxfifo_pending) {
fec8de3a 1265 DBG(dev, "udc_queue(): pending bytes in "
55d402d8
TD		 1266 "rxfifo after nyet\n");
1267 /*
1268 * read pending bytes afer nyet:
1269 * referring to isr
1270 */
1271 if (udc_rxfifo_read(ep, req)) {
1272 /* finish */
1273 complete_req(ep, req, 0);
1274 }
1275 udc_rxfifo_pending = 0;
1276
1277 }
1278 }
1279 }
1280
1281finished:
1282 spin_unlock_irqrestore(&dev->lock, iflags);
1283 return retval;
1284}
1285
1286/* Empty request queue of an endpoint; caller holds spinlock */
1287static void empty_req_queue(struct udc_ep *ep)
1288{
1289 struct udc_request *req;
1290
1291 ep->halted = 1;
1292 while (!list_empty(&ep->queue)) {
1293 req = list_entry(ep->queue.next,
1294 struct udc_request,
1295 queue);
1296 complete_req(ep, req, -ESHUTDOWN);
1297 }
1298}
1299
1300/* Dequeues a request packet, called by gadget driver */
1301static int udc_dequeue(struct usb_ep *usbep, struct usb_request *usbreq)
1302{
1303 struct udc_ep *ep;
1304 struct udc_request *req;
1305 unsigned halted;
1306 unsigned long iflags;
1307
1308 ep = container_of(usbep, struct udc_ep, ep);
ef20a72b 1309 if (!usbep || !usbreq || (!ep->ep.desc && (ep->num != 0
55d402d8
TD		 1310 && ep->num != UDC_EP0OUT_IX)))
1311 return -EINVAL;
1312
1313 req = container_of(usbreq, struct udc_request, req);
1314
1315 spin_lock_irqsave(&ep->dev->lock, iflags);
1316 halted = ep->halted;
1317 ep->halted = 1;
1318 /* request in processing or next one */
1319 if (ep->queue.next == &req->queue) {
1320 if (ep->dma && req->dma_going) {
1321 if (ep->in)
1322 ep->cancel_transfer = 1;
1323 else {
1324 u32 tmp;
1325 u32 dma_sts;
1326 /* stop potential receive DMA */
1327 tmp = readl(&udc->regs->ctl);
1328 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE),
1329 &udc->regs->ctl);
1330 /*
1331 * Cancel transfer later in ISR
1332 * if descriptor was touched.
1333 */
1334 dma_sts = AMD_GETBITS(req->td_data->status,
1335 UDC_DMA_OUT_STS_BS);
1336 if (dma_sts != UDC_DMA_OUT_STS_BS_HOST_READY)
1337 ep->cancel_transfer = 1;
1338 else {
1339 udc_init_bna_dummy(ep->req);
1340 writel(ep->bna_dummy_req->td_phys,
1341 &ep->regs->desptr);
1342 }
1343 writel(tmp, &udc->regs->ctl);
1344 }
1345 }
1346 }
1347 complete_req(ep, req, -ECONNRESET);
1348 ep->halted = halted;
1349
1350 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1351 return 0;
1352}
1353
1354/* Halt or clear halt of endpoint */
1355static int
1356udc_set_halt(struct usb_ep *usbep, int halt)
1357{
1358 struct udc_ep *ep;
1359 u32 tmp;
1360 unsigned long iflags;
1361 int retval = 0;
1362
1363 if (!usbep)
1364 return -EINVAL;
1365
1366 pr_debug("set_halt %s: halt=%d\n", usbep->name, halt);
1367
1368 ep = container_of(usbep, struct udc_ep, ep);
ef20a72b 1369 if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
55d402d8
TD		 1370 return -EINVAL;
1371 if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN)
1372 return -ESHUTDOWN;
1373
1374 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1375 /* halt or clear halt */
1376 if (halt) {
1377 if (ep->num == 0)
1378 ep->dev->stall_ep0in = 1;
1379 else {
1380 /*
1381 * set STALL
1382 * rxfifo empty not taken into acount
1383 */
1384 tmp = readl(&ep->regs->ctl);
1385 tmp |= AMD_BIT(UDC_EPCTL_S);
1386 writel(tmp, &ep->regs->ctl);
1387 ep->halted = 1;
1388
1389 /* setup poll timer */
1390 if (!timer_pending(&udc_pollstall_timer)) {
1391 udc_pollstall_timer.expires = jiffies +
1392 HZ * UDC_POLLSTALL_TIMER_USECONDS
1393 / (1000 * 1000);
1394 if (!stop_pollstall_timer) {
1395 DBG(ep->dev, "start polltimer\n");
1396 add_timer(&udc_pollstall_timer);
1397 }
1398 }
1399 }
1400 } else {
1401 /* ep is halted by set_halt() before */
1402 if (ep->halted) {
1403 tmp = readl(&ep->regs->ctl);
1404 /* clear stall bit */
1405 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
1406 /* clear NAK by writing CNAK */
1407 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1408 writel(tmp, &ep->regs->ctl);
1409 ep->halted = 0;
1410 UDC_QUEUE_CNAK(ep, ep->num);
1411 }
1412 }
1413 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1414 return retval;
1415}
1416
1417/* gadget interface */
1418static const struct usb_ep_ops udc_ep_ops = {
1419 .enable = udc_ep_enable,
1420 .disable = udc_ep_disable,
1421
1422 .alloc_request = udc_alloc_request,
1423 .free_request = udc_free_request,
1424
1425 .queue = udc_queue,
1426 .dequeue = udc_dequeue,
1427
1428 .set_halt = udc_set_halt,
1429 /* fifo ops not implemented */
1430};
1431
1432/*-------------------------------------------------------------------------*/
1433
1434/* Get frame counter (not implemented) */
1435static int udc_get_frame(struct usb_gadget *gadget)
1436{
1437 return -EOPNOTSUPP;
1438}
1439
79a5b4aa
SM		 1440/* Initiates a remote wakeup */
1441static int udc_remote_wakeup(struct udc *dev)
1442{
1443 unsigned long flags;
1444 u32 tmp;
1445
1446 DBG(dev, "UDC initiates remote wakeup\n");
1447
1448 spin_lock_irqsave(&dev->lock, flags);
1449
1450 tmp = readl(&dev->regs->ctl);
1451 tmp |= AMD_BIT(UDC_DEVCTL_RES);
1452 writel(tmp, &dev->regs->ctl);
1453 tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES);
1454 writel(tmp, &dev->regs->ctl);
1455
1456 spin_unlock_irqrestore(&dev->lock, flags);
1457 return 0;
1458}
1459
55d402d8
TD		 1460/* Remote wakeup gadget interface */
1461static int udc_wakeup(struct usb_gadget *gadget)
1462{
1463 struct udc *dev;
1464
1465 if (!gadget)
1466 return -EINVAL;
1467 dev = container_of(gadget, struct udc, gadget);
1468 udc_remote_wakeup(dev);
1469
1470 return 0;
1471}
1472
45005f69
FB		 1473static int amd5536_udc_start(struct usb_gadget *g,
1474 struct usb_gadget_driver *driver);
22835b80
FB		 1475static int amd5536_udc_stop(struct usb_gadget *g);
1476
55d402d8
TD		 1477static const struct usb_gadget_ops udc_ops = {
1478 .wakeup = udc_wakeup,
1479 .get_frame = udc_get_frame,
45005f69
FB		 1480 .udc_start = amd5536_udc_start,
1481 .udc_stop = amd5536_udc_stop,
55d402d8
TD		 1482};
1483
1484/* Setups endpoint parameters, adds endpoints to linked list */
1485static void make_ep_lists(struct udc *dev)
1486{
1487 /* make gadget ep lists */
1488 INIT_LIST_HEAD(&dev->gadget.ep_list);
1489 list_add_tail(&dev->ep[UDC_EPIN_STATUS_IX].ep.ep_list,
1490 &dev->gadget.ep_list);
1491 list_add_tail(&dev->ep[UDC_EPIN_IX].ep.ep_list,
1492 &dev->gadget.ep_list);
1493 list_add_tail(&dev->ep[UDC_EPOUT_IX].ep.ep_list,
1494 &dev->gadget.ep_list);
1495
1496 /* fifo config */
1497 dev->ep[UDC_EPIN_STATUS_IX].fifo_depth = UDC_EPIN_SMALLINT_BUFF_SIZE;
1498 if (dev->gadget.speed == USB_SPEED_FULL)
1499 dev->ep[UDC_EPIN_IX].fifo_depth = UDC_FS_EPIN_BUFF_SIZE;
1500 else if (dev->gadget.speed == USB_SPEED_HIGH)
1501 dev->ep[UDC_EPIN_IX].fifo_depth = hs_tx_buf;
1502 dev->ep[UDC_EPOUT_IX].fifo_depth = UDC_RXFIFO_SIZE;
1503}
1504
55d402d8
TD		 1505/* Inits UDC context */
1506static void udc_basic_init(struct udc *dev)
1507{
1508 u32 tmp;
1509
1510 DBG(dev, "udc_basic_init()\n");
1511
1512 dev->gadget.speed = USB_SPEED_UNKNOWN;
1513
1514 /* stop RDE timer */
1515 if (timer_pending(&udc_timer)) {
1516 set_rde = 0;
1517 mod_timer(&udc_timer, jiffies - 1);
1518 }
1519 /* stop poll stall timer */
170b778f 1520 if (timer_pending(&udc_pollstall_timer))
55d402d8 1521 mod_timer(&udc_pollstall_timer, jiffies - 1);
55d402d8
TD		 1522 /* disable DMA */
1523 tmp = readl(&dev->regs->ctl);
1524 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1525 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE);
1526 writel(tmp, &dev->regs->ctl);
1527
1528 /* enable dynamic CSR programming */
1529 tmp = readl(&dev->regs->cfg);
1530 tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG);
1531 /* set self powered */
1532 tmp |= AMD_BIT(UDC_DEVCFG_SP);
1533 /* set remote wakeupable */
1534 tmp |= AMD_BIT(UDC_DEVCFG_RWKP);
1535 writel(tmp, &dev->regs->cfg);
1536
1537 make_ep_lists(dev);
1538
1539 dev->data_ep_enabled = 0;
1540 dev->data_ep_queued = 0;
1541}
1542
5d31a17b
SM		 1543/* init registers at driver load time */
1544static int startup_registers(struct udc *dev)
1545{
1546 u32 tmp;
1547
1548 /* init controller by soft reset */
1549 udc_soft_reset(dev);
1550
1551 /* mask not needed interrupts */
1552 udc_mask_unused_interrupts(dev);
1553
1554 /* put into initial config */
1555 udc_basic_init(dev);
1556 /* link up all endpoints */
1557 udc_setup_endpoints(dev);
1558
1559 /* program speed */
1560 tmp = readl(&dev->regs->cfg);
1561 if (use_fullspeed)
1562 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1563 else
1564 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD);
1565 writel(tmp, &dev->regs->cfg);
1566
1567 return 0;
1568}
1569
55d402d8
TD		 1570/* Sets initial endpoint parameters */
1571static void udc_setup_endpoints(struct udc *dev)
1572{
1573 struct udc_ep *ep;
1574 u32 tmp;
1575 u32 reg;
1576
1577 DBG(dev, "udc_setup_endpoints()\n");
1578
1579 /* read enum speed */
1580 tmp = readl(&dev->regs->sts);
1581 tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED);
170b778f 1582 if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH)
55d402d8 1583 dev->gadget.speed = USB_SPEED_HIGH;
170b778f 1584 else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL)
55d402d8 1585 dev->gadget.speed = USB_SPEED_FULL;
55d402d8
TD		 1586
1587 /* set basic ep parameters */
1588 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1589 ep = &dev->ep[tmp];
1590 ep->dev = dev;
6f02ac5a
RB		 1591 ep->ep.name = ep_info[tmp].name;
1592 ep->ep.caps = ep_info[tmp].caps;
55d402d8
TD		 1593 ep->num = tmp;
1594 /* txfifo size is calculated at enable time */
1595 ep->txfifo = dev->txfifo;
1596
1597 /* fifo size */
1598 if (tmp < UDC_EPIN_NUM) {
1599 ep->fifo_depth = UDC_TXFIFO_SIZE;
1600 ep->in = 1;
1601 } else {
1602 ep->fifo_depth = UDC_RXFIFO_SIZE;
1603 ep->in = 0;
1604
1605 }
1606 ep->regs = &dev->ep_regs[tmp];
1607 /*
1608 * ep will be reset only if ep was not enabled before to avoid
1609 * disabling ep interrupts when ENUM interrupt occurs but ep is
1610 * not enabled by gadget driver
1611 */
ef20a72b 1612 if (!ep->ep.desc)
55d402d8 1613 ep_init(dev->regs, ep);
55d402d8
TD		 1614
1615 if (use_dma) {
1616 /*
1617 * ep->dma is not really used, just to indicate that
1618 * DMA is active: remove this
1619 * dma regs = dev control regs
1620 */
1621 ep->dma = &dev->regs->ctl;
1622
1623 /* nak OUT endpoints until enable - not for ep0 */
1624 if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX
1625 && tmp > UDC_EPIN_NUM) {
1626 /* set NAK */
1627 reg = readl(&dev->ep[tmp].regs->ctl);
1628 reg |= AMD_BIT(UDC_EPCTL_SNAK);
1629 writel(reg, &dev->ep[tmp].regs->ctl);
1630 dev->ep[tmp].naking = 1;
1631
1632 }
1633 }
1634 }
1635 /* EP0 max packet */
1636 if (dev->gadget.speed == USB_SPEED_FULL) {
e117e742
RB		 1637 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IX].ep,
1638 UDC_FS_EP0IN_MAX_PKT_SIZE);
1639 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IX].ep,
1640 UDC_FS_EP0OUT_MAX_PKT_SIZE);
55d402d8 1641 } else if (dev->gadget.speed == USB_SPEED_HIGH) {
e117e742
RB		 1642 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IX].ep,
1643 UDC_EP0IN_MAX_PKT_SIZE);
1644 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IX].ep,
1645 UDC_EP0OUT_MAX_PKT_SIZE);
55d402d8
TD		 1646 }
1647
1648 /*
1649 * with suspend bug workaround, ep0 params for gadget driver
1650 * are set at gadget driver bind() call
1651 */
1652 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
1653 dev->ep[UDC_EP0IN_IX].halted = 0;
1654 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1655
1656 /* init cfg/alt/int */
1657 dev->cur_config = 0;
1658 dev->cur_intf = 0;
1659 dev->cur_alt = 0;
1660}
1661
1662/* Bringup after Connect event, initial bringup to be ready for ep0 events */
1663static void usb_connect(struct udc *dev)
1664{
1665
1666 dev_info(&dev->pdev->dev, "USB Connect\n");
1667
1668 dev->connected = 1;
1669
1670 /* put into initial config */
1671 udc_basic_init(dev);
1672
1673 /* enable device setup interrupts */
1674 udc_enable_dev_setup_interrupts(dev);
1675}
1676
1677/*
1678 * Calls gadget with disconnect event and resets the UDC and makes
1679 * initial bringup to be ready for ep0 events
1680 */
1681static void usb_disconnect(struct udc *dev)
1682{
1683
1684 dev_info(&dev->pdev->dev, "USB Disconnect\n");
1685
1686 dev->connected = 0;
1687
1688 /* mask interrupts */
1689 udc_mask_unused_interrupts(dev);
1690
1691 /* REVISIT there doesn't seem to be a point to having this
1692 * talk to a tasklet ... do it directly, we already hold
1693 * the spinlock needed to process the disconnect.
1694 */
1695
1696 tasklet_schedule(&disconnect_tasklet);
1697}
1698
1699/* Tasklet for disconnect to be outside of interrupt context */
1700static void udc_tasklet_disconnect(unsigned long par)
1701{
1702 struct udc *dev = (struct udc *)(*((struct udc **) par));
1703 u32 tmp;
1704
1705 DBG(dev, "Tasklet disconnect\n");
1706 spin_lock_irq(&dev->lock);
1707
1708 if (dev->driver) {
1709 spin_unlock(&dev->lock);
1710 dev->driver->disconnect(&dev->gadget);
1711 spin_lock(&dev->lock);
1712
1713 /* empty queues */
170b778f 1714 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
55d402d8 1715 empty_req_queue(&dev->ep[tmp]);
55d402d8
TD		 1716
1717 }
1718
1719 /* disable ep0 */
1720 ep_init(dev->regs,
1721 &dev->ep[UDC_EP0IN_IX]);
1722
1723
1724 if (!soft_reset_occured) {
1725 /* init controller by soft reset */
1726 udc_soft_reset(dev);
1727 soft_reset_occured++;
1728 }
1729
1730 /* re-enable dev interrupts */
1731 udc_enable_dev_setup_interrupts(dev);
1732 /* back to full speed ? */
1733 if (use_fullspeed) {
1734 tmp = readl(&dev->regs->cfg);
1735 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1736 writel(tmp, &dev->regs->cfg);
1737 }
1738
1739 spin_unlock_irq(&dev->lock);
1740}
1741
1742/* Reset the UDC core */
1743static void udc_soft_reset(struct udc *dev)
1744{
1745 unsigned long flags;
1746
1747 DBG(dev, "Soft reset\n");
1748 /*
1749 * reset possible waiting interrupts, because int.
1750 * status is lost after soft reset,
1751 * ep int. status reset
1752 */
1753 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts);
1754 /* device int. status reset */
1755 writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts);
1756
1757 spin_lock_irqsave(&udc_irq_spinlock, flags);
1758 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
1759 readl(&dev->regs->cfg);
1760 spin_unlock_irqrestore(&udc_irq_spinlock, flags);
1761
1762}
1763
1764/* RDE timer callback to set RDE bit */
1765static void udc_timer_function(unsigned long v)
1766{
1767 u32 tmp;
1768
1769 spin_lock_irq(&udc_irq_spinlock);
1770
1771 if (set_rde > 0) {
1772 /*
1773 * open the fifo if fifo was filled on last timer call
1774 * conditionally
1775 */
1776 if (set_rde > 1) {
1777 /* set RDE to receive setup data */
1778 tmp = readl(&udc->regs->ctl);
1779 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1780 writel(tmp, &udc->regs->ctl);
1781 set_rde = -1;
1782 } else if (readl(&udc->regs->sts)
1783 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
1784 /*
1785 * if fifo empty setup polling, do not just
1786 * open the fifo
1787 */
1788 udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV;
170b778f 1789 if (!stop_timer)
55d402d8 1790 add_timer(&udc_timer);
55d402d8
TD		 1791 } else {
1792 /*
1793 * fifo contains data now, setup timer for opening
1794 * the fifo when timer expires to be able to receive
1795 * setup packets, when data packets gets queued by
1796 * gadget layer then timer will forced to expire with
1797 * set_rde=0 (RDE is set in udc_queue())
1798 */
1799 set_rde++;
1800 /* debug: lhadmot_timer_start = 221070 */
1801 udc_timer.expires = jiffies + HZ*UDC_RDE_TIMER_SECONDS;
170b778f 1802 if (!stop_timer)
55d402d8 1803 add_timer(&udc_timer);
55d402d8
TD		 1804 }
1805
1806 } else
1807 set_rde = -1; /* RDE was set by udc_queue() */
1808 spin_unlock_irq(&udc_irq_spinlock);
1809 if (stop_timer)
1810 complete(&on_exit);
1811
1812}
1813
1814/* Handle halt state, used in stall poll timer */
1815static void udc_handle_halt_state(struct udc_ep *ep)
1816{
1817 u32 tmp;
1818 /* set stall as long not halted */
1819 if (ep->halted == 1) {
1820 tmp = readl(&ep->regs->ctl);
1821 /* STALL cleared ? */
1822 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) {
1823 /*
1824 * FIXME: MSC spec requires that stall remains
1825 * even on receivng of CLEAR_FEATURE HALT. So
1826 * we would set STALL again here to be compliant.
1827 * But with current mass storage drivers this does
1828 * not work (would produce endless host retries).
1829 * So we clear halt on CLEAR_FEATURE.
1830 *
1831 DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1832 tmp |= AMD_BIT(UDC_EPCTL_S);
1833 writel(tmp, &ep->regs->ctl);*/
1834
1835 /* clear NAK by writing CNAK */
1836 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1837 writel(tmp, &ep->regs->ctl);
1838 ep->halted = 0;
1839 UDC_QUEUE_CNAK(ep, ep->num);
1840 }
1841 }
1842}
1843
1844/* Stall timer callback to poll S bit and set it again after */
1845static void udc_pollstall_timer_function(unsigned long v)
1846{
1847 struct udc_ep *ep;
1848 int halted = 0;
1849
1850 spin_lock_irq(&udc_stall_spinlock);
1851 /*
1852 * only one IN and OUT endpoints are handled
1853 * IN poll stall
1854 */
1855 ep = &udc->ep[UDC_EPIN_IX];
1856 udc_handle_halt_state(ep);
1857 if (ep->halted)
1858 halted = 1;
1859 /* OUT poll stall */
1860 ep = &udc->ep[UDC_EPOUT_IX];
1861 udc_handle_halt_state(ep);
1862 if (ep->halted)
1863 halted = 1;
1864
1865 /* setup timer again when still halted */
1866 if (!stop_pollstall_timer && halted) {
1867 udc_pollstall_timer.expires = jiffies +
1868 HZ * UDC_POLLSTALL_TIMER_USECONDS
1869 / (1000 * 1000);
1870 add_timer(&udc_pollstall_timer);
1871 }
1872 spin_unlock_irq(&udc_stall_spinlock);
1873
1874 if (stop_pollstall_timer)
1875 complete(&on_pollstall_exit);
1876}
1877
1878/* Inits endpoint 0 so that SETUP packets are processed */
1879static void activate_control_endpoints(struct udc *dev)
1880{
1881 u32 tmp;
1882
1883 DBG(dev, "activate_control_endpoints\n");
1884
1885 /* flush fifo */
1886 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1887 tmp |= AMD_BIT(UDC_EPCTL_F);
1888 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1889
1890 /* set ep0 directions */
1891 dev->ep[UDC_EP0IN_IX].in = 1;
1892 dev->ep[UDC_EP0OUT_IX].in = 0;
1893
1894 /* set buffer size (tx fifo entries) of EP0_IN */
1895 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1896 if (dev->gadget.speed == USB_SPEED_FULL)
1897 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE,
1898 UDC_EPIN_BUFF_SIZE);
1899 else if (dev->gadget.speed == USB_SPEED_HIGH)
1900 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE,
1901 UDC_EPIN_BUFF_SIZE);
1902 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1903
1904 /* set max packet size of EP0_IN */
1905 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1906 if (dev->gadget.speed == USB_SPEED_FULL)
1907 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE,
1908 UDC_EP_MAX_PKT_SIZE);
1909 else if (dev->gadget.speed == USB_SPEED_HIGH)
1910 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE,
1911 UDC_EP_MAX_PKT_SIZE);
1912 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1913
1914 /* set max packet size of EP0_OUT */
1915 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1916 if (dev->gadget.speed == USB_SPEED_FULL)
1917 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1918 UDC_EP_MAX_PKT_SIZE);
1919 else if (dev->gadget.speed == USB_SPEED_HIGH)
1920 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1921 UDC_EP_MAX_PKT_SIZE);
1922 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1923
1924 /* set max packet size of EP0 in UDC CSR */
1925 tmp = readl(&dev->csr->ne[0]);
1926 if (dev->gadget.speed == USB_SPEED_FULL)
1927 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1928 UDC_CSR_NE_MAX_PKT);
1929 else if (dev->gadget.speed == USB_SPEED_HIGH)
1930 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1931 UDC_CSR_NE_MAX_PKT);
1932 writel(tmp, &dev->csr->ne[0]);
1933
1934 if (use_dma) {
1935 dev->ep[UDC_EP0OUT_IX].td->status |=
1936 AMD_BIT(UDC_DMA_OUT_STS_L);
1937 /* write dma desc address */
1938 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma,
1939 &dev->ep[UDC_EP0OUT_IX].regs->subptr);
1940 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
1941 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
1942 /* stop RDE timer */
1943 if (timer_pending(&udc_timer)) {
1944 set_rde = 0;
1945 mod_timer(&udc_timer, jiffies - 1);
1946 }
1947 /* stop pollstall timer */
170b778f 1948 if (timer_pending(&udc_pollstall_timer))
55d402d8 1949 mod_timer(&udc_pollstall_timer, jiffies - 1);
55d402d8
TD		 1950 /* enable DMA */
1951 tmp = readl(&dev->regs->ctl);
1952 tmp |= AMD_BIT(UDC_DEVCTL_MODE)
1953 | AMD_BIT(UDC_DEVCTL_RDE)
1954 | AMD_BIT(UDC_DEVCTL_TDE);
170b778f 1955 if (use_dma_bufferfill_mode)
55d402d8 1956 tmp |= AMD_BIT(UDC_DEVCTL_BF);
170b778f 1957 else if (use_dma_ppb_du)
55d402d8 1958 tmp |= AMD_BIT(UDC_DEVCTL_DU);
55d402d8
TD		 1959 writel(tmp, &dev->regs->ctl);
1960 }
1961
1962 /* clear NAK by writing CNAK for EP0IN */
1963 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1964 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1965 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1966 dev->ep[UDC_EP0IN_IX].naking = 0;
1967 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
1968
1969 /* clear NAK by writing CNAK for EP0OUT */
1970 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
1971 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1972 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
1973 dev->ep[UDC_EP0OUT_IX].naking = 0;
1974 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
1975}
1976
1977/* Make endpoint 0 ready for control traffic */
1978static int setup_ep0(struct udc *dev)
1979{
1980 activate_control_endpoints(dev);
1981 /* enable ep0 interrupts */
1982 udc_enable_ep0_interrupts(dev);
1983 /* enable device setup interrupts */
1984 udc_enable_dev_setup_interrupts(dev);
1985
1986 return 0;
1987}
1988
1989/* Called by gadget driver to register itself */
45005f69
FB		 1990static int amd5536_udc_start(struct usb_gadget *g,
1991 struct usb_gadget_driver *driver)
55d402d8 1992{
45005f69 1993 struct udc *dev = to_amd5536_udc(g);
55d402d8
TD		 1994 u32 tmp;
1995
55d402d8
TD		 1996 driver->driver.bus = NULL;
1997 dev->driver = driver;
55d402d8 1998
55d402d8
TD		 1999 /* Some gadget drivers use both ep0 directions.
2000 * NOTE: to gadget driver, ep0 is just one endpoint...
2001 */
2002 dev->ep[UDC_EP0OUT_IX].ep.driver_data =
2003 dev->ep[UDC_EP0IN_IX].ep.driver_data;
2004
55d402d8
TD		 2005 /* get ready for ep0 traffic */
2006 setup_ep0(dev);
2007
2008 /* clear SD */
2009 tmp = readl(&dev->regs->ctl);
2010 tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD);
2011 writel(tmp, &dev->regs->ctl);
2012
2013 usb_connect(dev);
2014
2015 return 0;
2016}
55d402d8
TD		 2017
2018/* shutdown requests and disconnect from gadget */
2019static void
2020shutdown(struct udc *dev, struct usb_gadget_driver *driver)
2021__releases(dev->lock)
2022__acquires(dev->lock)
2023{
2024 int tmp;
2025
c5deb832
TD		 2026 /* empty queues and init hardware */
2027 udc_basic_init(dev);
45005f69 2028
c5deb832
TD		 2029 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
2030 empty_req_queue(&dev->ep[tmp]);
2031
55d402d8
TD		 2032 udc_setup_endpoints(dev);
2033}
2034
2035/* Called by gadget driver to unregister itself */
22835b80 2036static int amd5536_udc_stop(struct usb_gadget *g)
55d402d8 2037{
45005f69
FB		 2038 struct udc *dev = to_amd5536_udc(g);
2039 unsigned long flags;
55d402d8
TD		 2040 u32 tmp;
2041
55d402d8
TD		 2042 spin_lock_irqsave(&dev->lock, flags);
2043 udc_mask_unused_interrupts(dev);
21090f06 2044 shutdown(dev, NULL);
55d402d8
TD		 2045 spin_unlock_irqrestore(&dev->lock, flags);
2046
55d402d8
TD		 2047 dev->driver = NULL;
2048
2049 /* set SD */
2050 tmp = readl(&dev->regs->ctl);
2051 tmp |= AMD_BIT(UDC_DEVCTL_SD);
2052 writel(tmp, &dev->regs->ctl);
2053
55d402d8
TD		 2054 return 0;
2055}
55d402d8
TD		 2056
2057/* Clear pending NAK bits */
2058static void udc_process_cnak_queue(struct udc *dev)
2059{
2060 u32 tmp;
2061 u32 reg;
2062
2063 /* check epin's */
2064 DBG(dev, "CNAK pending queue processing\n");
2065 for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) {
2066 if (cnak_pending & (1 << tmp)) {
2067 DBG(dev, "CNAK pending for ep%d\n", tmp);
2068 /* clear NAK by writing CNAK */
2069 reg = readl(&dev->ep[tmp].regs->ctl);
2070 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2071 writel(reg, &dev->ep[tmp].regs->ctl);
2072 dev->ep[tmp].naking = 0;
2073 UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num);
2074 }
2075 }
2076 /* ... and ep0out */
2077 if (cnak_pending & (1 << UDC_EP0OUT_IX)) {
2078 DBG(dev, "CNAK pending for ep%d\n", UDC_EP0OUT_IX);
2079 /* clear NAK by writing CNAK */
2080 reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2081 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2082 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2083 dev->ep[UDC_EP0OUT_IX].naking = 0;
2084 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX],
2085 dev->ep[UDC_EP0OUT_IX].num);
2086 }
2087}
2088
2089/* Enabling RX DMA after setup packet */
2090static void udc_ep0_set_rde(struct udc *dev)
2091{
2092 if (use_dma) {
2093 /*
2094 * only enable RXDMA when no data endpoint enabled
2095 * or data is queued
2096 */
2097 if (!dev->data_ep_enabled || dev->data_ep_queued) {
2098 udc_set_rde(dev);
2099 } else {
2100 /*
2101 * setup timer for enabling RDE (to not enable
2102 * RXFIFO DMA for data endpoints to early)
2103 */
2104 if (set_rde != 0 && !timer_pending(&udc_timer)) {
2105 udc_timer.expires =
2106 jiffies + HZ/UDC_RDE_TIMER_DIV;
2107 set_rde = 1;
170b778f 2108 if (!stop_timer)
55d402d8 2109 add_timer(&udc_timer);
55d402d8
TD		 2110 }
2111 }
2112 }
2113}
2114
2115
2116/* Interrupt handler for data OUT traffic */
2117static irqreturn_t udc_data_out_isr(struct udc *dev, int ep_ix)
2118{
2119 irqreturn_t ret_val = IRQ_NONE;
2120 u32 tmp;
2121 struct udc_ep *ep;
2122 struct udc_request *req;
2123 unsigned int count;
2124 struct udc_data_dma *td = NULL;
2125 unsigned dma_done;
2126
2127 VDBG(dev, "ep%d irq\n", ep_ix);
2128 ep = &dev->ep[ep_ix];
2129
2130 tmp = readl(&ep->regs->sts);
2131 if (use_dma) {
2132 /* BNA event ? */
2133 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
5647a149 2134 DBG(dev, "BNA ep%dout occurred - DESPTR = %x\n",
55d402d8
TD		 2135 ep->num, readl(&ep->regs->desptr));
2136 /* clear BNA */
2137 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts);
2138 if (!ep->cancel_transfer)
2139 ep->bna_occurred = 1;
2140 else
2141 ep->cancel_transfer = 0;
2142 ret_val = IRQ_HANDLED;
2143 goto finished;
2144 }
2145 }
2146 /* HE event ? */
2147 if (tmp & AMD_BIT(UDC_EPSTS_HE)) {
25985edc 2148 dev_err(&dev->pdev->dev, "HE ep%dout occurred\n", ep->num);
55d402d8
TD		 2149
2150 /* clear HE */
2151 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2152 ret_val = IRQ_HANDLED;
2153 goto finished;
2154 }
2155
2156 if (!list_empty(&ep->queue)) {
2157
2158 /* next request */
2159 req = list_entry(ep->queue.next,
2160 struct udc_request, queue);
2161 } else {
2162 req = NULL;
2163 udc_rxfifo_pending = 1;
2164 }
2165 VDBG(dev, "req = %p\n", req);
2166 /* fifo mode */
2167 if (!use_dma) {
2168
2169 /* read fifo */
2170 if (req && udc_rxfifo_read(ep, req)) {
2171 ret_val = IRQ_HANDLED;
2172
2173 /* finish */
2174 complete_req(ep, req, 0);
2175 /* next request */
2176 if (!list_empty(&ep->queue) && !ep->halted) {
2177 req = list_entry(ep->queue.next,
2178 struct udc_request, queue);
2179 } else
2180 req = NULL;
2181 }
2182
2183 /* DMA */
1b701508 2184 } else if (!ep->cancel_transfer && req) {
55d402d8
TD		 2185 ret_val = IRQ_HANDLED;
2186
2187 /* check for DMA done */
2188 if (!use_dma_ppb) {
2189 dma_done = AMD_GETBITS(req->td_data->status,
2190 UDC_DMA_OUT_STS_BS);
2191 /* packet per buffer mode - rx bytes */
2192 } else {
2193 /*
2194 * if BNA occurred then recover desc. from
2195 * BNA dummy desc.
2196 */
2197 if (ep->bna_occurred) {
2198 VDBG(dev, "Recover desc. from BNA dummy\n");
2199 memcpy(req->td_data, ep->bna_dummy_req->td_data,
2200 sizeof(struct udc_data_dma));
2201 ep->bna_occurred = 0;
2202 udc_init_bna_dummy(ep->req);
2203 }
2204 td = udc_get_last_dma_desc(req);
2205 dma_done = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_BS);
2206 }
2207 if (dma_done == UDC_DMA_OUT_STS_BS_DMA_DONE) {
2208 /* buffer fill mode - rx bytes */
2209 if (!use_dma_ppb) {
2210 /* received number bytes */
2211 count = AMD_GETBITS(req->td_data->status,
2212 UDC_DMA_OUT_STS_RXBYTES);
2213 VDBG(dev, "rx bytes=%u\n", count);
2214 /* packet per buffer mode - rx bytes */
2215 } else {
2216 VDBG(dev, "req->td_data=%p\n", req->td_data);
2217 VDBG(dev, "last desc = %p\n", td);
2218 /* received number bytes */
2219 if (use_dma_ppb_du) {
2220 /* every desc. counts bytes */
2221 count = udc_get_ppbdu_rxbytes(req);
2222 } else {
2223 /* last desc. counts bytes */
2224 count = AMD_GETBITS(td->status,
2225 UDC_DMA_OUT_STS_RXBYTES);
2226 if (!count && req->req.length
2227 == UDC_DMA_MAXPACKET) {
2228 /*
2229 * on 64k packets the RXBYTES
2230 * field is zero
2231 */
2232 count = UDC_DMA_MAXPACKET;
2233 }
2234 }
2235 VDBG(dev, "last desc rx bytes=%u\n", count);
2236 }
2237
2238 tmp = req->req.length - req->req.actual;
2239 if (count > tmp) {
2240 if ((tmp % ep->ep.maxpacket) != 0) {
2241 DBG(dev, "%s: rx %db, space=%db\n",
2242 ep->ep.name, count, tmp);
2243 req->req.status = -EOVERFLOW;
2244 }
2245 count = tmp;
2246 }
2247 req->req.actual += count;
2248 req->dma_going = 0;
2249 /* complete request */
2250 complete_req(ep, req, 0);
2251
2252 /* next request */
2253 if (!list_empty(&ep->queue) && !ep->halted) {
2254 req = list_entry(ep->queue.next,
2255 struct udc_request,
2256 queue);
2257 /*
2258 * DMA may be already started by udc_queue()
2259 * called by gadget drivers completion
2260 * routine. This happens when queue
2261 * holds one request only.
2262 */
2263 if (req->dma_going == 0) {
2264 /* next dma */
2265 if (prep_dma(ep, req, GFP_ATOMIC) != 0)
2266 goto finished;
2267 /* write desc pointer */
2268 writel(req->td_phys,
2269 &ep->regs->desptr);
2270 req->dma_going = 1;
2271 /* enable DMA */
2272 udc_set_rde(dev);
2273 }
2274 } else {
2275 /*
2276 * implant BNA dummy descriptor to allow
2277 * RXFIFO opening by RDE
2278 */
2279 if (ep->bna_dummy_req) {
2280 /* write desc pointer */
2281 writel(ep->bna_dummy_req->td_phys,
2282 &ep->regs->desptr);
2283 ep->bna_occurred = 0;
2284 }
2285
2286 /*
2287 * schedule timer for setting RDE if queue
2288 * remains empty to allow ep0 packets pass
2289 * through
2290 */
2291 if (set_rde != 0
2292 && !timer_pending(&udc_timer)) {
2293 udc_timer.expires =
2294 jiffies
2295 + HZ*UDC_RDE_TIMER_SECONDS;
2296 set_rde = 1;
170b778f 2297 if (!stop_timer)
55d402d8 2298 add_timer(&udc_timer);
55d402d8
TD		 2299 }
2300 if (ep->num != UDC_EP0OUT_IX)
2301 dev->data_ep_queued = 0;
2302 }
2303
2304 } else {
2305 /*
2306 * RX DMA must be reenabled for each desc in PPBDU mode
2307 * and must be enabled for PPBNDU mode in case of BNA
2308 */
2309 udc_set_rde(dev);
2310 }
2311
2312 } else if (ep->cancel_transfer) {
2313 ret_val = IRQ_HANDLED;
2314 ep->cancel_transfer = 0;
2315 }
2316
2317 /* check pending CNAKS */
2318 if (cnak_pending) {
2319 /* CNAk processing when rxfifo empty only */
170b778f 2320 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
55d402d8 2321 udc_process_cnak_queue(dev);
55d402d8
TD		 2322 }
2323
2324 /* clear OUT bits in ep status */
2325 writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts);
2326finished:
2327 return ret_val;
2328}
2329
2330/* Interrupt handler for data IN traffic */
2331static irqreturn_t udc_data_in_isr(struct udc *dev, int ep_ix)
2332{
2333 irqreturn_t ret_val = IRQ_NONE;
2334 u32 tmp;
2335 u32 epsts;
2336 struct udc_ep *ep;
2337 struct udc_request *req;
2338 struct udc_data_dma *td;
55d402d8
TD		 2339 unsigned len;
2340
2341 ep = &dev->ep[ep_ix];
2342
2343 epsts = readl(&ep->regs->sts);
2344 if (use_dma) {
2345 /* BNA ? */
2346 if (epsts & AMD_BIT(UDC_EPSTS_BNA)) {
2347 dev_err(&dev->pdev->dev,
5647a149 2348 "BNA ep%din occurred - DESPTR = %08lx\n",
55d402d8
TD		 2349 ep->num,
2350 (unsigned long) readl(&ep->regs->desptr));
2351
2352 /* clear BNA */
2353 writel(epsts, &ep->regs->sts);
2354 ret_val = IRQ_HANDLED;
2355 goto finished;
2356 }
2357 }
2358 /* HE event ? */
2359 if (epsts & AMD_BIT(UDC_EPSTS_HE)) {
2360 dev_err(&dev->pdev->dev,
5647a149 2361 "HE ep%dn occurred - DESPTR = %08lx\n",
55d402d8
TD		 2362 ep->num, (unsigned long) readl(&ep->regs->desptr));
2363
2364 /* clear HE */
2365 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2366 ret_val = IRQ_HANDLED;
2367 goto finished;
2368 }
2369
2370 /* DMA completion */
2371 if (epsts & AMD_BIT(UDC_EPSTS_TDC)) {
2372 VDBG(dev, "TDC set- completion\n");
2373 ret_val = IRQ_HANDLED;
2374 if (!ep->cancel_transfer && !list_empty(&ep->queue)) {
2375 req = list_entry(ep->queue.next,
2376 struct udc_request, queue);
058e698b 2377 /*
25985edc 2378 * length bytes transferred
058e698b
JL		 2379 * check dma done of last desc. in PPBDU mode
2380 */
2381 if (use_dma_ppb_du) {
2382 td = udc_get_last_dma_desc(req);
872ce511 2383 if (td)
55d402d8 2384 req->req.actual = req->req.length;
058e698b
JL		 2385 } else {
2386 /* assume all bytes transferred */
2387 req->req.actual = req->req.length;
2388 }
55d402d8 2389
058e698b
JL		 2390 if (req->req.actual == req->req.length) {
2391 /* complete req */
2392 complete_req(ep, req, 0);
2393 req->dma_going = 0;
2394 /* further request available ? */
2395 if (list_empty(&ep->queue)) {
2396 /* disable interrupt */
2397 tmp = readl(&dev->regs->ep_irqmsk);
2398 tmp |= AMD_BIT(ep->num);
2399 writel(tmp, &dev->regs->ep_irqmsk);
55d402d8
TD		 2400 }
2401 }
2402 }
2403 ep->cancel_transfer = 0;
2404
2405 }
2406 /*
2407 * status reg has IN bit set and TDC not set (if TDC was handled,
2408 * IN must not be handled (UDC defect) ?
2409 */
2410 if ((epsts & AMD_BIT(UDC_EPSTS_IN))
2411 && !(epsts & AMD_BIT(UDC_EPSTS_TDC))) {
2412 ret_val = IRQ_HANDLED;
2413 if (!list_empty(&ep->queue)) {
2414 /* next request */
2415 req = list_entry(ep->queue.next,
2416 struct udc_request, queue);
2417 /* FIFO mode */
2418 if (!use_dma) {
2419 /* write fifo */
2420 udc_txfifo_write(ep, &req->req);
2421 len = req->req.length - req->req.actual;
1435db48
CR		 2422 if (len > ep->ep.maxpacket)
2423 len = ep->ep.maxpacket;
2424 req->req.actual += len;
55d402d8
TD		 2425 if (req->req.actual == req->req.length
2426 || (len != ep->ep.maxpacket)) {
2427 /* complete req */
2428 complete_req(ep, req, 0);
2429 }
2430 /* DMA */
2431 } else if (req && !req->dma_going) {
2432 VDBG(dev, "IN DMA : req=%p req->td_data=%p\n",
2433 req, req->td_data);
2434 if (req->td_data) {
2435
2436 req->dma_going = 1;
2437
2438 /*
2439 * unset L bit of first desc.
2440 * for chain
2441 */
2442 if (use_dma_ppb && req->req.length >
2443 ep->ep.maxpacket) {
2444 req->td_data->status &=
2445 AMD_CLEAR_BIT(
2446 UDC_DMA_IN_STS_L);
2447 }
2448
2449 /* write desc pointer */
2450 writel(req->td_phys, &ep->regs->desptr);
2451
2452 /* set HOST READY */
2453 req->td_data->status =
2454 AMD_ADDBITS(
2455 req->td_data->status,
2456 UDC_DMA_IN_STS_BS_HOST_READY,
2457 UDC_DMA_IN_STS_BS);
2458
2459 /* set poll demand bit */
2460 tmp = readl(&ep->regs->ctl);
2461 tmp |= AMD_BIT(UDC_EPCTL_P);
2462 writel(tmp, &ep->regs->ctl);
2463 }
2464 }
2465
c5deb832
TD		 2466 } else if (!use_dma && ep->in) {
2467 /* disable interrupt */
2468 tmp = readl(
2469 &dev->regs->ep_irqmsk);
2470 tmp |= AMD_BIT(ep->num);
2471 writel(tmp,
2472 &dev->regs->ep_irqmsk);
55d402d8
TD		 2473 }
2474 }
2475 /* clear status bits */
2476 writel(epsts, &ep->regs->sts);
2477
2478finished:
2479 return ret_val;
2480
2481}
2482
2483/* Interrupt handler for Control OUT traffic */
2484static irqreturn_t udc_control_out_isr(struct udc *dev)
2485__releases(dev->lock)
2486__acquires(dev->lock)
2487{
2488 irqreturn_t ret_val = IRQ_NONE;
2489 u32 tmp;
2490 int setup_supported;
2491 u32 count;
2492 int set = 0;
2493 struct udc_ep *ep;
2494 struct udc_ep *ep_tmp;
2495
2496 ep = &dev->ep[UDC_EP0OUT_IX];
2497
2498 /* clear irq */
2499 writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts);
2500
2501 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2502 /* check BNA and clear if set */
2503 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2504 VDBG(dev, "ep0: BNA set\n");
2505 writel(AMD_BIT(UDC_EPSTS_BNA),
2506 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2507 ep->bna_occurred = 1;
2508 ret_val = IRQ_HANDLED;
2509 goto finished;
2510 }
2511
2512 /* type of data: SETUP or DATA 0 bytes */
2513 tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT);
2514 VDBG(dev, "data_typ = %x\n", tmp);
2515
2516 /* setup data */
2517 if (tmp == UDC_EPSTS_OUT_SETUP) {
2518 ret_val = IRQ_HANDLED;
2519
2520 ep->dev->stall_ep0in = 0;
2521 dev->waiting_zlp_ack_ep0in = 0;
2522
2523 /* set NAK for EP0_IN */
2524 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2525 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
2526 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2527 dev->ep[UDC_EP0IN_IX].naking = 1;
2528 /* get setup data */
2529 if (use_dma) {
2530
2531 /* clear OUT bits in ep status */
2532 writel(UDC_EPSTS_OUT_CLEAR,
2533 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2534
2535 setup_data.data[0] =
2536 dev->ep[UDC_EP0OUT_IX].td_stp->data12;
2537 setup_data.data[1] =
2538 dev->ep[UDC_EP0OUT_IX].td_stp->data34;
2539 /* set HOST READY */
2540 dev->ep[UDC_EP0OUT_IX].td_stp->status =
2541 UDC_DMA_STP_STS_BS_HOST_READY;
2542 } else {
2543 /* read fifo */
2544 udc_rxfifo_read_dwords(dev, setup_data.data, 2);
2545 }
2546
2547 /* determine direction of control data */
2548 if ((setup_data.request.bRequestType & USB_DIR_IN) != 0) {
2549 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
2550 /* enable RDE */
2551 udc_ep0_set_rde(dev);
2552 set = 0;
2553 } else {
2554 dev->gadget.ep0 = &dev->ep[UDC_EP0OUT_IX].ep;
2555 /*
2556 * implant BNA dummy descriptor to allow RXFIFO opening
2557 * by RDE
2558 */
2559 if (ep->bna_dummy_req) {
2560 /* write desc pointer */
2561 writel(ep->bna_dummy_req->td_phys,
2562 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2563 ep->bna_occurred = 0;
2564 }
2565
2566 set = 1;
2567 dev->ep[UDC_EP0OUT_IX].naking = 1;
2568 /*
2569 * setup timer for enabling RDE (to not enable
2570 * RXFIFO DMA for data to early)
2571 */
2572 set_rde = 1;
2573 if (!timer_pending(&udc_timer)) {
2574 udc_timer.expires = jiffies +
2575 HZ/UDC_RDE_TIMER_DIV;
170b778f 2576 if (!stop_timer)
55d402d8 2577 add_timer(&udc_timer);
55d402d8
TD		 2578 }
2579 }
2580
2581 /*
2582 * mass storage reset must be processed here because
2583 * next packet may be a CLEAR_FEATURE HALT which would not
2584 * clear the stall bit when no STALL handshake was received
2585 * before (autostall can cause this)
2586 */
2587 if (setup_data.data[0] == UDC_MSCRES_DWORD0
2588 && setup_data.data[1] == UDC_MSCRES_DWORD1) {
2589 DBG(dev, "MSC Reset\n");
2590 /*
2591 * clear stall bits
2592 * only one IN and OUT endpoints are handled
2593 */
2594 ep_tmp = &udc->ep[UDC_EPIN_IX];
2595 udc_set_halt(&ep_tmp->ep, 0);
2596 ep_tmp = &udc->ep[UDC_EPOUT_IX];
2597 udc_set_halt(&ep_tmp->ep, 0);
2598 }
2599
2600 /* call gadget with setup data received */
2601 spin_unlock(&dev->lock);
2602 setup_supported = dev->driver->setup(&dev->gadget,
2603 &setup_data.request);
2604 spin_lock(&dev->lock);
2605
2606 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2607 /* ep0 in returns data (not zlp) on IN phase */
2608 if (setup_supported >= 0 && setup_supported <
2609 UDC_EP0IN_MAXPACKET) {
2610 /* clear NAK by writing CNAK in EP0_IN */
2611 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2612 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2613 dev->ep[UDC_EP0IN_IX].naking = 0;
2614 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
2615
2616 /* if unsupported request then stall */
2617 } else if (setup_supported < 0) {
2618 tmp |= AMD_BIT(UDC_EPCTL_S);
2619 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2620 } else
2621 dev->waiting_zlp_ack_ep0in = 1;
2622
2623
2624 /* clear NAK by writing CNAK in EP0_OUT */
2625 if (!set) {
2626 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2627 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2628 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2629 dev->ep[UDC_EP0OUT_IX].naking = 0;
2630 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
2631 }
2632
2633 if (!use_dma) {
2634 /* clear OUT bits in ep status */
2635 writel(UDC_EPSTS_OUT_CLEAR,
2636 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2637 }
2638
2639 /* data packet 0 bytes */
2640 } else if (tmp == UDC_EPSTS_OUT_DATA) {
2641 /* clear OUT bits in ep status */
2642 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
2643
2644 /* get setup data: only 0 packet */
2645 if (use_dma) {
2646 /* no req if 0 packet, just reactivate */
2647 if (list_empty(&dev->ep[UDC_EP0OUT_IX].queue)) {
2648 VDBG(dev, "ZLP\n");
2649
2650 /* set HOST READY */
2651 dev->ep[UDC_EP0OUT_IX].td->status =
2652 AMD_ADDBITS(
2653 dev->ep[UDC_EP0OUT_IX].td->status,
2654 UDC_DMA_OUT_STS_BS_HOST_READY,
2655 UDC_DMA_OUT_STS_BS);
2656 /* enable RDE */
2657 udc_ep0_set_rde(dev);
2658 ret_val = IRQ_HANDLED;
2659
2660 } else {
2661 /* control write */
2662 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2663 /* re-program desc. pointer for possible ZLPs */
2664 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
2665 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2666 /* enable RDE */
2667 udc_ep0_set_rde(dev);
2668 }
2669 } else {
2670
2671 /* received number bytes */
2672 count = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2673 count = AMD_GETBITS(count, UDC_EPSTS_RX_PKT_SIZE);
2674 /* out data for fifo mode not working */
2675 count = 0;
2676
2677 /* 0 packet or real data ? */
2678 if (count != 0) {
2679 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2680 } else {
2681 /* dummy read confirm */
2682 readl(&dev->ep[UDC_EP0OUT_IX].regs->confirm);
2683 ret_val = IRQ_HANDLED;
2684 }
2685 }
2686 }
2687
2688 /* check pending CNAKS */
2689 if (cnak_pending) {
2690 /* CNAk processing when rxfifo empty only */
170b778f 2691 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
55d402d8 2692 udc_process_cnak_queue(dev);
55d402d8
TD		 2693 }
2694
2695finished:
2696 return ret_val;
2697}
2698
2699/* Interrupt handler for Control IN traffic */
2700static irqreturn_t udc_control_in_isr(struct udc *dev)
2701{
2702 irqreturn_t ret_val = IRQ_NONE;
2703 u32 tmp;
2704 struct udc_ep *ep;
2705 struct udc_request *req;
2706 unsigned len;
2707
2708 ep = &dev->ep[UDC_EP0IN_IX];
2709
2710 /* clear irq */
2711 writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts);
2712
2713 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);
2714 /* DMA completion */
2715 if (tmp & AMD_BIT(UDC_EPSTS_TDC)) {
5647a149 2716 VDBG(dev, "isr: TDC clear\n");
55d402d8
TD		 2717 ret_val = IRQ_HANDLED;
2718
2719 /* clear TDC bit */
2720 writel(AMD_BIT(UDC_EPSTS_TDC),
2721 &dev->ep[UDC_EP0IN_IX].regs->sts);
2722
2723 /* status reg has IN bit set ? */
2724 } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) {
2725 ret_val = IRQ_HANDLED;
2726
2727 if (ep->dma) {
2728 /* clear IN bit */
2729 writel(AMD_BIT(UDC_EPSTS_IN),
2730 &dev->ep[UDC_EP0IN_IX].regs->sts);
2731 }
2732 if (dev->stall_ep0in) {
2733 DBG(dev, "stall ep0in\n");
2734 /* halt ep0in */
2735 tmp = readl(&ep->regs->ctl);
2736 tmp |= AMD_BIT(UDC_EPCTL_S);
2737 writel(tmp, &ep->regs->ctl);
2738 } else {
2739 if (!list_empty(&ep->queue)) {
2740 /* next request */
2741 req = list_entry(ep->queue.next,
2742 struct udc_request, queue);
2743
2744 if (ep->dma) {
2745 /* write desc pointer */
2746 writel(req->td_phys, &ep->regs->desptr);
2747 /* set HOST READY */
2748 req->td_data->status =
2749 AMD_ADDBITS(
2750 req->td_data->status,
2751 UDC_DMA_STP_STS_BS_HOST_READY,
2752 UDC_DMA_STP_STS_BS);
2753
2754 /* set poll demand bit */
2755 tmp =
2756 readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2757 tmp |= AMD_BIT(UDC_EPCTL_P);
2758 writel(tmp,
2759 &dev->ep[UDC_EP0IN_IX].regs->ctl);
2760
2761 /* all bytes will be transferred */
2762 req->req.actual = req->req.length;
2763
2764 /* complete req */
2765 complete_req(ep, req, 0);
2766
2767 } else {
2768 /* write fifo */
2769 udc_txfifo_write(ep, &req->req);
2770
25985edc 2771 /* lengh bytes transferred */
55d402d8
TD		 2772 len = req->req.length - req->req.actual;
2773 if (len > ep->ep.maxpacket)
2774 len = ep->ep.maxpacket;
2775
2776 req->req.actual += len;
2777 if (req->req.actual == req->req.length
2778 || (len != ep->ep.maxpacket)) {
2779 /* complete req */
2780 complete_req(ep, req, 0);
2781 }
2782 }
2783
2784 }
2785 }
2786 ep->halted = 0;
2787 dev->stall_ep0in = 0;
2788 if (!ep->dma) {
2789 /* clear IN bit */
2790 writel(AMD_BIT(UDC_EPSTS_IN),
2791 &dev->ep[UDC_EP0IN_IX].regs->sts);
2792 }
2793 }
2794
2795 return ret_val;
2796}
2797
2798
2799/* Interrupt handler for global device events */
2800static irqreturn_t udc_dev_isr(struct udc *dev, u32 dev_irq)
2801__releases(dev->lock)
2802__acquires(dev->lock)
2803{
2804 irqreturn_t ret_val = IRQ_NONE;
2805 u32 tmp;
2806 u32 cfg;
2807 struct udc_ep *ep;
2808 u16 i;
2809 u8 udc_csr_epix;
2810
2811 /* SET_CONFIG irq ? */
2812 if (dev_irq & AMD_BIT(UDC_DEVINT_SC)) {
2813 ret_val = IRQ_HANDLED;
2814
2815 /* read config value */
2816 tmp = readl(&dev->regs->sts);
2817 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG);
2818 DBG(dev, "SET_CONFIG interrupt: config=%d\n", cfg);
2819 dev->cur_config = cfg;
2820 dev->set_cfg_not_acked = 1;
2821
2822 /* make usb request for gadget driver */
2823 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2824 setup_data.request.bRequest = USB_REQ_SET_CONFIGURATION;
fd05e720 2825 setup_data.request.wValue = cpu_to_le16(dev->cur_config);
55d402d8
TD		 2826
2827 /* programm the NE registers */
2828 for (i = 0; i < UDC_EP_NUM; i++) {
2829 ep = &dev->ep[i];
2830 if (ep->in) {
2831
2832 /* ep ix in UDC CSR register space */
2833 udc_csr_epix = ep->num;
2834
2835
2836 /* OUT ep */
2837 } else {
2838 /* ep ix in UDC CSR register space */
2839 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2840 }
2841
2842 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2843 /* ep cfg */
2844 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config,
2845 UDC_CSR_NE_CFG);
2846 /* write reg */
2847 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2848
2849 /* clear stall bits */
2850 ep->halted = 0;
2851 tmp = readl(&ep->regs->ctl);
2852 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2853 writel(tmp, &ep->regs->ctl);
2854 }
2855 /* call gadget zero with setup data received */
2856 spin_unlock(&dev->lock);
2857 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2858 spin_lock(&dev->lock);
2859
2860 } /* SET_INTERFACE ? */
2861 if (dev_irq & AMD_BIT(UDC_DEVINT_SI)) {
2862 ret_val = IRQ_HANDLED;
2863
2864 dev->set_cfg_not_acked = 1;
2865 /* read interface and alt setting values */
2866 tmp = readl(&dev->regs->sts);
2867 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT);
2868 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF);
2869
2870 /* make usb request for gadget driver */
2871 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2872 setup_data.request.bRequest = USB_REQ_SET_INTERFACE;
2873 setup_data.request.bRequestType = USB_RECIP_INTERFACE;
fd05e720
AV		 2874 setup_data.request.wValue = cpu_to_le16(dev->cur_alt);
2875 setup_data.request.wIndex = cpu_to_le16(dev->cur_intf);
55d402d8
TD		 2876
2877 DBG(dev, "SET_INTERFACE interrupt: alt=%d intf=%d\n",
2878 dev->cur_alt, dev->cur_intf);
2879
2880 /* programm the NE registers */
2881 for (i = 0; i < UDC_EP_NUM; i++) {
2882 ep = &dev->ep[i];
2883 if (ep->in) {
2884
2885 /* ep ix in UDC CSR register space */
2886 udc_csr_epix = ep->num;
2887
2888
2889 /* OUT ep */
2890 } else {
2891 /* ep ix in UDC CSR register space */
2892 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2893 }
2894
2895 /* UDC CSR reg */
2896 /* set ep values */
2897 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2898 /* ep interface */
2899 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf,
2900 UDC_CSR_NE_INTF);
2901 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2902 /* ep alt */
2903 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt,
2904 UDC_CSR_NE_ALT);
2905 /* write reg */
2906 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2907
2908 /* clear stall bits */
2909 ep->halted = 0;
2910 tmp = readl(&ep->regs->ctl);
2911 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2912 writel(tmp, &ep->regs->ctl);
2913 }
2914
2915 /* call gadget zero with setup data received */
2916 spin_unlock(&dev->lock);
2917 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2918 spin_lock(&dev->lock);
2919
2920 } /* USB reset */
2921 if (dev_irq & AMD_BIT(UDC_DEVINT_UR)) {
2922 DBG(dev, "USB Reset interrupt\n");
2923 ret_val = IRQ_HANDLED;
2924
2925 /* allow soft reset when suspend occurs */
2926 soft_reset_occured = 0;
2927
2928 dev->waiting_zlp_ack_ep0in = 0;
2929 dev->set_cfg_not_acked = 0;
2930
2931 /* mask not needed interrupts */
2932 udc_mask_unused_interrupts(dev);
2933
2934 /* call gadget to resume and reset configs etc. */
2935 spin_unlock(&dev->lock);
2936 if (dev->sys_suspended && dev->driver->resume) {
2937 dev->driver->resume(&dev->gadget);
2938 dev->sys_suspended = 0;
2939 }
107d13c7 2940 usb_gadget_udc_reset(&dev->gadget, dev->driver);
55d402d8
TD		 2941 spin_lock(&dev->lock);
2942
2943 /* disable ep0 to empty req queue */
2944 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2945 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2946
2947 /* soft reset when rxfifo not empty */
2948 tmp = readl(&dev->regs->sts);
2949 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2950 && !soft_reset_after_usbreset_occured) {
2951 udc_soft_reset(dev);
2952 soft_reset_after_usbreset_occured++;
2953 }
2954
2955 /*
2956 * DMA reset to kill potential old DMA hw hang,
2957 * POLL bit is already reset by ep_init() through
2958 * disconnect()
2959 */
2960 DBG(dev, "DMA machine reset\n");
2961 tmp = readl(&dev->regs->cfg);
2962 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
2963 writel(tmp, &dev->regs->cfg);
2964
2965 /* put into initial config */
2966 udc_basic_init(dev);
2967
2968 /* enable device setup interrupts */
2969 udc_enable_dev_setup_interrupts(dev);
2970
2971 /* enable suspend interrupt */
2972 tmp = readl(&dev->regs->irqmsk);
2973 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US);
2974 writel(tmp, &dev->regs->irqmsk);
2975
2976 } /* USB suspend */
2977 if (dev_irq & AMD_BIT(UDC_DEVINT_US)) {
2978 DBG(dev, "USB Suspend interrupt\n");
2979 ret_val = IRQ_HANDLED;
2980 if (dev->driver->suspend) {
2981 spin_unlock(&dev->lock);
2982 dev->sys_suspended = 1;
2983 dev->driver->suspend(&dev->gadget);
2984 spin_lock(&dev->lock);
2985 }
2986 } /* new speed ? */
2987 if (dev_irq & AMD_BIT(UDC_DEVINT_ENUM)) {
2988 DBG(dev, "ENUM interrupt\n");
2989 ret_val = IRQ_HANDLED;
2990 soft_reset_after_usbreset_occured = 0;
2991
2992 /* disable ep0 to empty req queue */
2993 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2994 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2995
2996 /* link up all endpoints */
2997 udc_setup_endpoints(dev);
e538dfda
MN		 2998 dev_info(&dev->pdev->dev, "Connect: %s\n",
2999 usb_speed_string(dev->gadget.speed));
55d402d8
TD		 3000
3001 /* init ep 0 */
3002 activate_control_endpoints(dev);
3003
3004 /* enable ep0 interrupts */
3005 udc_enable_ep0_interrupts(dev);
3006 }
3007 /* session valid change interrupt */
3008 if (dev_irq & AMD_BIT(UDC_DEVINT_SVC)) {
3009 DBG(dev, "USB SVC interrupt\n");
3010 ret_val = IRQ_HANDLED;
3011
3012 /* check that session is not valid to detect disconnect */
3013 tmp = readl(&dev->regs->sts);
3014 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) {
3015 /* disable suspend interrupt */
3016 tmp = readl(&dev->regs->irqmsk);
3017 tmp |= AMD_BIT(UDC_DEVINT_US);
3018 writel(tmp, &dev->regs->irqmsk);
3019 DBG(dev, "USB Disconnect (session valid low)\n");
3020 /* cleanup on disconnect */
3021 usb_disconnect(udc);
3022 }
3023
3024 }
3025
3026 return ret_val;
3027}
3028
3029/* Interrupt Service Routine, see Linux Kernel Doc for parameters */
3030static irqreturn_t udc_irq(int irq, void *pdev)
3031{
3032 struct udc *dev = pdev;
3033 u32 reg;
3034 u16 i;
3035 u32 ep_irq;
3036 irqreturn_t ret_val = IRQ_NONE;
3037
3038 spin_lock(&dev->lock);
3039
3040 /* check for ep irq */
3041 reg = readl(&dev->regs->ep_irqsts);
3042 if (reg) {
3043 if (reg & AMD_BIT(UDC_EPINT_OUT_EP0))
3044 ret_val |= udc_control_out_isr(dev);
3045 if (reg & AMD_BIT(UDC_EPINT_IN_EP0))
3046 ret_val |= udc_control_in_isr(dev);
3047
3048 /*
3049 * data endpoint
3050 * iterate ep's
3051 */
3052 for (i = 1; i < UDC_EP_NUM; i++) {
3053 ep_irq = 1 << i;
3054 if (!(reg & ep_irq) || i == UDC_EPINT_OUT_EP0)
3055 continue;
3056
3057 /* clear irq status */
3058 writel(ep_irq, &dev->regs->ep_irqsts);
3059
3060 /* irq for out ep ? */
3061 if (i > UDC_EPIN_NUM)
3062 ret_val |= udc_data_out_isr(dev, i);
3063 else
3064 ret_val |= udc_data_in_isr(dev, i);
3065 }
3066
3067 }
3068
3069
3070 /* check for dev irq */
3071 reg = readl(&dev->regs->irqsts);
3072 if (reg) {
3073 /* clear irq */
3074 writel(reg, &dev->regs->irqsts);
3075 ret_val |= udc_dev_isr(dev, reg);
3076 }
3077
3078
3079 spin_unlock(&dev->lock);
3080 return ret_val;
3081}
3082
3083/* Tears down device */
3084static void gadget_release(struct device *pdev)
3085{
3086 struct amd5536udc *dev = dev_get_drvdata(pdev);
3087 kfree(dev);
3088}
3089
3090/* Cleanup on device remove */
3091static void udc_remove(struct udc *dev)
3092{
3093 /* remove timer */
3094 stop_timer++;
3095 if (timer_pending(&udc_timer))
3096 wait_for_completion(&on_exit);
3097 if (udc_timer.data)
3098 del_timer_sync(&udc_timer);
3099 /* remove pollstall timer */
3100 stop_pollstall_timer++;
3101 if (timer_pending(&udc_pollstall_timer))
3102 wait_for_completion(&on_pollstall_exit);
3103 if (udc_pollstall_timer.data)
3104 del_timer_sync(&udc_pollstall_timer);
3105 udc = NULL;
3106}
3107
580693bb
SM		 3108/* free all the dma pools */
3109static void free_dma_pools(struct udc *dev)
3110{
3111 dma_pool_free(dev->stp_requests, dev->ep[UDC_EP0OUT_IX].td,
3112 dev->ep[UDC_EP0OUT_IX].td_phys);
3113 dma_pool_free(dev->stp_requests, dev->ep[UDC_EP0OUT_IX].td_stp,
3114 dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3115 dma_pool_destroy(dev->stp_requests);
3116 dma_pool_destroy(dev->data_requests);
3117}
3118
55d402d8
TD		 3119/* Reset all pci context */
3120static void udc_pci_remove(struct pci_dev *pdev)
3121{
3122 struct udc *dev;
3123
3124 dev = pci_get_drvdata(pdev);
3125
0f91349b 3126 usb_del_gadget_udc(&udc->gadget);
55d402d8 3127 /* gadget driver must not be registered */
2e1b7d0c
SM		 3128 if (WARN_ON(dev->driver))
3129 return;
55d402d8
TD		 3130
3131 /* dma pool cleanup */
f349dd3c 3132 free_dma_pools(dev);
55d402d8
TD		 3133
3134 /* reset controller */
3135 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
76c3727d
SM		 3136 free_irq(pdev->irq, dev);
3137 iounmap(dev->virt_addr);
3138 release_mem_region(pci_resource_start(pdev, 0),
3139 pci_resource_len(pdev, 0));
3140 pci_disable_device(pdev);
55d402d8 3141
55d402d8
TD		 3142 udc_remove(dev);
3143}
3144
3145/* create dma pools on init */
3146static int init_dma_pools(struct udc *dev)
3147{
3148 struct udc_stp_dma *td_stp;
3149 struct udc_data_dma *td_data;
3150 int retval;
3151
3152 /* consistent DMA mode setting ? */
3153 if (use_dma_ppb) {
3154 use_dma_bufferfill_mode = 0;
3155 } else {
3156 use_dma_ppb_du = 0;
3157 use_dma_bufferfill_mode = 1;
3158 }
3159
3160 /* DMA setup */
3161 dev->data_requests = dma_pool_create("data_requests", NULL,
3162 sizeof(struct udc_data_dma), 0, 0);
3163 if (!dev->data_requests) {
3164 DBG(dev, "can't get request data pool\n");
14a37ec6 3165 return -ENOMEM;
55d402d8
TD		 3166 }
3167
3168 /* EP0 in dma regs = dev control regs */
3169 dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;
3170
3171 /* dma desc for setup data */
3172 dev->stp_requests = dma_pool_create("setup requests", NULL,
3173 sizeof(struct udc_stp_dma), 0, 0);
3174 if (!dev->stp_requests) {
3175 DBG(dev, "can't get stp request pool\n");
3176 retval = -ENOMEM;
14a37ec6 3177 goto err_create_dma_pool;
55d402d8
TD		 3178 }
3179 /* setup */
3180 td_stp = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3181 &dev->ep[UDC_EP0OUT_IX].td_stp_dma);
1b701508 3182 if (!td_stp) {
55d402d8 3183 retval = -ENOMEM;
14a37ec6 3184 goto err_alloc_dma;
55d402d8
TD		 3185 }
3186 dev->ep[UDC_EP0OUT_IX].td_stp = td_stp;
3187
3188 /* data: 0 packets !? */
3189 td_data = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3190 &dev->ep[UDC_EP0OUT_IX].td_phys);
1b701508 3191 if (!td_data) {
55d402d8 3192 retval = -ENOMEM;
14a37ec6 3193 goto err_alloc_phys;
55d402d8
TD		 3194 }
3195 dev->ep[UDC_EP0OUT_IX].td = td_data;
3196 return 0;
3197
14a37ec6
SM		 3198err_alloc_phys:
3199 dma_pool_free(dev->stp_requests, dev->ep[UDC_EP0OUT_IX].td_stp,
3200 dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3201err_alloc_dma:
3202 dma_pool_destroy(dev->stp_requests);
3203 dev->stp_requests = NULL;
3204err_create_dma_pool:
3205 dma_pool_destroy(dev->data_requests);
3206 dev->data_requests = NULL;
55d402d8
TD		 3207 return retval;
3208}
3209
4f06b6bb
SM		 3210/* general probe */
3211static int udc_probe(struct udc *dev)
3212{
3213 char tmp[128];
3214 u32 reg;
3215 int retval;
3216
3217 /* mark timer as not initialized */
3218 udc_timer.data = 0;
3219 udc_pollstall_timer.data = 0;
3220
3221 /* device struct setup */
3222 dev->gadget.ops = &udc_ops;
3223
3224 dev_set_name(&dev->gadget.dev, "gadget");
3225 dev->gadget.name = name;
3226 dev->gadget.max_speed = USB_SPEED_HIGH;
3227
3228 /* init registers, interrupts, ... */
3229 startup_registers(dev);
3230
3231 dev_info(&dev->pdev->dev, "%s\n", mod_desc);
3232
3233 snprintf(tmp, sizeof(tmp), "%d", dev->irq);
3234 dev_info(&dev->pdev->dev,
3235 "irq %s, pci mem %08lx, chip rev %02x(Geode5536 %s)\n",
3236 tmp, dev->phys_addr, dev->chiprev,
3237 (dev->chiprev == UDC_HSA0_REV) ? "A0" : "B1");
3238 strcpy(tmp, UDC_DRIVER_VERSION_STRING);
3239 if (dev->chiprev == UDC_HSA0_REV) {
3240 dev_err(&dev->pdev->dev, "chip revision is A0; too old\n");
3241 retval = -ENODEV;
3242 goto finished;
3243 }
3244 dev_info(&dev->pdev->dev,
3245 "driver version: %s(for Geode5536 B1)\n", tmp);
3246 udc = dev;
3247
3248 retval = usb_add_gadget_udc_release(&udc->pdev->dev, &dev->gadget,
3249 gadget_release);
3250 if (retval)
3251 goto finished;
3252
3253 /* timer init */
3254 init_timer(&udc_timer);
3255 udc_timer.function = udc_timer_function;
3256 udc_timer.data = 1;
3257 /* timer pollstall init */
3258 init_timer(&udc_pollstall_timer);
3259 udc_pollstall_timer.function = udc_pollstall_timer_function;
3260 udc_pollstall_timer.data = 1;
3261
3262 /* set SD */
3263 reg = readl(&dev->regs->ctl);
3264 reg |= AMD_BIT(UDC_DEVCTL_SD);
3265 writel(reg, &dev->regs->ctl);
3266
3267 /* print dev register info */
3268 print_regs(dev);
3269
3270 return 0;
3271
3272finished:
3273 return retval;
3274}
3275
55d402d8
TD		 3276/* Called by pci bus driver to init pci context */
3277static int udc_pci_probe(
3278 struct pci_dev *pdev,
3279 const struct pci_device_id *id
3280)
3281{
3282 struct udc *dev;
3283 unsigned long resource;
3284 unsigned long len;
3285 int retval = 0;
3286
3287 /* one udc only */
3288 if (udc) {
3289 dev_dbg(&pdev->dev, "already probed\n");
3290 return -EBUSY;
3291 }
3292
3293 /* init */
3294 dev = kzalloc(sizeof(struct udc), GFP_KERNEL);
6527cc27
AK		 3295 if (!dev)
3296 return -ENOMEM;
55d402d8
TD		 3297
3298 /* pci setup */
3299 if (pci_enable_device(pdev) < 0) {
3300 retval = -ENODEV;
6527cc27 3301 goto err_pcidev;
55d402d8 3302 }
55d402d8
TD		 3303
3304 /* PCI resource allocation */
3305 resource = pci_resource_start(pdev, 0);
3306 len = pci_resource_len(pdev, 0);
3307
3308 if (!request_mem_region(resource, len, name)) {
3309 dev_dbg(&pdev->dev, "pci device used already\n");
3310 retval = -EBUSY;
6527cc27 3311 goto err_memreg;
55d402d8 3312 }
55d402d8
TD		 3313
3314 dev->virt_addr = ioremap_nocache(resource, len);
1b701508 3315 if (!dev->virt_addr) {
55d402d8
TD		 3316 dev_dbg(&pdev->dev, "start address cannot be mapped\n");
3317 retval = -EFAULT;
6527cc27 3318 goto err_ioremap;
55d402d8
TD		 3319 }
3320
3321 if (!pdev->irq) {
25e14c1f 3322 dev_err(&pdev->dev, "irq not set\n");
55d402d8 3323 retval = -ENODEV;
6527cc27 3324 goto err_irq;
55d402d8
TD		 3325 }
3326
c5deb832
TD		 3327 spin_lock_init(&dev->lock);
3328 /* udc csr registers base */
3329 dev->csr = dev->virt_addr + UDC_CSR_ADDR;
3330 /* dev registers base */
3331 dev->regs = dev->virt_addr + UDC_DEVCFG_ADDR;
3332 /* ep registers base */
3333 dev->ep_regs = dev->virt_addr + UDC_EPREGS_ADDR;
3334 /* fifo's base */
3335 dev->rxfifo = (u32 __iomem *)(dev->virt_addr + UDC_RXFIFO_ADDR);
3336 dev->txfifo = (u32 __iomem *)(dev->virt_addr + UDC_TXFIFO_ADDR);
3337
55d402d8 3338 if (request_irq(pdev->irq, udc_irq, IRQF_SHARED, name, dev) != 0) {
25e14c1f 3339 dev_dbg(&pdev->dev, "request_irq(%d) fail\n", pdev->irq);
55d402d8 3340 retval = -EBUSY;
6527cc27 3341 goto err_irq;
55d402d8 3342 }
55d402d8
TD		 3343
3344 pci_set_drvdata(pdev, dev);
3345
1d3ee41e
AK		 3346 /* chip revision for Hs AMD5536 */
3347 dev->chiprev = pdev->revision;
55d402d8
TD		 3348
3349 pci_set_master(pdev);
51745281 3350 pci_try_set_mwi(pdev);
55d402d8 3351
55d402d8
TD		 3352 /* init dma pools */
3353 if (use_dma) {
3354 retval = init_dma_pools(dev);
3355 if (retval != 0)
580693bb 3356 goto err_dma;
55d402d8
TD		 3357 }
3358
3359 dev->phys_addr = resource;
3360 dev->irq = pdev->irq;
3361 dev->pdev = pdev;
55d402d8
TD		 3362
3363 /* general probing */
580693bb
SM		 3364 if (udc_probe(dev)) {
3365 retval = -ENODEV;
3366 goto err_probe;
3367 }
3368 return 0;
6527cc27 3369
580693bb
SM		 3370err_probe:
3371 if (use_dma)
3372 free_dma_pools(dev);
3373err_dma:
3374 free_irq(pdev->irq, dev);
6527cc27
AK		 3375err_irq:
3376 iounmap(dev->virt_addr);
3377err_ioremap:
3378 release_mem_region(resource, len);
3379err_memreg:
3380 pci_disable_device(pdev);
3381err_pcidev:
3382 kfree(dev);
55d402d8
TD		 3383 return retval;
3384}
3385
55d402d8 3386/* PCI device parameters */
9510ecee 3387static const struct pci_device_id pci_id[] = {
55d402d8
TD		 3388 {
3389 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x2096),
7b78f48a 3390 .class = PCI_CLASS_SERIAL_USB_DEVICE,
55d402d8
TD		 3391 .class_mask = 0xffffffff,
3392 },
3393 {},
3394};
3395MODULE_DEVICE_TABLE(pci, pci_id);
3396
3397/* PCI functions */
3398static struct pci_driver udc_pci_driver = {
3399 .name = (char *) name,
3400 .id_table = pci_id,
3401 .probe = udc_pci_probe,
3402 .remove = udc_pci_remove,
3403};
3404
3cdb7721 3405module_pci_driver(udc_pci_driver);
55d402d8
TD		 3406
3407MODULE_DESCRIPTION(UDC_MOD_DESCRIPTION);
3408MODULE_AUTHOR("Thomas Dahlmann");
3409MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)