Commit | Line | Data |
---|---|---|
8b9bc460 LM |
1 | /** |
2 | * linux/drivers/usb/gadget/s3c-hsotg.c | |
dfbc6fa3 AT |
3 | * |
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
5b7d70c6 BD |
6 | * |
7 | * Copyright 2008 Openmoko, Inc. | |
8 | * Copyright 2008 Simtec Electronics | |
9 | * Ben Dooks <ben@simtec.co.uk> | |
10 | * http://armlinux.simtec.co.uk/ | |
11 | * | |
12 | * S3C USB2.0 High-speed / OtG driver | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
8b9bc460 | 17 | */ |
5b7d70c6 BD |
18 | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/dma-mapping.h> | |
25 | #include <linux/debugfs.h> | |
26 | #include <linux/seq_file.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/io.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
e50bf385 | 30 | #include <linux/clk.h> |
fc9a731e | 31 | #include <linux/regulator/consumer.h> |
c50f056c | 32 | #include <linux/of_platform.h> |
5b7d70c6 BD |
33 | |
34 | #include <linux/usb/ch9.h> | |
35 | #include <linux/usb/gadget.h> | |
b2e587db | 36 | #include <linux/usb/phy.h> |
126625e1 | 37 | #include <linux/platform_data/s3c-hsotg.h> |
5b7d70c6 BD |
38 | |
39 | #include <mach/map.h> | |
40 | ||
127d42ae | 41 | #include "s3c-hsotg.h" |
5b7d70c6 | 42 | |
fc9a731e LM |
43 | static const char * const s3c_hsotg_supply_names[] = { |
44 | "vusb_d", /* digital USB supply, 1.2V */ | |
45 | "vusb_a", /* analog USB supply, 1.1V */ | |
46 | }; | |
47 | ||
8b9bc460 LM |
48 | /* |
49 | * EP0_MPS_LIMIT | |
5b7d70c6 BD |
50 | * |
51 | * Unfortunately there seems to be a limit of the amount of data that can | |
25985edc LDM |
52 | * be transferred by IN transactions on EP0. This is either 127 bytes or 3 |
53 | * packets (which practically means 1 packet and 63 bytes of data) when the | |
5b7d70c6 BD |
54 | * MPS is set to 64. |
55 | * | |
56 | * This means if we are wanting to move >127 bytes of data, we need to | |
57 | * split the transactions up, but just doing one packet at a time does | |
58 | * not work (this may be an implicit DATA0 PID on first packet of the | |
59 | * transaction) and doing 2 packets is outside the controller's limits. | |
60 | * | |
61 | * If we try to lower the MPS size for EP0, then no transfers work properly | |
62 | * for EP0, and the system will fail basic enumeration. As no cause for this | |
63 | * has currently been found, we cannot support any large IN transfers for | |
64 | * EP0. | |
65 | */ | |
66 | #define EP0_MPS_LIMIT 64 | |
67 | ||
68 | struct s3c_hsotg; | |
69 | struct s3c_hsotg_req; | |
70 | ||
71 | /** | |
72 | * struct s3c_hsotg_ep - driver endpoint definition. | |
73 | * @ep: The gadget layer representation of the endpoint. | |
74 | * @name: The driver generated name for the endpoint. | |
75 | * @queue: Queue of requests for this endpoint. | |
76 | * @parent: Reference back to the parent device structure. | |
77 | * @req: The current request that the endpoint is processing. This is | |
78 | * used to indicate an request has been loaded onto the endpoint | |
79 | * and has yet to be completed (maybe due to data move, or simply | |
80 | * awaiting an ack from the core all the data has been completed). | |
81 | * @debugfs: File entry for debugfs file for this endpoint. | |
82 | * @lock: State lock to protect contents of endpoint. | |
83 | * @dir_in: Set to true if this endpoint is of the IN direction, which | |
84 | * means that it is sending data to the Host. | |
85 | * @index: The index for the endpoint registers. | |
4fca54aa | 86 | * @mc: Multi Count - number of transactions per microframe |
1479e841 | 87 | * @interval - Interval for periodic endpoints |
5b7d70c6 BD |
88 | * @name: The name array passed to the USB core. |
89 | * @halted: Set if the endpoint has been halted. | |
90 | * @periodic: Set if this is a periodic ep, such as Interrupt | |
1479e841 | 91 | * @isochronous: Set if this is a isochronous ep |
5b7d70c6 BD |
92 | * @sent_zlp: Set if we've sent a zero-length packet. |
93 | * @total_data: The total number of data bytes done. | |
94 | * @fifo_size: The size of the FIFO (for periodic IN endpoints) | |
95 | * @fifo_load: The amount of data loaded into the FIFO (periodic IN) | |
96 | * @last_load: The offset of data for the last start of request. | |
97 | * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN | |
98 | * | |
99 | * This is the driver's state for each registered enpoint, allowing it | |
100 | * to keep track of transactions that need doing. Each endpoint has a | |
101 | * lock to protect the state, to try and avoid using an overall lock | |
102 | * for the host controller as much as possible. | |
103 | * | |
104 | * For periodic IN endpoints, we have fifo_size and fifo_load to try | |
105 | * and keep track of the amount of data in the periodic FIFO for each | |
106 | * of these as we don't have a status register that tells us how much | |
e7a9ff54 BD |
107 | * is in each of them. (note, this may actually be useless information |
108 | * as in shared-fifo mode periodic in acts like a single-frame packet | |
109 | * buffer than a fifo) | |
5b7d70c6 BD |
110 | */ |
111 | struct s3c_hsotg_ep { | |
112 | struct usb_ep ep; | |
113 | struct list_head queue; | |
114 | struct s3c_hsotg *parent; | |
115 | struct s3c_hsotg_req *req; | |
116 | struct dentry *debugfs; | |
117 | ||
5b7d70c6 BD |
118 | |
119 | unsigned long total_data; | |
120 | unsigned int size_loaded; | |
121 | unsigned int last_load; | |
122 | unsigned int fifo_load; | |
123 | unsigned short fifo_size; | |
124 | ||
125 | unsigned char dir_in; | |
126 | unsigned char index; | |
4fca54aa | 127 | unsigned char mc; |
1479e841 | 128 | unsigned char interval; |
5b7d70c6 BD |
129 | |
130 | unsigned int halted:1; | |
131 | unsigned int periodic:1; | |
1479e841 | 132 | unsigned int isochronous:1; |
5b7d70c6 BD |
133 | unsigned int sent_zlp:1; |
134 | ||
135 | char name[10]; | |
136 | }; | |
137 | ||
5b7d70c6 BD |
138 | /** |
139 | * struct s3c_hsotg - driver state. | |
140 | * @dev: The parent device supplied to the probe function | |
141 | * @driver: USB gadget driver | |
b2e587db PP |
142 | * @phy: The otg phy transceiver structure for phy control. |
143 | * @plat: The platform specific configuration data. This can be removed once | |
144 | * all SoCs support usb transceiver. | |
5b7d70c6 | 145 | * @regs: The memory area mapped for accessing registers. |
5b7d70c6 | 146 | * @irq: The IRQ number we are using |
fc9a731e | 147 | * @supplies: Definition of USB power supplies |
10aebc77 | 148 | * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. |
b3f489b2 | 149 | * @num_of_eps: Number of available EPs (excluding EP0) |
5b7d70c6 BD |
150 | * @debug_root: root directrory for debugfs. |
151 | * @debug_file: main status file for debugfs. | |
152 | * @debug_fifo: FIFO status file for debugfs. | |
153 | * @ep0_reply: Request used for ep0 reply. | |
154 | * @ep0_buff: Buffer for EP0 reply data, if needed. | |
155 | * @ctrl_buff: Buffer for EP0 control requests. | |
156 | * @ctrl_req: Request for EP0 control packets. | |
71225bee | 157 | * @setup: NAK management for EP0 SETUP |
12a1f4dc | 158 | * @last_rst: Time of last reset |
5b7d70c6 BD |
159 | * @eps: The endpoints being supplied to the gadget framework |
160 | */ | |
161 | struct s3c_hsotg { | |
162 | struct device *dev; | |
163 | struct usb_gadget_driver *driver; | |
b2e587db | 164 | struct usb_phy *phy; |
5b7d70c6 BD |
165 | struct s3c_hsotg_plat *plat; |
166 | ||
22258f49 LM |
167 | spinlock_t lock; |
168 | ||
5b7d70c6 | 169 | void __iomem *regs; |
5b7d70c6 | 170 | int irq; |
31ee04de | 171 | struct clk *clk; |
5b7d70c6 | 172 | |
fc9a731e LM |
173 | struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)]; |
174 | ||
10aebc77 | 175 | unsigned int dedicated_fifos:1; |
b3f489b2 | 176 | unsigned char num_of_eps; |
10aebc77 | 177 | |
5b7d70c6 BD |
178 | struct dentry *debug_root; |
179 | struct dentry *debug_file; | |
180 | struct dentry *debug_fifo; | |
181 | ||
182 | struct usb_request *ep0_reply; | |
183 | struct usb_request *ctrl_req; | |
184 | u8 ep0_buff[8]; | |
185 | u8 ctrl_buff[8]; | |
186 | ||
187 | struct usb_gadget gadget; | |
71225bee | 188 | unsigned int setup; |
12a1f4dc | 189 | unsigned long last_rst; |
b3f489b2 | 190 | struct s3c_hsotg_ep *eps; |
5b7d70c6 BD |
191 | }; |
192 | ||
193 | /** | |
194 | * struct s3c_hsotg_req - data transfer request | |
195 | * @req: The USB gadget request | |
196 | * @queue: The list of requests for the endpoint this is queued for. | |
197 | * @in_progress: Has already had size/packets written to core | |
198 | * @mapped: DMA buffer for this request has been mapped via dma_map_single(). | |
199 | */ | |
200 | struct s3c_hsotg_req { | |
201 | struct usb_request req; | |
202 | struct list_head queue; | |
203 | unsigned char in_progress; | |
204 | unsigned char mapped; | |
205 | }; | |
206 | ||
207 | /* conversion functions */ | |
208 | static inline struct s3c_hsotg_req *our_req(struct usb_request *req) | |
209 | { | |
210 | return container_of(req, struct s3c_hsotg_req, req); | |
211 | } | |
212 | ||
213 | static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep) | |
214 | { | |
215 | return container_of(ep, struct s3c_hsotg_ep, ep); | |
216 | } | |
217 | ||
218 | static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget) | |
219 | { | |
220 | return container_of(gadget, struct s3c_hsotg, gadget); | |
221 | } | |
222 | ||
223 | static inline void __orr32(void __iomem *ptr, u32 val) | |
224 | { | |
225 | writel(readl(ptr) | val, ptr); | |
226 | } | |
227 | ||
228 | static inline void __bic32(void __iomem *ptr, u32 val) | |
229 | { | |
230 | writel(readl(ptr) & ~val, ptr); | |
231 | } | |
232 | ||
233 | /* forward decleration of functions */ | |
234 | static void s3c_hsotg_dump(struct s3c_hsotg *hsotg); | |
235 | ||
236 | /** | |
237 | * using_dma - return the DMA status of the driver. | |
238 | * @hsotg: The driver state. | |
239 | * | |
240 | * Return true if we're using DMA. | |
241 | * | |
242 | * Currently, we have the DMA support code worked into everywhere | |
243 | * that needs it, but the AMBA DMA implementation in the hardware can | |
244 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
245 | * as the CDC Ethernet cannot work as they often pass packets which are | |
246 | * not 32bit aligned. | |
247 | * | |
248 | * Unfortunately the choice to use DMA or not is global to the controller | |
249 | * and seems to be only settable when the controller is being put through | |
250 | * a core reset. This means we either need to fix the gadgets to take | |
251 | * account of DMA alignment, or add bounce buffers (yuerk). | |
252 | * | |
253 | * Until this issue is sorted out, we always return 'false'. | |
254 | */ | |
255 | static inline bool using_dma(struct s3c_hsotg *hsotg) | |
256 | { | |
257 | return false; /* support is not complete */ | |
258 | } | |
259 | ||
260 | /** | |
261 | * s3c_hsotg_en_gsint - enable one or more of the general interrupt | |
262 | * @hsotg: The device state | |
263 | * @ints: A bitmask of the interrupts to enable | |
264 | */ | |
265 | static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints) | |
266 | { | |
94cb8fd6 | 267 | u32 gsintmsk = readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
268 | u32 new_gsintmsk; |
269 | ||
270 | new_gsintmsk = gsintmsk | ints; | |
271 | ||
272 | if (new_gsintmsk != gsintmsk) { | |
273 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
94cb8fd6 | 274 | writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
275 | } |
276 | } | |
277 | ||
278 | /** | |
279 | * s3c_hsotg_disable_gsint - disable one or more of the general interrupt | |
280 | * @hsotg: The device state | |
281 | * @ints: A bitmask of the interrupts to enable | |
282 | */ | |
283 | static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints) | |
284 | { | |
94cb8fd6 | 285 | u32 gsintmsk = readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
286 | u32 new_gsintmsk; |
287 | ||
288 | new_gsintmsk = gsintmsk & ~ints; | |
289 | ||
290 | if (new_gsintmsk != gsintmsk) | |
94cb8fd6 | 291 | writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
292 | } |
293 | ||
294 | /** | |
295 | * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq | |
296 | * @hsotg: The device state | |
297 | * @ep: The endpoint index | |
298 | * @dir_in: True if direction is in. | |
299 | * @en: The enable value, true to enable | |
300 | * | |
301 | * Set or clear the mask for an individual endpoint's interrupt | |
302 | * request. | |
303 | */ | |
304 | static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg, | |
305 | unsigned int ep, unsigned int dir_in, | |
306 | unsigned int en) | |
307 | { | |
308 | unsigned long flags; | |
309 | u32 bit = 1 << ep; | |
310 | u32 daint; | |
311 | ||
312 | if (!dir_in) | |
313 | bit <<= 16; | |
314 | ||
315 | local_irq_save(flags); | |
94cb8fd6 | 316 | daint = readl(hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
317 | if (en) |
318 | daint |= bit; | |
319 | else | |
320 | daint &= ~bit; | |
94cb8fd6 | 321 | writel(daint, hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
322 | local_irq_restore(flags); |
323 | } | |
324 | ||
325 | /** | |
326 | * s3c_hsotg_init_fifo - initialise non-periodic FIFOs | |
327 | * @hsotg: The device instance. | |
328 | */ | |
329 | static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg) | |
330 | { | |
0f002d20 BD |
331 | unsigned int ep; |
332 | unsigned int addr; | |
333 | unsigned int size; | |
1703a6d3 | 334 | int timeout; |
0f002d20 BD |
335 | u32 val; |
336 | ||
6d091ee7 | 337 | /* set FIFO sizes to 2048/1024 */ |
5b7d70c6 | 338 | |
94cb8fd6 LM |
339 | writel(2048, hsotg->regs + GRXFSIZ); |
340 | writel(GNPTXFSIZ_NPTxFStAddr(2048) | | |
341 | GNPTXFSIZ_NPTxFDep(1024), | |
342 | hsotg->regs + GNPTXFSIZ); | |
0f002d20 | 343 | |
8b9bc460 LM |
344 | /* |
345 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
346 | * block have overlapping default addresses. This also ensures |
347 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
348 | * known values. |
349 | */ | |
0f002d20 BD |
350 | |
351 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
352 | addr = 2048 + 1024; | |
353 | size = 768; | |
354 | ||
8b9bc460 LM |
355 | /* |
356 | * currently we allocate TX FIFOs for all possible endpoints, | |
357 | * and assume that they are all the same size. | |
358 | */ | |
0f002d20 | 359 | |
f7a83fe1 | 360 | for (ep = 1; ep <= 15; ep++) { |
0f002d20 | 361 | val = addr; |
94cb8fd6 | 362 | val |= size << DPTXFSIZn_DPTxFSize_SHIFT; |
0f002d20 BD |
363 | addr += size; |
364 | ||
94cb8fd6 | 365 | writel(val, hsotg->regs + DPTXFSIZn(ep)); |
0f002d20 | 366 | } |
1703a6d3 | 367 | |
8b9bc460 LM |
368 | /* |
369 | * according to p428 of the design guide, we need to ensure that | |
370 | * all fifos are flushed before continuing | |
371 | */ | |
1703a6d3 | 372 | |
94cb8fd6 LM |
373 | writel(GRSTCTL_TxFNum(0x10) | GRSTCTL_TxFFlsh | |
374 | GRSTCTL_RxFFlsh, hsotg->regs + GRSTCTL); | |
1703a6d3 BD |
375 | |
376 | /* wait until the fifos are both flushed */ | |
377 | timeout = 100; | |
378 | while (1) { | |
94cb8fd6 | 379 | val = readl(hsotg->regs + GRSTCTL); |
1703a6d3 | 380 | |
94cb8fd6 | 381 | if ((val & (GRSTCTL_TxFFlsh | GRSTCTL_RxFFlsh)) == 0) |
1703a6d3 BD |
382 | break; |
383 | ||
384 | if (--timeout == 0) { | |
385 | dev_err(hsotg->dev, | |
386 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
387 | __func__, val); | |
388 | } | |
389 | ||
390 | udelay(1); | |
391 | } | |
392 | ||
393 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
394 | } |
395 | ||
396 | /** | |
397 | * @ep: USB endpoint to allocate request for. | |
398 | * @flags: Allocation flags | |
399 | * | |
400 | * Allocate a new USB request structure appropriate for the specified endpoint | |
401 | */ | |
0978f8c5 MB |
402 | static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep, |
403 | gfp_t flags) | |
5b7d70c6 BD |
404 | { |
405 | struct s3c_hsotg_req *req; | |
406 | ||
407 | req = kzalloc(sizeof(struct s3c_hsotg_req), flags); | |
408 | if (!req) | |
409 | return NULL; | |
410 | ||
411 | INIT_LIST_HEAD(&req->queue); | |
412 | ||
5b7d70c6 BD |
413 | return &req->req; |
414 | } | |
415 | ||
416 | /** | |
417 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
418 | * @hs_ep: The endpoint to query. | |
419 | * | |
420 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
421 | * used for an Interrupt or ISO transfer. | |
422 | */ | |
423 | static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep) | |
424 | { | |
425 | return hs_ep->periodic; | |
426 | } | |
427 | ||
428 | /** | |
429 | * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request | |
430 | * @hsotg: The device state. | |
431 | * @hs_ep: The endpoint for the request | |
432 | * @hs_req: The request being processed. | |
433 | * | |
434 | * This is the reverse of s3c_hsotg_map_dma(), called for the completion | |
435 | * of a request to ensure the buffer is ready for access by the caller. | |
8b9bc460 | 436 | */ |
5b7d70c6 BD |
437 | static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg, |
438 | struct s3c_hsotg_ep *hs_ep, | |
439 | struct s3c_hsotg_req *hs_req) | |
440 | { | |
441 | struct usb_request *req = &hs_req->req; | |
5b7d70c6 BD |
442 | |
443 | /* ignore this if we're not moving any data */ | |
444 | if (hs_req->req.length == 0) | |
445 | return; | |
446 | ||
17d966a3 | 447 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
448 | } |
449 | ||
450 | /** | |
451 | * s3c_hsotg_write_fifo - write packet Data to the TxFIFO | |
452 | * @hsotg: The controller state. | |
453 | * @hs_ep: The endpoint we're going to write for. | |
454 | * @hs_req: The request to write data for. | |
455 | * | |
456 | * This is called when the TxFIFO has some space in it to hold a new | |
457 | * transmission and we have something to give it. The actual setup of | |
458 | * the data size is done elsewhere, so all we have to do is to actually | |
459 | * write the data. | |
460 | * | |
461 | * The return value is zero if there is more space (or nothing was done) | |
462 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
463 | * | |
464 | * This routine is only needed for PIO | |
8b9bc460 | 465 | */ |
5b7d70c6 BD |
466 | static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg, |
467 | struct s3c_hsotg_ep *hs_ep, | |
468 | struct s3c_hsotg_req *hs_req) | |
469 | { | |
470 | bool periodic = is_ep_periodic(hs_ep); | |
94cb8fd6 | 471 | u32 gnptxsts = readl(hsotg->regs + GNPTXSTS); |
5b7d70c6 BD |
472 | int buf_pos = hs_req->req.actual; |
473 | int to_write = hs_ep->size_loaded; | |
474 | void *data; | |
475 | int can_write; | |
476 | int pkt_round; | |
4fca54aa | 477 | int max_transfer; |
5b7d70c6 BD |
478 | |
479 | to_write -= (buf_pos - hs_ep->last_load); | |
480 | ||
481 | /* if there's nothing to write, get out early */ | |
482 | if (to_write == 0) | |
483 | return 0; | |
484 | ||
10aebc77 | 485 | if (periodic && !hsotg->dedicated_fifos) { |
94cb8fd6 | 486 | u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
487 | int size_left; |
488 | int size_done; | |
489 | ||
8b9bc460 LM |
490 | /* |
491 | * work out how much data was loaded so we can calculate | |
492 | * how much data is left in the fifo. | |
493 | */ | |
5b7d70c6 | 494 | |
94cb8fd6 | 495 | size_left = DxEPTSIZ_XferSize_GET(epsize); |
5b7d70c6 | 496 | |
8b9bc460 LM |
497 | /* |
498 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
499 | * previous data has been completely sent. |
500 | */ | |
501 | if (hs_ep->fifo_load != 0) { | |
94cb8fd6 | 502 | s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp); |
e7a9ff54 BD |
503 | return -ENOSPC; |
504 | } | |
505 | ||
5b7d70c6 BD |
506 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
507 | __func__, size_left, | |
508 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
509 | ||
510 | /* how much of the data has moved */ | |
511 | size_done = hs_ep->size_loaded - size_left; | |
512 | ||
513 | /* how much data is left in the fifo */ | |
514 | can_write = hs_ep->fifo_load - size_done; | |
515 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
516 | __func__, can_write); | |
517 | ||
518 | can_write = hs_ep->fifo_size - can_write; | |
519 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
520 | __func__, can_write); | |
521 | ||
522 | if (can_write <= 0) { | |
94cb8fd6 | 523 | s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp); |
5b7d70c6 BD |
524 | return -ENOSPC; |
525 | } | |
10aebc77 | 526 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
94cb8fd6 | 527 | can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index)); |
10aebc77 BD |
528 | |
529 | can_write &= 0xffff; | |
530 | can_write *= 4; | |
5b7d70c6 | 531 | } else { |
94cb8fd6 | 532 | if (GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
533 | dev_dbg(hsotg->dev, |
534 | "%s: no queue slots available (0x%08x)\n", | |
535 | __func__, gnptxsts); | |
536 | ||
94cb8fd6 | 537 | s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTxFEmp); |
5b7d70c6 BD |
538 | return -ENOSPC; |
539 | } | |
540 | ||
94cb8fd6 | 541 | can_write = GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts); |
679f9b7c | 542 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
543 | } |
544 | ||
4fca54aa RB |
545 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
546 | ||
547 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
548 | __func__, gnptxsts, can_write, to_write, max_transfer); | |
5b7d70c6 | 549 | |
8b9bc460 LM |
550 | /* |
551 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
552 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
553 | * fragment of the end of the transfer in it. | |
554 | */ | |
555 | if (can_write > 512) | |
556 | can_write = 512; | |
557 | ||
8b9bc460 LM |
558 | /* |
559 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 560 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
561 | * doing it. |
562 | */ | |
4fca54aa RB |
563 | if (to_write > max_transfer) { |
564 | to_write = max_transfer; | |
03e10e5a | 565 | |
5cb2ff0c RB |
566 | /* it's needed only when we do not use dedicated fifos */ |
567 | if (!hsotg->dedicated_fifos) | |
568 | s3c_hsotg_en_gsint(hsotg, | |
569 | periodic ? GINTSTS_PTxFEmp : | |
570 | GINTSTS_NPTxFEmp); | |
03e10e5a BD |
571 | } |
572 | ||
5b7d70c6 BD |
573 | /* see if we can write data */ |
574 | ||
575 | if (to_write > can_write) { | |
576 | to_write = can_write; | |
4fca54aa | 577 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 578 | |
8b9bc460 LM |
579 | /* |
580 | * Round the write down to an | |
5b7d70c6 BD |
581 | * exact number of packets. |
582 | * | |
583 | * Note, we do not currently check to see if we can ever | |
584 | * write a full packet or not to the FIFO. | |
585 | */ | |
586 | ||
587 | if (pkt_round) | |
588 | to_write -= pkt_round; | |
589 | ||
8b9bc460 LM |
590 | /* |
591 | * enable correct FIFO interrupt to alert us when there | |
592 | * is more room left. | |
593 | */ | |
5b7d70c6 | 594 | |
5cb2ff0c RB |
595 | /* it's needed only when we do not use dedicated fifos */ |
596 | if (!hsotg->dedicated_fifos) | |
597 | s3c_hsotg_en_gsint(hsotg, | |
598 | periodic ? GINTSTS_PTxFEmp : | |
599 | GINTSTS_NPTxFEmp); | |
5b7d70c6 BD |
600 | } |
601 | ||
602 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
603 | to_write, hs_req->req.length, can_write, buf_pos); | |
604 | ||
605 | if (to_write <= 0) | |
606 | return -ENOSPC; | |
607 | ||
608 | hs_req->req.actual = buf_pos + to_write; | |
609 | hs_ep->total_data += to_write; | |
610 | ||
611 | if (periodic) | |
612 | hs_ep->fifo_load += to_write; | |
613 | ||
614 | to_write = DIV_ROUND_UP(to_write, 4); | |
615 | data = hs_req->req.buf + buf_pos; | |
616 | ||
94cb8fd6 | 617 | writesl(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
618 | |
619 | return (to_write >= can_write) ? -ENOSPC : 0; | |
620 | } | |
621 | ||
622 | /** | |
623 | * get_ep_limit - get the maximum data legnth for this endpoint | |
624 | * @hs_ep: The endpoint | |
625 | * | |
626 | * Return the maximum data that can be queued in one go on a given endpoint | |
627 | * so that transfers that are too long can be split. | |
628 | */ | |
629 | static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep) | |
630 | { | |
631 | int index = hs_ep->index; | |
632 | unsigned maxsize; | |
633 | unsigned maxpkt; | |
634 | ||
635 | if (index != 0) { | |
94cb8fd6 LM |
636 | maxsize = DxEPTSIZ_XferSize_LIMIT + 1; |
637 | maxpkt = DxEPTSIZ_PktCnt_LIMIT + 1; | |
5b7d70c6 | 638 | } else { |
b05ca580 | 639 | maxsize = 64+64; |
66e5c643 | 640 | if (hs_ep->dir_in) |
94cb8fd6 | 641 | maxpkt = DIEPTSIZ0_PktCnt_LIMIT + 1; |
66e5c643 | 642 | else |
5b7d70c6 | 643 | maxpkt = 2; |
5b7d70c6 BD |
644 | } |
645 | ||
646 | /* we made the constant loading easier above by using +1 */ | |
647 | maxpkt--; | |
648 | maxsize--; | |
649 | ||
8b9bc460 LM |
650 | /* |
651 | * constrain by packet count if maxpkts*pktsize is greater | |
652 | * than the length register size. | |
653 | */ | |
5b7d70c6 BD |
654 | |
655 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
656 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
657 | ||
658 | return maxsize; | |
659 | } | |
660 | ||
661 | /** | |
662 | * s3c_hsotg_start_req - start a USB request from an endpoint's queue | |
663 | * @hsotg: The controller state. | |
664 | * @hs_ep: The endpoint to process a request for | |
665 | * @hs_req: The request to start. | |
666 | * @continuing: True if we are doing more for the current request. | |
667 | * | |
668 | * Start the given request running by setting the endpoint registers | |
669 | * appropriately, and writing any data to the FIFOs. | |
670 | */ | |
671 | static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg, | |
672 | struct s3c_hsotg_ep *hs_ep, | |
673 | struct s3c_hsotg_req *hs_req, | |
674 | bool continuing) | |
675 | { | |
676 | struct usb_request *ureq = &hs_req->req; | |
677 | int index = hs_ep->index; | |
678 | int dir_in = hs_ep->dir_in; | |
679 | u32 epctrl_reg; | |
680 | u32 epsize_reg; | |
681 | u32 epsize; | |
682 | u32 ctrl; | |
683 | unsigned length; | |
684 | unsigned packets; | |
685 | unsigned maxreq; | |
686 | ||
687 | if (index != 0) { | |
688 | if (hs_ep->req && !continuing) { | |
689 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
690 | WARN_ON(1); | |
691 | return; | |
692 | } else if (hs_ep->req != hs_req && continuing) { | |
693 | dev_err(hsotg->dev, | |
694 | "%s: continue different req\n", __func__); | |
695 | WARN_ON(1); | |
696 | return; | |
697 | } | |
698 | } | |
699 | ||
94cb8fd6 LM |
700 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
701 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
702 | |
703 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
704 | __func__, readl(hsotg->regs + epctrl_reg), index, | |
705 | hs_ep->dir_in ? "in" : "out"); | |
706 | ||
9c39ddc6 AT |
707 | /* If endpoint is stalled, we will restart request later */ |
708 | ctrl = readl(hsotg->regs + epctrl_reg); | |
709 | ||
94cb8fd6 | 710 | if (ctrl & DxEPCTL_Stall) { |
9c39ddc6 AT |
711 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
712 | return; | |
713 | } | |
714 | ||
5b7d70c6 | 715 | length = ureq->length - ureq->actual; |
71225bee LM |
716 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
717 | ureq->length, ureq->actual); | |
5b7d70c6 BD |
718 | if (0) |
719 | dev_dbg(hsotg->dev, | |
720 | "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n", | |
721 | ureq->buf, length, ureq->dma, | |
722 | ureq->no_interrupt, ureq->zero, ureq->short_not_ok); | |
723 | ||
724 | maxreq = get_ep_limit(hs_ep); | |
725 | if (length > maxreq) { | |
726 | int round = maxreq % hs_ep->ep.maxpacket; | |
727 | ||
728 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
729 | __func__, length, maxreq, round); | |
730 | ||
731 | /* round down to multiple of packets */ | |
732 | if (round) | |
733 | maxreq -= round; | |
734 | ||
735 | length = maxreq; | |
736 | } | |
737 | ||
738 | if (length) | |
739 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
740 | else | |
741 | packets = 1; /* send one packet if length is zero. */ | |
742 | ||
4fca54aa RB |
743 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
744 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
745 | return; | |
746 | } | |
747 | ||
5b7d70c6 | 748 | if (dir_in && index != 0) |
4fca54aa RB |
749 | if (hs_ep->isochronous) |
750 | epsize = DxEPTSIZ_MC(packets); | |
751 | else | |
752 | epsize = DxEPTSIZ_MC(1); | |
5b7d70c6 BD |
753 | else |
754 | epsize = 0; | |
755 | ||
756 | if (index != 0 && ureq->zero) { | |
8b9bc460 LM |
757 | /* |
758 | * test for the packets being exactly right for the | |
759 | * transfer | |
760 | */ | |
5b7d70c6 BD |
761 | |
762 | if (length == (packets * hs_ep->ep.maxpacket)) | |
763 | packets++; | |
764 | } | |
765 | ||
94cb8fd6 LM |
766 | epsize |= DxEPTSIZ_PktCnt(packets); |
767 | epsize |= DxEPTSIZ_XferSize(length); | |
5b7d70c6 BD |
768 | |
769 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
770 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
771 | ||
772 | /* store the request as the current one we're doing */ | |
773 | hs_ep->req = hs_req; | |
774 | ||
775 | /* write size / packets */ | |
776 | writel(epsize, hsotg->regs + epsize_reg); | |
777 | ||
db1d8ba3 | 778 | if (using_dma(hsotg) && !continuing) { |
5b7d70c6 BD |
779 | unsigned int dma_reg; |
780 | ||
8b9bc460 LM |
781 | /* |
782 | * write DMA address to control register, buffer already | |
783 | * synced by s3c_hsotg_ep_queue(). | |
784 | */ | |
5b7d70c6 | 785 | |
94cb8fd6 | 786 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
5b7d70c6 BD |
787 | writel(ureq->dma, hsotg->regs + dma_reg); |
788 | ||
789 | dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n", | |
790 | __func__, ureq->dma, dma_reg); | |
791 | } | |
792 | ||
94cb8fd6 LM |
793 | ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */ |
794 | ctrl |= DxEPCTL_USBActEp; | |
71225bee LM |
795 | |
796 | dev_dbg(hsotg->dev, "setup req:%d\n", hsotg->setup); | |
797 | ||
798 | /* For Setup request do not clear NAK */ | |
799 | if (hsotg->setup && index == 0) | |
800 | hsotg->setup = 0; | |
801 | else | |
94cb8fd6 | 802 | ctrl |= DxEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 803 | |
5b7d70c6 BD |
804 | |
805 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
806 | writel(ctrl, hsotg->regs + epctrl_reg); | |
807 | ||
8b9bc460 LM |
808 | /* |
809 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 810 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
811 | * this information. |
812 | */ | |
5b7d70c6 BD |
813 | hs_ep->size_loaded = length; |
814 | hs_ep->last_load = ureq->actual; | |
815 | ||
816 | if (dir_in && !using_dma(hsotg)) { | |
817 | /* set these anyway, we may need them for non-periodic in */ | |
818 | hs_ep->fifo_load = 0; | |
819 | ||
820 | s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req); | |
821 | } | |
822 | ||
8b9bc460 LM |
823 | /* |
824 | * clear the INTknTXFEmpMsk when we start request, more as a aide | |
825 | * to debugging to see what is going on. | |
826 | */ | |
5b7d70c6 | 827 | if (dir_in) |
94cb8fd6 LM |
828 | writel(DIEPMSK_INTknTXFEmpMsk, |
829 | hsotg->regs + DIEPINT(index)); | |
5b7d70c6 | 830 | |
8b9bc460 LM |
831 | /* |
832 | * Note, trying to clear the NAK here causes problems with transmit | |
833 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
834 | */ | |
5b7d70c6 BD |
835 | |
836 | /* check ep is enabled */ | |
94cb8fd6 | 837 | if (!(readl(hsotg->regs + epctrl_reg) & DxEPCTL_EPEna)) |
5b7d70c6 BD |
838 | dev_warn(hsotg->dev, |
839 | "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n", | |
840 | index, readl(hsotg->regs + epctrl_reg)); | |
841 | ||
842 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", | |
843 | __func__, readl(hsotg->regs + epctrl_reg)); | |
afcf4169 RB |
844 | |
845 | /* enable ep interrupts */ | |
846 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); | |
5b7d70c6 BD |
847 | } |
848 | ||
849 | /** | |
850 | * s3c_hsotg_map_dma - map the DMA memory being used for the request | |
851 | * @hsotg: The device state. | |
852 | * @hs_ep: The endpoint the request is on. | |
853 | * @req: The request being processed. | |
854 | * | |
855 | * We've been asked to queue a request, so ensure that the memory buffer | |
856 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
857 | * then ensure the buffer has been synced to memory. If our buffer has no | |
858 | * DMA memory, then we map the memory and mark our request to allow us to | |
859 | * cleanup on completion. | |
8b9bc460 | 860 | */ |
5b7d70c6 BD |
861 | static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg, |
862 | struct s3c_hsotg_ep *hs_ep, | |
863 | struct usb_request *req) | |
864 | { | |
5b7d70c6 | 865 | struct s3c_hsotg_req *hs_req = our_req(req); |
e58ebcd1 | 866 | int ret; |
5b7d70c6 BD |
867 | |
868 | /* if the length is zero, ignore the DMA data */ | |
869 | if (hs_req->req.length == 0) | |
870 | return 0; | |
871 | ||
e58ebcd1 FB |
872 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
873 | if (ret) | |
874 | goto dma_error; | |
5b7d70c6 BD |
875 | |
876 | return 0; | |
877 | ||
878 | dma_error: | |
879 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
880 | __func__, req->buf, req->length); | |
881 | ||
882 | return -EIO; | |
883 | } | |
884 | ||
885 | static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, | |
886 | gfp_t gfp_flags) | |
887 | { | |
888 | struct s3c_hsotg_req *hs_req = our_req(req); | |
889 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
890 | struct s3c_hsotg *hs = hs_ep->parent; | |
5b7d70c6 BD |
891 | bool first; |
892 | ||
893 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
894 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
895 | req->zero, req->short_not_ok); | |
896 | ||
897 | /* initialise status of the request */ | |
898 | INIT_LIST_HEAD(&hs_req->queue); | |
899 | req->actual = 0; | |
900 | req->status = -EINPROGRESS; | |
901 | ||
902 | /* if we're using DMA, sync the buffers as necessary */ | |
903 | if (using_dma(hs)) { | |
904 | int ret = s3c_hsotg_map_dma(hs, hs_ep, req); | |
905 | if (ret) | |
906 | return ret; | |
907 | } | |
908 | ||
5b7d70c6 BD |
909 | first = list_empty(&hs_ep->queue); |
910 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
911 | ||
912 | if (first) | |
913 | s3c_hsotg_start_req(hs, hs_ep, hs_req, false); | |
914 | ||
5b7d70c6 BD |
915 | return 0; |
916 | } | |
917 | ||
5ad1d316 LM |
918 | static int s3c_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
919 | gfp_t gfp_flags) | |
920 | { | |
921 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
922 | struct s3c_hsotg *hs = hs_ep->parent; | |
923 | unsigned long flags = 0; | |
924 | int ret = 0; | |
925 | ||
926 | spin_lock_irqsave(&hs->lock, flags); | |
927 | ret = s3c_hsotg_ep_queue(ep, req, gfp_flags); | |
928 | spin_unlock_irqrestore(&hs->lock, flags); | |
929 | ||
930 | return ret; | |
931 | } | |
932 | ||
5b7d70c6 BD |
933 | static void s3c_hsotg_ep_free_request(struct usb_ep *ep, |
934 | struct usb_request *req) | |
935 | { | |
936 | struct s3c_hsotg_req *hs_req = our_req(req); | |
937 | ||
938 | kfree(hs_req); | |
939 | } | |
940 | ||
941 | /** | |
942 | * s3c_hsotg_complete_oursetup - setup completion callback | |
943 | * @ep: The endpoint the request was on. | |
944 | * @req: The request completed. | |
945 | * | |
946 | * Called on completion of any requests the driver itself | |
947 | * submitted that need cleaning up. | |
948 | */ | |
949 | static void s3c_hsotg_complete_oursetup(struct usb_ep *ep, | |
950 | struct usb_request *req) | |
951 | { | |
952 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
953 | struct s3c_hsotg *hsotg = hs_ep->parent; | |
954 | ||
955 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
956 | ||
957 | s3c_hsotg_ep_free_request(ep, req); | |
958 | } | |
959 | ||
960 | /** | |
961 | * ep_from_windex - convert control wIndex value to endpoint | |
962 | * @hsotg: The driver state. | |
963 | * @windex: The control request wIndex field (in host order). | |
964 | * | |
965 | * Convert the given wIndex into a pointer to an driver endpoint | |
966 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 967 | */ |
5b7d70c6 BD |
968 | static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg, |
969 | u32 windex) | |
970 | { | |
971 | struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F]; | |
972 | int dir = (windex & USB_DIR_IN) ? 1 : 0; | |
973 | int idx = windex & 0x7F; | |
974 | ||
975 | if (windex >= 0x100) | |
976 | return NULL; | |
977 | ||
b3f489b2 | 978 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
979 | return NULL; |
980 | ||
981 | if (idx && ep->dir_in != dir) | |
982 | return NULL; | |
983 | ||
984 | return ep; | |
985 | } | |
986 | ||
987 | /** | |
988 | * s3c_hsotg_send_reply - send reply to control request | |
989 | * @hsotg: The device state | |
990 | * @ep: Endpoint 0 | |
991 | * @buff: Buffer for request | |
992 | * @length: Length of reply. | |
993 | * | |
994 | * Create a request and queue it on the given endpoint. This is useful as | |
995 | * an internal method of sending replies to certain control requests, etc. | |
996 | */ | |
997 | static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg, | |
998 | struct s3c_hsotg_ep *ep, | |
999 | void *buff, | |
1000 | int length) | |
1001 | { | |
1002 | struct usb_request *req; | |
1003 | int ret; | |
1004 | ||
1005 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
1006 | ||
1007 | req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); | |
1008 | hsotg->ep0_reply = req; | |
1009 | if (!req) { | |
1010 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
1011 | return -ENOMEM; | |
1012 | } | |
1013 | ||
1014 | req->buf = hsotg->ep0_buff; | |
1015 | req->length = length; | |
1016 | req->zero = 1; /* always do zero-length final transfer */ | |
1017 | req->complete = s3c_hsotg_complete_oursetup; | |
1018 | ||
1019 | if (length) | |
1020 | memcpy(req->buf, buff, length); | |
1021 | else | |
1022 | ep->sent_zlp = 1; | |
1023 | ||
1024 | ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); | |
1025 | if (ret) { | |
1026 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
1027 | return ret; | |
1028 | } | |
1029 | ||
1030 | return 0; | |
1031 | } | |
1032 | ||
1033 | /** | |
1034 | * s3c_hsotg_process_req_status - process request GET_STATUS | |
1035 | * @hsotg: The device state | |
1036 | * @ctrl: USB control request | |
1037 | */ | |
1038 | static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg, | |
1039 | struct usb_ctrlrequest *ctrl) | |
1040 | { | |
1041 | struct s3c_hsotg_ep *ep0 = &hsotg->eps[0]; | |
1042 | struct s3c_hsotg_ep *ep; | |
1043 | __le16 reply; | |
1044 | int ret; | |
1045 | ||
1046 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
1047 | ||
1048 | if (!ep0->dir_in) { | |
1049 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
1050 | return -EINVAL; | |
1051 | } | |
1052 | ||
1053 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
1054 | case USB_RECIP_DEVICE: | |
1055 | reply = cpu_to_le16(0); /* bit 0 => self powered, | |
1056 | * bit 1 => remote wakeup */ | |
1057 | break; | |
1058 | ||
1059 | case USB_RECIP_INTERFACE: | |
1060 | /* currently, the data result should be zero */ | |
1061 | reply = cpu_to_le16(0); | |
1062 | break; | |
1063 | ||
1064 | case USB_RECIP_ENDPOINT: | |
1065 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1066 | if (!ep) | |
1067 | return -ENOENT; | |
1068 | ||
1069 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
1070 | break; | |
1071 | ||
1072 | default: | |
1073 | return 0; | |
1074 | } | |
1075 | ||
1076 | if (le16_to_cpu(ctrl->wLength) != 2) | |
1077 | return -EINVAL; | |
1078 | ||
1079 | ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2); | |
1080 | if (ret) { | |
1081 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
1082 | return ret; | |
1083 | } | |
1084 | ||
1085 | return 1; | |
1086 | } | |
1087 | ||
1088 | static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value); | |
1089 | ||
9c39ddc6 AT |
1090 | /** |
1091 | * get_ep_head - return the first request on the endpoint | |
1092 | * @hs_ep: The controller endpoint to get | |
1093 | * | |
1094 | * Get the first request on the endpoint. | |
1095 | */ | |
1096 | static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep) | |
1097 | { | |
1098 | if (list_empty(&hs_ep->queue)) | |
1099 | return NULL; | |
1100 | ||
1101 | return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue); | |
1102 | } | |
1103 | ||
5b7d70c6 BD |
1104 | /** |
1105 | * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE | |
1106 | * @hsotg: The device state | |
1107 | * @ctrl: USB control request | |
1108 | */ | |
1109 | static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg, | |
1110 | struct usb_ctrlrequest *ctrl) | |
1111 | { | |
26ab3d0c | 1112 | struct s3c_hsotg_ep *ep0 = &hsotg->eps[0]; |
9c39ddc6 AT |
1113 | struct s3c_hsotg_req *hs_req; |
1114 | bool restart; | |
5b7d70c6 BD |
1115 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
1116 | struct s3c_hsotg_ep *ep; | |
26ab3d0c | 1117 | int ret; |
5b7d70c6 BD |
1118 | |
1119 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1120 | __func__, set ? "SET" : "CLEAR"); | |
1121 | ||
1122 | if (ctrl->bRequestType == USB_RECIP_ENDPOINT) { | |
1123 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1124 | if (!ep) { | |
1125 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
1126 | __func__, le16_to_cpu(ctrl->wIndex)); | |
1127 | return -ENOENT; | |
1128 | } | |
1129 | ||
1130 | switch (le16_to_cpu(ctrl->wValue)) { | |
1131 | case USB_ENDPOINT_HALT: | |
1132 | s3c_hsotg_ep_sethalt(&ep->ep, set); | |
26ab3d0c AT |
1133 | |
1134 | ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
1135 | if (ret) { | |
1136 | dev_err(hsotg->dev, | |
1137 | "%s: failed to send reply\n", __func__); | |
1138 | return ret; | |
1139 | } | |
9c39ddc6 AT |
1140 | |
1141 | if (!set) { | |
1142 | /* | |
1143 | * If we have request in progress, | |
1144 | * then complete it | |
1145 | */ | |
1146 | if (ep->req) { | |
1147 | hs_req = ep->req; | |
1148 | ep->req = NULL; | |
1149 | list_del_init(&hs_req->queue); | |
1150 | hs_req->req.complete(&ep->ep, | |
1151 | &hs_req->req); | |
1152 | } | |
1153 | ||
1154 | /* If we have pending request, then start it */ | |
1155 | restart = !list_empty(&ep->queue); | |
1156 | if (restart) { | |
1157 | hs_req = get_ep_head(ep); | |
1158 | s3c_hsotg_start_req(hsotg, ep, | |
1159 | hs_req, false); | |
1160 | } | |
1161 | } | |
1162 | ||
5b7d70c6 BD |
1163 | break; |
1164 | ||
1165 | default: | |
1166 | return -ENOENT; | |
1167 | } | |
1168 | } else | |
1169 | return -ENOENT; /* currently only deal with endpoint */ | |
1170 | ||
1171 | return 1; | |
1172 | } | |
1173 | ||
ab93e014 RB |
1174 | static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg); |
1175 | ||
5b7d70c6 BD |
1176 | /** |
1177 | * s3c_hsotg_process_control - process a control request | |
1178 | * @hsotg: The device state | |
1179 | * @ctrl: The control request received | |
1180 | * | |
1181 | * The controller has received the SETUP phase of a control request, and | |
1182 | * needs to work out what to do next (and whether to pass it on to the | |
1183 | * gadget driver). | |
1184 | */ | |
1185 | static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg, | |
1186 | struct usb_ctrlrequest *ctrl) | |
1187 | { | |
1188 | struct s3c_hsotg_ep *ep0 = &hsotg->eps[0]; | |
1189 | int ret = 0; | |
1190 | u32 dcfg; | |
1191 | ||
1192 | ep0->sent_zlp = 0; | |
1193 | ||
1194 | dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n", | |
1195 | ctrl->bRequest, ctrl->bRequestType, | |
1196 | ctrl->wValue, ctrl->wLength); | |
1197 | ||
8b9bc460 LM |
1198 | /* |
1199 | * record the direction of the request, for later use when enquing | |
1200 | * packets onto EP0. | |
1201 | */ | |
5b7d70c6 BD |
1202 | |
1203 | ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0; | |
1204 | dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in); | |
1205 | ||
8b9bc460 LM |
1206 | /* |
1207 | * if we've no data with this request, then the last part of the | |
1208 | * transaction is going to implicitly be IN. | |
1209 | */ | |
5b7d70c6 BD |
1210 | if (ctrl->wLength == 0) |
1211 | ep0->dir_in = 1; | |
1212 | ||
1213 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1214 | switch (ctrl->bRequest) { | |
1215 | case USB_REQ_SET_ADDRESS: | |
94cb8fd6 LM |
1216 | dcfg = readl(hsotg->regs + DCFG); |
1217 | dcfg &= ~DCFG_DevAddr_MASK; | |
1218 | dcfg |= ctrl->wValue << DCFG_DevAddr_SHIFT; | |
1219 | writel(dcfg, hsotg->regs + DCFG); | |
5b7d70c6 BD |
1220 | |
1221 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1222 | ||
1223 | ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
1224 | return; | |
1225 | ||
1226 | case USB_REQ_GET_STATUS: | |
1227 | ret = s3c_hsotg_process_req_status(hsotg, ctrl); | |
1228 | break; | |
1229 | ||
1230 | case USB_REQ_CLEAR_FEATURE: | |
1231 | case USB_REQ_SET_FEATURE: | |
1232 | ret = s3c_hsotg_process_req_feature(hsotg, ctrl); | |
1233 | break; | |
1234 | } | |
1235 | } | |
1236 | ||
1237 | /* as a fallback, try delivering it to the driver to deal with */ | |
1238 | ||
1239 | if (ret == 0 && hsotg->driver) { | |
1240 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); | |
1241 | if (ret < 0) | |
1242 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1243 | } | |
1244 | ||
8b9bc460 LM |
1245 | /* |
1246 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1247 | * so respond with a STALL for the status stage to indicate failure. |
1248 | */ | |
1249 | ||
1250 | if (ret < 0) { | |
1251 | u32 reg; | |
1252 | u32 ctrl; | |
1253 | ||
1254 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
94cb8fd6 | 1255 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; |
5b7d70c6 | 1256 | |
8b9bc460 | 1257 | /* |
94cb8fd6 | 1258 | * DxEPCTL_Stall will be cleared by EP once it has |
8b9bc460 LM |
1259 | * taken effect, so no need to clear later. |
1260 | */ | |
5b7d70c6 BD |
1261 | |
1262 | ctrl = readl(hsotg->regs + reg); | |
94cb8fd6 LM |
1263 | ctrl |= DxEPCTL_Stall; |
1264 | ctrl |= DxEPCTL_CNAK; | |
5b7d70c6 BD |
1265 | writel(ctrl, hsotg->regs + reg); |
1266 | ||
1267 | dev_dbg(hsotg->dev, | |
25985edc | 1268 | "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n", |
5b7d70c6 BD |
1269 | ctrl, reg, readl(hsotg->regs + reg)); |
1270 | ||
8b9bc460 LM |
1271 | /* |
1272 | * don't believe we need to anything more to get the EP | |
1273 | * to reply with a STALL packet | |
1274 | */ | |
ab93e014 RB |
1275 | |
1276 | /* | |
1277 | * complete won't be called, so we enqueue | |
1278 | * setup request here | |
1279 | */ | |
1280 | s3c_hsotg_enqueue_setup(hsotg); | |
5b7d70c6 BD |
1281 | } |
1282 | } | |
1283 | ||
5b7d70c6 BD |
1284 | /** |
1285 | * s3c_hsotg_complete_setup - completion of a setup transfer | |
1286 | * @ep: The endpoint the request was on. | |
1287 | * @req: The request completed. | |
1288 | * | |
1289 | * Called on completion of any requests the driver itself submitted for | |
1290 | * EP0 setup packets | |
1291 | */ | |
1292 | static void s3c_hsotg_complete_setup(struct usb_ep *ep, | |
1293 | struct usb_request *req) | |
1294 | { | |
1295 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
1296 | struct s3c_hsotg *hsotg = hs_ep->parent; | |
1297 | ||
1298 | if (req->status < 0) { | |
1299 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1300 | return; | |
1301 | } | |
1302 | ||
1303 | if (req->actual == 0) | |
1304 | s3c_hsotg_enqueue_setup(hsotg); | |
1305 | else | |
1306 | s3c_hsotg_process_control(hsotg, req->buf); | |
1307 | } | |
1308 | ||
1309 | /** | |
1310 | * s3c_hsotg_enqueue_setup - start a request for EP0 packets | |
1311 | * @hsotg: The device state. | |
1312 | * | |
1313 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1314 | * received from the host. | |
1315 | */ | |
1316 | static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg) | |
1317 | { | |
1318 | struct usb_request *req = hsotg->ctrl_req; | |
1319 | struct s3c_hsotg_req *hs_req = our_req(req); | |
1320 | int ret; | |
1321 | ||
1322 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1323 | ||
1324 | req->zero = 0; | |
1325 | req->length = 8; | |
1326 | req->buf = hsotg->ctrl_buff; | |
1327 | req->complete = s3c_hsotg_complete_setup; | |
1328 | ||
1329 | if (!list_empty(&hs_req->queue)) { | |
1330 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1331 | return; | |
1332 | } | |
1333 | ||
1334 | hsotg->eps[0].dir_in = 0; | |
1335 | ||
1336 | ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC); | |
1337 | if (ret < 0) { | |
1338 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
1339 | /* |
1340 | * Don't think there's much we can do other than watch the | |
1341 | * driver fail. | |
1342 | */ | |
5b7d70c6 BD |
1343 | } |
1344 | } | |
1345 | ||
5b7d70c6 BD |
1346 | /** |
1347 | * s3c_hsotg_complete_request - complete a request given to us | |
1348 | * @hsotg: The device state. | |
1349 | * @hs_ep: The endpoint the request was on. | |
1350 | * @hs_req: The request to complete. | |
1351 | * @result: The result code (0 => Ok, otherwise errno) | |
1352 | * | |
1353 | * The given request has finished, so call the necessary completion | |
1354 | * if it has one and then look to see if we can start a new request | |
1355 | * on the endpoint. | |
1356 | * | |
1357 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 1358 | */ |
5b7d70c6 BD |
1359 | static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg, |
1360 | struct s3c_hsotg_ep *hs_ep, | |
1361 | struct s3c_hsotg_req *hs_req, | |
1362 | int result) | |
1363 | { | |
1364 | bool restart; | |
1365 | ||
1366 | if (!hs_req) { | |
1367 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
1368 | return; | |
1369 | } | |
1370 | ||
1371 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
1372 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
1373 | ||
8b9bc460 LM |
1374 | /* |
1375 | * only replace the status if we've not already set an error | |
1376 | * from a previous transaction | |
1377 | */ | |
5b7d70c6 BD |
1378 | |
1379 | if (hs_req->req.status == -EINPROGRESS) | |
1380 | hs_req->req.status = result; | |
1381 | ||
1382 | hs_ep->req = NULL; | |
1383 | list_del_init(&hs_req->queue); | |
1384 | ||
1385 | if (using_dma(hsotg)) | |
1386 | s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
1387 | ||
8b9bc460 LM |
1388 | /* |
1389 | * call the complete request with the locks off, just in case the | |
1390 | * request tries to queue more work for this endpoint. | |
1391 | */ | |
5b7d70c6 BD |
1392 | |
1393 | if (hs_req->req.complete) { | |
22258f49 | 1394 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1395 | hs_req->req.complete(&hs_ep->ep, &hs_req->req); |
22258f49 | 1396 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1397 | } |
1398 | ||
8b9bc460 LM |
1399 | /* |
1400 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 1401 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
1402 | * so be careful when doing this. |
1403 | */ | |
5b7d70c6 BD |
1404 | |
1405 | if (!hs_ep->req && result >= 0) { | |
1406 | restart = !list_empty(&hs_ep->queue); | |
1407 | if (restart) { | |
1408 | hs_req = get_ep_head(hs_ep); | |
1409 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1410 | } | |
1411 | } | |
1412 | } | |
1413 | ||
5b7d70c6 BD |
1414 | /** |
1415 | * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint | |
1416 | * @hsotg: The device state. | |
1417 | * @ep_idx: The endpoint index for the data | |
1418 | * @size: The size of data in the fifo, in bytes | |
1419 | * | |
1420 | * The FIFO status shows there is data to read from the FIFO for a given | |
1421 | * endpoint, so sort out whether we need to read the data into a request | |
1422 | * that has been made for that endpoint. | |
1423 | */ | |
1424 | static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size) | |
1425 | { | |
1426 | struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx]; | |
1427 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
94cb8fd6 | 1428 | void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); |
5b7d70c6 BD |
1429 | int to_read; |
1430 | int max_req; | |
1431 | int read_ptr; | |
1432 | ||
22258f49 | 1433 | |
5b7d70c6 | 1434 | if (!hs_req) { |
94cb8fd6 | 1435 | u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx)); |
5b7d70c6 BD |
1436 | int ptr; |
1437 | ||
1438 | dev_warn(hsotg->dev, | |
1439 | "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n", | |
1440 | __func__, size, ep_idx, epctl); | |
1441 | ||
1442 | /* dump the data from the FIFO, we've nothing we can do */ | |
1443 | for (ptr = 0; ptr < size; ptr += 4) | |
1444 | (void)readl(fifo); | |
1445 | ||
1446 | return; | |
1447 | } | |
1448 | ||
5b7d70c6 BD |
1449 | to_read = size; |
1450 | read_ptr = hs_req->req.actual; | |
1451 | max_req = hs_req->req.length - read_ptr; | |
1452 | ||
a33e7136 BD |
1453 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
1454 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
1455 | ||
5b7d70c6 | 1456 | if (to_read > max_req) { |
8b9bc460 LM |
1457 | /* |
1458 | * more data appeared than we where willing | |
5b7d70c6 BD |
1459 | * to deal with in this request. |
1460 | */ | |
1461 | ||
1462 | /* currently we don't deal this */ | |
1463 | WARN_ON_ONCE(1); | |
1464 | } | |
1465 | ||
5b7d70c6 BD |
1466 | hs_ep->total_data += to_read; |
1467 | hs_req->req.actual += to_read; | |
1468 | to_read = DIV_ROUND_UP(to_read, 4); | |
1469 | ||
8b9bc460 LM |
1470 | /* |
1471 | * note, we might over-write the buffer end by 3 bytes depending on | |
1472 | * alignment of the data. | |
1473 | */ | |
5b7d70c6 | 1474 | readsl(fifo, hs_req->req.buf + read_ptr, to_read); |
5b7d70c6 BD |
1475 | } |
1476 | ||
1477 | /** | |
1478 | * s3c_hsotg_send_zlp - send zero-length packet on control endpoint | |
1479 | * @hsotg: The device instance | |
1480 | * @req: The request currently on this endpoint | |
1481 | * | |
1482 | * Generate a zero-length IN packet request for terminating a SETUP | |
1483 | * transaction. | |
1484 | * | |
1485 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 1486 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
1487 | * the TxFIFO. |
1488 | */ | |
1489 | static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg, | |
1490 | struct s3c_hsotg_req *req) | |
1491 | { | |
1492 | u32 ctrl; | |
1493 | ||
1494 | if (!req) { | |
1495 | dev_warn(hsotg->dev, "%s: no request?\n", __func__); | |
1496 | return; | |
1497 | } | |
1498 | ||
1499 | if (req->req.length == 0) { | |
1500 | hsotg->eps[0].sent_zlp = 1; | |
1501 | s3c_hsotg_enqueue_setup(hsotg); | |
1502 | return; | |
1503 | } | |
1504 | ||
1505 | hsotg->eps[0].dir_in = 1; | |
1506 | hsotg->eps[0].sent_zlp = 1; | |
1507 | ||
1508 | dev_dbg(hsotg->dev, "sending zero-length packet\n"); | |
1509 | ||
1510 | /* issue a zero-sized packet to terminate this */ | |
94cb8fd6 LM |
1511 | writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) | |
1512 | DxEPTSIZ_XferSize(0), hsotg->regs + DIEPTSIZ(0)); | |
5b7d70c6 | 1513 | |
94cb8fd6 LM |
1514 | ctrl = readl(hsotg->regs + DIEPCTL0); |
1515 | ctrl |= DxEPCTL_CNAK; /* clear NAK set by core */ | |
1516 | ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */ | |
1517 | ctrl |= DxEPCTL_USBActEp; | |
1518 | writel(ctrl, hsotg->regs + DIEPCTL0); | |
5b7d70c6 BD |
1519 | } |
1520 | ||
1521 | /** | |
1522 | * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO | |
1523 | * @hsotg: The device instance | |
1524 | * @epnum: The endpoint received from | |
1525 | * @was_setup: Set if processing a SetupDone event. | |
1526 | * | |
1527 | * The RXFIFO has delivered an OutDone event, which means that the data | |
1528 | * transfer for an OUT endpoint has been completed, either by a short | |
1529 | * packet or by the finish of a transfer. | |
8b9bc460 | 1530 | */ |
5b7d70c6 BD |
1531 | static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg, |
1532 | int epnum, bool was_setup) | |
1533 | { | |
94cb8fd6 | 1534 | u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum)); |
5b7d70c6 BD |
1535 | struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum]; |
1536 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
1537 | struct usb_request *req = &hs_req->req; | |
94cb8fd6 | 1538 | unsigned size_left = DxEPTSIZ_XferSize_GET(epsize); |
5b7d70c6 BD |
1539 | int result = 0; |
1540 | ||
1541 | if (!hs_req) { | |
1542 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
1543 | return; | |
1544 | } | |
1545 | ||
1546 | if (using_dma(hsotg)) { | |
5b7d70c6 | 1547 | unsigned size_done; |
5b7d70c6 | 1548 | |
8b9bc460 LM |
1549 | /* |
1550 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
1551 | * is left in the endpoint size register and then working it |
1552 | * out from the amount we loaded for the transfer. | |
1553 | * | |
1554 | * We need to do this as DMA pointers are always 32bit aligned | |
1555 | * so may overshoot/undershoot the transfer. | |
1556 | */ | |
1557 | ||
5b7d70c6 BD |
1558 | size_done = hs_ep->size_loaded - size_left; |
1559 | size_done += hs_ep->last_load; | |
1560 | ||
1561 | req->actual = size_done; | |
1562 | } | |
1563 | ||
a33e7136 BD |
1564 | /* if there is more request to do, schedule new transfer */ |
1565 | if (req->actual < req->length && size_left == 0) { | |
1566 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true); | |
1567 | return; | |
71225bee LM |
1568 | } else if (epnum == 0) { |
1569 | /* | |
1570 | * After was_setup = 1 => | |
1571 | * set CNAK for non Setup requests | |
1572 | */ | |
1573 | hsotg->setup = was_setup ? 0 : 1; | |
a33e7136 BD |
1574 | } |
1575 | ||
5b7d70c6 BD |
1576 | if (req->actual < req->length && req->short_not_ok) { |
1577 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
1578 | __func__, req->actual, req->length); | |
1579 | ||
8b9bc460 LM |
1580 | /* |
1581 | * todo - what should we return here? there's no one else | |
1582 | * even bothering to check the status. | |
1583 | */ | |
5b7d70c6 BD |
1584 | } |
1585 | ||
1586 | if (epnum == 0) { | |
d3ca0259 LM |
1587 | /* |
1588 | * Condition req->complete != s3c_hsotg_complete_setup says: | |
1589 | * send ZLP when we have an asynchronous request from gadget | |
1590 | */ | |
5b7d70c6 BD |
1591 | if (!was_setup && req->complete != s3c_hsotg_complete_setup) |
1592 | s3c_hsotg_send_zlp(hsotg, hs_req); | |
1593 | } | |
1594 | ||
5ad1d316 | 1595 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
1596 | } |
1597 | ||
1598 | /** | |
1599 | * s3c_hsotg_read_frameno - read current frame number | |
1600 | * @hsotg: The device instance | |
1601 | * | |
1602 | * Return the current frame number | |
8b9bc460 | 1603 | */ |
5b7d70c6 BD |
1604 | static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg) |
1605 | { | |
1606 | u32 dsts; | |
1607 | ||
94cb8fd6 LM |
1608 | dsts = readl(hsotg->regs + DSTS); |
1609 | dsts &= DSTS_SOFFN_MASK; | |
1610 | dsts >>= DSTS_SOFFN_SHIFT; | |
5b7d70c6 BD |
1611 | |
1612 | return dsts; | |
1613 | } | |
1614 | ||
1615 | /** | |
1616 | * s3c_hsotg_handle_rx - RX FIFO has data | |
1617 | * @hsotg: The device instance | |
1618 | * | |
1619 | * The IRQ handler has detected that the RX FIFO has some data in it | |
1620 | * that requires processing, so find out what is in there and do the | |
1621 | * appropriate read. | |
1622 | * | |
25985edc | 1623 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
1624 | * chunks, so if you have x packets received on an endpoint you'll get x |
1625 | * FIFO events delivered, each with a packet's worth of data in it. | |
1626 | * | |
1627 | * When using DMA, we should not be processing events from the RXFIFO | |
1628 | * as the actual data should be sent to the memory directly and we turn | |
1629 | * on the completion interrupts to get notifications of transfer completion. | |
1630 | */ | |
0978f8c5 | 1631 | static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg) |
5b7d70c6 | 1632 | { |
94cb8fd6 | 1633 | u32 grxstsr = readl(hsotg->regs + GRXSTSP); |
5b7d70c6 BD |
1634 | u32 epnum, status, size; |
1635 | ||
1636 | WARN_ON(using_dma(hsotg)); | |
1637 | ||
94cb8fd6 LM |
1638 | epnum = grxstsr & GRXSTS_EPNum_MASK; |
1639 | status = grxstsr & GRXSTS_PktSts_MASK; | |
5b7d70c6 | 1640 | |
94cb8fd6 LM |
1641 | size = grxstsr & GRXSTS_ByteCnt_MASK; |
1642 | size >>= GRXSTS_ByteCnt_SHIFT; | |
5b7d70c6 BD |
1643 | |
1644 | if (1) | |
1645 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", | |
1646 | __func__, grxstsr, size, epnum); | |
1647 | ||
94cb8fd6 | 1648 | #define __status(x) ((x) >> GRXSTS_PktSts_SHIFT) |
5b7d70c6 | 1649 | |
94cb8fd6 LM |
1650 | switch (status >> GRXSTS_PktSts_SHIFT) { |
1651 | case __status(GRXSTS_PktSts_GlobalOutNAK): | |
5b7d70c6 BD |
1652 | dev_dbg(hsotg->dev, "GlobalOutNAK\n"); |
1653 | break; | |
1654 | ||
94cb8fd6 | 1655 | case __status(GRXSTS_PktSts_OutDone): |
5b7d70c6 BD |
1656 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1657 | s3c_hsotg_read_frameno(hsotg)); | |
1658 | ||
1659 | if (!using_dma(hsotg)) | |
1660 | s3c_hsotg_handle_outdone(hsotg, epnum, false); | |
1661 | break; | |
1662 | ||
94cb8fd6 | 1663 | case __status(GRXSTS_PktSts_SetupDone): |
5b7d70c6 BD |
1664 | dev_dbg(hsotg->dev, |
1665 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1666 | s3c_hsotg_read_frameno(hsotg), | |
94cb8fd6 | 1667 | readl(hsotg->regs + DOEPCTL(0))); |
5b7d70c6 BD |
1668 | |
1669 | s3c_hsotg_handle_outdone(hsotg, epnum, true); | |
1670 | break; | |
1671 | ||
94cb8fd6 | 1672 | case __status(GRXSTS_PktSts_OutRX): |
5b7d70c6 BD |
1673 | s3c_hsotg_rx_data(hsotg, epnum, size); |
1674 | break; | |
1675 | ||
94cb8fd6 | 1676 | case __status(GRXSTS_PktSts_SetupRX): |
5b7d70c6 BD |
1677 | dev_dbg(hsotg->dev, |
1678 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1679 | s3c_hsotg_read_frameno(hsotg), | |
94cb8fd6 | 1680 | readl(hsotg->regs + DOEPCTL(0))); |
5b7d70c6 BD |
1681 | |
1682 | s3c_hsotg_rx_data(hsotg, epnum, size); | |
1683 | break; | |
1684 | ||
1685 | default: | |
1686 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
1687 | __func__, grxstsr); | |
1688 | ||
1689 | s3c_hsotg_dump(hsotg); | |
1690 | break; | |
1691 | } | |
1692 | } | |
1693 | ||
1694 | /** | |
1695 | * s3c_hsotg_ep0_mps - turn max packet size into register setting | |
1696 | * @mps: The maximum packet size in bytes. | |
8b9bc460 | 1697 | */ |
5b7d70c6 BD |
1698 | static u32 s3c_hsotg_ep0_mps(unsigned int mps) |
1699 | { | |
1700 | switch (mps) { | |
1701 | case 64: | |
94cb8fd6 | 1702 | return D0EPCTL_MPS_64; |
5b7d70c6 | 1703 | case 32: |
94cb8fd6 | 1704 | return D0EPCTL_MPS_32; |
5b7d70c6 | 1705 | case 16: |
94cb8fd6 | 1706 | return D0EPCTL_MPS_16; |
5b7d70c6 | 1707 | case 8: |
94cb8fd6 | 1708 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
1709 | } |
1710 | ||
1711 | /* bad max packet size, warn and return invalid result */ | |
1712 | WARN_ON(1); | |
1713 | return (u32)-1; | |
1714 | } | |
1715 | ||
1716 | /** | |
1717 | * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field | |
1718 | * @hsotg: The driver state. | |
1719 | * @ep: The index number of the endpoint | |
1720 | * @mps: The maximum packet size in bytes | |
1721 | * | |
1722 | * Configure the maximum packet size for the given endpoint, updating | |
1723 | * the hardware control registers to reflect this. | |
1724 | */ | |
1725 | static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg, | |
1726 | unsigned int ep, unsigned int mps) | |
1727 | { | |
1728 | struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep]; | |
1729 | void __iomem *regs = hsotg->regs; | |
1730 | u32 mpsval; | |
4fca54aa | 1731 | u32 mcval; |
5b7d70c6 BD |
1732 | u32 reg; |
1733 | ||
1734 | if (ep == 0) { | |
1735 | /* EP0 is a special case */ | |
1736 | mpsval = s3c_hsotg_ep0_mps(mps); | |
1737 | if (mpsval > 3) | |
1738 | goto bad_mps; | |
e9edd199 | 1739 | hs_ep->ep.maxpacket = mps; |
4fca54aa | 1740 | hs_ep->mc = 1; |
5b7d70c6 | 1741 | } else { |
e9edd199 RB |
1742 | mpsval = mps & DxEPCTL_MPS_MASK; |
1743 | if (mpsval > 1024) | |
5b7d70c6 | 1744 | goto bad_mps; |
4fca54aa RB |
1745 | mcval = ((mps >> 11) & 0x3) + 1; |
1746 | hs_ep->mc = mcval; | |
1747 | if (mcval > 3) | |
1748 | goto bad_mps; | |
e9edd199 | 1749 | hs_ep->ep.maxpacket = mpsval; |
5b7d70c6 BD |
1750 | } |
1751 | ||
8b9bc460 LM |
1752 | /* |
1753 | * update both the in and out endpoint controldir_ registers, even | |
1754 | * if one of the directions may not be in use. | |
1755 | */ | |
5b7d70c6 | 1756 | |
94cb8fd6 LM |
1757 | reg = readl(regs + DIEPCTL(ep)); |
1758 | reg &= ~DxEPCTL_MPS_MASK; | |
5b7d70c6 | 1759 | reg |= mpsval; |
94cb8fd6 | 1760 | writel(reg, regs + DIEPCTL(ep)); |
5b7d70c6 | 1761 | |
659ad60c | 1762 | if (ep) { |
94cb8fd6 LM |
1763 | reg = readl(regs + DOEPCTL(ep)); |
1764 | reg &= ~DxEPCTL_MPS_MASK; | |
659ad60c | 1765 | reg |= mpsval; |
94cb8fd6 | 1766 | writel(reg, regs + DOEPCTL(ep)); |
659ad60c | 1767 | } |
5b7d70c6 BD |
1768 | |
1769 | return; | |
1770 | ||
1771 | bad_mps: | |
1772 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
1773 | } | |
1774 | ||
9c39ddc6 AT |
1775 | /** |
1776 | * s3c_hsotg_txfifo_flush - flush Tx FIFO | |
1777 | * @hsotg: The driver state | |
1778 | * @idx: The index for the endpoint (0..15) | |
1779 | */ | |
1780 | static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx) | |
1781 | { | |
1782 | int timeout; | |
1783 | int val; | |
1784 | ||
94cb8fd6 LM |
1785 | writel(GRSTCTL_TxFNum(idx) | GRSTCTL_TxFFlsh, |
1786 | hsotg->regs + GRSTCTL); | |
9c39ddc6 AT |
1787 | |
1788 | /* wait until the fifo is flushed */ | |
1789 | timeout = 100; | |
1790 | ||
1791 | while (1) { | |
94cb8fd6 | 1792 | val = readl(hsotg->regs + GRSTCTL); |
9c39ddc6 | 1793 | |
94cb8fd6 | 1794 | if ((val & (GRSTCTL_TxFFlsh)) == 0) |
9c39ddc6 AT |
1795 | break; |
1796 | ||
1797 | if (--timeout == 0) { | |
1798 | dev_err(hsotg->dev, | |
1799 | "%s: timeout flushing fifo (GRSTCTL=%08x)\n", | |
1800 | __func__, val); | |
1801 | } | |
1802 | ||
1803 | udelay(1); | |
1804 | } | |
1805 | } | |
5b7d70c6 BD |
1806 | |
1807 | /** | |
1808 | * s3c_hsotg_trytx - check to see if anything needs transmitting | |
1809 | * @hsotg: The driver state | |
1810 | * @hs_ep: The driver endpoint to check. | |
1811 | * | |
1812 | * Check to see if there is a request that has data to send, and if so | |
1813 | * make an attempt to write data into the FIFO. | |
1814 | */ | |
1815 | static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg, | |
1816 | struct s3c_hsotg_ep *hs_ep) | |
1817 | { | |
1818 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
1819 | ||
afcf4169 RB |
1820 | if (!hs_ep->dir_in || !hs_req) { |
1821 | /** | |
1822 | * if request is not enqueued, we disable interrupts | |
1823 | * for endpoints, excepting ep0 | |
1824 | */ | |
1825 | if (hs_ep->index != 0) | |
1826 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, | |
1827 | hs_ep->dir_in, 0); | |
5b7d70c6 | 1828 | return 0; |
afcf4169 | 1829 | } |
5b7d70c6 BD |
1830 | |
1831 | if (hs_req->req.actual < hs_req->req.length) { | |
1832 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
1833 | hs_ep->index); | |
1834 | return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req); | |
1835 | } | |
1836 | ||
1837 | return 0; | |
1838 | } | |
1839 | ||
1840 | /** | |
1841 | * s3c_hsotg_complete_in - complete IN transfer | |
1842 | * @hsotg: The device state. | |
1843 | * @hs_ep: The endpoint that has just completed. | |
1844 | * | |
1845 | * An IN transfer has been completed, update the transfer's state and then | |
1846 | * call the relevant completion routines. | |
1847 | */ | |
1848 | static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg, | |
1849 | struct s3c_hsotg_ep *hs_ep) | |
1850 | { | |
1851 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
94cb8fd6 | 1852 | u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
1853 | int size_left, size_done; |
1854 | ||
1855 | if (!hs_req) { | |
1856 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
1857 | return; | |
1858 | } | |
1859 | ||
d3ca0259 LM |
1860 | /* Finish ZLP handling for IN EP0 transactions */ |
1861 | if (hsotg->eps[0].sent_zlp) { | |
1862 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
5ad1d316 | 1863 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
d3ca0259 LM |
1864 | return; |
1865 | } | |
1866 | ||
8b9bc460 LM |
1867 | /* |
1868 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
1869 | * in the endpoint size register and then working it out from |
1870 | * the amount we loaded for the transfer. | |
1871 | * | |
1872 | * We do this even for DMA, as the transfer may have incremented | |
1873 | * past the end of the buffer (DMA transfers are always 32bit | |
1874 | * aligned). | |
1875 | */ | |
1876 | ||
94cb8fd6 | 1877 | size_left = DxEPTSIZ_XferSize_GET(epsize); |
5b7d70c6 BD |
1878 | |
1879 | size_done = hs_ep->size_loaded - size_left; | |
1880 | size_done += hs_ep->last_load; | |
1881 | ||
1882 | if (hs_req->req.actual != size_done) | |
1883 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
1884 | __func__, hs_req->req.actual, size_done); | |
1885 | ||
1886 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
1887 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
1888 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
1889 | ||
1890 | /* | |
1891 | * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0 | |
1892 | * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B | |
1893 | * ,256B ... ), after last MPS sized packet send IN ZLP packet to | |
1894 | * inform the host that no more data is available. | |
1895 | * The state of req.zero member is checked to be sure that the value to | |
1896 | * send is smaller than wValue expected from host. | |
1897 | * Check req.length to NOT send another ZLP when the current one is | |
1898 | * under completion (the one for which this completion has been called). | |
1899 | */ | |
1900 | if (hs_req->req.length && hs_ep->index == 0 && hs_req->req.zero && | |
1901 | hs_req->req.length == hs_req->req.actual && | |
1902 | !(hs_req->req.length % hs_ep->ep.maxpacket)) { | |
1903 | ||
1904 | dev_dbg(hsotg->dev, "ep0 zlp IN packet sent\n"); | |
1905 | s3c_hsotg_send_zlp(hsotg, hs_req); | |
5b7d70c6 | 1906 | |
d3ca0259 LM |
1907 | return; |
1908 | } | |
5b7d70c6 BD |
1909 | |
1910 | if (!size_left && hs_req->req.actual < hs_req->req.length) { | |
1911 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1912 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true); | |
1913 | } else | |
5ad1d316 | 1914 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
5b7d70c6 BD |
1915 | } |
1916 | ||
1917 | /** | |
1918 | * s3c_hsotg_epint - handle an in/out endpoint interrupt | |
1919 | * @hsotg: The driver state | |
1920 | * @idx: The index for the endpoint (0..15) | |
1921 | * @dir_in: Set if this is an IN endpoint | |
1922 | * | |
1923 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 1924 | */ |
5b7d70c6 BD |
1925 | static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx, |
1926 | int dir_in) | |
1927 | { | |
1928 | struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx]; | |
94cb8fd6 LM |
1929 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
1930 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
1931 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 1932 | u32 ints; |
1479e841 | 1933 | u32 ctrl; |
5b7d70c6 BD |
1934 | |
1935 | ints = readl(hsotg->regs + epint_reg); | |
1479e841 | 1936 | ctrl = readl(hsotg->regs + epctl_reg); |
5b7d70c6 | 1937 | |
a3395f0d AT |
1938 | /* Clear endpoint interrupts */ |
1939 | writel(ints, hsotg->regs + epint_reg); | |
1940 | ||
5b7d70c6 BD |
1941 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
1942 | __func__, idx, dir_in ? "in" : "out", ints); | |
1943 | ||
94cb8fd6 | 1944 | if (ints & DxEPINT_XferCompl) { |
1479e841 RB |
1945 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
1946 | if (ctrl & DxEPCTL_EOFrNum) | |
1947 | ctrl |= DxEPCTL_SetEvenFr; | |
1948 | else | |
1949 | ctrl |= DxEPCTL_SetOddFr; | |
1950 | writel(ctrl, hsotg->regs + epctl_reg); | |
1951 | } | |
1952 | ||
5b7d70c6 BD |
1953 | dev_dbg(hsotg->dev, |
1954 | "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n", | |
1955 | __func__, readl(hsotg->regs + epctl_reg), | |
1956 | readl(hsotg->regs + epsiz_reg)); | |
1957 | ||
8b9bc460 LM |
1958 | /* |
1959 | * we get OutDone from the FIFO, so we only need to look | |
1960 | * at completing IN requests here | |
1961 | */ | |
5b7d70c6 BD |
1962 | if (dir_in) { |
1963 | s3c_hsotg_complete_in(hsotg, hs_ep); | |
1964 | ||
c9a64ea8 | 1965 | if (idx == 0 && !hs_ep->req) |
5b7d70c6 BD |
1966 | s3c_hsotg_enqueue_setup(hsotg); |
1967 | } else if (using_dma(hsotg)) { | |
8b9bc460 LM |
1968 | /* |
1969 | * We're using DMA, we need to fire an OutDone here | |
1970 | * as we ignore the RXFIFO. | |
1971 | */ | |
5b7d70c6 BD |
1972 | |
1973 | s3c_hsotg_handle_outdone(hsotg, idx, false); | |
1974 | } | |
5b7d70c6 BD |
1975 | } |
1976 | ||
94cb8fd6 | 1977 | if (ints & DxEPINT_EPDisbld) { |
5b7d70c6 | 1978 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); |
5b7d70c6 | 1979 | |
9c39ddc6 AT |
1980 | if (dir_in) { |
1981 | int epctl = readl(hsotg->regs + epctl_reg); | |
1982 | ||
1983 | s3c_hsotg_txfifo_flush(hsotg, idx); | |
1984 | ||
94cb8fd6 LM |
1985 | if ((epctl & DxEPCTL_Stall) && |
1986 | (epctl & DxEPCTL_EPType_Bulk)) { | |
1987 | int dctl = readl(hsotg->regs + DCTL); | |
9c39ddc6 | 1988 | |
94cb8fd6 LM |
1989 | dctl |= DCTL_CGNPInNAK; |
1990 | writel(dctl, hsotg->regs + DCTL); | |
9c39ddc6 AT |
1991 | } |
1992 | } | |
1993 | } | |
1994 | ||
94cb8fd6 | 1995 | if (ints & DxEPINT_AHBErr) |
5b7d70c6 | 1996 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 1997 | |
94cb8fd6 | 1998 | if (ints & DxEPINT_Setup) { /* Setup or Timeout */ |
5b7d70c6 BD |
1999 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
2000 | ||
2001 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
2002 | /* |
2003 | * this is the notification we've received a | |
5b7d70c6 BD |
2004 | * setup packet. In non-DMA mode we'd get this |
2005 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
2006 | * the setup here. |
2007 | */ | |
5b7d70c6 BD |
2008 | |
2009 | if (dir_in) | |
2010 | WARN_ON_ONCE(1); | |
2011 | else | |
2012 | s3c_hsotg_handle_outdone(hsotg, 0, true); | |
2013 | } | |
5b7d70c6 BD |
2014 | } |
2015 | ||
94cb8fd6 | 2016 | if (ints & DxEPINT_Back2BackSetup) |
5b7d70c6 | 2017 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 2018 | |
1479e841 | 2019 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 2020 | /* not sure if this is important, but we'll clear it anyway */ |
94cb8fd6 | 2021 | if (ints & DIEPMSK_INTknTXFEmpMsk) { |
5b7d70c6 BD |
2022 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
2023 | __func__, idx); | |
5b7d70c6 BD |
2024 | } |
2025 | ||
2026 | /* this probably means something bad is happening */ | |
94cb8fd6 | 2027 | if (ints & DIEPMSK_INTknEPMisMsk) { |
5b7d70c6 BD |
2028 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
2029 | __func__, idx); | |
5b7d70c6 | 2030 | } |
10aebc77 BD |
2031 | |
2032 | /* FIFO has space or is empty (see GAHBCFG) */ | |
2033 | if (hsotg->dedicated_fifos && | |
94cb8fd6 | 2034 | ints & DIEPMSK_TxFIFOEmpty) { |
10aebc77 BD |
2035 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
2036 | __func__, idx); | |
70fa030f AT |
2037 | if (!using_dma(hsotg)) |
2038 | s3c_hsotg_trytx(hsotg, hs_ep); | |
10aebc77 | 2039 | } |
5b7d70c6 | 2040 | } |
5b7d70c6 BD |
2041 | } |
2042 | ||
2043 | /** | |
2044 | * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) | |
2045 | * @hsotg: The device state. | |
2046 | * | |
2047 | * Handle updating the device settings after the enumeration phase has | |
2048 | * been completed. | |
8b9bc460 | 2049 | */ |
5b7d70c6 BD |
2050 | static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg) |
2051 | { | |
94cb8fd6 | 2052 | u32 dsts = readl(hsotg->regs + DSTS); |
5b7d70c6 BD |
2053 | int ep0_mps = 0, ep_mps; |
2054 | ||
8b9bc460 LM |
2055 | /* |
2056 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 2057 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
2058 | * we connected at. |
2059 | */ | |
5b7d70c6 BD |
2060 | |
2061 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
2062 | ||
8b9bc460 LM |
2063 | /* |
2064 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 2065 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
2066 | * not advertise a 64byte MPS on EP0. |
2067 | */ | |
5b7d70c6 BD |
2068 | |
2069 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
94cb8fd6 LM |
2070 | switch (dsts & DSTS_EnumSpd_MASK) { |
2071 | case DSTS_EnumSpd_FS: | |
2072 | case DSTS_EnumSpd_FS48: | |
5b7d70c6 | 2073 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 BD |
2074 | ep0_mps = EP0_MPS_LIMIT; |
2075 | ep_mps = 64; | |
2076 | break; | |
2077 | ||
94cb8fd6 | 2078 | case DSTS_EnumSpd_HS: |
5b7d70c6 | 2079 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 BD |
2080 | ep0_mps = EP0_MPS_LIMIT; |
2081 | ep_mps = 512; | |
2082 | break; | |
2083 | ||
94cb8fd6 | 2084 | case DSTS_EnumSpd_LS: |
5b7d70c6 | 2085 | hsotg->gadget.speed = USB_SPEED_LOW; |
8b9bc460 LM |
2086 | /* |
2087 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
2088 | * moment, and the documentation seems to imply that it isn't |
2089 | * supported by the PHYs on some of the devices. | |
2090 | */ | |
2091 | break; | |
2092 | } | |
e538dfda MN |
2093 | dev_info(hsotg->dev, "new device is %s\n", |
2094 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 2095 | |
8b9bc460 LM |
2096 | /* |
2097 | * we should now know the maximum packet size for an | |
2098 | * endpoint, so set the endpoints to a default value. | |
2099 | */ | |
5b7d70c6 BD |
2100 | |
2101 | if (ep0_mps) { | |
2102 | int i; | |
2103 | s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps); | |
b3f489b2 | 2104 | for (i = 1; i < hsotg->num_of_eps; i++) |
5b7d70c6 BD |
2105 | s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps); |
2106 | } | |
2107 | ||
2108 | /* ensure after enumeration our EP0 is active */ | |
2109 | ||
2110 | s3c_hsotg_enqueue_setup(hsotg); | |
2111 | ||
2112 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
94cb8fd6 LM |
2113 | readl(hsotg->regs + DIEPCTL0), |
2114 | readl(hsotg->regs + DOEPCTL0)); | |
5b7d70c6 BD |
2115 | } |
2116 | ||
2117 | /** | |
2118 | * kill_all_requests - remove all requests from the endpoint's queue | |
2119 | * @hsotg: The device state. | |
2120 | * @ep: The endpoint the requests may be on. | |
2121 | * @result: The result code to use. | |
2122 | * @force: Force removal of any current requests | |
2123 | * | |
2124 | * Go through the requests on the given endpoint and mark them | |
2125 | * completed with the given result code. | |
2126 | */ | |
2127 | static void kill_all_requests(struct s3c_hsotg *hsotg, | |
2128 | struct s3c_hsotg_ep *ep, | |
2129 | int result, bool force) | |
2130 | { | |
2131 | struct s3c_hsotg_req *req, *treq; | |
5b7d70c6 BD |
2132 | |
2133 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
8b9bc460 LM |
2134 | /* |
2135 | * currently, we can't do much about an already | |
2136 | * running request on an in endpoint | |
2137 | */ | |
5b7d70c6 BD |
2138 | |
2139 | if (ep->req == req && ep->dir_in && !force) | |
2140 | continue; | |
2141 | ||
2142 | s3c_hsotg_complete_request(hsotg, ep, req, | |
2143 | result); | |
2144 | } | |
5b7d70c6 BD |
2145 | } |
2146 | ||
2147 | #define call_gadget(_hs, _entry) \ | |
a023da33 | 2148 | do { \ |
5b7d70c6 | 2149 | if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ |
5ad1d316 LM |
2150 | (_hs)->driver && (_hs)->driver->_entry) { \ |
2151 | spin_unlock(&_hs->lock); \ | |
2152 | (_hs)->driver->_entry(&(_hs)->gadget); \ | |
2153 | spin_lock(&_hs->lock); \ | |
a023da33 PM |
2154 | } \ |
2155 | } while (0) | |
5b7d70c6 BD |
2156 | |
2157 | /** | |
5e891342 | 2158 | * s3c_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
2159 | * @hsotg: The device state. |
2160 | * | |
5e891342 LM |
2161 | * The device has been disconnected. Remove all current |
2162 | * transactions and signal the gadget driver that this | |
2163 | * has happened. | |
8b9bc460 | 2164 | */ |
5e891342 | 2165 | static void s3c_hsotg_disconnect(struct s3c_hsotg *hsotg) |
5b7d70c6 BD |
2166 | { |
2167 | unsigned ep; | |
2168 | ||
b3f489b2 | 2169 | for (ep = 0; ep < hsotg->num_of_eps; ep++) |
5b7d70c6 BD |
2170 | kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true); |
2171 | ||
2172 | call_gadget(hsotg, disconnect); | |
2173 | } | |
2174 | ||
2175 | /** | |
2176 | * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler | |
2177 | * @hsotg: The device state: | |
2178 | * @periodic: True if this is a periodic FIFO interrupt | |
2179 | */ | |
2180 | static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic) | |
2181 | { | |
2182 | struct s3c_hsotg_ep *ep; | |
2183 | int epno, ret; | |
2184 | ||
2185 | /* look through for any more data to transmit */ | |
2186 | ||
b3f489b2 | 2187 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
5b7d70c6 BD |
2188 | ep = &hsotg->eps[epno]; |
2189 | ||
2190 | if (!ep->dir_in) | |
2191 | continue; | |
2192 | ||
2193 | if ((periodic && !ep->periodic) || | |
2194 | (!periodic && ep->periodic)) | |
2195 | continue; | |
2196 | ||
2197 | ret = s3c_hsotg_trytx(hsotg, ep); | |
2198 | if (ret < 0) | |
2199 | break; | |
2200 | } | |
2201 | } | |
2202 | ||
5b7d70c6 | 2203 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
94cb8fd6 LM |
2204 | #define IRQ_RETRY_MASK (GINTSTS_NPTxFEmp | \ |
2205 | GINTSTS_PTxFEmp | \ | |
2206 | GINTSTS_RxFLvl) | |
5b7d70c6 | 2207 | |
308d734e LM |
2208 | /** |
2209 | * s3c_hsotg_corereset - issue softreset to the core | |
2210 | * @hsotg: The device state | |
2211 | * | |
2212 | * Issue a soft reset to the core, and await the core finishing it. | |
8b9bc460 | 2213 | */ |
308d734e LM |
2214 | static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg) |
2215 | { | |
2216 | int timeout; | |
2217 | u32 grstctl; | |
2218 | ||
2219 | dev_dbg(hsotg->dev, "resetting core\n"); | |
2220 | ||
2221 | /* issue soft reset */ | |
94cb8fd6 | 2222 | writel(GRSTCTL_CSftRst, hsotg->regs + GRSTCTL); |
308d734e | 2223 | |
2868fea2 | 2224 | timeout = 10000; |
308d734e | 2225 | do { |
94cb8fd6 LM |
2226 | grstctl = readl(hsotg->regs + GRSTCTL); |
2227 | } while ((grstctl & GRSTCTL_CSftRst) && timeout-- > 0); | |
308d734e | 2228 | |
94cb8fd6 | 2229 | if (grstctl & GRSTCTL_CSftRst) { |
308d734e LM |
2230 | dev_err(hsotg->dev, "Failed to get CSftRst asserted\n"); |
2231 | return -EINVAL; | |
2232 | } | |
2233 | ||
2868fea2 | 2234 | timeout = 10000; |
308d734e LM |
2235 | |
2236 | while (1) { | |
94cb8fd6 | 2237 | u32 grstctl = readl(hsotg->regs + GRSTCTL); |
308d734e LM |
2238 | |
2239 | if (timeout-- < 0) { | |
2240 | dev_info(hsotg->dev, | |
2241 | "%s: reset failed, GRSTCTL=%08x\n", | |
2242 | __func__, grstctl); | |
2243 | return -ETIMEDOUT; | |
2244 | } | |
2245 | ||
94cb8fd6 | 2246 | if (!(grstctl & GRSTCTL_AHBIdle)) |
308d734e LM |
2247 | continue; |
2248 | ||
2249 | break; /* reset done */ | |
2250 | } | |
2251 | ||
2252 | dev_dbg(hsotg->dev, "reset successful\n"); | |
2253 | return 0; | |
2254 | } | |
2255 | ||
8b9bc460 LM |
2256 | /** |
2257 | * s3c_hsotg_core_init - issue softreset to the core | |
2258 | * @hsotg: The device state | |
2259 | * | |
2260 | * Issue a soft reset to the core, and await the core finishing it. | |
2261 | */ | |
308d734e LM |
2262 | static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg) |
2263 | { | |
2264 | s3c_hsotg_corereset(hsotg); | |
2265 | ||
2266 | /* | |
2267 | * we must now enable ep0 ready for host detection and then | |
2268 | * set configuration. | |
2269 | */ | |
2270 | ||
2271 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
94cb8fd6 LM |
2272 | writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) | |
2273 | (0x5 << 10), hsotg->regs + GUSBCFG); | |
308d734e LM |
2274 | |
2275 | s3c_hsotg_init_fifo(hsotg); | |
2276 | ||
94cb8fd6 | 2277 | __orr32(hsotg->regs + DCTL, DCTL_SftDiscon); |
308d734e | 2278 | |
94cb8fd6 | 2279 | writel(1 << 18 | DCFG_DevSpd_HS, hsotg->regs + DCFG); |
308d734e LM |
2280 | |
2281 | /* Clear any pending OTG interrupts */ | |
94cb8fd6 | 2282 | writel(0xffffffff, hsotg->regs + GOTGINT); |
308d734e LM |
2283 | |
2284 | /* Clear any pending interrupts */ | |
94cb8fd6 | 2285 | writel(0xffffffff, hsotg->regs + GINTSTS); |
308d734e | 2286 | |
94cb8fd6 LM |
2287 | writel(GINTSTS_ErlySusp | GINTSTS_SessReqInt | |
2288 | GINTSTS_GOUTNakEff | GINTSTS_GINNakEff | | |
2289 | GINTSTS_ConIDStsChng | GINTSTS_USBRst | | |
2290 | GINTSTS_EnumDone | GINTSTS_OTGInt | | |
2291 | GINTSTS_USBSusp | GINTSTS_WkUpInt, | |
2292 | hsotg->regs + GINTMSK); | |
308d734e LM |
2293 | |
2294 | if (using_dma(hsotg)) | |
94cb8fd6 LM |
2295 | writel(GAHBCFG_GlblIntrEn | GAHBCFG_DMAEn | |
2296 | GAHBCFG_HBstLen_Incr4, | |
2297 | hsotg->regs + GAHBCFG); | |
308d734e | 2298 | else |
94cb8fd6 | 2299 | writel(GAHBCFG_GlblIntrEn, hsotg->regs + GAHBCFG); |
308d734e LM |
2300 | |
2301 | /* | |
2302 | * Enabling INTknTXFEmpMsk here seems to be a big mistake, we end | |
2303 | * up being flooded with interrupts if the host is polling the | |
2304 | * endpoint to try and read data. | |
2305 | */ | |
2306 | ||
94cb8fd6 LM |
2307 | writel(((hsotg->dedicated_fifos) ? DIEPMSK_TxFIFOEmpty : 0) | |
2308 | DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk | | |
2309 | DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk | | |
2310 | DIEPMSK_INTknEPMisMsk, | |
2311 | hsotg->regs + DIEPMSK); | |
308d734e LM |
2312 | |
2313 | /* | |
2314 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
2315 | * DMA mode we may need this. | |
2316 | */ | |
94cb8fd6 LM |
2317 | writel((using_dma(hsotg) ? (DIEPMSK_XferComplMsk | |
2318 | DIEPMSK_TimeOUTMsk) : 0) | | |
2319 | DOEPMSK_EPDisbldMsk | DOEPMSK_AHBErrMsk | | |
2320 | DOEPMSK_SetupMsk, | |
2321 | hsotg->regs + DOEPMSK); | |
308d734e | 2322 | |
94cb8fd6 | 2323 | writel(0, hsotg->regs + DAINTMSK); |
308d734e LM |
2324 | |
2325 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
94cb8fd6 LM |
2326 | readl(hsotg->regs + DIEPCTL0), |
2327 | readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2328 | |
2329 | /* enable in and out endpoint interrupts */ | |
94cb8fd6 | 2330 | s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPInt | GINTSTS_IEPInt); |
308d734e LM |
2331 | |
2332 | /* | |
2333 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
2334 | * the data. In DMA mode, we get events from the FIFO but also | |
2335 | * things we cannot process, so do not use it. | |
2336 | */ | |
2337 | if (!using_dma(hsotg)) | |
94cb8fd6 | 2338 | s3c_hsotg_en_gsint(hsotg, GINTSTS_RxFLvl); |
308d734e LM |
2339 | |
2340 | /* Enable interrupts for EP0 in and out */ | |
2341 | s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1); | |
2342 | s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
2343 | ||
94cb8fd6 | 2344 | __orr32(hsotg->regs + DCTL, DCTL_PWROnPrgDone); |
308d734e | 2345 | udelay(10); /* see openiboot */ |
94cb8fd6 | 2346 | __bic32(hsotg->regs + DCTL, DCTL_PWROnPrgDone); |
308d734e | 2347 | |
94cb8fd6 | 2348 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL)); |
308d734e LM |
2349 | |
2350 | /* | |
94cb8fd6 | 2351 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
2352 | * writing to the EPCTL register.. |
2353 | */ | |
2354 | ||
2355 | /* set to read 1 8byte packet */ | |
94cb8fd6 LM |
2356 | writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) | |
2357 | DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0); | |
308d734e LM |
2358 | |
2359 | writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) | | |
94cb8fd6 LM |
2360 | DxEPCTL_CNAK | DxEPCTL_EPEna | |
2361 | DxEPCTL_USBActEp, | |
2362 | hsotg->regs + DOEPCTL0); | |
308d734e LM |
2363 | |
2364 | /* enable, but don't activate EP0in */ | |
2365 | writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) | | |
94cb8fd6 | 2366 | DxEPCTL_USBActEp, hsotg->regs + DIEPCTL0); |
308d734e LM |
2367 | |
2368 | s3c_hsotg_enqueue_setup(hsotg); | |
2369 | ||
2370 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
94cb8fd6 LM |
2371 | readl(hsotg->regs + DIEPCTL0), |
2372 | readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2373 | |
2374 | /* clear global NAKs */ | |
94cb8fd6 LM |
2375 | writel(DCTL_CGOUTNak | DCTL_CGNPInNAK, |
2376 | hsotg->regs + DCTL); | |
308d734e LM |
2377 | |
2378 | /* must be at-least 3ms to allow bus to see disconnect */ | |
2379 | mdelay(3); | |
2380 | ||
2381 | /* remove the soft-disconnect and let's go */ | |
94cb8fd6 | 2382 | __bic32(hsotg->regs + DCTL, DCTL_SftDiscon); |
308d734e LM |
2383 | } |
2384 | ||
5b7d70c6 BD |
2385 | /** |
2386 | * s3c_hsotg_irq - handle device interrupt | |
2387 | * @irq: The IRQ number triggered | |
2388 | * @pw: The pw value when registered the handler. | |
2389 | */ | |
2390 | static irqreturn_t s3c_hsotg_irq(int irq, void *pw) | |
2391 | { | |
2392 | struct s3c_hsotg *hsotg = pw; | |
2393 | int retry_count = 8; | |
2394 | u32 gintsts; | |
2395 | u32 gintmsk; | |
2396 | ||
5ad1d316 | 2397 | spin_lock(&hsotg->lock); |
5b7d70c6 | 2398 | irq_retry: |
94cb8fd6 LM |
2399 | gintsts = readl(hsotg->regs + GINTSTS); |
2400 | gintmsk = readl(hsotg->regs + GINTMSK); | |
5b7d70c6 BD |
2401 | |
2402 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
2403 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
2404 | ||
2405 | gintsts &= gintmsk; | |
2406 | ||
94cb8fd6 LM |
2407 | if (gintsts & GINTSTS_OTGInt) { |
2408 | u32 otgint = readl(hsotg->regs + GOTGINT); | |
5b7d70c6 BD |
2409 | |
2410 | dev_info(hsotg->dev, "OTGInt: %08x\n", otgint); | |
2411 | ||
94cb8fd6 | 2412 | writel(otgint, hsotg->regs + GOTGINT); |
5b7d70c6 BD |
2413 | } |
2414 | ||
94cb8fd6 | 2415 | if (gintsts & GINTSTS_SessReqInt) { |
5b7d70c6 | 2416 | dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__); |
94cb8fd6 | 2417 | writel(GINTSTS_SessReqInt, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2418 | } |
2419 | ||
94cb8fd6 LM |
2420 | if (gintsts & GINTSTS_EnumDone) { |
2421 | writel(GINTSTS_EnumDone, hsotg->regs + GINTSTS); | |
a3395f0d AT |
2422 | |
2423 | s3c_hsotg_irq_enumdone(hsotg); | |
5b7d70c6 BD |
2424 | } |
2425 | ||
94cb8fd6 | 2426 | if (gintsts & GINTSTS_ConIDStsChng) { |
5b7d70c6 | 2427 | dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n", |
94cb8fd6 LM |
2428 | readl(hsotg->regs + DSTS), |
2429 | readl(hsotg->regs + GOTGCTL)); | |
5b7d70c6 | 2430 | |
94cb8fd6 | 2431 | writel(GINTSTS_ConIDStsChng, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2432 | } |
2433 | ||
94cb8fd6 LM |
2434 | if (gintsts & (GINTSTS_OEPInt | GINTSTS_IEPInt)) { |
2435 | u32 daint = readl(hsotg->regs + DAINT); | |
7e804650 RB |
2436 | u32 daintmsk = readl(hsotg->regs + DAINTMSK); |
2437 | u32 daint_out, daint_in; | |
5b7d70c6 BD |
2438 | int ep; |
2439 | ||
7e804650 RB |
2440 | daint &= daintmsk; |
2441 | daint_out = daint >> DAINT_OutEP_SHIFT; | |
2442 | daint_in = daint & ~(daint_out << DAINT_OutEP_SHIFT); | |
2443 | ||
5b7d70c6 BD |
2444 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
2445 | ||
2446 | for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) { | |
2447 | if (daint_out & 1) | |
2448 | s3c_hsotg_epint(hsotg, ep, 0); | |
2449 | } | |
2450 | ||
2451 | for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) { | |
2452 | if (daint_in & 1) | |
2453 | s3c_hsotg_epint(hsotg, ep, 1); | |
2454 | } | |
5b7d70c6 BD |
2455 | } |
2456 | ||
94cb8fd6 | 2457 | if (gintsts & GINTSTS_USBRst) { |
12a1f4dc | 2458 | |
94cb8fd6 | 2459 | u32 usb_status = readl(hsotg->regs + GOTGCTL); |
12a1f4dc | 2460 | |
5b7d70c6 BD |
2461 | dev_info(hsotg->dev, "%s: USBRst\n", __func__); |
2462 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", | |
94cb8fd6 | 2463 | readl(hsotg->regs + GNPTXSTS)); |
5b7d70c6 | 2464 | |
94cb8fd6 | 2465 | writel(GINTSTS_USBRst, hsotg->regs + GINTSTS); |
a3395f0d | 2466 | |
94cb8fd6 | 2467 | if (usb_status & GOTGCTL_BSESVLD) { |
12a1f4dc LM |
2468 | if (time_after(jiffies, hsotg->last_rst + |
2469 | msecs_to_jiffies(200))) { | |
5b7d70c6 | 2470 | |
12a1f4dc LM |
2471 | kill_all_requests(hsotg, &hsotg->eps[0], |
2472 | -ECONNRESET, true); | |
5b7d70c6 | 2473 | |
12a1f4dc LM |
2474 | s3c_hsotg_core_init(hsotg); |
2475 | hsotg->last_rst = jiffies; | |
2476 | } | |
2477 | } | |
5b7d70c6 BD |
2478 | } |
2479 | ||
2480 | /* check both FIFOs */ | |
2481 | ||
94cb8fd6 | 2482 | if (gintsts & GINTSTS_NPTxFEmp) { |
5b7d70c6 BD |
2483 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
2484 | ||
8b9bc460 LM |
2485 | /* |
2486 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 2487 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
2488 | * it needs re-enabling |
2489 | */ | |
5b7d70c6 | 2490 | |
94cb8fd6 | 2491 | s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTxFEmp); |
5b7d70c6 | 2492 | s3c_hsotg_irq_fifoempty(hsotg, false); |
5b7d70c6 BD |
2493 | } |
2494 | ||
94cb8fd6 | 2495 | if (gintsts & GINTSTS_PTxFEmp) { |
5b7d70c6 BD |
2496 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
2497 | ||
94cb8fd6 | 2498 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 2499 | |
94cb8fd6 | 2500 | s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTxFEmp); |
5b7d70c6 | 2501 | s3c_hsotg_irq_fifoempty(hsotg, true); |
5b7d70c6 BD |
2502 | } |
2503 | ||
94cb8fd6 | 2504 | if (gintsts & GINTSTS_RxFLvl) { |
8b9bc460 LM |
2505 | /* |
2506 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
5b7d70c6 | 2507 | * we need to retry s3c_hsotg_handle_rx if this is still |
8b9bc460 LM |
2508 | * set. |
2509 | */ | |
5b7d70c6 BD |
2510 | |
2511 | s3c_hsotg_handle_rx(hsotg); | |
5b7d70c6 BD |
2512 | } |
2513 | ||
94cb8fd6 | 2514 | if (gintsts & GINTSTS_ModeMis) { |
5b7d70c6 | 2515 | dev_warn(hsotg->dev, "warning, mode mismatch triggered\n"); |
94cb8fd6 | 2516 | writel(GINTSTS_ModeMis, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2517 | } |
2518 | ||
94cb8fd6 LM |
2519 | if (gintsts & GINTSTS_USBSusp) { |
2520 | dev_info(hsotg->dev, "GINTSTS_USBSusp\n"); | |
2521 | writel(GINTSTS_USBSusp, hsotg->regs + GINTSTS); | |
5b7d70c6 BD |
2522 | |
2523 | call_gadget(hsotg, suspend); | |
12a1f4dc | 2524 | s3c_hsotg_disconnect(hsotg); |
5b7d70c6 BD |
2525 | } |
2526 | ||
94cb8fd6 LM |
2527 | if (gintsts & GINTSTS_WkUpInt) { |
2528 | dev_info(hsotg->dev, "GINTSTS_WkUpIn\n"); | |
2529 | writel(GINTSTS_WkUpInt, hsotg->regs + GINTSTS); | |
5b7d70c6 BD |
2530 | |
2531 | call_gadget(hsotg, resume); | |
2532 | } | |
2533 | ||
94cb8fd6 LM |
2534 | if (gintsts & GINTSTS_ErlySusp) { |
2535 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); | |
2536 | writel(GINTSTS_ErlySusp, hsotg->regs + GINTSTS); | |
5b7d70c6 BD |
2537 | } |
2538 | ||
8b9bc460 LM |
2539 | /* |
2540 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 2541 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
2542 | * the occurrence. |
2543 | */ | |
5b7d70c6 | 2544 | |
94cb8fd6 | 2545 | if (gintsts & GINTSTS_GOUTNakEff) { |
5b7d70c6 BD |
2546 | dev_info(hsotg->dev, "GOUTNakEff triggered\n"); |
2547 | ||
94cb8fd6 | 2548 | writel(DCTL_CGOUTNak, hsotg->regs + DCTL); |
a3395f0d AT |
2549 | |
2550 | s3c_hsotg_dump(hsotg); | |
5b7d70c6 BD |
2551 | } |
2552 | ||
94cb8fd6 | 2553 | if (gintsts & GINTSTS_GINNakEff) { |
5b7d70c6 BD |
2554 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
2555 | ||
94cb8fd6 | 2556 | writel(DCTL_CGNPInNAK, hsotg->regs + DCTL); |
a3395f0d AT |
2557 | |
2558 | s3c_hsotg_dump(hsotg); | |
5b7d70c6 BD |
2559 | } |
2560 | ||
8b9bc460 LM |
2561 | /* |
2562 | * if we've had fifo events, we should try and go around the | |
2563 | * loop again to see if there's any point in returning yet. | |
2564 | */ | |
5b7d70c6 BD |
2565 | |
2566 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
2567 | goto irq_retry; | |
2568 | ||
5ad1d316 LM |
2569 | spin_unlock(&hsotg->lock); |
2570 | ||
5b7d70c6 BD |
2571 | return IRQ_HANDLED; |
2572 | } | |
2573 | ||
2574 | /** | |
2575 | * s3c_hsotg_ep_enable - enable the given endpoint | |
2576 | * @ep: The USB endpint to configure | |
2577 | * @desc: The USB endpoint descriptor to configure with. | |
2578 | * | |
2579 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 2580 | */ |
5b7d70c6 BD |
2581 | static int s3c_hsotg_ep_enable(struct usb_ep *ep, |
2582 | const struct usb_endpoint_descriptor *desc) | |
2583 | { | |
2584 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
2585 | struct s3c_hsotg *hsotg = hs_ep->parent; | |
2586 | unsigned long flags; | |
2587 | int index = hs_ep->index; | |
2588 | u32 epctrl_reg; | |
2589 | u32 epctrl; | |
2590 | u32 mps; | |
2591 | int dir_in; | |
19c190f9 | 2592 | int ret = 0; |
5b7d70c6 BD |
2593 | |
2594 | dev_dbg(hsotg->dev, | |
2595 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
2596 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
2597 | desc->wMaxPacketSize, desc->bInterval); | |
2598 | ||
2599 | /* not to be called for EP0 */ | |
2600 | WARN_ON(index == 0); | |
2601 | ||
2602 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
2603 | if (dir_in != hs_ep->dir_in) { | |
2604 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
2605 | return -EINVAL; | |
2606 | } | |
2607 | ||
29cc8897 | 2608 | mps = usb_endpoint_maxp(desc); |
5b7d70c6 BD |
2609 | |
2610 | /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */ | |
2611 | ||
94cb8fd6 | 2612 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 BD |
2613 | epctrl = readl(hsotg->regs + epctrl_reg); |
2614 | ||
2615 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
2616 | __func__, epctrl, epctrl_reg); | |
2617 | ||
22258f49 | 2618 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 2619 | |
94cb8fd6 LM |
2620 | epctrl &= ~(DxEPCTL_EPType_MASK | DxEPCTL_MPS_MASK); |
2621 | epctrl |= DxEPCTL_MPS(mps); | |
5b7d70c6 | 2622 | |
8b9bc460 LM |
2623 | /* |
2624 | * mark the endpoint as active, otherwise the core may ignore | |
2625 | * transactions entirely for this endpoint | |
2626 | */ | |
94cb8fd6 | 2627 | epctrl |= DxEPCTL_USBActEp; |
5b7d70c6 | 2628 | |
8b9bc460 LM |
2629 | /* |
2630 | * set the NAK status on the endpoint, otherwise we might try and | |
5b7d70c6 BD |
2631 | * do something with data that we've yet got a request to process |
2632 | * since the RXFIFO will take data for an endpoint even if the | |
2633 | * size register hasn't been set. | |
2634 | */ | |
2635 | ||
94cb8fd6 | 2636 | epctrl |= DxEPCTL_SNAK; |
5b7d70c6 BD |
2637 | |
2638 | /* update the endpoint state */ | |
e9edd199 | 2639 | s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps); |
5b7d70c6 BD |
2640 | |
2641 | /* default, set to non-periodic */ | |
1479e841 | 2642 | hs_ep->isochronous = 0; |
5b7d70c6 | 2643 | hs_ep->periodic = 0; |
1479e841 | 2644 | hs_ep->interval = desc->bInterval; |
5b7d70c6 | 2645 | |
4fca54aa RB |
2646 | if (hs_ep->interval > 1 && hs_ep->mc > 1) |
2647 | dev_err(hsotg->dev, "MC > 1 when interval is not 1\n"); | |
2648 | ||
5b7d70c6 BD |
2649 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
2650 | case USB_ENDPOINT_XFER_ISOC: | |
1479e841 RB |
2651 | epctrl |= DxEPCTL_EPType_Iso; |
2652 | epctrl |= DxEPCTL_SetEvenFr; | |
2653 | hs_ep->isochronous = 1; | |
2654 | if (dir_in) | |
2655 | hs_ep->periodic = 1; | |
2656 | break; | |
5b7d70c6 BD |
2657 | |
2658 | case USB_ENDPOINT_XFER_BULK: | |
94cb8fd6 | 2659 | epctrl |= DxEPCTL_EPType_Bulk; |
5b7d70c6 BD |
2660 | break; |
2661 | ||
2662 | case USB_ENDPOINT_XFER_INT: | |
2663 | if (dir_in) { | |
8b9bc460 LM |
2664 | /* |
2665 | * Allocate our TxFNum by simply using the index | |
5b7d70c6 BD |
2666 | * of the endpoint for the moment. We could do |
2667 | * something better if the host indicates how | |
8b9bc460 LM |
2668 | * many FIFOs we are expecting to use. |
2669 | */ | |
5b7d70c6 BD |
2670 | |
2671 | hs_ep->periodic = 1; | |
94cb8fd6 | 2672 | epctrl |= DxEPCTL_TxFNum(index); |
5b7d70c6 BD |
2673 | } |
2674 | ||
94cb8fd6 | 2675 | epctrl |= DxEPCTL_EPType_Intterupt; |
5b7d70c6 BD |
2676 | break; |
2677 | ||
2678 | case USB_ENDPOINT_XFER_CONTROL: | |
94cb8fd6 | 2679 | epctrl |= DxEPCTL_EPType_Control; |
5b7d70c6 BD |
2680 | break; |
2681 | } | |
2682 | ||
8b9bc460 LM |
2683 | /* |
2684 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
2685 | * a unique tx-fifo even if it is non-periodic. |
2686 | */ | |
2687 | if (dir_in && hsotg->dedicated_fifos) | |
94cb8fd6 | 2688 | epctrl |= DxEPCTL_TxFNum(index); |
10aebc77 | 2689 | |
5b7d70c6 BD |
2690 | /* for non control endpoints, set PID to D0 */ |
2691 | if (index) | |
94cb8fd6 | 2692 | epctrl |= DxEPCTL_SetD0PID; |
5b7d70c6 BD |
2693 | |
2694 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", | |
2695 | __func__, epctrl); | |
2696 | ||
2697 | writel(epctrl, hsotg->regs + epctrl_reg); | |
2698 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", | |
2699 | __func__, readl(hsotg->regs + epctrl_reg)); | |
2700 | ||
2701 | /* enable the endpoint interrupt */ | |
2702 | s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1); | |
2703 | ||
22258f49 | 2704 | spin_unlock_irqrestore(&hsotg->lock, flags); |
19c190f9 | 2705 | return ret; |
5b7d70c6 BD |
2706 | } |
2707 | ||
8b9bc460 LM |
2708 | /** |
2709 | * s3c_hsotg_ep_disable - disable given endpoint | |
2710 | * @ep: The endpoint to disable. | |
2711 | */ | |
5b7d70c6 BD |
2712 | static int s3c_hsotg_ep_disable(struct usb_ep *ep) |
2713 | { | |
2714 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
2715 | struct s3c_hsotg *hsotg = hs_ep->parent; | |
2716 | int dir_in = hs_ep->dir_in; | |
2717 | int index = hs_ep->index; | |
2718 | unsigned long flags; | |
2719 | u32 epctrl_reg; | |
2720 | u32 ctrl; | |
2721 | ||
2722 | dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep); | |
2723 | ||
2724 | if (ep == &hsotg->eps[0].ep) { | |
2725 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); | |
2726 | return -EINVAL; | |
2727 | } | |
2728 | ||
94cb8fd6 | 2729 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 2730 | |
5ad1d316 | 2731 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 BD |
2732 | /* terminate all requests with shutdown */ |
2733 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false); | |
2734 | ||
5b7d70c6 BD |
2735 | |
2736 | ctrl = readl(hsotg->regs + epctrl_reg); | |
94cb8fd6 LM |
2737 | ctrl &= ~DxEPCTL_EPEna; |
2738 | ctrl &= ~DxEPCTL_USBActEp; | |
2739 | ctrl |= DxEPCTL_SNAK; | |
5b7d70c6 BD |
2740 | |
2741 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
2742 | writel(ctrl, hsotg->regs + epctrl_reg); | |
2743 | ||
2744 | /* disable endpoint interrupts */ | |
2745 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); | |
2746 | ||
22258f49 | 2747 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
2748 | return 0; |
2749 | } | |
2750 | ||
2751 | /** | |
2752 | * on_list - check request is on the given endpoint | |
2753 | * @ep: The endpoint to check. | |
2754 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 2755 | */ |
5b7d70c6 BD |
2756 | static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test) |
2757 | { | |
2758 | struct s3c_hsotg_req *req, *treq; | |
2759 | ||
2760 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
2761 | if (req == test) | |
2762 | return true; | |
2763 | } | |
2764 | ||
2765 | return false; | |
2766 | } | |
2767 | ||
8b9bc460 LM |
2768 | /** |
2769 | * s3c_hsotg_ep_dequeue - dequeue given endpoint | |
2770 | * @ep: The endpoint to dequeue. | |
2771 | * @req: The request to be removed from a queue. | |
2772 | */ | |
5b7d70c6 BD |
2773 | static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
2774 | { | |
2775 | struct s3c_hsotg_req *hs_req = our_req(req); | |
2776 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
2777 | struct s3c_hsotg *hs = hs_ep->parent; | |
2778 | unsigned long flags; | |
2779 | ||
2780 | dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); | |
2781 | ||
22258f49 | 2782 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
2783 | |
2784 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 2785 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
2786 | return -EINVAL; |
2787 | } | |
2788 | ||
2789 | s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); | |
22258f49 | 2790 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
2791 | |
2792 | return 0; | |
2793 | } | |
2794 | ||
8b9bc460 LM |
2795 | /** |
2796 | * s3c_hsotg_ep_sethalt - set halt on a given endpoint | |
2797 | * @ep: The endpoint to set halt. | |
2798 | * @value: Set or unset the halt. | |
2799 | */ | |
5b7d70c6 BD |
2800 | static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value) |
2801 | { | |
2802 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
2803 | struct s3c_hsotg *hs = hs_ep->parent; | |
2804 | int index = hs_ep->index; | |
5b7d70c6 BD |
2805 | u32 epreg; |
2806 | u32 epctl; | |
9c39ddc6 | 2807 | u32 xfertype; |
5b7d70c6 BD |
2808 | |
2809 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
2810 | ||
5b7d70c6 BD |
2811 | /* write both IN and OUT control registers */ |
2812 | ||
94cb8fd6 | 2813 | epreg = DIEPCTL(index); |
5b7d70c6 BD |
2814 | epctl = readl(hs->regs + epreg); |
2815 | ||
9c39ddc6 | 2816 | if (value) { |
94cb8fd6 LM |
2817 | epctl |= DxEPCTL_Stall + DxEPCTL_SNAK; |
2818 | if (epctl & DxEPCTL_EPEna) | |
2819 | epctl |= DxEPCTL_EPDis; | |
9c39ddc6 | 2820 | } else { |
94cb8fd6 LM |
2821 | epctl &= ~DxEPCTL_Stall; |
2822 | xfertype = epctl & DxEPCTL_EPType_MASK; | |
2823 | if (xfertype == DxEPCTL_EPType_Bulk || | |
2824 | xfertype == DxEPCTL_EPType_Intterupt) | |
2825 | epctl |= DxEPCTL_SetD0PID; | |
9c39ddc6 | 2826 | } |
5b7d70c6 BD |
2827 | |
2828 | writel(epctl, hs->regs + epreg); | |
2829 | ||
94cb8fd6 | 2830 | epreg = DOEPCTL(index); |
5b7d70c6 BD |
2831 | epctl = readl(hs->regs + epreg); |
2832 | ||
2833 | if (value) | |
94cb8fd6 | 2834 | epctl |= DxEPCTL_Stall; |
9c39ddc6 | 2835 | else { |
94cb8fd6 LM |
2836 | epctl &= ~DxEPCTL_Stall; |
2837 | xfertype = epctl & DxEPCTL_EPType_MASK; | |
2838 | if (xfertype == DxEPCTL_EPType_Bulk || | |
2839 | xfertype == DxEPCTL_EPType_Intterupt) | |
2840 | epctl |= DxEPCTL_SetD0PID; | |
9c39ddc6 | 2841 | } |
5b7d70c6 BD |
2842 | |
2843 | writel(epctl, hs->regs + epreg); | |
2844 | ||
5b7d70c6 BD |
2845 | return 0; |
2846 | } | |
2847 | ||
5ad1d316 LM |
2848 | /** |
2849 | * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held | |
2850 | * @ep: The endpoint to set halt. | |
2851 | * @value: Set or unset the halt. | |
2852 | */ | |
2853 | static int s3c_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) | |
2854 | { | |
2855 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
2856 | struct s3c_hsotg *hs = hs_ep->parent; | |
2857 | unsigned long flags = 0; | |
2858 | int ret = 0; | |
2859 | ||
2860 | spin_lock_irqsave(&hs->lock, flags); | |
2861 | ret = s3c_hsotg_ep_sethalt(ep, value); | |
2862 | spin_unlock_irqrestore(&hs->lock, flags); | |
2863 | ||
2864 | return ret; | |
2865 | } | |
2866 | ||
5b7d70c6 BD |
2867 | static struct usb_ep_ops s3c_hsotg_ep_ops = { |
2868 | .enable = s3c_hsotg_ep_enable, | |
2869 | .disable = s3c_hsotg_ep_disable, | |
2870 | .alloc_request = s3c_hsotg_ep_alloc_request, | |
2871 | .free_request = s3c_hsotg_ep_free_request, | |
5ad1d316 | 2872 | .queue = s3c_hsotg_ep_queue_lock, |
5b7d70c6 | 2873 | .dequeue = s3c_hsotg_ep_dequeue, |
5ad1d316 | 2874 | .set_halt = s3c_hsotg_ep_sethalt_lock, |
25985edc | 2875 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
2876 | }; |
2877 | ||
41188786 LM |
2878 | /** |
2879 | * s3c_hsotg_phy_enable - enable platform phy dev | |
8b9bc460 | 2880 | * @hsotg: The driver state |
41188786 LM |
2881 | * |
2882 | * A wrapper for platform code responsible for controlling | |
2883 | * low-level USB code | |
2884 | */ | |
2885 | static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg) | |
2886 | { | |
2887 | struct platform_device *pdev = to_platform_device(hsotg->dev); | |
2888 | ||
2889 | dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev); | |
b2e587db PP |
2890 | |
2891 | if (hsotg->phy) | |
2892 | usb_phy_init(hsotg->phy); | |
2893 | else if (hsotg->plat->phy_init) | |
41188786 LM |
2894 | hsotg->plat->phy_init(pdev, hsotg->plat->phy_type); |
2895 | } | |
2896 | ||
2897 | /** | |
2898 | * s3c_hsotg_phy_disable - disable platform phy dev | |
8b9bc460 | 2899 | * @hsotg: The driver state |
41188786 LM |
2900 | * |
2901 | * A wrapper for platform code responsible for controlling | |
2902 | * low-level USB code | |
2903 | */ | |
2904 | static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg) | |
2905 | { | |
2906 | struct platform_device *pdev = to_platform_device(hsotg->dev); | |
2907 | ||
b2e587db PP |
2908 | if (hsotg->phy) |
2909 | usb_phy_shutdown(hsotg->phy); | |
2910 | else if (hsotg->plat->phy_exit) | |
41188786 LM |
2911 | hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type); |
2912 | } | |
2913 | ||
8b9bc460 LM |
2914 | /** |
2915 | * s3c_hsotg_init - initalize the usb core | |
2916 | * @hsotg: The driver state | |
2917 | */ | |
b3f489b2 LM |
2918 | static void s3c_hsotg_init(struct s3c_hsotg *hsotg) |
2919 | { | |
2920 | /* unmask subset of endpoint interrupts */ | |
2921 | ||
94cb8fd6 LM |
2922 | writel(DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk | |
2923 | DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk, | |
2924 | hsotg->regs + DIEPMSK); | |
b3f489b2 | 2925 | |
94cb8fd6 LM |
2926 | writel(DOEPMSK_SetupMsk | DOEPMSK_AHBErrMsk | |
2927 | DOEPMSK_EPDisbldMsk | DOEPMSK_XferComplMsk, | |
2928 | hsotg->regs + DOEPMSK); | |
b3f489b2 | 2929 | |
94cb8fd6 | 2930 | writel(0, hsotg->regs + DAINTMSK); |
b3f489b2 LM |
2931 | |
2932 | /* Be in disconnected state until gadget is registered */ | |
94cb8fd6 | 2933 | __orr32(hsotg->regs + DCTL, DCTL_SftDiscon); |
b3f489b2 LM |
2934 | |
2935 | if (0) { | |
2936 | /* post global nak until we're ready */ | |
94cb8fd6 LM |
2937 | writel(DCTL_SGNPInNAK | DCTL_SGOUTNak, |
2938 | hsotg->regs + DCTL); | |
b3f489b2 LM |
2939 | } |
2940 | ||
2941 | /* setup fifos */ | |
2942 | ||
2943 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
94cb8fd6 LM |
2944 | readl(hsotg->regs + GRXFSIZ), |
2945 | readl(hsotg->regs + GNPTXFSIZ)); | |
b3f489b2 LM |
2946 | |
2947 | s3c_hsotg_init_fifo(hsotg); | |
2948 | ||
2949 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
94cb8fd6 LM |
2950 | writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) | (0x5 << 10), |
2951 | hsotg->regs + GUSBCFG); | |
b3f489b2 | 2952 | |
94cb8fd6 LM |
2953 | writel(using_dma(hsotg) ? GAHBCFG_DMAEn : 0x0, |
2954 | hsotg->regs + GAHBCFG); | |
b3f489b2 LM |
2955 | } |
2956 | ||
8b9bc460 LM |
2957 | /** |
2958 | * s3c_hsotg_udc_start - prepare the udc for work | |
2959 | * @gadget: The usb gadget state | |
2960 | * @driver: The usb gadget driver | |
2961 | * | |
2962 | * Perform initialization to prepare udc device and driver | |
2963 | * to work. | |
2964 | */ | |
f65f0f10 LM |
2965 | static int s3c_hsotg_udc_start(struct usb_gadget *gadget, |
2966 | struct usb_gadget_driver *driver) | |
5b7d70c6 | 2967 | { |
f99b2bfe | 2968 | struct s3c_hsotg *hsotg = to_hsotg(gadget); |
5b7d70c6 BD |
2969 | int ret; |
2970 | ||
2971 | if (!hsotg) { | |
a023da33 | 2972 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
2973 | return -ENODEV; |
2974 | } | |
2975 | ||
2976 | if (!driver) { | |
2977 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
2978 | return -EINVAL; | |
2979 | } | |
2980 | ||
7177aed4 | 2981 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 2982 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 2983 | |
f65f0f10 | 2984 | if (!driver->setup) { |
5b7d70c6 BD |
2985 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
2986 | return -EINVAL; | |
2987 | } | |
2988 | ||
2989 | WARN_ON(hsotg->driver); | |
2990 | ||
2991 | driver->driver.bus = NULL; | |
2992 | hsotg->driver = driver; | |
7d7b2292 | 2993 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
2994 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
2995 | ||
f65f0f10 LM |
2996 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), |
2997 | hsotg->supplies); | |
5b7d70c6 | 2998 | if (ret) { |
f65f0f10 | 2999 | dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret); |
5b7d70c6 BD |
3000 | goto err; |
3001 | } | |
3002 | ||
12a1f4dc | 3003 | hsotg->last_rst = jiffies; |
5b7d70c6 BD |
3004 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
3005 | return 0; | |
3006 | ||
3007 | err: | |
3008 | hsotg->driver = NULL; | |
5b7d70c6 BD |
3009 | return ret; |
3010 | } | |
3011 | ||
8b9bc460 LM |
3012 | /** |
3013 | * s3c_hsotg_udc_stop - stop the udc | |
3014 | * @gadget: The usb gadget state | |
3015 | * @driver: The usb gadget driver | |
3016 | * | |
3017 | * Stop udc hw block and stay tunned for future transmissions | |
3018 | */ | |
f65f0f10 LM |
3019 | static int s3c_hsotg_udc_stop(struct usb_gadget *gadget, |
3020 | struct usb_gadget_driver *driver) | |
5b7d70c6 | 3021 | { |
f99b2bfe | 3022 | struct s3c_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 3023 | unsigned long flags = 0; |
5b7d70c6 BD |
3024 | int ep; |
3025 | ||
3026 | if (!hsotg) | |
3027 | return -ENODEV; | |
3028 | ||
5b7d70c6 | 3029 | /* all endpoints should be shutdown */ |
b3f489b2 | 3030 | for (ep = 0; ep < hsotg->num_of_eps; ep++) |
5b7d70c6 BD |
3031 | s3c_hsotg_ep_disable(&hsotg->eps[ep].ep); |
3032 | ||
2b19a52c LM |
3033 | spin_lock_irqsave(&hsotg->lock, flags); |
3034 | ||
f65f0f10 | 3035 | s3c_hsotg_phy_disable(hsotg); |
5b7d70c6 | 3036 | |
c8c10253 MS |
3037 | if (!driver) |
3038 | hsotg->driver = NULL; | |
3039 | ||
5b7d70c6 | 3040 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
5b7d70c6 | 3041 | |
2b19a52c LM |
3042 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3043 | ||
c8c10253 | 3044 | regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies); |
5b7d70c6 BD |
3045 | |
3046 | return 0; | |
3047 | } | |
5b7d70c6 | 3048 | |
8b9bc460 LM |
3049 | /** |
3050 | * s3c_hsotg_gadget_getframe - read the frame number | |
3051 | * @gadget: The usb gadget state | |
3052 | * | |
3053 | * Read the {micro} frame number | |
3054 | */ | |
5b7d70c6 BD |
3055 | static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget) |
3056 | { | |
3057 | return s3c_hsotg_read_frameno(to_hsotg(gadget)); | |
3058 | } | |
3059 | ||
a188b689 LM |
3060 | /** |
3061 | * s3c_hsotg_pullup - connect/disconnect the USB PHY | |
3062 | * @gadget: The usb gadget state | |
3063 | * @is_on: Current state of the USB PHY | |
3064 | * | |
3065 | * Connect/Disconnect the USB PHY pullup | |
3066 | */ | |
3067 | static int s3c_hsotg_pullup(struct usb_gadget *gadget, int is_on) | |
3068 | { | |
3069 | struct s3c_hsotg *hsotg = to_hsotg(gadget); | |
3070 | unsigned long flags = 0; | |
3071 | ||
3072 | dev_dbg(hsotg->dev, "%s: is_in: %d\n", __func__, is_on); | |
3073 | ||
3074 | spin_lock_irqsave(&hsotg->lock, flags); | |
3075 | if (is_on) { | |
3076 | s3c_hsotg_phy_enable(hsotg); | |
3077 | s3c_hsotg_core_init(hsotg); | |
3078 | } else { | |
3079 | s3c_hsotg_disconnect(hsotg); | |
3080 | s3c_hsotg_phy_disable(hsotg); | |
3081 | } | |
3082 | ||
3083 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
3084 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3085 | ||
3086 | return 0; | |
3087 | } | |
3088 | ||
eeef4587 | 3089 | static const struct usb_gadget_ops s3c_hsotg_gadget_ops = { |
5b7d70c6 | 3090 | .get_frame = s3c_hsotg_gadget_getframe, |
f65f0f10 LM |
3091 | .udc_start = s3c_hsotg_udc_start, |
3092 | .udc_stop = s3c_hsotg_udc_stop, | |
a188b689 | 3093 | .pullup = s3c_hsotg_pullup, |
5b7d70c6 BD |
3094 | }; |
3095 | ||
3096 | /** | |
3097 | * s3c_hsotg_initep - initialise a single endpoint | |
3098 | * @hsotg: The device state. | |
3099 | * @hs_ep: The endpoint to be initialised. | |
3100 | * @epnum: The endpoint number | |
3101 | * | |
3102 | * Initialise the given endpoint (as part of the probe and device state | |
3103 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
3104 | * direction information and other state that may be required. | |
3105 | */ | |
41ac7b3a | 3106 | static void s3c_hsotg_initep(struct s3c_hsotg *hsotg, |
5b7d70c6 BD |
3107 | struct s3c_hsotg_ep *hs_ep, |
3108 | int epnum) | |
3109 | { | |
3110 | u32 ptxfifo; | |
3111 | char *dir; | |
3112 | ||
3113 | if (epnum == 0) | |
3114 | dir = ""; | |
3115 | else if ((epnum % 2) == 0) { | |
3116 | dir = "out"; | |
3117 | } else { | |
3118 | dir = "in"; | |
3119 | hs_ep->dir_in = 1; | |
3120 | } | |
3121 | ||
3122 | hs_ep->index = epnum; | |
3123 | ||
3124 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
3125 | ||
3126 | INIT_LIST_HEAD(&hs_ep->queue); | |
3127 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
3128 | ||
5b7d70c6 BD |
3129 | /* add to the list of endpoints known by the gadget driver */ |
3130 | if (epnum) | |
3131 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
3132 | ||
3133 | hs_ep->parent = hsotg; | |
3134 | hs_ep->ep.name = hs_ep->name; | |
13613c13 | 3135 | hs_ep->ep.maxpacket = epnum ? 1024 : EP0_MPS_LIMIT; |
5b7d70c6 BD |
3136 | hs_ep->ep.ops = &s3c_hsotg_ep_ops; |
3137 | ||
8b9bc460 LM |
3138 | /* |
3139 | * Read the FIFO size for the Periodic TX FIFO, even if we're | |
5b7d70c6 BD |
3140 | * an OUT endpoint, we may as well do this if in future the |
3141 | * code is changed to make each endpoint's direction changeable. | |
3142 | */ | |
3143 | ||
94cb8fd6 LM |
3144 | ptxfifo = readl(hsotg->regs + DPTXFSIZn(epnum)); |
3145 | hs_ep->fifo_size = DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4; | |
5b7d70c6 | 3146 | |
8b9bc460 LM |
3147 | /* |
3148 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
3149 | * to be something valid. |
3150 | */ | |
3151 | ||
3152 | if (using_dma(hsotg)) { | |
94cb8fd6 LM |
3153 | u32 next = DxEPCTL_NextEp((epnum + 1) % 15); |
3154 | writel(next, hsotg->regs + DIEPCTL(epnum)); | |
3155 | writel(next, hsotg->regs + DOEPCTL(epnum)); | |
5b7d70c6 BD |
3156 | } |
3157 | } | |
3158 | ||
b3f489b2 LM |
3159 | /** |
3160 | * s3c_hsotg_hw_cfg - read HW configuration registers | |
3161 | * @param: The device state | |
3162 | * | |
3163 | * Read the USB core HW configuration registers | |
3164 | */ | |
3165 | static void s3c_hsotg_hw_cfg(struct s3c_hsotg *hsotg) | |
5b7d70c6 | 3166 | { |
b3f489b2 LM |
3167 | u32 cfg2, cfg4; |
3168 | /* check hardware configuration */ | |
5b7d70c6 | 3169 | |
b3f489b2 LM |
3170 | cfg2 = readl(hsotg->regs + 0x48); |
3171 | hsotg->num_of_eps = (cfg2 >> 10) & 0xF; | |
10aebc77 | 3172 | |
b3f489b2 | 3173 | dev_info(hsotg->dev, "EPs:%d\n", hsotg->num_of_eps); |
10aebc77 BD |
3174 | |
3175 | cfg4 = readl(hsotg->regs + 0x50); | |
3176 | hsotg->dedicated_fifos = (cfg4 >> 25) & 1; | |
3177 | ||
3178 | dev_info(hsotg->dev, "%s fifos\n", | |
3179 | hsotg->dedicated_fifos ? "dedicated" : "shared"); | |
5b7d70c6 BD |
3180 | } |
3181 | ||
8b9bc460 LM |
3182 | /** |
3183 | * s3c_hsotg_dump - dump state of the udc | |
3184 | * @param: The device state | |
3185 | */ | |
5b7d70c6 BD |
3186 | static void s3c_hsotg_dump(struct s3c_hsotg *hsotg) |
3187 | { | |
83a01804 | 3188 | #ifdef DEBUG |
5b7d70c6 BD |
3189 | struct device *dev = hsotg->dev; |
3190 | void __iomem *regs = hsotg->regs; | |
3191 | u32 val; | |
3192 | int idx; | |
3193 | ||
3194 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
94cb8fd6 LM |
3195 | readl(regs + DCFG), readl(regs + DCTL), |
3196 | readl(regs + DIEPMSK)); | |
5b7d70c6 BD |
3197 | |
3198 | dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n", | |
94cb8fd6 | 3199 | readl(regs + GAHBCFG), readl(regs + 0x44)); |
5b7d70c6 BD |
3200 | |
3201 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
94cb8fd6 | 3202 | readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ)); |
5b7d70c6 BD |
3203 | |
3204 | /* show periodic fifo settings */ | |
3205 | ||
3206 | for (idx = 1; idx <= 15; idx++) { | |
94cb8fd6 | 3207 | val = readl(regs + DPTXFSIZn(idx)); |
5b7d70c6 | 3208 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
94cb8fd6 LM |
3209 | val >> DPTXFSIZn_DPTxFSize_SHIFT, |
3210 | val & DPTXFSIZn_DPTxFStAddr_MASK); | |
5b7d70c6 BD |
3211 | } |
3212 | ||
3213 | for (idx = 0; idx < 15; idx++) { | |
3214 | dev_info(dev, | |
3215 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
94cb8fd6 LM |
3216 | readl(regs + DIEPCTL(idx)), |
3217 | readl(regs + DIEPTSIZ(idx)), | |
3218 | readl(regs + DIEPDMA(idx))); | |
5b7d70c6 | 3219 | |
94cb8fd6 | 3220 | val = readl(regs + DOEPCTL(idx)); |
5b7d70c6 BD |
3221 | dev_info(dev, |
3222 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
94cb8fd6 LM |
3223 | idx, readl(regs + DOEPCTL(idx)), |
3224 | readl(regs + DOEPTSIZ(idx)), | |
3225 | readl(regs + DOEPDMA(idx))); | |
5b7d70c6 BD |
3226 | |
3227 | } | |
3228 | ||
3229 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
94cb8fd6 | 3230 | readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE)); |
83a01804 | 3231 | #endif |
5b7d70c6 BD |
3232 | } |
3233 | ||
5b7d70c6 BD |
3234 | /** |
3235 | * state_show - debugfs: show overall driver and device state. | |
3236 | * @seq: The seq file to write to. | |
3237 | * @v: Unused parameter. | |
3238 | * | |
3239 | * This debugfs entry shows the overall state of the hardware and | |
3240 | * some general information about each of the endpoints available | |
3241 | * to the system. | |
3242 | */ | |
3243 | static int state_show(struct seq_file *seq, void *v) | |
3244 | { | |
3245 | struct s3c_hsotg *hsotg = seq->private; | |
3246 | void __iomem *regs = hsotg->regs; | |
3247 | int idx; | |
3248 | ||
3249 | seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", | |
94cb8fd6 LM |
3250 | readl(regs + DCFG), |
3251 | readl(regs + DCTL), | |
3252 | readl(regs + DSTS)); | |
5b7d70c6 BD |
3253 | |
3254 | seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n", | |
94cb8fd6 | 3255 | readl(regs + DIEPMSK), readl(regs + DOEPMSK)); |
5b7d70c6 BD |
3256 | |
3257 | seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n", | |
94cb8fd6 LM |
3258 | readl(regs + GINTMSK), |
3259 | readl(regs + GINTSTS)); | |
5b7d70c6 BD |
3260 | |
3261 | seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n", | |
94cb8fd6 LM |
3262 | readl(regs + DAINTMSK), |
3263 | readl(regs + DAINT)); | |
5b7d70c6 BD |
3264 | |
3265 | seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n", | |
94cb8fd6 LM |
3266 | readl(regs + GNPTXSTS), |
3267 | readl(regs + GRXSTSR)); | |
5b7d70c6 | 3268 | |
a023da33 | 3269 | seq_puts(seq, "\nEndpoint status:\n"); |
5b7d70c6 BD |
3270 | |
3271 | for (idx = 0; idx < 15; idx++) { | |
3272 | u32 in, out; | |
3273 | ||
94cb8fd6 LM |
3274 | in = readl(regs + DIEPCTL(idx)); |
3275 | out = readl(regs + DOEPCTL(idx)); | |
5b7d70c6 BD |
3276 | |
3277 | seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x", | |
3278 | idx, in, out); | |
3279 | ||
94cb8fd6 LM |
3280 | in = readl(regs + DIEPTSIZ(idx)); |
3281 | out = readl(regs + DOEPTSIZ(idx)); | |
5b7d70c6 BD |
3282 | |
3283 | seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x", | |
3284 | in, out); | |
3285 | ||
a023da33 | 3286 | seq_puts(seq, "\n"); |
5b7d70c6 BD |
3287 | } |
3288 | ||
3289 | return 0; | |
3290 | } | |
3291 | ||
3292 | static int state_open(struct inode *inode, struct file *file) | |
3293 | { | |
3294 | return single_open(file, state_show, inode->i_private); | |
3295 | } | |
3296 | ||
3297 | static const struct file_operations state_fops = { | |
3298 | .owner = THIS_MODULE, | |
3299 | .open = state_open, | |
3300 | .read = seq_read, | |
3301 | .llseek = seq_lseek, | |
3302 | .release = single_release, | |
3303 | }; | |
3304 | ||
3305 | /** | |
3306 | * fifo_show - debugfs: show the fifo information | |
3307 | * @seq: The seq_file to write data to. | |
3308 | * @v: Unused parameter. | |
3309 | * | |
3310 | * Show the FIFO information for the overall fifo and all the | |
3311 | * periodic transmission FIFOs. | |
8b9bc460 | 3312 | */ |
5b7d70c6 BD |
3313 | static int fifo_show(struct seq_file *seq, void *v) |
3314 | { | |
3315 | struct s3c_hsotg *hsotg = seq->private; | |
3316 | void __iomem *regs = hsotg->regs; | |
3317 | u32 val; | |
3318 | int idx; | |
3319 | ||
a023da33 | 3320 | seq_puts(seq, "Non-periodic FIFOs:\n"); |
94cb8fd6 | 3321 | seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ)); |
5b7d70c6 | 3322 | |
94cb8fd6 | 3323 | val = readl(regs + GNPTXFSIZ); |
5b7d70c6 | 3324 | seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n", |
94cb8fd6 LM |
3325 | val >> GNPTXFSIZ_NPTxFDep_SHIFT, |
3326 | val & GNPTXFSIZ_NPTxFStAddr_MASK); | |
5b7d70c6 | 3327 | |
a023da33 | 3328 | seq_puts(seq, "\nPeriodic TXFIFOs:\n"); |
5b7d70c6 BD |
3329 | |
3330 | for (idx = 1; idx <= 15; idx++) { | |
94cb8fd6 | 3331 | val = readl(regs + DPTXFSIZn(idx)); |
5b7d70c6 BD |
3332 | |
3333 | seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx, | |
94cb8fd6 LM |
3334 | val >> DPTXFSIZn_DPTxFSize_SHIFT, |
3335 | val & DPTXFSIZn_DPTxFStAddr_MASK); | |
5b7d70c6 BD |
3336 | } |
3337 | ||
3338 | return 0; | |
3339 | } | |
3340 | ||
3341 | static int fifo_open(struct inode *inode, struct file *file) | |
3342 | { | |
3343 | return single_open(file, fifo_show, inode->i_private); | |
3344 | } | |
3345 | ||
3346 | static const struct file_operations fifo_fops = { | |
3347 | .owner = THIS_MODULE, | |
3348 | .open = fifo_open, | |
3349 | .read = seq_read, | |
3350 | .llseek = seq_lseek, | |
3351 | .release = single_release, | |
3352 | }; | |
3353 | ||
3354 | ||
3355 | static const char *decode_direction(int is_in) | |
3356 | { | |
3357 | return is_in ? "in" : "out"; | |
3358 | } | |
3359 | ||
3360 | /** | |
3361 | * ep_show - debugfs: show the state of an endpoint. | |
3362 | * @seq: The seq_file to write data to. | |
3363 | * @v: Unused parameter. | |
3364 | * | |
3365 | * This debugfs entry shows the state of the given endpoint (one is | |
3366 | * registered for each available). | |
8b9bc460 | 3367 | */ |
5b7d70c6 BD |
3368 | static int ep_show(struct seq_file *seq, void *v) |
3369 | { | |
3370 | struct s3c_hsotg_ep *ep = seq->private; | |
3371 | struct s3c_hsotg *hsotg = ep->parent; | |
3372 | struct s3c_hsotg_req *req; | |
3373 | void __iomem *regs = hsotg->regs; | |
3374 | int index = ep->index; | |
3375 | int show_limit = 15; | |
3376 | unsigned long flags; | |
3377 | ||
3378 | seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n", | |
3379 | ep->index, ep->ep.name, decode_direction(ep->dir_in)); | |
3380 | ||
3381 | /* first show the register state */ | |
3382 | ||
3383 | seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n", | |
94cb8fd6 LM |
3384 | readl(regs + DIEPCTL(index)), |
3385 | readl(regs + DOEPCTL(index))); | |
5b7d70c6 BD |
3386 | |
3387 | seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n", | |
94cb8fd6 LM |
3388 | readl(regs + DIEPDMA(index)), |
3389 | readl(regs + DOEPDMA(index))); | |
5b7d70c6 BD |
3390 | |
3391 | seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n", | |
94cb8fd6 LM |
3392 | readl(regs + DIEPINT(index)), |
3393 | readl(regs + DOEPINT(index))); | |
5b7d70c6 BD |
3394 | |
3395 | seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n", | |
94cb8fd6 LM |
3396 | readl(regs + DIEPTSIZ(index)), |
3397 | readl(regs + DOEPTSIZ(index))); | |
5b7d70c6 | 3398 | |
a023da33 | 3399 | seq_puts(seq, "\n"); |
5b7d70c6 BD |
3400 | seq_printf(seq, "mps %d\n", ep->ep.maxpacket); |
3401 | seq_printf(seq, "total_data=%ld\n", ep->total_data); | |
3402 | ||
3403 | seq_printf(seq, "request list (%p,%p):\n", | |
3404 | ep->queue.next, ep->queue.prev); | |
3405 | ||
22258f49 | 3406 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 BD |
3407 | |
3408 | list_for_each_entry(req, &ep->queue, queue) { | |
3409 | if (--show_limit < 0) { | |
a023da33 | 3410 | seq_puts(seq, "not showing more requests...\n"); |
5b7d70c6 BD |
3411 | break; |
3412 | } | |
3413 | ||
3414 | seq_printf(seq, "%c req %p: %d bytes @%p, ", | |
3415 | req == ep->req ? '*' : ' ', | |
3416 | req, req->req.length, req->req.buf); | |
3417 | seq_printf(seq, "%d done, res %d\n", | |
3418 | req->req.actual, req->req.status); | |
3419 | } | |
3420 | ||
22258f49 | 3421 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
3422 | |
3423 | return 0; | |
3424 | } | |
3425 | ||
3426 | static int ep_open(struct inode *inode, struct file *file) | |
3427 | { | |
3428 | return single_open(file, ep_show, inode->i_private); | |
3429 | } | |
3430 | ||
3431 | static const struct file_operations ep_fops = { | |
3432 | .owner = THIS_MODULE, | |
3433 | .open = ep_open, | |
3434 | .read = seq_read, | |
3435 | .llseek = seq_lseek, | |
3436 | .release = single_release, | |
3437 | }; | |
3438 | ||
3439 | /** | |
3440 | * s3c_hsotg_create_debug - create debugfs directory and files | |
3441 | * @hsotg: The driver state | |
3442 | * | |
3443 | * Create the debugfs files to allow the user to get information | |
3444 | * about the state of the system. The directory name is created | |
3445 | * with the same name as the device itself, in case we end up | |
3446 | * with multiple blocks in future systems. | |
8b9bc460 | 3447 | */ |
41ac7b3a | 3448 | static void s3c_hsotg_create_debug(struct s3c_hsotg *hsotg) |
5b7d70c6 BD |
3449 | { |
3450 | struct dentry *root; | |
3451 | unsigned epidx; | |
3452 | ||
3453 | root = debugfs_create_dir(dev_name(hsotg->dev), NULL); | |
3454 | hsotg->debug_root = root; | |
3455 | if (IS_ERR(root)) { | |
3456 | dev_err(hsotg->dev, "cannot create debug root\n"); | |
3457 | return; | |
3458 | } | |
3459 | ||
3460 | /* create general state file */ | |
3461 | ||
3462 | hsotg->debug_file = debugfs_create_file("state", 0444, root, | |
3463 | hsotg, &state_fops); | |
3464 | ||
3465 | if (IS_ERR(hsotg->debug_file)) | |
3466 | dev_err(hsotg->dev, "%s: failed to create state\n", __func__); | |
3467 | ||
3468 | hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root, | |
3469 | hsotg, &fifo_fops); | |
3470 | ||
3471 | if (IS_ERR(hsotg->debug_fifo)) | |
3472 | dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__); | |
3473 | ||
3474 | /* create one file for each endpoint */ | |
3475 | ||
b3f489b2 | 3476 | for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) { |
5b7d70c6 BD |
3477 | struct s3c_hsotg_ep *ep = &hsotg->eps[epidx]; |
3478 | ||
3479 | ep->debugfs = debugfs_create_file(ep->name, 0444, | |
3480 | root, ep, &ep_fops); | |
3481 | ||
3482 | if (IS_ERR(ep->debugfs)) | |
3483 | dev_err(hsotg->dev, "failed to create %s debug file\n", | |
3484 | ep->name); | |
3485 | } | |
3486 | } | |
3487 | ||
3488 | /** | |
3489 | * s3c_hsotg_delete_debug - cleanup debugfs entries | |
3490 | * @hsotg: The driver state | |
3491 | * | |
3492 | * Cleanup (remove) the debugfs files for use on module exit. | |
8b9bc460 | 3493 | */ |
fb4e98ab | 3494 | static void s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg) |
5b7d70c6 BD |
3495 | { |
3496 | unsigned epidx; | |
3497 | ||
b3f489b2 | 3498 | for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) { |
5b7d70c6 BD |
3499 | struct s3c_hsotg_ep *ep = &hsotg->eps[epidx]; |
3500 | debugfs_remove(ep->debugfs); | |
3501 | } | |
3502 | ||
3503 | debugfs_remove(hsotg->debug_file); | |
3504 | debugfs_remove(hsotg->debug_fifo); | |
3505 | debugfs_remove(hsotg->debug_root); | |
3506 | } | |
3507 | ||
8b9bc460 LM |
3508 | /** |
3509 | * s3c_hsotg_probe - probe function for hsotg driver | |
3510 | * @pdev: The platform information for the driver | |
3511 | */ | |
f026a52d | 3512 | |
41ac7b3a | 3513 | static int s3c_hsotg_probe(struct platform_device *pdev) |
5b7d70c6 | 3514 | { |
e01ee9f5 | 3515 | struct s3c_hsotg_plat *plat = dev_get_platdata(&pdev->dev); |
b2e587db | 3516 | struct usb_phy *phy; |
5b7d70c6 | 3517 | struct device *dev = &pdev->dev; |
b3f489b2 | 3518 | struct s3c_hsotg_ep *eps; |
5b7d70c6 BD |
3519 | struct s3c_hsotg *hsotg; |
3520 | struct resource *res; | |
3521 | int epnum; | |
3522 | int ret; | |
fc9a731e | 3523 | int i; |
5b7d70c6 | 3524 | |
338edabc | 3525 | hsotg = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsotg), GFP_KERNEL); |
5b7d70c6 BD |
3526 | if (!hsotg) { |
3527 | dev_err(dev, "cannot get memory\n"); | |
3528 | return -ENOMEM; | |
3529 | } | |
3530 | ||
b2e587db | 3531 | phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); |
f4f5ba5e | 3532 | if (IS_ERR(phy)) { |
b2e587db | 3533 | /* Fallback for pdata */ |
e01ee9f5 | 3534 | plat = dev_get_platdata(&pdev->dev); |
b2e587db PP |
3535 | if (!plat) { |
3536 | dev_err(&pdev->dev, "no platform data or transceiver defined\n"); | |
3537 | return -EPROBE_DEFER; | |
3538 | } else { | |
3539 | hsotg->plat = plat; | |
3540 | } | |
3541 | } else { | |
3542 | hsotg->phy = phy; | |
3543 | } | |
3544 | ||
5b7d70c6 | 3545 | hsotg->dev = dev; |
5b7d70c6 | 3546 | |
84749c6d | 3547 | hsotg->clk = devm_clk_get(&pdev->dev, "otg"); |
31ee04de MS |
3548 | if (IS_ERR(hsotg->clk)) { |
3549 | dev_err(dev, "cannot get otg clock\n"); | |
338edabc | 3550 | return PTR_ERR(hsotg->clk); |
31ee04de MS |
3551 | } |
3552 | ||
5b7d70c6 BD |
3553 | platform_set_drvdata(pdev, hsotg); |
3554 | ||
3555 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
5b7d70c6 | 3556 | |
148e1134 TR |
3557 | hsotg->regs = devm_ioremap_resource(&pdev->dev, res); |
3558 | if (IS_ERR(hsotg->regs)) { | |
3559 | ret = PTR_ERR(hsotg->regs); | |
338edabc | 3560 | goto err_clk; |
5b7d70c6 BD |
3561 | } |
3562 | ||
3563 | ret = platform_get_irq(pdev, 0); | |
3564 | if (ret < 0) { | |
3565 | dev_err(dev, "cannot find IRQ\n"); | |
338edabc | 3566 | goto err_clk; |
5b7d70c6 BD |
3567 | } |
3568 | ||
22258f49 LM |
3569 | spin_lock_init(&hsotg->lock); |
3570 | ||
5b7d70c6 BD |
3571 | hsotg->irq = ret; |
3572 | ||
338edabc SK |
3573 | ret = devm_request_irq(&pdev->dev, hsotg->irq, s3c_hsotg_irq, 0, |
3574 | dev_name(dev), hsotg); | |
5b7d70c6 BD |
3575 | if (ret < 0) { |
3576 | dev_err(dev, "cannot claim IRQ\n"); | |
338edabc | 3577 | goto err_clk; |
5b7d70c6 BD |
3578 | } |
3579 | ||
3580 | dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq); | |
3581 | ||
d327ab5b | 3582 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
5b7d70c6 BD |
3583 | hsotg->gadget.ops = &s3c_hsotg_gadget_ops; |
3584 | hsotg->gadget.name = dev_name(dev); | |
5b7d70c6 | 3585 | |
5b7d70c6 BD |
3586 | /* reset the system */ |
3587 | ||
04b4a0fc | 3588 | clk_prepare_enable(hsotg->clk); |
31ee04de | 3589 | |
fc9a731e LM |
3590 | /* regulators */ |
3591 | ||
3592 | for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++) | |
3593 | hsotg->supplies[i].supply = s3c_hsotg_supply_names[i]; | |
3594 | ||
cd76213e | 3595 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies), |
fc9a731e LM |
3596 | hsotg->supplies); |
3597 | if (ret) { | |
3598 | dev_err(dev, "failed to request supplies: %d\n", ret); | |
338edabc | 3599 | goto err_clk; |
fc9a731e LM |
3600 | } |
3601 | ||
3602 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), | |
3603 | hsotg->supplies); | |
3604 | ||
3605 | if (ret) { | |
3606 | dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret); | |
3607 | goto err_supplies; | |
3608 | } | |
3609 | ||
41188786 LM |
3610 | /* usb phy enable */ |
3611 | s3c_hsotg_phy_enable(hsotg); | |
5b7d70c6 | 3612 | |
5b7d70c6 BD |
3613 | s3c_hsotg_corereset(hsotg); |
3614 | s3c_hsotg_init(hsotg); | |
b3f489b2 LM |
3615 | s3c_hsotg_hw_cfg(hsotg); |
3616 | ||
3617 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ | |
3618 | ||
3619 | if (hsotg->num_of_eps == 0) { | |
3620 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
dfdda5a0 | 3621 | ret = -EINVAL; |
b3f489b2 LM |
3622 | goto err_supplies; |
3623 | } | |
3624 | ||
3625 | eps = kcalloc(hsotg->num_of_eps + 1, sizeof(struct s3c_hsotg_ep), | |
3626 | GFP_KERNEL); | |
3627 | if (!eps) { | |
3628 | dev_err(dev, "cannot get memory\n"); | |
dfdda5a0 | 3629 | ret = -ENOMEM; |
b3f489b2 LM |
3630 | goto err_supplies; |
3631 | } | |
3632 | ||
3633 | hsotg->eps = eps; | |
3634 | ||
3635 | /* setup endpoint information */ | |
3636 | ||
3637 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
3638 | hsotg->gadget.ep0 = &hsotg->eps[0].ep; | |
3639 | ||
3640 | /* allocate EP0 request */ | |
3641 | ||
3642 | hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep, | |
3643 | GFP_KERNEL); | |
3644 | if (!hsotg->ctrl_req) { | |
3645 | dev_err(dev, "failed to allocate ctrl req\n"); | |
dfdda5a0 | 3646 | ret = -ENOMEM; |
b3f489b2 LM |
3647 | goto err_ep_mem; |
3648 | } | |
5b7d70c6 BD |
3649 | |
3650 | /* initialise the endpoints now the core has been initialised */ | |
b3f489b2 | 3651 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) |
5b7d70c6 BD |
3652 | s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum); |
3653 | ||
f65f0f10 LM |
3654 | /* disable power and clock */ |
3655 | ||
3656 | ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
3657 | hsotg->supplies); | |
3658 | if (ret) { | |
3659 | dev_err(hsotg->dev, "failed to disable supplies: %d\n", ret); | |
3660 | goto err_ep_mem; | |
3661 | } | |
3662 | ||
3663 | s3c_hsotg_phy_disable(hsotg); | |
3664 | ||
0f91349b SAS |
3665 | ret = usb_add_gadget_udc(&pdev->dev, &hsotg->gadget); |
3666 | if (ret) | |
b3f489b2 | 3667 | goto err_ep_mem; |
0f91349b | 3668 | |
5b7d70c6 BD |
3669 | s3c_hsotg_create_debug(hsotg); |
3670 | ||
3671 | s3c_hsotg_dump(hsotg); | |
3672 | ||
5b7d70c6 BD |
3673 | return 0; |
3674 | ||
1d144c67 | 3675 | err_ep_mem: |
b3f489b2 | 3676 | kfree(eps); |
fc9a731e | 3677 | err_supplies: |
41188786 | 3678 | s3c_hsotg_phy_disable(hsotg); |
31ee04de | 3679 | err_clk: |
1d144c67 | 3680 | clk_disable_unprepare(hsotg->clk); |
338edabc | 3681 | |
5b7d70c6 BD |
3682 | return ret; |
3683 | } | |
3684 | ||
8b9bc460 LM |
3685 | /** |
3686 | * s3c_hsotg_remove - remove function for hsotg driver | |
3687 | * @pdev: The platform information for the driver | |
3688 | */ | |
fb4e98ab | 3689 | static int s3c_hsotg_remove(struct platform_device *pdev) |
5b7d70c6 BD |
3690 | { |
3691 | struct s3c_hsotg *hsotg = platform_get_drvdata(pdev); | |
3692 | ||
0f91349b SAS |
3693 | usb_del_gadget_udc(&hsotg->gadget); |
3694 | ||
5b7d70c6 BD |
3695 | s3c_hsotg_delete_debug(hsotg); |
3696 | ||
f65f0f10 LM |
3697 | if (hsotg->driver) { |
3698 | /* should have been done already by driver model core */ | |
3699 | usb_gadget_unregister_driver(hsotg->driver); | |
3700 | } | |
5b7d70c6 | 3701 | |
41188786 | 3702 | s3c_hsotg_phy_disable(hsotg); |
04b4a0fc | 3703 | clk_disable_unprepare(hsotg->clk); |
31ee04de | 3704 | |
5b7d70c6 BD |
3705 | return 0; |
3706 | } | |
3707 | ||
3708 | #if 1 | |
3709 | #define s3c_hsotg_suspend NULL | |
3710 | #define s3c_hsotg_resume NULL | |
3711 | #endif | |
3712 | ||
c50f056c TF |
3713 | #ifdef CONFIG_OF |
3714 | static const struct of_device_id s3c_hsotg_of_ids[] = { | |
3715 | { .compatible = "samsung,s3c6400-hsotg", }, | |
3716 | { /* sentinel */ } | |
3717 | }; | |
3718 | MODULE_DEVICE_TABLE(of, s3c_hsotg_of_ids); | |
3719 | #endif | |
3720 | ||
5b7d70c6 BD |
3721 | static struct platform_driver s3c_hsotg_driver = { |
3722 | .driver = { | |
3723 | .name = "s3c-hsotg", | |
3724 | .owner = THIS_MODULE, | |
c50f056c | 3725 | .of_match_table = of_match_ptr(s3c_hsotg_of_ids), |
5b7d70c6 BD |
3726 | }, |
3727 | .probe = s3c_hsotg_probe, | |
7690417d | 3728 | .remove = s3c_hsotg_remove, |
5b7d70c6 BD |
3729 | .suspend = s3c_hsotg_suspend, |
3730 | .resume = s3c_hsotg_resume, | |
3731 | }; | |
3732 | ||
cc27c96c | 3733 | module_platform_driver(s3c_hsotg_driver); |
5b7d70c6 BD |
3734 | |
3735 | MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device"); | |
3736 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
3737 | MODULE_LICENSE("GPL"); | |
3738 | MODULE_ALIAS("platform:s3c-hsotg"); |