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d75379a5 RJ |
1 | /* |
2 | * linux/drivers/usb/gadget/pxa27x_udc.h | |
3 | * Intel PXA27x on-chip full speed USB device controller | |
4 | * | |
5 | * Inspired by original driver by Frank Becker, David Brownell, and others. | |
6 | * Copyright (C) 2008 Robert Jarzmik | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
d75379a5 RJ |
12 | */ |
13 | ||
14 | #ifndef __LINUX_USB_GADGET_PXA27X_H | |
15 | #define __LINUX_USB_GADGET_PXA27X_H | |
16 | ||
17 | #include <linux/types.h> | |
18 | #include <linux/spinlock.h> | |
19 | #include <linux/io.h> | |
7fec3c25 | 20 | #include <linux/usb/otg.h> |
d75379a5 RJ |
21 | |
22 | /* | |
23 | * Register definitions | |
24 | */ | |
25 | /* Offsets */ | |
26 | #define UDCCR 0x0000 /* UDC Control Register */ | |
27 | #define UDCICR0 0x0004 /* UDC Interrupt Control Register0 */ | |
28 | #define UDCICR1 0x0008 /* UDC Interrupt Control Register1 */ | |
29 | #define UDCISR0 0x000C /* UDC Interrupt Status Register 0 */ | |
30 | #define UDCISR1 0x0010 /* UDC Interrupt Status Register 1 */ | |
31 | #define UDCFNR 0x0014 /* UDC Frame Number Register */ | |
32 | #define UDCOTGICR 0x0018 /* UDC On-The-Go interrupt control */ | |
33 | #define UP2OCR 0x0020 /* USB Port 2 Output Control register */ | |
34 | #define UP3OCR 0x0024 /* USB Port 3 Output Control register */ | |
35 | #define UDCCSRn(x) (0x0100 + ((x)<<2)) /* UDC Control/Status register */ | |
36 | #define UDCBCRn(x) (0x0200 + ((x)<<2)) /* UDC Byte Count Register */ | |
37 | #define UDCDRn(x) (0x0300 + ((x)<<2)) /* UDC Data Register */ | |
38 | #define UDCCRn(x) (0x0400 + ((x)<<2)) /* UDC Control Register */ | |
39 | ||
40 | #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ | |
41 | #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation | |
42 | Protocol Port Support */ | |
43 | #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol | |
44 | Support */ | |
45 | #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol | |
46 | Enable */ | |
47 | #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */ | |
48 | #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */ | |
49 | #define UDCCR_ACN_S 11 | |
50 | #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */ | |
51 | #define UDCCR_AIN_S 8 | |
52 | #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface | |
53 | Setting Number */ | |
54 | #define UDCCR_AAISN_S 5 | |
55 | #define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active | |
56 | Configuration */ | |
57 | #define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration | |
58 | Error */ | |
59 | #define UDCCR_UDR (1 << 2) /* UDC Resume */ | |
60 | #define UDCCR_UDA (1 << 1) /* UDC Active */ | |
61 | #define UDCCR_UDE (1 << 0) /* UDC Enable */ | |
62 | ||
63 | #define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) | |
64 | #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */ | |
65 | #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ | |
66 | #define UDCICR1_IERU (1 << 29) /* IntEn - Resume */ | |
67 | #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ | |
68 | #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ | |
69 | #define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ | |
70 | #define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ | |
71 | #define UDCICR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL) | |
72 | ||
73 | #define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) | |
74 | #define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */ | |
75 | #define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */ | |
76 | #define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */ | |
77 | #define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */ | |
78 | #define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */ | |
79 | #define UDCISR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL) | |
80 | ||
81 | #define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ | |
7c9d440e | 82 | #define UDCOTGICR_IEXR (1 << 17) /* Extra Transceiver Interrupt |
d75379a5 | 83 | Rising Edge Interrupt Enable */ |
7c9d440e | 84 | #define UDCOTGICR_IEXF (1 << 16) /* Extra Transceiver Interrupt |
d75379a5 RJ |
85 | Falling Edge Interrupt Enable */ |
86 | #define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge | |
87 | Interrupt Enable */ | |
88 | #define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge | |
89 | Interrupt Enable */ | |
90 | #define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge | |
91 | Interrupt Enable */ | |
92 | #define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge | |
93 | Interrupt Enable */ | |
94 | #define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge | |
95 | Interrupt Enable */ | |
96 | #define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge | |
97 | Interrupt Enable */ | |
98 | #define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising | |
99 | Edge Interrupt Enable */ | |
100 | #define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling | |
101 | Edge Interrupt Enable */ | |
102 | #define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge | |
103 | Interrupt Enable */ | |
104 | #define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge | |
105 | Interrupt Enable */ | |
106 | ||
107 | /* Host Port 2 field bits */ | |
108 | #define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */ | |
109 | #define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */ | |
110 | /* Transceiver enablers */ | |
111 | #define UP2OCR_DPPDE (1 << 2) /* D+ Pull Down Enable */ | |
112 | #define UP2OCR_DMPDE (1 << 3) /* D- Pull Down Enable */ | |
113 | #define UP2OCR_DPPUE (1 << 4) /* D+ Pull Up Enable */ | |
114 | #define UP2OCR_DMPUE (1 << 5) /* D- Pull Up Enable */ | |
115 | #define UP2OCR_DPPUBE (1 << 6) /* D+ Pull Up Bypass Enable */ | |
116 | #define UP2OCR_DMPUBE (1 << 7) /* D- Pull Up Bypass Enable */ | |
117 | #define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */ | |
118 | #define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */ | |
119 | #define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ | |
120 | #define UP2OCR_HXS (1 << 16) /* Transceiver Output Select */ | |
121 | #define UP2OCR_HXOE (1 << 17) /* Transceiver Output Enable */ | |
122 | #define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */ | |
123 | ||
367815ee RJ |
124 | #define UDCCSR0_ACM (1 << 9) /* Ack Control Mode */ |
125 | #define UDCCSR0_AREN (1 << 8) /* Ack Response Enable */ | |
d75379a5 RJ |
126 | #define UDCCSR0_SA (1 << 7) /* Setup Active */ |
127 | #define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ | |
128 | #define UDCCSR0_FST (1 << 5) /* Force Stall */ | |
129 | #define UDCCSR0_SST (1 << 4) /* Sent Stall */ | |
130 | #define UDCCSR0_DME (1 << 3) /* DMA Enable */ | |
131 | #define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ | |
132 | #define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ | |
133 | #define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ | |
134 | ||
135 | #define UDCCSR_DPE (1 << 9) /* Data Packet Error */ | |
136 | #define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ | |
137 | #define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */ | |
138 | #define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */ | |
139 | #define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */ | |
140 | #define UDCCSR_FST (1 << 5) /* Force STALL */ | |
141 | #define UDCCSR_SST (1 << 4) /* Sent STALL */ | |
142 | #define UDCCSR_DME (1 << 3) /* DMA Enable */ | |
143 | #define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */ | |
144 | #define UDCCSR_PC (1 << 1) /* Packet Complete */ | |
145 | #define UDCCSR_FS (1 << 0) /* FIFO needs service */ | |
146 | ||
147 | #define UDCCONR_CN (0x03 << 25) /* Configuration Number */ | |
148 | #define UDCCONR_CN_S 25 | |
149 | #define UDCCONR_IN (0x07 << 22) /* Interface Number */ | |
150 | #define UDCCONR_IN_S 22 | |
151 | #define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */ | |
152 | #define UDCCONR_AISN_S 19 | |
153 | #define UDCCONR_EN (0x0f << 15) /* Endpoint Number */ | |
154 | #define UDCCONR_EN_S 15 | |
155 | #define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */ | |
156 | #define UDCCONR_ET_S 13 | |
157 | #define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */ | |
158 | #define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */ | |
159 | #define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */ | |
160 | #define UDCCONR_ET_NU (0x00 << 13) /* Not used */ | |
161 | #define UDCCONR_ED (1 << 12) /* Endpoint Direction */ | |
162 | #define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */ | |
163 | #define UDCCONR_MPS_S 2 | |
164 | #define UDCCONR_DE (1 << 1) /* Double Buffering Enable */ | |
165 | #define UDCCONR_EE (1 << 0) /* Endpoint Enable */ | |
166 | ||
167 | #define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_SMAC | UDCCR_UDR | UDCCR_UDE) | |
168 | #define UDCCSR_WR_MASK (UDCCSR_DME | UDCCSR_FST) | |
169 | #define UDC_FNR_MASK (0x7ff) | |
170 | #define UDC_BCR_MASK (0x3ff) | |
171 | ||
172 | /* | |
173 | * UDCCR = UDC Endpoint Configuration Registers | |
174 | * UDCCSR = UDC Control/Status Register for this EP | |
175 | * UDCBCR = UDC Byte Count Remaining (contents of OUT fifo) | |
176 | * UDCDR = UDC Endpoint Data Register (the fifo) | |
177 | */ | |
178 | #define ofs_UDCCR(ep) (UDCCRn(ep->idx)) | |
179 | #define ofs_UDCCSR(ep) (UDCCSRn(ep->idx)) | |
180 | #define ofs_UDCBCR(ep) (UDCBCRn(ep->idx)) | |
181 | #define ofs_UDCDR(ep) (UDCDRn(ep->idx)) | |
182 | ||
183 | /* Register access macros */ | |
184 | #define udc_ep_readl(ep, reg) \ | |
185 | __raw_readl((ep)->dev->regs + ofs_##reg(ep)) | |
186 | #define udc_ep_writel(ep, reg, value) \ | |
187 | __raw_writel((value), ep->dev->regs + ofs_##reg(ep)) | |
188 | #define udc_ep_readb(ep, reg) \ | |
189 | __raw_readb((ep)->dev->regs + ofs_##reg(ep)) | |
190 | #define udc_ep_writeb(ep, reg, value) \ | |
191 | __raw_writeb((value), ep->dev->regs + ofs_##reg(ep)) | |
192 | #define udc_readl(dev, reg) \ | |
193 | __raw_readl((dev)->regs + (reg)) | |
194 | #define udc_writel(udc, reg, value) \ | |
195 | __raw_writel((value), (udc)->regs + (reg)) | |
196 | ||
197 | #define UDCCSR_MASK (UDCCSR_FST | UDCCSR_DME) | |
198 | #define UDCCISR0_EP_MASK ~0 | |
199 | #define UDCCISR1_EP_MASK 0xffff | |
200 | #define UDCCSR0_CTRL_REQ_MASK (UDCCSR0_OPC | UDCCSR0_SA | UDCCSR0_RNE) | |
201 | ||
202 | #define EPIDX(ep) (ep->idx) | |
203 | #define EPADDR(ep) (ep->addr) | |
204 | #define EPXFERTYPE(ep) (ep->type) | |
205 | #define EPNAME(ep) (ep->name) | |
206 | #define is_ep0(ep) (!ep->idx) | |
207 | #define EPXFERTYPE_is_ISO(ep) (EPXFERTYPE(ep) == USB_ENDPOINT_XFER_ISOC) | |
208 | ||
209 | /* | |
210 | * Endpoint definitions | |
211 | * | |
212 | * Once enabled, pxa endpoint configuration is freezed, and cannot change | |
213 | * unless a reset happens or the udc is disabled. | |
214 | * Therefore, we must define all pxa potential endpoint definitions needed for | |
215 | * all gadget and set them up before the udc is enabled. | |
216 | * | |
217 | * As the architecture chosen is fully static, meaning the pxa endpoint | |
218 | * configurations are set up once and for all, we must provide a way to match | |
219 | * one usb endpoint (usb_ep) to several pxa endpoints. The reason is that gadget | |
220 | * layer autoconf doesn't choose the usb_ep endpoint on (config, interface, alt) | |
221 | * criteria, while the pxa architecture requires that. | |
222 | * | |
223 | * The solution is to define several pxa endpoints matching one usb_ep. Ex: | |
224 | * - "ep1-in" matches pxa endpoint EPA (which is an IN ep at addr 1, when | |
225 | * the udc talks on (config=3, interface=0, alt=0) | |
226 | * - "ep1-in" matches pxa endpoint EPB (which is an IN ep at addr 1, when | |
227 | * the udc talks on (config=3, interface=0, alt=1) | |
228 | * - "ep1-in" matches pxa endpoint EPC (which is an IN ep at addr 1, when | |
229 | * the udc talks on (config=2, interface=0, alt=0) | |
230 | * | |
231 | * We'll define the pxa endpoint by its index (EPA => idx=1, EPB => idx=2, ...) | |
232 | */ | |
233 | ||
234 | /* | |
235 | * Endpoint definition helpers | |
236 | */ | |
237 | #define USB_EP_DEF(addr, bname, dir, type, maxpkt) \ | |
238 | { .usb_ep = { .name = bname, .ops = &pxa_ep_ops, .maxpacket = maxpkt, }, \ | |
239 | .desc = { .bEndpointAddress = addr | (dir ? USB_DIR_IN : 0), \ | |
240 | .bmAttributes = type, \ | |
241 | .wMaxPacketSize = maxpkt, }, \ | |
242 | .dev = &memory \ | |
243 | } | |
244 | #define USB_EP_BULK(addr, bname, dir) \ | |
245 | USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE) | |
246 | #define USB_EP_ISO(addr, bname, dir) \ | |
247 | USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE) | |
248 | #define USB_EP_INT(addr, bname, dir) \ | |
249 | USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE) | |
250 | #define USB_EP_IN_BULK(n) USB_EP_BULK(n, "ep" #n "in-bulk", 1) | |
251 | #define USB_EP_OUT_BULK(n) USB_EP_BULK(n, "ep" #n "out-bulk", 0) | |
252 | #define USB_EP_IN_ISO(n) USB_EP_ISO(n, "ep" #n "in-iso", 1) | |
253 | #define USB_EP_OUT_ISO(n) USB_EP_ISO(n, "ep" #n "out-iso", 0) | |
254 | #define USB_EP_IN_INT(n) USB_EP_INT(n, "ep" #n "in-int", 1) | |
255 | #define USB_EP_CTRL USB_EP_DEF(0, "ep0", 0, 0, EP0_FIFO_SIZE) | |
256 | ||
257 | #define PXA_EP_DEF(_idx, _addr, dir, _type, maxpkt, _config, iface, altset) \ | |
258 | { \ | |
259 | .dev = &memory, \ | |
260 | .name = "ep" #_idx, \ | |
261 | .idx = _idx, .enabled = 0, \ | |
262 | .dir_in = dir, .addr = _addr, \ | |
263 | .config = _config, .interface = iface, .alternate = altset, \ | |
264 | .type = _type, .fifo_size = maxpkt, \ | |
265 | } | |
266 | #define PXA_EP_BULK(_idx, addr, dir, config, iface, alt) \ | |
267 | PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE, \ | |
268 | config, iface, alt) | |
269 | #define PXA_EP_ISO(_idx, addr, dir, config, iface, alt) \ | |
270 | PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE, \ | |
271 | config, iface, alt) | |
272 | #define PXA_EP_INT(_idx, addr, dir, config, iface, alt) \ | |
273 | PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE, \ | |
274 | config, iface, alt) | |
275 | #define PXA_EP_IN_BULK(i, adr, c, f, a) PXA_EP_BULK(i, adr, 1, c, f, a) | |
276 | #define PXA_EP_OUT_BULK(i, adr, c, f, a) PXA_EP_BULK(i, adr, 0, c, f, a) | |
277 | #define PXA_EP_IN_ISO(i, adr, c, f, a) PXA_EP_ISO(i, adr, 1, c, f, a) | |
278 | #define PXA_EP_OUT_ISO(i, adr, c, f, a) PXA_EP_ISO(i, adr, 0, c, f, a) | |
279 | #define PXA_EP_IN_INT(i, adr, c, f, a) PXA_EP_INT(i, adr, 1, c, f, a) | |
280 | #define PXA_EP_CTRL PXA_EP_DEF(0, 0, 0, 0, EP0_FIFO_SIZE, 0, 0, 0) | |
281 | ||
282 | struct pxa27x_udc; | |
283 | ||
284 | struct stats { | |
285 | unsigned long in_ops; | |
286 | unsigned long out_ops; | |
287 | unsigned long in_bytes; | |
288 | unsigned long out_bytes; | |
289 | unsigned long irqs; | |
290 | }; | |
291 | ||
292 | /** | |
293 | * struct udc_usb_ep - container of each usb_ep structure | |
294 | * @usb_ep: usb endpoint | |
295 | * @desc: usb descriptor, especially type and address | |
296 | * @dev: udc managing this endpoint | |
297 | * @pxa_ep: matching pxa_ep (cache of find_pxa_ep() call) | |
298 | */ | |
299 | struct udc_usb_ep { | |
300 | struct usb_ep usb_ep; | |
301 | struct usb_endpoint_descriptor desc; | |
302 | struct pxa_udc *dev; | |
303 | struct pxa_ep *pxa_ep; | |
304 | }; | |
305 | ||
306 | /** | |
307 | * struct pxa_ep - pxa endpoint | |
308 | * @dev: udc device | |
309 | * @queue: requests queue | |
310 | * @lock: lock to pxa_ep data (queues and stats) | |
311 | * @enabled: true when endpoint enabled (not stopped by gadget layer) | |
5e23e90f RJ |
312 | * @in_handle_ep: number of recursions of handle_ep() function |
313 | * Prevents deadlocks or infinite recursions of types : | |
314 | * irq->handle_ep()->req_done()->req.complete()->pxa_ep_queue()->handle_ep() | |
315 | * or | |
316 | * pxa_ep_queue()->handle_ep()->req_done()->req.complete()->pxa_ep_queue() | |
d75379a5 RJ |
317 | * @idx: endpoint index (1 => epA, 2 => epB, ..., 24 => epX) |
318 | * @name: endpoint name (for trace/debug purpose) | |
319 | * @dir_in: 1 if IN endpoint, 0 if OUT endpoint | |
320 | * @addr: usb endpoint number | |
321 | * @config: configuration in which this endpoint is active | |
322 | * @interface: interface in which this endpoint is active | |
323 | * @alternate: altsetting in which this endpoitn is active | |
324 | * @fifo_size: max packet size in the endpoint fifo | |
325 | * @type: endpoint type (bulk, iso, int, ...) | |
326 | * @udccsr_value: save register of UDCCSR0 for suspend/resume | |
327 | * @udccr_value: save register of UDCCR for suspend/resume | |
328 | * @stats: endpoint statistics | |
329 | * | |
330 | * The *PROBLEM* is that pxa's endpoint configuration scheme is both misdesigned | |
331 | * (cares about config/interface/altsetting, thus placing needless limits on | |
332 | * device capability) and full of implementation bugs forcing it to be set up | |
333 | * for use more or less like a pxa255. | |
334 | * | |
335 | * As we define the pxa_ep statically, we must guess all needed pxa_ep for all | |
336 | * gadget which may work with this udc driver. | |
337 | */ | |
338 | struct pxa_ep { | |
339 | struct pxa_udc *dev; | |
340 | ||
341 | struct list_head queue; | |
342 | spinlock_t lock; /* Protects this structure */ | |
343 | /* (queues, stats) */ | |
344 | unsigned enabled:1; | |
5e23e90f | 345 | unsigned in_handle_ep:1; |
d75379a5 RJ |
346 | |
347 | unsigned idx:5; | |
348 | char *name; | |
349 | ||
350 | /* | |
351 | * Specific pxa endpoint data, needed for hardware initialization | |
352 | */ | |
353 | unsigned dir_in:1; | |
0ff8d1b3 | 354 | unsigned addr:4; |
d75379a5 RJ |
355 | unsigned config:2; |
356 | unsigned interface:3; | |
357 | unsigned alternate:3; | |
358 | unsigned fifo_size; | |
359 | unsigned type; | |
360 | ||
361 | #ifdef CONFIG_PM | |
362 | u32 udccsr_value; | |
363 | u32 udccr_value; | |
364 | #endif | |
365 | struct stats stats; | |
366 | }; | |
367 | ||
368 | /** | |
369 | * struct pxa27x_request - container of each usb_request structure | |
370 | * @req: usb request | |
371 | * @udc_usb_ep: usb endpoint the request was submitted on | |
372 | * @in_use: sanity check if request already queued on an pxa_ep | |
373 | * @queue: linked list of requests, linked on pxa_ep->queue | |
374 | */ | |
375 | struct pxa27x_request { | |
376 | struct usb_request req; | |
377 | struct udc_usb_ep *udc_usb_ep; | |
378 | unsigned in_use:1; | |
379 | struct list_head queue; | |
380 | }; | |
381 | ||
382 | enum ep0_state { | |
383 | WAIT_FOR_SETUP, | |
384 | SETUP_STAGE, | |
385 | IN_DATA_STAGE, | |
386 | OUT_DATA_STAGE, | |
387 | IN_STATUS_STAGE, | |
388 | OUT_STATUS_STAGE, | |
389 | STALL, | |
390 | WAIT_ACK_SET_CONF_INTERF | |
391 | }; | |
392 | ||
393 | static char *ep0_state_name[] = { | |
394 | "WAIT_FOR_SETUP", "SETUP_STAGE", "IN_DATA_STAGE", "OUT_DATA_STAGE", | |
395 | "IN_STATUS_STAGE", "OUT_STATUS_STAGE", "STALL", | |
396 | "WAIT_ACK_SET_CONF_INTERF" | |
397 | }; | |
398 | #define EP0_STNAME(udc) ep0_state_name[(udc)->ep0state] | |
399 | ||
400 | #define EP0_FIFO_SIZE 16U | |
401 | #define BULK_FIFO_SIZE 64U | |
402 | #define ISO_FIFO_SIZE 256U | |
403 | #define INT_FIFO_SIZE 16U | |
404 | ||
405 | struct udc_stats { | |
406 | unsigned long irqs_reset; | |
407 | unsigned long irqs_suspend; | |
408 | unsigned long irqs_resume; | |
409 | unsigned long irqs_reconfig; | |
410 | }; | |
411 | ||
412 | #define NR_USB_ENDPOINTS (1 + 5) /* ep0 + ep1in-bulk + .. + ep3in-iso */ | |
413 | #define NR_PXA_ENDPOINTS (1 + 14) /* ep0 + epA + epB + .. + epX */ | |
414 | ||
415 | /** | |
416 | * struct pxa_udc - udc structure | |
417 | * @regs: mapped IO space | |
418 | * @irq: udc irq | |
419 | * @clk: udc clock | |
420 | * @usb_gadget: udc gadget structure | |
421 | * @driver: bound gadget (zero, g_ether, g_file_storage, ...) | |
422 | * @dev: device | |
423 | * @mach: machine info, used to activate specific GPIO | |
7fec3c25 | 424 | * @transceiver: external transceiver to handle vbus sense and D+ pullup |
d75379a5 RJ |
425 | * @ep0state: control endpoint state machine state |
426 | * @stats: statistics on udc usage | |
427 | * @udc_usb_ep: array of usb endpoints offered by the gadget | |
428 | * @pxa_ep: array of pxa available endpoints | |
eb507025 RJ |
429 | * @enabled: UDC was enabled by a previous udc_enable() |
430 | * @pullup_on: if pullup resistor connected to D+ pin | |
431 | * @pullup_resume: if pullup resistor should be connected to D+ pin on resume | |
d75379a5 RJ |
432 | * @config: UDC active configuration |
433 | * @last_interface: UDC interface of the last SET_INTERFACE host request | |
434 | * @last_alternate: UDC altsetting of the last SET_INTERFACE host request | |
435 | * @udccsr0: save of udccsr0 in case of suspend | |
436 | * @debugfs_root: root entry of debug filesystem | |
437 | * @debugfs_state: debugfs entry for "udcstate" | |
438 | * @debugfs_queues: debugfs entry for "queues" | |
439 | * @debugfs_eps: debugfs entry for "epstate" | |
440 | */ | |
441 | struct pxa_udc { | |
442 | void __iomem *regs; | |
443 | int irq; | |
444 | struct clk *clk; | |
445 | ||
446 | struct usb_gadget gadget; | |
447 | struct usb_gadget_driver *driver; | |
448 | struct device *dev; | |
449 | struct pxa2xx_udc_mach_info *mach; | |
86753811 | 450 | struct usb_phy *transceiver; |
d75379a5 RJ |
451 | |
452 | enum ep0_state ep0state; | |
453 | struct udc_stats stats; | |
454 | ||
455 | struct udc_usb_ep udc_usb_ep[NR_USB_ENDPOINTS]; | |
456 | struct pxa_ep pxa_ep[NR_PXA_ENDPOINTS]; | |
457 | ||
eb507025 RJ |
458 | unsigned enabled:1; |
459 | unsigned pullup_on:1; | |
460 | unsigned pullup_resume:1; | |
b799a7eb | 461 | unsigned vbus_sensed:1; |
d75379a5 RJ |
462 | unsigned config:2; |
463 | unsigned last_interface:3; | |
464 | unsigned last_alternate:3; | |
465 | ||
466 | #ifdef CONFIG_PM | |
467 | unsigned udccsr0; | |
468 | #endif | |
469 | #ifdef CONFIG_USB_GADGET_DEBUG_FS | |
470 | struct dentry *debugfs_root; | |
471 | struct dentry *debugfs_state; | |
472 | struct dentry *debugfs_queues; | |
473 | struct dentry *debugfs_eps; | |
474 | #endif | |
475 | }; | |
476 | ||
477 | static inline struct pxa_udc *to_gadget_udc(struct usb_gadget *gadget) | |
478 | { | |
479 | return container_of(gadget, struct pxa_udc, gadget); | |
480 | } | |
481 | ||
482 | /* | |
483 | * Debugging/message support | |
484 | */ | |
485 | #define ep_dbg(ep, fmt, arg...) \ | |
486 | dev_dbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg) | |
487 | #define ep_vdbg(ep, fmt, arg...) \ | |
488 | dev_vdbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg) | |
489 | #define ep_err(ep, fmt, arg...) \ | |
490 | dev_err(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg) | |
491 | #define ep_info(ep, fmt, arg...) \ | |
492 | dev_info(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg) | |
493 | #define ep_warn(ep, fmt, arg...) \ | |
494 | dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg) | |
495 | ||
496 | #endif /* __LINUX_USB_GADGET_PXA27X_H */ |