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usb: gadget: Clear usb_endpoint_descriptor inside the struct usb_ep on disable
[linux-2.6-block.git] / drivers / usb / gadget / langwell_udc.c
CommitLineData
5be19a9d
XS		 1/*
2 * Intel Langwell USB Device Controller driver
3 * Copyright (C) 2008-2009, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
5be19a9d
XS		 8 */
9
10
11/* #undef DEBUG */
5f81f4b0 12/* #undef VERBOSE_DEBUG */
5be19a9d
XS		 13
14#if defined(CONFIG_USB_LANGWELL_OTG)
15#define OTG_TRANSCEIVER
16#endif
17
18
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/dma-mapping.h>
22#include <linux/kernel.h>
23#include <linux/delay.h>
24#include <linux/ioport.h>
25#include <linux/sched.h>
26#include <linux/slab.h>
5be19a9d
XS		 27#include <linux/errno.h>
28#include <linux/init.h>
29#include <linux/timer.h>
30#include <linux/list.h>
31#include <linux/interrupt.h>
32#include <linux/moduleparam.h>
33#include <linux/device.h>
34#include <linux/usb/ch9.h>
35#include <linux/usb/gadget.h>
36#include <linux/usb/otg.h>
37#include <linux/pm.h>
38#include <linux/io.h>
39#include <linux/irq.h>
40#include <asm/system.h>
41#include <asm/unaligned.h>
42
43#include "langwell_udc.h"
44
45
46#define DRIVER_DESC "Intel Langwell USB Device Controller driver"
47#define DRIVER_VERSION "16 May 2009"
48
49static const char driver_name[] = "langwell_udc";
50static const char driver_desc[] = DRIVER_DESC;
51
52
5be19a9d
XS		 53/* for endpoint 0 operations */
54static const struct usb_endpoint_descriptor
55langwell_ep0_desc = {
56 .bLength = USB_DT_ENDPOINT_SIZE,
57 .bDescriptorType = USB_DT_ENDPOINT,
58 .bEndpointAddress = 0,
59 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
60 .wMaxPacketSize = EP0_MAX_PKT_SIZE,
61};
62
63
64/*-------------------------------------------------------------------------*/
65/* debugging */
66
5f81f4b0 67#ifdef VERBOSE_DEBUG
5be19a9d
XS		 68static inline void print_all_registers(struct langwell_udc *dev)
69{
70 int i;
71
72 /* Capability Registers */
5f81f4b0
J		 73 dev_dbg(&dev->pdev->dev,
74 "Capability Registers (offset: 0x%04x, length: 0x%08x)\n",
75 CAP_REG_OFFSET, (u32)sizeof(struct langwell_cap_regs));
76 dev_dbg(&dev->pdev->dev, "caplength=0x%02x\n",
5be19a9d 77 readb(&dev->cap_regs->caplength));
5f81f4b0 78 dev_dbg(&dev->pdev->dev, "hciversion=0x%04x\n",
5be19a9d 79 readw(&dev->cap_regs->hciversion));
5f81f4b0 80 dev_dbg(&dev->pdev->dev, "hcsparams=0x%08x\n",
5be19a9d 81 readl(&dev->cap_regs->hcsparams));
5f81f4b0 82 dev_dbg(&dev->pdev->dev, "hccparams=0x%08x\n",
5be19a9d 83 readl(&dev->cap_regs->hccparams));
5f81f4b0 84 dev_dbg(&dev->pdev->dev, "dciversion=0x%04x\n",
5be19a9d 85 readw(&dev->cap_regs->dciversion));
5f81f4b0 86 dev_dbg(&dev->pdev->dev, "dccparams=0x%08x\n",
5be19a9d
XS		 87 readl(&dev->cap_regs->dccparams));
88
89 /* Operational Registers */
5f81f4b0
J		 90 dev_dbg(&dev->pdev->dev,
91 "Operational Registers (offset: 0x%04x, length: 0x%08x)\n",
92 OP_REG_OFFSET, (u32)sizeof(struct langwell_op_regs));
93 dev_dbg(&dev->pdev->dev, "extsts=0x%08x\n",
5be19a9d 94 readl(&dev->op_regs->extsts));
5f81f4b0 95 dev_dbg(&dev->pdev->dev, "extintr=0x%08x\n",
5be19a9d 96 readl(&dev->op_regs->extintr));
5f81f4b0 97 dev_dbg(&dev->pdev->dev, "usbcmd=0x%08x\n",
5be19a9d 98 readl(&dev->op_regs->usbcmd));
5f81f4b0 99 dev_dbg(&dev->pdev->dev, "usbsts=0x%08x\n",
5be19a9d 100 readl(&dev->op_regs->usbsts));
5f81f4b0 101 dev_dbg(&dev->pdev->dev, "usbintr=0x%08x\n",
5be19a9d 102 readl(&dev->op_regs->usbintr));
5f81f4b0 103 dev_dbg(&dev->pdev->dev, "frindex=0x%08x\n",
5be19a9d 104 readl(&dev->op_regs->frindex));
5f81f4b0 105 dev_dbg(&dev->pdev->dev, "ctrldssegment=0x%08x\n",
5be19a9d 106 readl(&dev->op_regs->ctrldssegment));
5f81f4b0 107 dev_dbg(&dev->pdev->dev, "deviceaddr=0x%08x\n",
5be19a9d 108 readl(&dev->op_regs->deviceaddr));
5f81f4b0 109 dev_dbg(&dev->pdev->dev, "endpointlistaddr=0x%08x\n",
5be19a9d 110 readl(&dev->op_regs->endpointlistaddr));
5f81f4b0 111 dev_dbg(&dev->pdev->dev, "ttctrl=0x%08x\n",
5be19a9d 112 readl(&dev->op_regs->ttctrl));
5f81f4b0 113 dev_dbg(&dev->pdev->dev, "burstsize=0x%08x\n",
5be19a9d 114 readl(&dev->op_regs->burstsize));
5f81f4b0 115 dev_dbg(&dev->pdev->dev, "txfilltuning=0x%08x\n",
5be19a9d 116 readl(&dev->op_regs->txfilltuning));
5f81f4b0 117 dev_dbg(&dev->pdev->dev, "txttfilltuning=0x%08x\n",
5be19a9d 118 readl(&dev->op_regs->txttfilltuning));
5f81f4b0 119 dev_dbg(&dev->pdev->dev, "ic_usb=0x%08x\n",
5be19a9d 120 readl(&dev->op_regs->ic_usb));
5f81f4b0 121 dev_dbg(&dev->pdev->dev, "ulpi_viewport=0x%08x\n",
5be19a9d 122 readl(&dev->op_regs->ulpi_viewport));
5f81f4b0 123 dev_dbg(&dev->pdev->dev, "configflag=0x%08x\n",
5be19a9d 124 readl(&dev->op_regs->configflag));
5f81f4b0 125 dev_dbg(&dev->pdev->dev, "portsc1=0x%08x\n",
5be19a9d 126 readl(&dev->op_regs->portsc1));
5f81f4b0 127 dev_dbg(&dev->pdev->dev, "devlc=0x%08x\n",
5be19a9d 128 readl(&dev->op_regs->devlc));
5f81f4b0 129 dev_dbg(&dev->pdev->dev, "otgsc=0x%08x\n",
5be19a9d 130 readl(&dev->op_regs->otgsc));
5f81f4b0 131 dev_dbg(&dev->pdev->dev, "usbmode=0x%08x\n",
5be19a9d 132 readl(&dev->op_regs->usbmode));
5f81f4b0 133 dev_dbg(&dev->pdev->dev, "endptnak=0x%08x\n",
5be19a9d 134 readl(&dev->op_regs->endptnak));
5f81f4b0 135 dev_dbg(&dev->pdev->dev, "endptnaken=0x%08x\n",
5be19a9d 136 readl(&dev->op_regs->endptnaken));
5f81f4b0 137 dev_dbg(&dev->pdev->dev, "endptsetupstat=0x%08x\n",
5be19a9d 138 readl(&dev->op_regs->endptsetupstat));
5f81f4b0 139 dev_dbg(&dev->pdev->dev, "endptprime=0x%08x\n",
5be19a9d 140 readl(&dev->op_regs->endptprime));
5f81f4b0 141 dev_dbg(&dev->pdev->dev, "endptflush=0x%08x\n",
5be19a9d 142 readl(&dev->op_regs->endptflush));
5f81f4b0 143 dev_dbg(&dev->pdev->dev, "endptstat=0x%08x\n",
5be19a9d 144 readl(&dev->op_regs->endptstat));
5f81f4b0 145 dev_dbg(&dev->pdev->dev, "endptcomplete=0x%08x\n",
5be19a9d
XS		 146 readl(&dev->op_regs->endptcomplete));
147
148 for (i = 0; i < dev->ep_max / 2; i++) {
5f81f4b0 149 dev_dbg(&dev->pdev->dev, "endptctrl[%d]=0x%08x\n",
5be19a9d
XS		 150 i, readl(&dev->op_regs->endptctrl[i]));
151 }
152}
5f81f4b0
J		 153#else
154
155#define print_all_registers(dev) do { } while (0)
156
157#endif /* VERBOSE_DEBUG */
5be19a9d
XS		 158
159
160/*-------------------------------------------------------------------------*/
161
5f81f4b0
J		 162#define is_in(ep) (((ep)->ep_num == 0) ? ((ep)->dev->ep0_dir == \
163 USB_DIR_IN) : (usb_endpoint_dir_in((ep)->desc)))
5be19a9d 164
5f81f4b0 165#define DIR_STRING(ep) (is_in(ep) ? "in" : "out")
5be19a9d
XS		 166
167
5f81f4b0 168static char *type_string(const struct usb_endpoint_descriptor *desc)
5be19a9d 169{
5f81f4b0 170 switch (usb_endpoint_type(desc)) {
5be19a9d
XS		 171 case USB_ENDPOINT_XFER_BULK:
172 return "bulk";
173 case USB_ENDPOINT_XFER_ISOC:
174 return "iso";
175 case USB_ENDPOINT_XFER_INT:
176 return "int";
177 };
178
179 return "control";
180}
5be19a9d
XS		 181
182
183/* configure endpoint control registers */
184static void ep_reset(struct langwell_ep *ep, unsigned char ep_num,
185 unsigned char is_in, unsigned char ep_type)
186{
187 struct langwell_udc *dev;
188 u32 endptctrl;
189
190 dev = ep->dev;
5f81f4b0 191 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 192
193 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
194 if (is_in) { /* TX */
195 if (ep_num)
196 endptctrl |= EPCTRL_TXR;
197 endptctrl |= EPCTRL_TXE;
198 endptctrl |= ep_type << EPCTRL_TXT_SHIFT;
199 } else { /* RX */
200 if (ep_num)
201 endptctrl |= EPCTRL_RXR;
202 endptctrl |= EPCTRL_RXE;
203 endptctrl |= ep_type << EPCTRL_RXT_SHIFT;
204 }
205
206 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
207
5f81f4b0 208 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 209}
210
211
212/* reset ep0 dQH and endptctrl */
213static void ep0_reset(struct langwell_udc *dev)
214{
215 struct langwell_ep *ep;
216 int i;
217
5f81f4b0 218 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 219
220 /* ep0 in and out */
221 for (i = 0; i < 2; i++) {
222 ep = &dev->ep[i];
223 ep->dev = dev;
224
225 /* ep0 dQH */
226 ep->dqh = &dev->ep_dqh[i];
227
228 /* configure ep0 endpoint capabilities in dQH */
229 ep->dqh->dqh_ios = 1;
230 ep->dqh->dqh_mpl = EP0_MAX_PKT_SIZE;
231
3eed298f 232 /* enable ep0-in HW zero length termination select */
5be19a9d
XS		 233 if (is_in(ep))
234 ep->dqh->dqh_zlt = 0;
235 ep->dqh->dqh_mult = 0;
236
3eed298f
J		 237 ep->dqh->dtd_next = DTD_TERM;
238
5be19a9d
XS		 239 /* configure ep0 control registers */
240 ep_reset(&dev->ep[0], 0, i, USB_ENDPOINT_XFER_CONTROL);
241 }
242
5f81f4b0 243 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 244}
245
246
247/*-------------------------------------------------------------------------*/
248
249/* endpoints operations */
250
251/* configure endpoint, making it usable */
252static int langwell_ep_enable(struct usb_ep *_ep,
253 const struct usb_endpoint_descriptor *desc)
254{
255 struct langwell_udc *dev;
256 struct langwell_ep *ep;
257 u16 max = 0;
258 unsigned long flags;
3eed298f 259 int i, retval = 0;
5be19a9d
XS		 260 unsigned char zlt, ios = 0, mult = 0;
261
262 ep = container_of(_ep, struct langwell_ep, ep);
263 dev = ep->dev;
5f81f4b0 264 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 265
266 if (!_ep || !desc || ep->desc
267 || desc->bDescriptorType != USB_DT_ENDPOINT)
268 return -EINVAL;
269
270 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
271 return -ESHUTDOWN;
272
29cc8897 273 max = usb_endpoint_maxp(desc);
5be19a9d
XS		 274
275 /*
276 * disable HW zero length termination select
277 * driver handles zero length packet through req->req.zero
278 */
279 zlt = 1;
280
281 /*
282 * sanity check type, direction, address, and then
283 * initialize the endpoint capabilities fields in dQH
284 */
5f81f4b0 285 switch (usb_endpoint_type(desc)) {
5be19a9d
XS		 286 case USB_ENDPOINT_XFER_CONTROL:
287 ios = 1;
288 break;
289 case USB_ENDPOINT_XFER_BULK:
290 if ((dev->gadget.speed == USB_SPEED_HIGH
291 && max != 512)
292 || (dev->gadget.speed == USB_SPEED_FULL
293 && max > 64)) {
294 goto done;
295 }
296 break;
297 case USB_ENDPOINT_XFER_INT:
298 if (strstr(ep->ep.name, "-iso")) /* bulk is ok */
299 goto done;
300
301 switch (dev->gadget.speed) {
302 case USB_SPEED_HIGH:
303 if (max <= 1024)
304 break;
305 case USB_SPEED_FULL:
306 if (max <= 64)
307 break;
308 default:
309 if (max <= 8)
310 break;
311 goto done;
312 }
313 break;
314 case USB_ENDPOINT_XFER_ISOC:
315 if (strstr(ep->ep.name, "-bulk")
316 || strstr(ep->ep.name, "-int"))
317 goto done;
318
319 switch (dev->gadget.speed) {
320 case USB_SPEED_HIGH:
321 if (max <= 1024)
322 break;
323 case USB_SPEED_FULL:
324 if (max <= 1023)
325 break;
326 default:
327 goto done;
328 }
329 /*
330 * FIXME:
331 * calculate transactions needed for high bandwidth iso
332 */
333 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
334 max = max & 0x8ff; /* bit 0~10 */
335 /* 3 transactions at most */
336 if (mult > 3)
337 goto done;
338 break;
339 default:
340 goto done;
341 }
342
343 spin_lock_irqsave(&dev->lock, flags);
344
5be19a9d
XS		 345 ep->ep.maxpacket = max;
346 ep->desc = desc;
347 ep->stopped = 0;
5f81f4b0 348 ep->ep_num = usb_endpoint_num(desc);
5be19a9d
XS		 349
350 /* ep_type */
5f81f4b0 351 ep->ep_type = usb_endpoint_type(desc);
5be19a9d
XS		 352
353 /* configure endpoint control registers */
354 ep_reset(ep, ep->ep_num, is_in(ep), ep->ep_type);
355
3eed298f
J		 356 /* configure endpoint capabilities in dQH */
357 i = ep->ep_num * 2 + is_in(ep);
358 ep->dqh = &dev->ep_dqh[i];
359 ep->dqh->dqh_ios = ios;
360 ep->dqh->dqh_mpl = cpu_to_le16(max);
361 ep->dqh->dqh_zlt = zlt;
362 ep->dqh->dqh_mult = mult;
363 ep->dqh->dtd_next = DTD_TERM;
364
5f81f4b0 365 dev_dbg(&dev->pdev->dev, "enabled %s (ep%d%s-%s), max %04x\n",
5be19a9d
XS		 366 _ep->name,
367 ep->ep_num,
5f81f4b0
J		 368 DIR_STRING(ep),
369 type_string(desc),
5be19a9d
XS		 370 max);
371
372 spin_unlock_irqrestore(&dev->lock, flags);
373done:
5f81f4b0 374 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 375 return retval;
376}
377
378
379/*-------------------------------------------------------------------------*/
380
381/* retire a request */
382static void done(struct langwell_ep *ep, struct langwell_request *req,
383 int status)
384{
385 struct langwell_udc *dev = ep->dev;
386 unsigned stopped = ep->stopped;
387 struct langwell_dtd *curr_dtd, *next_dtd;
388 int i;
389
5f81f4b0 390 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 391
392 /* remove the req from ep->queue */
393 list_del_init(&req->queue);
394
395 if (req->req.status == -EINPROGRESS)
396 req->req.status = status;
397 else
398 status = req->req.status;
399
400 /* free dTD for the request */
401 next_dtd = req->head;
402 for (i = 0; i < req->dtd_count; i++) {
403 curr_dtd = next_dtd;
404 if (i != req->dtd_count - 1)
405 next_dtd = curr_dtd->next_dtd_virt;
406 dma_pool_free(dev->dtd_pool, curr_dtd, curr_dtd->dtd_dma);
407 }
408
409 if (req->mapped) {
5f81f4b0
J		 410 dma_unmap_single(&dev->pdev->dev,
411 req->req.dma, req->req.length,
5be19a9d
XS		 412 is_in(ep) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
413 req->req.dma = DMA_ADDR_INVALID;
414 req->mapped = 0;
415 } else
416 dma_sync_single_for_cpu(&dev->pdev->dev, req->req.dma,
417 req->req.length,
418 is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
419
420 if (status != -ESHUTDOWN)
5f81f4b0
J		 421 dev_dbg(&dev->pdev->dev,
422 "complete %s, req %p, stat %d, len %u/%u\n",
423 ep->ep.name, &req->req, status,
424 req->req.actual, req->req.length);
5be19a9d
XS		 425
426 /* don't modify queue heads during completion callback */
427 ep->stopped = 1;
428
429 spin_unlock(&dev->lock);
430 /* complete routine from gadget driver */
431 if (req->req.complete)
432 req->req.complete(&ep->ep, &req->req);
433
434 spin_lock(&dev->lock);
435 ep->stopped = stopped;
436
5f81f4b0 437 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 438}
439
440
441static void langwell_ep_fifo_flush(struct usb_ep *_ep);
442
443/* delete all endpoint requests, called with spinlock held */
444static void nuke(struct langwell_ep *ep, int status)
445{
446 /* called with spinlock held */
447 ep->stopped = 1;
448
449 /* endpoint fifo flush */
450 if (&ep->ep && ep->desc)
451 langwell_ep_fifo_flush(&ep->ep);
452
453 while (!list_empty(&ep->queue)) {
454 struct langwell_request *req = NULL;
455 req = list_entry(ep->queue.next, struct langwell_request,
456 queue);
457 done(ep, req, status);
458 }
459}
460
461
462/*-------------------------------------------------------------------------*/
463
464/* endpoint is no longer usable */
465static int langwell_ep_disable(struct usb_ep *_ep)
466{
467 struct langwell_ep *ep;
468 unsigned long flags;
469 struct langwell_udc *dev;
470 int ep_num;
471 u32 endptctrl;
472
473 ep = container_of(_ep, struct langwell_ep, ep);
474 dev = ep->dev;
5f81f4b0 475 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 476
477 if (!_ep || !ep->desc)
478 return -EINVAL;
479
480 spin_lock_irqsave(&dev->lock, flags);
481
482 /* disable endpoint control register */
483 ep_num = ep->ep_num;
484 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
485 if (is_in(ep))
486 endptctrl &= ~EPCTRL_TXE;
487 else
488 endptctrl &= ~EPCTRL_RXE;
489 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
490
491 /* nuke all pending requests (does flush) */
492 nuke(ep, -ESHUTDOWN);
493
494 ep->desc = NULL;
f9c56cdd 495 ep->ep.desc = NULL;
5be19a9d
XS		 496 ep->stopped = 1;
497
498 spin_unlock_irqrestore(&dev->lock, flags);
499
5f81f4b0
J		 500 dev_dbg(&dev->pdev->dev, "disabled %s\n", _ep->name);
501 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 502
503 return 0;
504}
505
506
507/* allocate a request object to use with this endpoint */
508static struct usb_request *langwell_alloc_request(struct usb_ep *_ep,
509 gfp_t gfp_flags)
510{
511 struct langwell_ep *ep;
512 struct langwell_udc *dev;
513 struct langwell_request *req = NULL;
514
515 if (!_ep)
516 return NULL;
517
518 ep = container_of(_ep, struct langwell_ep, ep);
519 dev = ep->dev;
5f81f4b0 520 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 521
522 req = kzalloc(sizeof(*req), gfp_flags);
523 if (!req)
524 return NULL;
525
526 req->req.dma = DMA_ADDR_INVALID;
527 INIT_LIST_HEAD(&req->queue);
528
5f81f4b0
J		 529 dev_vdbg(&dev->pdev->dev, "alloc request for %s\n", _ep->name);
530 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 531 return &req->req;
532}
533
534
535/* free a request object */
536static void langwell_free_request(struct usb_ep *_ep,
537 struct usb_request *_req)
538{
539 struct langwell_ep *ep;
540 struct langwell_udc *dev;
541 struct langwell_request *req = NULL;
542
543 ep = container_of(_ep, struct langwell_ep, ep);
544 dev = ep->dev;
5f81f4b0 545 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 546
547 if (!_ep || !_req)
548 return;
549
550 req = container_of(_req, struct langwell_request, req);
551 WARN_ON(!list_empty(&req->queue));
552
553 if (_req)
554 kfree(req);
555
5f81f4b0
J		 556 dev_vdbg(&dev->pdev->dev, "free request for %s\n", _ep->name);
557 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 558}
559
560
561/*-------------------------------------------------------------------------*/
562
563/* queue dTD and PRIME endpoint */
564static int queue_dtd(struct langwell_ep *ep, struct langwell_request *req)
565{
566 u32 bit_mask, usbcmd, endptstat, dtd_dma;
567 u8 dtd_status;
568 int i;
569 struct langwell_dqh *dqh;
570 struct langwell_udc *dev;
571
572 dev = ep->dev;
5f81f4b0 573 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 574
575 i = ep->ep_num * 2 + is_in(ep);
576 dqh = &dev->ep_dqh[i];
577
578 if (ep->ep_num)
5f81f4b0 579 dev_vdbg(&dev->pdev->dev, "%s\n", ep->name);
5be19a9d
XS		 580 else
581 /* ep0 */
5f81f4b0 582 dev_vdbg(&dev->pdev->dev, "%s-%s\n", ep->name, DIR_STRING(ep));
5be19a9d 583
b9af9ea4
FB		 584 dev_vdbg(&dev->pdev->dev, "ep_dqh[%d] addr: 0x%p\n",
585 i, &(dev->ep_dqh[i]));
5be19a9d
XS		 586
587 bit_mask = is_in(ep) ?
588 (1 << (ep->ep_num + 16)) : (1 << (ep->ep_num));
589
5f81f4b0 590 dev_vdbg(&dev->pdev->dev, "bit_mask = 0x%08x\n", bit_mask);
5be19a9d
XS		 591
592 /* check if the pipe is empty */
593 if (!(list_empty(&ep->queue))) {
594 /* add dTD to the end of linked list */
595 struct langwell_request *lastreq;
596 lastreq = list_entry(ep->queue.prev,
597 struct langwell_request, queue);
598
599 lastreq->tail->dtd_next =
600 cpu_to_le32(req->head->dtd_dma & DTD_NEXT_MASK);
601
602 /* read prime bit, if 1 goto out */
603 if (readl(&dev->op_regs->endptprime) & bit_mask)
604 goto out;
605
606 do {
607 /* set ATDTW bit in USBCMD */
608 usbcmd = readl(&dev->op_regs->usbcmd);
609 writel(usbcmd | CMD_ATDTW, &dev->op_regs->usbcmd);
610
611 /* read correct status bit */
612 endptstat = readl(&dev->op_regs->endptstat) & bit_mask;
613
614 } while (!(readl(&dev->op_regs->usbcmd) & CMD_ATDTW));
615
616 /* write ATDTW bit to 0 */
617 usbcmd = readl(&dev->op_regs->usbcmd);
618 writel(usbcmd & ~CMD_ATDTW, &dev->op_regs->usbcmd);
619
620 if (endptstat)
621 goto out;
622 }
623
624 /* write dQH next pointer and terminate bit to 0 */
625 dtd_dma = req->head->dtd_dma & DTD_NEXT_MASK;
626 dqh->dtd_next = cpu_to_le32(dtd_dma);
627
628 /* clear active and halt bit */
629 dtd_status = (u8) ~(DTD_STS_ACTIVE | DTD_STS_HALTED);
630 dqh->dtd_status &= dtd_status;
5f81f4b0
J		 631 dev_vdbg(&dev->pdev->dev, "dqh->dtd_status = 0x%x\n", dqh->dtd_status);
632
25985edc 633 /* ensure that updates to the dQH will occur before priming */
5f81f4b0 634 wmb();
5be19a9d
XS		 635
636 /* write 1 to endptprime register to PRIME endpoint */
637 bit_mask = is_in(ep) ? (1 << (ep->ep_num + 16)) : (1 << ep->ep_num);
5f81f4b0 638 dev_vdbg(&dev->pdev->dev, "endprime bit_mask = 0x%08x\n", bit_mask);
5be19a9d
XS		 639 writel(bit_mask, &dev->op_regs->endptprime);
640out:
5f81f4b0 641 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 642 return 0;
643}
644
645
646/* fill in the dTD structure to build a transfer descriptor */
647static struct langwell_dtd *build_dtd(struct langwell_request *req,
648 unsigned *length, dma_addr_t *dma, int *is_last)
649{
650 u32 buf_ptr;
651 struct langwell_dtd *dtd;
652 struct langwell_udc *dev;
653 int i;
654
655 dev = req->ep->dev;
5f81f4b0 656 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 657
658 /* the maximum transfer length, up to 16k bytes */
659 *length = min(req->req.length - req->req.actual,
660 (unsigned)DTD_MAX_TRANSFER_LENGTH);
661
662 /* create dTD dma_pool resource */
663 dtd = dma_pool_alloc(dev->dtd_pool, GFP_KERNEL, dma);
664 if (dtd == NULL)
665 return dtd;
666 dtd->dtd_dma = *dma;
667
668 /* initialize buffer page pointers */
669 buf_ptr = (u32)(req->req.dma + req->req.actual);
670 for (i = 0; i < 5; i++)
671 dtd->dtd_buf[i] = cpu_to_le32(buf_ptr + i * PAGE_SIZE);
672
673 req->req.actual += *length;
674
675 /* fill in total bytes with transfer size */
676 dtd->dtd_total = cpu_to_le16(*length);
5f81f4b0 677 dev_vdbg(&dev->pdev->dev, "dtd->dtd_total = %d\n", dtd->dtd_total);
5be19a9d
XS		 678
679 /* set is_last flag if req->req.zero is set or not */
680 if (req->req.zero) {
681 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
682 *is_last = 1;
683 else
684 *is_last = 0;
685 } else if (req->req.length == req->req.actual) {
686 *is_last = 1;
687 } else
688 *is_last = 0;
689
690 if (*is_last == 0)
5f81f4b0 691 dev_vdbg(&dev->pdev->dev, "multi-dtd request!\n");
5be19a9d
XS		 692
693 /* set interrupt on complete bit for the last dTD */
694 if (*is_last && !req->req.no_interrupt)
695 dtd->dtd_ioc = 1;
696
697 /* set multiplier override 0 for non-ISO and non-TX endpoint */
698 dtd->dtd_multo = 0;
699
700 /* set the active bit of status field to 1 */
701 dtd->dtd_status = DTD_STS_ACTIVE;
5f81f4b0
J		 702 dev_vdbg(&dev->pdev->dev, "dtd->dtd_status = 0x%02x\n",
703 dtd->dtd_status);
5be19a9d 704
5f81f4b0
J		 705 dev_vdbg(&dev->pdev->dev, "length = %d, dma addr= 0x%08x\n",
706 *length, (int)*dma);
707 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 708 return dtd;
709}
710
711
712/* generate dTD linked list for a request */
713static int req_to_dtd(struct langwell_request *req)
714{
715 unsigned count;
716 int is_last, is_first = 1;
717 struct langwell_dtd *dtd, *last_dtd = NULL;
718 struct langwell_udc *dev;
719 dma_addr_t dma;
720
721 dev = req->ep->dev;
5f81f4b0 722 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 723 do {
724 dtd = build_dtd(req, &count, &dma, &is_last);
725 if (dtd == NULL)
726 return -ENOMEM;
727
728 if (is_first) {
729 is_first = 0;
730 req->head = dtd;
731 } else {
732 last_dtd->dtd_next = cpu_to_le32(dma);
733 last_dtd->next_dtd_virt = dtd;
734 }
735 last_dtd = dtd;
736 req->dtd_count++;
737 } while (!is_last);
738
739 /* set terminate bit to 1 for the last dTD */
740 dtd->dtd_next = DTD_TERM;
741
742 req->tail = dtd;
743
5f81f4b0 744 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 745 return 0;
746}
747
748/*-------------------------------------------------------------------------*/
749
750/* queue (submits) an I/O requests to an endpoint */
751static int langwell_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
752 gfp_t gfp_flags)
753{
754 struct langwell_request *req;
755 struct langwell_ep *ep;
756 struct langwell_udc *dev;
757 unsigned long flags;
758 int is_iso = 0, zlflag = 0;
759
760 /* always require a cpu-view buffer */
761 req = container_of(_req, struct langwell_request, req);
762 ep = container_of(_ep, struct langwell_ep, ep);
763
764 if (!_req || !_req->complete || !_req->buf
765 || !list_empty(&req->queue)) {
766 return -EINVAL;
767 }
768
769 if (unlikely(!_ep || !ep->desc))
770 return -EINVAL;
771
772 dev = ep->dev;
773 req->ep = ep;
5f81f4b0 774 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d 775
5f81f4b0 776 if (usb_endpoint_xfer_isoc(ep->desc)) {
5be19a9d
XS		 777 if (req->req.length > ep->ep.maxpacket)
778 return -EMSGSIZE;
779 is_iso = 1;
780 }
781
782 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN))
783 return -ESHUTDOWN;
784
785 /* set up dma mapping in case the caller didn't */
786 if (_req->dma == DMA_ADDR_INVALID) {
787 /* WORKAROUND: WARN_ON(size == 0) */
788 if (_req->length == 0) {
5f81f4b0 789 dev_vdbg(&dev->pdev->dev, "req->length: 0->1\n");
5be19a9d
XS		 790 zlflag = 1;
791 _req->length++;
792 }
793
794 _req->dma = dma_map_single(&dev->pdev->dev,
795 _req->buf, _req->length,
796 is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
797 if (zlflag && (_req->length == 1)) {
5f81f4b0 798 dev_vdbg(&dev->pdev->dev, "req->length: 1->0\n");
5be19a9d
XS		 799 zlflag = 0;
800 _req->length = 0;
801 }
802
803 req->mapped = 1;
5f81f4b0 804 dev_vdbg(&dev->pdev->dev, "req->mapped = 1\n");
5be19a9d
XS		 805 } else {
806 dma_sync_single_for_device(&dev->pdev->dev,
807 _req->dma, _req->length,
808 is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
809 req->mapped = 0;
5f81f4b0 810 dev_vdbg(&dev->pdev->dev, "req->mapped = 0\n");
5be19a9d
XS		 811 }
812
5f81f4b0
J		 813 dev_dbg(&dev->pdev->dev,
814 "%s queue req %p, len %u, buf %p, dma 0x%08x\n",
815 _ep->name,
816 _req, _req->length, _req->buf, (int)_req->dma);
5be19a9d
XS		 817
818 _req->status = -EINPROGRESS;
819 _req->actual = 0;
820 req->dtd_count = 0;
821
822 spin_lock_irqsave(&dev->lock, flags);
823
824 /* build and put dTDs to endpoint queue */
825 if (!req_to_dtd(req)) {
826 queue_dtd(ep, req);
827 } else {
828 spin_unlock_irqrestore(&dev->lock, flags);
829 return -ENOMEM;
830 }
831
832 /* update ep0 state */
833 if (ep->ep_num == 0)
834 dev->ep0_state = DATA_STATE_XMIT;
835
836 if (likely(req != NULL)) {
837 list_add_tail(&req->queue, &ep->queue);
5f81f4b0 838 dev_vdbg(&dev->pdev->dev, "list_add_tail()\n");
5be19a9d
XS		 839 }
840
841 spin_unlock_irqrestore(&dev->lock, flags);
842
5f81f4b0 843 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 844 return 0;
845}
846
847
848/* dequeue (cancels, unlinks) an I/O request from an endpoint */
849static int langwell_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
850{
851 struct langwell_ep *ep;
852 struct langwell_udc *dev;
853 struct langwell_request *req;
854 unsigned long flags;
855 int stopped, ep_num, retval = 0;
856 u32 endptctrl;
857
858 ep = container_of(_ep, struct langwell_ep, ep);
859 dev = ep->dev;
5f81f4b0 860 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 861
862 if (!_ep || !ep->desc || !_req)
863 return -EINVAL;
864
865 if (!dev->driver)
866 return -ESHUTDOWN;
867
868 spin_lock_irqsave(&dev->lock, flags);
869 stopped = ep->stopped;
870
871 /* quiesce dma while we patch the queue */
872 ep->stopped = 1;
873 ep_num = ep->ep_num;
874
875 /* disable endpoint control register */
876 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
877 if (is_in(ep))
878 endptctrl &= ~EPCTRL_TXE;
879 else
880 endptctrl &= ~EPCTRL_RXE;
881 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
882
883 /* make sure it's still queued on this endpoint */
884 list_for_each_entry(req, &ep->queue, queue) {
885 if (&req->req == _req)
886 break;
887 }
888
889 if (&req->req != _req) {
890 retval = -EINVAL;
891 goto done;
892 }
893
894 /* queue head may be partially complete. */
895 if (ep->queue.next == &req->queue) {
5f81f4b0 896 dev_dbg(&dev->pdev->dev, "unlink (%s) dma\n", _ep->name);
5be19a9d
XS		 897 _req->status = -ECONNRESET;
898 langwell_ep_fifo_flush(&ep->ep);
899
900 /* not the last request in endpoint queue */
901 if (likely(ep->queue.next == &req->queue)) {
902 struct langwell_dqh *dqh;
903 struct langwell_request *next_req;
904
905 dqh = ep->dqh;
906 next_req = list_entry(req->queue.next,
907 struct langwell_request, queue);
908
909 /* point the dQH to the first dTD of next request */
910 writel((u32) next_req->head, &dqh->dqh_current);
911 }
912 } else {
913 struct langwell_request *prev_req;
914
915 prev_req = list_entry(req->queue.prev,
916 struct langwell_request, queue);
917 writel(readl(&req->tail->dtd_next),
918 &prev_req->tail->dtd_next);
919 }
920
921 done(ep, req, -ECONNRESET);
922
923done:
924 /* enable endpoint again */
925 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
926 if (is_in(ep))
927 endptctrl |= EPCTRL_TXE;
928 else
929 endptctrl |= EPCTRL_RXE;
930 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
931
932 ep->stopped = stopped;
933 spin_unlock_irqrestore(&dev->lock, flags);
934
5f81f4b0 935 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 936 return retval;
937}
938
939
940/*-------------------------------------------------------------------------*/
941
942/* endpoint set/clear halt */
943static void ep_set_halt(struct langwell_ep *ep, int value)
944{
945 u32 endptctrl = 0;
946 int ep_num;
947 struct langwell_udc *dev = ep->dev;
5f81f4b0 948 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 949
950 ep_num = ep->ep_num;
951 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
952
953 /* value: 1 - set halt, 0 - clear halt */
954 if (value) {
955 /* set the stall bit */
956 if (is_in(ep))
957 endptctrl |= EPCTRL_TXS;
958 else
959 endptctrl |= EPCTRL_RXS;
960 } else {
961 /* clear the stall bit and reset data toggle */
962 if (is_in(ep)) {
963 endptctrl &= ~EPCTRL_TXS;
964 endptctrl |= EPCTRL_TXR;
965 } else {
966 endptctrl &= ~EPCTRL_RXS;
967 endptctrl |= EPCTRL_RXR;
968 }
969 }
970
971 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
972
5f81f4b0 973 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 974}
975
976
977/* set the endpoint halt feature */
978static int langwell_ep_set_halt(struct usb_ep *_ep, int value)
979{
980 struct langwell_ep *ep;
981 struct langwell_udc *dev;
982 unsigned long flags;
983 int retval = 0;
984
985 ep = container_of(_ep, struct langwell_ep, ep);
986 dev = ep->dev;
987
5f81f4b0 988 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 989
990 if (!_ep || !ep->desc)
991 return -EINVAL;
992
993 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
994 return -ESHUTDOWN;
995
5f81f4b0 996 if (usb_endpoint_xfer_isoc(ep->desc))
5be19a9d
XS		 997 return -EOPNOTSUPP;
998
999 spin_lock_irqsave(&dev->lock, flags);
1000
1001 /*
1002 * attempt to halt IN ep will fail if any transfer requests
1003 * are still queue
1004 */
1005 if (!list_empty(&ep->queue) && is_in(ep) && value) {
1006 /* IN endpoint FIFO holds bytes */
5f81f4b0 1007 dev_dbg(&dev->pdev->dev, "%s FIFO holds bytes\n", _ep->name);
5be19a9d
XS		 1008 retval = -EAGAIN;
1009 goto done;
1010 }
1011
1012 /* endpoint set/clear halt */
1013 if (ep->ep_num) {
1014 ep_set_halt(ep, value);
1015 } else { /* endpoint 0 */
1016 dev->ep0_state = WAIT_FOR_SETUP;
1017 dev->ep0_dir = USB_DIR_OUT;
1018 }
1019done:
1020 spin_unlock_irqrestore(&dev->lock, flags);
5f81f4b0
J		 1021 dev_dbg(&dev->pdev->dev, "%s %s halt\n",
1022 _ep->name, value ? "set" : "clear");
1023 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1024 return retval;
1025}
1026
1027
1028/* set the halt feature and ignores clear requests */
1029static int langwell_ep_set_wedge(struct usb_ep *_ep)
1030{
1031 struct langwell_ep *ep;
1032 struct langwell_udc *dev;
1033
1034 ep = container_of(_ep, struct langwell_ep, ep);
1035 dev = ep->dev;
1036
5f81f4b0 1037 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1038
1039 if (!_ep || !ep->desc)
1040 return -EINVAL;
1041
5f81f4b0 1042 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1043 return usb_ep_set_halt(_ep);
1044}
1045
1046
1047/* flush contents of a fifo */
1048static void langwell_ep_fifo_flush(struct usb_ep *_ep)
1049{
1050 struct langwell_ep *ep;
1051 struct langwell_udc *dev;
1052 u32 flush_bit;
1053 unsigned long timeout;
1054
1055 ep = container_of(_ep, struct langwell_ep, ep);
1056 dev = ep->dev;
1057
5f81f4b0 1058 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1059
1060 if (!_ep || !ep->desc) {
5f81f4b0
J		 1061 dev_vdbg(&dev->pdev->dev, "ep or ep->desc is NULL\n");
1062 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1063 return;
1064 }
1065
5f81f4b0
J		 1066 dev_vdbg(&dev->pdev->dev, "%s-%s fifo flush\n",
1067 _ep->name, DIR_STRING(ep));
5be19a9d
XS		 1068
1069 /* flush endpoint buffer */
1070 if (ep->ep_num == 0)
1071 flush_bit = (1 << 16) | 1;
1072 else if (is_in(ep))
1073 flush_bit = 1 << (ep->ep_num + 16); /* TX */
1074 else
1075 flush_bit = 1 << ep->ep_num; /* RX */
1076
1077 /* wait until flush complete */
1078 timeout = jiffies + FLUSH_TIMEOUT;
1079 do {
1080 writel(flush_bit, &dev->op_regs->endptflush);
1081 while (readl(&dev->op_regs->endptflush)) {
1082 if (time_after(jiffies, timeout)) {
5f81f4b0 1083 dev_err(&dev->pdev->dev, "ep flush timeout\n");
5be19a9d
XS		 1084 goto done;
1085 }
1086 cpu_relax();
1087 }
1088 } while (readl(&dev->op_regs->endptstat) & flush_bit);
1089done:
5f81f4b0 1090 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1091}
1092
1093
1094/* endpoints operations structure */
1095static const struct usb_ep_ops langwell_ep_ops = {
1096
1097 /* configure endpoint, making it usable */
1098 .enable = langwell_ep_enable,
1099
1100 /* endpoint is no longer usable */
1101 .disable = langwell_ep_disable,
1102
1103 /* allocate a request object to use with this endpoint */
1104 .alloc_request = langwell_alloc_request,
1105
1106 /* free a request object */
1107 .free_request = langwell_free_request,
1108
1109 /* queue (submits) an I/O requests to an endpoint */
1110 .queue = langwell_ep_queue,
1111
1112 /* dequeue (cancels, unlinks) an I/O request from an endpoint */
1113 .dequeue = langwell_ep_dequeue,
1114
1115 /* set the endpoint halt feature */
1116 .set_halt = langwell_ep_set_halt,
1117
1118 /* set the halt feature and ignores clear requests */
1119 .set_wedge = langwell_ep_set_wedge,
1120
1121 /* flush contents of a fifo */
1122 .fifo_flush = langwell_ep_fifo_flush,
1123};
1124
1125
1126/*-------------------------------------------------------------------------*/
1127
1128/* device controller usb_gadget_ops structure */
1129
1130/* returns the current frame number */
1131static int langwell_get_frame(struct usb_gadget *_gadget)
1132{
1133 struct langwell_udc *dev;
1134 u16 retval;
1135
1136 if (!_gadget)
1137 return -ENODEV;
1138
1139 dev = container_of(_gadget, struct langwell_udc, gadget);
5f81f4b0 1140 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1141
1142 retval = readl(&dev->op_regs->frindex) & FRINDEX_MASK;
1143
5f81f4b0 1144 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1145 return retval;
1146}
1147
1148
513b91b6
J		 1149/* enter or exit PHY low power state */
1150static void langwell_phy_low_power(struct langwell_udc *dev, bool flag)
1151{
1152 u32 devlc;
1153 u8 devlc_byte2;
1154 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
1155
1156 devlc = readl(&dev->op_regs->devlc);
1157 dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc);
1158
1159 if (flag)
1160 devlc |= LPM_PHCD;
1161 else
1162 devlc &= ~LPM_PHCD;
1163
1164 /* FIXME: workaround for Langwell A1/A2/A3 sighting */
1165 devlc_byte2 = (devlc >> 16) & 0xff;
1166 writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2);
1167
1168 devlc = readl(&dev->op_regs->devlc);
1169 dev_vdbg(&dev->pdev->dev,
1170 "%s PHY low power suspend, devlc = 0x%08x\n",
1171 flag ? "enter" : "exit", devlc);
1172}
1173
1174
5be19a9d
XS		 1175/* tries to wake up the host connected to this gadget */
1176static int langwell_wakeup(struct usb_gadget *_gadget)
1177{
1178 struct langwell_udc *dev;
513b91b6 1179 u32 portsc1;
5f81f4b0 1180 unsigned long flags;
5be19a9d
XS		 1181
1182 if (!_gadget)
1183 return 0;
1184
1185 dev = container_of(_gadget, struct langwell_udc, gadget);
5f81f4b0 1186 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d 1187
5f81f4b0
J		 1188 /* remote wakeup feature not enabled by host */
1189 if (!dev->remote_wakeup) {
1190 dev_info(&dev->pdev->dev, "remote wakeup is disabled\n");
5be19a9d 1191 return -ENOTSUPP;
5f81f4b0 1192 }
5be19a9d
XS		 1193
1194 spin_lock_irqsave(&dev->lock, flags);
1195
1196 portsc1 = readl(&dev->op_regs->portsc1);
1197 if (!(portsc1 & PORTS_SUSP)) {
1198 spin_unlock_irqrestore(&dev->lock, flags);
1199 return 0;
1200 }
1201
513b91b6
J		 1202 /* LPM L1 to L0 or legacy remote wakeup */
1203 if (dev->lpm && dev->lpm_state == LPM_L1)
1204 dev_info(&dev->pdev->dev, "LPM L1 to L0 remote wakeup\n");
1205 else
1206 dev_info(&dev->pdev->dev, "device remote wakeup\n");
5be19a9d
XS		 1207
1208 /* exit PHY low power suspend */
513b91b6
J		 1209 if (dev->pdev->device != 0x0829)
1210 langwell_phy_low_power(dev, 0);
1211
1212 /* force port resume */
1213 portsc1 |= PORTS_FPR;
1214 writel(portsc1, &dev->op_regs->portsc1);
5be19a9d
XS		 1215
1216 spin_unlock_irqrestore(&dev->lock, flags);
1217
5f81f4b0 1218 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1219 return 0;
1220}
1221
1222
1223/* notify controller that VBUS is powered or not */
1224static int langwell_vbus_session(struct usb_gadget *_gadget, int is_active)
1225{
1226 struct langwell_udc *dev;
1227 unsigned long flags;
5f81f4b0 1228 u32 usbcmd;
5be19a9d
XS		 1229
1230 if (!_gadget)
1231 return -ENODEV;
1232
1233 dev = container_of(_gadget, struct langwell_udc, gadget);
5f81f4b0 1234 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1235
1236 spin_lock_irqsave(&dev->lock, flags);
5f81f4b0
J		 1237 dev_vdbg(&dev->pdev->dev, "VBUS status: %s\n",
1238 is_active ? "on" : "off");
5be19a9d
XS		 1239
1240 dev->vbus_active = (is_active != 0);
1241 if (dev->driver && dev->softconnected && dev->vbus_active) {
1242 usbcmd = readl(&dev->op_regs->usbcmd);
1243 usbcmd |= CMD_RUNSTOP;
1244 writel(usbcmd, &dev->op_regs->usbcmd);
1245 } else {
1246 usbcmd = readl(&dev->op_regs->usbcmd);
1247 usbcmd &= ~CMD_RUNSTOP;
1248 writel(usbcmd, &dev->op_regs->usbcmd);
1249 }
1250
1251 spin_unlock_irqrestore(&dev->lock, flags);
1252
5f81f4b0 1253 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1254 return 0;
1255}
1256
1257
1258/* constrain controller's VBUS power usage */
1259static int langwell_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1260{
1261 struct langwell_udc *dev;
1262
1263 if (!_gadget)
1264 return -ENODEV;
1265
1266 dev = container_of(_gadget, struct langwell_udc, gadget);
5f81f4b0 1267 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1268
1269 if (dev->transceiver) {
5f81f4b0
J		 1270 dev_vdbg(&dev->pdev->dev, "otg_set_power\n");
1271 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1272 return otg_set_power(dev->transceiver, mA);
1273 }
1274
5f81f4b0 1275 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1276 return -ENOTSUPP;
1277}
1278
1279
1280/* D+ pullup, software-controlled connect/disconnect to USB host */
1281static int langwell_pullup(struct usb_gadget *_gadget, int is_on)
1282{
1283 struct langwell_udc *dev;
5f81f4b0
J		 1284 u32 usbcmd;
1285 unsigned long flags;
5be19a9d
XS		 1286
1287 if (!_gadget)
1288 return -ENODEV;
1289
1290 dev = container_of(_gadget, struct langwell_udc, gadget);
1291
5f81f4b0 1292 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1293
1294 spin_lock_irqsave(&dev->lock, flags);
1295 dev->softconnected = (is_on != 0);
1296
1297 if (dev->driver && dev->softconnected && dev->vbus_active) {
1298 usbcmd = readl(&dev->op_regs->usbcmd);
1299 usbcmd |= CMD_RUNSTOP;
1300 writel(usbcmd, &dev->op_regs->usbcmd);
1301 } else {
1302 usbcmd = readl(&dev->op_regs->usbcmd);
1303 usbcmd &= ~CMD_RUNSTOP;
1304 writel(usbcmd, &dev->op_regs->usbcmd);
1305 }
1306 spin_unlock_irqrestore(&dev->lock, flags);
1307
5f81f4b0 1308 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1309 return 0;
1310}
1311
2c7f0989
FB		 1312static int langwell_start(struct usb_gadget *g,
1313 struct usb_gadget_driver *driver);
1314
1315static int langwell_stop(struct usb_gadget *g,
1316 struct usb_gadget_driver *driver);
1317
5be19a9d
XS		 1318/* device controller usb_gadget_ops structure */
1319static const struct usb_gadget_ops langwell_ops = {
1320
1321 /* returns the current frame number */
1322 .get_frame = langwell_get_frame,
1323
1324 /* tries to wake up the host connected to this gadget */
1325 .wakeup = langwell_wakeup,
1326
1327 /* set the device selfpowered feature, always selfpowered */
1328 /* .set_selfpowered = langwell_set_selfpowered, */
1329
1330 /* notify controller that VBUS is powered or not */
1331 .vbus_session = langwell_vbus_session,
1332
1333 /* constrain controller's VBUS power usage */
1334 .vbus_draw = langwell_vbus_draw,
1335
1336 /* D+ pullup, software-controlled connect/disconnect to USB host */
1337 .pullup = langwell_pullup,
0f91349b 1338
2c7f0989
FB		 1339 .udc_start = langwell_start,
1340 .udc_stop = langwell_stop,
5be19a9d
XS		 1341};
1342
1343
1344/*-------------------------------------------------------------------------*/
1345
1346/* device controller operations */
1347
1348/* reset device controller */
1349static int langwell_udc_reset(struct langwell_udc *dev)
1350{
1351 u32 usbcmd, usbmode, devlc, endpointlistaddr;
513b91b6 1352 u8 devlc_byte0, devlc_byte2;
5be19a9d
XS		 1353 unsigned long timeout;
1354
1355 if (!dev)
1356 return -EINVAL;
1357
5f81f4b0 1358 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1359
1360 /* set controller to stop state */
1361 usbcmd = readl(&dev->op_regs->usbcmd);
1362 usbcmd &= ~CMD_RUNSTOP;
1363 writel(usbcmd, &dev->op_regs->usbcmd);
1364
1365 /* reset device controller */
1366 usbcmd = readl(&dev->op_regs->usbcmd);
1367 usbcmd |= CMD_RST;
1368 writel(usbcmd, &dev->op_regs->usbcmd);
1369
1370 /* wait for reset to complete */
1371 timeout = jiffies + RESET_TIMEOUT;
1372 while (readl(&dev->op_regs->usbcmd) & CMD_RST) {
1373 if (time_after(jiffies, timeout)) {
5f81f4b0 1374 dev_err(&dev->pdev->dev, "device reset timeout\n");
5be19a9d
XS		 1375 return -ETIMEDOUT;
1376 }
1377 cpu_relax();
1378 }
1379
1380 /* set controller to device mode */
1381 usbmode = readl(&dev->op_regs->usbmode);
1382 usbmode |= MODE_DEVICE;
1383
1384 /* turn setup lockout off, require setup tripwire in usbcmd */
1385 usbmode |= MODE_SLOM;
1386
1387 writel(usbmode, &dev->op_regs->usbmode);
1388 usbmode = readl(&dev->op_regs->usbmode);
5f81f4b0 1389 dev_vdbg(&dev->pdev->dev, "usbmode=0x%08x\n", usbmode);
5be19a9d
XS		 1390
1391 /* Write-Clear setup status */
1392 writel(0, &dev->op_regs->usbsts);
1393
1394 /* if support USB LPM, ACK all LPM token */
1395 if (dev->lpm) {
1396 devlc = readl(&dev->op_regs->devlc);
513b91b6
J		 1397 dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc);
1398 /* FIXME: workaround for Langwell A1/A2/A3 sighting */
5be19a9d
XS		 1399 devlc &= ~LPM_STL; /* don't STALL LPM token */
1400 devlc &= ~LPM_NYT_ACK; /* ACK LPM token */
513b91b6
J		 1401 devlc_byte0 = devlc & 0xff;
1402 devlc_byte2 = (devlc >> 16) & 0xff;
1403 writeb(devlc_byte0, (u8 *)&dev->op_regs->devlc);
1404 writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2);
1405 devlc = readl(&dev->op_regs->devlc);
1406 dev_vdbg(&dev->pdev->dev,
1407 "ACK LPM token, devlc = 0x%08x\n", devlc);
5be19a9d
XS		 1408 }
1409
1410 /* fill endpointlistaddr register */
1411 endpointlistaddr = dev->ep_dqh_dma;
1412 endpointlistaddr &= ENDPOINTLISTADDR_MASK;
1413 writel(endpointlistaddr, &dev->op_regs->endpointlistaddr);
1414
5f81f4b0
J		 1415 dev_vdbg(&dev->pdev->dev,
1416 "dQH base (vir: %p, phy: 0x%08x), endpointlistaddr=0x%08x\n",
1417 dev->ep_dqh, endpointlistaddr,
1418 readl(&dev->op_regs->endpointlistaddr));
1419 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1420 return 0;
1421}
1422
1423
1424/* reinitialize device controller endpoints */
1425static int eps_reinit(struct langwell_udc *dev)
1426{
1427 struct langwell_ep *ep;
1428 char name[14];
1429 int i;
1430
5f81f4b0 1431 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1432
1433 /* initialize ep0 */
1434 ep = &dev->ep[0];
1435 ep->dev = dev;
1436 strncpy(ep->name, "ep0", sizeof(ep->name));
1437 ep->ep.name = ep->name;
1438 ep->ep.ops = &langwell_ep_ops;
1439 ep->stopped = 0;
1440 ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
1441 ep->ep_num = 0;
1442 ep->desc = &langwell_ep0_desc;
1443 INIT_LIST_HEAD(&ep->queue);
1444
1445 ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1446
1447 /* initialize other endpoints */
1448 for (i = 2; i < dev->ep_max; i++) {
1449 ep = &dev->ep[i];
1450 if (i % 2)
1451 snprintf(name, sizeof(name), "ep%din", i / 2);
1452 else
1453 snprintf(name, sizeof(name), "ep%dout", i / 2);
1454 ep->dev = dev;
1455 strncpy(ep->name, name, sizeof(ep->name));
1456 ep->ep.name = ep->name;
1457
1458 ep->ep.ops = &langwell_ep_ops;
1459 ep->stopped = 0;
1460 ep->ep.maxpacket = (unsigned short) ~0;
1461 ep->ep_num = i / 2;
1462
1463 INIT_LIST_HEAD(&ep->queue);
1464 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
5be19a9d
XS		 1465 }
1466
5f81f4b0 1467 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1468 return 0;
1469}
1470
1471
1472/* enable interrupt and set controller to run state */
1473static void langwell_udc_start(struct langwell_udc *dev)
1474{
1475 u32 usbintr, usbcmd;
5f81f4b0 1476 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1477
1478 /* enable interrupts */
1479 usbintr = INTR_ULPIE /* ULPI */
1480 | INTR_SLE /* suspend */
1481 /* | INTR_SRE SOF received */
1482 | INTR_URE /* USB reset */
1483 | INTR_AAE /* async advance */
1484 | INTR_SEE /* system error */
1485 | INTR_FRE /* frame list rollover */
1486 | INTR_PCE /* port change detect */
1487 | INTR_UEE /* USB error interrupt */
1488 | INTR_UE; /* USB interrupt */
1489 writel(usbintr, &dev->op_regs->usbintr);
1490
1491 /* clear stopped bit */
1492 dev->stopped = 0;
1493
1494 /* set controller to run */
1495 usbcmd = readl(&dev->op_regs->usbcmd);
1496 usbcmd |= CMD_RUNSTOP;
1497 writel(usbcmd, &dev->op_regs->usbcmd);
1498
5f81f4b0 1499 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1500}
1501
1502
1503/* disable interrupt and set controller to stop state */
1504static void langwell_udc_stop(struct langwell_udc *dev)
1505{
1506 u32 usbcmd;
1507
5f81f4b0 1508 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1509
1510 /* disable all interrupts */
1511 writel(0, &dev->op_regs->usbintr);
1512
1513 /* set stopped bit */
1514 dev->stopped = 1;
1515
1516 /* set controller to stop state */
1517 usbcmd = readl(&dev->op_regs->usbcmd);
1518 usbcmd &= ~CMD_RUNSTOP;
1519 writel(usbcmd, &dev->op_regs->usbcmd);
1520
5f81f4b0 1521 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1522}
1523
1524
1525/* stop all USB activities */
1526static void stop_activity(struct langwell_udc *dev,
1527 struct usb_gadget_driver *driver)
1528{
1529 struct langwell_ep *ep;
5f81f4b0 1530 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1531
1532 nuke(&dev->ep[0], -ESHUTDOWN);
1533
1534 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
1535 nuke(ep, -ESHUTDOWN);
1536 }
1537
1538 /* report disconnect; the driver is already quiesced */
1539 if (driver) {
1540 spin_unlock(&dev->lock);
1541 driver->disconnect(&dev->gadget);
1542 spin_lock(&dev->lock);
1543 }
1544
5f81f4b0 1545 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1546}
1547
1548
1549/*-------------------------------------------------------------------------*/
1550
1551/* device "function" sysfs attribute file */
1552static ssize_t show_function(struct device *_dev,
1553 struct device_attribute *attr, char *buf)
1554{
5bc639fc 1555 struct langwell_udc *dev = dev_get_drvdata(_dev);
5be19a9d
XS		 1556
1557 if (!dev->driver || !dev->driver->function
1558 || strlen(dev->driver->function) > PAGE_SIZE)
1559 return 0;
1560
1561 return scnprintf(buf, PAGE_SIZE, "%s\n", dev->driver->function);
1562}
1563static DEVICE_ATTR(function, S_IRUGO, show_function, NULL);
1564
1565
56526c0b
RD		 1566static inline enum usb_device_speed lpm_device_speed(u32 reg)
1567{
1568 switch (LPM_PSPD(reg)) {
1569 case LPM_SPEED_HIGH:
1570 return USB_SPEED_HIGH;
1571 case LPM_SPEED_FULL:
1572 return USB_SPEED_FULL;
1573 case LPM_SPEED_LOW:
1574 return USB_SPEED_LOW;
1575 default:
1576 return USB_SPEED_UNKNOWN;
1577 }
1578}
1579
5be19a9d
XS		 1580/* device "langwell_udc" sysfs attribute file */
1581static ssize_t show_langwell_udc(struct device *_dev,
1582 struct device_attribute *attr, char *buf)
1583{
5bc639fc 1584 struct langwell_udc *dev = dev_get_drvdata(_dev);
5be19a9d
XS		 1585 struct langwell_request *req;
1586 struct langwell_ep *ep = NULL;
1587 char *next;
1588 unsigned size;
1589 unsigned t;
1590 unsigned i;
1591 unsigned long flags;
1592 u32 tmp_reg;
1593
1594 next = buf;
1595 size = PAGE_SIZE;
1596 spin_lock_irqsave(&dev->lock, flags);
1597
1598 /* driver basic information */
1599 t = scnprintf(next, size,
1600 DRIVER_DESC "\n"
1601 "%s version: %s\n"
1602 "Gadget driver: %s\n\n",
1603 driver_name, DRIVER_VERSION,
1604 dev->driver ? dev->driver->driver.name : "(none)");
1605 size -= t;
1606 next += t;
1607
1608 /* device registers */
1609 tmp_reg = readl(&dev->op_regs->usbcmd);
1610 t = scnprintf(next, size,
1611 "USBCMD reg:\n"
1612 "SetupTW: %d\n"
1613 "Run/Stop: %s\n\n",
1614 (tmp_reg & CMD_SUTW) ? 1 : 0,
1615 (tmp_reg & CMD_RUNSTOP) ? "Run" : "Stop");
1616 size -= t;
1617 next += t;
1618
1619 tmp_reg = readl(&dev->op_regs->usbsts);
1620 t = scnprintf(next, size,
1621 "USB Status Reg:\n"
1622 "Device Suspend: %d\n"
1623 "Reset Received: %d\n"
1624 "System Error: %s\n"
1625 "USB Error Interrupt: %s\n\n",
1626 (tmp_reg & STS_SLI) ? 1 : 0,
1627 (tmp_reg & STS_URI) ? 1 : 0,
1628 (tmp_reg & STS_SEI) ? "Error" : "No error",
1629 (tmp_reg & STS_UEI) ? "Error detected" : "No error");
1630 size -= t;
1631 next += t;
1632
1633 tmp_reg = readl(&dev->op_regs->usbintr);
1634 t = scnprintf(next, size,
1635 "USB Intrrupt Enable Reg:\n"
1636 "Sleep Enable: %d\n"
1637 "SOF Received Enable: %d\n"
1638 "Reset Enable: %d\n"
1639 "System Error Enable: %d\n"
1640 "Port Change Dectected Enable: %d\n"
1641 "USB Error Intr Enable: %d\n"
1642 "USB Intr Enable: %d\n\n",
1643 (tmp_reg & INTR_SLE) ? 1 : 0,
1644 (tmp_reg & INTR_SRE) ? 1 : 0,
1645 (tmp_reg & INTR_URE) ? 1 : 0,
1646 (tmp_reg & INTR_SEE) ? 1 : 0,
1647 (tmp_reg & INTR_PCE) ? 1 : 0,
1648 (tmp_reg & INTR_UEE) ? 1 : 0,
1649 (tmp_reg & INTR_UE) ? 1 : 0);
1650 size -= t;
1651 next += t;
1652
1653 tmp_reg = readl(&dev->op_regs->frindex);
1654 t = scnprintf(next, size,
1655 "USB Frame Index Reg:\n"
1656 "Frame Number is 0x%08x\n\n",
1657 (tmp_reg & FRINDEX_MASK));
1658 size -= t;
1659 next += t;
1660
1661 tmp_reg = readl(&dev->op_regs->deviceaddr);
1662 t = scnprintf(next, size,
1663 "USB Device Address Reg:\n"
1664 "Device Addr is 0x%x\n\n",
1665 USBADR(tmp_reg));
1666 size -= t;
1667 next += t;
1668
1669 tmp_reg = readl(&dev->op_regs->endpointlistaddr);
1670 t = scnprintf(next, size,
1671 "USB Endpoint List Address Reg:\n"
1672 "Endpoint List Pointer is 0x%x\n\n",
1673 EPBASE(tmp_reg));
1674 size -= t;
1675 next += t;
1676
1677 tmp_reg = readl(&dev->op_regs->portsc1);
1678 t = scnprintf(next, size,
1679 "USB Port Status & Control Reg:\n"
1680 "Port Reset: %s\n"
1681 "Port Suspend Mode: %s\n"
1682 "Over-current Change: %s\n"
1683 "Port Enable/Disable Change: %s\n"
1684 "Port Enabled/Disabled: %s\n"
5f81f4b0
J		 1685 "Current Connect Status: %s\n"
1686 "LPM Suspend Status: %s\n\n",
5be19a9d
XS		 1687 (tmp_reg & PORTS_PR) ? "Reset" : "Not Reset",
1688 (tmp_reg & PORTS_SUSP) ? "Suspend " : "Not Suspend",
1689 (tmp_reg & PORTS_OCC) ? "Detected" : "No",
1690 (tmp_reg & PORTS_PEC) ? "Changed" : "Not Changed",
1691 (tmp_reg & PORTS_PE) ? "Enable" : "Not Correct",
5f81f4b0
J		 1692 (tmp_reg & PORTS_CCS) ? "Attached" : "Not Attached",
1693 (tmp_reg & PORTS_SLP) ? "LPM L1" : "LPM L0");
5be19a9d
XS		 1694 size -= t;
1695 next += t;
1696
1697 tmp_reg = readl(&dev->op_regs->devlc);
1698 t = scnprintf(next, size,
1699 "Device LPM Control Reg:\n"
1700 "Parallel Transceiver : %d\n"
1701 "Serial Transceiver : %d\n"
1702 "Port Speed: %s\n"
1703 "Port Force Full Speed Connenct: %s\n"
5f81f4b0 1704 "PHY Low Power Suspend Clock: %s\n"
5be19a9d
XS		 1705 "BmAttributes: %d\n\n",
1706 LPM_PTS(tmp_reg),
1707 (tmp_reg & LPM_STS) ? 1 : 0,
e538dfda 1708 usb_speed_string(lpm_device_speed(tmp_reg)),
5be19a9d
XS		 1709 (tmp_reg & LPM_PFSC) ? "Force Full Speed" : "Not Force",
1710 (tmp_reg & LPM_PHCD) ? "Disabled" : "Enabled",
1711 LPM_BA(tmp_reg));
1712 size -= t;
1713 next += t;
1714
1715 tmp_reg = readl(&dev->op_regs->usbmode);
1716 t = scnprintf(next, size,
1717 "USB Mode Reg:\n"
1718 "Controller Mode is : %s\n\n", ({
1719 char *s;
1720 switch (MODE_CM(tmp_reg)) {
1721 case MODE_IDLE:
1722 s = "Idle"; break;
1723 case MODE_DEVICE:
1724 s = "Device Controller"; break;
1725 case MODE_HOST:
1726 s = "Host Controller"; break;
1727 default:
1728 s = "None"; break;
1729 }
1730 s;
1731 }));
1732 size -= t;
1733 next += t;
1734
1735 tmp_reg = readl(&dev->op_regs->endptsetupstat);
1736 t = scnprintf(next, size,
1737 "Endpoint Setup Status Reg:\n"
1738 "SETUP on ep 0x%04x\n\n",
1739 tmp_reg & SETUPSTAT_MASK);
1740 size -= t;
1741 next += t;
1742
1743 for (i = 0; i < dev->ep_max / 2; i++) {
1744 tmp_reg = readl(&dev->op_regs->endptctrl[i]);
1745 t = scnprintf(next, size, "EP Ctrl Reg [%d]: 0x%08x\n",
1746 i, tmp_reg);
1747 size -= t;
1748 next += t;
1749 }
1750 tmp_reg = readl(&dev->op_regs->endptprime);
1751 t = scnprintf(next, size, "EP Prime Reg: 0x%08x\n\n", tmp_reg);
1752 size -= t;
1753 next += t;
1754
1755 /* langwell_udc, langwell_ep, langwell_request structure information */
1756 ep = &dev->ep[0];
1757 t = scnprintf(next, size, "%s MaxPacketSize: 0x%x, ep_num: %d\n",
1758 ep->ep.name, ep->ep.maxpacket, ep->ep_num);
1759 size -= t;
1760 next += t;
1761
1762 if (list_empty(&ep->queue)) {
1763 t = scnprintf(next, size, "its req queue is empty\n\n");
1764 size -= t;
1765 next += t;
1766 } else {
1767 list_for_each_entry(req, &ep->queue, queue) {
1768 t = scnprintf(next, size,
1769 "req %p actual 0x%x length 0x%x buf %p\n",
1770 &req->req, req->req.actual,
1771 req->req.length, req->req.buf);
1772 size -= t;
1773 next += t;
1774 }
1775 }
1776 /* other gadget->eplist ep */
1777 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
1778 if (ep->desc) {
1779 t = scnprintf(next, size,
1780 "\n%s MaxPacketSize: 0x%x, "
1781 "ep_num: %d\n",
1782 ep->ep.name, ep->ep.maxpacket,
1783 ep->ep_num);
1784 size -= t;
1785 next += t;
1786
1787 if (list_empty(&ep->queue)) {
1788 t = scnprintf(next, size,
1789 "its req queue is empty\n\n");
1790 size -= t;
1791 next += t;
1792 } else {
1793 list_for_each_entry(req, &ep->queue, queue) {
1794 t = scnprintf(next, size,
1795 "req %p actual 0x%x length "
1796 "0x%x buf %p\n",
1797 &req->req, req->req.actual,
1798 req->req.length, req->req.buf);
1799 size -= t;
1800 next += t;
1801 }
1802 }
1803 }
1804 }
1805
1806 spin_unlock_irqrestore(&dev->lock, flags);
1807 return PAGE_SIZE - size;
1808}
1809static DEVICE_ATTR(langwell_udc, S_IRUGO, show_langwell_udc, NULL);
1810
1811
3211cbc2
J		 1812/* device "remote_wakeup" sysfs attribute file */
1813static ssize_t store_remote_wakeup(struct device *_dev,
1814 struct device_attribute *attr, const char *buf, size_t count)
1815{
5bc639fc 1816 struct langwell_udc *dev = dev_get_drvdata(_dev);
3211cbc2
J		 1817 unsigned long flags;
1818 ssize_t rc = count;
1819
1820 if (count > 2)
1821 return -EINVAL;
1822
1823 if (count > 0 && buf[count-1] == '\n')
1824 ((char *) buf)[count-1] = 0;
1825
1826 if (buf[0] != '1')
1827 return -EINVAL;
1828
1829 /* force remote wakeup enabled in case gadget driver doesn't support */
1830 spin_lock_irqsave(&dev->lock, flags);
1831 dev->remote_wakeup = 1;
1832 dev->dev_status |= (1 << USB_DEVICE_REMOTE_WAKEUP);
1833 spin_unlock_irqrestore(&dev->lock, flags);
1834
1835 langwell_wakeup(&dev->gadget);
1836
1837 return rc;
1838}
1839static DEVICE_ATTR(remote_wakeup, S_IWUSR, NULL, store_remote_wakeup);
1840
1841
5be19a9d
XS		 1842/*-------------------------------------------------------------------------*/
1843
1844/*
1845 * when a driver is successfully registered, it will receive
1846 * control requests including set_configuration(), which enables
1847 * non-control requests. then usb traffic follows until a
1848 * disconnect is reported. then a host may connect again, or
1849 * the driver might get unbound.
1850 */
1851
2c7f0989
FB		 1852static int langwell_start(struct usb_gadget *g,
1853 struct usb_gadget_driver *driver)
5be19a9d 1854{
2c7f0989 1855 struct langwell_udc *dev = gadget_to_langwell(g);
5be19a9d
XS		 1856 unsigned long flags;
1857 int retval;
1858
5f81f4b0 1859 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d 1860
5be19a9d
XS		 1861 spin_lock_irqsave(&dev->lock, flags);
1862
1863 /* hook up the driver ... */
1864 driver->driver.bus = NULL;
1865 dev->driver = driver;
1866 dev->gadget.dev.driver = &driver->driver;
1867
1868 spin_unlock_irqrestore(&dev->lock, flags);
1869
5be19a9d
XS		 1870 retval = device_create_file(&dev->pdev->dev, &dev_attr_function);
1871 if (retval)
2c7f0989 1872 goto err;
5be19a9d
XS		 1873
1874 dev->usb_state = USB_STATE_ATTACHED;
1875 dev->ep0_state = WAIT_FOR_SETUP;
1876 dev->ep0_dir = USB_DIR_OUT;
1877
1878 /* enable interrupt and set controller to run state */
1879 if (dev->got_irq)
1880 langwell_udc_start(dev);
1881
5f81f4b0
J		 1882 dev_vdbg(&dev->pdev->dev,
1883 "After langwell_udc_start(), print all registers:\n");
5be19a9d 1884 print_all_registers(dev);
5be19a9d 1885
5f81f4b0
J		 1886 dev_info(&dev->pdev->dev, "register driver: %s\n",
1887 driver->driver.name);
1888 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2c7f0989 1889
5be19a9d
XS		 1890 return 0;
1891
2c7f0989 1892err:
5be19a9d
XS		 1893 dev->gadget.dev.driver = NULL;
1894 dev->driver = NULL;
1895
5f81f4b0 1896 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2c7f0989 1897
5be19a9d
XS		 1898 return retval;
1899}
5be19a9d
XS		 1900
1901/* unregister gadget driver */
2c7f0989
FB		 1902static int langwell_stop(struct usb_gadget *g,
1903 struct usb_gadget_driver *driver)
5be19a9d 1904{
2c7f0989 1905 struct langwell_udc *dev = gadget_to_langwell(g);
5be19a9d
XS		 1906 unsigned long flags;
1907
5f81f4b0 1908 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d 1909
513b91b6
J		 1910 /* exit PHY low power suspend */
1911 if (dev->pdev->device != 0x0829)
1912 langwell_phy_low_power(dev, 0);
1913
5be19a9d
XS		 1914 /* unbind OTG transceiver */
1915 if (dev->transceiver)
1916 (void)otg_set_peripheral(dev->transceiver, 0);
1917
1918 /* disable interrupt and set controller to stop state */
1919 langwell_udc_stop(dev);
1920
1921 dev->usb_state = USB_STATE_ATTACHED;
1922 dev->ep0_state = WAIT_FOR_SETUP;
1923 dev->ep0_dir = USB_DIR_OUT;
1924
1925 spin_lock_irqsave(&dev->lock, flags);
1926
1927 /* stop all usb activities */
1928 dev->gadget.speed = USB_SPEED_UNKNOWN;
1929 stop_activity(dev, driver);
1930 spin_unlock_irqrestore(&dev->lock, flags);
1931
5be19a9d
XS		 1932 dev->gadget.dev.driver = NULL;
1933 dev->driver = NULL;
1934
1935 device_remove_file(&dev->pdev->dev, &dev_attr_function);
1936
5f81f4b0
J		 1937 dev_info(&dev->pdev->dev, "unregistered driver '%s'\n",
1938 driver->driver.name);
1939 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2c7f0989 1940
5be19a9d
XS		 1941 return 0;
1942}
5be19a9d
XS		 1943
1944/*-------------------------------------------------------------------------*/
1945
1946/*
1947 * setup tripwire is used as a semaphore to ensure that the setup data
1948 * payload is extracted from a dQH without being corrupted
1949 */
1950static void setup_tripwire(struct langwell_udc *dev)
1951{
1952 u32 usbcmd,
1953 endptsetupstat;
1954 unsigned long timeout;
1955 struct langwell_dqh *dqh;
1956
5f81f4b0 1957 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1958
1959 /* ep0 OUT dQH */
1960 dqh = &dev->ep_dqh[EP_DIR_OUT];
1961
1962 /* Write-Clear endptsetupstat */
1963 endptsetupstat = readl(&dev->op_regs->endptsetupstat);
1964 writel(endptsetupstat, &dev->op_regs->endptsetupstat);
1965
1966 /* wait until endptsetupstat is cleared */
1967 timeout = jiffies + SETUPSTAT_TIMEOUT;
1968 while (readl(&dev->op_regs->endptsetupstat)) {
1969 if (time_after(jiffies, timeout)) {
5f81f4b0 1970 dev_err(&dev->pdev->dev, "setup_tripwire timeout\n");
5be19a9d
XS		 1971 break;
1972 }
1973 cpu_relax();
1974 }
1975
1976 /* while a hazard exists when setup packet arrives */
1977 do {
1978 /* set setup tripwire bit */
1979 usbcmd = readl(&dev->op_regs->usbcmd);
1980 writel(usbcmd | CMD_SUTW, &dev->op_regs->usbcmd);
1981
1982 /* copy the setup packet to local buffer */
1983 memcpy(&dev->local_setup_buff, &dqh->dqh_setup, 8);
1984 } while (!(readl(&dev->op_regs->usbcmd) & CMD_SUTW));
1985
1986 /* Write-Clear setup tripwire bit */
1987 usbcmd = readl(&dev->op_regs->usbcmd);
1988 writel(usbcmd & ~CMD_SUTW, &dev->op_regs->usbcmd);
1989
5f81f4b0 1990 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1991}
1992
1993
1994/* protocol ep0 stall, will automatically be cleared on new transaction */
1995static void ep0_stall(struct langwell_udc *dev)
1996{
1997 u32 endptctrl;
1998
5f81f4b0 1999 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2000
2001 /* set TX and RX to stall */
2002 endptctrl = readl(&dev->op_regs->endptctrl[0]);
2003 endptctrl |= EPCTRL_TXS | EPCTRL_RXS;
2004 writel(endptctrl, &dev->op_regs->endptctrl[0]);
2005
2006 /* update ep0 state */
2007 dev->ep0_state = WAIT_FOR_SETUP;
2008 dev->ep0_dir = USB_DIR_OUT;
2009
5f81f4b0 2010 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2011}
2012
2013
2014/* PRIME a status phase for ep0 */
2015static int prime_status_phase(struct langwell_udc *dev, int dir)
2016{
2017 struct langwell_request *req;
2018 struct langwell_ep *ep;
2019 int status = 0;
2020
5f81f4b0 2021 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2022
2023 if (dir == EP_DIR_IN)
2024 dev->ep0_dir = USB_DIR_IN;
2025 else
2026 dev->ep0_dir = USB_DIR_OUT;
2027
2028 ep = &dev->ep[0];
2029 dev->ep0_state = WAIT_FOR_OUT_STATUS;
2030
2031 req = dev->status_req;
2032
2033 req->ep = ep;
2034 req->req.length = 0;
2035 req->req.status = -EINPROGRESS;
2036 req->req.actual = 0;
2037 req->req.complete = NULL;
2038 req->dtd_count = 0;
2039
2040 if (!req_to_dtd(req))
2041 status = queue_dtd(ep, req);
2042 else
2043 return -ENOMEM;
2044
2045 if (status)
5f81f4b0 2046 dev_err(&dev->pdev->dev, "can't queue ep0 status request\n");
5be19a9d
XS		 2047
2048 list_add_tail(&req->queue, &ep->queue);
2049
5f81f4b0 2050 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2051 return status;
2052}
2053
2054
2055/* SET_ADDRESS request routine */
2056static void set_address(struct langwell_udc *dev, u16 value,
2057 u16 index, u16 length)
2058{
5f81f4b0 2059 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2060
2061 /* save the new address to device struct */
2062 dev->dev_addr = (u8) value;
5f81f4b0 2063 dev_vdbg(&dev->pdev->dev, "dev->dev_addr = %d\n", dev->dev_addr);
5be19a9d
XS		 2064
2065 /* update usb state */
2066 dev->usb_state = USB_STATE_ADDRESS;
2067
2068 /* STATUS phase */
2069 if (prime_status_phase(dev, EP_DIR_IN))
2070 ep0_stall(dev);
2071
5f81f4b0 2072 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2073}
2074
2075
2076/* return endpoint by windex */
2077static struct langwell_ep *get_ep_by_windex(struct langwell_udc *dev,
2078 u16 wIndex)
2079{
2080 struct langwell_ep *ep;
5f81f4b0 2081 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2082
2083 if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
2084 return &dev->ep[0];
2085
2086 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
2087 u8 bEndpointAddress;
2088 if (!ep->desc)
2089 continue;
2090
2091 bEndpointAddress = ep->desc->bEndpointAddress;
2092 if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
2093 continue;
2094
2095 if ((wIndex & USB_ENDPOINT_NUMBER_MASK)
2096 == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK))
2097 return ep;
2098 }
2099
5f81f4b0 2100 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2101 return NULL;
2102}
2103
2104
2105/* return whether endpoint is stalled, 0: not stalled; 1: stalled */
2106static int ep_is_stall(struct langwell_ep *ep)
2107{
2108 struct langwell_udc *dev = ep->dev;
2109 u32 endptctrl;
2110 int retval;
2111
5f81f4b0 2112 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2113
2114 endptctrl = readl(&dev->op_regs->endptctrl[ep->ep_num]);
2115 if (is_in(ep))
2116 retval = endptctrl & EPCTRL_TXS ? 1 : 0;
2117 else
2118 retval = endptctrl & EPCTRL_RXS ? 1 : 0;
2119
5f81f4b0 2120 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2121 return retval;
2122}
2123
2124
2125/* GET_STATUS request routine */
2126static void get_status(struct langwell_udc *dev, u8 request_type, u16 value,
2127 u16 index, u16 length)
2128{
2129 struct langwell_request *req;
2130 struct langwell_ep *ep;
2131 u16 status_data = 0; /* 16 bits cpu view status data */
2132 int status = 0;
2133
5f81f4b0 2134 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2135
2136 ep = &dev->ep[0];
2137
2138 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
2139 /* get device status */
3211cbc2 2140 status_data = dev->dev_status;
5be19a9d
XS		 2141 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
2142 /* get interface status */
2143 status_data = 0;
2144 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
2145 /* get endpoint status */
2146 struct langwell_ep *epn;
2147 epn = get_ep_by_windex(dev, index);
2148 /* stall if endpoint doesn't exist */
2149 if (!epn)
2150 goto stall;
2151
2152 status_data = ep_is_stall(epn) << USB_ENDPOINT_HALT;
2153 }
2154
5f81f4b0
J		 2155 dev_dbg(&dev->pdev->dev, "get status data: 0x%04x\n", status_data);
2156
5be19a9d
XS		 2157 dev->ep0_dir = USB_DIR_IN;
2158
2159 /* borrow the per device status_req */
2160 req = dev->status_req;
2161
2162 /* fill in the reqest structure */
2163 *((u16 *) req->req.buf) = cpu_to_le16(status_data);
2164 req->ep = ep;
2165 req->req.length = 2;
2166 req->req.status = -EINPROGRESS;
2167 req->req.actual = 0;
2168 req->req.complete = NULL;
2169 req->dtd_count = 0;
2170
2171 /* prime the data phase */
2172 if (!req_to_dtd(req))
2173 status = queue_dtd(ep, req);
2174 else /* no mem */
2175 goto stall;
2176
2177 if (status) {
5f81f4b0
J		 2178 dev_err(&dev->pdev->dev,
2179 "response error on GET_STATUS request\n");
5be19a9d
XS		 2180 goto stall;
2181 }
2182
2183 list_add_tail(&req->queue, &ep->queue);
2184 dev->ep0_state = DATA_STATE_XMIT;
2185
5f81f4b0 2186 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2187 return;
2188stall:
2189 ep0_stall(dev);
5f81f4b0 2190 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2191}
2192
2193
2194/* setup packet interrupt handler */
2195static void handle_setup_packet(struct langwell_udc *dev,
2196 struct usb_ctrlrequest *setup)
2197{
2198 u16 wValue = le16_to_cpu(setup->wValue);
2199 u16 wIndex = le16_to_cpu(setup->wIndex);
2200 u16 wLength = le16_to_cpu(setup->wLength);
7fc56f0d 2201 u32 portsc1;
5be19a9d 2202
5f81f4b0 2203 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2204
2205 /* ep0 fifo flush */
2206 nuke(&dev->ep[0], -ESHUTDOWN);
2207
5f81f4b0 2208 dev_dbg(&dev->pdev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
5be19a9d
XS		 2209 setup->bRequestType, setup->bRequest,
2210 wValue, wIndex, wLength);
2211
2212 /* RNDIS gadget delegate */
2213 if ((setup->bRequestType == 0x21) && (setup->bRequest == 0x00)) {
2214 /* USB_CDC_SEND_ENCAPSULATED_COMMAND */
2215 goto delegate;
2216 }
2217
2218 /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
2219 if ((setup->bRequestType == 0xa1) && (setup->bRequest == 0x01)) {
2220 /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
2221 goto delegate;
2222 }
2223
2224 /* We process some stardard setup requests here */
2225 switch (setup->bRequest) {
2226 case USB_REQ_GET_STATUS:
5f81f4b0 2227 dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_GET_STATUS\n");
5be19a9d
XS		 2228 /* get status, DATA and STATUS phase */
2229 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
2230 != (USB_DIR_IN | USB_TYPE_STANDARD))
2231 break;
2232 get_status(dev, setup->bRequestType, wValue, wIndex, wLength);
2233 goto end;
2234
2235 case USB_REQ_SET_ADDRESS:
5f81f4b0 2236 dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_SET_ADDRESS\n");
5be19a9d
XS		 2237 /* STATUS phase */
2238 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
2239 | USB_RECIP_DEVICE))
2240 break;
2241 set_address(dev, wValue, wIndex, wLength);
2242 goto end;
2243
2244 case USB_REQ_CLEAR_FEATURE:
2245 case USB_REQ_SET_FEATURE:
2246 /* STATUS phase */
2247 {
2248 int rc = -EOPNOTSUPP;
2249 if (setup->bRequest == USB_REQ_SET_FEATURE)
5f81f4b0
J		 2250 dev_dbg(&dev->pdev->dev,
2251 "SETUP: USB_REQ_SET_FEATURE\n");
5be19a9d 2252 else if (setup->bRequest == USB_REQ_CLEAR_FEATURE)
5f81f4b0
J		 2253 dev_dbg(&dev->pdev->dev,
2254 "SETUP: USB_REQ_CLEAR_FEATURE\n");
5be19a9d
XS		 2255
2256 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
2257 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
2258 struct langwell_ep *epn;
2259 epn = get_ep_by_windex(dev, wIndex);
2260 /* stall if endpoint doesn't exist */
2261 if (!epn) {
2262 ep0_stall(dev);
2263 goto end;
2264 }
2265
2266 if (wValue != 0 || wLength != 0
2267 || epn->ep_num > dev->ep_max)
2268 break;
2269
2270 spin_unlock(&dev->lock);
2271 rc = langwell_ep_set_halt(&epn->ep,
5f81f4b0
J		 2272 (setup->bRequest == USB_REQ_SET_FEATURE)
2273 ? 1 : 0);
5be19a9d
XS		 2274 spin_lock(&dev->lock);
2275
2276 } else if ((setup->bRequestType & (USB_RECIP_MASK
2277 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
2278 | USB_TYPE_STANDARD)) {
3211cbc2
J		 2279 rc = 0;
2280 switch (wValue) {
2281 case USB_DEVICE_REMOTE_WAKEUP:
2282 if (setup->bRequest == USB_REQ_SET_FEATURE) {
2283 dev->remote_wakeup = 1;
2284 dev->dev_status |= (1 << wValue);
2285 } else {
2286 dev->remote_wakeup = 0;
2287 dev->dev_status &= ~(1 << wValue);
2288 }
2289 break;
7fc56f0d
LA		 2290 case USB_DEVICE_TEST_MODE:
2291 dev_dbg(&dev->pdev->dev, "SETUP: TEST MODE\n");
2292 if ((wIndex & 0xff) ||
2293 (dev->gadget.speed != USB_SPEED_HIGH))
2294 ep0_stall(dev);
2295
2296 switch (wIndex >> 8) {
2297 case TEST_J:
2298 case TEST_K:
2299 case TEST_SE0_NAK:
2300 case TEST_PACKET:
2301 case TEST_FORCE_EN:
2302 if (prime_status_phase(dev, EP_DIR_IN))
2303 ep0_stall(dev);
2304 portsc1 = readl(&dev->op_regs->portsc1);
2305 portsc1 |= (wIndex & 0xf00) << 8;
2306 writel(portsc1, &dev->op_regs->portsc1);
2307 goto end;
2308 default:
2309 rc = -EOPNOTSUPP;
2310 }
2311 break;
3211cbc2
J		 2312 default:
2313 rc = -EOPNOTSUPP;
2314 break;
2315 }
2316
5be19a9d
XS		 2317 if (!gadget_is_otg(&dev->gadget))
2318 break;
2319 else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE) {
2320 dev->gadget.b_hnp_enable = 1;
2321#ifdef OTG_TRANSCEIVER
2322 if (!dev->lotg->otg.default_a)
2323 dev->lotg->hsm.b_hnp_enable = 1;
2324#endif
2325 } else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
2326 dev->gadget.a_hnp_support = 1;
2327 else if (setup->bRequest ==
2328 USB_DEVICE_A_ALT_HNP_SUPPORT)
2329 dev->gadget.a_alt_hnp_support = 1;
2330 else
2331 break;
5be19a9d
XS		 2332 } else
2333 break;
2334
2335 if (rc == 0) {
2336 if (prime_status_phase(dev, EP_DIR_IN))
2337 ep0_stall(dev);
2338 }
2339 goto end;
2340 }
2341
2342 case USB_REQ_GET_DESCRIPTOR:
5f81f4b0
J		 2343 dev_dbg(&dev->pdev->dev,
2344 "SETUP: USB_REQ_GET_DESCRIPTOR\n");
5be19a9d
XS		 2345 goto delegate;
2346
2347 case USB_REQ_SET_DESCRIPTOR:
5f81f4b0
J		 2348 dev_dbg(&dev->pdev->dev,
2349 "SETUP: USB_REQ_SET_DESCRIPTOR unsupported\n");
5be19a9d
XS		 2350 goto delegate;
2351
2352 case USB_REQ_GET_CONFIGURATION:
5f81f4b0
J		 2353 dev_dbg(&dev->pdev->dev,
2354 "SETUP: USB_REQ_GET_CONFIGURATION\n");
5be19a9d
XS		 2355 goto delegate;
2356
2357 case USB_REQ_SET_CONFIGURATION:
5f81f4b0
J		 2358 dev_dbg(&dev->pdev->dev,
2359 "SETUP: USB_REQ_SET_CONFIGURATION\n");
5be19a9d
XS		 2360 goto delegate;
2361
2362 case USB_REQ_GET_INTERFACE:
5f81f4b0
J		 2363 dev_dbg(&dev->pdev->dev,
2364 "SETUP: USB_REQ_GET_INTERFACE\n");
5be19a9d
XS		 2365 goto delegate;
2366
2367 case USB_REQ_SET_INTERFACE:
5f81f4b0
J		 2368 dev_dbg(&dev->pdev->dev,
2369 "SETUP: USB_REQ_SET_INTERFACE\n");
5be19a9d
XS		 2370 goto delegate;
2371
2372 case USB_REQ_SYNCH_FRAME:
5f81f4b0
J		 2373 dev_dbg(&dev->pdev->dev,
2374 "SETUP: USB_REQ_SYNCH_FRAME unsupported\n");
5be19a9d
XS		 2375 goto delegate;
2376
2377 default:
2378 /* delegate USB standard requests to the gadget driver */
2379 goto delegate;
2380delegate:
2381 /* USB requests handled by gadget */
2382 if (wLength) {
2383 /* DATA phase from gadget, STATUS phase from udc */
2384 dev->ep0_dir = (setup->bRequestType & USB_DIR_IN)
2385 ? USB_DIR_IN : USB_DIR_OUT;
5f81f4b0
J		 2386 dev_vdbg(&dev->pdev->dev,
2387 "dev->ep0_dir = 0x%x, wLength = %d\n",
5be19a9d
XS		 2388 dev->ep0_dir, wLength);
2389 spin_unlock(&dev->lock);
2390 if (dev->driver->setup(&dev->gadget,
2391 &dev->local_setup_buff) < 0)
2392 ep0_stall(dev);
2393 spin_lock(&dev->lock);
2394 dev->ep0_state = (setup->bRequestType & USB_DIR_IN)
2395 ? DATA_STATE_XMIT : DATA_STATE_RECV;
2396 } else {
2397 /* no DATA phase, IN STATUS phase from gadget */
2398 dev->ep0_dir = USB_DIR_IN;
5f81f4b0
J		 2399 dev_vdbg(&dev->pdev->dev,
2400 "dev->ep0_dir = 0x%x, wLength = %d\n",
5be19a9d
XS		 2401 dev->ep0_dir, wLength);
2402 spin_unlock(&dev->lock);
2403 if (dev->driver->setup(&dev->gadget,
2404 &dev->local_setup_buff) < 0)
2405 ep0_stall(dev);
2406 spin_lock(&dev->lock);
2407 dev->ep0_state = WAIT_FOR_OUT_STATUS;
2408 }
2409 break;
2410 }
2411end:
5f81f4b0 2412 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2413}
2414
2415
2416/* transfer completion, process endpoint request and free the completed dTDs
2417 * for this request
2418 */
2419static int process_ep_req(struct langwell_udc *dev, int index,
2420 struct langwell_request *curr_req)
2421{
2422 struct langwell_dtd *curr_dtd;
2423 struct langwell_dqh *curr_dqh;
2424 int td_complete, actual, remaining_length;
2425 int i, dir;
2426 u8 dtd_status = 0;
2427 int retval = 0;
2428
2429 curr_dqh = &dev->ep_dqh[index];
2430 dir = index % 2;
2431
2432 curr_dtd = curr_req->head;
2433 td_complete = 0;
2434 actual = curr_req->req.length;
2435
5f81f4b0 2436 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2437
2438 for (i = 0; i < curr_req->dtd_count; i++) {
5be19a9d
XS		 2439
2440 /* command execution states by dTD */
2441 dtd_status = curr_dtd->dtd_status;
2442
c8458d59
CL		 2443 barrier();
2444 remaining_length = le16_to_cpu(curr_dtd->dtd_total);
2445 actual -= remaining_length;
2446
5be19a9d
XS		 2447 if (!dtd_status) {
2448 /* transfers completed successfully */
2449 if (!remaining_length) {
2450 td_complete++;
5f81f4b0
J		 2451 dev_vdbg(&dev->pdev->dev,
2452 "dTD transmitted successfully\n");
5be19a9d
XS		 2453 } else {
2454 if (dir) {
5f81f4b0
J		 2455 dev_vdbg(&dev->pdev->dev,
2456 "TX dTD remains data\n");
5be19a9d
XS		 2457 retval = -EPROTO;
2458 break;
2459
2460 } else {
2461 td_complete++;
2462 break;
2463 }
2464 }
2465 } else {
2466 /* transfers completed with errors */
2467 if (dtd_status & DTD_STS_ACTIVE) {
5f81f4b0
J		 2468 dev_dbg(&dev->pdev->dev,
2469 "dTD status ACTIVE dQH[%d]\n", index);
5be19a9d
XS		 2470 retval = 1;
2471 return retval;
2472 } else if (dtd_status & DTD_STS_HALTED) {
5f81f4b0
J		 2473 dev_err(&dev->pdev->dev,
2474 "dTD error %08x dQH[%d]\n",
2475 dtd_status, index);
5be19a9d
XS		 2476 /* clear the errors and halt condition */
2477 curr_dqh->dtd_status = 0;
2478 retval = -EPIPE;
2479 break;
2480 } else if (dtd_status & DTD_STS_DBE) {
5f81f4b0
J		 2481 dev_dbg(&dev->pdev->dev,
2482 "data buffer (overflow) error\n");
5be19a9d
XS		 2483 retval = -EPROTO;
2484 break;
2485 } else if (dtd_status & DTD_STS_TRE) {
5f81f4b0
J		 2486 dev_dbg(&dev->pdev->dev,
2487 "transaction(ISO) error\n");
5be19a9d
XS		 2488 retval = -EILSEQ;
2489 break;
2490 } else
5f81f4b0
J		 2491 dev_err(&dev->pdev->dev,
2492 "unknown error (0x%x)!\n",
2493 dtd_status);
5be19a9d
XS		 2494 }
2495
2496 if (i != curr_req->dtd_count - 1)
2497 curr_dtd = (struct langwell_dtd *)
2498 curr_dtd->next_dtd_virt;
2499 }
2500
2501 if (retval)
2502 return retval;
2503
2504 curr_req->req.actual = actual;
2505
5f81f4b0 2506 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2507 return 0;
2508}
2509
2510
2511/* complete DATA or STATUS phase of ep0 prime status phase if needed */
2512static void ep0_req_complete(struct langwell_udc *dev,
2513 struct langwell_ep *ep0, struct langwell_request *req)
2514{
2515 u32 new_addr;
5f81f4b0 2516 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2517
2518 if (dev->usb_state == USB_STATE_ADDRESS) {
2519 /* set the new address */
2520 new_addr = (u32)dev->dev_addr;
2521 writel(new_addr << USBADR_SHIFT, &dev->op_regs->deviceaddr);
2522
2523 new_addr = USBADR(readl(&dev->op_regs->deviceaddr));
5f81f4b0 2524 dev_vdbg(&dev->pdev->dev, "new_addr = %d\n", new_addr);
5be19a9d
XS		 2525 }
2526
2527 done(ep0, req, 0);
2528
2529 switch (dev->ep0_state) {
2530 case DATA_STATE_XMIT:
2531 /* receive status phase */
2532 if (prime_status_phase(dev, EP_DIR_OUT))
2533 ep0_stall(dev);
2534 break;
2535 case DATA_STATE_RECV:
2536 /* send status phase */
2537 if (prime_status_phase(dev, EP_DIR_IN))
2538 ep0_stall(dev);
2539 break;
2540 case WAIT_FOR_OUT_STATUS:
2541 dev->ep0_state = WAIT_FOR_SETUP;
2542 break;
2543 case WAIT_FOR_SETUP:
5f81f4b0 2544 dev_err(&dev->pdev->dev, "unexpect ep0 packets\n");
5be19a9d
XS		 2545 break;
2546 default:
2547 ep0_stall(dev);
2548 break;
2549 }
2550
5f81f4b0 2551 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2552}
2553
2554
2555/* USB transfer completion interrupt */
2556static void handle_trans_complete(struct langwell_udc *dev)
2557{
2558 u32 complete_bits;
2559 int i, ep_num, dir, bit_mask, status;
2560 struct langwell_ep *epn;
2561 struct langwell_request *curr_req, *temp_req;
2562
5f81f4b0 2563 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2564
2565 complete_bits = readl(&dev->op_regs->endptcomplete);
5f81f4b0
J		 2566 dev_vdbg(&dev->pdev->dev, "endptcomplete register: 0x%08x\n",
2567 complete_bits);
5be19a9d
XS		 2568
2569 /* Write-Clear the bits in endptcomplete register */
2570 writel(complete_bits, &dev->op_regs->endptcomplete);
2571
2572 if (!complete_bits) {
5f81f4b0 2573 dev_dbg(&dev->pdev->dev, "complete_bits = 0\n");
5be19a9d
XS		 2574 goto done;
2575 }
2576
2577 for (i = 0; i < dev->ep_max; i++) {
2578 ep_num = i / 2;
2579 dir = i % 2;
2580
2581 bit_mask = 1 << (ep_num + 16 * dir);
2582
2583 if (!(complete_bits & bit_mask))
2584 continue;
2585
2586 /* ep0 */
2587 if (i == 1)
2588 epn = &dev->ep[0];
2589 else
2590 epn = &dev->ep[i];
2591
2592 if (epn->name == NULL) {
5f81f4b0 2593 dev_warn(&dev->pdev->dev, "invalid endpoint\n");
5be19a9d
XS		 2594 continue;
2595 }
2596
2597 if (i < 2)
2598 /* ep0 in and out */
5f81f4b0 2599 dev_dbg(&dev->pdev->dev, "%s-%s transfer completed\n",
5be19a9d
XS		 2600 epn->name,
2601 is_in(epn) ? "in" : "out");
2602 else
5f81f4b0
J		 2603 dev_dbg(&dev->pdev->dev, "%s transfer completed\n",
2604 epn->name);
5be19a9d
XS		 2605
2606 /* process the req queue until an uncomplete request */
2607 list_for_each_entry_safe(curr_req, temp_req,
2608 &epn->queue, queue) {
2609 status = process_ep_req(dev, i, curr_req);
5f81f4b0
J		 2610 dev_vdbg(&dev->pdev->dev, "%s req status: %d\n",
2611 epn->name, status);
5be19a9d
XS		 2612
2613 if (status)
2614 break;
2615
2616 /* write back status to req */
2617 curr_req->req.status = status;
2618
2619 /* ep0 request completion */
2620 if (ep_num == 0) {
2621 ep0_req_complete(dev, epn, curr_req);
2622 break;
2623 } else {
2624 done(epn, curr_req, status);
2625 }
2626 }
2627 }
2628done:
5f81f4b0 2629 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2630}
2631
5be19a9d
XS		 2632/* port change detect interrupt handler */
2633static void handle_port_change(struct langwell_udc *dev)
2634{
2635 u32 portsc1, devlc;
5be19a9d 2636
5f81f4b0 2637 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2638
2639 if (dev->bus_reset)
2640 dev->bus_reset = 0;
2641
2642 portsc1 = readl(&dev->op_regs->portsc1);
2643 devlc = readl(&dev->op_regs->devlc);
5f81f4b0 2644 dev_vdbg(&dev->pdev->dev, "portsc1 = 0x%08x, devlc = 0x%08x\n",
5be19a9d
XS		 2645 portsc1, devlc);
2646
2647 /* bus reset is finished */
2648 if (!(portsc1 & PORTS_PR)) {
2649 /* get the speed */
e538dfda
MN		 2650 dev->gadget.speed = lpm_device_speed(devlc);
2651 dev_vdbg(&dev->pdev->dev, "dev->gadget.speed = %d\n",
2652 dev->gadget.speed);
5be19a9d
XS		 2653 }
2654
2655 /* LPM L0 to L1 */
2656 if (dev->lpm && dev->lpm_state == LPM_L0)
2657 if (portsc1 & PORTS_SUSP && portsc1 & PORTS_SLP) {
5f81f4b0
J		 2658 dev_info(&dev->pdev->dev, "LPM L0 to L1\n");
2659 dev->lpm_state = LPM_L1;
5be19a9d
XS		 2660 }
2661
2662 /* LPM L1 to L0, force resume or remote wakeup finished */
2663 if (dev->lpm && dev->lpm_state == LPM_L1)
2664 if (!(portsc1 & PORTS_SUSP)) {
5f81f4b0 2665 dev_info(&dev->pdev->dev, "LPM L1 to L0\n");
5be19a9d
XS		 2666 dev->lpm_state = LPM_L0;
2667 }
2668
2669 /* update USB state */
2670 if (!dev->resume_state)
2671 dev->usb_state = USB_STATE_DEFAULT;
2672
5f81f4b0 2673 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2674}
2675
2676
2677/* USB reset interrupt handler */
2678static void handle_usb_reset(struct langwell_udc *dev)
2679{
2680 u32 deviceaddr,
2681 endptsetupstat,
2682 endptcomplete;
2683 unsigned long timeout;
2684
5f81f4b0 2685 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2686
2687 /* Write-Clear the device address */
2688 deviceaddr = readl(&dev->op_regs->deviceaddr);
2689 writel(deviceaddr & ~USBADR_MASK, &dev->op_regs->deviceaddr);
2690
2691 dev->dev_addr = 0;
2692
2693 /* clear usb state */
2694 dev->resume_state = 0;
2695
2696 /* LPM L1 to L0, reset */
2697 if (dev->lpm)
2698 dev->lpm_state = LPM_L0;
2699
2700 dev->ep0_dir = USB_DIR_OUT;
2701 dev->ep0_state = WAIT_FOR_SETUP;
3211cbc2
J		 2702
2703 /* remote wakeup reset to 0 when the device is reset */
2704 dev->remote_wakeup = 0;
2705 dev->dev_status = 1 << USB_DEVICE_SELF_POWERED;
5be19a9d
XS		 2706 dev->gadget.b_hnp_enable = 0;
2707 dev->gadget.a_hnp_support = 0;
2708 dev->gadget.a_alt_hnp_support = 0;
2709
2710 /* Write-Clear all the setup token semaphores */
2711 endptsetupstat = readl(&dev->op_regs->endptsetupstat);
2712 writel(endptsetupstat, &dev->op_regs->endptsetupstat);
2713
2714 /* Write-Clear all the endpoint complete status bits */
2715 endptcomplete = readl(&dev->op_regs->endptcomplete);
2716 writel(endptcomplete, &dev->op_regs->endptcomplete);
2717
2718 /* wait until all endptprime bits cleared */
2719 timeout = jiffies + PRIME_TIMEOUT;
2720 while (readl(&dev->op_regs->endptprime)) {
2721 if (time_after(jiffies, timeout)) {
5f81f4b0 2722 dev_err(&dev->pdev->dev, "USB reset timeout\n");
5be19a9d
XS		 2723 break;
2724 }
2725 cpu_relax();
2726 }
2727
2728 /* write 1s to endptflush register to clear any primed buffers */
2729 writel((u32) ~0, &dev->op_regs->endptflush);
2730
2731 if (readl(&dev->op_regs->portsc1) & PORTS_PR) {
5f81f4b0 2732 dev_vdbg(&dev->pdev->dev, "USB bus reset\n");
5be19a9d
XS		 2733 /* bus is reseting */
2734 dev->bus_reset = 1;
2735
2736 /* reset all the queues, stop all USB activities */
2737 stop_activity(dev, dev->driver);
2738 dev->usb_state = USB_STATE_DEFAULT;
2739 } else {
5f81f4b0 2740 dev_vdbg(&dev->pdev->dev, "device controller reset\n");
5be19a9d
XS		 2741 /* controller reset */
2742 langwell_udc_reset(dev);
2743
2744 /* reset all the queues, stop all USB activities */
2745 stop_activity(dev, dev->driver);
2746
2747 /* reset ep0 dQH and endptctrl */
2748 ep0_reset(dev);
2749
2750 /* enable interrupt and set controller to run state */
2751 langwell_udc_start(dev);
2752
2753 dev->usb_state = USB_STATE_ATTACHED;
2754 }
2755
2756#ifdef OTG_TRANSCEIVER
2757 /* refer to USB OTG 6.6.2.3 b_hnp_en is cleared */
2758 if (!dev->lotg->otg.default_a)
2759 dev->lotg->hsm.b_hnp_enable = 0;
2760#endif
2761
5f81f4b0 2762 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2763}
2764
2765
2766/* USB bus suspend/resume interrupt */
2767static void handle_bus_suspend(struct langwell_udc *dev)
2768{
5f81f4b0 2769 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2770
2771 dev->resume_state = dev->usb_state;
2772 dev->usb_state = USB_STATE_SUSPENDED;
2773
2774#ifdef OTG_TRANSCEIVER
2775 if (dev->lotg->otg.default_a) {
2776 if (dev->lotg->hsm.b_bus_suspend_vld == 1) {
2777 dev->lotg->hsm.b_bus_suspend = 1;
2778 /* notify transceiver the state changes */
2779 if (spin_trylock(&dev->lotg->wq_lock)) {
2780 langwell_update_transceiver();
2781 spin_unlock(&dev->lotg->wq_lock);
2782 }
2783 }
2784 dev->lotg->hsm.b_bus_suspend_vld++;
2785 } else {
2786 if (!dev->lotg->hsm.a_bus_suspend) {
2787 dev->lotg->hsm.a_bus_suspend = 1;
2788 /* notify transceiver the state changes */
2789 if (spin_trylock(&dev->lotg->wq_lock)) {
2790 langwell_update_transceiver();
2791 spin_unlock(&dev->lotg->wq_lock);
2792 }
2793 }
2794 }
2795#endif
2796
2797 /* report suspend to the driver */
2798 if (dev->driver) {
2799 if (dev->driver->suspend) {
2800 spin_unlock(&dev->lock);
2801 dev->driver->suspend(&dev->gadget);
2802 spin_lock(&dev->lock);
5f81f4b0
J		 2803 dev_dbg(&dev->pdev->dev, "suspend %s\n",
2804 dev->driver->driver.name);
5be19a9d
XS		 2805 }
2806 }
2807
2808 /* enter PHY low power suspend */
513b91b6
J		 2809 if (dev->pdev->device != 0x0829)
2810 langwell_phy_low_power(dev, 0);
5be19a9d 2811
5f81f4b0 2812 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2813}
2814
2815
2816static void handle_bus_resume(struct langwell_udc *dev)
2817{
5f81f4b0 2818 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2819
2820 dev->usb_state = dev->resume_state;
2821 dev->resume_state = 0;
2822
2823 /* exit PHY low power suspend */
513b91b6
J		 2824 if (dev->pdev->device != 0x0829)
2825 langwell_phy_low_power(dev, 0);
5be19a9d
XS		 2826
2827#ifdef OTG_TRANSCEIVER
2828 if (dev->lotg->otg.default_a == 0)
2829 dev->lotg->hsm.a_bus_suspend = 0;
2830#endif
2831
2832 /* report resume to the driver */
2833 if (dev->driver) {
2834 if (dev->driver->resume) {
2835 spin_unlock(&dev->lock);
2836 dev->driver->resume(&dev->gadget);
2837 spin_lock(&dev->lock);
5f81f4b0
J		 2838 dev_dbg(&dev->pdev->dev, "resume %s\n",
2839 dev->driver->driver.name);
5be19a9d
XS		 2840 }
2841 }
2842
5f81f4b0 2843 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2844}
2845
2846
2847/* USB device controller interrupt handler */
2848static irqreturn_t langwell_irq(int irq, void *_dev)
2849{
2850 struct langwell_udc *dev = _dev;
2851 u32 usbsts,
2852 usbintr,
2853 irq_sts,
2854 portsc1;
2855
5f81f4b0 2856 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2857
2858 if (dev->stopped) {
5f81f4b0
J		 2859 dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n");
2860 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2861 return IRQ_NONE;
2862 }
2863
2864 spin_lock(&dev->lock);
2865
2866 /* USB status */
2867 usbsts = readl(&dev->op_regs->usbsts);
2868
2869 /* USB interrupt enable */
2870 usbintr = readl(&dev->op_regs->usbintr);
2871
2872 irq_sts = usbsts & usbintr;
5f81f4b0
J		 2873 dev_vdbg(&dev->pdev->dev,
2874 "usbsts = 0x%08x, usbintr = 0x%08x, irq_sts = 0x%08x\n",
5be19a9d
XS		 2875 usbsts, usbintr, irq_sts);
2876
2877 if (!irq_sts) {
5f81f4b0
J		 2878 dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n");
2879 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2880 spin_unlock(&dev->lock);
2881 return IRQ_NONE;
2882 }
2883
2884 /* Write-Clear interrupt status bits */
2885 writel(irq_sts, &dev->op_regs->usbsts);
2886
2887 /* resume from suspend */
2888 portsc1 = readl(&dev->op_regs->portsc1);
2889 if (dev->usb_state == USB_STATE_SUSPENDED)
2890 if (!(portsc1 & PORTS_SUSP))
2891 handle_bus_resume(dev);
2892
2893 /* USB interrupt */
2894 if (irq_sts & STS_UI) {
5f81f4b0 2895 dev_vdbg(&dev->pdev->dev, "USB interrupt\n");
5be19a9d
XS		 2896
2897 /* setup packet received from ep0 */
2898 if (readl(&dev->op_regs->endptsetupstat)
2899 & EP0SETUPSTAT_MASK) {
5f81f4b0
J		 2900 dev_vdbg(&dev->pdev->dev,
2901 "USB SETUP packet received interrupt\n");
5be19a9d
XS		 2902 /* setup tripwire semaphone */
2903 setup_tripwire(dev);
2904 handle_setup_packet(dev, &dev->local_setup_buff);
2905 }
2906
2907 /* USB transfer completion */
2908 if (readl(&dev->op_regs->endptcomplete)) {
5f81f4b0
J		 2909 dev_vdbg(&dev->pdev->dev,
2910 "USB transfer completion interrupt\n");
5be19a9d
XS		 2911 handle_trans_complete(dev);
2912 }
2913 }
2914
2915 /* SOF received interrupt (for ISO transfer) */
2916 if (irq_sts & STS_SRI) {
2917 /* FIXME */
5f81f4b0 2918 /* dev_vdbg(&dev->pdev->dev, "SOF received interrupt\n"); */
5be19a9d
XS		 2919 }
2920
2921 /* port change detect interrupt */
2922 if (irq_sts & STS_PCI) {
5f81f4b0 2923 dev_vdbg(&dev->pdev->dev, "port change detect interrupt\n");
5be19a9d
XS		 2924 handle_port_change(dev);
2925 }
2926
fb914ebf 2927 /* suspend interrupt */
5be19a9d 2928 if (irq_sts & STS_SLI) {
5f81f4b0 2929 dev_vdbg(&dev->pdev->dev, "suspend interrupt\n");
5be19a9d
XS		 2930 handle_bus_suspend(dev);
2931 }
2932
2933 /* USB reset interrupt */
2934 if (irq_sts & STS_URI) {
5f81f4b0 2935 dev_vdbg(&dev->pdev->dev, "USB reset interrupt\n");
5be19a9d
XS		 2936 handle_usb_reset(dev);
2937 }
2938
2939 /* USB error or system error interrupt */
2940 if (irq_sts & (STS_UEI | STS_SEI)) {
2941 /* FIXME */
5f81f4b0 2942 dev_warn(&dev->pdev->dev, "error IRQ, irq_sts: %x\n", irq_sts);
5be19a9d
XS		 2943 }
2944
2945 spin_unlock(&dev->lock);
2946
5f81f4b0 2947 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2948 return IRQ_HANDLED;
2949}
2950
2951
2952/*-------------------------------------------------------------------------*/
2953
2954/* release device structure */
2955static void gadget_release(struct device *_dev)
2956{
5bc639fc 2957 struct langwell_udc *dev = dev_get_drvdata(_dev);
5be19a9d 2958
5f81f4b0 2959 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2960
2961 complete(dev->done);
2962
5f81f4b0 2963 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2964 kfree(dev);
2965}
2966
2967
912c93d1
J		 2968/* enable SRAM caching if SRAM detected */
2969static void sram_init(struct langwell_udc *dev)
2970{
2971 struct pci_dev *pdev = dev->pdev;
2972
2973 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
2974
2975 dev->sram_addr = pci_resource_start(pdev, 1);
2976 dev->sram_size = pci_resource_len(pdev, 1);
2977 dev_info(&dev->pdev->dev, "Found private SRAM at %x size:%x\n",
2978 dev->sram_addr, dev->sram_size);
2979 dev->got_sram = 1;
2980
2981 if (pci_request_region(pdev, 1, kobject_name(&pdev->dev.kobj))) {
2982 dev_warn(&dev->pdev->dev, "SRAM request failed\n");
2983 dev->got_sram = 0;
2984 } else if (!dma_declare_coherent_memory(&pdev->dev, dev->sram_addr,
2985 dev->sram_addr, dev->sram_size, DMA_MEMORY_MAP)) {
2986 dev_warn(&dev->pdev->dev, "SRAM DMA declare failed\n");
2987 pci_release_region(pdev, 1);
2988 dev->got_sram = 0;
2989 }
2990
2991 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2992}
2993
2994
2995/* release SRAM caching */
2996static void sram_deinit(struct langwell_udc *dev)
2997{
2998 struct pci_dev *pdev = dev->pdev;
2999
3000 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
3001
3002 dma_release_declared_memory(&pdev->dev);
3003 pci_release_region(pdev, 1);
3004
3005 dev->got_sram = 0;
3006
3007 dev_info(&dev->pdev->dev, "release SRAM caching\n");
3008 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
3009}
3010
3011
5be19a9d
XS		 3012/* tear down the binding between this driver and the pci device */
3013static void langwell_udc_remove(struct pci_dev *pdev)
3014{
5bc639fc 3015 struct langwell_udc *dev = pci_get_drvdata(pdev);
5be19a9d
XS		 3016
3017 DECLARE_COMPLETION(done);
3018
3019 BUG_ON(dev->driver);
5f81f4b0 3020 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 3021
3022 dev->done = &done;
3023
912c93d1
J		 3024#ifndef OTG_TRANSCEIVER
3025 /* free dTD dma_pool and dQH */
5be19a9d
XS		 3026 if (dev->dtd_pool)
3027 dma_pool_destroy(dev->dtd_pool);
3028
912c93d1
J		 3029 if (dev->ep_dqh)
3030 dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
3031 dev->ep_dqh, dev->ep_dqh_dma);
3032
3033 /* release SRAM caching */
3034 if (dev->has_sram && dev->got_sram)
3035 sram_deinit(dev);
3036#endif
3037
5be19a9d
XS		 3038 if (dev->status_req) {
3039 kfree(dev->status_req->req.buf);
3040 kfree(dev->status_req);
3041 }
3042
5be19a9d
XS		 3043 kfree(dev->ep);
3044
48e34d0f 3045 /* disable IRQ handler */
5be19a9d
XS		 3046 if (dev->got_irq)
3047 free_irq(pdev->irq, dev);
3048
3049#ifndef OTG_TRANSCEIVER
3050 if (dev->cap_regs)
3051 iounmap(dev->cap_regs);
3052
3053 if (dev->region)
3054 release_mem_region(pci_resource_start(pdev, 0),
3055 pci_resource_len(pdev, 0));
3056
3057 if (dev->enabled)
3058 pci_disable_device(pdev);
3059#else
3060 if (dev->transceiver) {
3061 otg_put_transceiver(dev->transceiver);
3062 dev->transceiver = NULL;
3063 dev->lotg = NULL;
3064 }
3065#endif
3066
3067 dev->cap_regs = NULL;
3068
5f81f4b0
J		 3069 dev_info(&dev->pdev->dev, "unbind\n");
3070 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3071
3072 device_unregister(&dev->gadget.dev);
3073 device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
3211cbc2 3074 device_remove_file(&pdev->dev, &dev_attr_remote_wakeup);
5be19a9d
XS		 3075
3076#ifndef OTG_TRANSCEIVER
3077 pci_set_drvdata(pdev, NULL);
3078#endif
3079
3080 /* free dev, wait for the release() finished */
3081 wait_for_completion(&done);
5be19a9d
XS		 3082}
3083
3084
3085/*
3086 * wrap this driver around the specified device, but
3087 * don't respond over USB until a gadget driver binds to us.
3088 */
3089static int langwell_udc_probe(struct pci_dev *pdev,
3090 const struct pci_device_id *id)
3091{
3092 struct langwell_udc *dev;
3093#ifndef OTG_TRANSCEIVER
3094 unsigned long resource, len;
3095#endif
3096 void __iomem *base = NULL;
3097 size_t size;
3098 int retval;
3099
5be19a9d
XS		 3100 /* alloc, and start init */
3101 dev = kzalloc(sizeof *dev, GFP_KERNEL);
3102 if (dev == NULL) {
3103 retval = -ENOMEM;
3104 goto error;
3105 }
3106
3107 /* initialize device spinlock */
3108 spin_lock_init(&dev->lock);
3109
3110 dev->pdev = pdev;
5f81f4b0 3111 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 3112
3113#ifdef OTG_TRANSCEIVER
3114 /* PCI device is already enabled by otg_transceiver driver */
3115 dev->enabled = 1;
3116
3117 /* mem region and register base */
3118 dev->region = 1;
3119 dev->transceiver = otg_get_transceiver();
3120 dev->lotg = otg_to_langwell(dev->transceiver);
3121 base = dev->lotg->regs;
3122#else
3123 pci_set_drvdata(pdev, dev);
3124
3125 /* now all the pci goodies ... */
3126 if (pci_enable_device(pdev) < 0) {
3127 retval = -ENODEV;
3128 goto error;
3129 }
3130 dev->enabled = 1;
3131
3132 /* control register: BAR 0 */
3133 resource = pci_resource_start(pdev, 0);
3134 len = pci_resource_len(pdev, 0);
3135 if (!request_mem_region(resource, len, driver_name)) {
5f81f4b0 3136 dev_err(&dev->pdev->dev, "controller already in use\n");
5be19a9d
XS		 3137 retval = -EBUSY;
3138 goto error;
3139 }
3140 dev->region = 1;
3141
3142 base = ioremap_nocache(resource, len);
3143#endif
3144 if (base == NULL) {
5f81f4b0 3145 dev_err(&dev->pdev->dev, "can't map memory\n");
5be19a9d
XS		 3146 retval = -EFAULT;
3147 goto error;
3148 }
3149
3150 dev->cap_regs = (struct langwell_cap_regs __iomem *) base;
5f81f4b0 3151 dev_vdbg(&dev->pdev->dev, "dev->cap_regs: %p\n", dev->cap_regs);
5be19a9d
XS		 3152 dev->op_regs = (struct langwell_op_regs __iomem *)
3153 (base + OP_REG_OFFSET);
5f81f4b0 3154 dev_vdbg(&dev->pdev->dev, "dev->op_regs: %p\n", dev->op_regs);
5be19a9d
XS		 3155
3156 /* irq setup after old hardware is cleaned up */
3157 if (!pdev->irq) {
5f81f4b0 3158 dev_err(&dev->pdev->dev, "No IRQ. Check PCI setup!\n");
5be19a9d
XS		 3159 retval = -ENODEV;
3160 goto error;
3161 }
3162
912c93d1
J		 3163 dev->has_sram = 1;
3164 dev->got_sram = 0;
3165 dev_vdbg(&dev->pdev->dev, "dev->has_sram: %d\n", dev->has_sram);
3166
5be19a9d 3167#ifndef OTG_TRANSCEIVER
912c93d1
J		 3168 /* enable SRAM caching if detected */
3169 if (dev->has_sram && !dev->got_sram)
3170 sram_init(dev);
3171
5f81f4b0
J		 3172 dev_info(&dev->pdev->dev,
3173 "irq %d, io mem: 0x%08lx, len: 0x%08lx, pci mem 0x%p\n",
5be19a9d
XS		 3174 pdev->irq, resource, len, base);
3175 /* enables bus-mastering for device dev */
3176 pci_set_master(pdev);
3177
3178 if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
3179 driver_name, dev) != 0) {
5f81f4b0
J		 3180 dev_err(&dev->pdev->dev,
3181 "request interrupt %d failed\n", pdev->irq);
5be19a9d
XS		 3182 retval = -EBUSY;
3183 goto error;
3184 }
3185 dev->got_irq = 1;
3186#endif
3187
3188 /* set stopped bit */
3189 dev->stopped = 1;
3190
3191 /* capabilities and endpoint number */
3192 dev->lpm = (readl(&dev->cap_regs->hccparams) & HCC_LEN) ? 1 : 0;
3193 dev->dciversion = readw(&dev->cap_regs->dciversion);
3194 dev->devcap = (readl(&dev->cap_regs->dccparams) & DEVCAP) ? 1 : 0;
5f81f4b0
J		 3195 dev_vdbg(&dev->pdev->dev, "dev->lpm: %d\n", dev->lpm);
3196 dev_vdbg(&dev->pdev->dev, "dev->dciversion: 0x%04x\n",
3197 dev->dciversion);
3198 dev_vdbg(&dev->pdev->dev, "dccparams: 0x%08x\n",
3199 readl(&dev->cap_regs->dccparams));
3200 dev_vdbg(&dev->pdev->dev, "dev->devcap: %d\n", dev->devcap);
5be19a9d 3201 if (!dev->devcap) {
5f81f4b0 3202 dev_err(&dev->pdev->dev, "can't support device mode\n");
5be19a9d
XS		 3203 retval = -ENODEV;
3204 goto error;
3205 }
3206
3207 /* a pair of endpoints (out/in) for each address */
3208 dev->ep_max = DEN(readl(&dev->cap_regs->dccparams)) * 2;
5f81f4b0 3209 dev_vdbg(&dev->pdev->dev, "dev->ep_max: %d\n", dev->ep_max);
5be19a9d
XS		 3210
3211 /* allocate endpoints memory */
3212 dev->ep = kzalloc(sizeof(struct langwell_ep) * dev->ep_max,
3213 GFP_KERNEL);
3214 if (!dev->ep) {
5f81f4b0 3215 dev_err(&dev->pdev->dev, "allocate endpoints memory failed\n");
5be19a9d
XS		 3216 retval = -ENOMEM;
3217 goto error;
3218 }
3219
3220 /* allocate device dQH memory */
3221 size = dev->ep_max * sizeof(struct langwell_dqh);
b9af9ea4 3222 dev_vdbg(&dev->pdev->dev, "orig size = %zd\n", size);
5be19a9d
XS		 3223 if (size < DQH_ALIGNMENT)
3224 size = DQH_ALIGNMENT;
3225 else if ((size % DQH_ALIGNMENT) != 0) {
3226 size += DQH_ALIGNMENT + 1;
3227 size &= ~(DQH_ALIGNMENT - 1);
3228 }
3229 dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
3230 &dev->ep_dqh_dma, GFP_KERNEL);
3231 if (!dev->ep_dqh) {
5f81f4b0 3232 dev_err(&dev->pdev->dev, "allocate dQH memory failed\n");
5be19a9d
XS		 3233 retval = -ENOMEM;
3234 goto error;
3235 }
3236 dev->ep_dqh_size = size;
b9af9ea4 3237 dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %zd\n", dev->ep_dqh_size);
5be19a9d
XS		 3238
3239 /* initialize ep0 status request structure */
3240 dev->status_req = kzalloc(sizeof(struct langwell_request), GFP_KERNEL);
3241 if (!dev->status_req) {
5f81f4b0
J		 3242 dev_err(&dev->pdev->dev,
3243 "allocate status_req memory failed\n");
5be19a9d
XS		 3244 retval = -ENOMEM;
3245 goto error;
3246 }
3247 INIT_LIST_HEAD(&dev->status_req->queue);
3248
3249 /* allocate a small amount of memory to get valid address */
3250 dev->status_req->req.buf = kmalloc(8, GFP_KERNEL);
3251 dev->status_req->req.dma = virt_to_phys(dev->status_req->req.buf);
3252
3253 dev->resume_state = USB_STATE_NOTATTACHED;
3254 dev->usb_state = USB_STATE_POWERED;
3255 dev->ep0_dir = USB_DIR_OUT;
3211cbc2
J		 3256
3257 /* remote wakeup reset to 0 when the device is reset */
3258 dev->remote_wakeup = 0;
3259 dev->dev_status = 1 << USB_DEVICE_SELF_POWERED;
5be19a9d
XS		 3260
3261#ifndef OTG_TRANSCEIVER
3262 /* reset device controller */
3263 langwell_udc_reset(dev);
3264#endif
3265
3266 /* initialize gadget structure */
3267 dev->gadget.ops = &langwell_ops; /* usb_gadget_ops */
3268 dev->gadget.ep0 = &dev->ep[0].ep; /* gadget ep0 */
3269 INIT_LIST_HEAD(&dev->gadget.ep_list); /* ep_list */
3270 dev->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
d327ab5b 3271 dev->gadget.max_speed = USB_SPEED_HIGH; /* support dual speed */
5be19a9d
XS		 3272#ifdef OTG_TRANSCEIVER
3273 dev->gadget.is_otg = 1; /* support otg mode */
3274#endif
3275
3276 /* the "gadget" abstracts/virtualizes the controller */
3277 dev_set_name(&dev->gadget.dev, "gadget");
3278 dev->gadget.dev.parent = &pdev->dev;
3279 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
3280 dev->gadget.dev.release = gadget_release;
3281 dev->gadget.name = driver_name; /* gadget name */
3282
3283 /* controller endpoints reinit */
3284 eps_reinit(dev);
3285
3286#ifndef OTG_TRANSCEIVER
3287 /* reset ep0 dQH and endptctrl */
3288 ep0_reset(dev);
3289#endif
3290
3291 /* create dTD dma_pool resource */
3292 dev->dtd_pool = dma_pool_create("langwell_dtd",
3293 &dev->pdev->dev,
3294 sizeof(struct langwell_dtd),
3295 DTD_ALIGNMENT,
3296 DMA_BOUNDARY);
3297
3298 if (!dev->dtd_pool) {
3299 retval = -ENOMEM;
3300 goto error;
3301 }
3302
3303 /* done */
5f81f4b0
J		 3304 dev_info(&dev->pdev->dev, "%s\n", driver_desc);
3305 dev_info(&dev->pdev->dev, "irq %d, pci mem %p\n", pdev->irq, base);
3306 dev_info(&dev->pdev->dev, "Driver version: " DRIVER_VERSION "\n");
3307 dev_info(&dev->pdev->dev, "Support (max) %d endpoints\n", dev->ep_max);
3308 dev_info(&dev->pdev->dev, "Device interface version: 0x%04x\n",
3309 dev->dciversion);
3310 dev_info(&dev->pdev->dev, "Controller mode: %s\n",
3311 dev->devcap ? "Device" : "Host");
3312 dev_info(&dev->pdev->dev, "Support USB LPM: %s\n",
3313 dev->lpm ? "Yes" : "No");
3314
3315 dev_vdbg(&dev->pdev->dev,
3316 "After langwell_udc_probe(), print all registers:\n");
5be19a9d 3317 print_all_registers(dev);
5be19a9d 3318
5be19a9d
XS		 3319 retval = device_register(&dev->gadget.dev);
3320 if (retval)
3321 goto error;
3322
0f91349b
SAS		 3323 retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
3324 if (retval)
3325 goto error;
3326
5be19a9d
XS		 3327 retval = device_create_file(&pdev->dev, &dev_attr_langwell_udc);
3328 if (retval)
3329 goto error;
3330
3211cbc2
J		 3331 retval = device_create_file(&pdev->dev, &dev_attr_remote_wakeup);
3332 if (retval)
3333 goto error_attr1;
3334
5f81f4b0 3335 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3336 return 0;
3337
3211cbc2
J		 3338error_attr1:
3339 device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
5be19a9d
XS		 3340error:
3341 if (dev) {
5f81f4b0 3342 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3343 langwell_udc_remove(pdev);
3344 }
3345
3346 return retval;
3347}
3348
3349
3350/* device controller suspend */
3351static int langwell_udc_suspend(struct pci_dev *pdev, pm_message_t state)
3352{
5bc639fc 3353 struct langwell_udc *dev = pci_get_drvdata(pdev);
5be19a9d 3354
5f81f4b0 3355 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d 3356
0f91349b 3357 usb_del_gadget_udc(&dev->gadget);
5be19a9d
XS		 3358 /* disable interrupt and set controller to stop state */
3359 langwell_udc_stop(dev);
3360
48e34d0f 3361 /* disable IRQ handler */
5be19a9d
XS		 3362 if (dev->got_irq)
3363 free_irq(pdev->irq, dev);
3364 dev->got_irq = 0;
3365
5be19a9d
XS		 3366 /* save PCI state */
3367 pci_save_state(pdev);
3368
cf7d3c8e
PS		 3369 spin_lock_irq(&dev->lock);
3370 /* stop all usb activities */
3371 stop_activity(dev, dev->driver);
3372 spin_unlock_irq(&dev->lock);
3373
912c93d1
J		 3374 /* free dTD dma_pool and dQH */
3375 if (dev->dtd_pool)
3376 dma_pool_destroy(dev->dtd_pool);
3377
3378 if (dev->ep_dqh)
3379 dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
3380 dev->ep_dqh, dev->ep_dqh_dma);
3381
3382 /* release SRAM caching */
3383 if (dev->has_sram && dev->got_sram)
3384 sram_deinit(dev);
3385
5be19a9d
XS		 3386 /* set device power state */
3387 pci_set_power_state(pdev, PCI_D3hot);
3388
3389 /* enter PHY low power suspend */
513b91b6
J		 3390 if (dev->pdev->device != 0x0829)
3391 langwell_phy_low_power(dev, 1);
5be19a9d 3392
5f81f4b0 3393 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3394 return 0;
3395}
3396
3397
3398/* device controller resume */
3399static int langwell_udc_resume(struct pci_dev *pdev)
3400{
5bc639fc 3401 struct langwell_udc *dev = pci_get_drvdata(pdev);
912c93d1 3402 size_t size;
5be19a9d 3403
5f81f4b0 3404 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 3405
3406 /* exit PHY low power suspend */
513b91b6
J		 3407 if (dev->pdev->device != 0x0829)
3408 langwell_phy_low_power(dev, 0);
5be19a9d
XS		 3409
3410 /* set device D0 power state */
3411 pci_set_power_state(pdev, PCI_D0);
3412
912c93d1
J		 3413 /* enable SRAM caching if detected */
3414 if (dev->has_sram && !dev->got_sram)
3415 sram_init(dev);
3416
3417 /* allocate device dQH memory */
3418 size = dev->ep_max * sizeof(struct langwell_dqh);
b9af9ea4 3419 dev_vdbg(&dev->pdev->dev, "orig size = %zd\n", size);
912c93d1
J		 3420 if (size < DQH_ALIGNMENT)
3421 size = DQH_ALIGNMENT;
3422 else if ((size % DQH_ALIGNMENT) != 0) {
3423 size += DQH_ALIGNMENT + 1;
3424 size &= ~(DQH_ALIGNMENT - 1);
3425 }
3426 dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
3427 &dev->ep_dqh_dma, GFP_KERNEL);
3428 if (!dev->ep_dqh) {
3429 dev_err(&dev->pdev->dev, "allocate dQH memory failed\n");
3430 return -ENOMEM;
3431 }
3432 dev->ep_dqh_size = size;
b9af9ea4 3433 dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %zd\n", dev->ep_dqh_size);
912c93d1
J		 3434
3435 /* create dTD dma_pool resource */
3436 dev->dtd_pool = dma_pool_create("langwell_dtd",
3437 &dev->pdev->dev,
3438 sizeof(struct langwell_dtd),
3439 DTD_ALIGNMENT,
3440 DMA_BOUNDARY);
3441
3442 if (!dev->dtd_pool)
3443 return -ENOMEM;
3444
5be19a9d
XS		 3445 /* restore PCI state */
3446 pci_restore_state(pdev);
3447
3448 /* enable IRQ handler */
5f81f4b0
J		 3449 if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
3450 driver_name, dev) != 0) {
3451 dev_err(&dev->pdev->dev, "request interrupt %d failed\n",
3452 pdev->irq);
3453 return -EBUSY;
5be19a9d
XS		 3454 }
3455 dev->got_irq = 1;
3456
3457 /* reset and start controller to run state */
3458 if (dev->stopped) {
3459 /* reset device controller */
3460 langwell_udc_reset(dev);
3461
3462 /* reset ep0 dQH and endptctrl */
3463 ep0_reset(dev);
3464
3465 /* start device if gadget is loaded */
3466 if (dev->driver)
3467 langwell_udc_start(dev);
3468 }
3469
3470 /* reset USB status */
3471 dev->usb_state = USB_STATE_ATTACHED;
3472 dev->ep0_state = WAIT_FOR_SETUP;
3473 dev->ep0_dir = USB_DIR_OUT;
3474
5f81f4b0 3475 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3476 return 0;
3477}
3478
3479
3480/* pci driver shutdown */
3481static void langwell_udc_shutdown(struct pci_dev *pdev)
3482{
5bc639fc 3483 struct langwell_udc *dev = pci_get_drvdata(pdev);
5be19a9d
XS		 3484 u32 usbmode;
3485
5f81f4b0 3486 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 3487
3488 /* reset controller mode to IDLE */
3489 usbmode = readl(&dev->op_regs->usbmode);
5f81f4b0 3490 dev_dbg(&dev->pdev->dev, "usbmode = 0x%08x\n", usbmode);
5be19a9d
XS		 3491 usbmode &= (~3 | MODE_IDLE);
3492 writel(usbmode, &dev->op_regs->usbmode);
3493
5f81f4b0 3494 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3495}
3496
3497/*-------------------------------------------------------------------------*/
3498
3499static const struct pci_device_id pci_ids[] = { {
3500 .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
3501 .class_mask = ~0,
3502 .vendor = 0x8086,
3503 .device = 0x0811,
3504 .subvendor = PCI_ANY_ID,
3505 .subdevice = PCI_ANY_ID,
3506}, { /* end: all zeroes */ }
3507};
3508
5be19a9d
XS		 3509MODULE_DEVICE_TABLE(pci, pci_ids);
3510
3511
3512static struct pci_driver langwell_pci_driver = {
3513 .name = (char *) driver_name,
3514 .id_table = pci_ids,
3515
3516 .probe = langwell_udc_probe,
3517 .remove = langwell_udc_remove,
3518
3519 /* device controller suspend/resume */
3520 .suspend = langwell_udc_suspend,
3521 .resume = langwell_udc_resume,
3522
3523 .shutdown = langwell_udc_shutdown,
3524};
3525
3526
5be19a9d
XS		 3527static int __init init(void)
3528{
3529#ifdef OTG_TRANSCEIVER
3530 return langwell_register_peripheral(&langwell_pci_driver);
3531#else
3532 return pci_register_driver(&langwell_pci_driver);
3533#endif
3534}
3535module_init(init);
3536
3537
3538static void __exit cleanup(void)
3539{
3540#ifdef OTG_TRANSCEIVER
3541 return langwell_unregister_peripheral(&langwell_pci_driver);
3542#else
3543 pci_unregister_driver(&langwell_pci_driver);
3544#endif
3545}
3546module_exit(cleanup);
3547
5f81f4b0
J		 3548
3549MODULE_DESCRIPTION(DRIVER_DESC);
3550MODULE_AUTHOR("Xiaochen Shen <xiaochen.shen@intel.com>");
3551MODULE_VERSION(DRIVER_VERSION);
3552MODULE_LICENSE("GPL");
3553
Linux 6.x block layer and io_uring tree(s)