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usb: gadget: Clear usb_endpoint_descriptor inside the struct usb_ep on disable
[linux-2.6-block.git] / drivers / usb / gadget / fsl_udc_core.c
CommitLineData
b504882d 1/*
ea437f39
RM		 2 * Copyright (C) 2004-2007,2011 Freescale Semiconductor, Inc.
3 * All rights reserved.
b504882d
LY		 4 *
5 * Author: Li Yang <leoli@freescale.com>
6 * Jiang Bo <tanya.jiang@freescale.com>
7 *
8 * Description:
9 * Freescale high-speed USB SOC DR module device controller driver.
2ea6698d 10 * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
b504882d
LY		 11 * The driver is previously named as mpc_udc. Based on bare board
12 * code from Dave Liu and Shlomi Gridish.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 */
19
20#undef VERBOSE
21
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/ioport.h>
25#include <linux/types.h>
26#include <linux/errno.h>
b504882d
LY		 27#include <linux/slab.h>
28#include <linux/init.h>
b504882d
LY		 29#include <linux/list.h>
30#include <linux/interrupt.h>
31#include <linux/proc_fs.h>
32#include <linux/mm.h>
33#include <linux/moduleparam.h>
34#include <linux/device.h>
35#include <linux/usb/ch9.h>
9454a57a 36#include <linux/usb/gadget.h>
b504882d
LY		 37#include <linux/usb/otg.h>
38#include <linux/dma-mapping.h>
39#include <linux/platform_device.h>
40#include <linux/fsl_devices.h>
41#include <linux/dmapool.h>
54e4026b 42#include <linux/delay.h>
b504882d
LY		 43
44#include <asm/byteorder.h>
45#include <asm/io.h>
b504882d
LY		 46#include <asm/system.h>
47#include <asm/unaligned.h>
48#include <asm/dma.h>
b504882d
LY		 49
50#include "fsl_usb2_udc.h"
51
52#define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
53#define DRIVER_AUTHOR "Li Yang/Jiang Bo"
54#define DRIVER_VERSION "Apr 20, 2007"
55
56#define DMA_ADDR_INVALID (~(dma_addr_t)0)
57
58static const char driver_name[] = "fsl-usb2-udc";
59static const char driver_desc[] = DRIVER_DESC;
60
7483cff8 61static struct usb_dr_device *dr_regs;
54e4026b 62#ifndef CONFIG_ARCH_MXC
7483cff8 63static struct usb_sys_interface *usb_sys_regs;
54e4026b 64#endif
b504882d
LY		 65
66/* it is initialized in probe() */
67static struct fsl_udc *udc_controller = NULL;
68
69static const struct usb_endpoint_descriptor
70fsl_ep0_desc = {
71 .bLength = USB_DT_ENDPOINT_SIZE,
72 .bDescriptorType = USB_DT_ENDPOINT,
73 .bEndpointAddress = 0,
74 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
75 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
76};
77
b504882d
LY		 78static void fsl_ep_fifo_flush(struct usb_ep *_ep);
79
80#ifdef CONFIG_PPC32
09ba0def
AG		 81/*
82 * On some SoCs, the USB controller registers can be big or little endian,
83 * depending on the version of the chip. In order to be able to run the
84 * same kernel binary on 2 different versions of an SoC, the BE/LE decision
85 * must be made at run time. _fsl_readl and fsl_writel are pointers to the
86 * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
87 * call through those pointers. Platform code for SoCs that have BE USB
88 * registers should set pdata->big_endian_mmio flag.
89 *
90 * This also applies to controller-to-cpu accessors for the USB descriptors,
91 * since their endianness is also SoC dependant. Platform code for SoCs that
92 * have BE USB descriptors should set pdata->big_endian_desc flag.
93 */
94static u32 _fsl_readl_be(const unsigned __iomem *p)
95{
96 return in_be32(p);
97}
98
99static u32 _fsl_readl_le(const unsigned __iomem *p)
100{
101 return in_le32(p);
102}
103
104static void _fsl_writel_be(u32 v, unsigned __iomem *p)
105{
106 out_be32(p, v);
107}
108
109static void _fsl_writel_le(u32 v, unsigned __iomem *p)
110{
111 out_le32(p, v);
112}
113
114static u32 (*_fsl_readl)(const unsigned __iomem *p);
115static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
116
117#define fsl_readl(p) (*_fsl_readl)((p))
118#define fsl_writel(v, p) (*_fsl_writel)((v), (p))
119
3140d5b2
AG		 120static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
121{
122 if (pdata->big_endian_mmio) {
123 _fsl_readl = _fsl_readl_be;
124 _fsl_writel = _fsl_writel_be;
125 } else {
126 _fsl_readl = _fsl_readl_le;
127 _fsl_writel = _fsl_writel_le;
128 }
129}
130
09ba0def
AG		 131static inline u32 cpu_to_hc32(const u32 x)
132{
133 return udc_controller->pdata->big_endian_desc
134 ? (__force u32)cpu_to_be32(x)
135 : (__force u32)cpu_to_le32(x);
136}
137
138static inline u32 hc32_to_cpu(const u32 x)
139{
140 return udc_controller->pdata->big_endian_desc
141 ? be32_to_cpu((__force __be32)x)
142 : le32_to_cpu((__force __le32)x);
143}
144#else /* !CONFIG_PPC32 */
3140d5b2
AG		 145static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
146
b504882d 147#define fsl_readl(addr) readl(addr)
c93eebbe 148#define fsl_writel(val32, addr) writel(val32, addr)
09ba0def
AG		 149#define cpu_to_hc32(x) cpu_to_le32(x)
150#define hc32_to_cpu(x) le32_to_cpu(x)
151#endif /* CONFIG_PPC32 */
b504882d
LY		 152
153/********************************************************************
154 * Internal Used Function
155********************************************************************/
156/*-----------------------------------------------------------------
157 * done() - retire a request; caller blocked irqs
158 * @status : request status to be set, only works when
159 * request is still in progress.
160 *--------------------------------------------------------------*/
161static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
162{
163 struct fsl_udc *udc = NULL;
164 unsigned char stopped = ep->stopped;
165 struct ep_td_struct *curr_td, *next_td;
166 int j;
167
168 udc = (struct fsl_udc *)ep->udc;
169 /* Removed the req from fsl_ep->queue */
170 list_del_init(&req->queue);
171
172 /* req.status should be set as -EINPROGRESS in ep_queue() */
173 if (req->req.status == -EINPROGRESS)
174 req->req.status = status;
175 else
176 status = req->req.status;
177
178 /* Free dtd for the request */
179 next_td = req->head;
180 for (j = 0; j < req->dtd_count; j++) {
181 curr_td = next_td;
182 if (j != req->dtd_count - 1) {
183 next_td = curr_td->next_td_virt;
184 }
185 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
186 }
187
188 if (req->mapped) {
189 dma_unmap_single(ep->udc->gadget.dev.parent,
190 req->req.dma, req->req.length,
191 ep_is_in(ep)
192 ? DMA_TO_DEVICE
193 : DMA_FROM_DEVICE);
194 req->req.dma = DMA_ADDR_INVALID;
195 req->mapped = 0;
196 } else
197 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
198 req->req.dma, req->req.length,
199 ep_is_in(ep)
200 ? DMA_TO_DEVICE
201 : DMA_FROM_DEVICE);
202
203 if (status && (status != -ESHUTDOWN))
204 VDBG("complete %s req %p stat %d len %u/%u",
205 ep->ep.name, &req->req, status,
206 req->req.actual, req->req.length);
207
208 ep->stopped = 1;
209
210 spin_unlock(&ep->udc->lock);
211 /* complete() is from gadget layer,
212 * eg fsg->bulk_in_complete() */
213 if (req->req.complete)
214 req->req.complete(&ep->ep, &req->req);
215
216 spin_lock(&ep->udc->lock);
217 ep->stopped = stopped;
218}
219
220/*-----------------------------------------------------------------
221 * nuke(): delete all requests related to this ep
222 * called with spinlock held
223 *--------------------------------------------------------------*/
224static void nuke(struct fsl_ep *ep, int status)
225{
226 ep->stopped = 1;
227
228 /* Flush fifo */
229 fsl_ep_fifo_flush(&ep->ep);
230
231 /* Whether this eq has request linked */
232 while (!list_empty(&ep->queue)) {
233 struct fsl_req *req = NULL;
234
235 req = list_entry(ep->queue.next, struct fsl_req, queue);
236 done(ep, req, status);
237 }
238}
239
240/*------------------------------------------------------------------
241 Internal Hardware related function
242 ------------------------------------------------------------------*/
243
244static int dr_controller_setup(struct fsl_udc *udc)
245{
ea437f39
RM		 246 unsigned int tmp, portctrl, ep_num;
247 unsigned int max_no_of_ep;
54e4026b
GL		 248#ifndef CONFIG_ARCH_MXC
249 unsigned int ctrl;
250#endif
b504882d
LY		 251 unsigned long timeout;
252#define FSL_UDC_RESET_TIMEOUT 1000
253
54e4026b
GL		 254 /* Config PHY interface */
255 portctrl = fsl_readl(&dr_regs->portsc1);
256 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
257 switch (udc->phy_mode) {
258 case FSL_USB2_PHY_ULPI:
259 portctrl |= PORTSCX_PTS_ULPI;
260 break;
261 case FSL_USB2_PHY_UTMI_WIDE:
262 portctrl |= PORTSCX_PTW_16BIT;
263 /* fall through */
264 case FSL_USB2_PHY_UTMI:
265 portctrl |= PORTSCX_PTS_UTMI;
266 break;
267 case FSL_USB2_PHY_SERIAL:
268 portctrl |= PORTSCX_PTS_FSLS;
269 break;
270 default:
271 return -EINVAL;
272 }
273 fsl_writel(portctrl, &dr_regs->portsc1);
274
b504882d
LY		 275 /* Stop and reset the usb controller */
276 tmp = fsl_readl(&dr_regs->usbcmd);
277 tmp &= ~USB_CMD_RUN_STOP;
278 fsl_writel(tmp, &dr_regs->usbcmd);
279
280 tmp = fsl_readl(&dr_regs->usbcmd);
281 tmp |= USB_CMD_CTRL_RESET;
282 fsl_writel(tmp, &dr_regs->usbcmd);
283
284 /* Wait for reset to complete */
285 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
286 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
287 if (time_after(jiffies, timeout)) {
bf7409a2 288 ERR("udc reset timeout!\n");
b504882d
LY		 289 return -ETIMEDOUT;
290 }
291 cpu_relax();
292 }
293
294 /* Set the controller as device mode */
295 tmp = fsl_readl(&dr_regs->usbmode);
2ea6698d 296 tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
b504882d
LY		 297 tmp |= USB_MODE_CTRL_MODE_DEVICE;
298 /* Disable Setup Lockout */
299 tmp |= USB_MODE_SETUP_LOCK_OFF;
2ea6698d
AG		 300 if (udc->pdata->es)
301 tmp |= USB_MODE_ES;
b504882d
LY		 302 fsl_writel(tmp, &dr_regs->usbmode);
303
304 /* Clear the setup status */
305 fsl_writel(0, &dr_regs->usbsts);
306
307 tmp = udc->ep_qh_dma;
308 tmp &= USB_EP_LIST_ADDRESS_MASK;
309 fsl_writel(tmp, &dr_regs->endpointlistaddr);
310
311 VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
6ef65a7f 312 udc->ep_qh, (int)tmp,
b504882d
LY		 313 fsl_readl(&dr_regs->endpointlistaddr));
314
ea437f39
RM		 315 max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
316 for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
317 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
318 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
319 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
320 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
321 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
322 }
b504882d 323 /* Config control enable i/o output, cpu endian register */
54e4026b 324#ifndef CONFIG_ARCH_MXC
2ea6698d
AG		 325 if (udc->pdata->have_sysif_regs) {
326 ctrl = __raw_readl(&usb_sys_regs->control);
327 ctrl |= USB_CTRL_IOENB;
328 __raw_writel(ctrl, &usb_sys_regs->control);
329 }
54e4026b 330#endif
b504882d
LY		 331
332#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
333 /* Turn on cache snooping hardware, since some PowerPC platforms
334 * wholly rely on hardware to deal with cache coherent. */
335
2ea6698d
AG		 336 if (udc->pdata->have_sysif_regs) {
337 /* Setup Snooping for all the 4GB space */
338 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
339 __raw_writel(tmp, &usb_sys_regs->snoop1);
340 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
341 __raw_writel(tmp, &usb_sys_regs->snoop2);
342 }
b504882d
LY		 343#endif
344
345 return 0;
346}
347
348/* Enable DR irq and set controller to run state */
349static void dr_controller_run(struct fsl_udc *udc)
350{
351 u32 temp;
352
353 /* Enable DR irq reg */
354 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
355 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
356 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
357
358 fsl_writel(temp, &dr_regs->usbintr);
359
360 /* Clear stopped bit */
361 udc->stopped = 0;
362
363 /* Set the controller as device mode */
364 temp = fsl_readl(&dr_regs->usbmode);
365 temp |= USB_MODE_CTRL_MODE_DEVICE;
366 fsl_writel(temp, &dr_regs->usbmode);
367
368 /* Set controller to Run */
369 temp = fsl_readl(&dr_regs->usbcmd);
370 temp |= USB_CMD_RUN_STOP;
371 fsl_writel(temp, &dr_regs->usbcmd);
b504882d
LY		 372}
373
374static void dr_controller_stop(struct fsl_udc *udc)
375{
376 unsigned int tmp;
377
83722bc9
AG		 378 pr_debug("%s\n", __func__);
379
380 /* if we're in OTG mode, and the Host is currently using the port,
381 * stop now and don't rip the controller out from under the
382 * ehci driver
383 */
384 if (udc->gadget.is_otg) {
385 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
386 pr_debug("udc: Leaving early\n");
387 return;
388 }
389 }
390
b504882d
LY		 391 /* disable all INTR */
392 fsl_writel(0, &dr_regs->usbintr);
393
394 /* Set stopped bit for isr */
395 udc->stopped = 1;
396
397 /* disable IO output */
398/* usb_sys_regs->control = 0; */
399
400 /* set controller to Stop */
401 tmp = fsl_readl(&dr_regs->usbcmd);
402 tmp &= ~USB_CMD_RUN_STOP;
403 fsl_writel(tmp, &dr_regs->usbcmd);
b504882d
LY		 404}
405
9c94155e
WN		 406static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
407 unsigned char ep_type)
b504882d
LY		 408{
409 unsigned int tmp_epctrl = 0;
410
411 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
412 if (dir) {
413 if (ep_num)
414 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
415 tmp_epctrl |= EPCTRL_TX_ENABLE;
ea437f39 416 tmp_epctrl &= ~EPCTRL_TX_TYPE;
b504882d
LY		 417 tmp_epctrl |= ((unsigned int)(ep_type)
418 << EPCTRL_TX_EP_TYPE_SHIFT);
419 } else {
420 if (ep_num)
421 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
422 tmp_epctrl |= EPCTRL_RX_ENABLE;
ea437f39 423 tmp_epctrl &= ~EPCTRL_RX_TYPE;
b504882d
LY		 424 tmp_epctrl |= ((unsigned int)(ep_type)
425 << EPCTRL_RX_EP_TYPE_SHIFT);
426 }
427
428 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
429}
430
431static void
432dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
433{
434 u32 tmp_epctrl = 0;
435
436 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
437
438 if (value) {
439 /* set the stall bit */
440 if (dir)
441 tmp_epctrl |= EPCTRL_TX_EP_STALL;
442 else
443 tmp_epctrl |= EPCTRL_RX_EP_STALL;
444 } else {
445 /* clear the stall bit and reset data toggle */
446 if (dir) {
447 tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
448 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
449 } else {
450 tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
451 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
452 }
453 }
454 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
455}
456
457/* Get stall status of a specific ep
458 Return: 0: not stalled; 1:stalled */
459static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
460{
461 u32 epctrl;
462
463 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
464 if (dir)
465 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
466 else
467 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
468}
469
470/********************************************************************
471 Internal Structure Build up functions
472********************************************************************/
473
474/*------------------------------------------------------------------
475* struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
476 * @zlt: Zero Length Termination Select (1: disable; 0: enable)
477 * @mult: Mult field
478 ------------------------------------------------------------------*/
479static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
480 unsigned char dir, unsigned char ep_type,
481 unsigned int max_pkt_len,
482 unsigned int zlt, unsigned char mult)
483{
484 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
485 unsigned int tmp = 0;
486
487 /* set the Endpoint Capabilites in QH */
488 switch (ep_type) {
489 case USB_ENDPOINT_XFER_CONTROL:
490 /* Interrupt On Setup (IOS). for control ep */
491 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
492 | EP_QUEUE_HEAD_IOS;
493 break;
494 case USB_ENDPOINT_XFER_ISOC:
495 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
496 | (mult << EP_QUEUE_HEAD_MULT_POS);
497 break;
498 case USB_ENDPOINT_XFER_BULK:
499 case USB_ENDPOINT_XFER_INT:
500 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
501 break;
502 default:
503 VDBG("error ep type is %d", ep_type);
504 return;
505 }
506 if (zlt)
507 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
9a6e184c 508
09ba0def 509 p_QH->max_pkt_length = cpu_to_hc32(tmp);
9a6e184c
LY		 510 p_QH->next_dtd_ptr = 1;
511 p_QH->size_ioc_int_sts = 0;
b504882d
LY		 512}
513
514/* Setup qh structure and ep register for ep0. */
515static void ep0_setup(struct fsl_udc *udc)
516{
517 /* the intialization of an ep includes: fields in QH, Regs,
518 * fsl_ep struct */
519 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
520 USB_MAX_CTRL_PAYLOAD, 0, 0);
521 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
522 USB_MAX_CTRL_PAYLOAD, 0, 0);
523 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
524 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
525
526 return;
527
528}
529
530/***********************************************************************
531 Endpoint Management Functions
532***********************************************************************/
533
534/*-------------------------------------------------------------------------
535 * when configurations are set, or when interface settings change
536 * for example the do_set_interface() in gadget layer,
537 * the driver will enable or disable the relevant endpoints
538 * ep0 doesn't use this routine. It is always enabled.
539-------------------------------------------------------------------------*/
540static int fsl_ep_enable(struct usb_ep *_ep,
541 const struct usb_endpoint_descriptor *desc)
542{
543 struct fsl_udc *udc = NULL;
544 struct fsl_ep *ep = NULL;
545 unsigned short max = 0;
546 unsigned char mult = 0, zlt;
547 int retval = -EINVAL;
548 unsigned long flags = 0;
549
550 ep = container_of(_ep, struct fsl_ep, ep);
551
552 /* catch various bogus parameters */
553 if (!_ep || !desc || ep->desc
554 || (desc->bDescriptorType != USB_DT_ENDPOINT))
555 return -EINVAL;
556
557 udc = ep->udc;
558
559 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
560 return -ESHUTDOWN;
561
29cc8897 562 max = usb_endpoint_maxp(desc);
b504882d 563
25985edc 564 /* Disable automatic zlp generation. Driver is responsible to indicate
b504882d
LY		 565 * explicitly through req->req.zero. This is needed to enable multi-td
566 * request. */
567 zlt = 1;
568
569 /* Assume the max packet size from gadget is always correct */
570 switch (desc->bmAttributes & 0x03) {
571 case USB_ENDPOINT_XFER_CONTROL:
572 case USB_ENDPOINT_XFER_BULK:
573 case USB_ENDPOINT_XFER_INT:
574 /* mult = 0. Execute N Transactions as demonstrated by
575 * the USB variable length packet protocol where N is
576 * computed using the Maximum Packet Length (dQH) and
577 * the Total Bytes field (dTD) */
578 mult = 0;
579 break;
580 case USB_ENDPOINT_XFER_ISOC:
581 /* Calculate transactions needed for high bandwidth iso */
582 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
88e3b59b 583 max = max & 0x7ff; /* bit 0~10 */
b504882d
LY		 584 /* 3 transactions at most */
585 if (mult > 3)
586 goto en_done;
587 break;
588 default:
589 goto en_done;
590 }
591
592 spin_lock_irqsave(&udc->lock, flags);
593 ep->ep.maxpacket = max;
594 ep->desc = desc;
595 ep->stopped = 0;
596
597 /* Controller related setup */
598 /* Init EPx Queue Head (Ep Capabilites field in QH
599 * according to max, zlt, mult) */
600 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
601 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
602 ? USB_SEND : USB_RECV),
603 (unsigned char) (desc->bmAttributes
604 & USB_ENDPOINT_XFERTYPE_MASK),
605 max, zlt, mult);
606
607 /* Init endpoint ctrl register */
608 dr_ep_setup((unsigned char) ep_index(ep),
609 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
610 ? USB_SEND : USB_RECV),
611 (unsigned char) (desc->bmAttributes
612 & USB_ENDPOINT_XFERTYPE_MASK));
613
614 spin_unlock_irqrestore(&udc->lock, flags);
615 retval = 0;
616
617 VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
618 ep->desc->bEndpointAddress & 0x0f,
619 (desc->bEndpointAddress & USB_DIR_IN)
620 ? "in" : "out", max);
621en_done:
622 return retval;
623}
624
625/*---------------------------------------------------------------------
626 * @ep : the ep being unconfigured. May not be ep0
627 * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
628*---------------------------------------------------------------------*/
629static int fsl_ep_disable(struct usb_ep *_ep)
630{
631 struct fsl_udc *udc = NULL;
632 struct fsl_ep *ep = NULL;
633 unsigned long flags = 0;
634 u32 epctrl;
635 int ep_num;
636
637 ep = container_of(_ep, struct fsl_ep, ep);
638 if (!_ep || !ep->desc) {
639 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
640 return -EINVAL;
641 }
642
643 /* disable ep on controller */
644 ep_num = ep_index(ep);
645 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
ea437f39
RM		 646 if (ep_is_in(ep)) {
647 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
648 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
649 } else {
650 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
651 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
652 }
b504882d
LY		 653 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
654
655 udc = (struct fsl_udc *)ep->udc;
656 spin_lock_irqsave(&udc->lock, flags);
657
658 /* nuke all pending requests (does flush) */
659 nuke(ep, -ESHUTDOWN);
660
7483cff8 661 ep->desc = NULL;
f9c56cdd 662 ep->ep.desc = NULL;
b504882d
LY		 663 ep->stopped = 1;
664 spin_unlock_irqrestore(&udc->lock, flags);
665
666 VDBG("disabled %s OK", _ep->name);
667 return 0;
668}
669
670/*---------------------------------------------------------------------
671 * allocate a request object used by this endpoint
672 * the main operation is to insert the req->queue to the eq->queue
673 * Returns the request, or null if one could not be allocated
674*---------------------------------------------------------------------*/
675static struct usb_request *
676fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
677{
678 struct fsl_req *req = NULL;
679
680 req = kzalloc(sizeof *req, gfp_flags);
681 if (!req)
682 return NULL;
683
684 req->req.dma = DMA_ADDR_INVALID;
685 INIT_LIST_HEAD(&req->queue);
686
687 return &req->req;
688}
689
690static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
691{
692 struct fsl_req *req = NULL;
693
694 req = container_of(_req, struct fsl_req, req);
695
696 if (_req)
697 kfree(req);
698}
699
6414e94c
LY		 700/* Actually add a dTD chain to an empty dQH and let go */
701static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
702{
703 struct ep_queue_head *qh = get_qh_by_ep(ep);
704
705 /* Write dQH next pointer and terminate bit to 0 */
706 qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
707 & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
708
709 /* Clear active and halt bit */
710 qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
711 | EP_QUEUE_HEAD_STATUS_HALT));
712
713 /* Ensure that updates to the QH will occur before priming. */
714 wmb();
715
716 /* Prime endpoint by writing correct bit to ENDPTPRIME */
717 fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
718 : (1 << (ep_index(ep))), &dr_regs->endpointprime);
719}
720
721/* Add dTD chain to the dQH of an EP */
224b5039 722static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
b504882d 723{
b504882d 724 u32 temp, bitmask, tmp_stat;
b504882d
LY		 725
726 /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
727 VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
728
729 bitmask = ep_is_in(ep)
730 ? (1 << (ep_index(ep) + 16))
731 : (1 << (ep_index(ep)));
732
733 /* check if the pipe is empty */
734 if (!(list_empty(&ep->queue))) {
735 /* Add td to the end */
736 struct fsl_req *lastreq;
737 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
738 lastreq->tail->next_td_ptr =
09ba0def 739 cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
b504882d
LY		 740 /* Read prime bit, if 1 goto done */
741 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
6414e94c 742 return;
b504882d
LY		 743
744 do {
745 /* Set ATDTW bit in USBCMD */
746 temp = fsl_readl(&dr_regs->usbcmd);
747 fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
748
749 /* Read correct status bit */
750 tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
751
752 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
753
754 /* Write ATDTW bit to 0 */
755 temp = fsl_readl(&dr_regs->usbcmd);
756 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
757
758 if (tmp_stat)
6414e94c 759 return;
b504882d
LY		 760 }
761
6414e94c 762 fsl_prime_ep(ep, req->head);
b504882d
LY		 763}
764
765/* Fill in the dTD structure
766 * @req: request that the transfer belongs to
767 * @length: return actually data length of the dTD
768 * @dma: return dma address of the dTD
769 * @is_last: return flag if it is the last dTD of the request
770 * return: pointer to the built dTD */
771static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
772 dma_addr_t *dma, int *is_last)
773{
774 u32 swap_temp;
775 struct ep_td_struct *dtd;
776
777 /* how big will this transfer be? */
778 *length = min(req->req.length - req->req.actual,
779 (unsigned)EP_MAX_LENGTH_TRANSFER);
780
781 dtd = dma_pool_alloc(udc_controller->td_pool, GFP_KERNEL, dma);
782 if (dtd == NULL)
783 return dtd;
784
785 dtd->td_dma = *dma;
786 /* Clear reserved field */
09ba0def 787 swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
b504882d 788 swap_temp &= ~DTD_RESERVED_FIELDS;
09ba0def 789 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
b504882d
LY		 790
791 /* Init all of buffer page pointers */
792 swap_temp = (u32) (req->req.dma + req->req.actual);
09ba0def
AG		 793 dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
794 dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
795 dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
796 dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
797 dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
b504882d
LY		 798
799 req->req.actual += *length;
800
801 /* zlp is needed if req->req.zero is set */
802 if (req->req.zero) {
803 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
804 *is_last = 1;
805 else
806 *is_last = 0;
807 } else if (req->req.length == req->req.actual)
808 *is_last = 1;
809 else
810 *is_last = 0;
811
812 if ((*is_last) == 0)
bf7409a2 813 VDBG("multi-dtd request!");
b504882d
LY		 814 /* Fill in the transfer size; set active bit */
815 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
816
817 /* Enable interrupt for the last dtd of a request */
818 if (*is_last && !req->req.no_interrupt)
819 swap_temp |= DTD_IOC;
820
09ba0def 821 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
b504882d
LY		 822
823 mb();
824
825 VDBG("length = %d address= 0x%x", *length, (int)*dma);
826
827 return dtd;
828}
829
830/* Generate dtd chain for a request */
831static int fsl_req_to_dtd(struct fsl_req *req)
832{
833 unsigned count;
834 int is_last;
835 int is_first =1;
836 struct ep_td_struct *last_dtd = NULL, *dtd;
837 dma_addr_t dma;
838
839 do {
840 dtd = fsl_build_dtd(req, &count, &dma, &is_last);
841 if (dtd == NULL)
842 return -ENOMEM;
843
844 if (is_first) {
845 is_first = 0;
846 req->head = dtd;
847 } else {
09ba0def 848 last_dtd->next_td_ptr = cpu_to_hc32(dma);
b504882d
LY		 849 last_dtd->next_td_virt = dtd;
850 }
851 last_dtd = dtd;
852
853 req->dtd_count++;
854 } while (!is_last);
855
09ba0def 856 dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
b504882d
LY		 857
858 req->tail = dtd;
859
860 return 0;
861}
862
863/* queues (submits) an I/O request to an endpoint */
864static int
865fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
866{
867 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
868 struct fsl_req *req = container_of(_req, struct fsl_req, req);
869 struct fsl_udc *udc;
870 unsigned long flags;
b504882d
LY		 871
872 /* catch various bogus parameters */
873 if (!_req || !req->req.complete || !req->req.buf
874 || !list_empty(&req->queue)) {
bf7409a2 875 VDBG("%s, bad params", __func__);
b504882d
LY		 876 return -EINVAL;
877 }
2336a986 878 if (unlikely(!_ep || !ep->desc)) {
bf7409a2 879 VDBG("%s, bad ep", __func__);
b504882d
LY		 880 return -EINVAL;
881 }
7c91d908 882 if (usb_endpoint_xfer_isoc(ep->desc)) {
b504882d
LY		 883 if (req->req.length > ep->ep.maxpacket)
884 return -EMSGSIZE;
b504882d
LY		 885 }
886
887 udc = ep->udc;
888 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
889 return -ESHUTDOWN;
890
891 req->ep = ep;
892
893 /* map virtual address to hardware */
894 if (req->req.dma == DMA_ADDR_INVALID) {
895 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
896 req->req.buf,
897 req->req.length, ep_is_in(ep)
898 ? DMA_TO_DEVICE
899 : DMA_FROM_DEVICE);
900 req->mapped = 1;
901 } else {
902 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
903 req->req.dma, req->req.length,
904 ep_is_in(ep)
905 ? DMA_TO_DEVICE
906 : DMA_FROM_DEVICE);
907 req->mapped = 0;
908 }
909
910 req->req.status = -EINPROGRESS;
911 req->req.actual = 0;
912 req->dtd_count = 0;
913
914 spin_lock_irqsave(&udc->lock, flags);
915
916 /* build dtds and push them to device queue */
917 if (!fsl_req_to_dtd(req)) {
918 fsl_queue_td(ep, req);
919 } else {
920 spin_unlock_irqrestore(&udc->lock, flags);
921 return -ENOMEM;
922 }
923
924 /* Update ep0 state */
925 if ((ep_index(ep) == 0))
926 udc->ep0_state = DATA_STATE_XMIT;
927
928 /* irq handler advances the queue */
929 if (req != NULL)
930 list_add_tail(&req->queue, &ep->queue);
931 spin_unlock_irqrestore(&udc->lock, flags);
932
933 return 0;
934}
935
936/* dequeues (cancels, unlinks) an I/O request from an endpoint */
937static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
938{
939 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
940 struct fsl_req *req;
941 unsigned long flags;
942 int ep_num, stopped, ret = 0;
943 u32 epctrl;
944
945 if (!_ep || !_req)
946 return -EINVAL;
947
948 spin_lock_irqsave(&ep->udc->lock, flags);
949 stopped = ep->stopped;
950
951 /* Stop the ep before we deal with the queue */
952 ep->stopped = 1;
953 ep_num = ep_index(ep);
954 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
955 if (ep_is_in(ep))
956 epctrl &= ~EPCTRL_TX_ENABLE;
957 else
958 epctrl &= ~EPCTRL_RX_ENABLE;
959 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
960
961 /* make sure it's actually queued on this endpoint */
962 list_for_each_entry(req, &ep->queue, queue) {
963 if (&req->req == _req)
964 break;
965 }
966 if (&req->req != _req) {
967 ret = -EINVAL;
968 goto out;
969 }
970
971 /* The request is in progress, or completed but not dequeued */
972 if (ep->queue.next == &req->queue) {
973 _req->status = -ECONNRESET;
974 fsl_ep_fifo_flush(_ep); /* flush current transfer */
975
976 /* The request isn't the last request in this ep queue */
977 if (req->queue.next != &ep->queue) {
b504882d
LY		 978 struct fsl_req *next_req;
979
b504882d
LY		 980 next_req = list_entry(req->queue.next, struct fsl_req,
981 queue);
982
6414e94c
LY		 983 /* prime with dTD of next request */
984 fsl_prime_ep(ep, next_req->head);
b504882d 985 }
6414e94c 986 /* The request hasn't been processed, patch up the TD chain */
b504882d
LY		 987 } else {
988 struct fsl_req *prev_req;
989
990 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
6414e94c 991 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
b504882d
LY		 992 }
993
994 done(ep, req, -ECONNRESET);
995
996 /* Enable EP */
997out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
998 if (ep_is_in(ep))
999 epctrl |= EPCTRL_TX_ENABLE;
1000 else
1001 epctrl |= EPCTRL_RX_ENABLE;
1002 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
1003 ep->stopped = stopped;
1004
1005 spin_unlock_irqrestore(&ep->udc->lock, flags);
1006 return ret;
1007}
1008
1009/*-------------------------------------------------------------------------*/
1010
1011/*-----------------------------------------------------------------
1012 * modify the endpoint halt feature
1013 * @ep: the non-isochronous endpoint being stalled
1014 * @value: 1--set halt 0--clear halt
1015 * Returns zero, or a negative error code.
1016*----------------------------------------------------------------*/
1017static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1018{
1019 struct fsl_ep *ep = NULL;
1020 unsigned long flags = 0;
1021 int status = -EOPNOTSUPP; /* operation not supported */
1022 unsigned char ep_dir = 0, ep_num = 0;
1023 struct fsl_udc *udc = NULL;
1024
1025 ep = container_of(_ep, struct fsl_ep, ep);
1026 udc = ep->udc;
1027 if (!_ep || !ep->desc) {
1028 status = -EINVAL;
1029 goto out;
1030 }
1031
7c91d908 1032 if (usb_endpoint_xfer_isoc(ep->desc)) {
b504882d
LY		 1033 status = -EOPNOTSUPP;
1034 goto out;
1035 }
1036
1037 /* Attempt to halt IN ep will fail if any transfer requests
1038 * are still queue */
1039 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1040 status = -EAGAIN;
1041 goto out;
1042 }
1043
1044 status = 0;
1045 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1046 ep_num = (unsigned char)(ep_index(ep));
1047 spin_lock_irqsave(&ep->udc->lock, flags);
1048 dr_ep_change_stall(ep_num, ep_dir, value);
1049 spin_unlock_irqrestore(&ep->udc->lock, flags);
1050
1051 if (ep_index(ep) == 0) {
1052 udc->ep0_state = WAIT_FOR_SETUP;
1053 udc->ep0_dir = 0;
1054 }
1055out:
1056 VDBG(" %s %s halt stat %d", ep->ep.name,
1057 value ? "set" : "clear", status);
1058
1059 return status;
1060}
1061
2ea6698d
AG		 1062static int fsl_ep_fifo_status(struct usb_ep *_ep)
1063{
1064 struct fsl_ep *ep;
1065 struct fsl_udc *udc;
1066 int size = 0;
1067 u32 bitmask;
6414e94c 1068 struct ep_queue_head *qh;
2ea6698d
AG		 1069
1070 ep = container_of(_ep, struct fsl_ep, ep);
1071 if (!_ep || (!ep->desc && ep_index(ep) != 0))
1072 return -ENODEV;
1073
1074 udc = (struct fsl_udc *)ep->udc;
1075
1076 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1077 return -ESHUTDOWN;
1078
6414e94c 1079 qh = get_qh_by_ep(ep);
2ea6698d
AG		 1080
1081 bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1082 (1 << (ep_index(ep)));
1083
1084 if (fsl_readl(&dr_regs->endptstatus) & bitmask)
6414e94c 1085 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
2ea6698d
AG		 1086 >> DTD_LENGTH_BIT_POS;
1087
1088 pr_debug("%s %u\n", __func__, size);
1089 return size;
1090}
1091
b504882d
LY		 1092static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1093{
1094 struct fsl_ep *ep;
1095 int ep_num, ep_dir;
1096 u32 bits;
1097 unsigned long timeout;
1098#define FSL_UDC_FLUSH_TIMEOUT 1000
1099
1100 if (!_ep) {
1101 return;
1102 } else {
1103 ep = container_of(_ep, struct fsl_ep, ep);
1104 if (!ep->desc)
1105 return;
1106 }
1107 ep_num = ep_index(ep);
1108 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1109
1110 if (ep_num == 0)
1111 bits = (1 << 16) | 1;
1112 else if (ep_dir == USB_SEND)
1113 bits = 1 << (16 + ep_num);
1114 else
1115 bits = 1 << ep_num;
1116
1117 timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1118 do {
1119 fsl_writel(bits, &dr_regs->endptflush);
1120
1121 /* Wait until flush complete */
1122 while (fsl_readl(&dr_regs->endptflush)) {
1123 if (time_after(jiffies, timeout)) {
1124 ERR("ep flush timeout\n");
1125 return;
1126 }
1127 cpu_relax();
1128 }
1129 /* See if we need to flush again */
1130 } while (fsl_readl(&dr_regs->endptstatus) & bits);
1131}
1132
1133static struct usb_ep_ops fsl_ep_ops = {
1134 .enable = fsl_ep_enable,
1135 .disable = fsl_ep_disable,
1136
1137 .alloc_request = fsl_alloc_request,
1138 .free_request = fsl_free_request,
1139
b504882d
LY		 1140 .queue = fsl_ep_queue,
1141 .dequeue = fsl_ep_dequeue,
1142
1143 .set_halt = fsl_ep_set_halt,
2ea6698d 1144 .fifo_status = fsl_ep_fifo_status,
b504882d
LY		 1145 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
1146};
1147
1148/*-------------------------------------------------------------------------
1149 Gadget Driver Layer Operations
1150-------------------------------------------------------------------------*/
1151
1152/*----------------------------------------------------------------------
1153 * Get the current frame number (from DR frame_index Reg )
1154 *----------------------------------------------------------------------*/
1155static int fsl_get_frame(struct usb_gadget *gadget)
1156{
1157 return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1158}
1159
1160/*-----------------------------------------------------------------------
1161 * Tries to wake up the host connected to this gadget
1162 -----------------------------------------------------------------------*/
1163static int fsl_wakeup(struct usb_gadget *gadget)
1164{
1165 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1166 u32 portsc;
1167
1168 /* Remote wakeup feature not enabled by host */
1169 if (!udc->remote_wakeup)
1170 return -ENOTSUPP;
1171
1172 portsc = fsl_readl(&dr_regs->portsc1);
1173 /* not suspended? */
1174 if (!(portsc & PORTSCX_PORT_SUSPEND))
1175 return 0;
1176 /* trigger force resume */
1177 portsc |= PORTSCX_PORT_FORCE_RESUME;
1178 fsl_writel(portsc, &dr_regs->portsc1);
1179 return 0;
1180}
1181
1182static int can_pullup(struct fsl_udc *udc)
1183{
1184 return udc->driver && udc->softconnect && udc->vbus_active;
1185}
1186
1187/* Notify controller that VBUS is powered, Called by whatever
1188 detects VBUS sessions */
1189static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1190{
1191 struct fsl_udc *udc;
1192 unsigned long flags;
1193
1194 udc = container_of(gadget, struct fsl_udc, gadget);
1195 spin_lock_irqsave(&udc->lock, flags);
bf7409a2 1196 VDBG("VBUS %s", is_active ? "on" : "off");
b504882d
LY		 1197 udc->vbus_active = (is_active != 0);
1198 if (can_pullup(udc))
1199 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1200 &dr_regs->usbcmd);
1201 else
1202 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1203 &dr_regs->usbcmd);
1204 spin_unlock_irqrestore(&udc->lock, flags);
1205 return 0;
1206}
1207
1208/* constrain controller's VBUS power usage
1209 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1210 * reporting how much power the device may consume. For example, this
1211 * could affect how quickly batteries are recharged.
1212 *
1213 * Returns zero on success, else negative errno.
1214 */
1215static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1216{
b504882d
LY		 1217 struct fsl_udc *udc;
1218
1219 udc = container_of(gadget, struct fsl_udc, gadget);
b504882d
LY		 1220 if (udc->transceiver)
1221 return otg_set_power(udc->transceiver, mA);
b504882d
LY		 1222 return -ENOTSUPP;
1223}
1224
1225/* Change Data+ pullup status
1226 * this func is used by usb_gadget_connect/disconnet
1227 */
1228static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1229{
1230 struct fsl_udc *udc;
1231
1232 udc = container_of(gadget, struct fsl_udc, gadget);
1233 udc->softconnect = (is_on != 0);
1234 if (can_pullup(udc))
1235 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1236 &dr_regs->usbcmd);
1237 else
1238 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1239 &dr_regs->usbcmd);
1240
1241 return 0;
1242}
1243
0f91349b
SAS		 1244static int fsl_start(struct usb_gadget_driver *driver,
1245 int (*bind)(struct usb_gadget *));
1246static int fsl_stop(struct usb_gadget_driver *driver);
9454a57a 1247/* defined in gadget.h */
b504882d
LY		 1248static struct usb_gadget_ops fsl_gadget_ops = {
1249 .get_frame = fsl_get_frame,
1250 .wakeup = fsl_wakeup,
1251/* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1252 .vbus_session = fsl_vbus_session,
1253 .vbus_draw = fsl_vbus_draw,
1254 .pullup = fsl_pullup,
0f91349b
SAS		 1255 .start = fsl_start,
1256 .stop = fsl_stop,
b504882d
LY		 1257};
1258
1259/* Set protocol stall on ep0, protocol stall will automatically be cleared
1260 on new transaction */
1261static void ep0stall(struct fsl_udc *udc)
1262{
1263 u32 tmp;
1264
1265 /* must set tx and rx to stall at the same time */
1266 tmp = fsl_readl(&dr_regs->endptctrl[0]);
1267 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1268 fsl_writel(tmp, &dr_regs->endptctrl[0]);
1269 udc->ep0_state = WAIT_FOR_SETUP;
1270 udc->ep0_dir = 0;
1271}
1272
1273/* Prime a status phase for ep0 */
1274static int ep0_prime_status(struct fsl_udc *udc, int direction)
1275{
1276 struct fsl_req *req = udc->status_req;
1277 struct fsl_ep *ep;
b504882d
LY		 1278
1279 if (direction == EP_DIR_IN)
1280 udc->ep0_dir = USB_DIR_IN;
1281 else
1282 udc->ep0_dir = USB_DIR_OUT;
1283
1284 ep = &udc->eps[0];
1285 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1286
1287 req->ep = ep;
1288 req->req.length = 0;
1289 req->req.status = -EINPROGRESS;
1290 req->req.actual = 0;
1291 req->req.complete = NULL;
1292 req->dtd_count = 0;
1293
3140d5b2
AG		 1294 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1295 req->req.buf, req->req.length,
1296 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1297 req->mapped = 1;
1298
b504882d 1299 if (fsl_req_to_dtd(req) == 0)
224b5039 1300 fsl_queue_td(ep, req);
b504882d
LY		 1301 else
1302 return -ENOMEM;
1303
b504882d
LY		 1304 list_add_tail(&req->queue, &ep->queue);
1305
224b5039 1306 return 0;
b504882d
LY		 1307}
1308
825bee3a 1309static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
b504882d
LY		 1310{
1311 struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1312
825bee3a
WN		 1313 if (ep->name)
1314 nuke(ep, -ESHUTDOWN);
b504882d
LY		 1315}
1316
1317/*
1318 * ch9 Set address
1319 */
1320static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1321{
1322 /* Save the new address to device struct */
1323 udc->device_address = (u8) value;
1324 /* Update usb state */
1325 udc->usb_state = USB_STATE_ADDRESS;
1326 /* Status phase */
1327 if (ep0_prime_status(udc, EP_DIR_IN))
1328 ep0stall(udc);
1329}
1330
1331/*
1332 * ch9 Get status
1333 */
1334static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1335 u16 index, u16 length)
1336{
1337 u16 tmp = 0; /* Status, cpu endian */
b504882d
LY		 1338 struct fsl_req *req;
1339 struct fsl_ep *ep;
b504882d
LY		 1340
1341 ep = &udc->eps[0];
1342
1343 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1344 /* Get device status */
1345 tmp = 1 << USB_DEVICE_SELF_POWERED;
1346 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1347 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1348 /* Get interface status */
1349 /* We don't have interface information in udc driver */
1350 tmp = 0;
1351 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1352 /* Get endpoint status */
1353 struct fsl_ep *target_ep;
1354
1355 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1356
1357 /* stall if endpoint doesn't exist */
1358 if (!target_ep->desc)
1359 goto stall;
1360 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1361 << USB_ENDPOINT_HALT;
1362 }
1363
1364 udc->ep0_dir = USB_DIR_IN;
1365 /* Borrow the per device status_req */
1366 req = udc->status_req;
1367 /* Fill in the reqest structure */
1368 *((u16 *) req->req.buf) = cpu_to_le16(tmp);
2ea6698d 1369
b504882d
LY		 1370 req->ep = ep;
1371 req->req.length = 2;
1372 req->req.status = -EINPROGRESS;
1373 req->req.actual = 0;
1374 req->req.complete = NULL;
1375 req->dtd_count = 0;
1376
3140d5b2
AG		 1377 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1378 req->req.buf, req->req.length,
1379 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1380 req->mapped = 1;
1381
b504882d
LY		 1382 /* prime the data phase */
1383 if ((fsl_req_to_dtd(req) == 0))
224b5039 1384 fsl_queue_td(ep, req);
b504882d
LY		 1385 else /* no mem */
1386 goto stall;
1387
b504882d
LY		 1388 list_add_tail(&req->queue, &ep->queue);
1389 udc->ep0_state = DATA_STATE_XMIT;
1390 return;
1391stall:
1392 ep0stall(udc);
1393}
1394
1395static void setup_received_irq(struct fsl_udc *udc,
1396 struct usb_ctrlrequest *setup)
1397{
1398 u16 wValue = le16_to_cpu(setup->wValue);
1399 u16 wIndex = le16_to_cpu(setup->wIndex);
1400 u16 wLength = le16_to_cpu(setup->wLength);
1401
1402 udc_reset_ep_queue(udc, 0);
1403
39d1f8c9 1404 /* We process some stardard setup requests here */
b504882d 1405 switch (setup->bRequest) {
b504882d 1406 case USB_REQ_GET_STATUS:
39d1f8c9
LY		 1407 /* Data+Status phase from udc */
1408 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
b504882d
LY		 1409 != (USB_DIR_IN | USB_TYPE_STANDARD))
1410 break;
1411 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
39d1f8c9 1412 return;
b504882d 1413
b504882d 1414 case USB_REQ_SET_ADDRESS:
39d1f8c9 1415 /* Status phase from udc */
b504882d
LY		 1416 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1417 | USB_RECIP_DEVICE))
1418 break;
1419 ch9setaddress(udc, wValue, wIndex, wLength);
39d1f8c9 1420 return;
b504882d 1421
b504882d
LY		 1422 case USB_REQ_CLEAR_FEATURE:
1423 case USB_REQ_SET_FEATURE:
39d1f8c9
LY		 1424 /* Status phase from udc */
1425 {
b504882d 1426 int rc = -EOPNOTSUPP;
2ea6698d 1427 u16 ptc = 0;
b504882d 1428
39d1f8c9
LY		 1429 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1430 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
b504882d
LY		 1431 int pipe = get_pipe_by_windex(wIndex);
1432 struct fsl_ep *ep;
1433
1434 if (wValue != 0 || wLength != 0 || pipe > udc->max_ep)
1435 break;
1436 ep = get_ep_by_pipe(udc, pipe);
1437
1438 spin_unlock(&udc->lock);
1439 rc = fsl_ep_set_halt(&ep->ep,
1440 (setup->bRequest == USB_REQ_SET_FEATURE)
1441 ? 1 : 0);
1442 spin_lock(&udc->lock);
1443
39d1f8c9
LY		 1444 } else if ((setup->bRequestType & (USB_RECIP_MASK
1445 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1446 | USB_TYPE_STANDARD)) {
b504882d
LY		 1447 /* Note: The driver has not include OTG support yet.
1448 * This will be set when OTG support is added */
2ea6698d
AG		 1449 if (wValue == USB_DEVICE_TEST_MODE)
1450 ptc = wIndex >> 8;
1451 else if (gadget_is_otg(&udc->gadget)) {
1452 if (setup->bRequest ==
1453 USB_DEVICE_B_HNP_ENABLE)
1454 udc->gadget.b_hnp_enable = 1;
1455 else if (setup->bRequest ==
1456 USB_DEVICE_A_HNP_SUPPORT)
1457 udc->gadget.a_hnp_support = 1;
1458 else if (setup->bRequest ==
1459 USB_DEVICE_A_ALT_HNP_SUPPORT)
1460 udc->gadget.a_alt_hnp_support = 1;
1461 }
b504882d 1462 rc = 0;
39d1f8c9
LY		 1463 } else
1464 break;
1465
b504882d
LY		 1466 if (rc == 0) {
1467 if (ep0_prime_status(udc, EP_DIR_IN))
1468 ep0stall(udc);
1469 }
2ea6698d
AG		 1470 if (ptc) {
1471 u32 tmp;
1472
1473 mdelay(10);
1474 tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1475 fsl_writel(tmp, &dr_regs->portsc1);
1476 printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1477 }
1478
39d1f8c9 1479 return;
b504882d 1480 }
b504882d 1481
39d1f8c9 1482 default:
b504882d
LY		 1483 break;
1484 }
39d1f8c9
LY		 1485
1486 /* Requests handled by gadget */
1487 if (wLength) {
1488 /* Data phase from gadget, status phase from udc */
1489 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1490 ? USB_DIR_IN : USB_DIR_OUT;
1491 spin_unlock(&udc->lock);
1492 if (udc->driver->setup(&udc->gadget,
1493 &udc->local_setup_buff) < 0)
1494 ep0stall(udc);
1495 spin_lock(&udc->lock);
1496 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1497 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1498 } else {
1499 /* No data phase, IN status from gadget */
1500 udc->ep0_dir = USB_DIR_IN;
1501 spin_unlock(&udc->lock);
1502 if (udc->driver->setup(&udc->gadget,
1503 &udc->local_setup_buff) < 0)
1504 ep0stall(udc);
1505 spin_lock(&udc->lock);
1506 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1507 }
b504882d
LY		 1508}
1509
1510/* Process request for Data or Status phase of ep0
1511 * prime status phase if needed */
1512static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1513 struct fsl_req *req)
1514{
1515 if (udc->usb_state == USB_STATE_ADDRESS) {
1516 /* Set the new address */
1517 u32 new_address = (u32) udc->device_address;
1518 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1519 &dr_regs->deviceaddr);
1520 }
1521
1522 done(ep0, req, 0);
1523
1524 switch (udc->ep0_state) {
1525 case DATA_STATE_XMIT:
1526 /* receive status phase */
1527 if (ep0_prime_status(udc, EP_DIR_OUT))
1528 ep0stall(udc);
1529 break;
1530 case DATA_STATE_RECV:
1531 /* send status phase */
1532 if (ep0_prime_status(udc, EP_DIR_IN))
1533 ep0stall(udc);
1534 break;
1535 case WAIT_FOR_OUT_STATUS:
1536 udc->ep0_state = WAIT_FOR_SETUP;
1537 break;
1538 case WAIT_FOR_SETUP:
bf7409a2 1539 ERR("Unexpect ep0 packets\n");
b504882d
LY		 1540 break;
1541 default:
1542 ep0stall(udc);
1543 break;
1544 }
1545}
1546
1547/* Tripwire mechanism to ensure a setup packet payload is extracted without
1548 * being corrupted by another incoming setup packet */
1549static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1550{
1551 u32 temp;
1552 struct ep_queue_head *qh;
09ba0def 1553 struct fsl_usb2_platform_data *pdata = udc->pdata;
b504882d
LY		 1554
1555 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1556
1557 /* Clear bit in ENDPTSETUPSTAT */
1558 temp = fsl_readl(&dr_regs->endptsetupstat);
1559 fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1560
1561 /* while a hazard exists when setup package arrives */
1562 do {
1563 /* Set Setup Tripwire */
1564 temp = fsl_readl(&dr_regs->usbcmd);
1565 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1566
1567 /* Copy the setup packet to local buffer */
09ba0def
AG		 1568 if (pdata->le_setup_buf) {
1569 u32 *p = (u32 *)buffer_ptr;
1570 u32 *s = (u32 *)qh->setup_buffer;
1571
1572 /* Convert little endian setup buffer to CPU endian */
1573 *p++ = le32_to_cpu(*s++);
1574 *p = le32_to_cpu(*s);
1575 } else {
1576 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1577 }
b504882d
LY		 1578 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1579
1580 /* Clear Setup Tripwire */
1581 temp = fsl_readl(&dr_regs->usbcmd);
1582 fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1583}
1584
1585/* process-ep_req(): free the completed Tds for this req */
1586static int process_ep_req(struct fsl_udc *udc, int pipe,
1587 struct fsl_req *curr_req)
1588{
1589 struct ep_td_struct *curr_td;
1590 int td_complete, actual, remaining_length, j, tmp;
1591 int status = 0;
1592 int errors = 0;
1593 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1594 int direction = pipe % 2;
1595
1596 curr_td = curr_req->head;
1597 td_complete = 0;
1598 actual = curr_req->req.length;
1599
1600 for (j = 0; j < curr_req->dtd_count; j++) {
09ba0def 1601 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
b504882d
LY		 1602 & DTD_PACKET_SIZE)
1603 >> DTD_LENGTH_BIT_POS;
1604 actual -= remaining_length;
1605
09ba0def
AG		 1606 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1607 if (errors & DTD_ERROR_MASK) {
b504882d
LY		 1608 if (errors & DTD_STATUS_HALTED) {
1609 ERR("dTD error %08x QH=%d\n", errors, pipe);
1610 /* Clear the errors and Halt condition */
09ba0def 1611 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
b504882d 1612 tmp &= ~errors;
09ba0def 1613 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
b504882d
LY		 1614 status = -EPIPE;
1615 /* FIXME: continue with next queued TD? */
1616
1617 break;
1618 }
1619 if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1620 VDBG("Transfer overflow");
1621 status = -EPROTO;
1622 break;
1623 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1624 VDBG("ISO error");
1625 status = -EILSEQ;
1626 break;
1627 } else
25985edc 1628 ERR("Unknown error has occurred (0x%x)!\n",
b504882d
LY		 1629 errors);
1630
09ba0def 1631 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
b504882d
LY		 1632 & DTD_STATUS_ACTIVE) {
1633 VDBG("Request not complete");
1634 status = REQ_UNCOMPLETE;
1635 return status;
1636 } else if (remaining_length) {
1637 if (direction) {
1638 VDBG("Transmit dTD remaining length not zero");
1639 status = -EPROTO;
1640 break;
1641 } else {
1642 td_complete++;
1643 break;
1644 }
1645 } else {
1646 td_complete++;
bf7409a2 1647 VDBG("dTD transmitted successful");
b504882d
LY		 1648 }
1649
1650 if (j != curr_req->dtd_count - 1)
1651 curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1652 }
1653
1654 if (status)
1655 return status;
1656
1657 curr_req->req.actual = actual;
1658
1659 return 0;
1660}
1661
1662/* Process a DTD completion interrupt */
1663static void dtd_complete_irq(struct fsl_udc *udc)
1664{
1665 u32 bit_pos;
1666 int i, ep_num, direction, bit_mask, status;
1667 struct fsl_ep *curr_ep;
1668 struct fsl_req *curr_req, *temp_req;
1669
1670 /* Clear the bits in the register */
1671 bit_pos = fsl_readl(&dr_regs->endptcomplete);
1672 fsl_writel(bit_pos, &dr_regs->endptcomplete);
1673
1674 if (!bit_pos)
1675 return;
1676
1677 for (i = 0; i < udc->max_ep * 2; i++) {
1678 ep_num = i >> 1;
1679 direction = i % 2;
1680
1681 bit_mask = 1 << (ep_num + 16 * direction);
1682
1683 if (!(bit_pos & bit_mask))
1684 continue;
1685
1686 curr_ep = get_ep_by_pipe(udc, i);
1687
1688 /* If the ep is configured */
1689 if (curr_ep->name == NULL) {
b6c63937 1690 WARNING("Invalid EP?");
b504882d
LY		 1691 continue;
1692 }
1693
1694 /* process the req queue until an uncomplete request */
1695 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1696 queue) {
1697 status = process_ep_req(udc, i, curr_req);
1698
1699 VDBG("status of process_ep_req= %d, ep = %d",
1700 status, ep_num);
1701 if (status == REQ_UNCOMPLETE)
1702 break;
1703 /* write back status to req */
1704 curr_req->req.status = status;
1705
1706 if (ep_num == 0) {
1707 ep0_req_complete(udc, curr_ep, curr_req);
1708 break;
1709 } else
1710 done(curr_ep, curr_req, status);
1711 }
1712 }
1713}
1714
e538dfda
MN		 1715static inline enum usb_device_speed portscx_device_speed(u32 reg)
1716{
0e042be3 1717 switch (reg & PORTSCX_PORT_SPEED_MASK) {
e538dfda
MN		 1718 case PORTSCX_PORT_SPEED_HIGH:
1719 return USB_SPEED_HIGH;
1720 case PORTSCX_PORT_SPEED_FULL:
1721 return USB_SPEED_FULL;
1722 case PORTSCX_PORT_SPEED_LOW:
1723 return USB_SPEED_LOW;
1724 default:
1725 return USB_SPEED_UNKNOWN;
1726 }
1727}
1728
b504882d
LY		 1729/* Process a port change interrupt */
1730static void port_change_irq(struct fsl_udc *udc)
1731{
83722bc9
AG		 1732 if (udc->bus_reset)
1733 udc->bus_reset = 0;
1734
b504882d 1735 /* Bus resetting is finished */
e538dfda 1736 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
b504882d 1737 /* Get the speed */
e538dfda
MN		 1738 udc->gadget.speed =
1739 portscx_device_speed(fsl_readl(&dr_regs->portsc1));
b504882d
LY		 1740
1741 /* Update USB state */
1742 if (!udc->resume_state)
1743 udc->usb_state = USB_STATE_DEFAULT;
1744}
1745
1746/* Process suspend interrupt */
1747static void suspend_irq(struct fsl_udc *udc)
1748{
1749 udc->resume_state = udc->usb_state;
1750 udc->usb_state = USB_STATE_SUSPENDED;
1751
1752 /* report suspend to the driver, serial.c does not support this */
1753 if (udc->driver->suspend)
1754 udc->driver->suspend(&udc->gadget);
1755}
1756
1757static void bus_resume(struct fsl_udc *udc)
1758{
1759 udc->usb_state = udc->resume_state;
1760 udc->resume_state = 0;
1761
1762 /* report resume to the driver, serial.c does not support this */
1763 if (udc->driver->resume)
1764 udc->driver->resume(&udc->gadget);
1765}
1766
1767/* Clear up all ep queues */
1768static int reset_queues(struct fsl_udc *udc)
1769{
1770 u8 pipe;
1771
1772 for (pipe = 0; pipe < udc->max_pipes; pipe++)
1773 udc_reset_ep_queue(udc, pipe);
1774
1775 /* report disconnect; the driver is already quiesced */
185e3dea 1776 spin_unlock(&udc->lock);
b504882d 1777 udc->driver->disconnect(&udc->gadget);
185e3dea 1778 spin_lock(&udc->lock);
b504882d
LY		 1779
1780 return 0;
1781}
1782
1783/* Process reset interrupt */
1784static void reset_irq(struct fsl_udc *udc)
1785{
1786 u32 temp;
1787 unsigned long timeout;
1788
1789 /* Clear the device address */
1790 temp = fsl_readl(&dr_regs->deviceaddr);
1791 fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1792
1793 udc->device_address = 0;
1794
1795 /* Clear usb state */
1796 udc->resume_state = 0;
1797 udc->ep0_dir = 0;
1798 udc->ep0_state = WAIT_FOR_SETUP;
1799 udc->remote_wakeup = 0; /* default to 0 on reset */
1800 udc->gadget.b_hnp_enable = 0;
1801 udc->gadget.a_hnp_support = 0;
1802 udc->gadget.a_alt_hnp_support = 0;
1803
1804 /* Clear all the setup token semaphores */
1805 temp = fsl_readl(&dr_regs->endptsetupstat);
1806 fsl_writel(temp, &dr_regs->endptsetupstat);
1807
1808 /* Clear all the endpoint complete status bits */
1809 temp = fsl_readl(&dr_regs->endptcomplete);
1810 fsl_writel(temp, &dr_regs->endptcomplete);
1811
1812 timeout = jiffies + 100;
1813 while (fsl_readl(&dr_regs->endpointprime)) {
1814 /* Wait until all endptprime bits cleared */
1815 if (time_after(jiffies, timeout)) {
1816 ERR("Timeout for reset\n");
1817 break;
1818 }
1819 cpu_relax();
1820 }
1821
1822 /* Write 1s to the flush register */
1823 fsl_writel(0xffffffff, &dr_regs->endptflush);
1824
1825 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1826 VDBG("Bus reset");
83722bc9
AG		 1827 /* Bus is reseting */
1828 udc->bus_reset = 1;
b504882d
LY		 1829 /* Reset all the queues, include XD, dTD, EP queue
1830 * head and TR Queue */
1831 reset_queues(udc);
1832 udc->usb_state = USB_STATE_DEFAULT;
1833 } else {
1834 VDBG("Controller reset");
1835 /* initialize usb hw reg except for regs for EP, not
1836 * touch usbintr reg */
1837 dr_controller_setup(udc);
1838
1839 /* Reset all internal used Queues */
1840 reset_queues(udc);
1841
1842 ep0_setup(udc);
1843
1844 /* Enable DR IRQ reg, Set Run bit, change udc state */
1845 dr_controller_run(udc);
1846 udc->usb_state = USB_STATE_ATTACHED;
1847 }
1848}
1849
1850/*
1851 * USB device controller interrupt handler
1852 */
1853static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1854{
1855 struct fsl_udc *udc = _udc;
1856 u32 irq_src;
1857 irqreturn_t status = IRQ_NONE;
1858 unsigned long flags;
1859
1860 /* Disable ISR for OTG host mode */
1861 if (udc->stopped)
1862 return IRQ_NONE;
1863 spin_lock_irqsave(&udc->lock, flags);
1864 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1865 /* Clear notification bits */
1866 fsl_writel(irq_src, &dr_regs->usbsts);
1867
1868 /* VDBG("irq_src [0x%8x]", irq_src); */
1869
1870 /* Need to resume? */
1871 if (udc->usb_state == USB_STATE_SUSPENDED)
1872 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1873 bus_resume(udc);
1874
1875 /* USB Interrupt */
1876 if (irq_src & USB_STS_INT) {
1877 VDBG("Packet int");
1878 /* Setup package, we only support ep0 as control ep */
1879 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1880 tripwire_handler(udc, 0,
1881 (u8 *) (&udc->local_setup_buff));
1882 setup_received_irq(udc, &udc->local_setup_buff);
1883 status = IRQ_HANDLED;
1884 }
1885
1886 /* completion of dtd */
1887 if (fsl_readl(&dr_regs->endptcomplete)) {
1888 dtd_complete_irq(udc);
1889 status = IRQ_HANDLED;
1890 }
1891 }
1892
1893 /* SOF (for ISO transfer) */
1894 if (irq_src & USB_STS_SOF) {
1895 status = IRQ_HANDLED;
1896 }
1897
1898 /* Port Change */
1899 if (irq_src & USB_STS_PORT_CHANGE) {
1900 port_change_irq(udc);
1901 status = IRQ_HANDLED;
1902 }
1903
1904 /* Reset Received */
1905 if (irq_src & USB_STS_RESET) {
83722bc9 1906 VDBG("reset int");
b504882d
LY		 1907 reset_irq(udc);
1908 status = IRQ_HANDLED;
1909 }
1910
1911 /* Sleep Enable (Suspend) */
1912 if (irq_src & USB_STS_SUSPEND) {
1913 suspend_irq(udc);
1914 status = IRQ_HANDLED;
1915 }
1916
1917 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
bf7409a2 1918 VDBG("Error IRQ %x", irq_src);
b504882d
LY		 1919 }
1920
1921 spin_unlock_irqrestore(&udc->lock, flags);
1922 return status;
1923}
1924
1925/*----------------------------------------------------------------*
1926 * Hook to gadget drivers
1927 * Called by initialization code of gadget drivers
1928*----------------------------------------------------------------*/
0f91349b 1929static int fsl_start(struct usb_gadget_driver *driver,
b0fca50f 1930 int (*bind)(struct usb_gadget *))
b504882d
LY		 1931{
1932 int retval = -ENODEV;
1933 unsigned long flags = 0;
1934
1935 if (!udc_controller)
1936 return -ENODEV;
1937
7177aed4 1938 if (!driver || driver->max_speed < USB_SPEED_FULL
b0fca50f 1939 || !bind || !driver->disconnect || !driver->setup)
b504882d
LY		 1940 return -EINVAL;
1941
1942 if (udc_controller->driver)
1943 return -EBUSY;
1944
1945 /* lock is needed but whether should use this lock or another */
1946 spin_lock_irqsave(&udc_controller->lock, flags);
1947
7483cff8 1948 driver->driver.bus = NULL;
b504882d
LY		 1949 /* hook up the driver */
1950 udc_controller->driver = driver;
1951 udc_controller->gadget.dev.driver = &driver->driver;
1952 spin_unlock_irqrestore(&udc_controller->lock, flags);
1953
1954 /* bind udc driver to gadget driver */
b0fca50f 1955 retval = bind(&udc_controller->gadget);
b504882d
LY		 1956 if (retval) {
1957 VDBG("bind to %s --> %d", driver->driver.name, retval);
7483cff8
WN		 1958 udc_controller->gadget.dev.driver = NULL;
1959 udc_controller->driver = NULL;
b504882d
LY		 1960 goto out;
1961 }
1962
83722bc9
AG		 1963 if (udc_controller->transceiver) {
1964 /* Suspend the controller until OTG enable it */
1965 udc_controller->stopped = 1;
1966 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1967
1968 /* connect to bus through transceiver */
1969 if (udc_controller->transceiver) {
1970 retval = otg_set_peripheral(udc_controller->transceiver,
1971 &udc_controller->gadget);
1972 if (retval < 0) {
1973 ERR("can't bind to transceiver\n");
1974 driver->unbind(&udc_controller->gadget);
1975 udc_controller->gadget.dev.driver = 0;
1976 udc_controller->driver = 0;
1977 return retval;
1978 }
1979 }
1980 } else {
1981 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1982 dr_controller_run(udc_controller);
1983 udc_controller->usb_state = USB_STATE_ATTACHED;
1984 udc_controller->ep0_state = WAIT_FOR_SETUP;
1985 udc_controller->ep0_dir = 0;
1986 }
bf7409a2 1987 printk(KERN_INFO "%s: bind to driver %s\n",
b504882d
LY		 1988 udc_controller->gadget.name, driver->driver.name);
1989
1990out:
1991 if (retval)
6f8aa65b
FS		 1992 printk(KERN_WARNING "gadget driver register failed %d\n",
1993 retval);
b504882d
LY		 1994 return retval;
1995}
b504882d
LY		 1996
1997/* Disconnect from gadget driver */
0f91349b 1998static int fsl_stop(struct usb_gadget_driver *driver)
b504882d
LY		 1999{
2000 struct fsl_ep *loop_ep;
2001 unsigned long flags;
2002
2003 if (!udc_controller)
2004 return -ENODEV;
2005
2006 if (!driver || driver != udc_controller->driver || !driver->unbind)
2007 return -EINVAL;
2008
b504882d 2009 if (udc_controller->transceiver)
7483cff8 2010 otg_set_peripheral(udc_controller->transceiver, NULL);
b504882d
LY		 2011
2012 /* stop DR, disable intr */
2013 dr_controller_stop(udc_controller);
2014
2015 /* in fact, no needed */
2016 udc_controller->usb_state = USB_STATE_ATTACHED;
2017 udc_controller->ep0_state = WAIT_FOR_SETUP;
2018 udc_controller->ep0_dir = 0;
2019
2020 /* stand operation */
2021 spin_lock_irqsave(&udc_controller->lock, flags);
2022 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2023 nuke(&udc_controller->eps[0], -ESHUTDOWN);
2024 list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2025 ep.ep_list)
2026 nuke(loop_ep, -ESHUTDOWN);
2027 spin_unlock_irqrestore(&udc_controller->lock, flags);
2028
1f15a506
AV		 2029 /* report disconnect; the controller is already quiesced */
2030 driver->disconnect(&udc_controller->gadget);
2031
b504882d
LY		 2032 /* unbind gadget and unhook driver. */
2033 driver->unbind(&udc_controller->gadget);
7483cff8
WN		 2034 udc_controller->gadget.dev.driver = NULL;
2035 udc_controller->driver = NULL;
b504882d 2036
6f8aa65b
FS		 2037 printk(KERN_WARNING "unregistered gadget driver '%s'\n",
2038 driver->driver.name);
b504882d
LY		 2039 return 0;
2040}
b504882d
LY		 2041
2042/*-------------------------------------------------------------------------
2043 PROC File System Support
2044-------------------------------------------------------------------------*/
2045#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2046
2047#include <linux/seq_file.h>
2048
2049static const char proc_filename[] = "driver/fsl_usb2_udc";
2050
2051static int fsl_proc_read(char *page, char **start, off_t off, int count,
2052 int *eof, void *_dev)
2053{
2054 char *buf = page;
2055 char *next = buf;
2056 unsigned size = count;
2057 unsigned long flags;
2058 int t, i;
2059 u32 tmp_reg;
2060 struct fsl_ep *ep = NULL;
2061 struct fsl_req *req;
2062
2063 struct fsl_udc *udc = udc_controller;
2064 if (off != 0)
2065 return 0;
2066
2067 spin_lock_irqsave(&udc->lock, flags);
2068
dc0d5c1e 2069 /* ------basic driver information ---- */
b504882d
LY		 2070 t = scnprintf(next, size,
2071 DRIVER_DESC "\n"
2072 "%s version: %s\n"
2073 "Gadget driver: %s\n\n",
2074 driver_name, DRIVER_VERSION,
2075 udc->driver ? udc->driver->driver.name : "(none)");
2076 size -= t;
2077 next += t;
2078
2079 /* ------ DR Registers ----- */
2080 tmp_reg = fsl_readl(&dr_regs->usbcmd);
2081 t = scnprintf(next, size,
2082 "USBCMD reg:\n"
2083 "SetupTW: %d\n"
2084 "Run/Stop: %s\n\n",
2085 (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2086 (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2087 size -= t;
2088 next += t;
2089
2090 tmp_reg = fsl_readl(&dr_regs->usbsts);
2091 t = scnprintf(next, size,
2092 "USB Status Reg:\n"
9d9d88c8 2093 "Dr Suspend: %d Reset Received: %d System Error: %s "
b504882d
LY		 2094 "USB Error Interrupt: %s\n\n",
2095 (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2096 (tmp_reg & USB_STS_RESET) ? 1 : 0,
2097 (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2098 (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2099 size -= t;
2100 next += t;
2101
2102 tmp_reg = fsl_readl(&dr_regs->usbintr);
2103 t = scnprintf(next, size,
2104 "USB Intrrupt Enable Reg:\n"
9d9d88c8 2105 "Sleep Enable: %d SOF Received Enable: %d "
b504882d 2106 "Reset Enable: %d\n"
9d9d88c8 2107 "System Error Enable: %d "
b504882d 2108 "Port Change Dectected Enable: %d\n"
9d9d88c8 2109 "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
b504882d
LY		 2110 (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2111 (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2112 (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2113 (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2114 (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2115 (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2116 (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2117 size -= t;
2118 next += t;
2119
2120 tmp_reg = fsl_readl(&dr_regs->frindex);
2121 t = scnprintf(next, size,
9d9d88c8 2122 "USB Frame Index Reg: Frame Number is 0x%x\n\n",
b504882d
LY		 2123 (tmp_reg & USB_FRINDEX_MASKS));
2124 size -= t;
2125 next += t;
2126
2127 tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2128 t = scnprintf(next, size,
9d9d88c8 2129 "USB Device Address Reg: Device Addr is 0x%x\n\n",
b504882d
LY		 2130 (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2131 size -= t;
2132 next += t;
2133
2134 tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2135 t = scnprintf(next, size,
9d9d88c8 2136 "USB Endpoint List Address Reg: "
b504882d
LY		 2137 "Device Addr is 0x%x\n\n",
2138 (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2139 size -= t;
2140 next += t;
2141
2142 tmp_reg = fsl_readl(&dr_regs->portsc1);
2143 t = scnprintf(next, size,
2144 "USB Port Status&Control Reg:\n"
9d9d88c8
WN		 2145 "Port Transceiver Type : %s Port Speed: %s\n"
2146 "PHY Low Power Suspend: %s Port Reset: %s "
2147 "Port Suspend Mode: %s\n"
2148 "Over-current Change: %s "
b504882d 2149 "Port Enable/Disable Change: %s\n"
9d9d88c8 2150 "Port Enabled/Disabled: %s "
b504882d
LY		 2151 "Current Connect Status: %s\n\n", ( {
2152 char *s;
2153 switch (tmp_reg & PORTSCX_PTS_FSLS) {
2154 case PORTSCX_PTS_UTMI:
2155 s = "UTMI"; break;
2156 case PORTSCX_PTS_ULPI:
2157 s = "ULPI "; break;
2158 case PORTSCX_PTS_FSLS:
2159 s = "FS/LS Serial"; break;
2160 default:
2161 s = "None"; break;
2162 }
e538dfda
MN		 2163 s;} ),
2164 usb_speed_string(portscx_device_speed(tmp_reg)),
b504882d
LY		 2165 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2166 "Normal PHY mode" : "Low power mode",
2167 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2168 "Not in Reset",
2169 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2170 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2171 "No",
2172 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2173 "Not change",
2174 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2175 "Not correct",
2176 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2177 "Attached" : "Not-Att");
2178 size -= t;
2179 next += t;
2180
2181 tmp_reg = fsl_readl(&dr_regs->usbmode);
2182 t = scnprintf(next, size,
9d9d88c8 2183 "USB Mode Reg: Controller Mode is: %s\n\n", ( {
b504882d
LY		 2184 char *s;
2185 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2186 case USB_MODE_CTRL_MODE_IDLE:
2187 s = "Idle"; break;
2188 case USB_MODE_CTRL_MODE_DEVICE:
2189 s = "Device Controller"; break;
2190 case USB_MODE_CTRL_MODE_HOST:
2191 s = "Host Controller"; break;
2192 default:
2193 s = "None"; break;
2194 }
2195 s;
2196 } ));
2197 size -= t;
2198 next += t;
2199
2200 tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2201 t = scnprintf(next, size,
9d9d88c8 2202 "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
b504882d
LY		 2203 (tmp_reg & EP_SETUP_STATUS_MASK));
2204 size -= t;
2205 next += t;
2206
2207 for (i = 0; i < udc->max_ep / 2; i++) {
2208 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2209 t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
2210 i, tmp_reg);
2211 size -= t;
2212 next += t;
2213 }
2214 tmp_reg = fsl_readl(&dr_regs->endpointprime);
9d9d88c8 2215 t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
b504882d
LY		 2216 size -= t;
2217 next += t;
2218
54e4026b 2219#ifndef CONFIG_ARCH_MXC
2ea6698d
AG		 2220 if (udc->pdata->have_sysif_regs) {
2221 tmp_reg = usb_sys_regs->snoop1;
2222 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2223 size -= t;
2224 next += t;
b504882d 2225
2ea6698d
AG		 2226 tmp_reg = usb_sys_regs->control;
2227 t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
2228 tmp_reg);
2229 size -= t;
2230 next += t;
2231 }
54e4026b 2232#endif
b504882d
LY		 2233
2234 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2235 ep = &udc->eps[0];
2236 t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
2237 ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2238 size -= t;
2239 next += t;
2240
2241 if (list_empty(&ep->queue)) {
2242 t = scnprintf(next, size, "its req queue is empty\n\n");
2243 size -= t;
2244 next += t;
2245 } else {
2246 list_for_each_entry(req, &ep->queue, queue) {
2247 t = scnprintf(next, size,
9d9d88c8 2248 "req %p actual 0x%x length 0x%x buf %p\n",
b504882d
LY		 2249 &req->req, req->req.actual,
2250 req->req.length, req->req.buf);
2251 size -= t;
2252 next += t;
2253 }
2254 }
2255 /* other gadget->eplist ep */
2256 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2257 if (ep->desc) {
2258 t = scnprintf(next, size,
2259 "\nFor %s Maxpkt is 0x%x "
2260 "index is 0x%x\n",
2261 ep->ep.name, ep_maxpacket(ep),
2262 ep_index(ep));
2263 size -= t;
2264 next += t;
2265
2266 if (list_empty(&ep->queue)) {
2267 t = scnprintf(next, size,
2268 "its req queue is empty\n\n");
2269 size -= t;
2270 next += t;
2271 } else {
2272 list_for_each_entry(req, &ep->queue, queue) {
2273 t = scnprintf(next, size,
9d9d88c8 2274 "req %p actual 0x%x length "
b504882d
LY		 2275 "0x%x buf %p\n",
2276 &req->req, req->req.actual,
2277 req->req.length, req->req.buf);
2278 size -= t;
2279 next += t;
2280 } /* end for each_entry of ep req */
2281 } /* end for else */
2282 } /* end for if(ep->queue) */
2283 } /* end (ep->desc) */
2284
2285 spin_unlock_irqrestore(&udc->lock, flags);
2286
2287 *eof = 1;
2288 return count - size;
2289}
2290
2291#define create_proc_file() create_proc_read_entry(proc_filename, \
2292 0, NULL, fsl_proc_read, NULL)
2293
2294#define remove_proc_file() remove_proc_entry(proc_filename, NULL)
2295
2296#else /* !CONFIG_USB_GADGET_DEBUG_FILES */
2297
2298#define create_proc_file() do {} while (0)
2299#define remove_proc_file() do {} while (0)
2300
2301#endif /* CONFIG_USB_GADGET_DEBUG_FILES */
2302
2303/*-------------------------------------------------------------------------*/
2304
2305/* Release udc structures */
2306static void fsl_udc_release(struct device *dev)
2307{
2308 complete(udc_controller->done);
37c4fd8c 2309 dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
b504882d
LY		 2310 udc_controller->ep_qh, udc_controller->ep_qh_dma);
2311 kfree(udc_controller);
2312}
2313
2314/******************************************************************
2315 Internal structure setup functions
2316*******************************************************************/
2317/*------------------------------------------------------------------
2318 * init resource for globle controller
2319 * Return the udc handle on success or NULL on failure
2320 ------------------------------------------------------------------*/
4365831d
LY		 2321static int __init struct_udc_setup(struct fsl_udc *udc,
2322 struct platform_device *pdev)
b504882d 2323{
b504882d
LY		 2324 struct fsl_usb2_platform_data *pdata;
2325 size_t size;
2326
b504882d
LY		 2327 pdata = pdev->dev.platform_data;
2328 udc->phy_mode = pdata->phy_mode;
b504882d
LY		 2329
2330 udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2331 if (!udc->eps) {
2332 ERR("malloc fsl_ep failed\n");
4365831d 2333 return -1;
b504882d
LY		 2334 }
2335
2336 /* initialized QHs, take care of alignment */
2337 size = udc->max_ep * sizeof(struct ep_queue_head);
2338 if (size < QH_ALIGNMENT)
2339 size = QH_ALIGNMENT;
2340 else if ((size % QH_ALIGNMENT) != 0) {
2341 size += QH_ALIGNMENT + 1;
2342 size &= ~(QH_ALIGNMENT - 1);
2343 }
2344 udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2345 &udc->ep_qh_dma, GFP_KERNEL);
2346 if (!udc->ep_qh) {
2347 ERR("malloc QHs for udc failed\n");
2348 kfree(udc->eps);
4365831d 2349 return -1;
b504882d
LY		 2350 }
2351
2352 udc->ep_qh_size = size;
2353
2354 /* Initialize ep0 status request structure */
2355 /* FIXME: fsl_alloc_request() ignores ep argument */
2356 udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2357 struct fsl_req, req);
2358 /* allocate a small amount of memory to get valid address */
2359 udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
b504882d
LY		 2360
2361 udc->resume_state = USB_STATE_NOTATTACHED;
2362 udc->usb_state = USB_STATE_POWERED;
2363 udc->ep0_dir = 0;
2364 udc->remote_wakeup = 0; /* default to 0 on reset */
b504882d 2365
4365831d 2366 return 0;
b504882d
LY		 2367}
2368
2369/*----------------------------------------------------------------
2370 * Setup the fsl_ep struct for eps
2371 * Link fsl_ep->ep to gadget->ep_list
2372 * ep0out is not used so do nothing here
2373 * ep0in should be taken care
2374 *--------------------------------------------------------------*/
2375static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2376 char *name, int link)
2377{
2378 struct fsl_ep *ep = &udc->eps[index];
2379
2380 ep->udc = udc;
2381 strcpy(ep->name, name);
2382 ep->ep.name = ep->name;
2383
2384 ep->ep.ops = &fsl_ep_ops;
2385 ep->stopped = 0;
2386
2387 /* for ep0: maxP defined in desc
2388 * for other eps, maxP is set by epautoconfig() called by gadget layer
2389 */
2390 ep->ep.maxpacket = (unsigned short) ~0;
2391
2392 /* the queue lists any req for this ep */
2393 INIT_LIST_HEAD(&ep->queue);
2394
2395 /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2396 if (link)
2397 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2398 ep->gadget = &udc->gadget;
2399 ep->qh = &udc->ep_qh[index];
2400
2401 return 0;
2402}
2403
2404/* Driver probe function
4365831d
LY		 2405 * all intialization operations implemented here except enabling usb_intr reg
2406 * board setup should have been done in the platform code
b504882d
LY		 2407 */
2408static int __init fsl_udc_probe(struct platform_device *pdev)
2409{
09ba0def 2410 struct fsl_usb2_platform_data *pdata;
b504882d
LY		 2411 struct resource *res;
2412 int ret = -ENODEV;
2413 unsigned int i;
4365831d 2414 u32 dccparams;
b504882d
LY		 2415
2416 if (strcmp(pdev->name, driver_name)) {
bf7409a2 2417 VDBG("Wrong device");
b504882d
LY		 2418 return -ENODEV;
2419 }
2420
4365831d
LY		 2421 udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2422 if (udc_controller == NULL) {
2423 ERR("malloc udc failed\n");
b504882d
LY		 2424 return -ENOMEM;
2425 }
2426
09ba0def
AG		 2427 pdata = pdev->dev.platform_data;
2428 udc_controller->pdata = pdata;
e06da9a8
WN		 2429 spin_lock_init(&udc_controller->lock);
2430 udc_controller->stopped = 1;
2431
83722bc9
AG		 2432#ifdef CONFIG_USB_OTG
2433 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2434 udc_controller->transceiver = otg_get_transceiver();
2435 if (!udc_controller->transceiver) {
2436 ERR("Can't find OTG driver!\n");
2437 ret = -ENODEV;
2438 goto err_kfree;
2439 }
2440 }
2441#endif
2442
b504882d 2443 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4365831d 2444 if (!res) {
23d7cd04
WN		 2445 ret = -ENXIO;
2446 goto err_kfree;
4365831d 2447 }
b504882d 2448
83722bc9 2449 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
28f65c11 2450 if (!request_mem_region(res->start, resource_size(res),
83722bc9
AG		 2451 driver_name)) {
2452 ERR("request mem region for %s failed\n", pdev->name);
2453 ret = -EBUSY;
2454 goto err_kfree;
2455 }
b504882d
LY		 2456 }
2457
54e4026b 2458 dr_regs = ioremap(res->start, resource_size(res));
b504882d
LY		 2459 if (!dr_regs) {
2460 ret = -ENOMEM;
23d7cd04 2461 goto err_release_mem_region;
b504882d
LY		 2462 }
2463
2ea6698d
AG		 2464 pdata->regs = (void *)dr_regs;
2465
2466 /*
2467 * do platform specific init: check the clock, grab/config pins, etc.
2468 */
2469 if (pdata->init && pdata->init(pdev)) {
2470 ret = -ENODEV;
2471 goto err_iounmap_noclk;
2472 }
2473
2474 /* Set accessors only after pdata->init() ! */
3140d5b2 2475 fsl_set_accessors(pdata);
09ba0def 2476
54e4026b 2477#ifndef CONFIG_ARCH_MXC
2ea6698d 2478 if (pdata->have_sysif_regs)
8981d76a 2479 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
54e4026b
GL		 2480#endif
2481
2482 /* Initialize USB clocks */
2483 ret = fsl_udc_clk_init(pdev);
2484 if (ret < 0)
2485 goto err_iounmap_noclk;
b504882d 2486
4365831d
LY		 2487 /* Read Device Controller Capability Parameters register */
2488 dccparams = fsl_readl(&dr_regs->dccparams);
2489 if (!(dccparams & DCCPARAMS_DC)) {
2490 ERR("This SOC doesn't support device role\n");
2491 ret = -ENODEV;
23d7cd04 2492 goto err_iounmap;
4365831d
LY		 2493 }
2494 /* Get max device endpoints */
2495 /* DEN is bidirectional ep number, max_ep doubles the number */
2496 udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2497
b504882d
LY		 2498 udc_controller->irq = platform_get_irq(pdev, 0);
2499 if (!udc_controller->irq) {
2500 ret = -ENODEV;
23d7cd04 2501 goto err_iounmap;
b504882d
LY		 2502 }
2503
37b5453d 2504 ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
b504882d
LY		 2505 driver_name, udc_controller);
2506 if (ret != 0) {
bf7409a2 2507 ERR("cannot request irq %d err %d\n",
b504882d 2508 udc_controller->irq, ret);
23d7cd04 2509 goto err_iounmap;
b504882d
LY		 2510 }
2511
4365831d
LY		 2512 /* Initialize the udc structure including QH member and other member */
2513 if (struct_udc_setup(udc_controller, pdev)) {
2514 ERR("Can't initialize udc data structure\n");
2515 ret = -ENOMEM;
23d7cd04 2516 goto err_free_irq;
4365831d
LY		 2517 }
2518
83722bc9
AG		 2519 if (!udc_controller->transceiver) {
2520 /* initialize usb hw reg except for regs for EP,
2521 * leave usbintr reg untouched */
2522 dr_controller_setup(udc_controller);
2523 }
b504882d 2524
54e4026b
GL		 2525 fsl_udc_clk_finalize(pdev);
2526
b504882d
LY		 2527 /* Setup gadget structure */
2528 udc_controller->gadget.ops = &fsl_gadget_ops;
d327ab5b 2529 udc_controller->gadget.max_speed = USB_SPEED_HIGH;
b504882d
LY		 2530 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2531 INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2532 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2533 udc_controller->gadget.name = driver_name;
2534
2535 /* Setup gadget.dev and register with kernel */
0031a06e 2536 dev_set_name(&udc_controller->gadget.dev, "gadget");
b504882d
LY		 2537 udc_controller->gadget.dev.release = fsl_udc_release;
2538 udc_controller->gadget.dev.parent = &pdev->dev;
2539 ret = device_register(&udc_controller->gadget.dev);
2540 if (ret < 0)
23d7cd04 2541 goto err_free_irq;
b504882d 2542
83722bc9
AG		 2543 if (udc_controller->transceiver)
2544 udc_controller->gadget.is_otg = 1;
2545
b504882d
LY		 2546 /* setup QH and epctrl for ep0 */
2547 ep0_setup(udc_controller);
2548
2549 /* setup udc->eps[] for ep0 */
2550 struct_ep_setup(udc_controller, 0, "ep0", 0);
2551 /* for ep0: the desc defined here;
2552 * for other eps, gadget layer called ep_enable with defined desc
2553 */
2554 udc_controller->eps[0].desc = &fsl_ep0_desc;
2555 udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2556
2557 /* setup the udc->eps[] for non-control endpoints and link
2558 * to gadget.ep_list */
2559 for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2560 char name[14];
2561
2562 sprintf(name, "ep%dout", i);
2563 struct_ep_setup(udc_controller, i * 2, name, 1);
2564 sprintf(name, "ep%din", i);
2565 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2566 }
2567
2568 /* use dma_pool for TD management */
2569 udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2570 sizeof(struct ep_td_struct),
2571 DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2572 if (udc_controller->td_pool == NULL) {
2573 ret = -ENOMEM;
23d7cd04 2574 goto err_unregister;
b504882d 2575 }
0f91349b
SAS		 2576
2577 ret = usb_add_gadget_udc(&pdev->dev, &udc_controller->gadget);
2578 if (ret)
2579 goto err_del_udc;
2580
b504882d
LY		 2581 create_proc_file();
2582 return 0;
2583
0f91349b
SAS		 2584err_del_udc:
2585 dma_pool_destroy(udc_controller->td_pool);
23d7cd04 2586err_unregister:
b504882d 2587 device_unregister(&udc_controller->gadget.dev);
23d7cd04 2588err_free_irq:
b504882d 2589 free_irq(udc_controller->irq, udc_controller);
23d7cd04 2590err_iounmap:
2ea6698d
AG		 2591 if (pdata->exit)
2592 pdata->exit(pdev);
54e4026b
GL		 2593 fsl_udc_clk_release();
2594err_iounmap_noclk:
b504882d 2595 iounmap(dr_regs);
23d7cd04 2596err_release_mem_region:
83722bc9 2597 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
28f65c11 2598 release_mem_region(res->start, resource_size(res));
23d7cd04 2599err_kfree:
4365831d 2600 kfree(udc_controller);
23d7cd04 2601 udc_controller = NULL;
b504882d
LY		 2602 return ret;
2603}
2604
2605/* Driver removal function
2606 * Free resources and finish pending transactions
2607 */
2608static int __exit fsl_udc_remove(struct platform_device *pdev)
2609{
2610 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2ea6698d 2611 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
b504882d
LY		 2612
2613 DECLARE_COMPLETION(done);
2614
2615 if (!udc_controller)
2616 return -ENODEV;
0f91349b
SAS		 2617
2618 usb_del_gadget_udc(&udc_controller->gadget);
b504882d
LY		 2619 udc_controller->done = &done;
2620
54e4026b
GL		 2621 fsl_udc_clk_release();
2622
b504882d
LY		 2623 /* DR has been stopped in usb_gadget_unregister_driver() */
2624 remove_proc_file();
2625
2626 /* Free allocated memory */
2627 kfree(udc_controller->status_req->req.buf);
2628 kfree(udc_controller->status_req);
2629 kfree(udc_controller->eps);
2630
2631 dma_pool_destroy(udc_controller->td_pool);
2632 free_irq(udc_controller->irq, udc_controller);
2633 iounmap(dr_regs);
83722bc9 2634 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
28f65c11 2635 release_mem_region(res->start, resource_size(res));
b504882d
LY		 2636
2637 device_unregister(&udc_controller->gadget.dev);
2638 /* free udc --wait for the release() finished */
2639 wait_for_completion(&done);
2640
2ea6698d
AG		 2641 /*
2642 * do platform specific un-initialization:
2643 * release iomux pins, etc.
2644 */
2645 if (pdata->exit)
2646 pdata->exit(pdev);
2647
b504882d
LY		 2648 return 0;
2649}
2650
2651/*-----------------------------------------------------------------
2652 * Modify Power management attributes
2653 * Used by OTG statemachine to disable gadget temporarily
2654 -----------------------------------------------------------------*/
2655static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2656{
2657 dr_controller_stop(udc_controller);
2658 return 0;
2659}
2660
2661/*-----------------------------------------------------------------
2662 * Invoked on USB resume. May be called in_interrupt.
2663 * Here we start the DR controller and enable the irq
2664 *-----------------------------------------------------------------*/
2665static int fsl_udc_resume(struct platform_device *pdev)
2666{
2667 /* Enable DR irq reg and set controller Run */
2668 if (udc_controller->stopped) {
2669 dr_controller_setup(udc_controller);
2670 dr_controller_run(udc_controller);
2671 }
2672 udc_controller->usb_state = USB_STATE_ATTACHED;
2673 udc_controller->ep0_state = WAIT_FOR_SETUP;
2674 udc_controller->ep0_dir = 0;
2675 return 0;
2676}
2677
83722bc9
AG		 2678static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2679{
2680 struct fsl_udc *udc = udc_controller;
2681 u32 mode, usbcmd;
2682
2683 mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2684
2685 pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2686
2687 /*
2688 * If the controller is already stopped, then this must be a
2689 * PM suspend. Remember this fact, so that we will leave the
2690 * controller stopped at PM resume time.
2691 */
2692 if (udc->stopped) {
2693 pr_debug("gadget already stopped, leaving early\n");
2694 udc->already_stopped = 1;
2695 return 0;
2696 }
2697
2698 if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2699 pr_debug("gadget not in device mode, leaving early\n");
2700 return 0;
2701 }
2702
2703 /* stop the controller */
2704 usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2705 fsl_writel(usbcmd, &dr_regs->usbcmd);
2706
2707 udc->stopped = 1;
2708
2709 pr_info("USB Gadget suspended\n");
2710
2711 return 0;
2712}
2713
2714static int fsl_udc_otg_resume(struct device *dev)
2715{
2716 pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
2717 udc_controller->stopped, udc_controller->already_stopped);
2718
2719 /*
2720 * If the controller was stopped at suspend time, then
2721 * don't resume it now.
2722 */
2723 if (udc_controller->already_stopped) {
2724 udc_controller->already_stopped = 0;
2725 pr_debug("gadget was already stopped, leaving early\n");
2726 return 0;
2727 }
2728
2729 pr_info("USB Gadget resume\n");
2730
2731 return fsl_udc_resume(NULL);
2732}
2733
b504882d
LY		 2734/*-------------------------------------------------------------------------
2735 Register entry point for the peripheral controller driver
2736--------------------------------------------------------------------------*/
2737
2738static struct platform_driver udc_driver = {
2739 .remove = __exit_p(fsl_udc_remove),
2740 /* these suspend and resume are not usb suspend and resume */
2741 .suspend = fsl_udc_suspend,
2742 .resume = fsl_udc_resume,
2743 .driver = {
2744 .name = (char *)driver_name,
2745 .owner = THIS_MODULE,
83722bc9
AG		 2746 /* udc suspend/resume called from OTG driver */
2747 .suspend = fsl_udc_otg_suspend,
2748 .resume = fsl_udc_otg_resume,
b504882d
LY		 2749 },
2750};
2751
2752static int __init udc_init(void)
2753{
2754 printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
2755 return platform_driver_probe(&udc_driver, fsl_udc_probe);
2756}
2757
2758module_init(udc_init);
2759
2760static void __exit udc_exit(void)
2761{
2762 platform_driver_unregister(&udc_driver);
6f8aa65b 2763 printk(KERN_WARNING "%s unregistered\n", driver_desc);
b504882d
LY		 2764}
2765
2766module_exit(udc_exit);
2767
2768MODULE_DESCRIPTION(DRIVER_DESC);
2769MODULE_AUTHOR(DRIVER_AUTHOR);
2770MODULE_LICENSE("GPL");
f34c32f1 2771MODULE_ALIAS("platform:fsl-usb2-udc");
Linux 6.x block layer and io_uring tree(s)