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Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...
[linux-2.6-block.git] / drivers / usb / gadget / ci13xxx_udc.c
CommitLineData
aa69a809
DL		 1/*
2 * ci13xxx_udc.c - MIPS USB IP core family device controller
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13/*
14 * Description: MIPS USB IP core family device controller
15 * Currently it only supports IP part number CI13412
16 *
17 * This driver is composed of several blocks:
18 * - HW: hardware interface
19 * - DBG: debug facilities (optional)
20 * - UTIL: utilities
21 * - ISR: interrupts handling
22 * - ENDPT: endpoint operations (Gadget API)
23 * - GADGET: gadget operations (Gadget API)
24 * - BUS: bus glue code, bus abstraction layer
25 * - PCI: PCI core interface and PCI resources (interrupts, memory...)
26 *
27 * Compile Options
28 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
29 * - STALL_IN: non-empty bulk-in pipes cannot be halted
30 * if defined mass storage compliance succeeds but with warnings
31 * => case 4: Hi > Dn
32 * => case 5: Hi > Di
33 * => case 8: Hi <> Do
34 * if undefined usbtest 13 fails
35 * - TRACE: enable function tracing (depends on DEBUG)
36 *
37 * Main Features
38 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
39 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
40 * - Normal & LPM support
41 *
42 * USBTEST Report
43 * - OK: 0-12, 13 (STALL_IN defined) & 14
44 * - Not Supported: 15 & 16 (ISO)
45 *
46 * TODO List
47 * - OTG
48 * - Isochronous & Interrupt Traffic
49 * - Handle requests which spawns into several TDs
50 * - GET_STATUS(device) - always reports 0
51 * - Gadget API (majority of optional features)
52 * - Suspend & Remote Wakeup
53 */
36825a2d 54#include <linux/delay.h>
aa69a809
DL		 55#include <linux/device.h>
56#include <linux/dmapool.h>
57#include <linux/dma-mapping.h>
58#include <linux/init.h>
59#include <linux/interrupt.h>
aa69a809
DL		 60#include <linux/io.h>
61#include <linux/irq.h>
62#include <linux/kernel.h>
63#include <linux/module.h>
64#include <linux/pci.h>
5a0e3ad6 65#include <linux/slab.h>
aa69a809
DL		 66#include <linux/usb/ch9.h>
67#include <linux/usb/gadget.h>
68
69#include "ci13xxx_udc.h"
70
71
72/******************************************************************************
73 * DEFINE
74 *****************************************************************************/
75/* ctrl register bank access */
76static DEFINE_SPINLOCK(udc_lock);
77
78/* driver name */
79#define UDC_DRIVER_NAME "ci13xxx_udc"
80
81/* control endpoint description */
82static const struct usb_endpoint_descriptor
83ctrl_endpt_desc = {
84 .bLength = USB_DT_ENDPOINT_SIZE,
85 .bDescriptorType = USB_DT_ENDPOINT,
86
87 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
88 .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
89};
90
91/* UDC descriptor */
92static struct ci13xxx *_udc;
93
94/* Interrupt statistics */
95#define ISR_MASK 0x1F
96static struct {
97 u32 test;
98 u32 ui;
99 u32 uei;
100 u32 pci;
101 u32 uri;
102 u32 sli;
103 u32 none;
104 struct {
105 u32 cnt;
106 u32 buf[ISR_MASK+1];
107 u32 idx;
108 } hndl;
109} isr_statistics;
110
111/**
112 * ffs_nr: find first (least significant) bit set
113 * @x: the word to search
114 *
115 * This function returns bit number (instead of position)
116 */
117static int ffs_nr(u32 x)
118{
119 int n = ffs(x);
120
121 return n ? n-1 : 32;
122}
123
124/******************************************************************************
125 * HW block
126 *****************************************************************************/
127/* register bank descriptor */
128static struct {
129 unsigned lpm; /* is LPM? */
130 void __iomem *abs; /* bus map offset */
131 void __iomem *cap; /* bus map offset + CAP offset + CAP data */
132 size_t size; /* bank size */
133} hw_bank;
134
135/* UDC register map */
136#define ABS_CAPLENGTH (0x100UL)
137#define ABS_HCCPARAMS (0x108UL)
138#define ABS_DCCPARAMS (0x124UL)
139#define ABS_TESTMODE (hw_bank.lpm ? 0x0FCUL : 0x138UL)
140/* offset to CAPLENTGH (addr + data) */
141#define CAP_USBCMD (0x000UL)
142#define CAP_USBSTS (0x004UL)
143#define CAP_USBINTR (0x008UL)
144#define CAP_DEVICEADDR (0x014UL)
145#define CAP_ENDPTLISTADDR (0x018UL)
146#define CAP_PORTSC (0x044UL)
f23e649b 147#define CAP_DEVLC (0x084UL)
aa69a809
DL		 148#define CAP_USBMODE (hw_bank.lpm ? 0x0C8UL : 0x068UL)
149#define CAP_ENDPTSETUPSTAT (hw_bank.lpm ? 0x0D8UL : 0x06CUL)
150#define CAP_ENDPTPRIME (hw_bank.lpm ? 0x0DCUL : 0x070UL)
151#define CAP_ENDPTFLUSH (hw_bank.lpm ? 0x0E0UL : 0x074UL)
152#define CAP_ENDPTSTAT (hw_bank.lpm ? 0x0E4UL : 0x078UL)
153#define CAP_ENDPTCOMPLETE (hw_bank.lpm ? 0x0E8UL : 0x07CUL)
154#define CAP_ENDPTCTRL (hw_bank.lpm ? 0x0ECUL : 0x080UL)
155#define CAP_LAST (hw_bank.lpm ? 0x12CUL : 0x0C0UL)
156
157/* maximum number of enpoints: valid only after hw_device_reset() */
158static unsigned hw_ep_max;
159
160/**
161 * hw_ep_bit: calculates the bit number
162 * @num: endpoint number
163 * @dir: endpoint direction
164 *
165 * This function returns bit number
166 */
167static inline int hw_ep_bit(int num, int dir)
168{
169 return num + (dir ? 16 : 0);
170}
171
172/**
173 * hw_aread: reads from register bitfield
174 * @addr: address relative to bus map
175 * @mask: bitfield mask
176 *
177 * This function returns register bitfield data
178 */
179static u32 hw_aread(u32 addr, u32 mask)
180{
181 return ioread32(addr + hw_bank.abs) & mask;
182}
183
184/**
185 * hw_awrite: writes to register bitfield
186 * @addr: address relative to bus map
187 * @mask: bitfield mask
188 * @data: new data
189 */
190static void hw_awrite(u32 addr, u32 mask, u32 data)
191{
192 iowrite32(hw_aread(addr, ~mask) | (data & mask),
193 addr + hw_bank.abs);
194}
195
196/**
197 * hw_cread: reads from register bitfield
198 * @addr: address relative to CAP offset plus content
199 * @mask: bitfield mask
200 *
201 * This function returns register bitfield data
202 */
203static u32 hw_cread(u32 addr, u32 mask)
204{
205 return ioread32(addr + hw_bank.cap) & mask;
206}
207
208/**
209 * hw_cwrite: writes to register bitfield
210 * @addr: address relative to CAP offset plus content
211 * @mask: bitfield mask
212 * @data: new data
213 */
214static void hw_cwrite(u32 addr, u32 mask, u32 data)
215{
216 iowrite32(hw_cread(addr, ~mask) | (data & mask),
217 addr + hw_bank.cap);
218}
219
220/**
221 * hw_ctest_and_clear: tests & clears register bitfield
222 * @addr: address relative to CAP offset plus content
223 * @mask: bitfield mask
224 *
225 * This function returns register bitfield data
226 */
227static u32 hw_ctest_and_clear(u32 addr, u32 mask)
228{
229 u32 reg = hw_cread(addr, mask);
230
231 iowrite32(reg, addr + hw_bank.cap);
232 return reg;
233}
234
235/**
236 * hw_ctest_and_write: tests & writes register bitfield
237 * @addr: address relative to CAP offset plus content
238 * @mask: bitfield mask
239 * @data: new data
240 *
241 * This function returns register bitfield data
242 */
243static u32 hw_ctest_and_write(u32 addr, u32 mask, u32 data)
244{
245 u32 reg = hw_cread(addr, ~0);
246
247 iowrite32((reg & ~mask) | (data & mask), addr + hw_bank.cap);
248 return (reg & mask) >> ffs_nr(mask);
249}
250
251/**
252 * hw_device_reset: resets chip (execute without interruption)
253 * @base: register base address
254 *
255 * This function returns an error code
256 */
257static int hw_device_reset(void __iomem *base)
258{
259 u32 reg;
260
261 /* bank is a module variable */
262 hw_bank.abs = base;
263
264 hw_bank.cap = hw_bank.abs;
265 hw_bank.cap += ABS_CAPLENGTH;
266 hw_bank.cap += ioread8(hw_bank.cap);
267
268 reg = hw_aread(ABS_HCCPARAMS, HCCPARAMS_LEN) >> ffs_nr(HCCPARAMS_LEN);
269 hw_bank.lpm = reg;
270 hw_bank.size = hw_bank.cap - hw_bank.abs;
271 hw_bank.size += CAP_LAST;
272 hw_bank.size /= sizeof(u32);
273
274 /* should flush & stop before reset */
275 hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0);
276 hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
277
278 hw_cwrite(CAP_USBCMD, USBCMD_RST, USBCMD_RST);
279 while (hw_cread(CAP_USBCMD, USBCMD_RST))
280 udelay(10); /* not RTOS friendly */
281
282 /* USBMODE should be configured step by step */
283 hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
284 hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
285 hw_cwrite(CAP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); /* HW >= 2.3 */
286
287 if (hw_cread(CAP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
288 pr_err("cannot enter in device mode");
289 pr_err("lpm = %i", hw_bank.lpm);
290 return -ENODEV;
291 }
292
293 reg = hw_aread(ABS_DCCPARAMS, DCCPARAMS_DEN) >> ffs_nr(DCCPARAMS_DEN);
294 if (reg == 0 || reg > ENDPT_MAX)
295 return -ENODEV;
296
297 hw_ep_max = reg; /* cache hw ENDPT_MAX */
298
299 /* setup lock mode ? */
300
301 /* ENDPTSETUPSTAT is '0' by default */
302
303 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
304
305 return 0;
306}
307
308/**
309 * hw_device_state: enables/disables interrupts & starts/stops device (execute
310 * without interruption)
311 * @dma: 0 => disable, !0 => enable and set dma engine
312 *
313 * This function returns an error code
314 */
315static int hw_device_state(u32 dma)
316{
317 if (dma) {
318 hw_cwrite(CAP_ENDPTLISTADDR, ~0, dma);
319 /* interrupt, error, port change, reset, sleep/suspend */
320 hw_cwrite(CAP_USBINTR, ~0,
321 USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
322 hw_cwrite(CAP_USBCMD, USBCMD_RS, USBCMD_RS);
323 } else {
324 hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
325 hw_cwrite(CAP_USBINTR, ~0, 0);
326 }
327 return 0;
328}
329
330/**
331 * hw_ep_flush: flush endpoint fifo (execute without interruption)
332 * @num: endpoint number
333 * @dir: endpoint direction
334 *
335 * This function returns an error code
336 */
337static int hw_ep_flush(int num, int dir)
338{
339 int n = hw_ep_bit(num, dir);
340
341 do {
342 /* flush any pending transfer */
343 hw_cwrite(CAP_ENDPTFLUSH, BIT(n), BIT(n));
344 while (hw_cread(CAP_ENDPTFLUSH, BIT(n)))
345 cpu_relax();
346 } while (hw_cread(CAP_ENDPTSTAT, BIT(n)));
347
348 return 0;
349}
350
351/**
352 * hw_ep_disable: disables endpoint (execute without interruption)
353 * @num: endpoint number
354 * @dir: endpoint direction
355 *
356 * This function returns an error code
357 */
358static int hw_ep_disable(int num, int dir)
359{
360 hw_ep_flush(num, dir);
361 hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32),
362 dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
363 return 0;
364}
365
366/**
367 * hw_ep_enable: enables endpoint (execute without interruption)
368 * @num: endpoint number
369 * @dir: endpoint direction
370 * @type: endpoint type
371 *
372 * This function returns an error code
373 */
374static int hw_ep_enable(int num, int dir, int type)
375{
376 u32 mask, data;
377
378 if (dir) {
379 mask = ENDPTCTRL_TXT; /* type */
380 data = type << ffs_nr(mask);
381
382 mask |= ENDPTCTRL_TXS; /* unstall */
383 mask |= ENDPTCTRL_TXR; /* reset data toggle */
384 data |= ENDPTCTRL_TXR;
385 mask |= ENDPTCTRL_TXE; /* enable */
386 data |= ENDPTCTRL_TXE;
387 } else {
388 mask = ENDPTCTRL_RXT; /* type */
389 data = type << ffs_nr(mask);
390
391 mask |= ENDPTCTRL_RXS; /* unstall */
392 mask |= ENDPTCTRL_RXR; /* reset data toggle */
393 data |= ENDPTCTRL_RXR;
394 mask |= ENDPTCTRL_RXE; /* enable */
395 data |= ENDPTCTRL_RXE;
396 }
397 hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32), mask, data);
398 return 0;
399}
400
401/**
402 * hw_ep_get_halt: return endpoint halt status
403 * @num: endpoint number
404 * @dir: endpoint direction
405 *
406 * This function returns 1 if endpoint halted
407 */
408static int hw_ep_get_halt(int num, int dir)
409{
410 u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
411
412 return hw_cread(CAP_ENDPTCTRL + num * sizeof(u32), mask) ? 1 : 0;
413}
414
415/**
416 * hw_ep_is_primed: test if endpoint is primed (execute without interruption)
417 * @num: endpoint number
418 * @dir: endpoint direction
419 *
420 * This function returns true if endpoint primed
421 */
422static int hw_ep_is_primed(int num, int dir)
423{
424 u32 reg = hw_cread(CAP_ENDPTPRIME, ~0) | hw_cread(CAP_ENDPTSTAT, ~0);
425
426 return test_bit(hw_ep_bit(num, dir), (void *)&reg);
427}
428
429/**
430 * hw_test_and_clear_setup_status: test & clear setup status (execute without
431 * interruption)
432 * @n: bit number (endpoint)
433 *
434 * This function returns setup status
435 */
436static int hw_test_and_clear_setup_status(int n)
437{
438 return hw_ctest_and_clear(CAP_ENDPTSETUPSTAT, BIT(n));
439}
440
441/**
442 * hw_ep_prime: primes endpoint (execute without interruption)
443 * @num: endpoint number
444 * @dir: endpoint direction
445 * @is_ctrl: true if control endpoint
446 *
447 * This function returns an error code
448 */
449static int hw_ep_prime(int num, int dir, int is_ctrl)
450{
451 int n = hw_ep_bit(num, dir);
452
453 /* the caller should flush first */
454 if (hw_ep_is_primed(num, dir))
455 return -EBUSY;
456
457 if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
458 return -EAGAIN;
459
460 hw_cwrite(CAP_ENDPTPRIME, BIT(n), BIT(n));
461
462 while (hw_cread(CAP_ENDPTPRIME, BIT(n)))
463 cpu_relax();
464 if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
465 return -EAGAIN;
466
467 /* status shoult be tested according with manual but it doesn't work */
468 return 0;
469}
470
471/**
472 * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
473 * without interruption)
474 * @num: endpoint number
475 * @dir: endpoint direction
476 * @value: true => stall, false => unstall
477 *
478 * This function returns an error code
479 */
480static int hw_ep_set_halt(int num, int dir, int value)
481{
482 if (value != 0 && value != 1)
483 return -EINVAL;
484
485 do {
486 u32 addr = CAP_ENDPTCTRL + num * sizeof(u32);
487 u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
488 u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
489
490 /* data toggle - reserved for EP0 but it's in ESS */
491 hw_cwrite(addr, mask_xs|mask_xr, value ? mask_xs : mask_xr);
492
493 } while (value != hw_ep_get_halt(num, dir));
494
495 return 0;
496}
497
498/**
499 * hw_intr_clear: disables interrupt & clears interrupt status (execute without
500 * interruption)
501 * @n: interrupt bit
502 *
503 * This function returns an error code
504 */
505static int hw_intr_clear(int n)
506{
507 if (n >= REG_BITS)
508 return -EINVAL;
509
510 hw_cwrite(CAP_USBINTR, BIT(n), 0);
511 hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
512 return 0;
513}
514
515/**
516 * hw_intr_force: enables interrupt & forces interrupt status (execute without
517 * interruption)
518 * @n: interrupt bit
519 *
520 * This function returns an error code
521 */
522static int hw_intr_force(int n)
523{
524 if (n >= REG_BITS)
525 return -EINVAL;
526
527 hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
528 hw_cwrite(CAP_USBINTR, BIT(n), BIT(n));
529 hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
530 hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, 0);
531 return 0;
532}
533
534/**
535 * hw_is_port_high_speed: test if port is high speed
536 *
537 * This function returns true if high speed port
538 */
539static int hw_port_is_high_speed(void)
540{
541 return hw_bank.lpm ? hw_cread(CAP_DEVLC, DEVLC_PSPD) :
542 hw_cread(CAP_PORTSC, PORTSC_HSP);
543}
544
545/**
546 * hw_port_test_get: reads port test mode value
547 *
548 * This function returns port test mode value
549 */
550static u8 hw_port_test_get(void)
551{
552 return hw_cread(CAP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
553}
554
555/**
556 * hw_port_test_set: writes port test mode (execute without interruption)
557 * @mode: new value
558 *
559 * This function returns an error code
560 */
561static int hw_port_test_set(u8 mode)
562{
563 const u8 TEST_MODE_MAX = 7;
564
565 if (mode > TEST_MODE_MAX)
566 return -EINVAL;
567
568 hw_cwrite(CAP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
569 return 0;
570}
571
572/**
573 * hw_read_intr_enable: returns interrupt enable register
574 *
575 * This function returns register data
576 */
577static u32 hw_read_intr_enable(void)
578{
579 return hw_cread(CAP_USBINTR, ~0);
580}
581
582/**
583 * hw_read_intr_status: returns interrupt status register
584 *
585 * This function returns register data
586 */
587static u32 hw_read_intr_status(void)
588{
589 return hw_cread(CAP_USBSTS, ~0);
590}
591
592/**
593 * hw_register_read: reads all device registers (execute without interruption)
594 * @buf: destination buffer
595 * @size: buffer size
596 *
597 * This function returns number of registers read
598 */
599static size_t hw_register_read(u32 *buf, size_t size)
600{
601 unsigned i;
602
603 if (size > hw_bank.size)
604 size = hw_bank.size;
605
606 for (i = 0; i < size; i++)
607 buf[i] = hw_aread(i * sizeof(u32), ~0);
608
609 return size;
610}
611
612/**
613 * hw_register_write: writes to register
614 * @addr: register address
615 * @data: register value
616 *
617 * This function returns an error code
618 */
619static int hw_register_write(u16 addr, u32 data)
620{
621 /* align */
622 addr /= sizeof(u32);
623
624 if (addr >= hw_bank.size)
625 return -EINVAL;
626
627 /* align */
628 addr *= sizeof(u32);
629
630 hw_awrite(addr, ~0, data);
631 return 0;
632}
633
634/**
635 * hw_test_and_clear_complete: test & clear complete status (execute without
636 * interruption)
637 * @n: bit number (endpoint)
638 *
639 * This function returns complete status
640 */
641static int hw_test_and_clear_complete(int n)
642{
643 return hw_ctest_and_clear(CAP_ENDPTCOMPLETE, BIT(n));
644}
645
646/**
647 * hw_test_and_clear_intr_active: test & clear active interrupts (execute
648 * without interruption)
649 *
650 * This function returns active interrutps
651 */
652static u32 hw_test_and_clear_intr_active(void)
653{
654 u32 reg = hw_read_intr_status() & hw_read_intr_enable();
655
656 hw_cwrite(CAP_USBSTS, ~0, reg);
657 return reg;
658}
659
660/**
661 * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
662 * interruption)
663 *
664 * This function returns guard value
665 */
666static int hw_test_and_clear_setup_guard(void)
667{
668 return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, 0);
669}
670
671/**
672 * hw_test_and_set_setup_guard: test & set setup guard (execute without
673 * interruption)
674 *
675 * This function returns guard value
676 */
677static int hw_test_and_set_setup_guard(void)
678{
679 return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
680}
681
682/**
683 * hw_usb_set_address: configures USB address (execute without interruption)
684 * @value: new USB address
685 *
686 * This function returns an error code
687 */
688static int hw_usb_set_address(u8 value)
689{
690 /* advance */
691 hw_cwrite(CAP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
692 value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
693 return 0;
694}
695
696/**
697 * hw_usb_reset: restart device after a bus reset (execute without
698 * interruption)
699 *
700 * This function returns an error code
701 */
702static int hw_usb_reset(void)
703{
704 hw_usb_set_address(0);
705
706 /* ESS flushes only at end?!? */
707 hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0); /* flush all EPs */
708
709 /* clear setup token semaphores */
710 hw_cwrite(CAP_ENDPTSETUPSTAT, 0, 0); /* writes its content */
711
712 /* clear complete status */
713 hw_cwrite(CAP_ENDPTCOMPLETE, 0, 0); /* writes its content */
714
715 /* wait until all bits cleared */
716 while (hw_cread(CAP_ENDPTPRIME, ~0))
717 udelay(10); /* not RTOS friendly */
718
719 /* reset all endpoints ? */
720
721 /* reset internal status and wait for further instructions
722 no need to verify the port reset status (ESS does it) */
723
724 return 0;
725}
726
727/******************************************************************************
728 * DBG block
729 *****************************************************************************/
730/**
731 * show_device: prints information about device capabilities and status
732 *
733 * Check "device.h" for details
734 */
735static ssize_t show_device(struct device *dev, struct device_attribute *attr,
736 char *buf)
737{
738 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
739 struct usb_gadget *gadget = &udc->gadget;
740 int n = 0;
741
742 dbg_trace("[%s] %p\n", __func__, buf);
743 if (attr == NULL || buf == NULL) {
744 dev_err(dev, "[%s] EINVAL\n", __func__);
745 return 0;
746 }
747
748 n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
749 gadget->speed);
750 n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
751 gadget->is_dualspeed);
752 n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
753 gadget->is_otg);
754 n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
755 gadget->is_a_peripheral);
756 n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
757 gadget->b_hnp_enable);
758 n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
759 gadget->a_hnp_support);
760 n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
761 gadget->a_alt_hnp_support);
762 n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
763 (gadget->name ? gadget->name : ""));
764
765 return n;
766}
767static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
768
769/**
770 * show_driver: prints information about attached gadget (if any)
771 *
772 * Check "device.h" for details
773 */
774static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
775 char *buf)
776{
777 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
778 struct usb_gadget_driver *driver = udc->driver;
779 int n = 0;
780
781 dbg_trace("[%s] %p\n", __func__, buf);
782 if (attr == NULL || buf == NULL) {
783 dev_err(dev, "[%s] EINVAL\n", __func__);
784 return 0;
785 }
786
787 if (driver == NULL)
788 return scnprintf(buf, PAGE_SIZE,
789 "There is no gadget attached!\n");
790
791 n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
792 (driver->function ? driver->function : ""));
793 n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
794 driver->speed);
795
796 return n;
797}
798static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
799
800/* Maximum event message length */
801#define DBG_DATA_MSG 64UL
802
803/* Maximum event messages */
804#define DBG_DATA_MAX 128UL
805
806/* Event buffer descriptor */
807static struct {
808 char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
809 unsigned idx; /* index */
810 unsigned tty; /* print to console? */
811 rwlock_t lck; /* lock */
812} dbg_data = {
813 .idx = 0,
814 .tty = 0,
815 .lck = __RW_LOCK_UNLOCKED(lck)
816};
817
818/**
819 * dbg_dec: decrements debug event index
820 * @idx: buffer index
821 */
822static void dbg_dec(unsigned *idx)
823{
824 *idx = (*idx - 1) & (DBG_DATA_MAX-1);
825}
826
827/**
828 * dbg_inc: increments debug event index
829 * @idx: buffer index
830 */
831static void dbg_inc(unsigned *idx)
832{
833 *idx = (*idx + 1) & (DBG_DATA_MAX-1);
834}
835
836/**
837 * dbg_print: prints the common part of the event
838 * @addr: endpoint address
839 * @name: event name
840 * @status: status
841 * @extra: extra information
842 */
843static void dbg_print(u8 addr, const char *name, int status, const char *extra)
844{
845 struct timeval tval;
846 unsigned int stamp;
847 unsigned long flags;
848
849 write_lock_irqsave(&dbg_data.lck, flags);
850
851 do_gettimeofday(&tval);
852 stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
853 stamp = stamp * 1000000 + tval.tv_usec;
854
855 scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
856