projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
usb: amd5536udc: Fix the type of ep_string
[linux-2.6-block.git] / drivers / usb / gadget / amd5536udc.c
CommitLineData
55d402d8
TD		 1/*
2 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
3 *
4 * Copyright (C) 2005-2007 AMD (http://www.amd.com)
5 * Author: Thomas Dahlmann
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
55d402d8
TD		 11 */
12
13/*
14 * The AMD5536 UDC is part of the x86 southbridge AMD Geode CS5536.
15 * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
16 * provides 4 IN and 4 OUT endpoints (bulk or interrupt type).
17 *
18 * Make sure that UDC is assigned to port 4 by BIOS settings (port can also
19 * be used as host port) and UOC bits PAD_EN and APU are set (should be done
20 * by BIOS init).
21 *
22 * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
23 * work without updating NET_IP_ALIGN. Or PIO mode (module param "use_dma=0")
24 * can be used with gadget ether.
25 */
26
27/* debug control */
28/* #define UDC_VERBOSE */
29
30/* Driver strings */
31#define UDC_MOD_DESCRIPTION "AMD 5536 UDC - USB Device Controller"
32#define UDC_DRIVER_VERSION_STRING "01.00.0206 - $Revision: #3 $"
33
34/* system */
35#include <linux/module.h>
36#include <linux/pci.h>
37#include <linux/kernel.h>
55d402d8
TD		 38#include <linux/delay.h>
39#include <linux/ioport.h>
40#include <linux/sched.h>
41#include <linux/slab.h>
55d402d8
TD		 42#include <linux/errno.h>
43#include <linux/init.h>
44#include <linux/timer.h>
45#include <linux/list.h>
46#include <linux/interrupt.h>
47#include <linux/ioctl.h>
48#include <linux/fs.h>
49#include <linux/dmapool.h>
50#include <linux/moduleparam.h>
51#include <linux/device.h>
52#include <linux/io.h>
53#include <linux/irq.h>
b38b03b3 54#include <linux/prefetch.h>
55d402d8
TD		 55
56#include <asm/byteorder.h>
57#include <asm/system.h>
58#include <asm/unaligned.h>
59
60/* gadget stack */
61#include <linux/usb/ch9.h>
9454a57a 62#include <linux/usb/gadget.h>
55d402d8
TD		 63
64/* udc specific */
65#include "amd5536udc.h"
66
67
68static void udc_tasklet_disconnect(unsigned long);
69static void empty_req_queue(struct udc_ep *);
70static int udc_probe(struct udc *dev);
71static void udc_basic_init(struct udc *dev);
72static void udc_setup_endpoints(struct udc *dev);
73static void udc_soft_reset(struct udc *dev);
74static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep);
75static void udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq);
76static int udc_free_dma_chain(struct udc *dev, struct udc_request *req);
77static int udc_create_dma_chain(struct udc_ep *ep, struct udc_request *req,
78 unsigned long buf_len, gfp_t gfp_flags);
79static int udc_remote_wakeup(struct udc *dev);
80static int udc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
81static void udc_pci_remove(struct pci_dev *pdev);
82
83/* description */
84static const char mod_desc[] = UDC_MOD_DESCRIPTION;
85static const char name[] = "amd5536udc";
86
87/* structure to hold endpoint function pointers */
88static const struct usb_ep_ops udc_ep_ops;
89
90/* received setup data */
91static union udc_setup_data setup_data;
92
93/* pointer to device object */
94static struct udc *udc;
95
96/* irq spin lock for soft reset */
97static DEFINE_SPINLOCK(udc_irq_spinlock);
98/* stall spin lock */
99static DEFINE_SPINLOCK(udc_stall_spinlock);
100
101/*
102* slave mode: pending bytes in rx fifo after nyet,
103* used if EPIN irq came but no req was available
104*/
105static unsigned int udc_rxfifo_pending;
106
107/* count soft resets after suspend to avoid loop */
108static int soft_reset_occured;
109static int soft_reset_after_usbreset_occured;
110
111/* timer */
112static struct timer_list udc_timer;
113static int stop_timer;
114
115/* set_rde -- Is used to control enabling of RX DMA. Problem is
116 * that UDC has only one bit (RDE) to enable/disable RX DMA for
117 * all OUT endpoints. So we have to handle race conditions like
118 * when OUT data reaches the fifo but no request was queued yet.
119 * This cannot be solved by letting the RX DMA disabled until a
120 * request gets queued because there may be other OUT packets
121 * in the FIFO (important for not blocking control traffic).
122 * The value of set_rde controls the correspondig timer.
123 *
124 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
125 * set_rde 0 == do not touch RDE, do no start the RDE timer
126 * set_rde 1 == timer function will look whether FIFO has data
127 * set_rde 2 == set by timer function to enable RX DMA on next call
128 */
129static int set_rde = -1;
130
131static DECLARE_COMPLETION(on_exit);
132static struct timer_list udc_pollstall_timer;
133static int stop_pollstall_timer;
134static DECLARE_COMPLETION(on_pollstall_exit);
135
136/* tasklet for usb disconnect */
137static DECLARE_TASKLET(disconnect_tasklet, udc_tasklet_disconnect,
138 (unsigned long) &udc);
139
140
141/* endpoint names used for print */
142static const char ep0_string[] = "ep0in";
34af3738 143static const char *const ep_string[] = {
55d402d8
TD		 144 ep0_string,
145 "ep1in-int", "ep2in-bulk", "ep3in-bulk", "ep4in-bulk", "ep5in-bulk",
146 "ep6in-bulk", "ep7in-bulk", "ep8in-bulk", "ep9in-bulk", "ep10in-bulk",
147 "ep11in-bulk", "ep12in-bulk", "ep13in-bulk", "ep14in-bulk",
148 "ep15in-bulk", "ep0out", "ep1out-bulk", "ep2out-bulk", "ep3out-bulk",
149 "ep4out-bulk", "ep5out-bulk", "ep6out-bulk", "ep7out-bulk",
150 "ep8out-bulk", "ep9out-bulk", "ep10out-bulk", "ep11out-bulk",
151 "ep12out-bulk", "ep13out-bulk", "ep14out-bulk", "ep15out-bulk"
152};
153
154/* DMA usage flag */
90ab5ee9 155static bool use_dma = 1;
55d402d8 156/* packet per buffer dma */
90ab5ee9 157static bool use_dma_ppb = 1;
55d402d8 158/* with per descr. update */
90ab5ee9 159static bool use_dma_ppb_du;
55d402d8
TD		 160/* buffer fill mode */
161static int use_dma_bufferfill_mode;
162/* full speed only mode */
90ab5ee9 163static bool use_fullspeed;
55d402d8
TD		 164/* tx buffer size for high speed */
165static unsigned long hs_tx_buf = UDC_EPIN_BUFF_SIZE;
166
167/* module parameters */
168module_param(use_dma, bool, S_IRUGO);
169MODULE_PARM_DESC(use_dma, "true for DMA");
170module_param(use_dma_ppb, bool, S_IRUGO);
171MODULE_PARM_DESC(use_dma_ppb, "true for DMA in packet per buffer mode");
172module_param(use_dma_ppb_du, bool, S_IRUGO);
173MODULE_PARM_DESC(use_dma_ppb_du,
174 "true for DMA in packet per buffer mode with descriptor update");
175module_param(use_fullspeed, bool, S_IRUGO);
176MODULE_PARM_DESC(use_fullspeed, "true for fullspeed only");
177
178/*---------------------------------------------------------------------------*/
179/* Prints UDC device registers and endpoint irq registers */
180static void print_regs(struct udc *dev)
181{
182 DBG(dev, "------- Device registers -------\n");
183 DBG(dev, "dev config = %08x\n", readl(&dev->regs->cfg));
184 DBG(dev, "dev control = %08x\n", readl(&dev->regs->ctl));
185 DBG(dev, "dev status = %08x\n", readl(&dev->regs->sts));
186 DBG(dev, "\n");
187 DBG(dev, "dev int's = %08x\n", readl(&dev->regs->irqsts));
188 DBG(dev, "dev intmask = %08x\n", readl(&dev->regs->irqmsk));
189 DBG(dev, "\n");
190 DBG(dev, "dev ep int's = %08x\n", readl(&dev->regs->ep_irqsts));
191 DBG(dev, "dev ep intmask = %08x\n", readl(&dev->regs->ep_irqmsk));
192 DBG(dev, "\n");
193 DBG(dev, "USE DMA = %d\n", use_dma);
194 if (use_dma && use_dma_ppb && !use_dma_ppb_du) {
195 DBG(dev, "DMA mode = PPBNDU (packet per buffer "
196 "WITHOUT desc. update)\n");
197 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBNDU");
0cf7a633 198 } else if (use_dma && use_dma_ppb && use_dma_ppb_du) {
55d402d8
TD		 199 DBG(dev, "DMA mode = PPBDU (packet per buffer "
200 "WITH desc. update)\n");
201 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBDU");
202 }
203 if (use_dma && use_dma_bufferfill_mode) {
204 DBG(dev, "DMA mode = BF (buffer fill mode)\n");
205 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "BF");
206 }
170b778f 207 if (!use_dma)
55d402d8 208 dev_info(&dev->pdev->dev, "FIFO mode\n");
55d402d8
TD		 209 DBG(dev, "-------------------------------------------------------\n");
210}
211
212/* Masks unused interrupts */
213static int udc_mask_unused_interrupts(struct udc *dev)
214{
215 u32 tmp;
216
217 /* mask all dev interrupts */
218 tmp = AMD_BIT(UDC_DEVINT_SVC) |
219 AMD_BIT(UDC_DEVINT_ENUM) |
220 AMD_BIT(UDC_DEVINT_US) |
221 AMD_BIT(UDC_DEVINT_UR) |
222 AMD_BIT(UDC_DEVINT_ES) |
223 AMD_BIT(UDC_DEVINT_SI) |
224 AMD_BIT(UDC_DEVINT_SOF)|
225 AMD_BIT(UDC_DEVINT_SC);
226 writel(tmp, &dev->regs->irqmsk);
227
228 /* mask all ep interrupts */
229 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk);
230
231 return 0;
232}
233
234/* Enables endpoint 0 interrupts */
235static int udc_enable_ep0_interrupts(struct udc *dev)
236{
237 u32 tmp;
238
239 DBG(dev, "udc_enable_ep0_interrupts()\n");
240
241 /* read irq mask */
242 tmp = readl(&dev->regs->ep_irqmsk);
243 /* enable ep0 irq's */
244 tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0)
245 & AMD_UNMASK_BIT(UDC_EPINT_OUT_EP0);
246 writel(tmp, &dev->regs->ep_irqmsk);
247
248 return 0;
249}
250
251/* Enables device interrupts for SET_INTF and SET_CONFIG */
252static int udc_enable_dev_setup_interrupts(struct udc *dev)
253{
254 u32 tmp;
255
256 DBG(dev, "enable device interrupts for setup data\n");
257
258 /* read irq mask */
259 tmp = readl(&dev->regs->irqmsk);
260
261 /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
262 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI)
263 & AMD_UNMASK_BIT(UDC_DEVINT_SC)
264 & AMD_UNMASK_BIT(UDC_DEVINT_UR)
265 & AMD_UNMASK_BIT(UDC_DEVINT_SVC)
266 & AMD_UNMASK_BIT(UDC_DEVINT_ENUM);
267 writel(tmp, &dev->regs->irqmsk);
268
269 return 0;
270}
271
25985edc 272/* Calculates fifo start of endpoint based on preceding endpoints */
55d402d8
TD		 273static int udc_set_txfifo_addr(struct udc_ep *ep)
274{
275 struct udc *dev;
276 u32 tmp;
277 int i;
278
279 if (!ep || !(ep->in))
280 return -EINVAL;
281
282 dev = ep->dev;
283 ep->txfifo = dev->txfifo;
284
285 /* traverse ep's */
286 for (i = 0; i < ep->num; i++) {
287 if (dev->ep[i].regs) {
288 /* read fifo size */
289 tmp = readl(&dev->ep[i].regs->bufin_framenum);
290 tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE);
291 ep->txfifo += tmp;
292 }
293 }
294 return 0;
295}
296
297/* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
298static u32 cnak_pending;
299
300static void UDC_QUEUE_CNAK(struct udc_ep *ep, unsigned num)
301{
302 if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) {
303 DBG(ep->dev, "NAK could not be cleared for ep%d\n", num);
304 cnak_pending |= 1 << (num);
305 ep->naking = 1;
306 } else
307 cnak_pending = cnak_pending & (~(1 << (num)));
308}
309
310
311/* Enables endpoint, is called by gadget driver */
312static int
313udc_ep_enable(struct usb_ep *usbep, const struct usb_endpoint_descriptor *desc)
314{
315 struct udc_ep *ep;
316 struct udc *dev;
317 u32 tmp;
318 unsigned long iflags;
319 u8 udc_csr_epix;
fd05e720 320 unsigned maxpacket;
55d402d8
TD		 321
322 if (!usbep
323 || usbep->name == ep0_string
324 || !desc
325 || desc->bDescriptorType != USB_DT_ENDPOINT)
326 return -EINVAL;
327
328 ep = container_of(usbep, struct udc_ep, ep);
329 dev = ep->dev;
330
331 DBG(dev, "udc_ep_enable() ep %d\n", ep->num);
332
333 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
334 return -ESHUTDOWN;
335
336 spin_lock_irqsave(&dev->lock, iflags);
337 ep->desc = desc;
338
339 ep->halted = 0;
340
341 /* set traffic type */
342 tmp = readl(&dev->ep[ep->num].regs->ctl);
343 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET);
344 writel(tmp, &dev->ep[ep->num].regs->ctl);
345
346 /* set max packet size */
29cc8897 347 maxpacket = usb_endpoint_maxp(desc);
55d402d8 348 tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt);
fd05e720
AV		 349 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE);
350 ep->ep.maxpacket = maxpacket;
55d402d8
TD		 351 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt);
352
353 /* IN ep */
354 if (ep->in) {
355
356 /* ep ix in UDC CSR register space */
357 udc_csr_epix = ep->num;
358
359 /* set buffer size (tx fifo entries) */
360 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum);
361 /* double buffering: fifo size = 2 x max packet size */
362 tmp = AMD_ADDBITS(
363 tmp,
fd05e720
AV		 364 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
365 / UDC_DWORD_BYTES,
55d402d8
TD		 366 UDC_EPIN_BUFF_SIZE);
367 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum);
368
369 /* calc. tx fifo base addr */
370 udc_set_txfifo_addr(ep);
371
372 /* flush fifo */
373 tmp = readl(&ep->regs->ctl);
374 tmp |= AMD_BIT(UDC_EPCTL_F);
375 writel(tmp, &ep->regs->ctl);
376
377 /* OUT ep */
378 } else {
379 /* ep ix in UDC CSR register space */
380 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
381
382 /* set max packet size UDC CSR */
383 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
fd05e720 384 tmp = AMD_ADDBITS(tmp, maxpacket,
55d402d8
TD		 385 UDC_CSR_NE_MAX_PKT);
386 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
387
388 if (use_dma && !ep->in) {
389 /* alloc and init BNA dummy request */
390 ep->bna_dummy_req = udc_alloc_bna_dummy(ep);
391 ep->bna_occurred = 0;
392 }
393
394 if (ep->num != UDC_EP0OUT_IX)
395 dev->data_ep_enabled = 1;
396 }
397
398 /* set ep values */
399 tmp = readl(&dev->csr->ne[udc_csr_epix]);
400 /* max packet */
fd05e720 401 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT);
55d402d8
TD		 402 /* ep number */
403 tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM);
404 /* ep direction */
405 tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR);
406 /* ep type */
407 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE);
408 /* ep config */
409 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG);
410 /* ep interface */
411 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF);
412 /* ep alt */
413 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT);
414 /* write reg */
415 writel(tmp, &dev->csr->ne[udc_csr_epix]);
416
417 /* enable ep irq */
418 tmp = readl(&dev->regs->ep_irqmsk);
419 tmp &= AMD_UNMASK_BIT(ep->num);
420 writel(tmp, &dev->regs->ep_irqmsk);
421
422 /*
423 * clear NAK by writing CNAK
424 * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
425 */
426 if (!use_dma || ep->in) {
427 tmp = readl(&ep->regs->ctl);
428 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
429 writel(tmp, &ep->regs->ctl);
430 ep->naking = 0;
431 UDC_QUEUE_CNAK(ep, ep->num);
432 }
433 tmp = desc->bEndpointAddress;
434 DBG(dev, "%s enabled\n", usbep->name);
435
436 spin_unlock_irqrestore(&dev->lock, iflags);
437 return 0;
438}
439
440/* Resets endpoint */
441static void ep_init(struct udc_regs __iomem *regs, struct udc_ep *ep)
442{
443 u32 tmp;
444
445 VDBG(ep->dev, "ep-%d reset\n", ep->num);
446 ep->desc = NULL;
f9c56cdd 447 ep->ep.desc = NULL;
55d402d8
TD		 448 ep->ep.ops = &udc_ep_ops;
449 INIT_LIST_HEAD(&ep->queue);
450
451 ep->ep.maxpacket = (u16) ~0;
452 /* set NAK */
453 tmp = readl(&ep->regs->ctl);
454 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
455 writel(tmp, &ep->regs->ctl);
456 ep->naking = 1;
457
458 /* disable interrupt */
459 tmp = readl(&regs->ep_irqmsk);
460 tmp |= AMD_BIT(ep->num);
461 writel(tmp, &regs->ep_irqmsk);
462
463 if (ep->in) {
464 /* unset P and IN bit of potential former DMA */
465 tmp = readl(&ep->regs->ctl);
466 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P);
467 writel(tmp, &ep->regs->ctl);
468
469 tmp = readl(&ep->regs->sts);
470 tmp |= AMD_BIT(UDC_EPSTS_IN);
471 writel(tmp, &ep->regs->sts);
472
473 /* flush the fifo */
474 tmp = readl(&ep->regs->ctl);
475 tmp |= AMD_BIT(UDC_EPCTL_F);
476 writel(tmp, &ep->regs->ctl);
477
478 }
479 /* reset desc pointer */
480 writel(0, &ep->regs->desptr);
481}
482
483/* Disables endpoint, is called by gadget driver */
484static int udc_ep_disable(struct usb_ep *usbep)
485{
486 struct udc_ep *ep = NULL;
487 unsigned long iflags;
488
489 if (!usbep)
490 return -EINVAL;
491
492 ep = container_of(usbep, struct udc_ep, ep);
493 if (usbep->name == ep0_string || !ep->desc)
494 return -EINVAL;
495
496 DBG(ep->dev, "Disable ep-%d\n", ep->num);
497
498 spin_lock_irqsave(&ep->dev->lock, iflags);
499 udc_free_request(&ep->ep, &ep->bna_dummy_req->req);
500 empty_req_queue(ep);
501 ep_init(ep->dev->regs, ep);
502 spin_unlock_irqrestore(&ep->dev->lock, iflags);
503
504 return 0;
505}
506
507/* Allocates request packet, called by gadget driver */
508static struct usb_request *
509udc_alloc_request(struct usb_ep *usbep, gfp_t gfp)
510{
511 struct udc_request *req;
512 struct udc_data_dma *dma_desc;
513 struct udc_ep *ep;
514
515 if (!usbep)
516 return NULL;
517
518 ep = container_of(usbep, struct udc_ep, ep);
519
520 VDBG(ep->dev, "udc_alloc_req(): ep%d\n", ep->num);
521 req = kzalloc(sizeof(struct udc_request), gfp);
522 if (!req)
523 return NULL;
524
525 req->req.dma = DMA_DONT_USE;
526 INIT_LIST_HEAD(&req->queue);
527
528 if (ep->dma) {
529 /* ep0 in requests are allocated from data pool here */
530 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
531 &req->td_phys);
532 if (!dma_desc) {
533 kfree(req);
534 return NULL;
535 }
536
537 VDBG(ep->dev, "udc_alloc_req: req = %p dma_desc = %p, "
538 "td_phys = %lx\n",
539 req, dma_desc,
540 (unsigned long)req->td_phys);
541 /* prevent from using desc. - set HOST BUSY */
542 dma_desc->status = AMD_ADDBITS(dma_desc->status,
543 UDC_DMA_STP_STS_BS_HOST_BUSY,
544 UDC_DMA_STP_STS_BS);
551509d2 545 dma_desc->bufptr = cpu_to_le32(DMA_DONT_USE);
55d402d8
TD		 546 req->td_data = dma_desc;
547 req->td_data_last = NULL;
548 req->chain_len = 1;
549 }
550
551 return &req->req;
552}
553
554/* Frees request packet, called by gadget driver */
555static void
556udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq)
557{
558 struct udc_ep *ep;
559 struct udc_request *req;
560
561 if (!usbep || !usbreq)
562 return;
563
564 ep = container_of(usbep, struct udc_ep, ep);
565 req = container_of(usbreq, struct udc_request, req);
566 VDBG(ep->dev, "free_req req=%p\n", req);
567 BUG_ON(!list_empty(&req->queue));
568 if (req->td_data) {
569 VDBG(ep->dev, "req->td_data=%p\n", req->td_data);
570
571 /* free dma chain if created */
170b778f 572 if (req->chain_len > 1)
55d402d8 573 udc_free_dma_chain(ep->dev, req);
55d402d8
TD		 574
575 pci_pool_free(ep->dev->data_requests, req->td_data,
576 req->td_phys);
577 }
578 kfree(req);
579}
580
581/* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
582static void udc_init_bna_dummy(struct udc_request *req)
583{
584 if (req) {
585 /* set last bit */
586 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
587 /* set next pointer to itself */
588 req->td_data->next = req->td_phys;
589 /* set HOST BUSY */
590 req->td_data->status
591 = AMD_ADDBITS(req->td_data->status,
592 UDC_DMA_STP_STS_BS_DMA_DONE,
593 UDC_DMA_STP_STS_BS);
594#ifdef UDC_VERBOSE
595 pr_debug("bna desc = %p, sts = %08x\n",
596 req->td_data, req->td_data->status);
597#endif
598 }
599}
600
601/* Allocate BNA dummy descriptor */
602static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep)
603{
604 struct udc_request *req = NULL;
605 struct usb_request *_req = NULL;
606
607 /* alloc the dummy request */
608 _req = udc_alloc_request(&ep->ep, GFP_ATOMIC);
609 if (_req) {
610 req = container_of(_req, struct udc_request, req);
611 ep->bna_dummy_req = req;
612 udc_init_bna_dummy(req);
613 }
614 return req;
615}
616
617/* Write data to TX fifo for IN packets */
618static void
619udc_txfifo_write(struct udc_ep *ep, struct usb_request *req)
620{
621 u8 *req_buf;
622 u32 *buf;
623 int i, j;
624 unsigned bytes = 0;
625 unsigned remaining = 0;
626
627 if (!req || !ep)
628 return;
629
630 req_buf = req->buf + req->actual;
631 prefetch(req_buf);
632 remaining = req->length - req->actual;
633
634 buf = (u32 *) req_buf;
635
636 bytes = ep->ep.maxpacket;
637 if (bytes > remaining)
638 bytes = remaining;
639
640 /* dwords first */
170b778f 641 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
55d402d8 642 writel(*(buf + i), ep->txfifo);
55d402d8
TD		 643
644 /* remaining bytes must be written by byte access */
645 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
646 writeb((u8)(*(buf + i) >> (j << UDC_BITS_PER_BYTE_SHIFT)),
647 ep->txfifo);
648 }
649
650 /* dummy write confirm */
651 writel(0, &ep->regs->confirm);
652}
653
654/* Read dwords from RX fifo for OUT transfers */
655static int udc_rxfifo_read_dwords(struct udc *dev, u32 *buf, int dwords)
656{
657 int i;
658
659 VDBG(dev, "udc_read_dwords(): %d dwords\n", dwords);
660
170b778f 661 for (i = 0; i < dwords; i++)
55d402d8 662 *(buf + i) = readl(dev->rxfifo);
55d402d8
TD		 663 return 0;
664}
665
666/* Read bytes from RX fifo for OUT transfers */
667static int udc_rxfifo_read_bytes(struct udc *dev, u8 *buf, int bytes)
668{
669 int i, j;
670 u32 tmp;
671
672 VDBG(dev, "udc_read_bytes(): %d bytes\n", bytes);
673
674 /* dwords first */
170b778f 675 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
55d402d8 676 *((u32 *)(buf + (i<<2))) = readl(dev->rxfifo);
55d402d8
TD		 677
678 /* remaining bytes must be read by byte access */
679 if (bytes % UDC_DWORD_BYTES) {
680 tmp = readl(dev->rxfifo);
681 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
682 *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK);
683 tmp = tmp >> UDC_BITS_PER_BYTE;
684 }
685 }
686
687 return 0;
688}
689
690/* Read data from RX fifo for OUT transfers */
691static int
692udc_rxfifo_read(struct udc_ep *ep, struct udc_request *req)
693{
694 u8 *buf;
695 unsigned buf_space;
696 unsigned bytes = 0;
697 unsigned finished = 0;
698
699 /* received number bytes */
700 bytes = readl(&ep->regs->sts);
701 bytes = AMD_GETBITS(bytes, UDC_EPSTS_RX_PKT_SIZE);
702
703 buf_space = req->req.length - req->req.actual;
704 buf = req->req.buf + req->req.actual;
705 if (bytes > buf_space) {
706 if ((buf_space % ep->ep.maxpacket) != 0) {
707 DBG(ep->dev,
708 "%s: rx %d bytes, rx-buf space = %d bytesn\n",
709 ep->ep.name, bytes, buf_space);
710 req->req.status = -EOVERFLOW;
711 }
712 bytes = buf_space;
713 }
714 req->req.actual += bytes;
715
716 /* last packet ? */
717 if (((bytes % ep->ep.maxpacket) != 0) || (!bytes)
718 || ((req->req.actual == req->req.length) && !req->req.zero))
719 finished = 1;
720
721 /* read rx fifo bytes */
722 VDBG(ep->dev, "ep %s: rxfifo read %d bytes\n", ep->ep.name, bytes);
723 udc_rxfifo_read_bytes(ep->dev, buf, bytes);
724
725 return finished;
726}
727
728/* create/re-init a DMA descriptor or a DMA descriptor chain */
729static int prep_dma(struct udc_ep *ep, struct udc_request *req, gfp_t gfp)
730{
731 int retval = 0;
732 u32 tmp;
733
734 VDBG(ep->dev, "prep_dma\n");
735 VDBG(ep->dev, "prep_dma ep%d req->td_data=%p\n",
736 ep->num, req->td_data);
737
738 /* set buffer pointer */
739 req->td_data->bufptr = req->req.dma;
740
741 /* set last bit */
742 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
743
744 /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
745 if (use_dma_ppb) {
746
747 retval = udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
748 if (retval != 0) {
749 if (retval == -ENOMEM)
750 DBG(ep->dev, "Out of DMA memory\n");
751 return retval;
752 }
753 if (ep->in) {
754 if (req->req.length == ep->ep.maxpacket) {
755 /* write tx bytes */
756 req->td_data->status =
757 AMD_ADDBITS(req->td_data->status,
758 ep->ep.maxpacket,
759 UDC_DMA_IN_STS_TXBYTES);
760
761 }
762 }
763
764 }
765
766 if (ep->in) {
767 VDBG(ep->dev, "IN: use_dma_ppb=%d req->req.len=%d "
768 "maxpacket=%d ep%d\n",
769 use_dma_ppb, req->req.length,
770 ep->ep.maxpacket, ep->num);
771 /*
772 * if bytes < max packet then tx bytes must
773 * be written in packet per buffer mode
774 */
775 if (!use_dma_ppb || req->req.length < ep->ep.maxpacket
776 || ep->num == UDC_EP0OUT_IX
777 || ep->num == UDC_EP0IN_IX) {
778 /* write tx bytes */
779 req->td_data->status =
780 AMD_ADDBITS(req->td_data->status,
781 req->req.length,
782 UDC_DMA_IN_STS_TXBYTES);
783 /* reset frame num */
784 req->td_data->status =
785 AMD_ADDBITS(req->td_data->status,
786 0,
787 UDC_DMA_IN_STS_FRAMENUM);
788 }
789 /* set HOST BUSY */
790 req->td_data->status =
791 AMD_ADDBITS(req->td_data->status,
792 UDC_DMA_STP_STS_BS_HOST_BUSY,
793 UDC_DMA_STP_STS_BS);
794 } else {
795 VDBG(ep->dev, "OUT set host ready\n");
796 /* set HOST READY */
797 req->td_data->status =
798 AMD_ADDBITS(req->td_data->status,
799 UDC_DMA_STP_STS_BS_HOST_READY,
800 UDC_DMA_STP_STS_BS);
801
802
803 /* clear NAK by writing CNAK */
804 if (ep->naking) {
805 tmp = readl(&ep->regs->ctl);
806 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
807 writel(tmp, &ep->regs->ctl);
808 ep->naking = 0;
809 UDC_QUEUE_CNAK(ep, ep->num);
810 }
811
812 }
813
814 return retval;
815}
816
817/* Completes request packet ... caller MUST hold lock */
818static void
819complete_req(struct udc_ep *ep, struct udc_request *req, int sts)
820__releases(ep->dev->lock)
821__acquires(ep->dev->lock)
822{
823 struct udc *dev;
824 unsigned halted;
825
826 VDBG(ep->dev, "complete_req(): ep%d\n", ep->num);
827
828 dev = ep->dev;
829 /* unmap DMA */
830 if (req->dma_mapping) {
831 if (ep->in)
832 pci_unmap_single(dev->pdev,
833 req->req.dma,
834 req->req.length,
835 PCI_DMA_TODEVICE);
836 else
837 pci_unmap_single(dev->pdev,
838 req->req.dma,
839 req->req.length,
840 PCI_DMA_FROMDEVICE);
841 req->dma_mapping = 0;
842 req->req.dma = DMA_DONT_USE;
843 }
844
845 halted = ep->halted;
846 ep->halted = 1;
847
848 /* set new status if pending */
849 if (req->req.status == -EINPROGRESS)
850 req->req.status = sts;
851
852 /* remove from ep queue */
853 list_del_init(&req->queue);
854
855 VDBG(ep->dev, "req %p => complete %d bytes at %s with sts %d\n",
856 &req->req, req->req.length, ep->ep.name, sts);
857
858 spin_unlock(&dev->lock);
859 req->req.complete(&ep->ep, &req->req);
860 spin_lock(&dev->lock);
861 ep->halted = halted;
862}
863
864/* frees pci pool descriptors of a DMA chain */
865static int udc_free_dma_chain(struct udc *dev, struct udc_request *req)
866{
867
868 int ret_val = 0;
869 struct udc_data_dma *td;
870 struct udc_data_dma *td_last = NULL;
871 unsigned int i;
872
873 DBG(dev, "free chain req = %p\n", req);
874
875 /* do not free first desc., will be done by free for request */
876 td_last = req->td_data;
877 td = phys_to_virt(td_last->next);
878
879 for (i = 1; i < req->chain_len; i++) {
880
881 pci_pool_free(dev->data_requests, td,
882 (dma_addr_t) td_last->next);
883 td_last = td;
884 td = phys_to_virt(td_last->next);
885 }
886
887 return ret_val;
888}
889
890/* Iterates to the end of a DMA chain and returns last descriptor */
891static struct udc_data_dma *udc_get_last_dma_desc(struct udc_request *req)
892{
893 struct udc_data_dma *td;
894
895 td = req->td_data;
170b778f 896 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L)))
55d402d8 897 td = phys_to_virt(td->next);
55d402d8
TD		 898
899 return td;
900
901}
902
903/* Iterates to the end of a DMA chain and counts bytes received */
904static u32 udc_get_ppbdu_rxbytes(struct udc_request *req)
905{
906 struct udc_data_dma *td;
907 u32 count;
908
909 td = req->td_data;
910 /* received number bytes */
911 count = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES);
912
913 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
914 td = phys_to_virt(td->next);
915 /* received number bytes */
916 if (td) {
917 count += AMD_GETBITS(td->status,
918 UDC_DMA_OUT_STS_RXBYTES);
919 }
920 }
921
922 return count;
923
924}
925
926/* Creates or re-inits a DMA chain */
927static int udc_create_dma_chain(
928 struct udc_ep *ep,
929 struct udc_request *req,
930 unsigned long buf_len, gfp_t gfp_flags
931)
932{
933 unsigned long bytes = req->req.length;
934 unsigned int i;
935 dma_addr_t dma_addr;
936 struct udc_data_dma *td = NULL;
937 struct udc_data_dma *last = NULL;
938 unsigned long txbytes;
939 unsigned create_new_chain = 0;
940 unsigned len;
941
942 VDBG(ep->dev, "udc_create_dma_chain: bytes=%ld buf_len=%ld\n",
943 bytes, buf_len);
944 dma_addr = DMA_DONT_USE;
945
946 /* unset L bit in first desc for OUT */
170b778f 947 if (!ep->in)
55d402d8 948 req->td_data->status &= AMD_CLEAR_BIT(UDC_DMA_IN_STS_L);
55d402d8
TD		 949
950 /* alloc only new desc's if not already available */
951 len = req->req.length / ep->ep.maxpacket;
170b778f 952 if (req->req.length % ep->ep.maxpacket)
55d402d8 953 len++;
55d402d8
TD		 954
955 if (len > req->chain_len) {
956 /* shorter chain already allocated before */
170b778f 957 if (req->chain_len > 1)
55d402d8 958 udc_free_dma_chain(ep->dev, req);
55d402d8
TD		 959 req->chain_len = len;
960 create_new_chain = 1;
961 }
962
963 td = req->td_data;
964 /* gen. required number of descriptors and buffers */
965 for (i = buf_len; i < bytes; i += buf_len) {
966 /* create or determine next desc. */
967 if (create_new_chain) {
968
969 td = pci_pool_alloc(ep->dev->data_requests,
970 gfp_flags, &dma_addr);
971 if (!td)
972 return -ENOMEM;
973
974 td->status = 0;
975 } else if (i == buf_len) {
976 /* first td */
977 td = (struct udc_data_dma *) phys_to_virt(
978 req->td_data->next);
979 td->status = 0;
980 } else {
981 td = (struct udc_data_dma *) phys_to_virt(last->next);
982 td->status = 0;
983 }
984
985
986 if (td)
987 td->bufptr = req->req.dma + i; /* assign buffer */
988 else
989 break;
990
991 /* short packet ? */
992 if ((bytes - i) >= buf_len) {
993 txbytes = buf_len;
994 } else {
995 /* short packet */
996 txbytes = bytes - i;
997 }
998
999 /* link td and assign tx bytes */
1000 if (i == buf_len) {
170b778f 1001 if (create_new_chain)
55d402d8 1002 req->td_data->next = dma_addr;
170b778f
CR		 1003 /*
1004 else
1005 req->td_data->next = virt_to_phys(td);
1006 */
55d402d8
TD		 1007 /* write tx bytes */
1008 if (ep->in) {
1009 /* first desc */
1010 req->td_data->status =
1011 AMD_ADDBITS(req->td_data->status,
1012 ep->ep.maxpacket,
1013 UDC_DMA_IN_STS_TXBYTES);
1014 /* second desc */
1015 td->status = AMD_ADDBITS(td->status,
1016 txbytes,
1017 UDC_DMA_IN_STS_TXBYTES);
1018 }
1019 } else {
170b778f 1020 if (create_new_chain)
55d402d8 1021 last->next = dma_addr;
170b778f
CR		 1022 /*
1023 else
1024 last->next = virt_to_phys(td);
1025 */
55d402d8
TD		 1026 if (ep->in) {
1027 /* write tx bytes */
1028 td->status = AMD_ADDBITS(td->status,
1029 txbytes,
1030 UDC_DMA_IN_STS_TXBYTES);
1031 }
1032 }
1033 last = td;
1034 }
1035 /* set last bit */
1036 if (td) {
1037 td->status |= AMD_BIT(UDC_DMA_IN_STS_L);
1038 /* last desc. points to itself */
1039 req->td_data_last = td;
1040 }
1041
1042 return 0;
1043}
1044
1045/* Enabling RX DMA */
1046static void udc_set_rde(struct udc *dev)
1047{
1048 u32 tmp;
1049
1050 VDBG(dev, "udc_set_rde()\n");
1051 /* stop RDE timer */
1052 if (timer_pending(&udc_timer)) {
1053 set_rde = 0;
1054 mod_timer(&udc_timer, jiffies - 1);
1055 }
1056 /* set RDE */
1057 tmp = readl(&dev->regs->ctl);
1058 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1059 writel(tmp, &dev->regs->ctl);
1060}
1061
1062/* Queues a request packet, called by gadget driver */
1063static int
1064udc_queue(struct usb_ep *usbep, struct usb_request *usbreq, gfp_t gfp)
1065{
1066 int retval = 0;
1067 u8 open_rxfifo = 0;
1068 unsigned long iflags;
1069 struct udc_ep *ep;
1070 struct udc_request *req;
1071 struct udc *dev;
1072 u32 tmp;
1073
1074 /* check the inputs */
1075 req = container_of(usbreq, struct udc_request, req);
1076
1077 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf
1078 || !list_empty(&req->queue))
1079 return -EINVAL;
1080
1081 ep = container_of(usbep, struct udc_ep, ep);
1082 if (!ep->desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1083 return -EINVAL;
1084
1085 VDBG(ep->dev, "udc_queue(): ep%d-in=%d\n", ep->num, ep->in);
1086 dev = ep->dev;
1087
1088 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1089 return -ESHUTDOWN;
1090
1091 /* map dma (usually done before) */
1092 if (ep->dma && usbreq->length != 0
1093 && (usbreq->dma == DMA_DONT_USE || usbreq->dma == 0)) {
1094 VDBG(dev, "DMA map req %p\n", req);
1095 if (ep->in)
1096 usbreq->dma = pci_map_single(dev->pdev,
1097 usbreq->buf,
1098 usbreq->length,
1099 PCI_DMA_TODEVICE);
1100 else
1101 usbreq->dma = pci_map_single(dev->pdev,
1102 usbreq->buf,
1103 usbreq->length,
1104 PCI_DMA_FROMDEVICE);
1105 req->dma_mapping = 1;
1106 }
1107
1108 VDBG(dev, "%s queue req %p, len %d req->td_data=%p buf %p\n",
1109 usbep->name, usbreq, usbreq->length,
1110 req->td_data, usbreq->buf);
1111
1112 spin_lock_irqsave(&dev->lock, iflags);
1113 usbreq->actual = 0;
1114 usbreq->status = -EINPROGRESS;
1115 req->dma_done = 0;
1116
1117 /* on empty queue just do first transfer */
1118 if (list_empty(&ep->queue)) {
1119 /* zlp */
1120 if (usbreq->length == 0) {
1121 /* IN zlp's are handled by hardware */
1122 complete_req(ep, req, 0);
1123 VDBG(dev, "%s: zlp\n", ep->ep.name);
1124 /*
1125 * if set_config or set_intf is waiting for ack by zlp
1126 * then set CSR_DONE
1127 */
1128 if (dev->set_cfg_not_acked) {
1129 tmp = readl(&dev->regs->ctl);
1130 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE);
1131 writel(tmp, &dev->regs->ctl);
1132 dev->set_cfg_not_acked = 0;
1133 }
1134 /* setup command is ACK'ed now by zlp */
1135 if (dev->waiting_zlp_ack_ep0in) {
1136 /* clear NAK by writing CNAK in EP0_IN */
1137 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1138 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1139 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1140 dev->ep[UDC_EP0IN_IX].naking = 0;
1141 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX],
1142 UDC_EP0IN_IX);
1143 dev->waiting_zlp_ack_ep0in = 0;
1144 }
1145 goto finished;
1146 }
1147 if (ep->dma) {
1148 retval = prep_dma(ep, req, gfp);
1149 if (retval != 0)
1150 goto finished;
1151 /* write desc pointer to enable DMA */
1152 if (ep->in) {
1153 /* set HOST READY */
1154 req->td_data->status =
1155 AMD_ADDBITS(req->td_data->status,
1156 UDC_DMA_IN_STS_BS_HOST_READY,
1157 UDC_DMA_IN_STS_BS);
1158 }
1159
1160 /* disabled rx dma while descriptor update */
1161 if (!ep->in) {
1162 /* stop RDE timer */
1163 if (timer_pending(&udc_timer)) {
1164 set_rde = 0;
1165 mod_timer(&udc_timer, jiffies - 1);
1166 }
1167 /* clear RDE */
1168 tmp = readl(&dev->regs->ctl);
1169 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1170 writel(tmp, &dev->regs->ctl);
1171 open_rxfifo = 1;
1172
1173 /*
1174 * if BNA occurred then let BNA dummy desc.
1175 * point to current desc.
1176 */
1177 if (ep->bna_occurred) {
1178 VDBG(dev, "copy to BNA dummy desc.\n");
1179 memcpy(ep->bna_dummy_req->td_data,
1180 req->td_data,
1181 sizeof(struct udc_data_dma));
1182 }
1183 }
1184 /* write desc pointer */
1185 writel(req->td_phys, &ep->regs->desptr);
1186
1187 /* clear NAK by writing CNAK */
1188 if (ep->naking) {
1189 tmp = readl(&ep->regs->ctl);
1190 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1191 writel(tmp, &ep->regs->ctl);
1192 ep->naking = 0;
1193 UDC_QUEUE_CNAK(ep, ep->num);
1194 }
1195
1196 if (ep->in) {
1197 /* enable ep irq */
1198 tmp = readl(&dev->regs->ep_irqmsk);
1199 tmp &= AMD_UNMASK_BIT(ep->num);
1200 writel(tmp, &dev->regs->ep_irqmsk);
1201 }
c5deb832
TD		 1202 } else if (ep->in) {
1203 /* enable ep irq */
1204 tmp = readl(&dev->regs->ep_irqmsk);
1205 tmp &= AMD_UNMASK_BIT(ep->num);
1206 writel(tmp, &dev->regs->ep_irqmsk);
1207 }
55d402d8
TD		 1208
1209 } else if (ep->dma) {
1210
1211 /*
1212 * prep_dma not used for OUT ep's, this is not possible
1213 * for PPB modes, because of chain creation reasons
1214 */
1215 if (ep->in) {
1216 retval = prep_dma(ep, req, gfp);
1217 if (retval != 0)
1218 goto finished;
1219 }
1220 }
1221 VDBG(dev, "list_add\n");
1222 /* add request to ep queue */
1223 if (req) {
1224
1225 list_add_tail(&req->queue, &ep->queue);
1226
1227 /* open rxfifo if out data queued */
1228 if (open_rxfifo) {
1229 /* enable DMA */
1230 req->dma_going = 1;
1231 udc_set_rde(dev);
1232 if (ep->num != UDC_EP0OUT_IX)
1233 dev->data_ep_queued = 1;
1234 }
1235 /* stop OUT naking */
1236 if (!ep->in) {
1237 if (!use_dma && udc_rxfifo_pending) {
fec8de3a 1238 DBG(dev, "udc_queue(): pending bytes in "
55d402d8
TD		 1239 "rxfifo after nyet\n");
1240 /*
1241 * read pending bytes afer nyet:
1242 * referring to isr
1243 */
1244 if (udc_rxfifo_read(ep, req)) {
1245 /* finish */
1246 complete_req(ep, req, 0);
1247 }
1248 udc_rxfifo_pending = 0;
1249
1250 }
1251 }
1252 }
1253
1254finished:
1255 spin_unlock_irqrestore(&dev->lock, iflags);
1256 return retval;
1257}
1258
1259/* Empty request queue of an endpoint; caller holds spinlock */
1260static void empty_req_queue(struct udc_ep *ep)
1261{
1262 struct udc_request *req;
1263
1264 ep->halted = 1;
1265 while (!list_empty(&ep->queue)) {
1266 req = list_entry(ep->queue.next,
1267 struct udc_request,
1268 queue);
1269 complete_req(ep, req, -ESHUTDOWN);
1270 }
1271}
1272
1273/* Dequeues a request packet, called by gadget driver */
1274static int udc_dequeue(struct usb_ep *usbep, struct usb_request *usbreq)
1275{
1276 struct udc_ep *ep;
1277 struct udc_request *req;
1278 unsigned halted;
1279 unsigned long iflags;
1280
1281 ep = container_of(usbep, struct udc_ep, ep);
1282 if (!usbep || !usbreq || (!ep->desc && (ep->num != 0
1283 && ep->num != UDC_EP0OUT_IX)))
1284 return -EINVAL;
1285
1286 req = container_of(usbreq, struct udc_request, req);
1287
1288 spin_lock_irqsave(&ep->dev->lock, iflags);
1289 halted = ep->halted;
1290 ep->halted = 1;
1291 /* request in processing or next one */
1292 if (ep->queue.next == &req->queue) {
1293 if (ep->dma && req->dma_going) {
1294 if (ep->in)
1295 ep->cancel_transfer = 1;
1296 else {
1297 u32 tmp;
1298 u32 dma_sts;
1299 /* stop potential receive DMA */
1300 tmp = readl(&udc->regs->ctl);
1301 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE),
1302 &udc->regs->ctl);
1303 /*
1304 * Cancel transfer later in ISR
1305 * if descriptor was touched.
1306 */
1307 dma_sts = AMD_GETBITS(req->td_data->status,
1308 UDC_DMA_OUT_STS_BS);
1309 if (dma_sts != UDC_DMA_OUT_STS_BS_HOST_READY)
1310 ep->cancel_transfer = 1;
1311 else {
1312 udc_init_bna_dummy(ep->req);
1313 writel(ep->bna_dummy_req->td_phys,
1314 &ep->regs->desptr);
1315 }
1316 writel(tmp, &udc->regs->ctl);
1317 }
1318 }
1319 }
1320 complete_req(ep, req, -ECONNRESET);
1321 ep->halted = halted;
1322
1323 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1324 return 0;
1325}
1326
1327/* Halt or clear halt of endpoint */
1328static int
1329udc_set_halt(struct usb_ep *usbep, int halt)
1330{
1331 struct udc_ep *ep;
1332 u32 tmp;
1333 unsigned long iflags;
1334 int retval = 0;
1335
1336 if (!usbep)
1337 return -EINVAL;
1338
1339 pr_debug("set_halt %s: halt=%d\n", usbep->name, halt);
1340
1341 ep = container_of(usbep, struct udc_ep, ep);
1342 if (!ep->desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1343 return -EINVAL;
1344 if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN)
1345 return -ESHUTDOWN;
1346
1347 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1348 /* halt or clear halt */
1349 if (halt) {
1350 if (ep->num == 0)
1351 ep->dev->stall_ep0in = 1;
1352 else {
1353 /*
1354 * set STALL
1355 * rxfifo empty not taken into acount
1356 */
1357 tmp = readl(&ep->regs->ctl);
1358 tmp |= AMD_BIT(UDC_EPCTL_S);
1359 writel(tmp, &ep->regs->ctl);
1360 ep->halted = 1;
1361
1362 /* setup poll timer */
1363 if (!timer_pending(&udc_pollstall_timer)) {
1364 udc_pollstall_timer.expires = jiffies +
1365 HZ * UDC_POLLSTALL_TIMER_USECONDS
1366 / (1000 * 1000);
1367 if (!stop_pollstall_timer) {
1368 DBG(ep->dev, "start polltimer\n");
1369 add_timer(&udc_pollstall_timer);
1370 }
1371 }
1372 }
1373 } else {
1374 /* ep is halted by set_halt() before */
1375 if (ep->halted) {
1376 tmp = readl(&ep->regs->ctl);
1377 /* clear stall bit */
1378 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
1379 /* clear NAK by writing CNAK */
1380 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1381 writel(tmp, &ep->regs->ctl);
1382 ep->halted = 0;
1383 UDC_QUEUE_CNAK(ep, ep->num);
1384 }
1385 }
1386 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1387 return retval;
1388}
1389
1390/* gadget interface */
1391static const struct usb_ep_ops udc_ep_ops = {
1392 .enable = udc_ep_enable,
1393 .disable = udc_ep_disable,
1394
1395 .alloc_request = udc_alloc_request,
1396 .free_request = udc_free_request,
1397
1398 .queue = udc_queue,
1399 .dequeue = udc_dequeue,
1400
1401 .set_halt = udc_set_halt,
1402 /* fifo ops not implemented */
1403};
1404
1405/*-------------------------------------------------------------------------*/
1406
1407/* Get frame counter (not implemented) */
1408static int udc_get_frame(struct usb_gadget *gadget)
1409{
1410 return -EOPNOTSUPP;
1411}
1412
1413/* Remote wakeup gadget interface */
1414static int udc_wakeup(struct usb_gadget *gadget)
1415{
1416 struct udc *dev;
1417
1418 if (!gadget)
1419 return -EINVAL;
1420 dev = container_of(gadget, struct udc, gadget);
1421 udc_remote_wakeup(dev);
1422
1423 return 0;
1424}
1425
0f91349b
SAS		 1426static int amd5536_start(struct usb_gadget_driver *driver,
1427 int (*bind)(struct usb_gadget *));
1428static int amd5536_stop(struct usb_gadget_driver *driver);
55d402d8
TD		 1429/* gadget operations */
1430static const struct usb_gadget_ops udc_ops = {
1431 .wakeup = udc_wakeup,
1432 .get_frame = udc_get_frame,
0f91349b
SAS		 1433 .start = amd5536_start,
1434 .stop = amd5536_stop,
55d402d8
TD		 1435};
1436
1437/* Setups endpoint parameters, adds endpoints to linked list */
1438static void make_ep_lists(struct udc *dev)
1439{
1440 /* make gadget ep lists */
1441 INIT_LIST_HEAD(&dev->gadget.ep_list);
1442 list_add_tail(&dev->ep[UDC_EPIN_STATUS_IX].ep.ep_list,
1443 &dev->gadget.ep_list);
1444 list_add_tail(&dev->ep[UDC_EPIN_IX].ep.ep_list,
1445 &dev->gadget.ep_list);
1446 list_add_tail(&dev->ep[UDC_EPOUT_IX].ep.ep_list,
1447 &dev->gadget.ep_list);
1448
1449 /* fifo config */
1450 dev->ep[UDC_EPIN_STATUS_IX].fifo_depth = UDC_EPIN_SMALLINT_BUFF_SIZE;
1451 if (dev->gadget.speed == USB_SPEED_FULL)
1452 dev->ep[UDC_EPIN_IX].fifo_depth = UDC_FS_EPIN_BUFF_SIZE;
1453 else if (dev->gadget.speed == USB_SPEED_HIGH)
1454 dev->ep[UDC_EPIN_IX].fifo_depth = hs_tx_buf;
1455 dev->ep[UDC_EPOUT_IX].fifo_depth = UDC_RXFIFO_SIZE;
1456}
1457
1458/* init registers at driver load time */
1459static int startup_registers(struct udc *dev)
1460{
1461 u32 tmp;
1462
1463 /* init controller by soft reset */
1464 udc_soft_reset(dev);
1465
1466 /* mask not needed interrupts */
1467 udc_mask_unused_interrupts(dev);
1468
1469 /* put into initial config */
1470 udc_basic_init(dev);
1471 /* link up all endpoints */
1472 udc_setup_endpoints(dev);
1473
1474 /* program speed */
1475 tmp = readl(&dev->regs->cfg);
170b778f 1476 if (use_fullspeed)
55d402d8 1477 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
170b778f 1478 else
55d402d8 1479 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD);
55d402d8
TD		 1480 writel(tmp, &dev->regs->cfg);
1481
1482 return 0;
1483}
1484
1485/* Inits UDC context */
1486static void udc_basic_init(struct udc *dev)
1487{
1488 u32 tmp;
1489
1490 DBG(dev, "udc_basic_init()\n");
1491
1492 dev->gadget.speed = USB_SPEED_UNKNOWN;
1493
1494 /* stop RDE timer */
1495 if (timer_pending(&udc_timer)) {
1496 set_rde = 0;
1497 mod_timer(&udc_timer, jiffies - 1);
1498 }
1499 /* stop poll stall timer */
170b778f 1500 if (timer_pending(&udc_pollstall_timer))
55d402d8 1501 mod_timer(&udc_pollstall_timer, jiffies - 1);
55d402d8
TD		 1502 /* disable DMA */
1503 tmp = readl(&dev->regs->ctl);
1504 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1505 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE);
1506 writel(tmp, &dev->regs->ctl);
1507
1508 /* enable dynamic CSR programming */
1509 tmp = readl(&dev->regs->cfg);
1510 tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG);
1511 /* set self powered */
1512 tmp |= AMD_BIT(UDC_DEVCFG_SP);
1513 /* set remote wakeupable */
1514 tmp |= AMD_BIT(UDC_DEVCFG_RWKP);
1515 writel(tmp, &dev->regs->cfg);
1516
1517 make_ep_lists(dev);
1518
1519 dev->data_ep_enabled = 0;
1520 dev->data_ep_queued = 0;
1521}
1522
1523/* Sets initial endpoint parameters */
1524static void udc_setup_endpoints(struct udc *dev)
1525{
1526 struct udc_ep *ep;
1527 u32 tmp;
1528 u32 reg;
1529
1530 DBG(dev, "udc_setup_endpoints()\n");
1531
1532 /* read enum speed */
1533 tmp = readl(&dev->regs->sts);
1534 tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED);
170b778f 1535 if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH)
55d402d8 1536 dev->gadget.speed = USB_SPEED_HIGH;
170b778f 1537 else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL)
55d402d8 1538 dev->gadget.speed = USB_SPEED_FULL;
55d402d8
TD		 1539
1540 /* set basic ep parameters */
1541 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1542 ep = &dev->ep[tmp];
1543 ep->dev = dev;
1544 ep->ep.name = ep_string[tmp];
1545 ep->num = tmp;
1546 /* txfifo size is calculated at enable time */
1547 ep->txfifo = dev->txfifo;
1548
1549 /* fifo size */
1550 if (tmp < UDC_EPIN_NUM) {
1551 ep->fifo_depth = UDC_TXFIFO_SIZE;
1552 ep->in = 1;
1553 } else {
1554 ep->fifo_depth = UDC_RXFIFO_SIZE;
1555 ep->in = 0;
1556
1557 }
1558 ep->regs = &dev->ep_regs[tmp];
1559 /*
1560 * ep will be reset only if ep was not enabled before to avoid
1561 * disabling ep interrupts when ENUM interrupt occurs but ep is
1562 * not enabled by gadget driver
1563 */
170b778f 1564 if (!ep->desc)
55d402d8 1565 ep_init(dev->regs, ep);
55d402d8
TD		 1566
1567 if (use_dma) {
1568 /*
1569 * ep->dma is not really used, just to indicate that
1570 * DMA is active: remove this
1571 * dma regs = dev control regs
1572 */
1573 ep->dma = &dev->regs->ctl;
1574
1575 /* nak OUT endpoints until enable - not for ep0 */
1576 if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX
1577 && tmp > UDC_EPIN_NUM) {
1578 /* set NAK */
1579 reg = readl(&dev->ep[tmp].regs->ctl);
1580 reg |= AMD_BIT(UDC_EPCTL_SNAK);
1581 writel(reg, &dev->ep[tmp].regs->ctl);
1582 dev->ep[tmp].naking = 1;
1583
1584 }
1585 }
1586 }
1587 /* EP0 max packet */
1588 if (dev->gadget.speed == USB_SPEED_FULL) {
1589 dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_FS_EP0IN_MAX_PKT_SIZE;
1590 dev->ep[UDC_EP0OUT_IX].ep.maxpacket =
1591 UDC_FS_EP0OUT_MAX_PKT_SIZE;
1592 } else if (dev->gadget.speed == USB_SPEED_HIGH) {
1593 dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
1594 dev->ep[UDC_EP0OUT_IX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
1595 }
1596
1597 /*
1598 * with suspend bug workaround, ep0 params for gadget driver
1599 * are set at gadget driver bind() call
1600 */
1601 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
1602 dev->ep[UDC_EP0IN_IX].halted = 0;
1603 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1604
1605 /* init cfg/alt/int */
1606 dev->cur_config = 0;
1607 dev->cur_intf = 0;
1608 dev->cur_alt = 0;
1609}
1610
1611/* Bringup after Connect event, initial bringup to be ready for ep0 events */
1612static void usb_connect(struct udc *dev)
1613{
1614
1615 dev_info(&dev->pdev->dev, "USB Connect\n");
1616
1617 dev->connected = 1;
1618
1619 /* put into initial config */
1620 udc_basic_init(dev);
1621
1622 /* enable device setup interrupts */
1623 udc_enable_dev_setup_interrupts(dev);
1624}
1625
1626/*
1627 * Calls gadget with disconnect event and resets the UDC and makes
1628 * initial bringup to be ready for ep0 events
1629 */
1630static void usb_disconnect(struct udc *dev)
1631{
1632
1633 dev_info(&dev->pdev->dev, "USB Disconnect\n");
1634
1635 dev->connected = 0;
1636
1637 /* mask interrupts */
1638 udc_mask_unused_interrupts(dev);
1639
1640 /* REVISIT there doesn't seem to be a point to having this
1641 * talk to a tasklet ... do it directly, we already hold
1642 * the spinlock needed to process the disconnect.
1643 */
1644
1645 tasklet_schedule(&disconnect_tasklet);
1646}
1647
1648/* Tasklet for disconnect to be outside of interrupt context */
1649static void udc_tasklet_disconnect(unsigned long par)
1650{
1651 struct udc *dev = (struct udc *)(*((struct udc **) par));
1652 u32 tmp;
1653
1654 DBG(dev, "Tasklet disconnect\n");
1655 spin_lock_irq(&dev->lock);
1656
1657 if (dev->driver) {
1658 spin_unlock(&dev->lock);
1659 dev->driver->disconnect(&dev->gadget);
1660 spin_lock(&dev->lock);
1661
1662 /* empty queues */
170b778f 1663 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
55d402d8 1664 empty_req_queue(&dev->ep[tmp]);
55d402d8
TD		 1665
1666 }
1667
1668 /* disable ep0 */
1669 ep_init(dev->regs,
1670 &dev->ep[UDC_EP0IN_IX]);
1671
1672
1673 if (!soft_reset_occured) {
1674 /* init controller by soft reset */
1675 udc_soft_reset(dev);
1676 soft_reset_occured++;
1677 }
1678
1679 /* re-enable dev interrupts */
1680 udc_enable_dev_setup_interrupts(dev);
1681 /* back to full speed ? */
1682 if (use_fullspeed) {
1683 tmp = readl(&dev->regs->cfg);
1684 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1685 writel(tmp, &dev->regs->cfg);
1686 }
1687
1688 spin_unlock_irq(&dev->lock);
1689}
1690
1691/* Reset the UDC core */
1692static void udc_soft_reset(struct udc *dev)
1693{
1694 unsigned long flags;
1695
1696 DBG(dev, "Soft reset\n");
1697 /*
1698 * reset possible waiting interrupts, because int.
1699 * status is lost after soft reset,
1700 * ep int. status reset
1701 */
1702 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts);
1703 /* device int. status reset */
1704 writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts);
1705
1706 spin_lock_irqsave(&udc_irq_spinlock, flags);
1707 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
1708 readl(&dev->regs->cfg);
1709 spin_unlock_irqrestore(&udc_irq_spinlock, flags);
1710
1711}
1712
1713/* RDE timer callback to set RDE bit */
1714static void udc_timer_function(unsigned long v)
1715{
1716 u32 tmp;
1717
1718 spin_lock_irq(&udc_irq_spinlock);
1719
1720 if (set_rde > 0) {
1721 /*
1722 * open the fifo if fifo was filled on last timer call
1723 * conditionally
1724 */
1725 if (set_rde > 1) {
1726 /* set RDE to receive setup data */
1727 tmp = readl(&udc->regs->ctl);
1728 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1729 writel(tmp, &udc->regs->ctl);
1730 set_rde = -1;
1731 } else if (readl(&udc->regs->sts)
1732 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
1733 /*
1734 * if fifo empty setup polling, do not just
1735 * open the fifo
1736 */
1737 udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV;
170b778f 1738 if (!stop_timer)
55d402d8 1739 add_timer(&udc_timer);
55d402d8
TD		 1740 } else {
1741 /*
1742 * fifo contains data now, setup timer for opening
1743 * the fifo when timer expires to be able to receive
1744 * setup packets, when data packets gets queued by
1745 * gadget layer then timer will forced to expire with
1746 * set_rde=0 (RDE is set in udc_queue())
1747 */
1748 set_rde++;
1749 /* debug: lhadmot_timer_start = 221070 */
1750 udc_timer.expires = jiffies + HZ*UDC_RDE_TIMER_SECONDS;
170b778f 1751 if (!stop_timer)
55d402d8 1752 add_timer(&udc_timer);
55d402d8
TD		 1753 }
1754
1755 } else
1756 set_rde = -1; /* RDE was set by udc_queue() */
1757 spin_unlock_irq(&udc_irq_spinlock);
1758 if (stop_timer)
1759 complete(&on_exit);
1760
1761}
1762
1763/* Handle halt state, used in stall poll timer */
1764static void udc_handle_halt_state(struct udc_ep *ep)
1765{
1766 u32 tmp;
1767 /* set stall as long not halted */
1768 if (ep->halted == 1) {
1769 tmp = readl(&ep->regs->ctl);
1770 /* STALL cleared ? */
1771 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) {
1772 /*
1773 * FIXME: MSC spec requires that stall remains
1774 * even on receivng of CLEAR_FEATURE HALT. So
1775 * we would set STALL again here to be compliant.
1776 * But with current mass storage drivers this does
1777 * not work (would produce endless host retries).
1778 * So we clear halt on CLEAR_FEATURE.
1779 *
1780 DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1781 tmp |= AMD_BIT(UDC_EPCTL_S);
1782 writel(tmp, &ep->regs->ctl);*/
1783
1784 /* clear NAK by writing CNAK */
1785 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1786 writel(tmp, &ep->regs->ctl);
1787 ep->halted = 0;
1788 UDC_QUEUE_CNAK(ep, ep->num);
1789 }
1790 }
1791}
1792
1793/* Stall timer callback to poll S bit and set it again after */
1794static void udc_pollstall_timer_function(unsigned long v)
1795{
1796 struct udc_ep *ep;
1797 int halted = 0;
1798
1799 spin_lock_irq(&udc_stall_spinlock);
1800 /*
1801 * only one IN and OUT endpoints are handled
1802 * IN poll stall
1803 */
1804 ep = &udc->ep[UDC_EPIN_IX];
1805 udc_handle_halt_state(ep);
1806 if (ep->halted)
1807 halted = 1;
1808 /* OUT poll stall */
1809 ep = &udc->ep[UDC_EPOUT_IX];
1810 udc_handle_halt_state(ep);
1811 if (ep->halted)
1812 halted = 1;
1813
1814 /* setup timer again when still halted */
1815 if (!stop_pollstall_timer && halted) {
1816 udc_pollstall_timer.expires = jiffies +
1817 HZ * UDC_POLLSTALL_TIMER_USECONDS
1818 / (1000 * 1000);
1819 add_timer(&udc_pollstall_timer);
1820 }
1821 spin_unlock_irq(&udc_stall_spinlock);
1822
1823 if (stop_pollstall_timer)
1824 complete(&on_pollstall_exit);
1825}
1826
1827/* Inits endpoint 0 so that SETUP packets are processed */
1828static void activate_control_endpoints(struct udc *dev)
1829{
1830 u32 tmp;
1831
1832 DBG(dev, "activate_control_endpoints\n");
1833
1834 /* flush fifo */
1835 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1836 tmp |= AMD_BIT(UDC_EPCTL_F);
1837 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1838
1839 /* set ep0 directions */
1840 dev->ep[UDC_EP0IN_IX].in = 1;
1841 dev->ep[UDC_EP0OUT_IX].in = 0;
1842
1843 /* set buffer size (tx fifo entries) of EP0_IN */
1844 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1845 if (dev->gadget.speed == USB_SPEED_FULL)
1846 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE,
1847 UDC_EPIN_BUFF_SIZE);
1848 else if (dev->gadget.speed == USB_SPEED_HIGH)
1849 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE,
1850 UDC_EPIN_BUFF_SIZE);
1851 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1852
1853 /* set max packet size of EP0_IN */
1854 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1855 if (dev->gadget.speed == USB_SPEED_FULL)
1856 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE,
1857 UDC_EP_MAX_PKT_SIZE);
1858 else if (dev->gadget.speed == USB_SPEED_HIGH)
1859 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE,
1860 UDC_EP_MAX_PKT_SIZE);
1861 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1862
1863 /* set max packet size of EP0_OUT */
1864 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1865 if (dev->gadget.speed == USB_SPEED_FULL)
1866 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1867 UDC_EP_MAX_PKT_SIZE);
1868 else if (dev->gadget.speed == USB_SPEED_HIGH)
1869 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1870 UDC_EP_MAX_PKT_SIZE);
1871 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1872
1873 /* set max packet size of EP0 in UDC CSR */
1874 tmp = readl(&dev->csr->ne[0]);
1875 if (dev->gadget.speed == USB_SPEED_FULL)
1876 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1877 UDC_CSR_NE_MAX_PKT);
1878 else if (dev->gadget.speed == USB_SPEED_HIGH)
1879 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1880 UDC_CSR_NE_MAX_PKT);
1881 writel(tmp, &dev->csr->ne[0]);
1882
1883 if (use_dma) {
1884 dev->ep[UDC_EP0OUT_IX].td->status |=
1885 AMD_BIT(UDC_DMA_OUT_STS_L);
1886 /* write dma desc address */
1887 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma,
1888 &dev->ep[UDC_EP0OUT_IX].regs->subptr);
1889 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
1890 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
1891 /* stop RDE timer */
1892 if (timer_pending(&udc_timer)) {
1893 set_rde = 0;
1894 mod_timer(&udc_timer, jiffies - 1);
1895 }
1896 /* stop pollstall timer */
170b778f 1897 if (timer_pending(&udc_pollstall_timer))
55d402d8 1898 mod_timer(&udc_pollstall_timer, jiffies - 1);
55d402d8
TD		 1899 /* enable DMA */
1900 tmp = readl(&dev->regs->ctl);
1901 tmp |= AMD_BIT(UDC_DEVCTL_MODE)
1902 | AMD_BIT(UDC_DEVCTL_RDE)
1903 | AMD_BIT(UDC_DEVCTL_TDE);
170b778f 1904 if (use_dma_bufferfill_mode)
55d402d8 1905 tmp |= AMD_BIT(UDC_DEVCTL_BF);
170b778f 1906 else if (use_dma_ppb_du)
55d402d8 1907 tmp |= AMD_BIT(UDC_DEVCTL_DU);
55d402d8
TD		 1908 writel(tmp, &dev->regs->ctl);
1909 }
1910
1911 /* clear NAK by writing CNAK for EP0IN */
1912 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1913 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1914 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1915 dev->ep[UDC_EP0IN_IX].naking = 0;
1916 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
1917
1918 /* clear NAK by writing CNAK for EP0OUT */
1919 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
1920 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1921 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
1922 dev->ep[UDC_EP0OUT_IX].naking = 0;
1923 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
1924}
1925
1926/* Make endpoint 0 ready for control traffic */
1927static int setup_ep0(struct udc *dev)
1928{
1929 activate_control_endpoints(dev);
1930 /* enable ep0 interrupts */
1931 udc_enable_ep0_interrupts(dev);
1932 /* enable device setup interrupts */
1933 udc_enable_dev_setup_interrupts(dev);
1934
1935 return 0;
1936}
1937
1938/* Called by gadget driver to register itself */
0f91349b 1939static int amd5536_start(struct usb_gadget_driver *driver,
b0fca50f 1940 int (*bind)(struct usb_gadget *))
55d402d8
TD		 1941{
1942 struct udc *dev = udc;
1943 int retval;
1944 u32 tmp;
1945
b0fca50f 1946 if (!driver || !bind || !driver->setup
7177aed4 1947 || driver->max_speed < USB_SPEED_HIGH)
55d402d8
TD		 1948 return -EINVAL;
1949 if (!dev)
1950 return -ENODEV;
1951 if (dev->driver)
1952 return -EBUSY;
1953
1954 driver->driver.bus = NULL;
1955 dev->driver = driver;
1956 dev->gadget.dev.driver = &driver->driver;
1957
b0fca50f 1958 retval = bind(&dev->gadget);
55d402d8
TD		 1959
1960 /* Some gadget drivers use both ep0 directions.
1961 * NOTE: to gadget driver, ep0 is just one endpoint...
1962 */
1963 dev->ep[UDC_EP0OUT_IX].ep.driver_data =
1964 dev->ep[UDC_EP0IN_IX].ep.driver_data;
1965
1966 if (retval) {
1967 DBG(dev, "binding to %s returning %d\n",
1968 driver->driver.name, retval);
1969 dev->driver = NULL;
1970 dev->gadget.dev.driver = NULL;
1971 return retval;
1972 }
1973
1974 /* get ready for ep0 traffic */
1975 setup_ep0(dev);
1976
1977 /* clear SD */
1978 tmp = readl(&dev->regs->ctl);
1979 tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD);
1980 writel(tmp, &dev->regs->ctl);
1981
1982 usb_connect(dev);
1983
1984 return 0;
1985}
55d402d8
TD		 1986
1987/* shutdown requests and disconnect from gadget */
1988static void
1989shutdown(struct udc *dev, struct usb_gadget_driver *driver)
1990__releases(dev->lock)
1991__acquires(dev->lock)
1992{
1993 int tmp;
1994
55d402d8
TD		 1995 if (dev->gadget.speed != USB_SPEED_UNKNOWN) {
1996 spin_unlock(&dev->lock);
1997 driver->disconnect(&dev->gadget);
1998 spin_lock(&dev->lock);
1999 }
c5deb832
TD		 2000
2001 /* empty queues and init hardware */
2002 udc_basic_init(dev);
2003 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
2004 empty_req_queue(&dev->ep[tmp]);
2005
55d402d8
TD		 2006 udc_setup_endpoints(dev);
2007}
2008
2009/* Called by gadget driver to unregister itself */
0f91349b 2010static int amd5536_stop(struct usb_gadget_driver *driver)
55d402d8
TD		 2011{
2012 struct udc *dev = udc;
2013 unsigned long flags;
2014 u32 tmp;
2015
2016 if (!dev)
2017 return -ENODEV;
2018 if (!driver || driver != dev->driver || !driver->unbind)
2019 return -EINVAL;
2020
2021 spin_lock_irqsave(&dev->lock, flags);
2022 udc_mask_unused_interrupts(dev);
2023 shutdown(dev, driver);
2024 spin_unlock_irqrestore(&dev->lock, flags);
2025
2026 driver->unbind(&dev->gadget);
eb0be47d 2027 dev->gadget.dev.driver = NULL;
55d402d8
TD		 2028 dev->driver = NULL;
2029
2030 /* set SD */
2031 tmp = readl(&dev->regs->ctl);
2032 tmp |= AMD_BIT(UDC_DEVCTL_SD);
2033 writel(tmp, &dev->regs->ctl);
2034
2035
2036 DBG(dev, "%s: unregistered\n", driver->driver.name);
2037
2038 return 0;
2039}
55d402d8
TD		 2040
2041/* Clear pending NAK bits */
2042static void udc_process_cnak_queue(struct udc *dev)
2043{
2044 u32 tmp;
2045 u32 reg;
2046
2047 /* check epin's */
2048 DBG(dev, "CNAK pending queue processing\n");
2049 for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) {
2050 if (cnak_pending & (1 << tmp)) {
2051 DBG(dev, "CNAK pending for ep%d\n", tmp);
2052 /* clear NAK by writing CNAK */
2053 reg = readl(&dev->ep[tmp].regs->ctl);
2054 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2055 writel(reg, &dev->ep[tmp].regs->ctl);
2056 dev->ep[tmp].naking = 0;
2057 UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num);
2058 }
2059 }
2060 /* ... and ep0out */
2061 if (cnak_pending & (1 << UDC_EP0OUT_IX)) {
2062 DBG(dev, "CNAK pending for ep%d\n", UDC_EP0OUT_IX);
2063 /* clear NAK by writing CNAK */
2064 reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2065 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2066 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2067 dev->ep[UDC_EP0OUT_IX].naking = 0;
2068 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX],
2069 dev->ep[UDC_EP0OUT_IX].num);
2070 }
2071}
2072
2073/* Enabling RX DMA after setup packet */
2074static void udc_ep0_set_rde(struct udc *dev)
2075{
2076 if (use_dma) {
2077 /*
2078 * only enable RXDMA when no data endpoint enabled
2079 * or data is queued
2080 */
2081 if (!dev->data_ep_enabled || dev->data_ep_queued) {
2082 udc_set_rde(dev);
2083 } else {
2084 /*
2085 * setup timer for enabling RDE (to not enable
2086 * RXFIFO DMA for data endpoints to early)
2087 */
2088 if (set_rde != 0 && !timer_pending(&udc_timer)) {
2089 udc_timer.expires =
2090 jiffies + HZ/UDC_RDE_TIMER_DIV;
2091 set_rde = 1;
170b778f 2092 if (!stop_timer)
55d402d8 2093 add_timer(&udc_timer);
55d402d8
TD		 2094 }
2095 }
2096 }
2097}
2098
2099
2100/* Interrupt handler for data OUT traffic */
2101static irqreturn_t udc_data_out_isr(struct udc *dev, int ep_ix)
2102{
2103 irqreturn_t ret_val = IRQ_NONE;
2104 u32 tmp;
2105 struct udc_ep *ep;
2106 struct udc_request *req;
2107 unsigned int count;
2108 struct udc_data_dma *td = NULL;
2109 unsigned dma_done;
2110
2111 VDBG(dev, "ep%d irq\n", ep_ix);
2112 ep = &dev->ep[ep_ix];
2113
2114 tmp = readl(&ep->regs->sts);
2115 if (use_dma) {
2116 /* BNA event ? */
2117 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
5647a149 2118 DBG(dev, "BNA ep%dout occurred - DESPTR = %x\n",
55d402d8
TD		 2119 ep->num, readl(&ep->regs->desptr));
2120 /* clear BNA */
2121 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts);
2122 if (!ep->cancel_transfer)
2123 ep->bna_occurred = 1;
2124 else
2125 ep->cancel_transfer = 0;
2126 ret_val = IRQ_HANDLED;
2127 goto finished;
2128 }
2129 }
2130 /* HE event ? */
2131 if (tmp & AMD_BIT(UDC_EPSTS_HE)) {
25985edc 2132 dev_err(&dev->pdev->dev, "HE ep%dout occurred\n", ep->num);
55d402d8
TD		 2133
2134 /* clear HE */
2135 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2136 ret_val = IRQ_HANDLED;
2137 goto finished;
2138 }
2139
2140 if (!list_empty(&ep->queue)) {
2141
2142 /* next request */
2143 req = list_entry(ep->queue.next,
2144 struct udc_request, queue);
2145 } else {
2146 req = NULL;
2147 udc_rxfifo_pending = 1;
2148 }
2149 VDBG(dev, "req = %p\n", req);
2150 /* fifo mode */
2151 if (!use_dma) {
2152
2153 /* read fifo */
2154 if (req && udc_rxfifo_read(ep, req)) {
2155 ret_val = IRQ_HANDLED;
2156
2157 /* finish */
2158 complete_req(ep, req, 0);
2159 /* next request */
2160 if (!list_empty(&ep->queue) && !ep->halted) {
2161 req = list_entry(ep->queue.next,
2162 struct udc_request, queue);
2163 } else
2164 req = NULL;
2165 }
2166
2167 /* DMA */
2168 } else if (!ep->cancel_transfer && req != NULL) {
2169 ret_val = IRQ_HANDLED;
2170
2171 /* check for DMA done */
2172 if (!use_dma_ppb) {
2173 dma_done = AMD_GETBITS(req->td_data->status,
2174 UDC_DMA_OUT_STS_BS);
2175 /* packet per buffer mode - rx bytes */
2176 } else {
2177 /*
2178 * if BNA occurred then recover desc. from
2179 * BNA dummy desc.
2180 */
2181 if (ep->bna_occurred) {
2182 VDBG(dev, "Recover desc. from BNA dummy\n");
2183 memcpy(req->td_data, ep->bna_dummy_req->td_data,
2184 sizeof(struct udc_data_dma));
2185 ep->bna_occurred = 0;
2186 udc_init_bna_dummy(ep->req);
2187 }
2188 td = udc_get_last_dma_desc(req);
2189 dma_done = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_BS);
2190 }
2191 if (dma_done == UDC_DMA_OUT_STS_BS_DMA_DONE) {
2192 /* buffer fill mode - rx bytes */
2193 if (!use_dma_ppb) {
2194 /* received number bytes */
2195 count = AMD_GETBITS(req->td_data->status,
2196 UDC_DMA_OUT_STS_RXBYTES);
2197 VDBG(dev, "rx bytes=%u\n", count);
2198 /* packet per buffer mode - rx bytes */
2199 } else {
2200 VDBG(dev, "req->td_data=%p\n", req->td_data);
2201 VDBG(dev, "last desc = %p\n", td);
2202 /* received number bytes */
2203 if (use_dma_ppb_du) {
2204 /* every desc. counts bytes */
2205 count = udc_get_ppbdu_rxbytes(req);
2206 } else {
2207 /* last desc. counts bytes */
2208 count = AMD_GETBITS(td->status,
2209 UDC_DMA_OUT_STS_RXBYTES);
2210 if (!count && req->req.length
2211 == UDC_DMA_MAXPACKET) {
2212 /*
2213 * on 64k packets the RXBYTES
2214 * field is zero
2215 */
2216 count = UDC_DMA_MAXPACKET;
2217 }
2218 }
2219 VDBG(dev, "last desc rx bytes=%u\n", count);
2220 }
2221
2222 tmp = req->req.length - req->req.actual;
2223 if (count > tmp) {
2224 if ((tmp % ep->ep.maxpacket) != 0) {
2225 DBG(dev, "%s: rx %db, space=%db\n",
2226 ep->ep.name, count, tmp);
2227 req->req.status = -EOVERFLOW;
2228 }
2229 count = tmp;
2230 }
2231 req->req.actual += count;
2232 req->dma_going = 0;
2233 /* complete request */
2234 complete_req(ep, req, 0);
2235
2236 /* next request */
2237 if (!list_empty(&ep->queue) && !ep->halted) {
2238 req = list_entry(ep->queue.next,
2239 struct udc_request,
2240 queue);
2241 /*
2242 * DMA may be already started by udc_queue()
2243 * called by gadget drivers completion
2244 * routine. This happens when queue
2245 * holds one request only.
2246 */
2247 if (req->dma_going == 0) {
2248 /* next dma */
2249 if (prep_dma(ep, req, GFP_ATOMIC) != 0)
2250 goto finished;
2251 /* write desc pointer */
2252 writel(req->td_phys,
2253 &ep->regs->desptr);
2254 req->dma_going = 1;
2255 /* enable DMA */
2256 udc_set_rde(dev);
2257 }
2258 } else {
2259 /*
2260 * implant BNA dummy descriptor to allow
2261 * RXFIFO opening by RDE
2262 */
2263 if (ep->bna_dummy_req) {
2264 /* write desc pointer */
2265 writel(ep->bna_dummy_req->td_phys,
2266 &ep->regs->desptr);
2267 ep->bna_occurred = 0;
2268 }
2269
2270 /*
2271 * schedule timer for setting RDE if queue
2272 * remains empty to allow ep0 packets pass
2273 * through
2274 */
2275 if (set_rde != 0
2276 && !timer_pending(&udc_timer)) {
2277 udc_timer.expires =
2278 jiffies
2279 + HZ*UDC_RDE_TIMER_SECONDS;
2280 set_rde = 1;
170b778f 2281 if (!stop_timer)
55d402d8 2282 add_timer(&udc_timer);
55d402d8
TD		 2283 }
2284 if (ep->num != UDC_EP0OUT_IX)
2285 dev->data_ep_queued = 0;
2286 }
2287
2288 } else {
2289 /*
2290 * RX DMA must be reenabled for each desc in PPBDU mode
2291 * and must be enabled for PPBNDU mode in case of BNA
2292 */
2293 udc_set_rde(dev);
2294 }
2295
2296 } else if (ep->cancel_transfer) {
2297 ret_val = IRQ_HANDLED;
2298 ep->cancel_transfer = 0;
2299 }
2300
2301 /* check pending CNAKS */
2302 if (cnak_pending) {
2303 /* CNAk processing when rxfifo empty only */
170b778f 2304 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
55d402d8 2305 udc_process_cnak_queue(dev);
55d402d8
TD		 2306 }
2307
2308 /* clear OUT bits in ep status */
2309 writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts);
2310finished:
2311 return ret_val;
2312}
2313
2314/* Interrupt handler for data IN traffic */
2315static irqreturn_t udc_data_in_isr(struct udc *dev, int ep_ix)
2316{
2317 irqreturn_t ret_val = IRQ_NONE;
2318 u32 tmp;
2319 u32 epsts;
2320 struct udc_ep *ep;
2321 struct udc_request *req;
2322 struct udc_data_dma *td;
2323 unsigned dma_done;
2324 unsigned len;
2325
2326 ep = &dev->ep[ep_ix];
2327
2328 epsts = readl(&ep->regs->sts);
2329 if (use_dma) {
2330 /* BNA ? */
2331 if (epsts & AMD_BIT(UDC_EPSTS_BNA)) {
2332 dev_err(&dev->pdev->dev,
5647a149 2333 "BNA ep%din occurred - DESPTR = %08lx\n",
55d402d8
TD		 2334 ep->num,
2335 (unsigned long) readl(&ep->regs->desptr));
2336
2337 /* clear BNA */
2338 writel(epsts, &ep->regs->sts);
2339 ret_val = IRQ_HANDLED;
2340 goto finished;
2341 }
2342 }
2343 /* HE event ? */
2344 if (epsts & AMD_BIT(UDC_EPSTS_HE)) {
2345 dev_err(&dev->pdev->dev,
5647a149 2346 "HE ep%dn occurred - DESPTR = %08lx\n",
55d402d8
TD		 2347 ep->num, (unsigned long) readl(&ep->regs->desptr));
2348
2349 /* clear HE */
2350 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2351 ret_val = IRQ_HANDLED;
2352 goto finished;
2353 }
2354
2355 /* DMA completion */
2356 if (epsts & AMD_BIT(UDC_EPSTS_TDC)) {
2357 VDBG(dev, "TDC set- completion\n");
2358 ret_val = IRQ_HANDLED;
2359 if (!ep->cancel_transfer && !list_empty(&ep->queue)) {
2360 req = list_entry(ep->queue.next,
2361 struct udc_request, queue);
058e698b 2362 /*
25985edc 2363 * length bytes transferred
058e698b
JL		 2364 * check dma done of last desc. in PPBDU mode
2365 */
2366 if (use_dma_ppb_du) {
2367 td = udc_get_last_dma_desc(req);
2368 if (td) {
2369 dma_done =
2370 AMD_GETBITS(td->status,
2371 UDC_DMA_IN_STS_BS);
2372 /* don't care DMA done */
55d402d8
TD		 2373 req->req.actual = req->req.length;
2374 }
058e698b
JL		 2375 } else {
2376 /* assume all bytes transferred */
2377 req->req.actual = req->req.length;
2378 }
55d402d8 2379
058e698b
JL		 2380 if (req->req.actual == req->req.length) {
2381 /* complete req */
2382 complete_req(ep, req, 0);
2383 req->dma_going = 0;
2384 /* further request available ? */
2385 if (list_empty(&ep->queue)) {
2386 /* disable interrupt */
2387 tmp = readl(&dev->regs->ep_irqmsk);
2388 tmp |= AMD_BIT(ep->num);
2389 writel(tmp, &dev->regs->ep_irqmsk);
55d402d8
TD		 2390 }
2391 }
2392 }
2393 ep->cancel_transfer = 0;
2394
2395 }
2396 /*
2397 * status reg has IN bit set and TDC not set (if TDC was handled,
2398 * IN must not be handled (UDC defect) ?
2399 */
2400 if ((epsts & AMD_BIT(UDC_EPSTS_IN))
2401 && !(epsts & AMD_BIT(UDC_EPSTS_TDC))) {
2402 ret_val = IRQ_HANDLED;
2403 if (!list_empty(&ep->queue)) {
2404 /* next request */
2405 req = list_entry(ep->queue.next,
2406 struct udc_request, queue);
2407 /* FIFO mode */
2408 if (!use_dma) {
2409 /* write fifo */
2410 udc_txfifo_write(ep, &req->req);
2411 len = req->req.length - req->req.actual;
1435db48
CR		 2412 if (len > ep->ep.maxpacket)
2413 len = ep->ep.maxpacket;
2414 req->req.actual += len;
55d402d8
TD		 2415 if (req->req.actual == req->req.length
2416 || (len != ep->ep.maxpacket)) {
2417 /* complete req */
2418 complete_req(ep, req, 0);
2419 }
2420 /* DMA */
2421 } else if (req && !req->dma_going) {
2422 VDBG(dev, "IN DMA : req=%p req->td_data=%p\n",
2423 req, req->td_data);
2424 if (req->td_data) {
2425
2426 req->dma_going = 1;
2427
2428 /*
2429 * unset L bit of first desc.
2430 * for chain
2431 */
2432 if (use_dma_ppb && req->req.length >
2433 ep->ep.maxpacket) {
2434 req->td_data->status &=
2435 AMD_CLEAR_BIT(
2436 UDC_DMA_IN_STS_L);
2437 }
2438
2439 /* write desc pointer */
2440 writel(req->td_phys, &ep->regs->desptr);
2441
2442 /* set HOST READY */
2443 req->td_data->status =
2444 AMD_ADDBITS(
2445 req->td_data->status,
2446 UDC_DMA_IN_STS_BS_HOST_READY,
2447 UDC_DMA_IN_STS_BS);
2448
2449 /* set poll demand bit */
2450 tmp = readl(&ep->regs->ctl);
2451 tmp |= AMD_BIT(UDC_EPCTL_P);
2452 writel(tmp, &ep->regs->ctl);
2453 }
2454 }
2455
c5deb832
TD		 2456 } else if (!use_dma && ep->in) {
2457 /* disable interrupt */
2458 tmp = readl(
2459 &dev->regs->ep_irqmsk);
2460 tmp |= AMD_BIT(ep->num);
2461 writel(tmp,
2462 &dev->regs->ep_irqmsk);
55d402d8
TD		 2463 }
2464 }
2465 /* clear status bits */
2466 writel(epsts, &ep->regs->sts);
2467
2468finished:
2469 return ret_val;
2470
2471}
2472
2473/* Interrupt handler for Control OUT traffic */
2474static irqreturn_t udc_control_out_isr(struct udc *dev)
2475__releases(dev->lock)
2476__acquires(dev->lock)
2477{
2478 irqreturn_t ret_val = IRQ_NONE;
2479 u32 tmp;
2480 int setup_supported;
2481 u32 count;
2482 int set = 0;
2483 struct udc_ep *ep;
2484 struct udc_ep *ep_tmp;
2485
2486 ep = &dev->ep[UDC_EP0OUT_IX];
2487
2488 /* clear irq */
2489 writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts);
2490
2491 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2492 /* check BNA and clear if set */
2493 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2494 VDBG(dev, "ep0: BNA set\n");
2495 writel(AMD_BIT(UDC_EPSTS_BNA),
2496 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2497 ep->bna_occurred = 1;
2498 ret_val = IRQ_HANDLED;
2499 goto finished;
2500 }
2501
2502 /* type of data: SETUP or DATA 0 bytes */
2503 tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT);
2504 VDBG(dev, "data_typ = %x\n", tmp);
2505
2506 /* setup data */
2507 if (tmp == UDC_EPSTS_OUT_SETUP) {
2508 ret_val = IRQ_HANDLED;
2509
2510 ep->dev->stall_ep0in = 0;
2511 dev->waiting_zlp_ack_ep0in = 0;
2512
2513 /* set NAK for EP0_IN */
2514 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2515 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
2516 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2517 dev->ep[UDC_EP0IN_IX].naking = 1;
2518 /* get setup data */
2519 if (use_dma) {
2520
2521 /* clear OUT bits in ep status */
2522 writel(UDC_EPSTS_OUT_CLEAR,
2523 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2524
2525 setup_data.data[0] =
2526 dev->ep[UDC_EP0OUT_IX].td_stp->data12;
2527 setup_data.data[1] =
2528 dev->ep[UDC_EP0OUT_IX].td_stp->data34;
2529 /* set HOST READY */
2530 dev->ep[UDC_EP0OUT_IX].td_stp->status =
2531 UDC_DMA_STP_STS_BS_HOST_READY;
2532 } else {
2533 /* read fifo */
2534 udc_rxfifo_read_dwords(dev, setup_data.data, 2);
2535 }
2536
2537 /* determine direction of control data */
2538 if ((setup_data.request.bRequestType & USB_DIR_IN) != 0) {
2539 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
2540 /* enable RDE */
2541 udc_ep0_set_rde(dev);
2542 set = 0;
2543 } else {
2544 dev->gadget.ep0 = &dev->ep[UDC_EP0OUT_IX].ep;
2545 /*
2546 * implant BNA dummy descriptor to allow RXFIFO opening
2547 * by RDE
2548 */
2549 if (ep->bna_dummy_req) {
2550 /* write desc pointer */
2551 writel(ep->bna_dummy_req->td_phys,
2552 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2553 ep->bna_occurred = 0;
2554 }
2555
2556 set = 1;
2557 dev->ep[UDC_EP0OUT_IX].naking = 1;
2558 /*
2559 * setup timer for enabling RDE (to not enable
2560 * RXFIFO DMA for data to early)
2561 */
2562 set_rde = 1;
2563 if (!timer_pending(&udc_timer)) {
2564 udc_timer.expires = jiffies +
2565 HZ/UDC_RDE_TIMER_DIV;
170b778f 2566 if (!stop_timer)
55d402d8 2567 add_timer(&udc_timer);
55d402d8
TD		 2568 }
2569 }
2570
2571 /*
2572 * mass storage reset must be processed here because
2573 * next packet may be a CLEAR_FEATURE HALT which would not
2574 * clear the stall bit when no STALL handshake was received
2575 * before (autostall can cause this)
2576 */
2577 if (setup_data.data[0] == UDC_MSCRES_DWORD0
2578 && setup_data.data[1] == UDC_MSCRES_DWORD1) {
2579 DBG(dev, "MSC Reset\n");
2580 /*
2581 * clear stall bits
2582 * only one IN and OUT endpoints are handled
2583 */
2584 ep_tmp = &udc->ep[UDC_EPIN_IX];
2585 udc_set_halt(&ep_tmp->ep, 0);
2586 ep_tmp = &udc->ep[UDC_EPOUT_IX];
2587 udc_set_halt(&ep_tmp->ep, 0);
2588 }
2589
2590 /* call gadget with setup data received */
2591 spin_unlock(&dev->lock);
2592 setup_supported = dev->driver->setup(&dev->gadget,
2593 &setup_data.request);
2594 spin_lock(&dev->lock);
2595
2596 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2597 /* ep0 in returns data (not zlp) on IN phase */
2598 if (setup_supported >= 0 && setup_supported <
2599 UDC_EP0IN_MAXPACKET) {
2600 /* clear NAK by writing CNAK in EP0_IN */
2601 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2602 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2603 dev->ep[UDC_EP0IN_IX].naking = 0;
2604 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
2605
2606 /* if unsupported request then stall */
2607 } else if (setup_supported < 0) {
2608 tmp |= AMD_BIT(UDC_EPCTL_S);
2609 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2610 } else
2611 dev->waiting_zlp_ack_ep0in = 1;
2612
2613
2614 /* clear NAK by writing CNAK in EP0_OUT */
2615 if (!set) {
2616 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2617 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2618 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2619 dev->ep[UDC_EP0OUT_IX].naking = 0;
2620 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
2621 }
2622
2623 if (!use_dma) {
2624 /* clear OUT bits in ep status */
2625 writel(UDC_EPSTS_OUT_CLEAR,
2626 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2627 }
2628
2629 /* data packet 0 bytes */
2630 } else if (tmp == UDC_EPSTS_OUT_DATA) {
2631 /* clear OUT bits in ep status */
2632 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
2633
2634 /* get setup data: only 0 packet */
2635 if (use_dma) {
2636 /* no req if 0 packet, just reactivate */
2637 if (list_empty(&dev->ep[UDC_EP0OUT_IX].queue)) {
2638 VDBG(dev, "ZLP\n");
2639
2640 /* set HOST READY */
2641 dev->ep[UDC_EP0OUT_IX].td->status =
2642 AMD_ADDBITS(
2643 dev->ep[UDC_EP0OUT_IX].td->status,
2644 UDC_DMA_OUT_STS_BS_HOST_READY,
2645 UDC_DMA_OUT_STS_BS);
2646 /* enable RDE */
2647 udc_ep0_set_rde(dev);
2648 ret_val = IRQ_HANDLED;
2649
2650 } else {
2651 /* control write */
2652 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2653 /* re-program desc. pointer for possible ZLPs */
2654 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
2655 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2656 /* enable RDE */
2657 udc_ep0_set_rde(dev);
2658 }
2659 } else {
2660
2661 /* received number bytes */
2662 count = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2663 count = AMD_GETBITS(count, UDC_EPSTS_RX_PKT_SIZE);
2664 /* out data for fifo mode not working */
2665 count = 0;
2666
2667 /* 0 packet or real data ? */
2668 if (count != 0) {
2669 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2670 } else {
2671 /* dummy read confirm */
2672 readl(&dev->ep[UDC_EP0OUT_IX].regs->confirm);
2673 ret_val = IRQ_HANDLED;
2674 }
2675 }
2676 }
2677
2678 /* check pending CNAKS */
2679 if (cnak_pending) {
2680 /* CNAk processing when rxfifo empty only */
170b778f 2681 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
55d402d8 2682 udc_process_cnak_queue(dev);
55d402d8
TD		 2683 }
2684
2685finished:
2686 return ret_val;
2687}
2688
2689/* Interrupt handler for Control IN traffic */
2690static irqreturn_t udc_control_in_isr(struct udc *dev)
2691{
2692 irqreturn_t ret_val = IRQ_NONE;
2693 u32 tmp;
2694 struct udc_ep *ep;
2695 struct udc_request *req;
2696 unsigned len;
2697
2698 ep = &dev->ep[UDC_EP0IN_IX];
2699
2700 /* clear irq */
2701 writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts);
2702
2703 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);
2704 /* DMA completion */
2705 if (tmp & AMD_BIT(UDC_EPSTS_TDC)) {
5647a149 2706 VDBG(dev, "isr: TDC clear\n");
55d402d8
TD		 2707 ret_val = IRQ_HANDLED;
2708
2709 /* clear TDC bit */
2710 writel(AMD_BIT(UDC_EPSTS_TDC),
2711 &dev->ep[UDC_EP0IN_IX].regs->sts);
2712
2713 /* status reg has IN bit set ? */
2714 } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) {
2715 ret_val = IRQ_HANDLED;
2716
2717 if (ep->dma) {
2718 /* clear IN bit */
2719 writel(AMD_BIT(UDC_EPSTS_IN),
2720 &dev->ep[UDC_EP0IN_IX].regs->sts);
2721 }
2722 if (dev->stall_ep0in) {
2723 DBG(dev, "stall ep0in\n");
2724 /* halt ep0in */
2725 tmp = readl(&ep->regs->ctl);
2726 tmp |= AMD_BIT(UDC_EPCTL_S);
2727 writel(tmp, &ep->regs->ctl);
2728 } else {
2729 if (!list_empty(&ep->queue)) {
2730 /* next request */
2731 req = list_entry(ep->queue.next,
2732 struct udc_request, queue);
2733
2734 if (ep->dma) {
2735 /* write desc pointer */
2736 writel(req->td_phys, &ep->regs->desptr);
2737 /* set HOST READY */
2738 req->td_data->status =
2739 AMD_ADDBITS(
2740 req->td_data->status,
2741 UDC_DMA_STP_STS_BS_HOST_READY,
2742 UDC_DMA_STP_STS_BS);
2743
2744 /* set poll demand bit */
2745 tmp =
2746 readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2747 tmp |= AMD_BIT(UDC_EPCTL_P);
2748 writel(tmp,
2749 &dev->ep[UDC_EP0IN_IX].regs->ctl);
2750
2751 /* all bytes will be transferred */
2752 req->req.actual = req->req.length;
2753
2754 /* complete req */
2755 complete_req(ep, req, 0);
2756
2757 } else {
2758 /* write fifo */
2759 udc_txfifo_write(ep, &req->req);
2760
25985edc 2761 /* lengh bytes transferred */
55d402d8
TD		 2762 len = req->req.length - req->req.actual;
2763 if (len > ep->ep.maxpacket)
2764 len = ep->ep.maxpacket;
2765
2766 req->req.actual += len;
2767 if (req->req.actual == req->req.length
2768 || (len != ep->ep.maxpacket)) {
2769 /* complete req */
2770 complete_req(ep, req, 0);
2771 }
2772 }
2773
2774 }
2775 }
2776 ep->halted = 0;
2777 dev->stall_ep0in = 0;
2778 if (!ep->dma) {
2779 /* clear IN bit */
2780 writel(AMD_BIT(UDC_EPSTS_IN),
2781 &dev->ep[UDC_EP0IN_IX].regs->sts);
2782 }
2783 }
2784
2785 return ret_val;
2786}
2787
2788
2789/* Interrupt handler for global device events */
2790static irqreturn_t udc_dev_isr(struct udc *dev, u32 dev_irq)
2791__releases(dev->lock)
2792__acquires(dev->lock)
2793{
2794 irqreturn_t ret_val = IRQ_NONE;
2795 u32 tmp;
2796 u32 cfg;
2797 struct udc_ep *ep;
2798 u16 i;
2799 u8 udc_csr_epix;
2800
2801 /* SET_CONFIG irq ? */
2802 if (dev_irq & AMD_BIT(UDC_DEVINT_SC)) {
2803 ret_val = IRQ_HANDLED;
2804
2805 /* read config value */
2806 tmp = readl(&dev->regs->sts);
2807 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG);
2808 DBG(dev, "SET_CONFIG interrupt: config=%d\n", cfg);
2809 dev->cur_config = cfg;
2810 dev->set_cfg_not_acked = 1;
2811
2812 /* make usb request for gadget driver */
2813 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2814 setup_data.request.bRequest = USB_REQ_SET_CONFIGURATION;
fd05e720 2815 setup_data.request.wValue = cpu_to_le16(dev->cur_config);
55d402d8
TD		 2816
2817 /* programm the NE registers */
2818 for (i = 0; i < UDC_EP_NUM; i++) {
2819 ep = &dev->ep[i];
2820 if (ep->in) {
2821
2822 /* ep ix in UDC CSR register space */
2823 udc_csr_epix = ep->num;
2824
2825
2826 /* OUT ep */
2827 } else {
2828 /* ep ix in UDC CSR register space */
2829 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2830 }
2831
2832 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2833 /* ep cfg */
2834 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config,
2835 UDC_CSR_NE_CFG);
2836 /* write reg */
2837 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2838
2839 /* clear stall bits */
2840 ep->halted = 0;
2841 tmp = readl(&ep->regs->ctl);
2842 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2843 writel(tmp, &ep->regs->ctl);
2844 }
2845 /* call gadget zero with setup data received */
2846 spin_unlock(&dev->lock);
2847 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2848 spin_lock(&dev->lock);
2849
2850 } /* SET_INTERFACE ? */
2851 if (dev_irq & AMD_BIT(UDC_DEVINT_SI)) {
2852 ret_val = IRQ_HANDLED;
2853
2854 dev->set_cfg_not_acked = 1;
2855 /* read interface and alt setting values */
2856 tmp = readl(&dev->regs->sts);
2857 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT);
2858 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF);
2859
2860 /* make usb request for gadget driver */
2861 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2862 setup_data.request.bRequest = USB_REQ_SET_INTERFACE;
2863 setup_data.request.bRequestType = USB_RECIP_INTERFACE;
fd05e720
AV		 2864 setup_data.request.wValue = cpu_to_le16(dev->cur_alt);
2865 setup_data.request.wIndex = cpu_to_le16(dev->cur_intf);
55d402d8
TD		 2866
2867 DBG(dev, "SET_INTERFACE interrupt: alt=%d intf=%d\n",
2868 dev->cur_alt, dev->cur_intf);
2869
2870 /* programm the NE registers */
2871 for (i = 0; i < UDC_EP_NUM; i++) {
2872 ep = &dev->ep[i];
2873 if (ep->in) {
2874
2875 /* ep ix in UDC CSR register space */
2876 udc_csr_epix = ep->num;
2877
2878
2879 /* OUT ep */
2880 } else {
2881 /* ep ix in UDC CSR register space */
2882 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2883 }
2884
2885 /* UDC CSR reg */
2886 /* set ep values */
2887 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2888 /* ep interface */
2889 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf,
2890 UDC_CSR_NE_INTF);
2891 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2892 /* ep alt */
2893 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt,
2894 UDC_CSR_NE_ALT);
2895 /* write reg */
2896 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2897
2898 /* clear stall bits */
2899 ep->halted = 0;
2900 tmp = readl(&ep->regs->ctl);
2901 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2902 writel(tmp, &ep->regs->ctl);
2903 }
2904
2905 /* call gadget zero with setup data received */
2906 spin_unlock(&dev->lock);
2907 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2908 spin_lock(&dev->lock);
2909
2910 } /* USB reset */
2911 if (dev_irq & AMD_BIT(UDC_DEVINT_UR)) {
2912 DBG(dev, "USB Reset interrupt\n");
2913 ret_val = IRQ_HANDLED;
2914
2915 /* allow soft reset when suspend occurs */
2916 soft_reset_occured = 0;
2917
2918 dev->waiting_zlp_ack_ep0in = 0;
2919 dev->set_cfg_not_acked = 0;
2920
2921 /* mask not needed interrupts */
2922 udc_mask_unused_interrupts(dev);
2923
2924 /* call gadget to resume and reset configs etc. */
2925 spin_unlock(&dev->lock);
2926 if (dev->sys_suspended && dev->driver->resume) {
2927 dev->driver->resume(&dev->gadget);
2928 dev->sys_suspended = 0;
2929 }
2930 dev->driver->disconnect(&dev->gadget);
2931 spin_lock(&dev->lock);
2932
2933 /* disable ep0 to empty req queue */
2934 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2935 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2936
2937 /* soft reset when rxfifo not empty */
2938 tmp = readl(&dev->regs->sts);
2939 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2940 && !soft_reset_after_usbreset_occured) {
2941 udc_soft_reset(dev);
2942 soft_reset_after_usbreset_occured++;
2943 }
2944
2945 /*
2946 * DMA reset to kill potential old DMA hw hang,
2947 * POLL bit is already reset by ep_init() through
2948 * disconnect()
2949 */
2950 DBG(dev, "DMA machine reset\n");
2951 tmp = readl(&dev->regs->cfg);
2952 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
2953 writel(tmp, &dev->regs->cfg);
2954
2955 /* put into initial config */
2956 udc_basic_init(dev);
2957
2958 /* enable device setup interrupts */
2959 udc_enable_dev_setup_interrupts(dev);
2960
2961 /* enable suspend interrupt */
2962 tmp = readl(&dev->regs->irqmsk);
2963 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US);
2964 writel(tmp, &dev->regs->irqmsk);
2965
2966 } /* USB suspend */
2967 if (dev_irq & AMD_BIT(UDC_DEVINT_US)) {
2968 DBG(dev, "USB Suspend interrupt\n");
2969 ret_val = IRQ_HANDLED;
2970 if (dev->driver->suspend) {
2971 spin_unlock(&dev->lock);
2972 dev->sys_suspended = 1;
2973 dev->driver->suspend(&dev->gadget);
2974 spin_lock(&dev->lock);
2975 }
2976 } /* new speed ? */
2977 if (dev_irq & AMD_BIT(UDC_DEVINT_ENUM)) {
2978 DBG(dev, "ENUM interrupt\n");
2979 ret_val = IRQ_HANDLED;
2980 soft_reset_after_usbreset_occured = 0;
2981
2982 /* disable ep0 to empty req queue */
2983 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2984 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2985
2986 /* link up all endpoints */
2987 udc_setup_endpoints(dev);
e538dfda
MN		 2988 dev_info(&dev->pdev->dev, "Connect: %s\n",
2989 usb_speed_string(dev->gadget.speed));
55d402d8
TD		 2990
2991 /* init ep 0 */
2992 activate_control_endpoints(dev);
2993
2994 /* enable ep0 interrupts */
2995 udc_enable_ep0_interrupts(dev);
2996 }
2997 /* session valid change interrupt */
2998 if (dev_irq & AMD_BIT(UDC_DEVINT_SVC)) {
2999 DBG(dev, "USB SVC interrupt\n");
3000 ret_val = IRQ_HANDLED;
3001
3002 /* check that session is not valid to detect disconnect */
3003 tmp = readl(&dev->regs->sts);
3004 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) {
3005 /* disable suspend interrupt */
3006 tmp = readl(&dev->regs->irqmsk);
3007 tmp |= AMD_BIT(UDC_DEVINT_US);
3008 writel(tmp, &dev->regs->irqmsk);
3009 DBG(dev, "USB Disconnect (session valid low)\n");
3010 /* cleanup on disconnect */
3011 usb_disconnect(udc);
3012 }
3013
3014 }
3015
3016 return ret_val;
3017}
3018
3019/* Interrupt Service Routine, see Linux Kernel Doc for parameters */
3020static irqreturn_t udc_irq(int irq, void *pdev)
3021{
3022 struct udc *dev = pdev;
3023 u32 reg;
3024 u16 i;
3025 u32 ep_irq;
3026 irqreturn_t ret_val = IRQ_NONE;
3027
3028 spin_lock(&dev->lock);
3029
3030 /* check for ep irq */
3031 reg = readl(&dev->regs->ep_irqsts);
3032 if (reg) {
3033 if (reg & AMD_BIT(UDC_EPINT_OUT_EP0))
3034 ret_val |= udc_control_out_isr(dev);
3035 if (reg & AMD_BIT(UDC_EPINT_IN_EP0))
3036 ret_val |= udc_control_in_isr(dev);
3037
3038 /*
3039 * data endpoint
3040 * iterate ep's
3041 */
3042 for (i = 1; i < UDC_EP_NUM; i++) {
3043 ep_irq = 1 << i;
3044 if (!(reg & ep_irq) || i == UDC_EPINT_OUT_EP0)
3045 continue;
3046
3047 /* clear irq status */
3048 writel(ep_irq, &dev->regs->ep_irqsts);
3049
3050 /* irq for out ep ? */
3051 if (i > UDC_EPIN_NUM)
3052 ret_val |= udc_data_out_isr(dev, i);
3053 else
3054 ret_val |= udc_data_in_isr(dev, i);
3055 }
3056
3057 }
3058
3059
3060 /* check for dev irq */
3061 reg = readl(&dev->regs->irqsts);
3062 if (reg) {
3063 /* clear irq */
3064 writel(reg, &dev->regs->irqsts);
3065 ret_val |= udc_dev_isr(dev, reg);
3066 }
3067
3068
3069 spin_unlock(&dev->lock);
3070 return ret_val;
3071}
3072
3073/* Tears down device */
3074static void gadget_release(struct device *pdev)
3075{
3076 struct amd5536udc *dev = dev_get_drvdata(pdev);
3077 kfree(dev);
3078}
3079
3080/* Cleanup on device remove */
3081static void udc_remove(struct udc *dev)
3082{
3083 /* remove timer */
3084 stop_timer++;
3085 if (timer_pending(&udc_timer))
3086 wait_for_completion(&on_exit);
3087 if (udc_timer.data)
3088 del_timer_sync(&udc_timer);
3089 /* remove pollstall timer */
3090 stop_pollstall_timer++;
3091 if (timer_pending(&udc_pollstall_timer))
3092 wait_for_completion(&on_pollstall_exit);
3093 if (udc_pollstall_timer.data)
3094 del_timer_sync(&udc_pollstall_timer);
3095 udc = NULL;
3096}
3097
3098/* Reset all pci context */
3099static void udc_pci_remove(struct pci_dev *pdev)
3100{
3101 struct udc *dev;
3102
3103 dev = pci_get_drvdata(pdev);
3104
0f91349b 3105 usb_del_gadget_udc(&udc->gadget);
55d402d8
TD		 3106 /* gadget driver must not be registered */
3107 BUG_ON(dev->driver != NULL);
3108
3109 /* dma pool cleanup */
3110 if (dev->data_requests)
3111 pci_pool_destroy(dev->data_requests);
3112
3113 if (dev->stp_requests) {
3114 /* cleanup DMA desc's for ep0in */
3115 pci_pool_free(dev->stp_requests,
3116 dev->ep[UDC_EP0OUT_IX].td_stp,
3117 dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3118 pci_pool_free(dev->stp_requests,
3119 dev->ep[UDC_EP0OUT_IX].td,
3120 dev->ep[UDC_EP0OUT_IX].td_phys);
3121
3122 pci_pool_destroy(dev->stp_requests);
3123 }
3124
3125 /* reset controller */
3126 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
3127 if (dev->irq_registered)
3128 free_irq(pdev->irq, dev);
3129 if (dev->regs)
3130 iounmap(dev->regs);
3131 if (dev->mem_region)
3132 release_mem_region(pci_resource_start(pdev, 0),
3133 pci_resource_len(pdev, 0));
3134 if (dev->active)
3135 pci_disable_device(pdev);
3136
3137 device_unregister(&dev->gadget.dev);
3138 pci_set_drvdata(pdev, NULL);
3139
3140 udc_remove(dev);
3141}
3142
3143/* create dma pools on init */
3144static int init_dma_pools(struct udc *dev)
3145{
3146 struct udc_stp_dma *td_stp;
3147 struct udc_data_dma *td_data;
3148 int retval;
3149
3150 /* consistent DMA mode setting ? */
3151 if (use_dma_ppb) {
3152 use_dma_bufferfill_mode = 0;
3153 } else {
3154 use_dma_ppb_du = 0;
3155 use_dma_bufferfill_mode = 1;
3156 }
3157
3158 /* DMA setup */
3159 dev->data_requests = dma_pool_create("data_requests", NULL,
3160 sizeof(struct udc_data_dma), 0, 0);
3161 if (!dev->data_requests) {
3162 DBG(dev, "can't get request data pool\n");
3163 retval = -ENOMEM;
3164 goto finished;
3165 }
3166
3167 /* EP0 in dma regs = dev control regs */
3168 dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;
3169
3170 /* dma desc for setup data */
3171 dev->stp_requests = dma_pool_create("setup requests", NULL,
3172 sizeof(struct udc_stp_dma), 0, 0);
3173 if (!dev->stp_requests) {
3174 DBG(dev, "can't get stp request pool\n");
3175 retval = -ENOMEM;
3176 goto finished;
3177 }
3178 /* setup */
3179 td_stp = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3180 &dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3181 if (td_stp == NULL) {
3182 retval = -ENOMEM;
3183 goto finished;
3184 }
3185 dev->ep[UDC_EP0OUT_IX].td_stp = td_stp;
3186
3187 /* data: 0 packets !? */
3188 td_data = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3189 &dev->ep[UDC_EP0OUT_IX].td_phys);
3190 if (td_data == NULL) {
3191 retval = -ENOMEM;
3192 goto finished;
3193 }
3194 dev->ep[UDC_EP0OUT_IX].td = td_data;
3195 return 0;
3196
3197finished:
3198 return retval;
3199}
3200
3201/* Called by pci bus driver to init pci context */
3202static int udc_pci_probe(
3203 struct pci_dev *pdev,
3204 const struct pci_device_id *id
3205)
3206{
3207 struct udc *dev;
3208 unsigned long resource;
3209 unsigned long len;
3210 int retval = 0;
3211
3212 /* one udc only */
3213 if (udc) {
3214 dev_dbg(&pdev->dev, "already probed\n");
3215 return -EBUSY;
3216 }
3217
3218 /* init */
3219 dev = kzalloc(sizeof(struct udc), GFP_KERNEL);
3220 if (!dev) {
3221 retval = -ENOMEM;
3222 goto finished;
3223 }
55d402d8
TD		 3224
3225 /* pci setup */
3226 if (pci_enable_device(pdev) < 0) {
73d79aab 3227 kfree(dev);
af3d305c 3228 dev = NULL;
55d402d8
TD		 3229 retval = -ENODEV;
3230 goto finished;
3231 }
3232 dev->active = 1;
3233
3234 /* PCI resource allocation */
3235 resource = pci_resource_start(pdev, 0);
3236 len = pci_resource_len(pdev, 0);
3237
3238 if (!request_mem_region(resource, len, name)) {
3239 dev_dbg(&pdev->dev, "pci device used already\n");
73d79aab 3240 kfree(dev);
af3d305c 3241 dev = NULL;
55d402d8
TD		 3242 retval = -EBUSY;
3243 goto finished;
3244 }
3245 dev->mem_region = 1;
3246
3247 dev->virt_addr = ioremap_nocache(resource, len);
3248 if (dev->virt_addr == NULL) {
3249 dev_dbg(&pdev->dev, "start address cannot be mapped\n");
73d79aab 3250 kfree(dev);
af3d305c 3251 dev = NULL;
55d402d8
TD		 3252 retval = -EFAULT;
3253 goto finished;
3254 }
3255
3256 if (!pdev->irq) {
3257 dev_err(&dev->pdev->dev, "irq not set\n");
73d79aab 3258 kfree(dev);
af3d305c 3259 dev = NULL;
55d402d8
TD		 3260 retval = -ENODEV;
3261 goto finished;
3262 }
3263
c5deb832
TD		 3264 spin_lock_init(&dev->lock);
3265 /* udc csr registers base */
3266 dev->csr = dev->virt_addr + UDC_CSR_ADDR;
3267 /* dev registers base */
3268 dev->regs = dev->virt_addr + UDC_DEVCFG_ADDR;
3269 /* ep registers base */
3270 dev->ep_regs = dev->virt_addr + UDC_EPREGS_ADDR;
3271 /* fifo's base */
3272 dev->rxfifo = (u32 __iomem *)(dev->virt_addr + UDC_RXFIFO_ADDR);
3273 dev->txfifo = (u32 __iomem *)(dev->virt_addr + UDC_TXFIFO_ADDR);
3274
55d402d8
TD		 3275 if (request_irq(pdev->irq, udc_irq, IRQF_SHARED, name, dev) != 0) {
3276 dev_dbg(&dev->pdev->dev, "request_irq(%d) fail\n", pdev->irq);
73d79aab 3277 kfree(dev);
af3d305c 3278 dev = NULL;
55d402d8
TD		 3279 retval = -EBUSY;
3280 goto finished;
3281 }
3282 dev->irq_registered = 1;
3283
3284 pci_set_drvdata(pdev, dev);
3285
1d3ee41e
AK		 3286 /* chip revision for Hs AMD5536 */
3287 dev->chiprev = pdev->revision;
55d402d8
TD		 3288
3289 pci_set_master(pdev);
51745281 3290 pci_try_set_mwi(pdev);
55d402d8 3291
55d402d8
TD		 3292 /* init dma pools */
3293 if (use_dma) {
3294 retval = init_dma_pools(dev);
3295 if (retval != 0)
3296 goto finished;
3297 }
3298
3299 dev->phys_addr = resource;
3300 dev->irq = pdev->irq;
3301 dev->pdev = pdev;
3302 dev->gadget.dev.parent = &pdev->dev;
3303 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
3304
3305 /* general probing */
3306 if (udc_probe(dev) == 0)
3307 return 0;
3308
3309finished:
3310 if (dev)
3311 udc_pci_remove(pdev);
3312 return retval;
3313}
3314
3315/* general probe */
3316static int udc_probe(struct udc *dev)
3317{
3318 char tmp[128];
3319 u32 reg;
3320 int retval;
3321
3322 /* mark timer as not initialized */
3323 udc_timer.data = 0;
3324 udc_pollstall_timer.data = 0;
3325
3326 /* device struct setup */
55d402d8
TD		 3327 dev->gadget.ops = &udc_ops;
3328
0031a06e 3329 dev_set_name(&dev->gadget.dev, "gadget");
55d402d8
TD		 3330 dev->gadget.dev.release = gadget_release;
3331 dev->gadget.name = name;
d327ab5b 3332 dev->gadget.max_speed = USB_SPEED_HIGH;
55d402d8 3333
55d402d8
TD		 3334 /* init registers, interrupts, ... */
3335 startup_registers(dev);
3336
3337 dev_info(&dev->pdev->dev, "%s\n", mod_desc);
3338
3339 snprintf(tmp, sizeof tmp, "%d", dev->irq);
3340 dev_info(&dev->pdev->dev,
3341 "irq %s, pci mem %08lx, chip rev %02x(Geode5536 %s)\n",
3342 tmp, dev->phys_addr, dev->chiprev,
3343 (dev->chiprev == UDC_HSA0_REV) ? "A0" : "B1");
3344 strcpy(tmp, UDC_DRIVER_VERSION_STRING);
3345 if (dev->chiprev == UDC_HSA0_REV) {
3346 dev_err(&dev->pdev->dev, "chip revision is A0; too old\n");
3347 retval = -ENODEV;
3348 goto finished;
3349 }
3350 dev_info(&dev->pdev->dev,
3351 "driver version: %s(for Geode5536 B1)\n", tmp);
3352 udc = dev;
3353
0f91349b
SAS		 3354 retval = usb_add_gadget_udc(&udc->pdev->dev, &dev->gadget);
3355 if (retval)
3356 goto finished;
3357
55d402d8 3358 retval = device_register(&dev->gadget.dev);
f34c25ed 3359 if (retval) {
0f91349b 3360 usb_del_gadget_udc(&dev->gadget);
f34c25ed 3361 put_device(&dev->gadget.dev);
55d402d8 3362 goto finished;
f34c25ed 3363 }
55d402d8
TD		 3364
3365 /* timer init */
3366 init_timer(&udc_timer);
3367 udc_timer.function = udc_timer_function;
3368 udc_timer.data = 1;
3369 /* timer pollstall init */
3370 init_timer(&udc_pollstall_timer);
3371 udc_pollstall_timer.function = udc_pollstall_timer_function;
3372 udc_pollstall_timer.data = 1;
3373
3374 /* set SD */
3375 reg = readl(&dev->regs->ctl);
3376 reg |= AMD_BIT(UDC_DEVCTL_SD);
3377 writel(reg, &dev->regs->ctl);
3378
3379 /* print dev register info */
3380 print_regs(dev);
3381
3382 return 0;
3383
3384finished:
3385 return retval;
3386}
3387
3388/* Initiates a remote wakeup */
3389static int udc_remote_wakeup(struct udc *dev)
3390{
3391 unsigned long flags;
3392 u32 tmp;
3393
3394 DBG(dev, "UDC initiates remote wakeup\n");
3395
3396 spin_lock_irqsave(&dev->lock, flags);
3397
3398 tmp = readl(&dev->regs->ctl);
3399 tmp |= AMD_BIT(UDC_DEVCTL_RES);
3400 writel(tmp, &dev->regs->ctl);
3401 tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES);
3402 writel(tmp, &dev->regs->ctl);
3403
3404 spin_unlock_irqrestore(&dev->lock, flags);
3405 return 0;
3406}
3407
3408/* PCI device parameters */
1b8860df 3409static DEFINE_PCI_DEVICE_TABLE(pci_id) = {
55d402d8
TD		 3410 {
3411 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x2096),
3412 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3413 .class_mask = 0xffffffff,
3414 },
3415 {},
3416};
3417MODULE_DEVICE_TABLE(pci, pci_id);
3418
3419/* PCI functions */
3420static struct pci_driver udc_pci_driver = {
3421 .name = (char *) name,
3422 .id_table = pci_id,
3423 .probe = udc_pci_probe,
3424 .remove = udc_pci_remove,
3425};
3426
3427/* Inits driver */
3428static int __init init(void)
3429{
3430 return pci_register_driver(&udc_pci_driver);
3431}
3432module_init(init);
3433
3434/* Cleans driver */
3435static void __exit cleanup(void)
3436{
3437 pci_unregister_driver(&udc_pci_driver);
3438}
3439module_exit(cleanup);
3440
3441MODULE_DESCRIPTION(UDC_MOD_DESCRIPTION);
3442MODULE_AUTHOR("Thomas Dahlmann");
3443MODULE_LICENSE("GPL");
3444
Linux 6.x block layer and io_uring tree(s)