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usb: dwc3: gadget: Simplify skipping of link TRBs
[linux-2.6-block.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4
FB		 17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
80977dc9 33#include "debug.h"
72246da4
FB		 34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
04a9bfcd
FB		 38/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
911f1f88
PZ		 71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
8598bde7
FB		 87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
aee63e3c 93 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
aee63e3c 97 int retries = 10000;
8598bde7
FB		 98 u32 reg;
99
802fde98
PZ		 100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
8598bde7
FB		 117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
802fde98
PZ		 124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
8598bde7 131 /* wait for a change in DSTS */
aed430e5 132 retries = 10000;
8598bde7
FB		 133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
8598bde7
FB		 136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
aee63e3c 139 udelay(5);
8598bde7
FB		 140 }
141
73815280
FB		 142 dwc3_trace(trace_dwc3_gadget,
143 "link state change request timed out");
8598bde7
FB		 144
145 return -ETIMEDOUT;
146}
147
dca0119c
JY		 148/**
149 * dwc3_ep_inc_trb() - Increment a TRB index.
150 * @index - Pointer to the TRB index to increment.
151 *
152 * The index should never point to the link TRB. After incrementing,
153 * if it is point to the link TRB, wrap around to the beginning. The
154 * link TRB is always at the last TRB entry.
155 */
156static void dwc3_ep_inc_trb(u8 *index)
457e84b6 157{
dca0119c
JY		 158 (*index)++;
159 if (*index == (DWC3_TRB_NUM - 1))
160 *index = 0;
ef966b9d 161}
457e84b6 162
dca0119c 163static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
ef966b9d 164{
dca0119c 165 dwc3_ep_inc_trb(&dep->trb_enqueue);
ef966b9d 166}
457e84b6 167
dca0119c 168static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
ef966b9d 169{
dca0119c 170 dwc3_ep_inc_trb(&dep->trb_dequeue);
457e84b6
FB		 171}
172
72246da4
FB		 173void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
174 int status)
175{
176 struct dwc3 *dwc = dep->dwc;
e5ba5ec8 177 int i;
72246da4 178
aa3342c8 179 if (req->started) {
e5ba5ec8
PA		 180 i = 0;
181 do {
ef966b9d 182 dwc3_ep_inc_deq(dep);
e5ba5ec8 183 } while(++i < req->request.num_mapped_sgs);
aa3342c8 184 req->started = false;
72246da4
FB		 185 }
186 list_del(&req->list);
eeb720fb 187 req->trb = NULL;
72246da4
FB		 188
189 if (req->request.status == -EINPROGRESS)
190 req->request.status = status;
191
0416e494
PA		 192 if (dwc->ep0_bounced && dep->number == 0)
193 dwc->ep0_bounced = false;
194 else
195 usb_gadget_unmap_request(&dwc->gadget, &req->request,
196 req->direction);
72246da4 197
2c4cbe6e 198 trace_dwc3_gadget_giveback(req);
72246da4
FB		 199
200 spin_unlock(&dwc->lock);
304f7e5e 201 usb_gadget_giveback_request(&dep->endpoint, &req->request);
72246da4 202 spin_lock(&dwc->lock);
fc8bb91b
FB		 203
204 if (dep->number > 1)
205 pm_runtime_put(dwc->dev);
72246da4
FB		 206}
207
3ece0ec4 208int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
b09bb642
FB		 209{
210 u32 timeout = 500;
71f7e702 211 int status = 0;
0fe886cd 212 int ret = 0;
b09bb642
FB		 213 u32 reg;
214
215 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
216 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
217
218 do {
219 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
220 if (!(reg & DWC3_DGCMD_CMDACT)) {
71f7e702
FB		 221 status = DWC3_DGCMD_STATUS(reg);
222 if (status)
0fe886cd
FB		 223 ret = -EINVAL;
224 break;
b09bb642 225 }
0fe886cd
FB		 226 } while (timeout--);
227
228 if (!timeout) {
0fe886cd 229 ret = -ETIMEDOUT;
71f7e702 230 status = -ETIMEDOUT;
0fe886cd
FB		 231 }
232
71f7e702
FB		 233 trace_dwc3_gadget_generic_cmd(cmd, param, status);
234
0fe886cd 235 return ret;
b09bb642
FB		 236}
237
c36d8e94
FB		 238static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
239
2cd4718d
FB		 240int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
241 struct dwc3_gadget_ep_cmd_params *params)
72246da4 242{
2cd4718d 243 struct dwc3 *dwc = dep->dwc;
61d58242 244 u32 timeout = 500;
72246da4
FB		 245 u32 reg;
246
0933df15 247 int cmd_status = 0;
2b0f11df 248 int susphy = false;
c0ca324d 249 int ret = -EINVAL;
72246da4 250
2b0f11df
FB		 251 /*
252 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
253 * we're issuing an endpoint command, we must check if
254 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
255 *
256 * We will also set SUSPHY bit to what it was before returning as stated
257 * by the same section on Synopsys databook.
258 */
ab2a92e7
FB		 259 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
260 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
261 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
262 susphy = true;
263 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
264 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
265 }
2b0f11df
FB		 266 }
267
c36d8e94
FB		 268 if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
269 int needs_wakeup;
270
271 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
272 dwc->link_state == DWC3_LINK_STATE_U2 ||
273 dwc->link_state == DWC3_LINK_STATE_U3);
274
275 if (unlikely(needs_wakeup)) {
276 ret = __dwc3_gadget_wakeup(dwc);
277 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
278 ret);
279 }
280 }
281
2eb88016
FB		 282 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
283 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
284 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
72246da4 285
2eb88016 286 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd | DWC3_DEPCMD_CMDACT);
72246da4 287 do {
2eb88016 288 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
72246da4 289 if (!(reg & DWC3_DEPCMD_CMDACT)) {
0933df15 290 cmd_status = DWC3_DEPCMD_STATUS(reg);
7b9cc7a2 291
73815280
FB		 292 dwc3_trace(trace_dwc3_gadget,
293 "Command Complete --> %d",
7b9cc7a2
KL		 294 cmd_status);
295
296 switch (cmd_status) {
297 case 0:
298 ret = 0;
299 break;
300 case DEPEVT_TRANSFER_NO_RESOURCE:
ba159841 301 dwc3_trace(trace_dwc3_gadget, "no resource available");
7b9cc7a2 302 ret = -EINVAL;
c0ca324d 303 break;
7b9cc7a2
KL		 304 case DEPEVT_TRANSFER_BUS_EXPIRY:
305 /*
306 * SW issues START TRANSFER command to
307 * isochronous ep with future frame interval. If
308 * future interval time has already passed when
309 * core receives the command, it will respond
310 * with an error status of 'Bus Expiry'.
311 *
312 * Instead of always returning -EINVAL, let's
313 * give a hint to the gadget driver that this is
314 * the case by returning -EAGAIN.
315 */
ba159841 316 dwc3_trace(trace_dwc3_gadget, "bus expiry");
7b9cc7a2
KL		 317 ret = -EAGAIN;
318 break;
319 default:
320 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
321 }
322
c0ca324d 323 break;
72246da4 324 }
f6bb225b 325 } while (--timeout);
72246da4 326
f6bb225b
FB		 327 if (timeout == 0) {
328 dwc3_trace(trace_dwc3_gadget,
329 "Command Timed Out");
330 ret = -ETIMEDOUT;
0933df15 331 cmd_status = -ETIMEDOUT;
f6bb225b 332 }
c0ca324d 333
0933df15
FB		 334 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
335
2b0f11df
FB		 336 if (unlikely(susphy)) {
337 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
338 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
339 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
340 }
341
c0ca324d 342 return ret;
72246da4
FB		 343}
344
50c763f8
JY		 345static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
346{
347 struct dwc3 *dwc = dep->dwc;
348 struct dwc3_gadget_ep_cmd_params params;
349 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
350
351 /*
352 * As of core revision 2.60a the recommended programming model
353 * is to set the ClearPendIN bit when issuing a Clear Stall EP
354 * command for IN endpoints. This is to prevent an issue where
355 * some (non-compliant) hosts may not send ACK TPs for pending
356 * IN transfers due to a mishandled error condition. Synopsys
357 * STAR 9000614252.
358 */
359 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A))
360 cmd |= DWC3_DEPCMD_CLEARPENDIN;
361
362 memset(&params, 0, sizeof(params));
363
2cd4718d 364 return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
50c763f8
JY		 365}
366
72246da4 367static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 368 struct dwc3_trb *trb)
72246da4 369{
c439ef87 370 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 371
372 return dep->trb_pool_dma + offset;
373}
374
375static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
376{
377 struct dwc3 *dwc = dep->dwc;
378
379 if (dep->trb_pool)
380 return 0;
381
72246da4
FB		 382 dep->trb_pool = dma_alloc_coherent(dwc->dev,
383 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
384 &dep->trb_pool_dma, GFP_KERNEL);
385 if (!dep->trb_pool) {
386 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
387 dep->name);
388 return -ENOMEM;
389 }
390
391 return 0;
392}
393
394static void dwc3_free_trb_pool(struct dwc3_ep *dep)
395{
396 struct dwc3 *dwc = dep->dwc;
397
398 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
399 dep->trb_pool, dep->trb_pool_dma);
400
401 dep->trb_pool = NULL;
402 dep->trb_pool_dma = 0;
403}
404
c4509601
JY		 405static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
406
407/**
408 * dwc3_gadget_start_config - Configure EP resources
409 * @dwc: pointer to our controller context structure
410 * @dep: endpoint that is being enabled
411 *
412 * The assignment of transfer resources cannot perfectly follow the
413 * data book due to the fact that the controller driver does not have
414 * all knowledge of the configuration in advance. It is given this
415 * information piecemeal by the composite gadget framework after every
416 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
417 * programming model in this scenario can cause errors. For two
418 * reasons:
419 *
420 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
421 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
422 * multiple interfaces.
423 *
424 * 2) The databook does not mention doing more DEPXFERCFG for new
425 * endpoint on alt setting (8.1.6).
426 *
427 * The following simplified method is used instead:
428 *
429 * All hardware endpoints can be assigned a transfer resource and this
430 * setting will stay persistent until either a core reset or
431 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
432 * do DEPXFERCFG for every hardware endpoint as well. We are
433 * guaranteed that there are as many transfer resources as endpoints.
434 *
435 * This function is called for each endpoint when it is being enabled
436 * but is triggered only when called for EP0-out, which always happens
437 * first, and which should only happen in one of the above conditions.
438 */
72246da4
FB		 439static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
440{
441 struct dwc3_gadget_ep_cmd_params params;
442 u32 cmd;
c4509601
JY		 443 int i;
444 int ret;
445
446 if (dep->number)
447 return 0;
72246da4
FB		 448
449 memset(&params, 0x00, sizeof(params));
c4509601 450 cmd = DWC3_DEPCMD_DEPSTARTCFG;
72246da4 451
2cd4718d 452 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
c4509601
JY		 453 if (ret)
454 return ret;
455
456 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
457 struct dwc3_ep *dep = dwc->eps[i];
72246da4 458
c4509601
JY		 459 if (!dep)
460 continue;
461
462 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
463 if (ret)
464 return ret;
72246da4
FB		 465 }
466
467 return 0;
468}
469
470static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
c90bfaec 471 const struct usb_endpoint_descriptor *desc,
4b345c9a 472 const struct usb_ss_ep_comp_descriptor *comp_desc,
265b70a7 473 bool ignore, bool restore)
72246da4
FB		 474{
475 struct dwc3_gadget_ep_cmd_params params;
476
477 memset(&params, 0x00, sizeof(params));
478
dc1c70a7 479 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
d2e9a13a
CP		 480 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
481
482 /* Burst size is only needed in SuperSpeed mode */
ee5cd41c 483 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
676e3497 484 u32 burst = dep->endpoint.maxburst;
676e3497 485 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
d2e9a13a 486 }
72246da4 487
4b345c9a
FB		 488 if (ignore)
489 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
490
265b70a7
PZ		 491 if (restore) {
492 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
493 params.param2 |= dep->saved_state;
494 }
495
dc1c70a7
FB		 496 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
497 | DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 498
18b7ede5 499 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 500 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
501 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 502 dep->stream_capable = true;
503 }
504
0b93a4c8 505 if (!usb_endpoint_xfer_control(desc))
dc1c70a7 506 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 507
508 /*
509 * We are doing 1:1 mapping for endpoints, meaning
510 * Physical Endpoints 2 maps to Logical Endpoint 2 and
511 * so on. We consider the direction bit as part of the physical
512 * endpoint number. So USB endpoint 0x81 is 0x03.
513 */
dc1c70a7 514 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 515
516 /*
517 * We must use the lower 16 TX FIFOs even though
518 * HW might have more
519 */
520 if (dep->direction)
dc1c70a7 521 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 522
523 if (desc->bInterval) {
dc1c70a7 524 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 525 dep->interval = 1 << (desc->bInterval - 1);
526 }
527
2cd4718d 528 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
72246da4
FB		 529}
530
531static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
532{
533 struct dwc3_gadget_ep_cmd_params params;
534
535 memset(&params, 0x00, sizeof(params));
536
dc1c70a7 537 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4 538
2cd4718d
FB		 539 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
540 &params);
72246da4
FB		 541}
542
543/**
544 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
545 * @dep: endpoint to be initialized
546 * @desc: USB Endpoint Descriptor
547 *
548 * Caller should take care of locking
549 */
550static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
c90bfaec 551 const struct usb_endpoint_descriptor *desc,
4b345c9a 552 const struct usb_ss_ep_comp_descriptor *comp_desc,
265b70a7 553 bool ignore, bool restore)
72246da4
FB		 554{
555 struct dwc3 *dwc = dep->dwc;
556 u32 reg;
b09e99ee 557 int ret;
72246da4 558
73815280 559 dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
ff62d6b6 560
72246da4
FB		 561 if (!(dep->flags & DWC3_EP_ENABLED)) {
562 ret = dwc3_gadget_start_config(dwc, dep);
563 if (ret)
564 return ret;
565 }
566
265b70a7
PZ		 567 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
568 restore);
72246da4
FB		 569 if (ret)
570 return ret;
571
572 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 573 struct dwc3_trb *trb_st_hw;
574 struct dwc3_trb *trb_link;
72246da4 575
16e78db7 576 dep->endpoint.desc = desc;
c90bfaec 577 dep->comp_desc = comp_desc;
72246da4
FB		 578 dep->type = usb_endpoint_type(desc);
579 dep->flags |= DWC3_EP_ENABLED;
580
581 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
582 reg |= DWC3_DALEPENA_EP(dep->number);
583 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
584
36b68aae 585 if (usb_endpoint_xfer_control(desc))
7ab373aa 586 return 0;
72246da4 587
36b68aae 588 /* Link TRB. The HWO bit is never reset */
72246da4
FB		 589 trb_st_hw = &dep->trb_pool[0];
590
f6bafc6a 591 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
1200a82a 592 memset(trb_link, 0, sizeof(*trb_link));
72246da4 593
f6bafc6a
FB		 594 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
595 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
596 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
597 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 598 }
599
600 return 0;
601}
602
b992e681 603static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
624407f9 604static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 605{
606 struct dwc3_request *req;
607
aa3342c8 608 if (!list_empty(&dep->started_list)) {
b992e681 609 dwc3_stop_active_transfer(dwc, dep->number, true);
624407f9 610
57911504 611 /* - giveback all requests to gadget driver */
aa3342c8
FB		 612 while (!list_empty(&dep->started_list)) {
613 req = next_request(&dep->started_list);
1591633e
PA		 614
615 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
616 }
ea53b882
FB		 617 }
618
aa3342c8
FB		 619 while (!list_empty(&dep->pending_list)) {
620 req = next_request(&dep->pending_list);
72246da4 621
624407f9 622 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 623 }
72246da4
FB		 624}
625
626/**
627 * __dwc3_gadget_ep_disable - Disables a HW endpoint
628 * @dep: the endpoint to disable
629 *
624407f9
SAS		 630 * This function also removes requests which are currently processed ny the
631 * hardware and those which are not yet scheduled.
632 * Caller should take care of locking.
72246da4 633 */
72246da4
FB		 634static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
635{
636 struct dwc3 *dwc = dep->dwc;
637 u32 reg;
638
7eaeac5c
FB		 639 dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
640
624407f9 641 dwc3_remove_requests(dwc, dep);
72246da4 642
687ef981
FB		 643 /* make sure HW endpoint isn't stalled */
644 if (dep->flags & DWC3_EP_STALL)
7a608559 645 __dwc3_gadget_ep_set_halt(dep, 0, false);
687ef981 646
72246da4
FB		 647 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
648 reg &= ~DWC3_DALEPENA_EP(dep->number);
649 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
650
879631aa 651 dep->stream_capable = false;
f9c56cdd 652 dep->endpoint.desc = NULL;
c90bfaec 653 dep->comp_desc = NULL;
72246da4 654 dep->type = 0;
879631aa 655 dep->flags = 0;
72246da4
FB		 656
657 return 0;
658}
659
660/* -------------------------------------------------------------------------- */
661
662static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
663 const struct usb_endpoint_descriptor *desc)
664{
665 return -EINVAL;
666}
667
668static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
669{
670 return -EINVAL;
671}
672
673/* -------------------------------------------------------------------------- */
674
675static int dwc3_gadget_ep_enable(struct usb_ep *ep,
676 const struct usb_endpoint_descriptor *desc)
677{
678 struct dwc3_ep *dep;
679 struct dwc3 *dwc;
680 unsigned long flags;
681 int ret;
682
683 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
684 pr_debug("dwc3: invalid parameters\n");
685 return -EINVAL;
686 }
687
688 if (!desc->wMaxPacketSize) {
689 pr_debug("dwc3: missing wMaxPacketSize\n");
690 return -EINVAL;
691 }
692
693 dep = to_dwc3_ep(ep);
694 dwc = dep->dwc;
695
95ca961c
FB		 696 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
697 "%s is already enabled\n",
698 dep->name))
c6f83f38 699 return 0;
c6f83f38 700
72246da4 701 spin_lock_irqsave(&dwc->lock, flags);
265b70a7 702 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
72246da4
FB		 703 spin_unlock_irqrestore(&dwc->lock, flags);
704
705 return ret;
706}
707
708static int dwc3_gadget_ep_disable(struct usb_ep *ep)
709{
710 struct dwc3_ep *dep;
711 struct dwc3 *dwc;
712 unsigned long flags;
713 int ret;
714
715 if (!ep) {
716 pr_debug("dwc3: invalid parameters\n");
717 return -EINVAL;
718 }
719
720 dep = to_dwc3_ep(ep);
721 dwc = dep->dwc;
722
95ca961c
FB		 723 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
724 "%s is already disabled\n",
725 dep->name))
72246da4 726 return 0;
72246da4 727
72246da4
FB		 728 spin_lock_irqsave(&dwc->lock, flags);
729 ret = __dwc3_gadget_ep_disable(dep);
730 spin_unlock_irqrestore(&dwc->lock, flags);
731
732 return ret;
733}
734
735static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
736 gfp_t gfp_flags)
737{
738 struct dwc3_request *req;
739 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4
FB		 740
741 req = kzalloc(sizeof(*req), gfp_flags);
734d5a53 742 if (!req)
72246da4 743 return NULL;
72246da4
FB		 744
745 req->epnum = dep->number;
746 req->dep = dep;
72246da4 747
2c4cbe6e
FB		 748 trace_dwc3_alloc_request(req);
749
72246da4
FB		 750 return &req->request;
751}
752
753static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
754 struct usb_request *request)
755{
756 struct dwc3_request *req = to_dwc3_request(request);
757
2c4cbe6e 758 trace_dwc3_free_request(req);
72246da4
FB		 759 kfree(req);
760}
761
c71fc37c
FB		 762/**
763 * dwc3_prepare_one_trb - setup one TRB from one request
764 * @dep: endpoint for which this request is prepared
765 * @req: dwc3_request pointer
766 */
68e823e2 767static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
eeb720fb 768 struct dwc3_request *req, dma_addr_t dma,
e5ba5ec8 769 unsigned length, unsigned last, unsigned chain, unsigned node)
c71fc37c 770{
f6bafc6a 771 struct dwc3_trb *trb;
c71fc37c 772
73815280 773 dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
eeb720fb
FB		 774 dep->name, req, (unsigned long long) dma,
775 length, last ? " last" : "",
776 chain ? " chain" : "");
777
915e202a 778
4faf7550 779 trb = &dep->trb_pool[dep->trb_enqueue];
c71fc37c 780
eeb720fb 781 if (!req->trb) {
aa3342c8 782 dwc3_gadget_move_started_request(req);
f6bafc6a
FB		 783 req->trb = trb;
784 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
4faf7550 785 req->first_trb_index = dep->trb_enqueue;
eeb720fb 786 }
c71fc37c 787
ef966b9d 788 dwc3_ep_inc_enq(dep);
e5ba5ec8 789
f6bafc6a
FB		 790 trb->size = DWC3_TRB_SIZE_LENGTH(length);
791 trb->bpl = lower_32_bits(dma);
792 trb->bph = upper_32_bits(dma);
c71fc37c 793
16e78db7 794 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 795 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 796 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 797 break;
798
799 case USB_ENDPOINT_XFER_ISOC:
e5ba5ec8
PA		 800 if (!node)
801 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
802 else
803 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
ca4d44ea
FB		 804
805 /* always enable Interrupt on Missed ISOC */
806 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
c71fc37c
FB		 807 break;
808
809 case USB_ENDPOINT_XFER_BULK:
810 case USB_ENDPOINT_XFER_INT:
f6bafc6a 811 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 812 break;
813 default:
814 /*
815 * This is only possible with faulty memory because we
816 * checked it already :)
817 */
818 BUG();
819 }
820
ca4d44ea
FB		 821 /* always enable Continue on Short Packet */
822 trb->ctrl |= DWC3_TRB_CTRL_CSP;
f3af3651 823
f3af3651 824 if (!req->request.no_interrupt && !chain)
ca4d44ea 825 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
f3af3651 826
ca4d44ea 827 if (last)
e5ba5ec8 828 trb->ctrl |= DWC3_TRB_CTRL_LST;
c71fc37c 829
e5ba5ec8
PA		 830 if (chain)
831 trb->ctrl |= DWC3_TRB_CTRL_CHN;
832
16e78db7 833 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
f6bafc6a 834 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
c71fc37c 835
f6bafc6a 836 trb->ctrl |= DWC3_TRB_CTRL_HWO;
2c4cbe6e
FB		 837
838 trace_dwc3_prepare_trb(dep, trb);
c71fc37c
FB		 839}
840
c4233573
FB		 841static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
842{
843 struct dwc3_trb *tmp;
844
845 /*
846 * If enqueue & dequeue are equal than it is either full or empty.
847 *
848 * One way to know for sure is if the TRB right before us has HWO bit
849 * set or not. If it has, then we're definitely full and can't fit any
850 * more transfers in our ring.
851 */
852 if (dep->trb_enqueue == dep->trb_dequeue) {
853 /* If we're full, enqueue/dequeue are > 0 */
854 if (dep->trb_enqueue) {
855 tmp = &dep->trb_pool[dep->trb_enqueue - 1];
856 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
857 return 0;
858 }
859
860 return DWC3_TRB_NUM - 1;
861 }
862
863 return dep->trb_dequeue - dep->trb_enqueue;
864}
865
5ee85d89
FB		 866static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
867 struct dwc3_request *req, unsigned int trbs_left)
868{
869 struct usb_request *request = &req->request;
870 struct scatterlist *sg = request->sg;
871 struct scatterlist *s;
872 unsigned int last = false;
873 unsigned int length;
874 dma_addr_t dma;
875 int i;
876
877 for_each_sg(sg, s, request->num_mapped_sgs, i) {
878 unsigned chain = true;
879
880 length = sg_dma_len(s);
881 dma = sg_dma_address(s);
882
883 if (sg_is_last(s)) {
884 if (list_is_last(&req->list, &dep->pending_list))
885 last = true;
886
887 chain = false;
888 }
889
890 if (!trbs_left)
891 last = true;
892
893 if (last)
894 chain = false;
895
896 dwc3_prepare_one_trb(dep, req, dma, length,
897 last, chain, i);
898
899 if (last)
900 break;
901 }
902}
903
904static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
905 struct dwc3_request *req, unsigned int trbs_left)
906{
907 unsigned int last = false;
908 unsigned int length;
909 dma_addr_t dma;
910
911 dma = req->request.dma;
912 length = req->request.length;
913
914 if (!trbs_left)
915 last = true;
916
917 /* Is this the last request? */
918 if (list_is_last(&req->list, &dep->pending_list))
919 last = true;
920
921 dwc3_prepare_one_trb(dep, req, dma, length,
922 last, false, 0);
923}
924
72246da4
FB		 925/*
926 * dwc3_prepare_trbs - setup TRBs from requests
927 * @dep: endpoint for which requests are being prepared
72246da4 928 *
1d046793
PZ		 929 * The function goes through the requests list and sets up TRBs for the
930 * transfers. The function returns once there are no more TRBs available or
931 * it runs out of requests.
72246da4 932 */
c4233573 933static void dwc3_prepare_trbs(struct dwc3_ep *dep)
72246da4 934{
68e823e2 935 struct dwc3_request *req, *n;
72246da4
FB		 936 u32 trbs_left;
937
938 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
939
c4233573 940 trbs_left = dwc3_calc_trbs_left(dep);
72246da4 941
aa3342c8 942 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
5ee85d89
FB		 943 if (req->request.num_mapped_sgs > 0)
944 dwc3_prepare_one_trb_sg(dep, req, trbs_left--);
945 else
946 dwc3_prepare_one_trb_linear(dep, req, trbs_left--);
72246da4 947
5ee85d89
FB		 948 if (!trbs_left)
949 return;
72246da4 950 }
72246da4
FB		 951}
952
4fae2e3e 953static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
72246da4
FB		 954{
955 struct dwc3_gadget_ep_cmd_params params;
956 struct dwc3_request *req;
957 struct dwc3 *dwc = dep->dwc;
4fae2e3e 958 int starting;
72246da4
FB		 959 int ret;
960 u32 cmd;
961
4fae2e3e 962 starting = !(dep->flags & DWC3_EP_BUSY);
72246da4 963
4fae2e3e
FB		 964 dwc3_prepare_trbs(dep);
965 req = next_request(&dep->started_list);
72246da4
FB		 966 if (!req) {
967 dep->flags |= DWC3_EP_PENDING_REQUEST;
968 return 0;
969 }
970
971 memset(&params, 0, sizeof(params));
72246da4 972
4fae2e3e 973 if (starting) {
1877d6c9
PA		 974 params.param0 = upper_32_bits(req->trb_dma);
975 params.param1 = lower_32_bits(req->trb_dma);
72246da4 976 cmd = DWC3_DEPCMD_STARTTRANSFER;
1877d6c9 977 } else {
72246da4 978 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1877d6c9 979 }
72246da4
FB		 980
981 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
2cd4718d 982 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
72246da4 983 if (ret < 0) {
72246da4
FB		 984 /*
985 * FIXME we need to iterate over the list of requests
986 * here and stop, unmap, free and del each of the linked
1d046793 987 * requests instead of what we do now.
72246da4 988 */
0fc9a1be
FB		 989 usb_gadget_unmap_request(&dwc->gadget, &req->request,
990 req->direction);
72246da4
FB		 991 list_del(&req->list);
992 return ret;
993 }
994
995 dep->flags |= DWC3_EP_BUSY;
25b8ff68 996
4fae2e3e 997 if (starting) {
2eb88016 998 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
b4996a86 999 WARN_ON_ONCE(!dep->resource_index);
f898ae09 1000 }
25b8ff68 1001
72246da4
FB		 1002 return 0;
1003}
1004
d6d6ec7b
PA		 1005static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1006 struct dwc3_ep *dep, u32 cur_uf)
1007{
1008 u32 uf;
1009
aa3342c8 1010 if (list_empty(&dep->pending_list)) {
73815280
FB		 1011 dwc3_trace(trace_dwc3_gadget,
1012 "ISOC ep %s run out for requests",
1013 dep->name);
f4a53c55 1014 dep->flags |= DWC3_EP_PENDING_REQUEST;
d6d6ec7b
PA		 1015 return;
1016 }
1017
1018 /* 4 micro frames in the future */
1019 uf = cur_uf + dep->interval * 4;
1020
4fae2e3e 1021 __dwc3_gadget_kick_transfer(dep, uf);
d6d6ec7b
PA		 1022}
1023
1024static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1025 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1026{
1027 u32 cur_uf, mask;
1028
1029 mask = ~(dep->interval - 1);
1030 cur_uf = event->parameters & mask;
1031
1032 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1033}
1034
72246da4
FB		 1035static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1036{
0fc9a1be
FB		 1037 struct dwc3 *dwc = dep->dwc;
1038 int ret;
1039
bb423984 1040 if (!dep->endpoint.desc) {
ec5e795c
FB		 1041 dwc3_trace(trace_dwc3_gadget,
1042 "trying to queue request %p to disabled %s\n",
bb423984
FB		 1043 &req->request, dep->endpoint.name);
1044 return -ESHUTDOWN;
1045 }
1046
1047 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1048 &req->request, req->dep->name)) {
ec5e795c
FB		 1049 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1050 &req->request, req->dep->name);
bb423984
FB		 1051 return -EINVAL;
1052 }
1053
fc8bb91b
FB		 1054 pm_runtime_get(dwc->dev);
1055
72246da4
FB		 1056 req->request.actual = 0;
1057 req->request.status = -EINPROGRESS;
1058 req->direction = dep->direction;
1059 req->epnum = dep->number;
1060
fe84f522
FB		 1061 trace_dwc3_ep_queue(req);
1062
72246da4
FB		 1063 /*
1064 * We only add to our list of requests now and
1065 * start consuming the list once we get XferNotReady
1066 * IRQ.
1067 *
1068 * That way, we avoid doing anything that we don't need
1069 * to do now and defer it until the point we receive a
1070 * particular token from the Host side.
1071 *
1072 * This will also avoid Host cancelling URBs due to too
1d046793 1073 * many NAKs.
72246da4 1074 */
0fc9a1be
FB		 1075 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1076 dep->direction);
1077 if (ret)
1078 return ret;
1079
aa3342c8 1080 list_add_tail(&req->list, &dep->pending_list);
72246da4 1081
1d6a3918
FB		 1082 /*
1083 * If there are no pending requests and the endpoint isn't already
1084 * busy, we will just start the request straight away.
1085 *
1086 * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1087 * little bit faster.
1088 */
1089 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
62e345ae 1090 !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1d6a3918 1091 !(dep->flags & DWC3_EP_BUSY)) {
4fae2e3e 1092 ret = __dwc3_gadget_kick_transfer(dep, 0);
a8f32817 1093 goto out;
1d6a3918
FB		 1094 }
1095
72246da4 1096 /*
b511e5e7 1097 * There are a few special cases:
72246da4 1098 *
f898ae09
PZ		 1099 * 1. XferNotReady with empty list of requests. We need to kick the
1100 * transfer here in that situation, otherwise we will be NAKing
1101 * forever. If we get XferNotReady before gadget driver has a
1102 * chance to queue a request, we will ACK the IRQ but won't be
1103 * able to receive the data until the next request is queued.
1104 * The following code is handling exactly that.
72246da4 1105 *
72246da4
FB		 1106 */
1107 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
f4a53c55
PA		 1108 /*
1109 * If xfernotready is already elapsed and it is a case
1110 * of isoc transfer, then issue END TRANSFER, so that
1111 * you can receive xfernotready again and can have
1112 * notion of current microframe.
1113 */
1114 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
aa3342c8 1115 if (list_empty(&dep->started_list)) {
b992e681 1116 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 1117 dep->flags = DWC3_EP_ENABLED;
1118 }
f4a53c55
PA		 1119 return 0;
1120 }
1121
4fae2e3e 1122 ret = __dwc3_gadget_kick_transfer(dep, 0);
89185916
FB		 1123 if (!ret)
1124 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1125
a8f32817 1126 goto out;
b511e5e7 1127 }
72246da4 1128
b511e5e7
FB		 1129 /*
1130 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1131 * kick the transfer here after queuing a request, otherwise the
1132 * core may not see the modified TRB(s).
1133 */
1134 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
79c9046e
PA		 1135 (dep->flags & DWC3_EP_BUSY) &&
1136 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
b4996a86 1137 WARN_ON_ONCE(!dep->resource_index);
4fae2e3e 1138 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index);
a8f32817 1139 goto out;
a0925324 1140 }
72246da4 1141
b997ada5
FB		 1142 /*
1143 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1144 * right away, otherwise host will not know we have streams to be
1145 * handled.
1146 */
a8f32817 1147 if (dep->stream_capable)
4fae2e3e 1148 ret = __dwc3_gadget_kick_transfer(dep, 0);
b997ada5 1149
a8f32817
FB		 1150out:
1151 if (ret && ret != -EBUSY)
ec5e795c
FB		 1152 dwc3_trace(trace_dwc3_gadget,
1153 "%s: failed to kick transfers\n",
a8f32817
FB		 1154 dep->name);
1155 if (ret == -EBUSY)
1156 ret = 0;
1157
1158 return ret;
72246da4
FB		 1159}
1160
04c03d10
FB		 1161static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1162 struct usb_request *request)
1163{
1164 dwc3_gadget_ep_free_request(ep, request);
1165}
1166
1167static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1168{
1169 struct dwc3_request *req;
1170 struct usb_request *request;
1171 struct usb_ep *ep = &dep->endpoint;
1172
1173 dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1174 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1175 if (!request)
1176 return -ENOMEM;
1177
1178 request->length = 0;
1179 request->buf = dwc->zlp_buf;
1180 request->complete = __dwc3_gadget_ep_zlp_complete;
1181
1182 req = to_dwc3_request(request);
1183
1184 return __dwc3_gadget_ep_queue(dep, req);
1185}
1186
72246da4
FB		 1187static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1188 gfp_t gfp_flags)
1189{
1190 struct dwc3_request *req = to_dwc3_request(request);
1191 struct dwc3_ep *dep = to_dwc3_ep(ep);
1192 struct dwc3 *dwc = dep->dwc;
1193
1194 unsigned long flags;
1195
1196 int ret;
1197
fdee4eba 1198 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1199 ret = __dwc3_gadget_ep_queue(dep, req);
04c03d10
FB		 1200
1201 /*
1202 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1203 * setting request->zero, instead of doing magic, we will just queue an
1204 * extra usb_request ourselves so that it gets handled the same way as
1205 * any other request.
1206 */
d9261898
JY		 1207 if (ret == 0 && request->zero && request->length &&
1208 (request->length % ep->maxpacket == 0))
04c03d10
FB		 1209 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1210
72246da4
FB		 1211 spin_unlock_irqrestore(&dwc->lock, flags);
1212
1213 return ret;
1214}
1215
1216static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1217 struct usb_request *request)
1218{
1219 struct dwc3_request *req = to_dwc3_request(request);
1220 struct dwc3_request *r = NULL;
1221
1222 struct dwc3_ep *dep = to_dwc3_ep(ep);
1223 struct dwc3 *dwc = dep->dwc;
1224
1225 unsigned long flags;
1226 int ret = 0;
1227
2c4cbe6e
FB		 1228 trace_dwc3_ep_dequeue(req);
1229
72246da4
FB		 1230 spin_lock_irqsave(&dwc->lock, flags);
1231
aa3342c8 1232 list_for_each_entry(r, &dep->pending_list, list) {
72246da4
FB		 1233 if (r == req)
1234 break;
1235 }
1236
1237 if (r != req) {
aa3342c8 1238 list_for_each_entry(r, &dep->started_list, list) {
72246da4
FB		 1239 if (r == req)
1240 break;
1241 }
1242 if (r == req) {
1243 /* wait until it is processed */
b992e681 1244 dwc3_stop_active_transfer(dwc, dep->number, true);
e8d4e8be 1245 goto out1;
72246da4
FB		 1246 }
1247 dev_err(dwc->dev, "request %p was not queued to %s\n",
1248 request, ep->name);
1249 ret = -EINVAL;
1250 goto out0;
1251 }
1252
e8d4e8be 1253out1:
72246da4
FB		 1254 /* giveback the request */
1255 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1256
1257out0:
1258 spin_unlock_irqrestore(&dwc->lock, flags);
1259
1260 return ret;
1261}
1262
7a608559 1263int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
72246da4
FB		 1264{
1265 struct dwc3_gadget_ep_cmd_params params;
1266 struct dwc3 *dwc = dep->dwc;
1267 int ret;
1268
5ad02fb8
FB		 1269 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1270 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1271 return -EINVAL;
1272 }
1273
72246da4
FB		 1274 memset(&params, 0x00, sizeof(params));
1275
1276 if (value) {
7a608559 1277 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
aa3342c8
FB		 1278 (!list_empty(&dep->started_list) ||
1279 !list_empty(&dep->pending_list)))) {
ec5e795c 1280 dwc3_trace(trace_dwc3_gadget,
052ba52e 1281 "%s: pending request, cannot halt",
7a608559
FB		 1282 dep->name);
1283 return -EAGAIN;
1284 }
1285
2cd4718d
FB		 1286 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1287 &params);
72246da4 1288 if (ret)
3f89204b 1289 dev_err(dwc->dev, "failed to set STALL on %s\n",
72246da4
FB		 1290 dep->name);
1291 else
1292 dep->flags |= DWC3_EP_STALL;
1293 } else {
2cd4718d 1294
50c763f8 1295 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4 1296 if (ret)
3f89204b 1297 dev_err(dwc->dev, "failed to clear STALL on %s\n",
72246da4
FB		 1298 dep->name);
1299 else
a535d81c 1300 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
72246da4 1301 }
5275455a 1302
72246da4
FB		 1303 return ret;
1304}
1305
1306static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1307{
1308 struct dwc3_ep *dep = to_dwc3_ep(ep);
1309 struct dwc3 *dwc = dep->dwc;
1310
1311 unsigned long flags;
1312
1313 int ret;
1314
1315 spin_lock_irqsave(&dwc->lock, flags);
7a608559 1316 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
72246da4
FB		 1317 spin_unlock_irqrestore(&dwc->lock, flags);
1318
1319 return ret;
1320}
1321
1322static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1323{
1324 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1325 struct dwc3 *dwc = dep->dwc;
1326 unsigned long flags;
95aa4e8d 1327 int ret;
72246da4 1328
249a4569 1329 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1330 dep->flags |= DWC3_EP_WEDGE;
1331
08f0d966 1332 if (dep->number == 0 || dep->number == 1)
95aa4e8d 1333 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
08f0d966 1334 else
7a608559 1335 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
95aa4e8d
FB		 1336 spin_unlock_irqrestore(&dwc->lock, flags);
1337
1338 return ret;
72246da4
FB		 1339}
1340
1341/* -------------------------------------------------------------------------- */
1342
1343static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1344 .bLength = USB_DT_ENDPOINT_SIZE,
1345 .bDescriptorType = USB_DT_ENDPOINT,
1346 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1347};
1348
1349static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1350 .enable = dwc3_gadget_ep0_enable,
1351 .disable = dwc3_gadget_ep0_disable,
1352 .alloc_request = dwc3_gadget_ep_alloc_request,
1353 .free_request = dwc3_gadget_ep_free_request,
1354 .queue = dwc3_gadget_ep0_queue,
1355 .dequeue = dwc3_gadget_ep_dequeue,
08f0d966 1356 .set_halt = dwc3_gadget_ep0_set_halt,
72246da4
FB		 1357 .set_wedge = dwc3_gadget_ep_set_wedge,
1358};
1359
1360static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1361 .enable = dwc3_gadget_ep_enable,
1362 .disable = dwc3_gadget_ep_disable,
1363 .alloc_request = dwc3_gadget_ep_alloc_request,
1364 .free_request = dwc3_gadget_ep_free_request,
1365 .queue = dwc3_gadget_ep_queue,
1366 .dequeue = dwc3_gadget_ep_dequeue,
1367 .set_halt = dwc3_gadget_ep_set_halt,
1368 .set_wedge = dwc3_gadget_ep_set_wedge,
1369};
1370
1371/* -------------------------------------------------------------------------- */
1372
1373static int dwc3_gadget_get_frame(struct usb_gadget *g)
1374{
1375 struct dwc3 *dwc = gadget_to_dwc(g);
1376 u32 reg;
1377
1378 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1379 return DWC3_DSTS_SOFFN(reg);
1380}
1381
218ef7b6 1382static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
72246da4 1383{
72246da4 1384 unsigned long timeout;
72246da4 1385
218ef7b6 1386 int ret;
72246da4
FB		 1387 u32 reg;
1388
72246da4
FB		 1389 u8 link_state;
1390 u8 speed;
1391
72246da4
FB		 1392 /*
1393 * According to the Databook Remote wakeup request should
1394 * be issued only when the device is in early suspend state.
1395 *
1396 * We can check that via USB Link State bits in DSTS register.
1397 */
1398 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1399
1400 speed = reg & DWC3_DSTS_CONNECTSPD;
ee5cd41c
JY		 1401 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1402 (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
ec5e795c 1403 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
6b742899 1404 return 0;
72246da4
FB		 1405 }
1406
1407 link_state = DWC3_DSTS_USBLNKST(reg);
1408
1409 switch (link_state) {
1410 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1411 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1412 break;
1413 default:
ec5e795c
FB		 1414 dwc3_trace(trace_dwc3_gadget,
1415 "can't wakeup from '%s'\n",
1416 dwc3_gadget_link_string(link_state));
218ef7b6 1417 return -EINVAL;
72246da4
FB		 1418 }
1419
8598bde7
FB		 1420 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1421 if (ret < 0) {
1422 dev_err(dwc->dev, "failed to put link in Recovery\n");
218ef7b6 1423 return ret;
8598bde7 1424 }
72246da4 1425
802fde98
PZ		 1426 /* Recent versions do this automatically */
1427 if (dwc->revision < DWC3_REVISION_194A) {
1428 /* write zeroes to Link Change Request */
fcc023c7 1429 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1430 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1431 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1432 }
72246da4 1433
1d046793 1434 /* poll until Link State changes to ON */
72246da4
FB		 1435 timeout = jiffies + msecs_to_jiffies(100);
1436
1d046793 1437 while (!time_after(jiffies, timeout)) {
72246da4
FB		 1438 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1439
1440 /* in HS, means ON */
1441 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1442 break;
1443 }
1444
1445 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1446 dev_err(dwc->dev, "failed to send remote wakeup\n");
218ef7b6 1447 return -EINVAL;
72246da4
FB		 1448 }
1449
218ef7b6
FB		 1450 return 0;
1451}
1452
1453static int dwc3_gadget_wakeup(struct usb_gadget *g)
1454{
1455 struct dwc3 *dwc = gadget_to_dwc(g);
1456 unsigned long flags;
1457 int ret;
1458
1459 spin_lock_irqsave(&dwc->lock, flags);
1460 ret = __dwc3_gadget_wakeup(dwc);
72246da4
FB		 1461 spin_unlock_irqrestore(&dwc->lock, flags);
1462
1463 return ret;
1464}
1465
1466static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1467 int is_selfpowered)
1468{
1469 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1470 unsigned long flags;
72246da4 1471
249a4569 1472 spin_lock_irqsave(&dwc->lock, flags);
bcdea503 1473 g->is_selfpowered = !!is_selfpowered;
249a4569 1474 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1475
1476 return 0;
1477}
1478
7b2a0368 1479static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
72246da4
FB		 1480{
1481 u32 reg;
61d58242 1482 u32 timeout = 500;
72246da4 1483
fc8bb91b
FB		 1484 if (pm_runtime_suspended(dwc->dev))
1485 return 0;
1486
72246da4 1487 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1488 if (is_on) {
802fde98
PZ		 1489 if (dwc->revision <= DWC3_REVISION_187A) {
1490 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1491 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1492 }
1493
1494 if (dwc->revision >= DWC3_REVISION_194A)
1495 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1496 reg |= DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1497
1498 if (dwc->has_hibernation)
1499 reg |= DWC3_DCTL_KEEP_CONNECT;
1500
9fcb3bd8 1501 dwc->pullups_connected = true;
8db7ed15 1502 } else {
72246da4 1503 reg &= ~DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1504
1505 if (dwc->has_hibernation && !suspend)
1506 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1507
9fcb3bd8 1508 dwc->pullups_connected = false;
8db7ed15 1509 }
72246da4
FB		 1510
1511 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1512
1513 do {
1514 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1515 if (is_on) {
1516 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1517 break;
1518 } else {
1519 if (reg & DWC3_DSTS_DEVCTRLHLT)
1520 break;
1521 }
72246da4
FB		 1522 timeout--;
1523 if (!timeout)
6f17f74b 1524 return -ETIMEDOUT;
61d58242 1525 udelay(1);
72246da4
FB		 1526 } while (1);
1527
73815280 1528 dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
72246da4
FB		 1529 dwc->gadget_driver
1530 ? dwc->gadget_driver->function : "no-function",
1531 is_on ? "connect" : "disconnect");
6f17f74b
PA		 1532
1533 return 0;
72246da4
FB		 1534}
1535
1536static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1537{
1538 struct dwc3 *dwc = gadget_to_dwc(g);
1539 unsigned long flags;
6f17f74b 1540 int ret;
72246da4
FB		 1541
1542 is_on = !!is_on;
1543
1544 spin_lock_irqsave(&dwc->lock, flags);
7b2a0368 1545 ret = dwc3_gadget_run_stop(dwc, is_on, false);
72246da4
FB		 1546 spin_unlock_irqrestore(&dwc->lock, flags);
1547
6f17f74b 1548 return ret;
72246da4
FB		 1549}
1550
8698e2ac
FB		 1551static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1552{
1553 u32 reg;
1554
1555 /* Enable all but Start and End of Frame IRQs */
1556 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1557 DWC3_DEVTEN_EVNTOVERFLOWEN |
1558 DWC3_DEVTEN_CMDCMPLTEN |
1559 DWC3_DEVTEN_ERRTICERREN |
1560 DWC3_DEVTEN_WKUPEVTEN |
1561 DWC3_DEVTEN_ULSTCNGEN |
1562 DWC3_DEVTEN_CONNECTDONEEN |
1563 DWC3_DEVTEN_USBRSTEN |
1564 DWC3_DEVTEN_DISCONNEVTEN);
1565
1566 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1567}
1568
1569static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1570{
1571 /* mask all interrupts */
1572 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1573}
1574
1575static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
b15a762f 1576static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
8698e2ac 1577
4e99472b
FB		 1578/**
1579 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1580 * dwc: pointer to our context structure
1581 *
1582 * The following looks like complex but it's actually very simple. In order to
1583 * calculate the number of packets we can burst at once on OUT transfers, we're
1584 * gonna use RxFIFO size.
1585 *
1586 * To calculate RxFIFO size we need two numbers:
1587 * MDWIDTH = size, in bits, of the internal memory bus
1588 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1589 *
1590 * Given these two numbers, the formula is simple:
1591 *
1592 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1593 *
1594 * 24 bytes is for 3x SETUP packets
1595 * 16 bytes is a clock domain crossing tolerance
1596 *
1597 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1598 */
1599static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1600{
1601 u32 ram2_depth;
1602 u32 mdwidth;
1603 u32 nump;
1604 u32 reg;
1605
1606 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1607 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1608
1609 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1610 nump = min_t(u32, nump, 16);
1611
1612 /* update NumP */
1613 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1614 reg &= ~DWC3_DCFG_NUMP_MASK;
1615 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1616 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1617}
1618
d7be2952 1619static int __dwc3_gadget_start(struct dwc3 *dwc)
72246da4 1620{
72246da4 1621 struct dwc3_ep *dep;
72246da4
FB		 1622 int ret = 0;
1623 u32 reg;
1624
72246da4
FB		 1625 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1626 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1627
1628 /**
1629 * WORKAROUND: DWC3 revision < 2.20a have an issue
1630 * which would cause metastability state on Run/Stop
1631 * bit if we try to force the IP to USB2-only mode.
1632 *
1633 * Because of that, we cannot configure the IP to any
1634 * speed other than the SuperSpeed
1635 *
1636 * Refers to:
1637 *
1638 * STAR#9000525659: Clock Domain Crossing on DCTL in
1639 * USB 2.0 Mode
1640 */
f7e846f0 1641 if (dwc->revision < DWC3_REVISION_220A) {
07e7f47b 1642 reg |= DWC3_DCFG_SUPERSPEED;
f7e846f0
FB		 1643 } else {
1644 switch (dwc->maximum_speed) {
1645 case USB_SPEED_LOW:
1646 reg |= DWC3_DSTS_LOWSPEED;
1647 break;
1648 case USB_SPEED_FULL:
1649 reg |= DWC3_DSTS_FULLSPEED1;
1650 break;
1651 case USB_SPEED_HIGH:
1652 reg |= DWC3_DSTS_HIGHSPEED;
1653 break;
7580862b
JY		 1654 case USB_SPEED_SUPER_PLUS:
1655 reg |= DWC3_DSTS_SUPERSPEED_PLUS;
1656 break;
f7e846f0 1657 default:
77966eb8
JY		 1658 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1659 dwc->maximum_speed);
1660 /* fall through */
1661 case USB_SPEED_SUPER:
1662 reg |= DWC3_DCFG_SUPERSPEED;
1663 break;
f7e846f0
FB		 1664 }
1665 }
72246da4
FB		 1666 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1667
2a58f9c1
FB		 1668 /*
1669 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1670 * field instead of letting dwc3 itself calculate that automatically.
1671 *
1672 * This way, we maximize the chances that we'll be able to get several
1673 * bursts of data without going through any sort of endpoint throttling.
1674 */
1675 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1676 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1677 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1678
4e99472b
FB		 1679 dwc3_gadget_setup_nump(dwc);
1680
72246da4
FB		 1681 /* Start with SuperSpeed Default */
1682 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1683
1684 dep = dwc->eps[0];
265b70a7
PZ		 1685 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1686 false);
72246da4
FB		 1687 if (ret) {
1688 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1689 goto err0;
72246da4
FB		 1690 }
1691
1692 dep = dwc->eps[1];
265b70a7
PZ		 1693 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1694 false);
72246da4
FB		 1695 if (ret) {
1696 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1697 goto err1;
72246da4
FB		 1698 }
1699
1700 /* begin to receive SETUP packets */
c7fcdeb2 1701 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1702 dwc3_ep0_out_start(dwc);
1703
8698e2ac
FB		 1704 dwc3_gadget_enable_irq(dwc);
1705
72246da4
FB		 1706 return 0;
1707
b0d7ffd4 1708err1:
d7be2952 1709 __dwc3_gadget_ep_disable(dwc->eps[0]);
b0d7ffd4
FB		 1710
1711err0:
72246da4
FB		 1712 return ret;
1713}
1714
d7be2952
FB		 1715static int dwc3_gadget_start(struct usb_gadget *g,
1716 struct usb_gadget_driver *driver)
72246da4
FB		 1717{
1718 struct dwc3 *dwc = gadget_to_dwc(g);
1719 unsigned long flags;
d7be2952 1720 int ret = 0;
8698e2ac 1721 int irq;
72246da4 1722
d7be2952
FB		 1723 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1724 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1725 IRQF_SHARED, "dwc3", dwc->ev_buf);
1726 if (ret) {
1727 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1728 irq, ret);
1729 goto err0;
1730 }
3f308d17 1731 dwc->irq_gadget = irq;
d7be2952 1732
72246da4 1733 spin_lock_irqsave(&dwc->lock, flags);
d7be2952
FB		 1734 if (dwc->gadget_driver) {
1735 dev_err(dwc->dev, "%s is already bound to %s\n",
1736 dwc->gadget.name,
1737 dwc->gadget_driver->driver.name);
1738 ret = -EBUSY;
1739 goto err1;
1740 }
1741
1742 dwc->gadget_driver = driver;
1743
fc8bb91b
FB		 1744 if (pm_runtime_active(dwc->dev))
1745 __dwc3_gadget_start(dwc);
1746
d7be2952
FB		 1747 spin_unlock_irqrestore(&dwc->lock, flags);
1748
1749 return 0;
1750
1751err1:
1752 spin_unlock_irqrestore(&dwc->lock, flags);
1753 free_irq(irq, dwc);
1754
1755err0:
1756 return ret;
1757}
72246da4 1758
d7be2952
FB		 1759static void __dwc3_gadget_stop(struct dwc3 *dwc)
1760{
8698e2ac 1761 dwc3_gadget_disable_irq(dwc);
72246da4
FB		 1762 __dwc3_gadget_ep_disable(dwc->eps[0]);
1763 __dwc3_gadget_ep_disable(dwc->eps[1]);
d7be2952 1764}
72246da4 1765
d7be2952
FB		 1766static int dwc3_gadget_stop(struct usb_gadget *g)
1767{
1768 struct dwc3 *dwc = gadget_to_dwc(g);
1769 unsigned long flags;
72246da4 1770
d7be2952
FB		 1771 spin_lock_irqsave(&dwc->lock, flags);
1772 __dwc3_gadget_stop(dwc);
1773 dwc->gadget_driver = NULL;
72246da4
FB		 1774 spin_unlock_irqrestore(&dwc->lock, flags);
1775
3f308d17 1776 free_irq(dwc->irq_gadget, dwc->ev_buf);
b0d7ffd4 1777
72246da4
FB		 1778 return 0;
1779}
802fde98 1780
72246da4
FB		 1781static const struct usb_gadget_ops dwc3_gadget_ops = {
1782 .get_frame = dwc3_gadget_get_frame,
1783 .wakeup = dwc3_gadget_wakeup,
1784 .set_selfpowered = dwc3_gadget_set_selfpowered,
1785 .pullup = dwc3_gadget_pullup,
1786 .udc_start = dwc3_gadget_start,
1787 .udc_stop = dwc3_gadget_stop,
1788};
1789
1790/* -------------------------------------------------------------------------- */
1791
6a1e3ef4
FB		 1792static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1793 u8 num, u32 direction)
72246da4
FB		 1794{
1795 struct dwc3_ep *dep;
6a1e3ef4 1796 u8 i;
72246da4 1797
6a1e3ef4 1798 for (i = 0; i < num; i++) {
d07fa665 1799 u8 epnum = (i << 1) | (direction ? 1 : 0);
72246da4 1800
72246da4 1801 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
734d5a53 1802 if (!dep)
72246da4 1803 return -ENOMEM;
72246da4
FB		 1804
1805 dep->dwc = dwc;
1806 dep->number = epnum;
9aa62ae4 1807 dep->direction = !!direction;
2eb88016 1808 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
72246da4
FB		 1809 dwc->eps[epnum] = dep;
1810
1811 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1812 (epnum & 1) ? "in" : "out");
6a1e3ef4 1813
72246da4 1814 dep->endpoint.name = dep->name;
74674cbf 1815 spin_lock_init(&dep->lock);
72246da4 1816
73815280 1817 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
653df35e 1818
72246da4 1819 if (epnum == 0 || epnum == 1) {
e117e742 1820 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
6048e4c6 1821 dep->endpoint.maxburst = 1;
72246da4
FB		 1822 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1823 if (!epnum)
1824 dwc->gadget.ep0 = &dep->endpoint;
1825 } else {
1826 int ret;
1827
e117e742 1828 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
12d36c16 1829 dep->endpoint.max_streams = 15;
72246da4
FB		 1830 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1831 list_add_tail(&dep->endpoint.ep_list,
1832 &dwc->gadget.ep_list);
1833
1834 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 1835 if (ret)
72246da4 1836 return ret;
72246da4 1837 }
25b8ff68 1838
a474d3b7
RB		 1839 if (epnum == 0 || epnum == 1) {
1840 dep->endpoint.caps.type_control = true;
1841 } else {
1842 dep->endpoint.caps.type_iso = true;
1843 dep->endpoint.caps.type_bulk = true;
1844 dep->endpoint.caps.type_int = true;
1845 }
1846
1847 dep->endpoint.caps.dir_in = !!direction;
1848 dep->endpoint.caps.dir_out = !direction;
1849
aa3342c8
FB		 1850 INIT_LIST_HEAD(&dep->pending_list);
1851 INIT_LIST_HEAD(&dep->started_list);
72246da4
FB		 1852 }
1853
1854 return 0;
1855}
1856
6a1e3ef4
FB		 1857static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1858{
1859 int ret;
1860
1861 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1862
1863 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1864 if (ret < 0) {
73815280
FB		 1865 dwc3_trace(trace_dwc3_gadget,
1866 "failed to allocate OUT endpoints");
6a1e3ef4
FB		 1867 return ret;
1868 }
1869
1870 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1871 if (ret < 0) {
73815280
FB		 1872 dwc3_trace(trace_dwc3_gadget,
1873 "failed to allocate IN endpoints");
6a1e3ef4
FB		 1874 return ret;
1875 }
1876
1877 return 0;
1878}
1879
72246da4
FB		 1880static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1881{
1882 struct dwc3_ep *dep;
1883 u8 epnum;
1884
1885 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1886 dep = dwc->eps[epnum];
6a1e3ef4
FB		 1887 if (!dep)
1888 continue;
5bf8fae3
GC		 1889 /*
1890 * Physical endpoints 0 and 1 are special; they form the
1891 * bi-directional USB endpoint 0.
1892 *
1893 * For those two physical endpoints, we don't allocate a TRB
1894 * pool nor do we add them the endpoints list. Due to that, we
1895 * shouldn't do these two operations otherwise we would end up
1896 * with all sorts of bugs when removing dwc3.ko.
1897 */
1898 if (epnum != 0 && epnum != 1) {
1899 dwc3_free_trb_pool(dep);
72246da4 1900 list_del(&dep->endpoint.ep_list);
5bf8fae3 1901 }
72246da4
FB		 1902
1903 kfree(dep);
1904 }
1905}
1906
72246da4 1907/* -------------------------------------------------------------------------- */
e5caff68 1908
e5ba5ec8
PA		 1909static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1910 struct dwc3_request *req, struct dwc3_trb *trb,
72246da4
FB		 1911 const struct dwc3_event_depevt *event, int status)
1912{
72246da4
FB		 1913 unsigned int count;
1914 unsigned int s_pkt = 0;
d6d6ec7b 1915 unsigned int trb_status;
72246da4 1916
2c4cbe6e
FB		 1917 trace_dwc3_complete_trb(dep, trb);
1918
e5ba5ec8
PA		 1919 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1920 /*
1921 * We continue despite the error. There is not much we
1922 * can do. If we don't clean it up we loop forever. If
1923 * we skip the TRB then it gets overwritten after a
1924 * while since we use them in a ring buffer. A BUG()
1925 * would help. Lets hope that if this occurs, someone
1926 * fixes the root cause instead of looking away :)
1927 */
1928 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1929 dep->name, trb);
1930 count = trb->size & DWC3_TRB_SIZE_MASK;
1931
1932 if (dep->direction) {
1933 if (count) {
1934 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1935 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
ec5e795c
FB		 1936 dwc3_trace(trace_dwc3_gadget,
1937 "%s: incomplete IN transfer\n",
e5ba5ec8
PA		 1938 dep->name);
1939 /*
1940 * If missed isoc occurred and there is
1941 * no request queued then issue END
1942 * TRANSFER, so that core generates
1943 * next xfernotready and we will issue
1944 * a fresh START TRANSFER.
1945 * If there are still queued request
1946 * then wait, do not issue either END
1947 * or UPDATE TRANSFER, just attach next
aa3342c8 1948 * request in pending_list during
e5ba5ec8
PA		 1949 * giveback.If any future queued request
1950 * is successfully transferred then we
1951 * will issue UPDATE TRANSFER for all
aa3342c8 1952 * request in the pending_list.
e5ba5ec8
PA		 1953 */
1954 dep->flags |= DWC3_EP_MISSED_ISOC;
1955 } else {
1956 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1957 dep->name);
1958 status = -ECONNRESET;
1959 }
1960 } else {
1961 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1962 }
1963 } else {
1964 if (count && (event->status & DEPEVT_STATUS_SHORT))
1965 s_pkt = 1;
1966 }
1967
1968 /*
1969 * We assume here we will always receive the entire data block
1970 * which we should receive. Meaning, if we program RX to
1971 * receive 4K but we receive only 2K, we assume that's all we
1972 * should receive and we simply bounce the request back to the
1973 * gadget driver for further processing.
1974 */
1975 req->request.actual += req->request.length - count;
1976 if (s_pkt)
1977 return 1;
1978 if ((event->status & DEPEVT_STATUS_LST) &&
1979 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1980 DWC3_TRB_CTRL_HWO)))
1981 return 1;
1982 if ((event->status & DEPEVT_STATUS_IOC) &&
1983 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1984 return 1;
1985 return 0;
1986}
1987
1988static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1989 const struct dwc3_event_depevt *event, int status)
1990{
1991 struct dwc3_request *req;
1992 struct dwc3_trb *trb;
1993 unsigned int slot;
1994 unsigned int i;
1995 int ret;
1996
72246da4 1997 do {
aa3342c8 1998 req = next_request(&dep->started_list);
ac7bdcc1 1999 if (WARN_ON_ONCE(!req))
d115d705 2000 return 1;
ac7bdcc1 2001
d115d705
VS		 2002 i = 0;
2003 do {
53fd8818 2004 slot = req->first_trb_index + i;
36b68aae 2005 if (slot == DWC3_TRB_NUM - 1)
d115d705
VS		 2006 slot++;
2007 slot %= DWC3_TRB_NUM;
2008 trb = &dep->trb_pool[slot];
2009
2010 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2011 event, status);
2012 if (ret)
2013 break;
2014 } while (++i < req->request.num_mapped_sgs);
2015
2016 dwc3_gadget_giveback(dep, req, status);
e5ba5ec8
PA		 2017
2018 if (ret)
72246da4 2019 break;
d115d705 2020 } while (1);
72246da4 2021
4cb42217
FB		 2022 /*
2023 * Our endpoint might get disabled by another thread during
2024 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2025 * early on so DWC3_EP_BUSY flag gets cleared
2026 */
2027 if (!dep->endpoint.desc)
2028 return 1;
2029
cdc359dd 2030 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
aa3342c8
FB		 2031 list_empty(&dep->started_list)) {
2032 if (list_empty(&dep->pending_list)) {
cdc359dd
PA		 2033 /*
2034 * If there is no entry in request list then do
2035 * not issue END TRANSFER now. Just set PENDING
2036 * flag, so that END TRANSFER is issued when an
2037 * entry is added into request list.
2038 */
2039 dep->flags = DWC3_EP_PENDING_REQUEST;
2040 } else {
b992e681 2041 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 2042 dep->flags = DWC3_EP_ENABLED;
2043 }
7efea86c
PA		 2044 return 1;
2045 }
2046
9cad39fe
KL		 2047 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
2048 if ((event->status & DEPEVT_STATUS_IOC) &&
2049 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2050 return 0;
72246da4
FB		 2051 return 1;
2052}
2053
2054static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
029d97ff 2055 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
72246da4
FB		 2056{
2057 unsigned status = 0;
2058 int clean_busy;
e18b7975
FB		 2059 u32 is_xfer_complete;
2060
2061 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
72246da4
FB		 2062
2063 if (event->status & DEPEVT_STATUS_BUSERR)
2064 status = -ECONNRESET;
2065
1d046793 2066 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
4cb42217 2067 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
e18b7975 2068 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
72246da4 2069 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 2070
2071 /*
2072 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2073 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2074 */
2075 if (dwc->revision < DWC3_REVISION_183A) {
2076 u32 reg;
2077 int i;
2078
2079 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
348e026f 2080 dep = dwc->eps[i];
fae2b904
FB		 2081
2082 if (!(dep->flags & DWC3_EP_ENABLED))
2083 continue;
2084
aa3342c8 2085 if (!list_empty(&dep->started_list))
fae2b904
FB		 2086 return;
2087 }
2088
2089 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2090 reg |= dwc->u1u2;
2091 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2092
2093 dwc->u1u2 = 0;
2094 }
8a1a9c9e 2095
4cb42217
FB		 2096 /*
2097 * Our endpoint might get disabled by another thread during
2098 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2099 * early on so DWC3_EP_BUSY flag gets cleared
2100 */
2101 if (!dep->endpoint.desc)
2102 return;
2103
e6e709b7 2104 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8a1a9c9e
FB		 2105 int ret;
2106
4fae2e3e 2107 ret = __dwc3_gadget_kick_transfer(dep, 0);
8a1a9c9e
FB		 2108 if (!ret || ret == -EBUSY)
2109 return;
2110 }
72246da4
FB		 2111}
2112
72246da4
FB		 2113static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2114 const struct dwc3_event_depevt *event)
2115{
2116 struct dwc3_ep *dep;
2117 u8 epnum = event->endpoint_number;
2118
2119 dep = dwc->eps[epnum];
2120
3336abb5
FB		 2121 if (!(dep->flags & DWC3_EP_ENABLED))
2122 return;
2123
72246da4
FB		 2124 if (epnum == 0 || epnum == 1) {
2125 dwc3_ep0_interrupt(dwc, event);
2126 return;
2127 }
2128
2129 switch (event->endpoint_event) {
2130 case DWC3_DEPEVT_XFERCOMPLETE:
b4996a86 2131 dep->resource_index = 0;
c2df85ca 2132
16e78db7 2133 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
ec5e795c
FB		 2134 dwc3_trace(trace_dwc3_gadget,
2135 "%s is an Isochronous endpoint\n",
72246da4
FB		 2136 dep->name);
2137 return;
2138 }
2139
029d97ff 2140 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2141 break;
2142 case DWC3_DEPEVT_XFERINPROGRESS:
029d97ff 2143 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2144 break;
2145 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 2146 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 2147 dwc3_gadget_start_isoc(dwc, dep, event);
2148 } else {
6bb4fe12 2149 int active;
72246da4
FB		 2150 int ret;
2151
6bb4fe12
FB		 2152 active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2153
73815280 2154 dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
6bb4fe12 2155 dep->name, active ? "Transfer Active"
72246da4
FB		 2156 : "Transfer Not Active");
2157
4fae2e3e 2158 ret = __dwc3_gadget_kick_transfer(dep, 0);
72246da4
FB		 2159 if (!ret || ret == -EBUSY)
2160 return;
2161
ec5e795c
FB		 2162 dwc3_trace(trace_dwc3_gadget,
2163 "%s: failed to kick transfers\n",
72246da4
FB		 2164 dep->name);
2165 }
2166
879631aa
FB		 2167 break;
2168 case DWC3_DEPEVT_STREAMEVT:
16e78db7 2169 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 2170 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2171 dep->name);
2172 return;
2173 }
2174
2175 switch (event->status) {
2176 case DEPEVT_STREAMEVT_FOUND:
73815280
FB		 2177 dwc3_trace(trace_dwc3_gadget,
2178 "Stream %d found and started",
879631aa
FB		 2179 event->parameters);
2180
2181 break;
2182 case DEPEVT_STREAMEVT_NOTFOUND:
2183 /* FALLTHROUGH */
2184 default:
ec5e795c
FB		 2185 dwc3_trace(trace_dwc3_gadget,
2186 "unable to find suitable stream\n");
879631aa 2187 }
72246da4
FB		 2188 break;
2189 case DWC3_DEPEVT_RXTXFIFOEVT:
ec5e795c 2190 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
72246da4 2191 break;
72246da4 2192 case DWC3_DEPEVT_EPCMDCMPLT:
73815280 2193 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
72246da4
FB		 2194 break;
2195 }
2196}
2197
2198static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2199{
2200 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2201 spin_unlock(&dwc->lock);
2202 dwc->gadget_driver->disconnect(&dwc->gadget);
2203 spin_lock(&dwc->lock);
2204 }
2205}
2206
bc5ba2e0
FB		 2207static void dwc3_suspend_gadget(struct dwc3 *dwc)
2208{
73a30bfc 2209 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
bc5ba2e0
FB		 2210 spin_unlock(&dwc->lock);
2211 dwc->gadget_driver->suspend(&dwc->gadget);
2212 spin_lock(&dwc->lock);
2213 }
2214}
2215
2216static void dwc3_resume_gadget(struct dwc3 *dwc)
2217{
73a30bfc 2218 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
bc5ba2e0
FB		 2219 spin_unlock(&dwc->lock);
2220 dwc->gadget_driver->resume(&dwc->gadget);
5c7b3b02 2221 spin_lock(&dwc->lock);
8e74475b
FB		 2222 }
2223}
2224
2225static void dwc3_reset_gadget(struct dwc3 *dwc)
2226{
2227 if (!dwc->gadget_driver)
2228 return;
2229
2230 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2231 spin_unlock(&dwc->lock);
2232 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
bc5ba2e0
FB		 2233 spin_lock(&dwc->lock);
2234 }
2235}
2236
b992e681 2237static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
72246da4
FB		 2238{
2239 struct dwc3_ep *dep;
2240 struct dwc3_gadget_ep_cmd_params params;
2241 u32 cmd;
2242 int ret;
2243
2244 dep = dwc->eps[epnum];
2245
b4996a86 2246 if (!dep->resource_index)
3daf74d7
PA		 2247 return;
2248
57911504
PA		 2249 /*
2250 * NOTICE: We are violating what the Databook says about the
2251 * EndTransfer command. Ideally we would _always_ wait for the
2252 * EndTransfer Command Completion IRQ, but that's causing too
2253 * much trouble synchronizing between us and gadget driver.
2254 *
2255 * We have discussed this with the IP Provider and it was
2256 * suggested to giveback all requests here, but give HW some
2257 * extra time to synchronize with the interconnect. We're using
dc93b41a 2258 * an arbitrary 100us delay for that.
57911504
PA		 2259 *
2260 * Note also that a similar handling was tested by Synopsys
2261 * (thanks a lot Paul) and nothing bad has come out of it.
2262 * In short, what we're doing is:
2263 *
2264 * - Issue EndTransfer WITH CMDIOC bit set
2265 * - Wait 100us
2266 */
2267
3daf74d7 2268 cmd = DWC3_DEPCMD_ENDTRANSFER;
b992e681
PZ		 2269 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2270 cmd |= DWC3_DEPCMD_CMDIOC;
b4996a86 2271 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3daf74d7 2272 memset(&params, 0, sizeof(params));
2cd4718d 2273 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
3daf74d7 2274 WARN_ON_ONCE(ret);
b4996a86 2275 dep->resource_index = 0;
041d81f4 2276 dep->flags &= ~DWC3_EP_BUSY;
57911504 2277 udelay(100);
72246da4
FB		 2278}
2279
2280static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2281{
2282 u32 epnum;
2283
2284 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2285 struct dwc3_ep *dep;
2286
2287 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2288 if (!dep)
2289 continue;
2290
72246da4
FB		 2291 if (!(dep->flags & DWC3_EP_ENABLED))
2292 continue;
2293
624407f9 2294 dwc3_remove_requests(dwc, dep);
72246da4
FB		 2295 }
2296}
2297
2298static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2299{
2300 u32 epnum;
2301
2302 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2303 struct dwc3_ep *dep;
72246da4
FB		 2304 int ret;
2305
2306 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2307 if (!dep)
2308 continue;
72246da4
FB		 2309
2310 if (!(dep->flags & DWC3_EP_STALL))
2311 continue;
2312
2313 dep->flags &= ~DWC3_EP_STALL;
2314
50c763f8 2315 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4
FB		 2316 WARN_ON_ONCE(ret);
2317 }
2318}
2319
2320static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2321{
c4430a26
FB		 2322 int reg;
2323
72246da4
FB		 2324 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2325 reg &= ~DWC3_DCTL_INITU1ENA;
2326 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2327
2328 reg &= ~DWC3_DCTL_INITU2ENA;
2329 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 2330
72246da4
FB		 2331 dwc3_disconnect_gadget(dwc);
2332
2333 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 2334 dwc->setup_packet_pending = false;
06a374ed 2335 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
fc8bb91b
FB		 2336
2337 dwc->connected = false;
72246da4
FB		 2338}
2339
72246da4
FB		 2340static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2341{
2342 u32 reg;
2343
fc8bb91b
FB		 2344 dwc->connected = true;
2345
df62df56
FB		 2346 /*
2347 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2348 * would cause a missing Disconnect Event if there's a
2349 * pending Setup Packet in the FIFO.
2350 *
2351 * There's no suggested workaround on the official Bug
2352 * report, which states that "unless the driver/application
2353 * is doing any special handling of a disconnect event,
2354 * there is no functional issue".
2355 *
2356 * Unfortunately, it turns out that we _do_ some special
2357 * handling of a disconnect event, namely complete all
2358 * pending transfers, notify gadget driver of the
2359 * disconnection, and so on.
2360 *
2361 * Our suggested workaround is to follow the Disconnect
2362 * Event steps here, instead, based on a setup_packet_pending
b5d335e5
FB		 2363 * flag. Such flag gets set whenever we have a SETUP_PENDING
2364 * status for EP0 TRBs and gets cleared on XferComplete for the
df62df56
FB		 2365 * same endpoint.
2366 *
2367 * Refers to:
2368 *
2369 * STAR#9000466709: RTL: Device : Disconnect event not
2370 * generated if setup packet pending in FIFO
2371 */
2372 if (dwc->revision < DWC3_REVISION_188A) {
2373 if (dwc->setup_packet_pending)
2374 dwc3_gadget_disconnect_interrupt(dwc);
2375 }
2376
8e74475b 2377 dwc3_reset_gadget(dwc);
72246da4
FB		 2378
2379 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2380 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2381 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2382 dwc->test_mode = false;
72246da4
FB		 2383
2384 dwc3_stop_active_transfers(dwc);
2385 dwc3_clear_stall_all_ep(dwc);
2386
2387 /* Reset device address to zero */
2388 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2389 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2390 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2391}
2392
2393static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2394{
2395 u32 reg;
2396 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2397
2398 /*
2399 * We change the clock only at SS but I dunno why I would want to do
2400 * this. Maybe it becomes part of the power saving plan.
2401 */
2402
ee5cd41c
JY		 2403 if ((speed != DWC3_DSTS_SUPERSPEED) &&
2404 (speed != DWC3_DSTS_SUPERSPEED_PLUS))
72246da4
FB		 2405 return;
2406
2407 /*
2408 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2409 * each time on Connect Done.
2410 */
2411 if (!usb30_clock)
2412 return;
2413
2414 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2415 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2416 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2417}
2418
72246da4
FB		 2419static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2420{
72246da4
FB		 2421 struct dwc3_ep *dep;
2422 int ret;
2423 u32 reg;
2424 u8 speed;
2425
72246da4
FB		 2426 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2427 speed = reg & DWC3_DSTS_CONNECTSPD;
2428 dwc->speed = speed;
2429
2430 dwc3_update_ram_clk_sel(dwc, speed);
2431
2432 switch (speed) {
7580862b
JY		 2433 case DWC3_DCFG_SUPERSPEED_PLUS:
2434 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2435 dwc->gadget.ep0->maxpacket = 512;
2436 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2437 break;
72246da4 2438 case DWC3_DCFG_SUPERSPEED:
05870c5b
FB		 2439 /*
2440 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2441 * would cause a missing USB3 Reset event.
2442 *
2443 * In such situations, we should force a USB3 Reset
2444 * event by calling our dwc3_gadget_reset_interrupt()
2445 * routine.
2446 *
2447 * Refers to:
2448 *
2449 * STAR#9000483510: RTL: SS : USB3 reset event may
2450 * not be generated always when the link enters poll
2451 */
2452 if (dwc->revision < DWC3_REVISION_190A)
2453 dwc3_gadget_reset_interrupt(dwc);
2454
72246da4
FB		 2455 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2456 dwc->gadget.ep0->maxpacket = 512;
2457 dwc->gadget.speed = USB_SPEED_SUPER;
2458 break;
2459 case DWC3_DCFG_HIGHSPEED:
2460 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2461 dwc->gadget.ep0->maxpacket = 64;
2462 dwc->gadget.speed = USB_SPEED_HIGH;
2463 break;
2464 case DWC3_DCFG_FULLSPEED2:
2465 case DWC3_DCFG_FULLSPEED1:
2466 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2467 dwc->gadget.ep0->maxpacket = 64;
2468 dwc->gadget.speed = USB_SPEED_FULL;
2469 break;
2470 case DWC3_DCFG_LOWSPEED:
2471 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2472 dwc->gadget.ep0->maxpacket = 8;
2473 dwc->gadget.speed = USB_SPEED_LOW;
2474 break;
2475 }
2476
2b758350
PA		 2477 /* Enable USB2 LPM Capability */
2478
ee5cd41c
JY		 2479 if ((dwc->revision > DWC3_REVISION_194A) &&
2480 (speed != DWC3_DCFG_SUPERSPEED) &&
2481 (speed != DWC3_DCFG_SUPERSPEED_PLUS)) {
2b758350
PA		 2482 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2483 reg |= DWC3_DCFG_LPM_CAP;
2484 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2485
2486 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2487 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2488
460d098c 2489 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2b758350 2490
80caf7d2
HR		 2491 /*
2492 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2493 * DCFG.LPMCap is set, core responses with an ACK and the
2494 * BESL value in the LPM token is less than or equal to LPM
2495 * NYET threshold.
2496 */
2497 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2498 && dwc->has_lpm_erratum,
2499 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2500
2501 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2502 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2503
356363bf
FB		 2504 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2505 } else {
2506 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2507 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2b758350
PA		 2508 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2509 }
2510
72246da4 2511 dep = dwc->eps[0];
265b70a7
PZ		 2512 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2513 false);
72246da4
FB		 2514 if (ret) {
2515 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2516 return;
2517 }
2518
2519 dep = dwc->eps[1];
265b70a7
PZ		 2520 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2521 false);
72246da4
FB		 2522 if (ret) {
2523 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2524 return;
2525 }
2526
2527 /*
2528 * Configure PHY via GUSB3PIPECTLn if required.
2529 *
2530 * Update GTXFIFOSIZn
2531 *
2532 * In both cases reset values should be sufficient.
2533 */
2534}
2535
2536static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2537{
72246da4
FB		 2538 /*
2539 * TODO take core out of low power mode when that's
2540 * implemented.
2541 */
2542
ad14d4e0
JL		 2543 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2544 spin_unlock(&dwc->lock);
2545 dwc->gadget_driver->resume(&dwc->gadget);
2546 spin_lock(&dwc->lock);
2547 }
72246da4
FB		 2548}
2549
2550static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2551 unsigned int evtinfo)
2552{
fae2b904 2553 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
0b0cc1cd
FB		 2554 unsigned int pwropt;
2555
2556 /*
2557 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2558 * Hibernation mode enabled which would show up when device detects
2559 * host-initiated U3 exit.
2560 *
2561 * In that case, device will generate a Link State Change Interrupt
2562 * from U3 to RESUME which is only necessary if Hibernation is
2563 * configured in.
2564 *
2565 * There are no functional changes due to such spurious event and we
2566 * just need to ignore it.
2567 *
2568 * Refers to:
2569 *
2570 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2571 * operational mode
2572 */
2573 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2574 if ((dwc->revision < DWC3_REVISION_250A) &&
2575 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2576 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2577 (next == DWC3_LINK_STATE_RESUME)) {
73815280
FB		 2578 dwc3_trace(trace_dwc3_gadget,
2579 "ignoring transition U3 -> Resume");
0b0cc1cd
FB		 2580 return;
2581 }
2582 }
fae2b904
FB		 2583
2584 /*
2585 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2586 * on the link partner, the USB session might do multiple entry/exit
2587 * of low power states before a transfer takes place.
2588 *
2589 * Due to this problem, we might experience lower throughput. The
2590 * suggested workaround is to disable DCTL[12:9] bits if we're
2591 * transitioning from U1/U2 to U0 and enable those bits again
2592 * after a transfer completes and there are no pending transfers
2593 * on any of the enabled endpoints.
2594 *
2595 * This is the first half of that workaround.
2596 *
2597 * Refers to:
2598 *
2599 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2600 * core send LGO_Ux entering U0
2601 */
2602 if (dwc->revision < DWC3_REVISION_183A) {
2603 if (next == DWC3_LINK_STATE_U0) {
2604 u32 u1u2;
2605 u32 reg;
2606
2607 switch (dwc->link_state) {
2608 case DWC3_LINK_STATE_U1:
2609 case DWC3_LINK_STATE_U2:
2610 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2611 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2612 | DWC3_DCTL_ACCEPTU2ENA
2613 | DWC3_DCTL_INITU1ENA
2614 | DWC3_DCTL_ACCEPTU1ENA);
2615
2616 if (!dwc->u1u2)
2617 dwc->u1u2 = reg & u1u2;
2618
2619 reg &= ~u1u2;
2620
2621 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2622 break;
2623 default:
2624 /* do nothing */
2625 break;
2626 }
2627 }
2628 }
2629
bc5ba2e0
FB		 2630 switch (next) {
2631 case DWC3_LINK_STATE_U1:
2632 if (dwc->speed == USB_SPEED_SUPER)
2633 dwc3_suspend_gadget(dwc);
2634 break;
2635 case DWC3_LINK_STATE_U2:
2636 case DWC3_LINK_STATE_U3:
2637 dwc3_suspend_gadget(dwc);
2638 break;
2639 case DWC3_LINK_STATE_RESUME:
2640 dwc3_resume_gadget(dwc);
2641 break;
2642 default:
2643 /* do nothing */
2644 break;
2645 }
2646
e57ebc1d 2647 dwc->link_state = next;
72246da4
FB		 2648}
2649
e1dadd3b
FB		 2650static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2651 unsigned int evtinfo)
2652{
2653 unsigned int is_ss = evtinfo & BIT(4);
2654
2655 /**
2656 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2657 * have a known issue which can cause USB CV TD.9.23 to fail
2658 * randomly.
2659 *
2660 * Because of this issue, core could generate bogus hibernation
2661 * events which SW needs to ignore.
2662 *
2663 * Refers to:
2664 *
2665 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2666 * Device Fallback from SuperSpeed
2667 */
2668 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2669 return;
2670
2671 /* enter hibernation here */
2672}
2673
72246da4
FB		 2674static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2675 const struct dwc3_event_devt *event)
2676{
2677 switch (event->type) {
2678 case DWC3_DEVICE_EVENT_DISCONNECT:
2679 dwc3_gadget_disconnect_interrupt(dwc);
2680 break;
2681 case DWC3_DEVICE_EVENT_RESET:
2682 dwc3_gadget_reset_interrupt(dwc);
2683 break;
2684 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2685 dwc3_gadget_conndone_interrupt(dwc);
2686 break;
2687 case DWC3_DEVICE_EVENT_WAKEUP:
2688 dwc3_gadget_wakeup_interrupt(dwc);
2689 break;
e1dadd3b
FB		 2690 case DWC3_DEVICE_EVENT_HIBER_REQ:
2691 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2692 "unexpected hibernation event\n"))
2693 break;
2694
2695 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2696 break;
72246da4
FB		 2697 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2698 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2699 break;
2700 case DWC3_DEVICE_EVENT_EOPF:
73815280 2701 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
72246da4
FB		 2702 break;
2703 case DWC3_DEVICE_EVENT_SOF:
73815280 2704 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
72246da4
FB		 2705 break;
2706 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
73815280 2707 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
72246da4
FB		 2708 break;
2709 case DWC3_DEVICE_EVENT_CMD_CMPL:
73815280 2710 dwc3_trace(trace_dwc3_gadget, "Command Complete");
72246da4
FB		 2711 break;
2712 case DWC3_DEVICE_EVENT_OVERFLOW:
73815280 2713 dwc3_trace(trace_dwc3_gadget, "Overflow");
72246da4
FB		 2714 break;
2715 default:
e9f2aa87 2716 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
72246da4
FB		 2717 }
2718}
2719
2720static void dwc3_process_event_entry(struct dwc3 *dwc,
2721 const union dwc3_event *event)
2722{
2c4cbe6e
FB		 2723 trace_dwc3_event(event->raw);
2724
72246da4
FB		 2725 /* Endpoint IRQ, handle it and return early */
2726 if (event->type.is_devspec == 0) {
2727 /* depevt */
2728 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2729 }
2730
2731 switch (event->type.type) {
2732 case DWC3_EVENT_TYPE_DEV:
2733 dwc3_gadget_interrupt(dwc, &event->devt);
2734 break;
2735 /* REVISIT what to do with Carkit and I2C events ? */
2736 default:
2737 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2738 }
2739}
2740
dea520a4 2741static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
b15a762f 2742{
dea520a4 2743 struct dwc3 *dwc = evt->dwc;
b15a762f 2744 irqreturn_t ret = IRQ_NONE;
f42f2447 2745 int left;
e8adfc30 2746 u32 reg;
b15a762f 2747
f42f2447 2748 left = evt->count;
b15a762f 2749
f42f2447
FB		 2750 if (!(evt->flags & DWC3_EVENT_PENDING))
2751 return IRQ_NONE;
b15a762f 2752
f42f2447
FB		 2753 while (left > 0) {
2754 union dwc3_event event;
b15a762f 2755
f42f2447 2756 event.raw = *(u32 *) (evt->buf + evt->lpos);
b15a762f 2757
f42f2447 2758 dwc3_process_event_entry(dwc, &event);
b15a762f 2759
f42f2447
FB		 2760 /*
2761 * FIXME we wrap around correctly to the next entry as
2762 * almost all entries are 4 bytes in size. There is one
2763 * entry which has 12 bytes which is a regular entry
2764 * followed by 8 bytes data. ATM I don't know how
2765 * things are organized if we get next to the a
2766 * boundary so I worry about that once we try to handle
2767 * that.
2768 */
2769 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2770 left -= 4;
b15a762f 2771
660e9bde 2772 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
f42f2447 2773 }
b15a762f 2774
f42f2447
FB		 2775 evt->count = 0;
2776 evt->flags &= ~DWC3_EVENT_PENDING;
2777 ret = IRQ_HANDLED;
b15a762f 2778
f42f2447 2779 /* Unmask interrupt */
660e9bde 2780 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
f42f2447 2781 reg &= ~DWC3_GEVNTSIZ_INTMASK;
660e9bde 2782 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
b15a762f 2783
f42f2447
FB		 2784 return ret;
2785}
e8adfc30 2786
dea520a4 2787static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
f42f2447 2788{
dea520a4
FB		 2789 struct dwc3_event_buffer *evt = _evt;
2790 struct dwc3 *dwc = evt->dwc;
e5f68b4a 2791 unsigned long flags;
f42f2447 2792 irqreturn_t ret = IRQ_NONE;
f42f2447 2793
e5f68b4a 2794 spin_lock_irqsave(&dwc->lock, flags);
dea520a4 2795 ret = dwc3_process_event_buf(evt);
e5f68b4a 2796 spin_unlock_irqrestore(&dwc->lock, flags);
b15a762f
FB		 2797
2798 return ret;
2799}
2800
dea520a4 2801static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
72246da4 2802{
dea520a4 2803 struct dwc3 *dwc = evt->dwc;
72246da4 2804 u32 count;
e8adfc30 2805 u32 reg;
72246da4 2806
fc8bb91b
FB		 2807 if (pm_runtime_suspended(dwc->dev)) {
2808 pm_runtime_get(dwc->dev);
2809 disable_irq_nosync(dwc->irq_gadget);
2810 dwc->pending_events = true;
2811 return IRQ_HANDLED;
2812 }
2813
660e9bde 2814 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
72246da4
FB		 2815 count &= DWC3_GEVNTCOUNT_MASK;
2816 if (!count)
2817 return IRQ_NONE;
2818
b15a762f
FB		 2819 evt->count = count;
2820 evt->flags |= DWC3_EVENT_PENDING;
72246da4 2821
e8adfc30 2822 /* Mask interrupt */
660e9bde 2823 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
e8adfc30 2824 reg |= DWC3_GEVNTSIZ_INTMASK;
660e9bde 2825 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
e8adfc30 2826
b15a762f 2827 return IRQ_WAKE_THREAD;
72246da4
FB		 2828}
2829
dea520a4 2830static irqreturn_t dwc3_interrupt(int irq, void *_evt)
72246da4 2831{
dea520a4 2832 struct dwc3_event_buffer *evt = _evt;
72246da4 2833
dea520a4 2834 return dwc3_check_event_buf(evt);
72246da4
FB		 2835}
2836
2837/**
2838 * dwc3_gadget_init - Initializes gadget related registers
1d046793 2839 * @dwc: pointer to our controller context structure
72246da4
FB		 2840 *
2841 * Returns 0 on success otherwise negative errno.
2842 */
41ac7b3a 2843int dwc3_gadget_init(struct dwc3 *dwc)
72246da4 2844{
72246da4 2845 int ret;
72246da4
FB		 2846
2847 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2848 &dwc->ctrl_req_addr, GFP_KERNEL);
2849 if (!dwc->ctrl_req) {
2850 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2851 ret = -ENOMEM;
2852 goto err0;
2853 }
2854
2abd9d5f 2855 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 2856 &dwc->ep0_trb_addr, GFP_KERNEL);
2857 if (!dwc->ep0_trb) {
2858 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2859 ret = -ENOMEM;
2860 goto err1;
2861 }
2862
3ef35faf 2863 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
72246da4 2864 if (!dwc->setup_buf) {
72246da4
FB		 2865 ret = -ENOMEM;
2866 goto err2;
2867 }
2868
5812b1c2 2869 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
3ef35faf
FB		 2870 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2871 GFP_KERNEL);
5812b1c2
FB		 2872 if (!dwc->ep0_bounce) {
2873 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2874 ret = -ENOMEM;
2875 goto err3;
2876 }
2877
04c03d10
FB		 2878 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2879 if (!dwc->zlp_buf) {
2880 ret = -ENOMEM;
2881 goto err4;
2882 }
2883
72246da4 2884 dwc->gadget.ops = &dwc3_gadget_ops;
72246da4 2885 dwc->gadget.speed = USB_SPEED_UNKNOWN;
eeb720fb 2886 dwc->gadget.sg_supported = true;
72246da4 2887 dwc->gadget.name = "dwc3-gadget";
6a4290cc 2888 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
72246da4 2889
b9e51b2b
BM		 2890 /*
2891 * FIXME We might be setting max_speed to <SUPER, however versions
2892 * <2.20a of dwc3 have an issue with metastability (documented
2893 * elsewhere in this driver) which tells us we can't set max speed to
2894 * anything lower than SUPER.
2895 *
2896 * Because gadget.max_speed is only used by composite.c and function
2897 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2898 * to happen so we avoid sending SuperSpeed Capability descriptor
2899 * together with our BOS descriptor as that could confuse host into
2900 * thinking we can handle super speed.
2901 *
2902 * Note that, in fact, we won't even support GetBOS requests when speed
2903 * is less than super speed because we don't have means, yet, to tell
2904 * composite.c that we are USB 2.0 + LPM ECN.
2905 */
2906 if (dwc->revision < DWC3_REVISION_220A)
2907 dwc3_trace(trace_dwc3_gadget,
2908 "Changing max_speed on rev %08x\n",
2909 dwc->revision);
2910
2911 dwc->gadget.max_speed = dwc->maximum_speed;
2912
a4b9d94b
DC		 2913 /*
2914 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2915 * on ep out.
2916 */
2917 dwc->gadget.quirk_ep_out_aligned_size = true;
2918
72246da4
FB		 2919 /*
2920 * REVISIT: Here we should clear all pending IRQs to be
2921 * sure we're starting from a well known location.
2922 */
2923
2924 ret = dwc3_gadget_init_endpoints(dwc);
2925 if (ret)
04c03d10 2926 goto err5;
72246da4 2927
72246da4
FB		 2928 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2929 if (ret) {
2930 dev_err(dwc->dev, "failed to register udc\n");
04c03d10 2931 goto err5;
72246da4
FB		 2932 }
2933
2934 return 0;
2935
04c03d10
FB		 2936err5:
2937 kfree(dwc->zlp_buf);
2938
5812b1c2 2939err4:
e1f80467 2940 dwc3_gadget_free_endpoints(dwc);
3ef35faf
FB		 2941 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2942 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 2943
72246da4 2944err3:
0fc9a1be 2945 kfree(dwc->setup_buf);
72246da4
FB		 2946
2947err2:
2948 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2949 dwc->ep0_trb, dwc->ep0_trb_addr);
2950
2951err1:
2952 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2953 dwc->ctrl_req, dwc->ctrl_req_addr);
2954
2955err0:
2956 return ret;
2957}
2958
7415f17c
FB		 2959/* -------------------------------------------------------------------------- */
2960
72246da4
FB		 2961void dwc3_gadget_exit(struct dwc3 *dwc)
2962{
72246da4 2963 usb_del_gadget_udc(&dwc->gadget);
72246da4 2964
72246da4
FB		 2965 dwc3_gadget_free_endpoints(dwc);
2966
3ef35faf
FB		 2967 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2968 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 2969
0fc9a1be 2970 kfree(dwc->setup_buf);
04c03d10 2971 kfree(dwc->zlp_buf);
72246da4
FB		 2972
2973 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2974 dwc->ep0_trb, dwc->ep0_trb_addr);
2975
2976 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2977 dwc->ctrl_req, dwc->ctrl_req_addr);
72246da4 2978}
7415f17c 2979
0b0231aa 2980int dwc3_gadget_suspend(struct dwc3 *dwc)
7415f17c 2981{
9f8a67b6
FB		 2982 int ret;
2983
9772b47a
RQ		 2984 if (!dwc->gadget_driver)
2985 return 0;
2986
9f8a67b6
FB		 2987 ret = dwc3_gadget_run_stop(dwc, false, false);
2988 if (ret < 0)
2989 return ret;
7415f17c 2990
9f8a67b6
FB		 2991 dwc3_disconnect_gadget(dwc);
2992 __dwc3_gadget_stop(dwc);
7415f17c
FB		 2993
2994 return 0;
2995}
2996
2997int dwc3_gadget_resume(struct dwc3 *dwc)
2998{
7415f17c
FB		 2999 int ret;
3000
9772b47a
RQ		 3001 if (!dwc->gadget_driver)
3002 return 0;
3003
9f8a67b6
FB		 3004 ret = __dwc3_gadget_start(dwc);
3005 if (ret < 0)
7415f17c
FB		 3006 goto err0;
3007
9f8a67b6
FB		 3008 ret = dwc3_gadget_run_stop(dwc, true, false);
3009 if (ret < 0)
7415f17c
FB		 3010 goto err1;
3011
7415f17c
FB		 3012 return 0;
3013
3014err1:
9f8a67b6 3015 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3016
3017err0:
3018 return ret;
3019}
fc8bb91b
FB		 3020
3021void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3022{
3023 if (dwc->pending_events) {
3024 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3025 dwc->pending_events = false;
3026 enable_irq(dwc->irq_gadget);
3027 }
3028}
Linux 6.x block layer and io_uring tree(s)