Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
bfad65ee | 2 | /* |
72246da4 FB |
3 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link |
4 | * | |
5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
6 | * |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
72246da4 FB |
9 | */ |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/pm_runtime.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | ||
22 | #include <linux/usb/ch9.h> | |
23 | #include <linux/usb/gadget.h> | |
24 | ||
80977dc9 | 25 | #include "debug.h" |
72246da4 FB |
26 | #include "core.h" |
27 | #include "gadget.h" | |
28 | #include "io.h" | |
29 | ||
d5370106 | 30 | #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \ |
f62afb49 FB |
31 | & ~((d)->interval - 1)) |
32 | ||
04a9bfcd | 33 | /** |
bfad65ee | 34 | * dwc3_gadget_set_test_mode - enables usb2 test modes |
04a9bfcd FB |
35 | * @dwc: pointer to our context structure |
36 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
37 | * | |
bfad65ee FB |
38 | * Caller should take care of locking. This function will return 0 on |
39 | * success or -EINVAL if wrong Test Selector is passed. | |
04a9bfcd FB |
40 | */ |
41 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
42 | { | |
43 | u32 reg; | |
44 | ||
45 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
46 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
47 | ||
48 | switch (mode) { | |
49 | case TEST_J: | |
50 | case TEST_K: | |
51 | case TEST_SE0_NAK: | |
52 | case TEST_PACKET: | |
53 | case TEST_FORCE_EN: | |
54 | reg |= mode << 1; | |
55 | break; | |
56 | default: | |
57 | return -EINVAL; | |
58 | } | |
59 | ||
5b738211 | 60 | dwc3_gadget_dctl_write_safe(dwc, reg); |
04a9bfcd FB |
61 | |
62 | return 0; | |
63 | } | |
64 | ||
911f1f88 | 65 | /** |
bfad65ee | 66 | * dwc3_gadget_get_link_state - gets current state of usb link |
911f1f88 PZ |
67 | * @dwc: pointer to our context structure |
68 | * | |
69 | * Caller should take care of locking. This function will | |
70 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
71 | */ | |
72 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
73 | { | |
74 | u32 reg; | |
75 | ||
76 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
77 | ||
78 | return DWC3_DSTS_USBLNKST(reg); | |
79 | } | |
80 | ||
8598bde7 | 81 | /** |
bfad65ee | 82 | * dwc3_gadget_set_link_state - sets usb link to a particular state |
8598bde7 FB |
83 | * @dwc: pointer to our context structure |
84 | * @state: the state to put link into | |
85 | * | |
86 | * Caller should take care of locking. This function will | |
aee63e3c | 87 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
88 | */ |
89 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
90 | { | |
aee63e3c | 91 | int retries = 10000; |
8598bde7 FB |
92 | u32 reg; |
93 | ||
802fde98 PZ |
94 | /* |
95 | * Wait until device controller is ready. Only applies to 1.94a and | |
96 | * later RTL. | |
97 | */ | |
98 | if (dwc->revision >= DWC3_REVISION_194A) { | |
99 | while (--retries) { | |
100 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
101 | if (reg & DWC3_DSTS_DCNRD) | |
102 | udelay(5); | |
103 | else | |
104 | break; | |
105 | } | |
106 | ||
107 | if (retries <= 0) | |
108 | return -ETIMEDOUT; | |
109 | } | |
110 | ||
8598bde7 FB |
111 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
112 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
113 | ||
2e708fa3 TN |
114 | /* set no action before sending new link state change */ |
115 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
116 | ||
8598bde7 FB |
117 | /* set requested state */ |
118 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
119 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
120 | ||
802fde98 PZ |
121 | /* |
122 | * The following code is racy when called from dwc3_gadget_wakeup, | |
123 | * and is not needed, at least on newer versions | |
124 | */ | |
125 | if (dwc->revision >= DWC3_REVISION_194A) | |
126 | return 0; | |
127 | ||
8598bde7 | 128 | /* wait for a change in DSTS */ |
aed430e5 | 129 | retries = 10000; |
8598bde7 FB |
130 | while (--retries) { |
131 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
132 | ||
8598bde7 FB |
133 | if (DWC3_DSTS_USBLNKST(reg) == state) |
134 | return 0; | |
135 | ||
aee63e3c | 136 | udelay(5); |
8598bde7 FB |
137 | } |
138 | ||
8598bde7 FB |
139 | return -ETIMEDOUT; |
140 | } | |
141 | ||
dca0119c | 142 | /** |
bfad65ee FB |
143 | * dwc3_ep_inc_trb - increment a trb index. |
144 | * @index: Pointer to the TRB index to increment. | |
dca0119c JY |
145 | * |
146 | * The index should never point to the link TRB. After incrementing, | |
147 | * if it is point to the link TRB, wrap around to the beginning. The | |
148 | * link TRB is always at the last TRB entry. | |
149 | */ | |
150 | static void dwc3_ep_inc_trb(u8 *index) | |
457e84b6 | 151 | { |
dca0119c JY |
152 | (*index)++; |
153 | if (*index == (DWC3_TRB_NUM - 1)) | |
154 | *index = 0; | |
ef966b9d | 155 | } |
457e84b6 | 156 | |
bfad65ee FB |
157 | /** |
158 | * dwc3_ep_inc_enq - increment endpoint's enqueue pointer | |
159 | * @dep: The endpoint whose enqueue pointer we're incrementing | |
160 | */ | |
dca0119c | 161 | static void dwc3_ep_inc_enq(struct dwc3_ep *dep) |
ef966b9d | 162 | { |
dca0119c | 163 | dwc3_ep_inc_trb(&dep->trb_enqueue); |
ef966b9d | 164 | } |
457e84b6 | 165 | |
bfad65ee FB |
166 | /** |
167 | * dwc3_ep_inc_deq - increment endpoint's dequeue pointer | |
168 | * @dep: The endpoint whose enqueue pointer we're incrementing | |
169 | */ | |
dca0119c | 170 | static void dwc3_ep_inc_deq(struct dwc3_ep *dep) |
ef966b9d | 171 | { |
dca0119c | 172 | dwc3_ep_inc_trb(&dep->trb_dequeue); |
457e84b6 FB |
173 | } |
174 | ||
69102510 | 175 | static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep, |
c91815b5 | 176 | struct dwc3_request *req, int status) |
72246da4 FB |
177 | { |
178 | struct dwc3 *dwc = dep->dwc; | |
179 | ||
72246da4 | 180 | list_del(&req->list); |
e62c5bc5 | 181 | req->remaining = 0; |
bd674224 | 182 | req->needs_extra_trb = false; |
72246da4 FB |
183 | |
184 | if (req->request.status == -EINPROGRESS) | |
185 | req->request.status = status; | |
186 | ||
4a71fcb8 JP |
187 | if (req->trb) |
188 | usb_gadget_unmap_request_by_dev(dwc->sysdev, | |
c91815b5 | 189 | &req->request, req->direction); |
4a71fcb8 JP |
190 | |
191 | req->trb = NULL; | |
2c4cbe6e | 192 | trace_dwc3_gadget_giveback(req); |
72246da4 | 193 | |
c91815b5 FB |
194 | if (dep->number > 1) |
195 | pm_runtime_put(dwc->dev); | |
196 | } | |
197 | ||
198 | /** | |
199 | * dwc3_gadget_giveback - call struct usb_request's ->complete callback | |
200 | * @dep: The endpoint to whom the request belongs to | |
201 | * @req: The request we're giving back | |
202 | * @status: completion code for the request | |
203 | * | |
204 | * Must be called with controller's lock held and interrupts disabled. This | |
205 | * function will unmap @req and call its ->complete() callback to notify upper | |
206 | * layers that it has completed. | |
207 | */ | |
208 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, | |
209 | int status) | |
210 | { | |
211 | struct dwc3 *dwc = dep->dwc; | |
212 | ||
213 | dwc3_gadget_del_and_unmap_request(dep, req, status); | |
a3af5e3a | 214 | req->status = DWC3_REQUEST_STATUS_COMPLETED; |
c91815b5 | 215 | |
72246da4 | 216 | spin_unlock(&dwc->lock); |
304f7e5e | 217 | usb_gadget_giveback_request(&dep->endpoint, &req->request); |
72246da4 FB |
218 | spin_lock(&dwc->lock); |
219 | } | |
220 | ||
bfad65ee FB |
221 | /** |
222 | * dwc3_send_gadget_generic_command - issue a generic command for the controller | |
223 | * @dwc: pointer to the controller context | |
224 | * @cmd: the command to be issued | |
225 | * @param: command parameter | |
226 | * | |
227 | * Caller should take care of locking. Issue @cmd with a given @param to @dwc | |
228 | * and wait for its completion. | |
229 | */ | |
3ece0ec4 | 230 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param) |
b09bb642 FB |
231 | { |
232 | u32 timeout = 500; | |
71f7e702 | 233 | int status = 0; |
0fe886cd | 234 | int ret = 0; |
b09bb642 FB |
235 | u32 reg; |
236 | ||
237 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); | |
238 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
239 | ||
240 | do { | |
241 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
242 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
71f7e702 FB |
243 | status = DWC3_DGCMD_STATUS(reg); |
244 | if (status) | |
0fe886cd FB |
245 | ret = -EINVAL; |
246 | break; | |
b09bb642 | 247 | } |
e3aee486 | 248 | } while (--timeout); |
0fe886cd FB |
249 | |
250 | if (!timeout) { | |
0fe886cd | 251 | ret = -ETIMEDOUT; |
71f7e702 | 252 | status = -ETIMEDOUT; |
0fe886cd FB |
253 | } |
254 | ||
71f7e702 FB |
255 | trace_dwc3_gadget_generic_cmd(cmd, param, status); |
256 | ||
0fe886cd | 257 | return ret; |
b09bb642 FB |
258 | } |
259 | ||
c36d8e94 FB |
260 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc); |
261 | ||
bfad65ee FB |
262 | /** |
263 | * dwc3_send_gadget_ep_cmd - issue an endpoint command | |
264 | * @dep: the endpoint to which the command is going to be issued | |
265 | * @cmd: the command to be issued | |
266 | * @params: parameters to the command | |
267 | * | |
268 | * Caller should handle locking. This function will issue @cmd with given | |
269 | * @params to @dep and wait for its completion. | |
270 | */ | |
2cd4718d FB |
271 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, |
272 | struct dwc3_gadget_ep_cmd_params *params) | |
72246da4 | 273 | { |
8897a761 | 274 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
2cd4718d | 275 | struct dwc3 *dwc = dep->dwc; |
8722e095 | 276 | u32 timeout = 1000; |
87dd9611 | 277 | u32 saved_config = 0; |
72246da4 FB |
278 | u32 reg; |
279 | ||
0933df15 | 280 | int cmd_status = 0; |
c0ca324d | 281 | int ret = -EINVAL; |
72246da4 | 282 | |
2b0f11df | 283 | /* |
87dd9611 TN |
284 | * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or |
285 | * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an | |
286 | * endpoint command. | |
2b0f11df | 287 | * |
87dd9611 TN |
288 | * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY |
289 | * settings. Restore them after the command is completed. | |
290 | * | |
291 | * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2 | |
2b0f11df | 292 | */ |
ab2a92e7 FB |
293 | if (dwc->gadget.speed <= USB_SPEED_HIGH) { |
294 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
295 | if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) { | |
87dd9611 | 296 | saved_config |= DWC3_GUSB2PHYCFG_SUSPHY; |
ab2a92e7 | 297 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; |
ab2a92e7 | 298 | } |
87dd9611 TN |
299 | |
300 | if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) { | |
301 | saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM; | |
302 | reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; | |
303 | } | |
304 | ||
305 | if (saved_config) | |
306 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
2b0f11df FB |
307 | } |
308 | ||
5999914f | 309 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { |
c36d8e94 FB |
310 | int needs_wakeup; |
311 | ||
312 | needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 || | |
313 | dwc->link_state == DWC3_LINK_STATE_U2 || | |
314 | dwc->link_state == DWC3_LINK_STATE_U3); | |
315 | ||
316 | if (unlikely(needs_wakeup)) { | |
317 | ret = __dwc3_gadget_wakeup(dwc); | |
318 | dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n", | |
319 | ret); | |
320 | } | |
321 | } | |
322 | ||
2eb88016 FB |
323 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0); |
324 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1); | |
325 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2); | |
72246da4 | 326 | |
8897a761 FB |
327 | /* |
328 | * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're | |
329 | * not relying on XferNotReady, we can make use of a special "No | |
330 | * Response Update Transfer" command where we should clear both CmdAct | |
331 | * and CmdIOC bits. | |
332 | * | |
333 | * With this, we don't need to wait for command completion and can | |
334 | * straight away issue further commands to the endpoint. | |
335 | * | |
336 | * NOTICE: We're making an assumption that control endpoints will never | |
337 | * make use of Update Transfer command. This is a safe assumption | |
338 | * because we can never have more than one request at a time with | |
339 | * Control Endpoints. If anybody changes that assumption, this chunk | |
340 | * needs to be updated accordingly. | |
341 | */ | |
342 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER && | |
343 | !usb_endpoint_xfer_isoc(desc)) | |
344 | cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT); | |
345 | else | |
346 | cmd |= DWC3_DEPCMD_CMDACT; | |
347 | ||
348 | dwc3_writel(dep->regs, DWC3_DEPCMD, cmd); | |
72246da4 | 349 | do { |
2eb88016 | 350 | reg = dwc3_readl(dep->regs, DWC3_DEPCMD); |
72246da4 | 351 | if (!(reg & DWC3_DEPCMD_CMDACT)) { |
0933df15 | 352 | cmd_status = DWC3_DEPCMD_STATUS(reg); |
7b9cc7a2 | 353 | |
7b9cc7a2 KL |
354 | switch (cmd_status) { |
355 | case 0: | |
356 | ret = 0; | |
357 | break; | |
358 | case DEPEVT_TRANSFER_NO_RESOURCE: | |
7b9cc7a2 | 359 | ret = -EINVAL; |
c0ca324d | 360 | break; |
7b9cc7a2 KL |
361 | case DEPEVT_TRANSFER_BUS_EXPIRY: |
362 | /* | |
363 | * SW issues START TRANSFER command to | |
364 | * isochronous ep with future frame interval. If | |
365 | * future interval time has already passed when | |
366 | * core receives the command, it will respond | |
367 | * with an error status of 'Bus Expiry'. | |
368 | * | |
369 | * Instead of always returning -EINVAL, let's | |
370 | * give a hint to the gadget driver that this is | |
371 | * the case by returning -EAGAIN. | |
372 | */ | |
7b9cc7a2 KL |
373 | ret = -EAGAIN; |
374 | break; | |
375 | default: | |
376 | dev_WARN(dwc->dev, "UNKNOWN cmd status\n"); | |
377 | } | |
378 | ||
c0ca324d | 379 | break; |
72246da4 | 380 | } |
f6bb225b | 381 | } while (--timeout); |
72246da4 | 382 | |
f6bb225b | 383 | if (timeout == 0) { |
f6bb225b | 384 | ret = -ETIMEDOUT; |
0933df15 | 385 | cmd_status = -ETIMEDOUT; |
f6bb225b | 386 | } |
c0ca324d | 387 | |
0933df15 FB |
388 | trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status); |
389 | ||
acbfa6c2 FB |
390 | if (ret == 0 && DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { |
391 | dep->flags |= DWC3_EP_TRANSFER_STARTED; | |
392 | dwc3_gadget_ep_get_transfer_index(dep); | |
6cb2e4e3 FB |
393 | } |
394 | ||
87dd9611 | 395 | if (saved_config) { |
2b0f11df | 396 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
87dd9611 | 397 | reg |= saved_config; |
2b0f11df FB |
398 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
399 | } | |
400 | ||
c0ca324d | 401 | return ret; |
72246da4 FB |
402 | } |
403 | ||
50c763f8 JY |
404 | static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep) |
405 | { | |
406 | struct dwc3 *dwc = dep->dwc; | |
407 | struct dwc3_gadget_ep_cmd_params params; | |
408 | u32 cmd = DWC3_DEPCMD_CLEARSTALL; | |
409 | ||
410 | /* | |
411 | * As of core revision 2.60a the recommended programming model | |
412 | * is to set the ClearPendIN bit when issuing a Clear Stall EP | |
413 | * command for IN endpoints. This is to prevent an issue where | |
414 | * some (non-compliant) hosts may not send ACK TPs for pending | |
415 | * IN transfers due to a mishandled error condition. Synopsys | |
416 | * STAR 9000614252. | |
417 | */ | |
5e6c88d2 LB |
418 | if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) && |
419 | (dwc->gadget.speed >= USB_SPEED_SUPER)) | |
50c763f8 JY |
420 | cmd |= DWC3_DEPCMD_CLEARPENDIN; |
421 | ||
422 | memset(¶ms, 0, sizeof(params)); | |
423 | ||
2cd4718d | 424 | return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
50c763f8 JY |
425 | } |
426 | ||
72246da4 | 427 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, |
f6bafc6a | 428 | struct dwc3_trb *trb) |
72246da4 | 429 | { |
c439ef87 | 430 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
431 | |
432 | return dep->trb_pool_dma + offset; | |
433 | } | |
434 | ||
435 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
436 | { | |
437 | struct dwc3 *dwc = dep->dwc; | |
438 | ||
439 | if (dep->trb_pool) | |
440 | return 0; | |
441 | ||
d64ff406 | 442 | dep->trb_pool = dma_alloc_coherent(dwc->sysdev, |
72246da4 FB |
443 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, |
444 | &dep->trb_pool_dma, GFP_KERNEL); | |
445 | if (!dep->trb_pool) { | |
446 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
447 | dep->name); | |
448 | return -ENOMEM; | |
449 | } | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
454 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
455 | { | |
456 | struct dwc3 *dwc = dep->dwc; | |
457 | ||
d64ff406 | 458 | dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, |
72246da4 FB |
459 | dep->trb_pool, dep->trb_pool_dma); |
460 | ||
461 | dep->trb_pool = NULL; | |
462 | dep->trb_pool_dma = 0; | |
463 | } | |
464 | ||
20d1d43f FB |
465 | static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep) |
466 | { | |
467 | struct dwc3_gadget_ep_cmd_params params; | |
468 | ||
469 | memset(¶ms, 0x00, sizeof(params)); | |
470 | ||
471 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); | |
472 | ||
473 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE, | |
474 | ¶ms); | |
475 | } | |
c4509601 JY |
476 | |
477 | /** | |
bfad65ee | 478 | * dwc3_gadget_start_config - configure ep resources |
c4509601 JY |
479 | * @dep: endpoint that is being enabled |
480 | * | |
bfad65ee FB |
481 | * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's |
482 | * completion, it will set Transfer Resource for all available endpoints. | |
c4509601 | 483 | * |
bfad65ee FB |
484 | * The assignment of transfer resources cannot perfectly follow the data book |
485 | * due to the fact that the controller driver does not have all knowledge of the | |
486 | * configuration in advance. It is given this information piecemeal by the | |
487 | * composite gadget framework after every SET_CONFIGURATION and | |
488 | * SET_INTERFACE. Trying to follow the databook programming model in this | |
489 | * scenario can cause errors. For two reasons: | |
c4509601 | 490 | * |
bfad65ee FB |
491 | * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every |
492 | * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is | |
493 | * incorrect in the scenario of multiple interfaces. | |
494 | * | |
495 | * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new | |
c4509601 JY |
496 | * endpoint on alt setting (8.1.6). |
497 | * | |
498 | * The following simplified method is used instead: | |
499 | * | |
bfad65ee FB |
500 | * All hardware endpoints can be assigned a transfer resource and this setting |
501 | * will stay persistent until either a core reset or hibernation. So whenever we | |
502 | * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do | |
503 | * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are | |
c4509601 JY |
504 | * guaranteed that there are as many transfer resources as endpoints. |
505 | * | |
bfad65ee FB |
506 | * This function is called for each endpoint when it is being enabled but is |
507 | * triggered only when called for EP0-out, which always happens first, and which | |
508 | * should only happen in one of the above conditions. | |
c4509601 | 509 | */ |
b07c2db8 | 510 | static int dwc3_gadget_start_config(struct dwc3_ep *dep) |
72246da4 FB |
511 | { |
512 | struct dwc3_gadget_ep_cmd_params params; | |
b07c2db8 | 513 | struct dwc3 *dwc; |
72246da4 | 514 | u32 cmd; |
c4509601 JY |
515 | int i; |
516 | int ret; | |
517 | ||
518 | if (dep->number) | |
519 | return 0; | |
72246da4 FB |
520 | |
521 | memset(¶ms, 0x00, sizeof(params)); | |
c4509601 | 522 | cmd = DWC3_DEPCMD_DEPSTARTCFG; |
b07c2db8 | 523 | dwc = dep->dwc; |
72246da4 | 524 | |
2cd4718d | 525 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
c4509601 JY |
526 | if (ret) |
527 | return ret; | |
528 | ||
529 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
530 | struct dwc3_ep *dep = dwc->eps[i]; | |
72246da4 | 531 | |
c4509601 JY |
532 | if (!dep) |
533 | continue; | |
534 | ||
b07c2db8 | 535 | ret = dwc3_gadget_set_xfer_resource(dep); |
c4509601 JY |
536 | if (ret) |
537 | return ret; | |
72246da4 FB |
538 | } |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
b07c2db8 | 543 | static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action) |
72246da4 | 544 | { |
39ebb05c JY |
545 | const struct usb_ss_ep_comp_descriptor *comp_desc; |
546 | const struct usb_endpoint_descriptor *desc; | |
72246da4 | 547 | struct dwc3_gadget_ep_cmd_params params; |
b07c2db8 | 548 | struct dwc3 *dwc = dep->dwc; |
72246da4 | 549 | |
39ebb05c JY |
550 | comp_desc = dep->endpoint.comp_desc; |
551 | desc = dep->endpoint.desc; | |
552 | ||
72246da4 FB |
553 | memset(¶ms, 0x00, sizeof(params)); |
554 | ||
dc1c70a7 | 555 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
556 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
557 | ||
558 | /* Burst size is only needed in SuperSpeed mode */ | |
ee5cd41c | 559 | if (dwc->gadget.speed >= USB_SPEED_SUPER) { |
676e3497 | 560 | u32 burst = dep->endpoint.maxburst; |
676e3497 | 561 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1); |
d2e9a13a | 562 | } |
72246da4 | 563 | |
a2d23f08 FB |
564 | params.param0 |= action; |
565 | if (action == DWC3_DEPCFG_ACTION_RESTORE) | |
265b70a7 | 566 | params.param2 |= dep->saved_state; |
265b70a7 | 567 | |
4bc48c97 FB |
568 | if (usb_endpoint_xfer_control(desc)) |
569 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN; | |
13fa2e69 FB |
570 | |
571 | if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc)) | |
572 | params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 573 | |
18b7ede5 | 574 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 FB |
575 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
576 | | DWC3_DEPCFG_STREAM_EVENT_EN; | |
879631aa FB |
577 | dep->stream_capable = true; |
578 | } | |
579 | ||
0b93a4c8 | 580 | if (!usb_endpoint_xfer_control(desc)) |
dc1c70a7 | 581 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
582 | |
583 | /* | |
584 | * We are doing 1:1 mapping for endpoints, meaning | |
585 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
586 | * so on. We consider the direction bit as part of the physical | |
587 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
588 | */ | |
dc1c70a7 | 589 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
590 | |
591 | /* | |
592 | * We must use the lower 16 TX FIFOs even though | |
593 | * HW might have more | |
594 | */ | |
595 | if (dep->direction) | |
dc1c70a7 | 596 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
597 | |
598 | if (desc->bInterval) { | |
dc1c70a7 | 599 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
72246da4 FB |
600 | dep->interval = 1 << (desc->bInterval - 1); |
601 | } | |
602 | ||
2cd4718d | 603 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms); |
72246da4 FB |
604 | } |
605 | ||
72246da4 | 606 | /** |
bfad65ee | 607 | * __dwc3_gadget_ep_enable - initializes a hw endpoint |
72246da4 | 608 | * @dep: endpoint to be initialized |
a2d23f08 | 609 | * @action: one of INIT, MODIFY or RESTORE |
72246da4 | 610 | * |
bfad65ee FB |
611 | * Caller should take care of locking. Execute all necessary commands to |
612 | * initialize a HW endpoint so it can be used by a gadget driver. | |
72246da4 | 613 | */ |
a2d23f08 | 614 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) |
72246da4 | 615 | { |
39ebb05c | 616 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
72246da4 | 617 | struct dwc3 *dwc = dep->dwc; |
39ebb05c | 618 | |
72246da4 | 619 | u32 reg; |
b09e99ee | 620 | int ret; |
72246da4 FB |
621 | |
622 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
b07c2db8 | 623 | ret = dwc3_gadget_start_config(dep); |
72246da4 FB |
624 | if (ret) |
625 | return ret; | |
626 | } | |
627 | ||
b07c2db8 | 628 | ret = dwc3_gadget_set_ep_config(dep, action); |
72246da4 FB |
629 | if (ret) |
630 | return ret; | |
631 | ||
632 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
633 | struct dwc3_trb *trb_st_hw; |
634 | struct dwc3_trb *trb_link; | |
72246da4 | 635 | |
72246da4 FB |
636 | dep->type = usb_endpoint_type(desc); |
637 | dep->flags |= DWC3_EP_ENABLED; | |
638 | ||
639 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
640 | reg |= DWC3_DALEPENA_EP(dep->number); | |
641 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
642 | ||
36b68aae | 643 | if (usb_endpoint_xfer_control(desc)) |
2870e501 | 644 | goto out; |
72246da4 | 645 | |
0d25744a JY |
646 | /* Initialize the TRB ring */ |
647 | dep->trb_dequeue = 0; | |
648 | dep->trb_enqueue = 0; | |
649 | memset(dep->trb_pool, 0, | |
650 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM); | |
651 | ||
36b68aae | 652 | /* Link TRB. The HWO bit is never reset */ |
72246da4 FB |
653 | trb_st_hw = &dep->trb_pool[0]; |
654 | ||
f6bafc6a | 655 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
f6bafc6a FB |
656 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
657 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
658 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
659 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
660 | } |
661 | ||
a97ea994 FB |
662 | /* |
663 | * Issue StartTransfer here with no-op TRB so we can always rely on No | |
664 | * Response Update Transfer command. | |
665 | */ | |
26d62b4d | 666 | if ((usb_endpoint_xfer_bulk(desc) && !dep->stream_capable) || |
52fcc0be | 667 | usb_endpoint_xfer_int(desc)) { |
a97ea994 FB |
668 | struct dwc3_gadget_ep_cmd_params params; |
669 | struct dwc3_trb *trb; | |
670 | dma_addr_t trb_dma; | |
671 | u32 cmd; | |
672 | ||
673 | memset(¶ms, 0, sizeof(params)); | |
674 | trb = &dep->trb_pool[0]; | |
675 | trb_dma = dwc3_trb_dma_offset(dep, trb); | |
676 | ||
677 | params.param0 = upper_32_bits(trb_dma); | |
678 | params.param1 = lower_32_bits(trb_dma); | |
679 | ||
680 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
681 | ||
682 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
683 | if (ret < 0) | |
684 | return ret; | |
a97ea994 FB |
685 | } |
686 | ||
2870e501 FB |
687 | out: |
688 | trace_dwc3_gadget_ep_enable(dep); | |
689 | ||
72246da4 FB |
690 | return 0; |
691 | } | |
692 | ||
c5353b22 FB |
693 | static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, |
694 | bool interrupt); | |
624407f9 | 695 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) |
72246da4 FB |
696 | { |
697 | struct dwc3_request *req; | |
698 | ||
c5353b22 | 699 | dwc3_stop_active_transfer(dep, true, false); |
624407f9 | 700 | |
0e146028 FB |
701 | /* - giveback all requests to gadget driver */ |
702 | while (!list_empty(&dep->started_list)) { | |
703 | req = next_request(&dep->started_list); | |
1591633e | 704 | |
0e146028 | 705 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
ea53b882 FB |
706 | } |
707 | ||
aa3342c8 FB |
708 | while (!list_empty(&dep->pending_list)) { |
709 | req = next_request(&dep->pending_list); | |
72246da4 | 710 | |
d8eca64e FB |
711 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
712 | } | |
713 | ||
714 | while (!list_empty(&dep->cancelled_list)) { | |
715 | req = next_request(&dep->cancelled_list); | |
716 | ||
624407f9 | 717 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 718 | } |
72246da4 FB |
719 | } |
720 | ||
721 | /** | |
bfad65ee | 722 | * __dwc3_gadget_ep_disable - disables a hw endpoint |
72246da4 FB |
723 | * @dep: the endpoint to disable |
724 | * | |
bfad65ee FB |
725 | * This function undoes what __dwc3_gadget_ep_enable did and also removes |
726 | * requests which are currently being processed by the hardware and those which | |
727 | * are not yet scheduled. | |
728 | * | |
624407f9 | 729 | * Caller should take care of locking. |
72246da4 | 730 | */ |
72246da4 FB |
731 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
732 | { | |
733 | struct dwc3 *dwc = dep->dwc; | |
734 | u32 reg; | |
735 | ||
2870e501 | 736 | trace_dwc3_gadget_ep_disable(dep); |
7eaeac5c | 737 | |
624407f9 | 738 | dwc3_remove_requests(dwc, dep); |
72246da4 | 739 | |
687ef981 FB |
740 | /* make sure HW endpoint isn't stalled */ |
741 | if (dep->flags & DWC3_EP_STALL) | |
7a608559 | 742 | __dwc3_gadget_ep_set_halt(dep, 0, false); |
687ef981 | 743 | |
72246da4 FB |
744 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
745 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
746 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
747 | ||
879631aa | 748 | dep->stream_capable = false; |
72246da4 | 749 | dep->type = 0; |
3aec9915 | 750 | dep->flags = 0; |
72246da4 | 751 | |
39ebb05c JY |
752 | /* Clear out the ep descriptors for non-ep0 */ |
753 | if (dep->number > 1) { | |
754 | dep->endpoint.comp_desc = NULL; | |
755 | dep->endpoint.desc = NULL; | |
756 | } | |
757 | ||
72246da4 FB |
758 | return 0; |
759 | } | |
760 | ||
761 | /* -------------------------------------------------------------------------- */ | |
762 | ||
763 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
764 | const struct usb_endpoint_descriptor *desc) | |
765 | { | |
766 | return -EINVAL; | |
767 | } | |
768 | ||
769 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
770 | { | |
771 | return -EINVAL; | |
772 | } | |
773 | ||
774 | /* -------------------------------------------------------------------------- */ | |
775 | ||
776 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
777 | const struct usb_endpoint_descriptor *desc) | |
778 | { | |
779 | struct dwc3_ep *dep; | |
780 | struct dwc3 *dwc; | |
781 | unsigned long flags; | |
782 | int ret; | |
783 | ||
784 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
785 | pr_debug("dwc3: invalid parameters\n"); | |
786 | return -EINVAL; | |
787 | } | |
788 | ||
789 | if (!desc->wMaxPacketSize) { | |
790 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
791 | return -EINVAL; | |
792 | } | |
793 | ||
794 | dep = to_dwc3_ep(ep); | |
795 | dwc = dep->dwc; | |
796 | ||
95ca961c FB |
797 | if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED, |
798 | "%s is already enabled\n", | |
799 | dep->name)) | |
c6f83f38 | 800 | return 0; |
c6f83f38 | 801 | |
72246da4 | 802 | spin_lock_irqsave(&dwc->lock, flags); |
a2d23f08 | 803 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
804 | spin_unlock_irqrestore(&dwc->lock, flags); |
805 | ||
806 | return ret; | |
807 | } | |
808 | ||
809 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
810 | { | |
811 | struct dwc3_ep *dep; | |
812 | struct dwc3 *dwc; | |
813 | unsigned long flags; | |
814 | int ret; | |
815 | ||
816 | if (!ep) { | |
817 | pr_debug("dwc3: invalid parameters\n"); | |
818 | return -EINVAL; | |
819 | } | |
820 | ||
821 | dep = to_dwc3_ep(ep); | |
822 | dwc = dep->dwc; | |
823 | ||
95ca961c FB |
824 | if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED), |
825 | "%s is already disabled\n", | |
826 | dep->name)) | |
72246da4 | 827 | return 0; |
72246da4 | 828 | |
72246da4 FB |
829 | spin_lock_irqsave(&dwc->lock, flags); |
830 | ret = __dwc3_gadget_ep_disable(dep); | |
831 | spin_unlock_irqrestore(&dwc->lock, flags); | |
832 | ||
833 | return ret; | |
834 | } | |
835 | ||
836 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
0bd0f6d2 | 837 | gfp_t gfp_flags) |
72246da4 FB |
838 | { |
839 | struct dwc3_request *req; | |
840 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
72246da4 FB |
841 | |
842 | req = kzalloc(sizeof(*req), gfp_flags); | |
734d5a53 | 843 | if (!req) |
72246da4 | 844 | return NULL; |
72246da4 | 845 | |
31a2f5a7 | 846 | req->direction = dep->direction; |
72246da4 FB |
847 | req->epnum = dep->number; |
848 | req->dep = dep; | |
a3af5e3a | 849 | req->status = DWC3_REQUEST_STATUS_UNKNOWN; |
72246da4 | 850 | |
2c4cbe6e FB |
851 | trace_dwc3_alloc_request(req); |
852 | ||
72246da4 FB |
853 | return &req->request; |
854 | } | |
855 | ||
856 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
857 | struct usb_request *request) | |
858 | { | |
859 | struct dwc3_request *req = to_dwc3_request(request); | |
860 | ||
2c4cbe6e | 861 | trace_dwc3_free_request(req); |
72246da4 FB |
862 | kfree(req); |
863 | } | |
864 | ||
42626919 FB |
865 | /** |
866 | * dwc3_ep_prev_trb - returns the previous TRB in the ring | |
867 | * @dep: The endpoint with the TRB ring | |
868 | * @index: The index of the current TRB in the ring | |
869 | * | |
870 | * Returns the TRB prior to the one pointed to by the index. If the | |
871 | * index is 0, we will wrap backwards, skip the link TRB, and return | |
872 | * the one just before that. | |
873 | */ | |
874 | static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index) | |
875 | { | |
876 | u8 tmp = index; | |
877 | ||
878 | if (!tmp) | |
879 | tmp = DWC3_TRB_NUM - 1; | |
880 | ||
881 | return &dep->trb_pool[tmp - 1]; | |
882 | } | |
883 | ||
884 | static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep) | |
885 | { | |
886 | struct dwc3_trb *tmp; | |
887 | u8 trbs_left; | |
888 | ||
889 | /* | |
890 | * If enqueue & dequeue are equal than it is either full or empty. | |
891 | * | |
892 | * One way to know for sure is if the TRB right before us has HWO bit | |
893 | * set or not. If it has, then we're definitely full and can't fit any | |
894 | * more transfers in our ring. | |
895 | */ | |
896 | if (dep->trb_enqueue == dep->trb_dequeue) { | |
897 | tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue); | |
898 | if (tmp->ctrl & DWC3_TRB_CTRL_HWO) | |
899 | return 0; | |
900 | ||
901 | return DWC3_TRB_NUM - 1; | |
902 | } | |
903 | ||
904 | trbs_left = dep->trb_dequeue - dep->trb_enqueue; | |
905 | trbs_left &= (DWC3_TRB_NUM - 1); | |
906 | ||
907 | if (dep->trb_dequeue < dep->trb_enqueue) | |
908 | trbs_left--; | |
909 | ||
910 | return trbs_left; | |
911 | } | |
2c78c029 | 912 | |
e49d3cf4 FB |
913 | static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb, |
914 | dma_addr_t dma, unsigned length, unsigned chain, unsigned node, | |
915 | unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt) | |
c71fc37c | 916 | { |
6b9018d4 FB |
917 | struct dwc3 *dwc = dep->dwc; |
918 | struct usb_gadget *gadget = &dwc->gadget; | |
919 | enum usb_device_speed speed = gadget->speed; | |
c71fc37c | 920 | |
f6bafc6a FB |
921 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
922 | trb->bpl = lower_32_bits(dma); | |
923 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 924 | |
16e78db7 | 925 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 926 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 927 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
928 | break; |
929 | ||
930 | case USB_ENDPOINT_XFER_ISOC: | |
6b9018d4 | 931 | if (!node) { |
e5ba5ec8 | 932 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; |
6b9018d4 | 933 | |
40d829fb MG |
934 | /* |
935 | * USB Specification 2.0 Section 5.9.2 states that: "If | |
936 | * there is only a single transaction in the microframe, | |
937 | * only a DATA0 data packet PID is used. If there are | |
938 | * two transactions per microframe, DATA1 is used for | |
939 | * the first transaction data packet and DATA0 is used | |
940 | * for the second transaction data packet. If there are | |
941 | * three transactions per microframe, DATA2 is used for | |
942 | * the first transaction data packet, DATA1 is used for | |
943 | * the second, and DATA0 is used for the third." | |
944 | * | |
945 | * IOW, we should satisfy the following cases: | |
946 | * | |
947 | * 1) length <= maxpacket | |
948 | * - DATA0 | |
949 | * | |
950 | * 2) maxpacket < length <= (2 * maxpacket) | |
951 | * - DATA1, DATA0 | |
952 | * | |
953 | * 3) (2 * maxpacket) < length <= (3 * maxpacket) | |
954 | * - DATA2, DATA1, DATA0 | |
955 | */ | |
6b9018d4 FB |
956 | if (speed == USB_SPEED_HIGH) { |
957 | struct usb_ep *ep = &dep->endpoint; | |
ec5bb87e | 958 | unsigned int mult = 2; |
40d829fb MG |
959 | unsigned int maxp = usb_endpoint_maxp(ep->desc); |
960 | ||
961 | if (length <= (2 * maxp)) | |
962 | mult--; | |
963 | ||
964 | if (length <= maxp) | |
965 | mult--; | |
966 | ||
967 | trb->size |= DWC3_TRB_SIZE_PCM1(mult); | |
6b9018d4 FB |
968 | } |
969 | } else { | |
e5ba5ec8 | 970 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; |
6b9018d4 | 971 | } |
ca4d44ea FB |
972 | |
973 | /* always enable Interrupt on Missed ISOC */ | |
974 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; | |
c71fc37c FB |
975 | break; |
976 | ||
977 | case USB_ENDPOINT_XFER_BULK: | |
978 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 979 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
980 | break; |
981 | default: | |
982 | /* | |
983 | * This is only possible with faulty memory because we | |
984 | * checked it already :) | |
985 | */ | |
0a695d4c FB |
986 | dev_WARN(dwc->dev, "Unknown endpoint type %d\n", |
987 | usb_endpoint_type(dep->endpoint.desc)); | |
c71fc37c FB |
988 | } |
989 | ||
244add8e TJ |
990 | /* |
991 | * Enable Continue on Short Packet | |
992 | * when endpoint is not a stream capable | |
993 | */ | |
c9508c8c | 994 | if (usb_endpoint_dir_out(dep->endpoint.desc)) { |
244add8e TJ |
995 | if (!dep->stream_capable) |
996 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
f3af3651 | 997 | |
e49d3cf4 | 998 | if (short_not_ok) |
c9508c8c FB |
999 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; |
1000 | } | |
1001 | ||
e49d3cf4 | 1002 | if ((!no_interrupt && !chain) || |
b7a4fbe2 | 1003 | (dwc3_calc_trbs_left(dep) == 1)) |
c9508c8c | 1004 | trb->ctrl |= DWC3_TRB_CTRL_IOC; |
f3af3651 | 1005 | |
e5ba5ec8 PA |
1006 | if (chain) |
1007 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
1008 | ||
16e78db7 | 1009 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
e49d3cf4 | 1010 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id); |
c71fc37c | 1011 | |
f6bafc6a | 1012 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
2c4cbe6e | 1013 | |
b7a4fbe2 AKV |
1014 | dwc3_ep_inc_enq(dep); |
1015 | ||
2c4cbe6e | 1016 | trace_dwc3_prepare_trb(dep, trb); |
c71fc37c FB |
1017 | } |
1018 | ||
e49d3cf4 FB |
1019 | /** |
1020 | * dwc3_prepare_one_trb - setup one TRB from one request | |
1021 | * @dep: endpoint for which this request is prepared | |
1022 | * @req: dwc3_request pointer | |
1023 | * @chain: should this TRB be chained to the next? | |
1024 | * @node: only for isochronous endpoints. First TRB needs different type. | |
1025 | */ | |
1026 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, | |
1027 | struct dwc3_request *req, unsigned chain, unsigned node) | |
1028 | { | |
1029 | struct dwc3_trb *trb; | |
a31e63b6 AKV |
1030 | unsigned int length; |
1031 | dma_addr_t dma; | |
e49d3cf4 FB |
1032 | unsigned stream_id = req->request.stream_id; |
1033 | unsigned short_not_ok = req->request.short_not_ok; | |
1034 | unsigned no_interrupt = req->request.no_interrupt; | |
a31e63b6 AKV |
1035 | |
1036 | if (req->request.num_sgs > 0) { | |
1037 | length = sg_dma_len(req->start_sg); | |
1038 | dma = sg_dma_address(req->start_sg); | |
1039 | } else { | |
1040 | length = req->request.length; | |
1041 | dma = req->request.dma; | |
1042 | } | |
e49d3cf4 FB |
1043 | |
1044 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
1045 | ||
1046 | if (!req->trb) { | |
1047 | dwc3_gadget_move_started_request(req); | |
1048 | req->trb = trb; | |
1049 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
e49d3cf4 FB |
1050 | } |
1051 | ||
09fe1f8d FB |
1052 | req->num_trbs++; |
1053 | ||
e49d3cf4 FB |
1054 | __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node, |
1055 | stream_id, short_not_ok, no_interrupt); | |
1056 | } | |
1057 | ||
5ee85d89 | 1058 | static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep, |
7ae7df49 | 1059 | struct dwc3_request *req) |
5ee85d89 | 1060 | { |
a31e63b6 | 1061 | struct scatterlist *sg = req->start_sg; |
5ee85d89 | 1062 | struct scatterlist *s; |
5ee85d89 FB |
1063 | int i; |
1064 | ||
c96e6725 AKV |
1065 | unsigned int remaining = req->request.num_mapped_sgs |
1066 | - req->num_queued_sgs; | |
1067 | ||
1068 | for_each_sg(sg, s, remaining, i) { | |
c6267a51 FB |
1069 | unsigned int length = req->request.length; |
1070 | unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc); | |
1071 | unsigned int rem = length % maxp; | |
5ee85d89 FB |
1072 | unsigned chain = true; |
1073 | ||
dad2aff3 PP |
1074 | /* |
1075 | * IOMMU driver is coalescing the list of sgs which shares a | |
1076 | * page boundary into one and giving it to USB driver. With | |
1077 | * this the number of sgs mapped is not equal to the number of | |
1078 | * sgs passed. So mark the chain bit to false if it isthe last | |
1079 | * mapped sg. | |
1080 | */ | |
1081 | if (i == remaining - 1) | |
5ee85d89 FB |
1082 | chain = false; |
1083 | ||
c6267a51 FB |
1084 | if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) { |
1085 | struct dwc3 *dwc = dep->dwc; | |
1086 | struct dwc3_trb *trb; | |
1087 | ||
1a22ec64 | 1088 | req->needs_extra_trb = true; |
c6267a51 FB |
1089 | |
1090 | /* prepare normal TRB */ | |
1091 | dwc3_prepare_one_trb(dep, req, true, i); | |
1092 | ||
1093 | /* Now prepare one extra TRB to align transfer size */ | |
1094 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
09fe1f8d | 1095 | req->num_trbs++; |
c6267a51 | 1096 | __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, |
2fc6d4be | 1097 | maxp - rem, false, 1, |
c6267a51 FB |
1098 | req->request.stream_id, |
1099 | req->request.short_not_ok, | |
1100 | req->request.no_interrupt); | |
1101 | } else { | |
1102 | dwc3_prepare_one_trb(dep, req, chain, i); | |
1103 | } | |
5ee85d89 | 1104 | |
a31e63b6 AKV |
1105 | /* |
1106 | * There can be a situation where all sgs in sglist are not | |
1107 | * queued because of insufficient trb number. To handle this | |
1108 | * case, update start_sg to next sg to be queued, so that | |
1109 | * we have free trbs we can continue queuing from where we | |
1110 | * previously stopped | |
1111 | */ | |
1112 | if (chain) | |
1113 | req->start_sg = sg_next(s); | |
1114 | ||
c96e6725 AKV |
1115 | req->num_queued_sgs++; |
1116 | ||
7ae7df49 | 1117 | if (!dwc3_calc_trbs_left(dep)) |
5ee85d89 FB |
1118 | break; |
1119 | } | |
1120 | } | |
1121 | ||
1122 | static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep, | |
7ae7df49 | 1123 | struct dwc3_request *req) |
5ee85d89 | 1124 | { |
c6267a51 FB |
1125 | unsigned int length = req->request.length; |
1126 | unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc); | |
1127 | unsigned int rem = length % maxp; | |
1128 | ||
1e19cdc8 | 1129 | if ((!length || rem) && usb_endpoint_dir_out(dep->endpoint.desc)) { |
c6267a51 FB |
1130 | struct dwc3 *dwc = dep->dwc; |
1131 | struct dwc3_trb *trb; | |
1132 | ||
1a22ec64 | 1133 | req->needs_extra_trb = true; |
c6267a51 FB |
1134 | |
1135 | /* prepare normal TRB */ | |
1136 | dwc3_prepare_one_trb(dep, req, true, 0); | |
1137 | ||
1138 | /* Now prepare one extra TRB to align transfer size */ | |
1139 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
09fe1f8d | 1140 | req->num_trbs++; |
c6267a51 | 1141 | __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem, |
2fc6d4be | 1142 | false, 1, req->request.stream_id, |
c6267a51 FB |
1143 | req->request.short_not_ok, |
1144 | req->request.no_interrupt); | |
d6e5a549 | 1145 | } else if (req->request.zero && req->request.length && |
4ea438da | 1146 | (IS_ALIGNED(req->request.length, maxp))) { |
d6e5a549 FB |
1147 | struct dwc3 *dwc = dep->dwc; |
1148 | struct dwc3_trb *trb; | |
1149 | ||
1a22ec64 | 1150 | req->needs_extra_trb = true; |
d6e5a549 FB |
1151 | |
1152 | /* prepare normal TRB */ | |
1153 | dwc3_prepare_one_trb(dep, req, true, 0); | |
1154 | ||
1155 | /* Now prepare one extra TRB to handle ZLP */ | |
1156 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
09fe1f8d | 1157 | req->num_trbs++; |
d6e5a549 | 1158 | __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0, |
2fc6d4be | 1159 | false, 1, req->request.stream_id, |
d6e5a549 FB |
1160 | req->request.short_not_ok, |
1161 | req->request.no_interrupt); | |
c6267a51 FB |
1162 | } else { |
1163 | dwc3_prepare_one_trb(dep, req, false, 0); | |
1164 | } | |
5ee85d89 FB |
1165 | } |
1166 | ||
72246da4 FB |
1167 | /* |
1168 | * dwc3_prepare_trbs - setup TRBs from requests | |
1169 | * @dep: endpoint for which requests are being prepared | |
72246da4 | 1170 | * |
1d046793 PZ |
1171 | * The function goes through the requests list and sets up TRBs for the |
1172 | * transfers. The function returns once there are no more TRBs available or | |
1173 | * it runs out of requests. | |
72246da4 | 1174 | */ |
c4233573 | 1175 | static void dwc3_prepare_trbs(struct dwc3_ep *dep) |
72246da4 | 1176 | { |
68e823e2 | 1177 | struct dwc3_request *req, *n; |
72246da4 FB |
1178 | |
1179 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
1180 | ||
d86c5a67 FB |
1181 | /* |
1182 | * We can get in a situation where there's a request in the started list | |
1183 | * but there weren't enough TRBs to fully kick it in the first time | |
1184 | * around, so it has been waiting for more TRBs to be freed up. | |
1185 | * | |
1186 | * In that case, we should check if we have a request with pending_sgs | |
1187 | * in the started list and prepare TRBs for that request first, | |
1188 | * otherwise we will prepare TRBs completely out of order and that will | |
1189 | * break things. | |
1190 | */ | |
1191 | list_for_each_entry(req, &dep->started_list, list) { | |
1192 | if (req->num_pending_sgs > 0) | |
1193 | dwc3_prepare_one_trb_sg(dep, req); | |
1194 | ||
1195 | if (!dwc3_calc_trbs_left(dep)) | |
1196 | return; | |
1197 | } | |
1198 | ||
aa3342c8 | 1199 | list_for_each_entry_safe(req, n, &dep->pending_list, list) { |
cdb55b39 FB |
1200 | struct dwc3 *dwc = dep->dwc; |
1201 | int ret; | |
1202 | ||
1203 | ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request, | |
1204 | dep->direction); | |
1205 | if (ret) | |
1206 | return; | |
1207 | ||
1208 | req->sg = req->request.sg; | |
a31e63b6 | 1209 | req->start_sg = req->sg; |
c96e6725 | 1210 | req->num_queued_sgs = 0; |
cdb55b39 FB |
1211 | req->num_pending_sgs = req->request.num_mapped_sgs; |
1212 | ||
1f512119 | 1213 | if (req->num_pending_sgs > 0) |
7ae7df49 | 1214 | dwc3_prepare_one_trb_sg(dep, req); |
5ee85d89 | 1215 | else |
7ae7df49 | 1216 | dwc3_prepare_one_trb_linear(dep, req); |
72246da4 | 1217 | |
7ae7df49 | 1218 | if (!dwc3_calc_trbs_left(dep)) |
5ee85d89 | 1219 | return; |
72246da4 | 1220 | } |
72246da4 FB |
1221 | } |
1222 | ||
7fdca766 | 1223 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep) |
72246da4 FB |
1224 | { |
1225 | struct dwc3_gadget_ep_cmd_params params; | |
1226 | struct dwc3_request *req; | |
4fae2e3e | 1227 | int starting; |
72246da4 FB |
1228 | int ret; |
1229 | u32 cmd; | |
1230 | ||
ccb94ebf FB |
1231 | if (!dwc3_calc_trbs_left(dep)) |
1232 | return 0; | |
1233 | ||
1912cbc6 | 1234 | starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED); |
72246da4 | 1235 | |
4fae2e3e FB |
1236 | dwc3_prepare_trbs(dep); |
1237 | req = next_request(&dep->started_list); | |
72246da4 FB |
1238 | if (!req) { |
1239 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
1240 | return 0; | |
1241 | } | |
1242 | ||
1243 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 1244 | |
4fae2e3e | 1245 | if (starting) { |
1877d6c9 PA |
1246 | params.param0 = upper_32_bits(req->trb_dma); |
1247 | params.param1 = lower_32_bits(req->trb_dma); | |
7fdca766 FB |
1248 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
1249 | ||
a7351807 AKV |
1250 | if (dep->stream_capable) |
1251 | cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id); | |
1252 | ||
7fdca766 FB |
1253 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
1254 | cmd |= DWC3_DEPCMD_PARAM(dep->frame_number); | |
1877d6c9 | 1255 | } else { |
b6b1c6db FB |
1256 | cmd = DWC3_DEPCMD_UPDATETRANSFER | |
1257 | DWC3_DEPCMD_PARAM(dep->resource_index); | |
1877d6c9 | 1258 | } |
72246da4 | 1259 | |
2cd4718d | 1260 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
72246da4 | 1261 | if (ret < 0) { |
72246da4 FB |
1262 | /* |
1263 | * FIXME we need to iterate over the list of requests | |
1264 | * here and stop, unmap, free and del each of the linked | |
1d046793 | 1265 | * requests instead of what we do now. |
72246da4 | 1266 | */ |
ce3fc8b3 JD |
1267 | if (req->trb) |
1268 | memset(req->trb, 0, sizeof(struct dwc3_trb)); | |
c91815b5 | 1269 | dwc3_gadget_del_and_unmap_request(dep, req, ret); |
72246da4 FB |
1270 | return ret; |
1271 | } | |
1272 | ||
72246da4 FB |
1273 | return 0; |
1274 | } | |
1275 | ||
6cb2e4e3 FB |
1276 | static int __dwc3_gadget_get_frame(struct dwc3 *dwc) |
1277 | { | |
1278 | u32 reg; | |
1279 | ||
1280 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1281 | return DWC3_DSTS_SOFFN(reg); | |
1282 | } | |
1283 | ||
d92021f6 TN |
1284 | /** |
1285 | * dwc3_gadget_start_isoc_quirk - workaround invalid frame number | |
1286 | * @dep: isoc endpoint | |
1287 | * | |
1288 | * This function tests for the correct combination of BIT[15:14] from the 16-bit | |
1289 | * microframe number reported by the XferNotReady event for the future frame | |
1290 | * number to start the isoc transfer. | |
1291 | * | |
1292 | * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed | |
1293 | * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the | |
1294 | * XferNotReady event are invalid. The driver uses this number to schedule the | |
1295 | * isochronous transfer and passes it to the START TRANSFER command. Because | |
1296 | * this number is invalid, the command may fail. If BIT[15:14] matches the | |
1297 | * internal 16-bit microframe, the START TRANSFER command will pass and the | |
1298 | * transfer will start at the scheduled time, if it is off by 1, the command | |
1299 | * will still pass, but the transfer will start 2 seconds in the future. For all | |
1300 | * other conditions, the START TRANSFER command will fail with bus-expiry. | |
1301 | * | |
1302 | * In order to workaround this issue, we can test for the correct combination of | |
1303 | * BIT[15:14] by sending START TRANSFER commands with different values of | |
1304 | * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart | |
1305 | * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status. | |
1306 | * As the result, within the 4 possible combinations for BIT[15:14], there will | |
1307 | * be 2 successful and 2 failure START COMMAND status. One of the 2 successful | |
1308 | * command status will result in a 2-second delay start. The smaller BIT[15:14] | |
1309 | * value is the correct combination. | |
1310 | * | |
1311 | * Since there are only 4 outcomes and the results are ordered, we can simply | |
1312 | * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to | |
1313 | * deduce the smaller successful combination. | |
1314 | * | |
1315 | * Let test0 = test status for combination 'b00 and test1 = test status for 'b01 | |
1316 | * of BIT[15:14]. The correct combination is as follow: | |
1317 | * | |
1318 | * if test0 fails and test1 passes, BIT[15:14] is 'b01 | |
1319 | * if test0 fails and test1 fails, BIT[15:14] is 'b10 | |
1320 | * if test0 passes and test1 fails, BIT[15:14] is 'b11 | |
1321 | * if test0 passes and test1 passes, BIT[15:14] is 'b00 | |
1322 | * | |
1323 | * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN | |
1324 | * endpoints. | |
1325 | */ | |
25abad6a | 1326 | static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep) |
d92021f6 TN |
1327 | { |
1328 | int cmd_status = 0; | |
1329 | bool test0; | |
1330 | bool test1; | |
1331 | ||
1332 | while (dep->combo_num < 2) { | |
1333 | struct dwc3_gadget_ep_cmd_params params; | |
1334 | u32 test_frame_number; | |
1335 | u32 cmd; | |
1336 | ||
1337 | /* | |
1338 | * Check if we can start isoc transfer on the next interval or | |
1339 | * 4 uframes in the future with BIT[15:14] as dep->combo_num | |
1340 | */ | |
1341 | test_frame_number = dep->frame_number & 0x3fff; | |
1342 | test_frame_number |= dep->combo_num << 14; | |
1343 | test_frame_number += max_t(u32, 4, dep->interval); | |
1344 | ||
1345 | params.param0 = upper_32_bits(dep->dwc->bounce_addr); | |
1346 | params.param1 = lower_32_bits(dep->dwc->bounce_addr); | |
1347 | ||
1348 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
1349 | cmd |= DWC3_DEPCMD_PARAM(test_frame_number); | |
1350 | cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
1351 | ||
1352 | /* Redo if some other failure beside bus-expiry is received */ | |
1353 | if (cmd_status && cmd_status != -EAGAIN) { | |
1354 | dep->start_cmd_status = 0; | |
1355 | dep->combo_num = 0; | |
25abad6a | 1356 | return 0; |
d92021f6 TN |
1357 | } |
1358 | ||
1359 | /* Store the first test status */ | |
1360 | if (dep->combo_num == 0) | |
1361 | dep->start_cmd_status = cmd_status; | |
1362 | ||
1363 | dep->combo_num++; | |
1364 | ||
1365 | /* | |
1366 | * End the transfer if the START_TRANSFER command is successful | |
1367 | * to wait for the next XferNotReady to test the command again | |
1368 | */ | |
1369 | if (cmd_status == 0) { | |
c5353b22 | 1370 | dwc3_stop_active_transfer(dep, true, true); |
25abad6a | 1371 | return 0; |
d92021f6 TN |
1372 | } |
1373 | } | |
1374 | ||
1375 | /* test0 and test1 are both completed at this point */ | |
1376 | test0 = (dep->start_cmd_status == 0); | |
1377 | test1 = (cmd_status == 0); | |
1378 | ||
1379 | if (!test0 && test1) | |
1380 | dep->combo_num = 1; | |
1381 | else if (!test0 && !test1) | |
1382 | dep->combo_num = 2; | |
1383 | else if (test0 && !test1) | |
1384 | dep->combo_num = 3; | |
1385 | else if (test0 && test1) | |
1386 | dep->combo_num = 0; | |
1387 | ||
1388 | dep->frame_number &= 0x3fff; | |
1389 | dep->frame_number |= dep->combo_num << 14; | |
1390 | dep->frame_number += max_t(u32, 4, dep->interval); | |
1391 | ||
1392 | /* Reinitialize test variables */ | |
1393 | dep->start_cmd_status = 0; | |
1394 | dep->combo_num = 0; | |
1395 | ||
25abad6a | 1396 | return __dwc3_gadget_kick_transfer(dep); |
d92021f6 TN |
1397 | } |
1398 | ||
25abad6a | 1399 | static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep) |
d6d6ec7b | 1400 | { |
d92021f6 | 1401 | struct dwc3 *dwc = dep->dwc; |
d5370106 FB |
1402 | int ret; |
1403 | int i; | |
d92021f6 | 1404 | |
aa3342c8 | 1405 | if (list_empty(&dep->pending_list)) { |
f4a53c55 | 1406 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
25abad6a | 1407 | return -EAGAIN; |
d6d6ec7b PA |
1408 | } |
1409 | ||
d92021f6 TN |
1410 | if (!dwc->dis_start_transfer_quirk && dwc3_is_usb31(dwc) && |
1411 | (dwc->revision <= DWC3_USB31_REVISION_160A || | |
1412 | (dwc->revision == DWC3_USB31_REVISION_170A && | |
1413 | dwc->version_type >= DWC31_VERSIONTYPE_EA01 && | |
1414 | dwc->version_type <= DWC31_VERSIONTYPE_EA06))) { | |
1415 | ||
25abad6a FB |
1416 | if (dwc->gadget.speed <= USB_SPEED_HIGH && dep->direction) |
1417 | return dwc3_gadget_start_isoc_quirk(dep); | |
d6d6ec7b PA |
1418 | } |
1419 | ||
d5370106 FB |
1420 | for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) { |
1421 | dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1); | |
1422 | ||
1423 | ret = __dwc3_gadget_kick_transfer(dep); | |
1424 | if (ret != -EAGAIN) | |
1425 | break; | |
1426 | } | |
1427 | ||
1428 | return ret; | |
d6d6ec7b PA |
1429 | } |
1430 | ||
72246da4 FB |
1431 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1432 | { | |
0fc9a1be | 1433 | struct dwc3 *dwc = dep->dwc; |
0fc9a1be | 1434 | |
bb423984 | 1435 | if (!dep->endpoint.desc) { |
5eb30ced FB |
1436 | dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", |
1437 | dep->name); | |
bb423984 FB |
1438 | return -ESHUTDOWN; |
1439 | } | |
1440 | ||
04fb365c FB |
1441 | if (WARN(req->dep != dep, "request %pK belongs to '%s'\n", |
1442 | &req->request, req->dep->name)) | |
bb423984 | 1443 | return -EINVAL; |
bb423984 | 1444 | |
b2b6d601 FB |
1445 | if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED, |
1446 | "%s: request %pK already in flight\n", | |
1447 | dep->name, &req->request)) | |
1448 | return -EINVAL; | |
1449 | ||
fc8bb91b FB |
1450 | pm_runtime_get(dwc->dev); |
1451 | ||
72246da4 FB |
1452 | req->request.actual = 0; |
1453 | req->request.status = -EINPROGRESS; | |
72246da4 | 1454 | |
fe84f522 FB |
1455 | trace_dwc3_ep_queue(req); |
1456 | ||
aa3342c8 | 1457 | list_add_tail(&req->list, &dep->pending_list); |
a3af5e3a | 1458 | req->status = DWC3_REQUEST_STATUS_QUEUED; |
72246da4 | 1459 | |
da10bcdd TN |
1460 | /* Start the transfer only after the END_TRANSFER is completed */ |
1461 | if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) { | |
1462 | dep->flags |= DWC3_EP_DELAY_START; | |
1463 | return 0; | |
1464 | } | |
1465 | ||
d889c23c FB |
1466 | /* |
1467 | * NOTICE: Isochronous endpoints should NEVER be prestarted. We must | |
1468 | * wait for a XferNotReady event so we will know what's the current | |
1469 | * (micro-)frame number. | |
1470 | * | |
1471 | * Without this trick, we are very, very likely gonna get Bus Expiry | |
1472 | * errors which will force us issue EndTransfer command. | |
1473 | */ | |
1474 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
fe990cea FB |
1475 | if (!(dep->flags & DWC3_EP_PENDING_REQUEST) && |
1476 | !(dep->flags & DWC3_EP_TRANSFER_STARTED)) | |
1477 | return 0; | |
1478 | ||
6cb2e4e3 | 1479 | if ((dep->flags & DWC3_EP_PENDING_REQUEST)) { |
fe990cea | 1480 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) { |
25abad6a | 1481 | return __dwc3_gadget_start_isoc(dep); |
6cb2e4e3 | 1482 | } |
08a36b54 | 1483 | } |
64e01080 | 1484 | } |
b997ada5 | 1485 | |
7fdca766 | 1486 | return __dwc3_gadget_kick_transfer(dep); |
72246da4 FB |
1487 | } |
1488 | ||
1489 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, | |
1490 | gfp_t gfp_flags) | |
1491 | { | |
1492 | struct dwc3_request *req = to_dwc3_request(request); | |
1493 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1494 | struct dwc3 *dwc = dep->dwc; | |
1495 | ||
1496 | unsigned long flags; | |
1497 | ||
1498 | int ret; | |
1499 | ||
fdee4eba | 1500 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1501 | ret = __dwc3_gadget_ep_queue(dep, req); |
1502 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1503 | ||
1504 | return ret; | |
1505 | } | |
1506 | ||
7746a8df FB |
1507 | static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req) |
1508 | { | |
1509 | int i; | |
1510 | ||
1511 | /* | |
1512 | * If request was already started, this means we had to | |
1513 | * stop the transfer. With that we also need to ignore | |
1514 | * all TRBs used by the request, however TRBs can only | |
1515 | * be modified after completion of END_TRANSFER | |
1516 | * command. So what we do here is that we wait for | |
1517 | * END_TRANSFER completion and only after that, we jump | |
1518 | * over TRBs by clearing HWO and incrementing dequeue | |
1519 | * pointer. | |
1520 | */ | |
1521 | for (i = 0; i < req->num_trbs; i++) { | |
1522 | struct dwc3_trb *trb; | |
1523 | ||
2dedea03 | 1524 | trb = &dep->trb_pool[dep->trb_dequeue]; |
7746a8df FB |
1525 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; |
1526 | dwc3_ep_inc_deq(dep); | |
1527 | } | |
c7152763 TN |
1528 | |
1529 | req->num_trbs = 0; | |
7746a8df FB |
1530 | } |
1531 | ||
d4f1afe5 FB |
1532 | static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep) |
1533 | { | |
1534 | struct dwc3_request *req; | |
1535 | struct dwc3_request *tmp; | |
1536 | ||
1537 | list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) { | |
1538 | dwc3_gadget_ep_skip_trbs(dep, req); | |
1539 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1540 | } | |
1541 | } | |
1542 | ||
72246da4 FB |
1543 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, |
1544 | struct usb_request *request) | |
1545 | { | |
1546 | struct dwc3_request *req = to_dwc3_request(request); | |
1547 | struct dwc3_request *r = NULL; | |
1548 | ||
1549 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1550 | struct dwc3 *dwc = dep->dwc; | |
1551 | ||
1552 | unsigned long flags; | |
1553 | int ret = 0; | |
1554 | ||
2c4cbe6e FB |
1555 | trace_dwc3_ep_dequeue(req); |
1556 | ||
72246da4 FB |
1557 | spin_lock_irqsave(&dwc->lock, flags); |
1558 | ||
aa3342c8 | 1559 | list_for_each_entry(r, &dep->pending_list, list) { |
72246da4 FB |
1560 | if (r == req) |
1561 | break; | |
1562 | } | |
1563 | ||
1564 | if (r != req) { | |
aa3342c8 | 1565 | list_for_each_entry(r, &dep->started_list, list) { |
72246da4 FB |
1566 | if (r == req) |
1567 | break; | |
1568 | } | |
1569 | if (r == req) { | |
1570 | /* wait until it is processed */ | |
c5353b22 | 1571 | dwc3_stop_active_transfer(dep, true, true); |
cf3113d8 | 1572 | |
cf3113d8 | 1573 | if (!r->trb) |
05645366 | 1574 | goto out0; |
cf3113d8 | 1575 | |
d4f1afe5 | 1576 | dwc3_gadget_move_cancelled_request(req); |
9f45581f FB |
1577 | if (dep->flags & DWC3_EP_TRANSFER_STARTED) |
1578 | goto out0; | |
1579 | else | |
1580 | goto out1; | |
72246da4 | 1581 | } |
04fb365c | 1582 | dev_err(dwc->dev, "request %pK was not queued to %s\n", |
72246da4 FB |
1583 | request, ep->name); |
1584 | ret = -EINVAL; | |
1585 | goto out0; | |
1586 | } | |
1587 | ||
9f45581f | 1588 | out1: |
72246da4 FB |
1589 | dwc3_gadget_giveback(dep, req, -ECONNRESET); |
1590 | ||
1591 | out0: | |
1592 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1593 | ||
1594 | return ret; | |
1595 | } | |
1596 | ||
7a608559 | 1597 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) |
72246da4 FB |
1598 | { |
1599 | struct dwc3_gadget_ep_cmd_params params; | |
1600 | struct dwc3 *dwc = dep->dwc; | |
1601 | int ret; | |
1602 | ||
5ad02fb8 FB |
1603 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
1604 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); | |
1605 | return -EINVAL; | |
1606 | } | |
1607 | ||
72246da4 FB |
1608 | memset(¶ms, 0x00, sizeof(params)); |
1609 | ||
1610 | if (value) { | |
69450c4d FB |
1611 | struct dwc3_trb *trb; |
1612 | ||
1613 | unsigned transfer_in_flight; | |
1614 | unsigned started; | |
1615 | ||
1616 | if (dep->number > 1) | |
1617 | trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue); | |
1618 | else | |
1619 | trb = &dwc->ep0_trb[dep->trb_enqueue]; | |
1620 | ||
1621 | transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO; | |
1622 | started = !list_empty(&dep->started_list); | |
1623 | ||
1624 | if (!protocol && ((dep->direction && transfer_in_flight) || | |
1625 | (!dep->direction && started))) { | |
7a608559 FB |
1626 | return -EAGAIN; |
1627 | } | |
1628 | ||
2cd4718d FB |
1629 | ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL, |
1630 | ¶ms); | |
72246da4 | 1631 | if (ret) |
3f89204b | 1632 | dev_err(dwc->dev, "failed to set STALL on %s\n", |
72246da4 FB |
1633 | dep->name); |
1634 | else | |
1635 | dep->flags |= DWC3_EP_STALL; | |
1636 | } else { | |
2cd4718d | 1637 | |
50c763f8 | 1638 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 | 1639 | if (ret) |
3f89204b | 1640 | dev_err(dwc->dev, "failed to clear STALL on %s\n", |
72246da4 FB |
1641 | dep->name); |
1642 | else | |
a535d81c | 1643 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); |
72246da4 | 1644 | } |
5275455a | 1645 | |
72246da4 FB |
1646 | return ret; |
1647 | } | |
1648 | ||
1649 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1650 | { | |
1651 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1652 | struct dwc3 *dwc = dep->dwc; | |
1653 | ||
1654 | unsigned long flags; | |
1655 | ||
1656 | int ret; | |
1657 | ||
1658 | spin_lock_irqsave(&dwc->lock, flags); | |
7a608559 | 1659 | ret = __dwc3_gadget_ep_set_halt(dep, value, false); |
72246da4 FB |
1660 | spin_unlock_irqrestore(&dwc->lock, flags); |
1661 | ||
1662 | return ret; | |
1663 | } | |
1664 | ||
1665 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1666 | { | |
1667 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1668 | struct dwc3 *dwc = dep->dwc; |
1669 | unsigned long flags; | |
95aa4e8d | 1670 | int ret; |
72246da4 | 1671 | |
249a4569 | 1672 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1673 | dep->flags |= DWC3_EP_WEDGE; |
1674 | ||
08f0d966 | 1675 | if (dep->number == 0 || dep->number == 1) |
95aa4e8d | 1676 | ret = __dwc3_gadget_ep0_set_halt(ep, 1); |
08f0d966 | 1677 | else |
7a608559 | 1678 | ret = __dwc3_gadget_ep_set_halt(dep, 1, false); |
95aa4e8d FB |
1679 | spin_unlock_irqrestore(&dwc->lock, flags); |
1680 | ||
1681 | return ret; | |
72246da4 FB |
1682 | } |
1683 | ||
1684 | /* -------------------------------------------------------------------------- */ | |
1685 | ||
1686 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1687 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1688 | .bDescriptorType = USB_DT_ENDPOINT, | |
1689 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1690 | }; | |
1691 | ||
1692 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1693 | .enable = dwc3_gadget_ep0_enable, | |
1694 | .disable = dwc3_gadget_ep0_disable, | |
1695 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1696 | .free_request = dwc3_gadget_ep_free_request, | |
1697 | .queue = dwc3_gadget_ep0_queue, | |
1698 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 1699 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
1700 | .set_wedge = dwc3_gadget_ep_set_wedge, |
1701 | }; | |
1702 | ||
1703 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1704 | .enable = dwc3_gadget_ep_enable, | |
1705 | .disable = dwc3_gadget_ep_disable, | |
1706 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1707 | .free_request = dwc3_gadget_ep_free_request, | |
1708 | .queue = dwc3_gadget_ep_queue, | |
1709 | .dequeue = dwc3_gadget_ep_dequeue, | |
1710 | .set_halt = dwc3_gadget_ep_set_halt, | |
1711 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1712 | }; | |
1713 | ||
1714 | /* -------------------------------------------------------------------------- */ | |
1715 | ||
1716 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1717 | { | |
1718 | struct dwc3 *dwc = gadget_to_dwc(g); | |
72246da4 | 1719 | |
6cb2e4e3 | 1720 | return __dwc3_gadget_get_frame(dwc); |
72246da4 FB |
1721 | } |
1722 | ||
218ef7b6 | 1723 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc) |
72246da4 | 1724 | { |
d6011f6f | 1725 | int retries; |
72246da4 | 1726 | |
218ef7b6 | 1727 | int ret; |
72246da4 FB |
1728 | u32 reg; |
1729 | ||
72246da4 FB |
1730 | u8 link_state; |
1731 | u8 speed; | |
1732 | ||
72246da4 FB |
1733 | /* |
1734 | * According to the Databook Remote wakeup request should | |
1735 | * be issued only when the device is in early suspend state. | |
1736 | * | |
1737 | * We can check that via USB Link State bits in DSTS register. | |
1738 | */ | |
1739 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1740 | ||
1741 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
ee5cd41c | 1742 | if ((speed == DWC3_DSTS_SUPERSPEED) || |
5eb30ced | 1743 | (speed == DWC3_DSTS_SUPERSPEED_PLUS)) |
6b742899 | 1744 | return 0; |
72246da4 FB |
1745 | |
1746 | link_state = DWC3_DSTS_USBLNKST(reg); | |
1747 | ||
1748 | switch (link_state) { | |
1749 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ | |
1750 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
1751 | break; | |
1752 | default: | |
218ef7b6 | 1753 | return -EINVAL; |
72246da4 FB |
1754 | } |
1755 | ||
8598bde7 FB |
1756 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
1757 | if (ret < 0) { | |
1758 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
218ef7b6 | 1759 | return ret; |
8598bde7 | 1760 | } |
72246da4 | 1761 | |
802fde98 PZ |
1762 | /* Recent versions do this automatically */ |
1763 | if (dwc->revision < DWC3_REVISION_194A) { | |
1764 | /* write zeroes to Link Change Request */ | |
fcc023c7 | 1765 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
1766 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
1767 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1768 | } | |
72246da4 | 1769 | |
1d046793 | 1770 | /* poll until Link State changes to ON */ |
d6011f6f | 1771 | retries = 20000; |
72246da4 | 1772 | |
d6011f6f | 1773 | while (retries--) { |
72246da4 FB |
1774 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
1775 | ||
1776 | /* in HS, means ON */ | |
1777 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1778 | break; | |
1779 | } | |
1780 | ||
1781 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1782 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
218ef7b6 | 1783 | return -EINVAL; |
72246da4 FB |
1784 | } |
1785 | ||
218ef7b6 FB |
1786 | return 0; |
1787 | } | |
1788 | ||
1789 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1790 | { | |
1791 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1792 | unsigned long flags; | |
1793 | int ret; | |
1794 | ||
1795 | spin_lock_irqsave(&dwc->lock, flags); | |
1796 | ret = __dwc3_gadget_wakeup(dwc); | |
72246da4 FB |
1797 | spin_unlock_irqrestore(&dwc->lock, flags); |
1798 | ||
1799 | return ret; | |
1800 | } | |
1801 | ||
1802 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1803 | int is_selfpowered) | |
1804 | { | |
1805 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 1806 | unsigned long flags; |
72246da4 | 1807 | |
249a4569 | 1808 | spin_lock_irqsave(&dwc->lock, flags); |
bcdea503 | 1809 | g->is_selfpowered = !!is_selfpowered; |
249a4569 | 1810 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
1811 | |
1812 | return 0; | |
1813 | } | |
1814 | ||
7b2a0368 | 1815 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) |
72246da4 FB |
1816 | { |
1817 | u32 reg; | |
61d58242 | 1818 | u32 timeout = 500; |
72246da4 | 1819 | |
fc8bb91b FB |
1820 | if (pm_runtime_suspended(dwc->dev)) |
1821 | return 0; | |
1822 | ||
72246da4 | 1823 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
8db7ed15 | 1824 | if (is_on) { |
802fde98 PZ |
1825 | if (dwc->revision <= DWC3_REVISION_187A) { |
1826 | reg &= ~DWC3_DCTL_TRGTULST_MASK; | |
1827 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
1828 | } | |
1829 | ||
1830 | if (dwc->revision >= DWC3_REVISION_194A) | |
1831 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1832 | reg |= DWC3_DCTL_RUN_STOP; | |
7b2a0368 FB |
1833 | |
1834 | if (dwc->has_hibernation) | |
1835 | reg |= DWC3_DCTL_KEEP_CONNECT; | |
1836 | ||
9fcb3bd8 | 1837 | dwc->pullups_connected = true; |
8db7ed15 | 1838 | } else { |
72246da4 | 1839 | reg &= ~DWC3_DCTL_RUN_STOP; |
7b2a0368 FB |
1840 | |
1841 | if (dwc->has_hibernation && !suspend) | |
1842 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1843 | ||
9fcb3bd8 | 1844 | dwc->pullups_connected = false; |
8db7ed15 | 1845 | } |
72246da4 | 1846 | |
5b738211 | 1847 | dwc3_gadget_dctl_write_safe(dwc, reg); |
72246da4 FB |
1848 | |
1849 | do { | |
1850 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
b6d4e16e FB |
1851 | reg &= DWC3_DSTS_DEVCTRLHLT; |
1852 | } while (--timeout && !(!is_on ^ !reg)); | |
f2df679b FB |
1853 | |
1854 | if (!timeout) | |
1855 | return -ETIMEDOUT; | |
72246da4 | 1856 | |
6f17f74b | 1857 | return 0; |
72246da4 FB |
1858 | } |
1859 | ||
1860 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1861 | { | |
1862 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1863 | unsigned long flags; | |
6f17f74b | 1864 | int ret; |
72246da4 FB |
1865 | |
1866 | is_on = !!is_on; | |
1867 | ||
bb014736 BW |
1868 | /* |
1869 | * Per databook, when we want to stop the gadget, if a control transfer | |
1870 | * is still in process, complete it and get the core into setup phase. | |
1871 | */ | |
1872 | if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) { | |
1873 | reinit_completion(&dwc->ep0_in_setup); | |
1874 | ||
1875 | ret = wait_for_completion_timeout(&dwc->ep0_in_setup, | |
1876 | msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT)); | |
1877 | if (ret == 0) { | |
1878 | dev_err(dwc->dev, "timed out waiting for SETUP phase\n"); | |
1879 | return -ETIMEDOUT; | |
1880 | } | |
1881 | } | |
1882 | ||
72246da4 | 1883 | spin_lock_irqsave(&dwc->lock, flags); |
7b2a0368 | 1884 | ret = dwc3_gadget_run_stop(dwc, is_on, false); |
72246da4 FB |
1885 | spin_unlock_irqrestore(&dwc->lock, flags); |
1886 | ||
6f17f74b | 1887 | return ret; |
72246da4 FB |
1888 | } |
1889 | ||
8698e2ac FB |
1890 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
1891 | { | |
1892 | u32 reg; | |
1893 | ||
1894 | /* Enable all but Start and End of Frame IRQs */ | |
1895 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
1896 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
1897 | DWC3_DEVTEN_CMDCMPLTEN | | |
1898 | DWC3_DEVTEN_ERRTICERREN | | |
1899 | DWC3_DEVTEN_WKUPEVTEN | | |
8698e2ac FB |
1900 | DWC3_DEVTEN_CONNECTDONEEN | |
1901 | DWC3_DEVTEN_USBRSTEN | | |
1902 | DWC3_DEVTEN_DISCONNEVTEN); | |
1903 | ||
799e9dc8 FB |
1904 | if (dwc->revision < DWC3_REVISION_250A) |
1905 | reg |= DWC3_DEVTEN_ULSTCNGEN; | |
1906 | ||
8698e2ac FB |
1907 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); |
1908 | } | |
1909 | ||
1910 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
1911 | { | |
1912 | /* mask all interrupts */ | |
1913 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
1914 | } | |
1915 | ||
1916 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 1917 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 1918 | |
4e99472b | 1919 | /** |
bfad65ee FB |
1920 | * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG |
1921 | * @dwc: pointer to our context structure | |
4e99472b FB |
1922 | * |
1923 | * The following looks like complex but it's actually very simple. In order to | |
1924 | * calculate the number of packets we can burst at once on OUT transfers, we're | |
1925 | * gonna use RxFIFO size. | |
1926 | * | |
1927 | * To calculate RxFIFO size we need two numbers: | |
1928 | * MDWIDTH = size, in bits, of the internal memory bus | |
1929 | * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits) | |
1930 | * | |
1931 | * Given these two numbers, the formula is simple: | |
1932 | * | |
1933 | * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16; | |
1934 | * | |
1935 | * 24 bytes is for 3x SETUP packets | |
1936 | * 16 bytes is a clock domain crossing tolerance | |
1937 | * | |
1938 | * Given RxFIFO Size, NUMP = RxFIFOSize / 1024; | |
1939 | */ | |
1940 | static void dwc3_gadget_setup_nump(struct dwc3 *dwc) | |
1941 | { | |
1942 | u32 ram2_depth; | |
1943 | u32 mdwidth; | |
1944 | u32 nump; | |
1945 | u32 reg; | |
1946 | ||
1947 | ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7); | |
1948 | mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0); | |
1949 | ||
1950 | nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024; | |
1951 | nump = min_t(u32, nump, 16); | |
1952 | ||
1953 | /* update NumP */ | |
1954 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
1955 | reg &= ~DWC3_DCFG_NUMP_MASK; | |
1956 | reg |= nump << DWC3_DCFG_NUMP_SHIFT; | |
1957 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
1958 | } | |
1959 | ||
d7be2952 | 1960 | static int __dwc3_gadget_start(struct dwc3 *dwc) |
72246da4 | 1961 | { |
72246da4 | 1962 | struct dwc3_ep *dep; |
72246da4 FB |
1963 | int ret = 0; |
1964 | u32 reg; | |
1965 | ||
cf40b86b JY |
1966 | /* |
1967 | * Use IMOD if enabled via dwc->imod_interval. Otherwise, if | |
1968 | * the core supports IMOD, disable it. | |
1969 | */ | |
1970 | if (dwc->imod_interval) { | |
1971 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); | |
1972 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); | |
1973 | } else if (dwc3_has_imod(dwc)) { | |
1974 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0); | |
1975 | } | |
1976 | ||
2a58f9c1 FB |
1977 | /* |
1978 | * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP | |
1979 | * field instead of letting dwc3 itself calculate that automatically. | |
1980 | * | |
1981 | * This way, we maximize the chances that we'll be able to get several | |
1982 | * bursts of data without going through any sort of endpoint throttling. | |
1983 | */ | |
1984 | reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); | |
01b0e2cc TN |
1985 | if (dwc3_is_usb31(dwc)) |
1986 | reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL; | |
1987 | else | |
1988 | reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL; | |
1989 | ||
2a58f9c1 FB |
1990 | dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); |
1991 | ||
4e99472b FB |
1992 | dwc3_gadget_setup_nump(dwc); |
1993 | ||
72246da4 FB |
1994 | /* Start with SuperSpeed Default */ |
1995 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1996 | ||
1997 | dep = dwc->eps[0]; | |
a2d23f08 | 1998 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
1999 | if (ret) { |
2000 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 2001 | goto err0; |
72246da4 FB |
2002 | } |
2003 | ||
2004 | dep = dwc->eps[1]; | |
a2d23f08 | 2005 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
2006 | if (ret) { |
2007 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 2008 | goto err1; |
72246da4 FB |
2009 | } |
2010 | ||
2011 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 2012 | dwc->ep0state = EP0_SETUP_PHASE; |
88b1bb1f | 2013 | dwc->link_state = DWC3_LINK_STATE_SS_DIS; |
72246da4 FB |
2014 | dwc3_ep0_out_start(dwc); |
2015 | ||
8698e2ac FB |
2016 | dwc3_gadget_enable_irq(dwc); |
2017 | ||
72246da4 FB |
2018 | return 0; |
2019 | ||
b0d7ffd4 | 2020 | err1: |
d7be2952 | 2021 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
b0d7ffd4 FB |
2022 | |
2023 | err0: | |
72246da4 FB |
2024 | return ret; |
2025 | } | |
2026 | ||
d7be2952 FB |
2027 | static int dwc3_gadget_start(struct usb_gadget *g, |
2028 | struct usb_gadget_driver *driver) | |
72246da4 FB |
2029 | { |
2030 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2031 | unsigned long flags; | |
d7be2952 | 2032 | int ret = 0; |
8698e2ac | 2033 | int irq; |
72246da4 | 2034 | |
9522def4 | 2035 | irq = dwc->irq_gadget; |
d7be2952 FB |
2036 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, |
2037 | IRQF_SHARED, "dwc3", dwc->ev_buf); | |
2038 | if (ret) { | |
2039 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
2040 | irq, ret); | |
2041 | goto err0; | |
2042 | } | |
2043 | ||
72246da4 | 2044 | spin_lock_irqsave(&dwc->lock, flags); |
d7be2952 FB |
2045 | if (dwc->gadget_driver) { |
2046 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
2047 | dwc->gadget.name, | |
2048 | dwc->gadget_driver->driver.name); | |
2049 | ret = -EBUSY; | |
2050 | goto err1; | |
2051 | } | |
2052 | ||
2053 | dwc->gadget_driver = driver; | |
2054 | ||
fc8bb91b FB |
2055 | if (pm_runtime_active(dwc->dev)) |
2056 | __dwc3_gadget_start(dwc); | |
2057 | ||
d7be2952 FB |
2058 | spin_unlock_irqrestore(&dwc->lock, flags); |
2059 | ||
2060 | return 0; | |
2061 | ||
2062 | err1: | |
2063 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2064 | free_irq(irq, dwc); | |
2065 | ||
2066 | err0: | |
2067 | return ret; | |
2068 | } | |
72246da4 | 2069 | |
d7be2952 FB |
2070 | static void __dwc3_gadget_stop(struct dwc3 *dwc) |
2071 | { | |
8698e2ac | 2072 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
2073 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
2074 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
d7be2952 | 2075 | } |
72246da4 | 2076 | |
d7be2952 FB |
2077 | static int dwc3_gadget_stop(struct usb_gadget *g) |
2078 | { | |
2079 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2080 | unsigned long flags; | |
72246da4 | 2081 | |
d7be2952 | 2082 | spin_lock_irqsave(&dwc->lock, flags); |
76a638f8 BW |
2083 | |
2084 | if (pm_runtime_suspended(dwc->dev)) | |
2085 | goto out; | |
2086 | ||
d7be2952 | 2087 | __dwc3_gadget_stop(dwc); |
76a638f8 | 2088 | |
76a638f8 | 2089 | out: |
d7be2952 | 2090 | dwc->gadget_driver = NULL; |
72246da4 FB |
2091 | spin_unlock_irqrestore(&dwc->lock, flags); |
2092 | ||
3f308d17 | 2093 | free_irq(dwc->irq_gadget, dwc->ev_buf); |
b0d7ffd4 | 2094 | |
72246da4 FB |
2095 | return 0; |
2096 | } | |
802fde98 | 2097 | |
729dcffd AKV |
2098 | static void dwc3_gadget_config_params(struct usb_gadget *g, |
2099 | struct usb_dcd_config_params *params) | |
2100 | { | |
2101 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2102 | ||
54fb5ba6 TN |
2103 | params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED; |
2104 | params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED; | |
2105 | ||
2106 | /* Recommended BESL */ | |
2107 | if (!dwc->dis_enblslpm_quirk) { | |
17b63704 TN |
2108 | /* |
2109 | * If the recommended BESL baseline is 0 or if the BESL deep is | |
2110 | * less than 2, Microsoft's Windows 10 host usb stack will issue | |
2111 | * a usb reset immediately after it receives the extended BOS | |
2112 | * descriptor and the enumeration will fail. To maintain | |
2113 | * compatibility with the Windows' usb stack, let's set the | |
2114 | * recommended BESL baseline to 1 and clamp the BESL deep to be | |
2115 | * within 2 to 15. | |
2116 | */ | |
2117 | params->besl_baseline = 1; | |
54fb5ba6 | 2118 | if (dwc->is_utmi_l1_suspend) |
17b63704 TN |
2119 | params->besl_deep = |
2120 | clamp_t(u8, dwc->hird_threshold, 2, 15); | |
54fb5ba6 TN |
2121 | } |
2122 | ||
729dcffd AKV |
2123 | /* U1 Device exit Latency */ |
2124 | if (dwc->dis_u1_entry_quirk) | |
2125 | params->bU1devExitLat = 0; | |
2126 | else | |
2127 | params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT; | |
2128 | ||
2129 | /* U2 Device exit Latency */ | |
2130 | if (dwc->dis_u2_entry_quirk) | |
2131 | params->bU2DevExitLat = 0; | |
2132 | else | |
2133 | params->bU2DevExitLat = | |
2134 | cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT); | |
2135 | } | |
2136 | ||
7d8d0639 FB |
2137 | static void dwc3_gadget_set_speed(struct usb_gadget *g, |
2138 | enum usb_device_speed speed) | |
2139 | { | |
2140 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2141 | unsigned long flags; | |
2142 | u32 reg; | |
2143 | ||
2144 | spin_lock_irqsave(&dwc->lock, flags); | |
2145 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2146 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
2147 | ||
2148 | /* | |
2149 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
2150 | * which would cause metastability state on Run/Stop | |
2151 | * bit if we try to force the IP to USB2-only mode. | |
2152 | * | |
2153 | * Because of that, we cannot configure the IP to any | |
2154 | * speed other than the SuperSpeed | |
2155 | * | |
2156 | * Refers to: | |
2157 | * | |
2158 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
2159 | * USB 2.0 Mode | |
2160 | */ | |
42bf02ec RQ |
2161 | if (dwc->revision < DWC3_REVISION_220A && |
2162 | !dwc->dis_metastability_quirk) { | |
7d8d0639 FB |
2163 | reg |= DWC3_DCFG_SUPERSPEED; |
2164 | } else { | |
2165 | switch (speed) { | |
2166 | case USB_SPEED_LOW: | |
2167 | reg |= DWC3_DCFG_LOWSPEED; | |
2168 | break; | |
2169 | case USB_SPEED_FULL: | |
2170 | reg |= DWC3_DCFG_FULLSPEED; | |
2171 | break; | |
2172 | case USB_SPEED_HIGH: | |
2173 | reg |= DWC3_DCFG_HIGHSPEED; | |
2174 | break; | |
2175 | case USB_SPEED_SUPER: | |
2176 | reg |= DWC3_DCFG_SUPERSPEED; | |
2177 | break; | |
2178 | case USB_SPEED_SUPER_PLUS: | |
2f3090c6 TN |
2179 | if (dwc3_is_usb31(dwc)) |
2180 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; | |
2181 | else | |
2182 | reg |= DWC3_DCFG_SUPERSPEED; | |
7d8d0639 FB |
2183 | break; |
2184 | default: | |
2185 | dev_err(dwc->dev, "invalid speed (%d)\n", speed); | |
2186 | ||
2187 | if (dwc->revision & DWC3_REVISION_IS_DWC31) | |
2188 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; | |
2189 | else | |
2190 | reg |= DWC3_DCFG_SUPERSPEED; | |
2191 | } | |
2192 | } | |
2193 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2194 | ||
2195 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2196 | } | |
2197 | ||
72246da4 FB |
2198 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
2199 | .get_frame = dwc3_gadget_get_frame, | |
2200 | .wakeup = dwc3_gadget_wakeup, | |
2201 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
2202 | .pullup = dwc3_gadget_pullup, | |
2203 | .udc_start = dwc3_gadget_start, | |
2204 | .udc_stop = dwc3_gadget_stop, | |
7d8d0639 | 2205 | .udc_set_speed = dwc3_gadget_set_speed, |
729dcffd | 2206 | .get_config_params = dwc3_gadget_config_params, |
72246da4 FB |
2207 | }; |
2208 | ||
2209 | /* -------------------------------------------------------------------------- */ | |
2210 | ||
8f1c99cd | 2211 | static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep) |
72246da4 | 2212 | { |
8f1c99cd | 2213 | struct dwc3 *dwc = dep->dwc; |
72246da4 | 2214 | |
8f1c99cd FB |
2215 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
2216 | dep->endpoint.maxburst = 1; | |
2217 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; | |
2218 | if (!dep->direction) | |
2219 | dwc->gadget.ep0 = &dep->endpoint; | |
f3bcfc7e | 2220 | |
8f1c99cd | 2221 | dep->endpoint.caps.type_control = true; |
72246da4 | 2222 | |
8f1c99cd FB |
2223 | return 0; |
2224 | } | |
72246da4 | 2225 | |
8f1c99cd FB |
2226 | static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep) |
2227 | { | |
2228 | struct dwc3 *dwc = dep->dwc; | |
2229 | int mdwidth; | |
2230 | int kbytes; | |
2231 | int size; | |
72246da4 | 2232 | |
8f1c99cd FB |
2233 | mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); |
2234 | /* MDWIDTH is represented in bits, we need it in bytes */ | |
2235 | mdwidth /= 8; | |
6a1e3ef4 | 2236 | |
8f1c99cd FB |
2237 | size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1)); |
2238 | if (dwc3_is_usb31(dwc)) | |
2239 | size = DWC31_GTXFIFOSIZ_TXFDEF(size); | |
2240 | else | |
2241 | size = DWC3_GTXFIFOSIZ_TXFDEF(size); | |
39ebb05c | 2242 | |
8f1c99cd FB |
2243 | /* FIFO Depth is in MDWDITH bytes. Multiply */ |
2244 | size *= mdwidth; | |
39ebb05c | 2245 | |
8f1c99cd FB |
2246 | kbytes = size / 1024; |
2247 | if (kbytes == 0) | |
2248 | kbytes = 1; | |
28781789 | 2249 | |
8f1c99cd FB |
2250 | /* |
2251 | * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for | |
2252 | * internal overhead. We don't really know how these are used, | |
2253 | * but documentation say it exists. | |
2254 | */ | |
2255 | size -= mdwidth * (kbytes + 1); | |
2256 | size /= kbytes; | |
28781789 | 2257 | |
8f1c99cd | 2258 | usb_ep_set_maxpacket_limit(&dep->endpoint, size); |
28781789 | 2259 | |
8f1c99cd FB |
2260 | dep->endpoint.max_streams = 15; |
2261 | dep->endpoint.ops = &dwc3_gadget_ep_ops; | |
2262 | list_add_tail(&dep->endpoint.ep_list, | |
2263 | &dwc->gadget.ep_list); | |
2264 | dep->endpoint.caps.type_iso = true; | |
2265 | dep->endpoint.caps.type_bulk = true; | |
2266 | dep->endpoint.caps.type_int = true; | |
28781789 | 2267 | |
8f1c99cd FB |
2268 | return dwc3_alloc_trb_pool(dep); |
2269 | } | |
28781789 | 2270 | |
8f1c99cd FB |
2271 | static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep) |
2272 | { | |
2273 | struct dwc3 *dwc = dep->dwc; | |
28781789 | 2274 | |
8f1c99cd FB |
2275 | usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); |
2276 | dep->endpoint.max_streams = 15; | |
2277 | dep->endpoint.ops = &dwc3_gadget_ep_ops; | |
2278 | list_add_tail(&dep->endpoint.ep_list, | |
2279 | &dwc->gadget.ep_list); | |
2280 | dep->endpoint.caps.type_iso = true; | |
2281 | dep->endpoint.caps.type_bulk = true; | |
2282 | dep->endpoint.caps.type_int = true; | |
72246da4 | 2283 | |
8f1c99cd FB |
2284 | return dwc3_alloc_trb_pool(dep); |
2285 | } | |
72246da4 | 2286 | |
8f1c99cd FB |
2287 | static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum) |
2288 | { | |
2289 | struct dwc3_ep *dep; | |
2290 | bool direction = epnum & 1; | |
2291 | int ret; | |
2292 | u8 num = epnum >> 1; | |
25b8ff68 | 2293 | |
8f1c99cd FB |
2294 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
2295 | if (!dep) | |
2296 | return -ENOMEM; | |
2297 | ||
2298 | dep->dwc = dwc; | |
2299 | dep->number = epnum; | |
2300 | dep->direction = direction; | |
2301 | dep->regs = dwc->regs + DWC3_DEP_BASE(epnum); | |
2302 | dwc->eps[epnum] = dep; | |
d92021f6 TN |
2303 | dep->combo_num = 0; |
2304 | dep->start_cmd_status = 0; | |
8f1c99cd FB |
2305 | |
2306 | snprintf(dep->name, sizeof(dep->name), "ep%u%s", num, | |
2307 | direction ? "in" : "out"); | |
2308 | ||
2309 | dep->endpoint.name = dep->name; | |
2310 | ||
2311 | if (!(dep->number > 1)) { | |
2312 | dep->endpoint.desc = &dwc3_gadget_ep0_desc; | |
2313 | dep->endpoint.comp_desc = NULL; | |
2314 | } | |
2315 | ||
8f1c99cd FB |
2316 | if (num == 0) |
2317 | ret = dwc3_gadget_init_control_endpoint(dep); | |
2318 | else if (direction) | |
2319 | ret = dwc3_gadget_init_in_endpoint(dep); | |
2320 | else | |
2321 | ret = dwc3_gadget_init_out_endpoint(dep); | |
2322 | ||
2323 | if (ret) | |
2324 | return ret; | |
a474d3b7 | 2325 | |
8f1c99cd FB |
2326 | dep->endpoint.caps.dir_in = direction; |
2327 | dep->endpoint.caps.dir_out = !direction; | |
a474d3b7 | 2328 | |
8f1c99cd FB |
2329 | INIT_LIST_HEAD(&dep->pending_list); |
2330 | INIT_LIST_HEAD(&dep->started_list); | |
d5443bbf | 2331 | INIT_LIST_HEAD(&dep->cancelled_list); |
8f1c99cd FB |
2332 | |
2333 | return 0; | |
2334 | } | |
2335 | ||
2336 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total) | |
2337 | { | |
2338 | u8 epnum; | |
2339 | ||
2340 | INIT_LIST_HEAD(&dwc->gadget.ep_list); | |
2341 | ||
2342 | for (epnum = 0; epnum < total; epnum++) { | |
2343 | int ret; | |
2344 | ||
2345 | ret = dwc3_gadget_init_endpoint(dwc, epnum); | |
2346 | if (ret) | |
2347 | return ret; | |
72246da4 FB |
2348 | } |
2349 | ||
2350 | return 0; | |
2351 | } | |
2352 | ||
2353 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) | |
2354 | { | |
2355 | struct dwc3_ep *dep; | |
2356 | u8 epnum; | |
2357 | ||
2358 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2359 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2360 | if (!dep) |
2361 | continue; | |
5bf8fae3 GC |
2362 | /* |
2363 | * Physical endpoints 0 and 1 are special; they form the | |
2364 | * bi-directional USB endpoint 0. | |
2365 | * | |
2366 | * For those two physical endpoints, we don't allocate a TRB | |
2367 | * pool nor do we add them the endpoints list. Due to that, we | |
2368 | * shouldn't do these two operations otherwise we would end up | |
2369 | * with all sorts of bugs when removing dwc3.ko. | |
2370 | */ | |
2371 | if (epnum != 0 && epnum != 1) { | |
2372 | dwc3_free_trb_pool(dep); | |
72246da4 | 2373 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 2374 | } |
72246da4 FB |
2375 | |
2376 | kfree(dep); | |
2377 | } | |
2378 | } | |
2379 | ||
72246da4 | 2380 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 2381 | |
8f608e8a FB |
2382 | static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep, |
2383 | struct dwc3_request *req, struct dwc3_trb *trb, | |
2384 | const struct dwc3_event_depevt *event, int status, int chain) | |
72246da4 | 2385 | { |
72246da4 | 2386 | unsigned int count; |
72246da4 | 2387 | |
dc55c67e | 2388 | dwc3_ep_inc_deq(dep); |
a9c3ca5f | 2389 | |
2c4cbe6e | 2390 | trace_dwc3_complete_trb(dep, trb); |
09fe1f8d | 2391 | req->num_trbs--; |
2c4cbe6e | 2392 | |
e5b36ae2 FB |
2393 | /* |
2394 | * If we're in the middle of series of chained TRBs and we | |
2395 | * receive a short transfer along the way, DWC3 will skip | |
2396 | * through all TRBs including the last TRB in the chain (the | |
2397 | * where CHN bit is zero. DWC3 will also avoid clearing HWO | |
2398 | * bit and SW has to do it manually. | |
2399 | * | |
2400 | * We're going to do that here to avoid problems of HW trying | |
2401 | * to use bogus TRBs for transfers. | |
2402 | */ | |
2403 | if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO)) | |
2404 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; | |
2405 | ||
6abfa0f5 TN |
2406 | /* |
2407 | * For isochronous transfers, the first TRB in a service interval must | |
2408 | * have the Isoc-First type. Track and report its interval frame number. | |
2409 | */ | |
2410 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
2411 | (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) { | |
2412 | unsigned int frame_number; | |
2413 | ||
2414 | frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl); | |
2415 | frame_number &= ~(dep->interval - 1); | |
2416 | req->request.frame_number = frame_number; | |
2417 | } | |
2418 | ||
c6267a51 FB |
2419 | /* |
2420 | * If we're dealing with unaligned size OUT transfer, we will be left | |
2421 | * with one TRB pending in the ring. We need to manually clear HWO bit | |
2422 | * from that TRB. | |
2423 | */ | |
1a22ec64 FB |
2424 | |
2425 | if (req->needs_extra_trb && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) { | |
c6267a51 FB |
2426 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; |
2427 | return 1; | |
2428 | } | |
2429 | ||
e5ba5ec8 | 2430 | count = trb->size & DWC3_TRB_SIZE_MASK; |
e62c5bc5 | 2431 | req->remaining += count; |
e5ba5ec8 | 2432 | |
35b2719e FB |
2433 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
2434 | return 1; | |
2435 | ||
d80fe1b6 | 2436 | if (event->status & DEPEVT_STATUS_SHORT && !chain) |
e5ba5ec8 | 2437 | return 1; |
f99f53f2 | 2438 | |
5ee85897 AKV |
2439 | if ((trb->ctrl & DWC3_TRB_CTRL_IOC) || |
2440 | (trb->ctrl & DWC3_TRB_CTRL_LST)) | |
e5ba5ec8 | 2441 | return 1; |
f99f53f2 | 2442 | |
e5ba5ec8 PA |
2443 | return 0; |
2444 | } | |
2445 | ||
d3692953 FB |
2446 | static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep, |
2447 | struct dwc3_request *req, const struct dwc3_event_depevt *event, | |
2448 | int status) | |
2449 | { | |
2450 | struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue]; | |
2451 | struct scatterlist *sg = req->sg; | |
2452 | struct scatterlist *s; | |
2453 | unsigned int pending = req->num_pending_sgs; | |
2454 | unsigned int i; | |
2455 | int ret = 0; | |
2456 | ||
2457 | for_each_sg(sg, s, pending, i) { | |
2458 | trb = &dep->trb_pool[dep->trb_dequeue]; | |
2459 | ||
2460 | if (trb->ctrl & DWC3_TRB_CTRL_HWO) | |
2461 | break; | |
2462 | ||
2463 | req->sg = sg_next(s); | |
2464 | req->num_pending_sgs--; | |
2465 | ||
2466 | ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req, | |
2467 | trb, event, status, true); | |
2468 | if (ret) | |
2469 | break; | |
2470 | } | |
2471 | ||
2472 | return ret; | |
2473 | } | |
2474 | ||
2475 | static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep, | |
2476 | struct dwc3_request *req, const struct dwc3_event_depevt *event, | |
2477 | int status) | |
2478 | { | |
2479 | struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue]; | |
2480 | ||
2481 | return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb, | |
2482 | event, status, false); | |
2483 | } | |
2484 | ||
e0c42ce5 FB |
2485 | static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req) |
2486 | { | |
ea0d7627 TN |
2487 | /* |
2488 | * For OUT direction, host may send less than the setup | |
2489 | * length. Return true for all OUT requests. | |
2490 | */ | |
2491 | if (!req->direction) | |
2492 | return true; | |
2493 | ||
e0c42ce5 FB |
2494 | return req->request.actual == req->request.length; |
2495 | } | |
2496 | ||
f38e35dd FB |
2497 | static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep, |
2498 | const struct dwc3_event_depevt *event, | |
2499 | struct dwc3_request *req, int status) | |
2500 | { | |
2501 | int ret; | |
2502 | ||
2503 | if (req->num_pending_sgs) | |
2504 | ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event, | |
2505 | status); | |
2506 | else | |
2507 | ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event, | |
2508 | status); | |
2509 | ||
1a22ec64 | 2510 | if (req->needs_extra_trb) { |
f38e35dd FB |
2511 | ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event, |
2512 | status); | |
1a22ec64 | 2513 | req->needs_extra_trb = false; |
f38e35dd FB |
2514 | } |
2515 | ||
2516 | req->request.actual = req->request.length - req->remaining; | |
2517 | ||
8c7d4b7b | 2518 | if (!dwc3_gadget_ep_request_completed(req) || |
f38e35dd FB |
2519 | req->num_pending_sgs) { |
2520 | __dwc3_gadget_kick_transfer(dep); | |
2521 | goto out; | |
2522 | } | |
2523 | ||
2524 | dwc3_gadget_giveback(dep, req, status); | |
2525 | ||
2526 | out: | |
2527 | return ret; | |
2528 | } | |
2529 | ||
12a3a4ad | 2530 | static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep, |
8f608e8a | 2531 | const struct dwc3_event_depevt *event, int status) |
e5ba5ec8 | 2532 | { |
6afbdb57 FB |
2533 | struct dwc3_request *req; |
2534 | struct dwc3_request *tmp; | |
e5ba5ec8 | 2535 | |
6afbdb57 | 2536 | list_for_each_entry_safe(req, tmp, &dep->started_list, list) { |
fee73e61 | 2537 | int ret; |
e5b36ae2 | 2538 | |
f38e35dd FB |
2539 | ret = dwc3_gadget_ep_cleanup_completed_request(dep, event, |
2540 | req, status); | |
58f0218a | 2541 | if (ret) |
72246da4 | 2542 | break; |
31162af4 | 2543 | } |
72246da4 FB |
2544 | } |
2545 | ||
ee3638b8 FB |
2546 | static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep, |
2547 | const struct dwc3_event_depevt *event) | |
2548 | { | |
f62afb49 | 2549 | dep->frame_number = event->parameters; |
ee3638b8 FB |
2550 | } |
2551 | ||
8f608e8a FB |
2552 | static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep, |
2553 | const struct dwc3_event_depevt *event) | |
72246da4 | 2554 | { |
8f608e8a | 2555 | struct dwc3 *dwc = dep->dwc; |
72246da4 | 2556 | unsigned status = 0; |
6d8a0196 | 2557 | bool stop = false; |
72246da4 | 2558 | |
ee3638b8 FB |
2559 | dwc3_gadget_endpoint_frame_from_event(dep, event); |
2560 | ||
72246da4 FB |
2561 | if (event->status & DEPEVT_STATUS_BUSERR) |
2562 | status = -ECONNRESET; | |
2563 | ||
6d8a0196 FB |
2564 | if (event->status & DEPEVT_STATUS_MISSED_ISOC) { |
2565 | status = -EXDEV; | |
d513320f FB |
2566 | |
2567 | if (list_empty(&dep->started_list)) | |
2568 | stop = true; | |
6d8a0196 FB |
2569 | } |
2570 | ||
5f2e7975 | 2571 | dwc3_gadget_ep_cleanup_completed_requests(dep, event, status); |
fae2b904 | 2572 | |
a114c4ca | 2573 | if (stop) |
c5353b22 | 2574 | dwc3_stop_active_transfer(dep, true, true); |
6d8a0196 | 2575 | |
fae2b904 FB |
2576 | /* |
2577 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
2578 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
2579 | */ | |
2580 | if (dwc->revision < DWC3_REVISION_183A) { | |
2581 | u32 reg; | |
2582 | int i; | |
2583 | ||
2584 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 2585 | dep = dwc->eps[i]; |
fae2b904 FB |
2586 | |
2587 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
2588 | continue; | |
2589 | ||
aa3342c8 | 2590 | if (!list_empty(&dep->started_list)) |
fae2b904 FB |
2591 | return; |
2592 | } | |
2593 | ||
2594 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2595 | reg |= dwc->u1u2; | |
2596 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2597 | ||
2598 | dwc->u1u2 = 0; | |
2599 | } | |
72246da4 FB |
2600 | } |
2601 | ||
8f608e8a FB |
2602 | static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep, |
2603 | const struct dwc3_event_depevt *event) | |
32033865 | 2604 | { |
ee3638b8 | 2605 | dwc3_gadget_endpoint_frame_from_event(dep, event); |
25abad6a | 2606 | (void) __dwc3_gadget_start_isoc(dep); |
32033865 FB |
2607 | } |
2608 | ||
72246da4 FB |
2609 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
2610 | const struct dwc3_event_depevt *event) | |
2611 | { | |
2612 | struct dwc3_ep *dep; | |
2613 | u8 epnum = event->endpoint_number; | |
76a638f8 | 2614 | u8 cmd; |
72246da4 FB |
2615 | |
2616 | dep = dwc->eps[epnum]; | |
2617 | ||
d7fd41c6 | 2618 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
3aec9915 | 2619 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) |
d7fd41c6 JD |
2620 | return; |
2621 | ||
2622 | /* Handle only EPCMDCMPLT when EP disabled */ | |
2623 | if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT) | |
2624 | return; | |
2625 | } | |
3336abb5 | 2626 | |
72246da4 FB |
2627 | if (epnum == 0 || epnum == 1) { |
2628 | dwc3_ep0_interrupt(dwc, event); | |
2629 | return; | |
2630 | } | |
2631 | ||
2632 | switch (event->endpoint_event) { | |
72246da4 | 2633 | case DWC3_DEPEVT_XFERINPROGRESS: |
8f608e8a | 2634 | dwc3_gadget_endpoint_transfer_in_progress(dep, event); |
72246da4 FB |
2635 | break; |
2636 | case DWC3_DEPEVT_XFERNOTREADY: | |
8f608e8a | 2637 | dwc3_gadget_endpoint_transfer_not_ready(dep, event); |
879631aa | 2638 | break; |
72246da4 | 2639 | case DWC3_DEPEVT_EPCMDCMPLT: |
76a638f8 BW |
2640 | cmd = DEPEVT_PARAMETER_CMD(event->parameters); |
2641 | ||
2642 | if (cmd == DWC3_DEPCMD_ENDTRANSFER) { | |
c58d8bfc | 2643 | dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; |
3aec9915 | 2644 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; |
fec9095b | 2645 | dwc3_gadget_ep_cleanup_cancelled_requests(dep); |
da10bcdd TN |
2646 | if ((dep->flags & DWC3_EP_DELAY_START) && |
2647 | !usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
2648 | __dwc3_gadget_kick_transfer(dep); | |
2649 | ||
2650 | dep->flags &= ~DWC3_EP_DELAY_START; | |
76a638f8 BW |
2651 | } |
2652 | break; | |
a24a6ab1 | 2653 | case DWC3_DEPEVT_STREAMEVT: |
742a4fff | 2654 | case DWC3_DEPEVT_XFERCOMPLETE: |
76a638f8 | 2655 | case DWC3_DEPEVT_RXTXFIFOEVT: |
72246da4 FB |
2656 | break; |
2657 | } | |
2658 | } | |
2659 | ||
2660 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
2661 | { | |
2662 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
2663 | spin_unlock(&dwc->lock); | |
2664 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
2665 | spin_lock(&dwc->lock); | |
2666 | } | |
2667 | } | |
2668 | ||
bc5ba2e0 FB |
2669 | static void dwc3_suspend_gadget(struct dwc3 *dwc) |
2670 | { | |
73a30bfc | 2671 | if (dwc->gadget_driver && dwc->gadget_driver->suspend) { |
bc5ba2e0 FB |
2672 | spin_unlock(&dwc->lock); |
2673 | dwc->gadget_driver->suspend(&dwc->gadget); | |
2674 | spin_lock(&dwc->lock); | |
2675 | } | |
2676 | } | |
2677 | ||
2678 | static void dwc3_resume_gadget(struct dwc3 *dwc) | |
2679 | { | |
73a30bfc | 2680 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
bc5ba2e0 FB |
2681 | spin_unlock(&dwc->lock); |
2682 | dwc->gadget_driver->resume(&dwc->gadget); | |
5c7b3b02 | 2683 | spin_lock(&dwc->lock); |
8e74475b FB |
2684 | } |
2685 | } | |
2686 | ||
2687 | static void dwc3_reset_gadget(struct dwc3 *dwc) | |
2688 | { | |
2689 | if (!dwc->gadget_driver) | |
2690 | return; | |
2691 | ||
2692 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) { | |
2693 | spin_unlock(&dwc->lock); | |
2694 | usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver); | |
bc5ba2e0 FB |
2695 | spin_lock(&dwc->lock); |
2696 | } | |
2697 | } | |
2698 | ||
c5353b22 FB |
2699 | static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, |
2700 | bool interrupt) | |
72246da4 | 2701 | { |
72246da4 FB |
2702 | struct dwc3_gadget_ep_cmd_params params; |
2703 | u32 cmd; | |
2704 | int ret; | |
2705 | ||
c58d8bfc TN |
2706 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) || |
2707 | (dep->flags & DWC3_EP_END_TRANSFER_PENDING)) | |
3daf74d7 PA |
2708 | return; |
2709 | ||
57911504 PA |
2710 | /* |
2711 | * NOTICE: We are violating what the Databook says about the | |
2712 | * EndTransfer command. Ideally we would _always_ wait for the | |
2713 | * EndTransfer Command Completion IRQ, but that's causing too | |
2714 | * much trouble synchronizing between us and gadget driver. | |
2715 | * | |
2716 | * We have discussed this with the IP Provider and it was | |
cf2f8b63 | 2717 | * suggested to giveback all requests here. |
57911504 PA |
2718 | * |
2719 | * Note also that a similar handling was tested by Synopsys | |
2720 | * (thanks a lot Paul) and nothing bad has come out of it. | |
cf2f8b63 TN |
2721 | * In short, what we're doing is issuing EndTransfer with |
2722 | * CMDIOC bit set and delay kicking transfer until the | |
2723 | * EndTransfer command had completed. | |
06281d46 JY |
2724 | * |
2725 | * As of IP version 3.10a of the DWC_usb3 IP, the controller | |
2726 | * supports a mode to work around the above limitation. The | |
2727 | * software can poll the CMDACT bit in the DEPCMD register | |
2728 | * after issuing a EndTransfer command. This mode is enabled | |
2729 | * by writing GUCTL2[14]. This polling is already done in the | |
2730 | * dwc3_send_gadget_ep_cmd() function so if the mode is | |
2731 | * enabled, the EndTransfer command will have completed upon | |
cf2f8b63 | 2732 | * returning from this function. |
06281d46 JY |
2733 | * |
2734 | * This mode is NOT available on the DWC_usb31 IP. | |
57911504 PA |
2735 | */ |
2736 | ||
3daf74d7 | 2737 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
b992e681 | 2738 | cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; |
c5353b22 | 2739 | cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0; |
b4996a86 | 2740 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 | 2741 | memset(¶ms, 0, sizeof(params)); |
2cd4718d | 2742 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
3daf74d7 | 2743 | WARN_ON_ONCE(ret); |
b4996a86 | 2744 | dep->resource_index = 0; |
06281d46 | 2745 | |
d3abda5a TN |
2746 | if (!interrupt) |
2747 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; | |
c58d8bfc TN |
2748 | else |
2749 | dep->flags |= DWC3_EP_END_TRANSFER_PENDING; | |
72246da4 FB |
2750 | } |
2751 | ||
72246da4 FB |
2752 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) |
2753 | { | |
2754 | u32 epnum; | |
2755 | ||
2756 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2757 | struct dwc3_ep *dep; | |
72246da4 FB |
2758 | int ret; |
2759 | ||
2760 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2761 | if (!dep) |
2762 | continue; | |
72246da4 FB |
2763 | |
2764 | if (!(dep->flags & DWC3_EP_STALL)) | |
2765 | continue; | |
2766 | ||
2767 | dep->flags &= ~DWC3_EP_STALL; | |
2768 | ||
50c763f8 | 2769 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 FB |
2770 | WARN_ON_ONCE(ret); |
2771 | } | |
2772 | } | |
2773 | ||
2774 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
2775 | { | |
c4430a26 FB |
2776 | int reg; |
2777 | ||
1b6009ea TN |
2778 | dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET); |
2779 | ||
72246da4 FB |
2780 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
2781 | reg &= ~DWC3_DCTL_INITU1ENA; | |
72246da4 | 2782 | reg &= ~DWC3_DCTL_INITU2ENA; |
5b738211 | 2783 | dwc3_gadget_dctl_write_safe(dwc, reg); |
72246da4 | 2784 | |
72246da4 FB |
2785 | dwc3_disconnect_gadget(dwc); |
2786 | ||
2787 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
df62df56 | 2788 | dwc->setup_packet_pending = false; |
06a374ed | 2789 | usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED); |
fc8bb91b FB |
2790 | |
2791 | dwc->connected = false; | |
72246da4 FB |
2792 | } |
2793 | ||
72246da4 FB |
2794 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
2795 | { | |
2796 | u32 reg; | |
2797 | ||
fc8bb91b FB |
2798 | dwc->connected = true; |
2799 | ||
df62df56 FB |
2800 | /* |
2801 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
2802 | * would cause a missing Disconnect Event if there's a | |
2803 | * pending Setup Packet in the FIFO. | |
2804 | * | |
2805 | * There's no suggested workaround on the official Bug | |
2806 | * report, which states that "unless the driver/application | |
2807 | * is doing any special handling of a disconnect event, | |
2808 | * there is no functional issue". | |
2809 | * | |
2810 | * Unfortunately, it turns out that we _do_ some special | |
2811 | * handling of a disconnect event, namely complete all | |
2812 | * pending transfers, notify gadget driver of the | |
2813 | * disconnection, and so on. | |
2814 | * | |
2815 | * Our suggested workaround is to follow the Disconnect | |
2816 | * Event steps here, instead, based on a setup_packet_pending | |
b5d335e5 FB |
2817 | * flag. Such flag gets set whenever we have a SETUP_PENDING |
2818 | * status for EP0 TRBs and gets cleared on XferComplete for the | |
df62df56 FB |
2819 | * same endpoint. |
2820 | * | |
2821 | * Refers to: | |
2822 | * | |
2823 | * STAR#9000466709: RTL: Device : Disconnect event not | |
2824 | * generated if setup packet pending in FIFO | |
2825 | */ | |
2826 | if (dwc->revision < DWC3_REVISION_188A) { | |
2827 | if (dwc->setup_packet_pending) | |
2828 | dwc3_gadget_disconnect_interrupt(dwc); | |
2829 | } | |
2830 | ||
8e74475b | 2831 | dwc3_reset_gadget(dwc); |
72246da4 FB |
2832 | |
2833 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2834 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
5b738211 | 2835 | dwc3_gadget_dctl_write_safe(dwc, reg); |
3b637367 | 2836 | dwc->test_mode = false; |
72246da4 FB |
2837 | dwc3_clear_stall_all_ep(dwc); |
2838 | ||
2839 | /* Reset device address to zero */ | |
2840 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2841 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
2842 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
2843 | } |
2844 | ||
72246da4 FB |
2845 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
2846 | { | |
72246da4 FB |
2847 | struct dwc3_ep *dep; |
2848 | int ret; | |
2849 | u32 reg; | |
2850 | u8 speed; | |
2851 | ||
72246da4 FB |
2852 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2853 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
2854 | dwc->speed = speed; | |
2855 | ||
5fb6fdaf JY |
2856 | /* |
2857 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
2858 | * each time on Connect Done. | |
2859 | * | |
2860 | * Currently we always use the reset value. If any platform | |
2861 | * wants to set this to a different value, we need to add a | |
2862 | * setting and update GCTL.RAMCLKSEL here. | |
2863 | */ | |
72246da4 FB |
2864 | |
2865 | switch (speed) { | |
2da9ad76 | 2866 | case DWC3_DSTS_SUPERSPEED_PLUS: |
7580862b JY |
2867 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2868 | dwc->gadget.ep0->maxpacket = 512; | |
2869 | dwc->gadget.speed = USB_SPEED_SUPER_PLUS; | |
2870 | break; | |
2da9ad76 | 2871 | case DWC3_DSTS_SUPERSPEED: |
05870c5b FB |
2872 | /* |
2873 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
2874 | * would cause a missing USB3 Reset event. | |
2875 | * | |
2876 | * In such situations, we should force a USB3 Reset | |
2877 | * event by calling our dwc3_gadget_reset_interrupt() | |
2878 | * routine. | |
2879 | * | |
2880 | * Refers to: | |
2881 | * | |
2882 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
2883 | * not be generated always when the link enters poll | |
2884 | */ | |
2885 | if (dwc->revision < DWC3_REVISION_190A) | |
2886 | dwc3_gadget_reset_interrupt(dwc); | |
2887 | ||
72246da4 FB |
2888 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2889 | dwc->gadget.ep0->maxpacket = 512; | |
2890 | dwc->gadget.speed = USB_SPEED_SUPER; | |
2891 | break; | |
2da9ad76 | 2892 | case DWC3_DSTS_HIGHSPEED: |
72246da4 FB |
2893 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
2894 | dwc->gadget.ep0->maxpacket = 64; | |
2895 | dwc->gadget.speed = USB_SPEED_HIGH; | |
2896 | break; | |
9418ee15 | 2897 | case DWC3_DSTS_FULLSPEED: |
72246da4 FB |
2898 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
2899 | dwc->gadget.ep0->maxpacket = 64; | |
2900 | dwc->gadget.speed = USB_SPEED_FULL; | |
2901 | break; | |
2da9ad76 | 2902 | case DWC3_DSTS_LOWSPEED: |
72246da4 FB |
2903 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); |
2904 | dwc->gadget.ep0->maxpacket = 8; | |
2905 | dwc->gadget.speed = USB_SPEED_LOW; | |
2906 | break; | |
2907 | } | |
2908 | ||
61800263 TN |
2909 | dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket; |
2910 | ||
2b758350 PA |
2911 | /* Enable USB2 LPM Capability */ |
2912 | ||
ee5cd41c | 2913 | if ((dwc->revision > DWC3_REVISION_194A) && |
2da9ad76 JY |
2914 | (speed != DWC3_DSTS_SUPERSPEED) && |
2915 | (speed != DWC3_DSTS_SUPERSPEED_PLUS)) { | |
2b758350 PA |
2916 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
2917 | reg |= DWC3_DCFG_LPM_CAP; | |
2918 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2919 | ||
2920 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2921 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
2922 | ||
16fe4f30 TN |
2923 | reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold | |
2924 | (dwc->is_utmi_l1_suspend << 4)); | |
2b758350 | 2925 | |
80caf7d2 HR |
2926 | /* |
2927 | * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and | |
2928 | * DCFG.LPMCap is set, core responses with an ACK and the | |
2929 | * BESL value in the LPM token is less than or equal to LPM | |
2930 | * NYET threshold. | |
2931 | */ | |
2932 | WARN_ONCE(dwc->revision < DWC3_REVISION_240A | |
2933 | && dwc->has_lpm_erratum, | |
9165dabb | 2934 | "LPM Erratum not available on dwc3 revisions < 2.40a\n"); |
80caf7d2 HR |
2935 | |
2936 | if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A) | |
2e487d28 | 2937 | reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold); |
80caf7d2 | 2938 | |
5b738211 | 2939 | dwc3_gadget_dctl_write_safe(dwc, reg); |
356363bf FB |
2940 | } else { |
2941 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2942 | reg &= ~DWC3_DCTL_HIRD_THRES_MASK; | |
5b738211 | 2943 | dwc3_gadget_dctl_write_safe(dwc, reg); |
2b758350 PA |
2944 | } |
2945 | ||
72246da4 | 2946 | dep = dwc->eps[0]; |
a2d23f08 | 2947 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY); |
72246da4 FB |
2948 | if (ret) { |
2949 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2950 | return; | |
2951 | } | |
2952 | ||
2953 | dep = dwc->eps[1]; | |
a2d23f08 | 2954 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY); |
72246da4 FB |
2955 | if (ret) { |
2956 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2957 | return; | |
2958 | } | |
2959 | ||
2960 | /* | |
2961 | * Configure PHY via GUSB3PIPECTLn if required. | |
2962 | * | |
2963 | * Update GTXFIFOSIZn | |
2964 | * | |
2965 | * In both cases reset values should be sufficient. | |
2966 | */ | |
2967 | } | |
2968 | ||
2969 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
2970 | { | |
72246da4 FB |
2971 | /* |
2972 | * TODO take core out of low power mode when that's | |
2973 | * implemented. | |
2974 | */ | |
2975 | ||
ad14d4e0 JL |
2976 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
2977 | spin_unlock(&dwc->lock); | |
2978 | dwc->gadget_driver->resume(&dwc->gadget); | |
2979 | spin_lock(&dwc->lock); | |
2980 | } | |
72246da4 FB |
2981 | } |
2982 | ||
2983 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
2984 | unsigned int evtinfo) | |
2985 | { | |
fae2b904 | 2986 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
2987 | unsigned int pwropt; |
2988 | ||
2989 | /* | |
2990 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
2991 | * Hibernation mode enabled which would show up when device detects | |
2992 | * host-initiated U3 exit. | |
2993 | * | |
2994 | * In that case, device will generate a Link State Change Interrupt | |
2995 | * from U3 to RESUME which is only necessary if Hibernation is | |
2996 | * configured in. | |
2997 | * | |
2998 | * There are no functional changes due to such spurious event and we | |
2999 | * just need to ignore it. | |
3000 | * | |
3001 | * Refers to: | |
3002 | * | |
3003 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
3004 | * operational mode | |
3005 | */ | |
3006 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
3007 | if ((dwc->revision < DWC3_REVISION_250A) && | |
3008 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { | |
3009 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
3010 | (next == DWC3_LINK_STATE_RESUME)) { | |
0b0cc1cd FB |
3011 | return; |
3012 | } | |
3013 | } | |
fae2b904 FB |
3014 | |
3015 | /* | |
3016 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
3017 | * on the link partner, the USB session might do multiple entry/exit | |
3018 | * of low power states before a transfer takes place. | |
3019 | * | |
3020 | * Due to this problem, we might experience lower throughput. The | |
3021 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
3022 | * transitioning from U1/U2 to U0 and enable those bits again | |
3023 | * after a transfer completes and there are no pending transfers | |
3024 | * on any of the enabled endpoints. | |
3025 | * | |
3026 | * This is the first half of that workaround. | |
3027 | * | |
3028 | * Refers to: | |
3029 | * | |
3030 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
3031 | * core send LGO_Ux entering U0 | |
3032 | */ | |
3033 | if (dwc->revision < DWC3_REVISION_183A) { | |
3034 | if (next == DWC3_LINK_STATE_U0) { | |
3035 | u32 u1u2; | |
3036 | u32 reg; | |
3037 | ||
3038 | switch (dwc->link_state) { | |
3039 | case DWC3_LINK_STATE_U1: | |
3040 | case DWC3_LINK_STATE_U2: | |
3041 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3042 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
3043 | | DWC3_DCTL_ACCEPTU2ENA | |
3044 | | DWC3_DCTL_INITU1ENA | |
3045 | | DWC3_DCTL_ACCEPTU1ENA); | |
3046 | ||
3047 | if (!dwc->u1u2) | |
3048 | dwc->u1u2 = reg & u1u2; | |
3049 | ||
3050 | reg &= ~u1u2; | |
3051 | ||
5b738211 | 3052 | dwc3_gadget_dctl_write_safe(dwc, reg); |
fae2b904 FB |
3053 | break; |
3054 | default: | |
3055 | /* do nothing */ | |
3056 | break; | |
3057 | } | |
3058 | } | |
3059 | } | |
3060 | ||
bc5ba2e0 FB |
3061 | switch (next) { |
3062 | case DWC3_LINK_STATE_U1: | |
3063 | if (dwc->speed == USB_SPEED_SUPER) | |
3064 | dwc3_suspend_gadget(dwc); | |
3065 | break; | |
3066 | case DWC3_LINK_STATE_U2: | |
3067 | case DWC3_LINK_STATE_U3: | |
3068 | dwc3_suspend_gadget(dwc); | |
3069 | break; | |
3070 | case DWC3_LINK_STATE_RESUME: | |
3071 | dwc3_resume_gadget(dwc); | |
3072 | break; | |
3073 | default: | |
3074 | /* do nothing */ | |
3075 | break; | |
3076 | } | |
3077 | ||
e57ebc1d | 3078 | dwc->link_state = next; |
72246da4 FB |
3079 | } |
3080 | ||
72704f87 BW |
3081 | static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc, |
3082 | unsigned int evtinfo) | |
3083 | { | |
3084 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; | |
3085 | ||
3086 | if (dwc->link_state != next && next == DWC3_LINK_STATE_U3) | |
3087 | dwc3_suspend_gadget(dwc); | |
3088 | ||
3089 | dwc->link_state = next; | |
3090 | } | |
3091 | ||
e1dadd3b FB |
3092 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, |
3093 | unsigned int evtinfo) | |
3094 | { | |
3095 | unsigned int is_ss = evtinfo & BIT(4); | |
3096 | ||
bfad65ee | 3097 | /* |
e1dadd3b FB |
3098 | * WORKAROUND: DWC3 revison 2.20a with hibernation support |
3099 | * have a known issue which can cause USB CV TD.9.23 to fail | |
3100 | * randomly. | |
3101 | * | |
3102 | * Because of this issue, core could generate bogus hibernation | |
3103 | * events which SW needs to ignore. | |
3104 | * | |
3105 | * Refers to: | |
3106 | * | |
3107 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
3108 | * Device Fallback from SuperSpeed | |
3109 | */ | |
3110 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
3111 | return; | |
3112 | ||
3113 | /* enter hibernation here */ | |
3114 | } | |
3115 | ||
72246da4 FB |
3116 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, |
3117 | const struct dwc3_event_devt *event) | |
3118 | { | |
3119 | switch (event->type) { | |
3120 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
3121 | dwc3_gadget_disconnect_interrupt(dwc); | |
3122 | break; | |
3123 | case DWC3_DEVICE_EVENT_RESET: | |
3124 | dwc3_gadget_reset_interrupt(dwc); | |
3125 | break; | |
3126 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
3127 | dwc3_gadget_conndone_interrupt(dwc); | |
3128 | break; | |
3129 | case DWC3_DEVICE_EVENT_WAKEUP: | |
3130 | dwc3_gadget_wakeup_interrupt(dwc); | |
3131 | break; | |
e1dadd3b FB |
3132 | case DWC3_DEVICE_EVENT_HIBER_REQ: |
3133 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
3134 | "unexpected hibernation event\n")) | |
3135 | break; | |
3136 | ||
3137 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
3138 | break; | |
72246da4 FB |
3139 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: |
3140 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
3141 | break; | |
3142 | case DWC3_DEVICE_EVENT_EOPF: | |
72704f87 | 3143 | /* It changed to be suspend event for version 2.30a and above */ |
5eb30ced | 3144 | if (dwc->revision >= DWC3_REVISION_230A) { |
72704f87 BW |
3145 | /* |
3146 | * Ignore suspend event until the gadget enters into | |
3147 | * USB_STATE_CONFIGURED state. | |
3148 | */ | |
3149 | if (dwc->gadget.state >= USB_STATE_CONFIGURED) | |
3150 | dwc3_gadget_suspend_interrupt(dwc, | |
3151 | event->event_info); | |
3152 | } | |
72246da4 FB |
3153 | break; |
3154 | case DWC3_DEVICE_EVENT_SOF: | |
72246da4 | 3155 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: |
72246da4 | 3156 | case DWC3_DEVICE_EVENT_CMD_CMPL: |
72246da4 | 3157 | case DWC3_DEVICE_EVENT_OVERFLOW: |
72246da4 FB |
3158 | break; |
3159 | default: | |
e9f2aa87 | 3160 | dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type); |
72246da4 FB |
3161 | } |
3162 | } | |
3163 | ||
3164 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
3165 | const union dwc3_event *event) | |
3166 | { | |
43c96be1 | 3167 | trace_dwc3_event(event->raw, dwc); |
2c4cbe6e | 3168 | |
dfc5e805 FB |
3169 | if (!event->type.is_devspec) |
3170 | dwc3_endpoint_interrupt(dwc, &event->depevt); | |
3171 | else if (event->type.type == DWC3_EVENT_TYPE_DEV) | |
72246da4 | 3172 | dwc3_gadget_interrupt(dwc, &event->devt); |
dfc5e805 | 3173 | else |
72246da4 | 3174 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); |
72246da4 FB |
3175 | } |
3176 | ||
dea520a4 | 3177 | static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt) |
b15a762f | 3178 | { |
dea520a4 | 3179 | struct dwc3 *dwc = evt->dwc; |
b15a762f | 3180 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 3181 | int left; |
e8adfc30 | 3182 | u32 reg; |
b15a762f | 3183 | |
f42f2447 | 3184 | left = evt->count; |
b15a762f | 3185 | |
f42f2447 FB |
3186 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
3187 | return IRQ_NONE; | |
b15a762f | 3188 | |
f42f2447 FB |
3189 | while (left > 0) { |
3190 | union dwc3_event event; | |
b15a762f | 3191 | |
ebbb2d59 | 3192 | event.raw = *(u32 *) (evt->cache + evt->lpos); |
b15a762f | 3193 | |
f42f2447 | 3194 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 3195 | |
f42f2447 FB |
3196 | /* |
3197 | * FIXME we wrap around correctly to the next entry as | |
3198 | * almost all entries are 4 bytes in size. There is one | |
3199 | * entry which has 12 bytes which is a regular entry | |
3200 | * followed by 8 bytes data. ATM I don't know how | |
3201 | * things are organized if we get next to the a | |
3202 | * boundary so I worry about that once we try to handle | |
3203 | * that. | |
3204 | */ | |
caefe6c7 | 3205 | evt->lpos = (evt->lpos + 4) % evt->length; |
f42f2447 | 3206 | left -= 4; |
f42f2447 | 3207 | } |
b15a762f | 3208 | |
f42f2447 FB |
3209 | evt->count = 0; |
3210 | evt->flags &= ~DWC3_EVENT_PENDING; | |
3211 | ret = IRQ_HANDLED; | |
b15a762f | 3212 | |
f42f2447 | 3213 | /* Unmask interrupt */ |
660e9bde | 3214 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
f42f2447 | 3215 | reg &= ~DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 3216 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
b15a762f | 3217 | |
cf40b86b JY |
3218 | if (dwc->imod_interval) { |
3219 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); | |
3220 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); | |
3221 | } | |
3222 | ||
f42f2447 FB |
3223 | return ret; |
3224 | } | |
e8adfc30 | 3225 | |
dea520a4 | 3226 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt) |
f42f2447 | 3227 | { |
dea520a4 FB |
3228 | struct dwc3_event_buffer *evt = _evt; |
3229 | struct dwc3 *dwc = evt->dwc; | |
e5f68b4a | 3230 | unsigned long flags; |
f42f2447 | 3231 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 3232 | |
e5f68b4a | 3233 | spin_lock_irqsave(&dwc->lock, flags); |
dea520a4 | 3234 | ret = dwc3_process_event_buf(evt); |
e5f68b4a | 3235 | spin_unlock_irqrestore(&dwc->lock, flags); |
b15a762f FB |
3236 | |
3237 | return ret; | |
3238 | } | |
3239 | ||
dea520a4 | 3240 | static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) |
72246da4 | 3241 | { |
dea520a4 | 3242 | struct dwc3 *dwc = evt->dwc; |
ebbb2d59 | 3243 | u32 amount; |
72246da4 | 3244 | u32 count; |
e8adfc30 | 3245 | u32 reg; |
72246da4 | 3246 | |
fc8bb91b FB |
3247 | if (pm_runtime_suspended(dwc->dev)) { |
3248 | pm_runtime_get(dwc->dev); | |
3249 | disable_irq_nosync(dwc->irq_gadget); | |
3250 | dwc->pending_events = true; | |
3251 | return IRQ_HANDLED; | |
3252 | } | |
3253 | ||
d325a1de TN |
3254 | /* |
3255 | * With PCIe legacy interrupt, test shows that top-half irq handler can | |
3256 | * be called again after HW interrupt deassertion. Check if bottom-half | |
3257 | * irq event handler completes before caching new event to prevent | |
3258 | * losing events. | |
3259 | */ | |
3260 | if (evt->flags & DWC3_EVENT_PENDING) | |
3261 | return IRQ_HANDLED; | |
3262 | ||
660e9bde | 3263 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); |
72246da4 FB |
3264 | count &= DWC3_GEVNTCOUNT_MASK; |
3265 | if (!count) | |
3266 | return IRQ_NONE; | |
3267 | ||
b15a762f FB |
3268 | evt->count = count; |
3269 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 3270 | |
e8adfc30 | 3271 | /* Mask interrupt */ |
660e9bde | 3272 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
e8adfc30 | 3273 | reg |= DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 3274 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
e8adfc30 | 3275 | |
ebbb2d59 JY |
3276 | amount = min(count, evt->length - evt->lpos); |
3277 | memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount); | |
3278 | ||
3279 | if (amount < count) | |
3280 | memcpy(evt->cache, evt->buf, count - amount); | |
3281 | ||
65aca320 JY |
3282 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count); |
3283 | ||
b15a762f | 3284 | return IRQ_WAKE_THREAD; |
72246da4 FB |
3285 | } |
3286 | ||
dea520a4 | 3287 | static irqreturn_t dwc3_interrupt(int irq, void *_evt) |
72246da4 | 3288 | { |
dea520a4 | 3289 | struct dwc3_event_buffer *evt = _evt; |
72246da4 | 3290 | |
dea520a4 | 3291 | return dwc3_check_event_buf(evt); |
72246da4 FB |
3292 | } |
3293 | ||
6db3812e FB |
3294 | static int dwc3_gadget_get_irq(struct dwc3 *dwc) |
3295 | { | |
3296 | struct platform_device *dwc3_pdev = to_platform_device(dwc->dev); | |
3297 | int irq; | |
3298 | ||
f146b40b | 3299 | irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral"); |
6db3812e FB |
3300 | if (irq > 0) |
3301 | goto out; | |
3302 | ||
3303 | if (irq == -EPROBE_DEFER) | |
3304 | goto out; | |
3305 | ||
f146b40b | 3306 | irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3"); |
6db3812e FB |
3307 | if (irq > 0) |
3308 | goto out; | |
3309 | ||
3310 | if (irq == -EPROBE_DEFER) | |
3311 | goto out; | |
3312 | ||
3313 | irq = platform_get_irq(dwc3_pdev, 0); | |
3314 | if (irq > 0) | |
3315 | goto out; | |
3316 | ||
6db3812e FB |
3317 | if (!irq) |
3318 | irq = -EINVAL; | |
3319 | ||
3320 | out: | |
3321 | return irq; | |
3322 | } | |
3323 | ||
72246da4 | 3324 | /** |
bfad65ee | 3325 | * dwc3_gadget_init - initializes gadget related registers |
1d046793 | 3326 | * @dwc: pointer to our controller context structure |
72246da4 FB |
3327 | * |
3328 | * Returns 0 on success otherwise negative errno. | |
3329 | */ | |
41ac7b3a | 3330 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 3331 | { |
6db3812e FB |
3332 | int ret; |
3333 | int irq; | |
9522def4 | 3334 | |
6db3812e FB |
3335 | irq = dwc3_gadget_get_irq(dwc); |
3336 | if (irq < 0) { | |
3337 | ret = irq; | |
3338 | goto err0; | |
9522def4 RQ |
3339 | } |
3340 | ||
3341 | dwc->irq_gadget = irq; | |
72246da4 | 3342 | |
d64ff406 AB |
3343 | dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev, |
3344 | sizeof(*dwc->ep0_trb) * 2, | |
3345 | &dwc->ep0_trb_addr, GFP_KERNEL); | |
72246da4 FB |
3346 | if (!dwc->ep0_trb) { |
3347 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
3348 | ret = -ENOMEM; | |
7d5e650a | 3349 | goto err0; |
72246da4 FB |
3350 | } |
3351 | ||
4199c5f8 | 3352 | dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL); |
72246da4 | 3353 | if (!dwc->setup_buf) { |
72246da4 | 3354 | ret = -ENOMEM; |
7d5e650a | 3355 | goto err1; |
72246da4 FB |
3356 | } |
3357 | ||
905dc04e FB |
3358 | dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, |
3359 | &dwc->bounce_addr, GFP_KERNEL); | |
3360 | if (!dwc->bounce) { | |
3361 | ret = -ENOMEM; | |
d6e5a549 | 3362 | goto err2; |
905dc04e FB |
3363 | } |
3364 | ||
bb014736 BW |
3365 | init_completion(&dwc->ep0_in_setup); |
3366 | ||
72246da4 | 3367 | dwc->gadget.ops = &dwc3_gadget_ops; |
72246da4 | 3368 | dwc->gadget.speed = USB_SPEED_UNKNOWN; |
eeb720fb | 3369 | dwc->gadget.sg_supported = true; |
72246da4 | 3370 | dwc->gadget.name = "dwc3-gadget"; |
c729969b | 3371 | dwc->gadget.lpm_capable = true; |
72246da4 | 3372 | |
b9e51b2b BM |
3373 | /* |
3374 | * FIXME We might be setting max_speed to <SUPER, however versions | |
3375 | * <2.20a of dwc3 have an issue with metastability (documented | |
3376 | * elsewhere in this driver) which tells us we can't set max speed to | |
3377 | * anything lower than SUPER. | |
3378 | * | |
3379 | * Because gadget.max_speed is only used by composite.c and function | |
3380 | * drivers (i.e. it won't go into dwc3's registers) we are allowing this | |
3381 | * to happen so we avoid sending SuperSpeed Capability descriptor | |
3382 | * together with our BOS descriptor as that could confuse host into | |
3383 | * thinking we can handle super speed. | |
3384 | * | |
3385 | * Note that, in fact, we won't even support GetBOS requests when speed | |
3386 | * is less than super speed because we don't have means, yet, to tell | |
3387 | * composite.c that we are USB 2.0 + LPM ECN. | |
3388 | */ | |
42bf02ec RQ |
3389 | if (dwc->revision < DWC3_REVISION_220A && |
3390 | !dwc->dis_metastability_quirk) | |
5eb30ced | 3391 | dev_info(dwc->dev, "changing max_speed on rev %08x\n", |
b9e51b2b BM |
3392 | dwc->revision); |
3393 | ||
3394 | dwc->gadget.max_speed = dwc->maximum_speed; | |
3395 | ||
72246da4 FB |
3396 | /* |
3397 | * REVISIT: Here we should clear all pending IRQs to be | |
3398 | * sure we're starting from a well known location. | |
3399 | */ | |
3400 | ||
f3bcfc7e | 3401 | ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps); |
72246da4 | 3402 | if (ret) |
d6e5a549 | 3403 | goto err3; |
72246da4 | 3404 | |
72246da4 FB |
3405 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); |
3406 | if (ret) { | |
3407 | dev_err(dwc->dev, "failed to register udc\n"); | |
d6e5a549 | 3408 | goto err4; |
72246da4 FB |
3409 | } |
3410 | ||
169e3b68 RQ |
3411 | dwc3_gadget_set_speed(&dwc->gadget, dwc->maximum_speed); |
3412 | ||
72246da4 FB |
3413 | return 0; |
3414 | ||
7d5e650a | 3415 | err4: |
d6e5a549 | 3416 | dwc3_gadget_free_endpoints(dwc); |
04c03d10 | 3417 | |
7d5e650a | 3418 | err3: |
d6e5a549 FB |
3419 | dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce, |
3420 | dwc->bounce_addr); | |
5812b1c2 | 3421 | |
7d5e650a | 3422 | err2: |
0fc9a1be | 3423 | kfree(dwc->setup_buf); |
72246da4 | 3424 | |
7d5e650a | 3425 | err1: |
d64ff406 | 3426 | dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
3427 | dwc->ep0_trb, dwc->ep0_trb_addr); |
3428 | ||
72246da4 FB |
3429 | err0: |
3430 | return ret; | |
3431 | } | |
3432 | ||
7415f17c FB |
3433 | /* -------------------------------------------------------------------------- */ |
3434 | ||
72246da4 FB |
3435 | void dwc3_gadget_exit(struct dwc3 *dwc) |
3436 | { | |
72246da4 | 3437 | usb_del_gadget_udc(&dwc->gadget); |
72246da4 | 3438 | dwc3_gadget_free_endpoints(dwc); |
905dc04e | 3439 | dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce, |
d6e5a549 | 3440 | dwc->bounce_addr); |
0fc9a1be | 3441 | kfree(dwc->setup_buf); |
d64ff406 | 3442 | dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, |
d6e5a549 | 3443 | dwc->ep0_trb, dwc->ep0_trb_addr); |
72246da4 | 3444 | } |
7415f17c | 3445 | |
0b0231aa | 3446 | int dwc3_gadget_suspend(struct dwc3 *dwc) |
7415f17c | 3447 | { |
9772b47a RQ |
3448 | if (!dwc->gadget_driver) |
3449 | return 0; | |
3450 | ||
1551e35e | 3451 | dwc3_gadget_run_stop(dwc, false, false); |
9f8a67b6 FB |
3452 | dwc3_disconnect_gadget(dwc); |
3453 | __dwc3_gadget_stop(dwc); | |
7415f17c FB |
3454 | |
3455 | return 0; | |
3456 | } | |
3457 | ||
3458 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
3459 | { | |
7415f17c FB |
3460 | int ret; |
3461 | ||
9772b47a RQ |
3462 | if (!dwc->gadget_driver) |
3463 | return 0; | |
3464 | ||
9f8a67b6 FB |
3465 | ret = __dwc3_gadget_start(dwc); |
3466 | if (ret < 0) | |
7415f17c FB |
3467 | goto err0; |
3468 | ||
9f8a67b6 FB |
3469 | ret = dwc3_gadget_run_stop(dwc, true, false); |
3470 | if (ret < 0) | |
7415f17c FB |
3471 | goto err1; |
3472 | ||
7415f17c FB |
3473 | return 0; |
3474 | ||
3475 | err1: | |
9f8a67b6 | 3476 | __dwc3_gadget_stop(dwc); |
7415f17c FB |
3477 | |
3478 | err0: | |
3479 | return ret; | |
3480 | } | |
fc8bb91b FB |
3481 | |
3482 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc) | |
3483 | { | |
3484 | if (dwc->pending_events) { | |
3485 | dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf); | |
3486 | dwc->pending_events = false; | |
3487 | enable_irq(dwc->irq_gadget); | |
3488 | } | |
3489 | } |