Commit | Line | Data |
---|---|---|
5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
bfad65ee | 2 | /* |
72246da4 FB |
3 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link |
4 | * | |
10623b87 | 5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com |
72246da4 FB |
6 | * |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
72246da4 FB |
9 | */ |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/pm_runtime.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | ||
22 | #include <linux/usb/ch9.h> | |
23 | #include <linux/usb/gadget.h> | |
24 | ||
80977dc9 | 25 | #include "debug.h" |
72246da4 FB |
26 | #include "core.h" |
27 | #include "gadget.h" | |
28 | #include "io.h" | |
29 | ||
d5370106 | 30 | #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \ |
f62afb49 FB |
31 | & ~((d)->interval - 1)) |
32 | ||
04a9bfcd | 33 | /** |
bfad65ee | 34 | * dwc3_gadget_set_test_mode - enables usb2 test modes |
04a9bfcd FB |
35 | * @dwc: pointer to our context structure |
36 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
37 | * | |
bfad65ee FB |
38 | * Caller should take care of locking. This function will return 0 on |
39 | * success or -EINVAL if wrong Test Selector is passed. | |
04a9bfcd FB |
40 | */ |
41 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
42 | { | |
43 | u32 reg; | |
44 | ||
45 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
46 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
47 | ||
48 | switch (mode) { | |
62fb45d3 GKH |
49 | case USB_TEST_J: |
50 | case USB_TEST_K: | |
51 | case USB_TEST_SE0_NAK: | |
52 | case USB_TEST_PACKET: | |
53 | case USB_TEST_FORCE_ENABLE: | |
04a9bfcd FB |
54 | reg |= mode << 1; |
55 | break; | |
56 | default: | |
57 | return -EINVAL; | |
58 | } | |
59 | ||
5b738211 | 60 | dwc3_gadget_dctl_write_safe(dwc, reg); |
04a9bfcd FB |
61 | |
62 | return 0; | |
63 | } | |
64 | ||
911f1f88 | 65 | /** |
bfad65ee | 66 | * dwc3_gadget_get_link_state - gets current state of usb link |
911f1f88 PZ |
67 | * @dwc: pointer to our context structure |
68 | * | |
69 | * Caller should take care of locking. This function will | |
70 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
71 | */ | |
72 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
73 | { | |
74 | u32 reg; | |
75 | ||
76 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
77 | ||
78 | return DWC3_DSTS_USBLNKST(reg); | |
79 | } | |
80 | ||
8598bde7 | 81 | /** |
bfad65ee | 82 | * dwc3_gadget_set_link_state - sets usb link to a particular state |
8598bde7 FB |
83 | * @dwc: pointer to our context structure |
84 | * @state: the state to put link into | |
85 | * | |
86 | * Caller should take care of locking. This function will | |
aee63e3c | 87 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
88 | */ |
89 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
90 | { | |
aee63e3c | 91 | int retries = 10000; |
8598bde7 FB |
92 | u32 reg; |
93 | ||
802fde98 PZ |
94 | /* |
95 | * Wait until device controller is ready. Only applies to 1.94a and | |
96 | * later RTL. | |
97 | */ | |
9af21dd6 | 98 | if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) { |
802fde98 PZ |
99 | while (--retries) { |
100 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
101 | if (reg & DWC3_DSTS_DCNRD) | |
102 | udelay(5); | |
103 | else | |
104 | break; | |
105 | } | |
106 | ||
107 | if (retries <= 0) | |
108 | return -ETIMEDOUT; | |
109 | } | |
110 | ||
8598bde7 FB |
111 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
112 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
113 | ||
2e708fa3 TN |
114 | /* set no action before sending new link state change */ |
115 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
116 | ||
8598bde7 FB |
117 | /* set requested state */ |
118 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
119 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
120 | ||
802fde98 PZ |
121 | /* |
122 | * The following code is racy when called from dwc3_gadget_wakeup, | |
123 | * and is not needed, at least on newer versions | |
124 | */ | |
9af21dd6 | 125 | if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) |
802fde98 PZ |
126 | return 0; |
127 | ||
8598bde7 | 128 | /* wait for a change in DSTS */ |
aed430e5 | 129 | retries = 10000; |
8598bde7 FB |
130 | while (--retries) { |
131 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
132 | ||
8598bde7 FB |
133 | if (DWC3_DSTS_USBLNKST(reg) == state) |
134 | return 0; | |
135 | ||
aee63e3c | 136 | udelay(5); |
8598bde7 FB |
137 | } |
138 | ||
8598bde7 FB |
139 | return -ETIMEDOUT; |
140 | } | |
141 | ||
dca0119c | 142 | /** |
bfad65ee FB |
143 | * dwc3_ep_inc_trb - increment a trb index. |
144 | * @index: Pointer to the TRB index to increment. | |
dca0119c JY |
145 | * |
146 | * The index should never point to the link TRB. After incrementing, | |
147 | * if it is point to the link TRB, wrap around to the beginning. The | |
148 | * link TRB is always at the last TRB entry. | |
149 | */ | |
150 | static void dwc3_ep_inc_trb(u8 *index) | |
457e84b6 | 151 | { |
dca0119c JY |
152 | (*index)++; |
153 | if (*index == (DWC3_TRB_NUM - 1)) | |
154 | *index = 0; | |
ef966b9d | 155 | } |
457e84b6 | 156 | |
bfad65ee FB |
157 | /** |
158 | * dwc3_ep_inc_enq - increment endpoint's enqueue pointer | |
159 | * @dep: The endpoint whose enqueue pointer we're incrementing | |
160 | */ | |
dca0119c | 161 | static void dwc3_ep_inc_enq(struct dwc3_ep *dep) |
ef966b9d | 162 | { |
dca0119c | 163 | dwc3_ep_inc_trb(&dep->trb_enqueue); |
ef966b9d | 164 | } |
457e84b6 | 165 | |
bfad65ee FB |
166 | /** |
167 | * dwc3_ep_inc_deq - increment endpoint's dequeue pointer | |
168 | * @dep: The endpoint whose enqueue pointer we're incrementing | |
169 | */ | |
dca0119c | 170 | static void dwc3_ep_inc_deq(struct dwc3_ep *dep) |
ef966b9d | 171 | { |
dca0119c | 172 | dwc3_ep_inc_trb(&dep->trb_dequeue); |
457e84b6 FB |
173 | } |
174 | ||
69102510 | 175 | static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep, |
c91815b5 | 176 | struct dwc3_request *req, int status) |
72246da4 FB |
177 | { |
178 | struct dwc3 *dwc = dep->dwc; | |
179 | ||
72246da4 | 180 | list_del(&req->list); |
e62c5bc5 | 181 | req->remaining = 0; |
bd674224 | 182 | req->needs_extra_trb = false; |
72246da4 FB |
183 | |
184 | if (req->request.status == -EINPROGRESS) | |
185 | req->request.status = status; | |
186 | ||
4a71fcb8 JP |
187 | if (req->trb) |
188 | usb_gadget_unmap_request_by_dev(dwc->sysdev, | |
c91815b5 | 189 | &req->request, req->direction); |
4a71fcb8 JP |
190 | |
191 | req->trb = NULL; | |
2c4cbe6e | 192 | trace_dwc3_gadget_giveback(req); |
72246da4 | 193 | |
c91815b5 FB |
194 | if (dep->number > 1) |
195 | pm_runtime_put(dwc->dev); | |
196 | } | |
197 | ||
198 | /** | |
199 | * dwc3_gadget_giveback - call struct usb_request's ->complete callback | |
200 | * @dep: The endpoint to whom the request belongs to | |
201 | * @req: The request we're giving back | |
202 | * @status: completion code for the request | |
203 | * | |
204 | * Must be called with controller's lock held and interrupts disabled. This | |
205 | * function will unmap @req and call its ->complete() callback to notify upper | |
206 | * layers that it has completed. | |
207 | */ | |
208 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, | |
209 | int status) | |
210 | { | |
211 | struct dwc3 *dwc = dep->dwc; | |
212 | ||
213 | dwc3_gadget_del_and_unmap_request(dep, req, status); | |
a3af5e3a | 214 | req->status = DWC3_REQUEST_STATUS_COMPLETED; |
c91815b5 | 215 | |
72246da4 | 216 | spin_unlock(&dwc->lock); |
304f7e5e | 217 | usb_gadget_giveback_request(&dep->endpoint, &req->request); |
72246da4 FB |
218 | spin_lock(&dwc->lock); |
219 | } | |
220 | ||
bfad65ee FB |
221 | /** |
222 | * dwc3_send_gadget_generic_command - issue a generic command for the controller | |
223 | * @dwc: pointer to the controller context | |
224 | * @cmd: the command to be issued | |
225 | * @param: command parameter | |
226 | * | |
227 | * Caller should take care of locking. Issue @cmd with a given @param to @dwc | |
228 | * and wait for its completion. | |
229 | */ | |
3ece0ec4 | 230 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param) |
b09bb642 FB |
231 | { |
232 | u32 timeout = 500; | |
71f7e702 | 233 | int status = 0; |
0fe886cd | 234 | int ret = 0; |
b09bb642 FB |
235 | u32 reg; |
236 | ||
237 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); | |
238 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
239 | ||
240 | do { | |
241 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
242 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
71f7e702 FB |
243 | status = DWC3_DGCMD_STATUS(reg); |
244 | if (status) | |
0fe886cd FB |
245 | ret = -EINVAL; |
246 | break; | |
b09bb642 | 247 | } |
e3aee486 | 248 | } while (--timeout); |
0fe886cd FB |
249 | |
250 | if (!timeout) { | |
0fe886cd | 251 | ret = -ETIMEDOUT; |
71f7e702 | 252 | status = -ETIMEDOUT; |
0fe886cd FB |
253 | } |
254 | ||
71f7e702 FB |
255 | trace_dwc3_gadget_generic_cmd(cmd, param, status); |
256 | ||
0fe886cd | 257 | return ret; |
b09bb642 FB |
258 | } |
259 | ||
c36d8e94 FB |
260 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc); |
261 | ||
bfad65ee FB |
262 | /** |
263 | * dwc3_send_gadget_ep_cmd - issue an endpoint command | |
264 | * @dep: the endpoint to which the command is going to be issued | |
265 | * @cmd: the command to be issued | |
266 | * @params: parameters to the command | |
267 | * | |
268 | * Caller should handle locking. This function will issue @cmd with given | |
269 | * @params to @dep and wait for its completion. | |
270 | */ | |
2cd4718d FB |
271 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, |
272 | struct dwc3_gadget_ep_cmd_params *params) | |
72246da4 | 273 | { |
8897a761 | 274 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
2cd4718d | 275 | struct dwc3 *dwc = dep->dwc; |
1c0e69ae | 276 | u32 timeout = 5000; |
87dd9611 | 277 | u32 saved_config = 0; |
72246da4 FB |
278 | u32 reg; |
279 | ||
0933df15 | 280 | int cmd_status = 0; |
c0ca324d | 281 | int ret = -EINVAL; |
72246da4 | 282 | |
2b0f11df | 283 | /* |
87dd9611 TN |
284 | * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or |
285 | * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an | |
286 | * endpoint command. | |
2b0f11df | 287 | * |
87dd9611 TN |
288 | * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY |
289 | * settings. Restore them after the command is completed. | |
290 | * | |
291 | * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2 | |
2b0f11df | 292 | */ |
ab2a92e7 FB |
293 | if (dwc->gadget.speed <= USB_SPEED_HIGH) { |
294 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
295 | if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) { | |
87dd9611 | 296 | saved_config |= DWC3_GUSB2PHYCFG_SUSPHY; |
ab2a92e7 | 297 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; |
ab2a92e7 | 298 | } |
87dd9611 TN |
299 | |
300 | if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) { | |
301 | saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM; | |
302 | reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; | |
303 | } | |
304 | ||
305 | if (saved_config) | |
306 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
2b0f11df FB |
307 | } |
308 | ||
5999914f | 309 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { |
c36d8e94 FB |
310 | int needs_wakeup; |
311 | ||
312 | needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 || | |
313 | dwc->link_state == DWC3_LINK_STATE_U2 || | |
314 | dwc->link_state == DWC3_LINK_STATE_U3); | |
315 | ||
316 | if (unlikely(needs_wakeup)) { | |
317 | ret = __dwc3_gadget_wakeup(dwc); | |
318 | dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n", | |
319 | ret); | |
320 | } | |
321 | } | |
322 | ||
2eb88016 FB |
323 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0); |
324 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1); | |
325 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2); | |
72246da4 | 326 | |
8897a761 FB |
327 | /* |
328 | * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're | |
329 | * not relying on XferNotReady, we can make use of a special "No | |
330 | * Response Update Transfer" command where we should clear both CmdAct | |
331 | * and CmdIOC bits. | |
332 | * | |
333 | * With this, we don't need to wait for command completion and can | |
334 | * straight away issue further commands to the endpoint. | |
335 | * | |
336 | * NOTICE: We're making an assumption that control endpoints will never | |
337 | * make use of Update Transfer command. This is a safe assumption | |
338 | * because we can never have more than one request at a time with | |
339 | * Control Endpoints. If anybody changes that assumption, this chunk | |
340 | * needs to be updated accordingly. | |
341 | */ | |
342 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER && | |
343 | !usb_endpoint_xfer_isoc(desc)) | |
344 | cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT); | |
345 | else | |
346 | cmd |= DWC3_DEPCMD_CMDACT; | |
347 | ||
348 | dwc3_writel(dep->regs, DWC3_DEPCMD, cmd); | |
72246da4 | 349 | do { |
2eb88016 | 350 | reg = dwc3_readl(dep->regs, DWC3_DEPCMD); |
72246da4 | 351 | if (!(reg & DWC3_DEPCMD_CMDACT)) { |
0933df15 | 352 | cmd_status = DWC3_DEPCMD_STATUS(reg); |
7b9cc7a2 | 353 | |
7b9cc7a2 KL |
354 | switch (cmd_status) { |
355 | case 0: | |
356 | ret = 0; | |
357 | break; | |
358 | case DEPEVT_TRANSFER_NO_RESOURCE: | |
f7ac582e TN |
359 | dev_WARN(dwc->dev, "No resource for %s\n", |
360 | dep->name); | |
7b9cc7a2 | 361 | ret = -EINVAL; |
c0ca324d | 362 | break; |
7b9cc7a2 KL |
363 | case DEPEVT_TRANSFER_BUS_EXPIRY: |
364 | /* | |
365 | * SW issues START TRANSFER command to | |
366 | * isochronous ep with future frame interval. If | |
367 | * future interval time has already passed when | |
368 | * core receives the command, it will respond | |
369 | * with an error status of 'Bus Expiry'. | |
370 | * | |
371 | * Instead of always returning -EINVAL, let's | |
372 | * give a hint to the gadget driver that this is | |
373 | * the case by returning -EAGAIN. | |
374 | */ | |
7b9cc7a2 KL |
375 | ret = -EAGAIN; |
376 | break; | |
377 | default: | |
378 | dev_WARN(dwc->dev, "UNKNOWN cmd status\n"); | |
379 | } | |
380 | ||
c0ca324d | 381 | break; |
72246da4 | 382 | } |
f6bb225b | 383 | } while (--timeout); |
72246da4 | 384 | |
f6bb225b | 385 | if (timeout == 0) { |
f6bb225b | 386 | ret = -ETIMEDOUT; |
0933df15 | 387 | cmd_status = -ETIMEDOUT; |
f6bb225b | 388 | } |
c0ca324d | 389 | |
0933df15 FB |
390 | trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status); |
391 | ||
9bc3395c TN |
392 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { |
393 | if (ret == 0) | |
394 | dep->flags |= DWC3_EP_TRANSFER_STARTED; | |
395 | ||
396 | if (ret != -ETIMEDOUT) | |
397 | dwc3_gadget_ep_get_transfer_index(dep); | |
6cb2e4e3 FB |
398 | } |
399 | ||
87dd9611 | 400 | if (saved_config) { |
2b0f11df | 401 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
87dd9611 | 402 | reg |= saved_config; |
2b0f11df FB |
403 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
404 | } | |
405 | ||
c0ca324d | 406 | return ret; |
72246da4 FB |
407 | } |
408 | ||
50c763f8 JY |
409 | static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep) |
410 | { | |
411 | struct dwc3 *dwc = dep->dwc; | |
412 | struct dwc3_gadget_ep_cmd_params params; | |
413 | u32 cmd = DWC3_DEPCMD_CLEARSTALL; | |
414 | ||
415 | /* | |
416 | * As of core revision 2.60a the recommended programming model | |
417 | * is to set the ClearPendIN bit when issuing a Clear Stall EP | |
418 | * command for IN endpoints. This is to prevent an issue where | |
419 | * some (non-compliant) hosts may not send ACK TPs for pending | |
420 | * IN transfers due to a mishandled error condition. Synopsys | |
421 | * STAR 9000614252. | |
422 | */ | |
9af21dd6 TN |
423 | if (dep->direction && |
424 | !DWC3_VER_IS_PRIOR(DWC3, 260A) && | |
5e6c88d2 | 425 | (dwc->gadget.speed >= USB_SPEED_SUPER)) |
50c763f8 JY |
426 | cmd |= DWC3_DEPCMD_CLEARPENDIN; |
427 | ||
428 | memset(¶ms, 0, sizeof(params)); | |
429 | ||
2cd4718d | 430 | return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
50c763f8 JY |
431 | } |
432 | ||
72246da4 | 433 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, |
f6bafc6a | 434 | struct dwc3_trb *trb) |
72246da4 | 435 | { |
c439ef87 | 436 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
437 | |
438 | return dep->trb_pool_dma + offset; | |
439 | } | |
440 | ||
441 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
442 | { | |
443 | struct dwc3 *dwc = dep->dwc; | |
444 | ||
445 | if (dep->trb_pool) | |
446 | return 0; | |
447 | ||
d64ff406 | 448 | dep->trb_pool = dma_alloc_coherent(dwc->sysdev, |
72246da4 FB |
449 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, |
450 | &dep->trb_pool_dma, GFP_KERNEL); | |
451 | if (!dep->trb_pool) { | |
452 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
453 | dep->name); | |
454 | return -ENOMEM; | |
455 | } | |
456 | ||
457 | return 0; | |
458 | } | |
459 | ||
460 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
461 | { | |
462 | struct dwc3 *dwc = dep->dwc; | |
463 | ||
d64ff406 | 464 | dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, |
72246da4 FB |
465 | dep->trb_pool, dep->trb_pool_dma); |
466 | ||
467 | dep->trb_pool = NULL; | |
468 | dep->trb_pool_dma = 0; | |
469 | } | |
470 | ||
20d1d43f FB |
471 | static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep) |
472 | { | |
473 | struct dwc3_gadget_ep_cmd_params params; | |
474 | ||
475 | memset(¶ms, 0x00, sizeof(params)); | |
476 | ||
477 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); | |
478 | ||
479 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE, | |
480 | ¶ms); | |
481 | } | |
c4509601 JY |
482 | |
483 | /** | |
bfad65ee | 484 | * dwc3_gadget_start_config - configure ep resources |
c4509601 JY |
485 | * @dep: endpoint that is being enabled |
486 | * | |
bfad65ee FB |
487 | * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's |
488 | * completion, it will set Transfer Resource for all available endpoints. | |
c4509601 | 489 | * |
bfad65ee FB |
490 | * The assignment of transfer resources cannot perfectly follow the data book |
491 | * due to the fact that the controller driver does not have all knowledge of the | |
492 | * configuration in advance. It is given this information piecemeal by the | |
493 | * composite gadget framework after every SET_CONFIGURATION and | |
494 | * SET_INTERFACE. Trying to follow the databook programming model in this | |
495 | * scenario can cause errors. For two reasons: | |
c4509601 | 496 | * |
bfad65ee FB |
497 | * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every |
498 | * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is | |
499 | * incorrect in the scenario of multiple interfaces. | |
500 | * | |
501 | * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new | |
c4509601 JY |
502 | * endpoint on alt setting (8.1.6). |
503 | * | |
504 | * The following simplified method is used instead: | |
505 | * | |
bfad65ee FB |
506 | * All hardware endpoints can be assigned a transfer resource and this setting |
507 | * will stay persistent until either a core reset or hibernation. So whenever we | |
508 | * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do | |
509 | * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are | |
c4509601 JY |
510 | * guaranteed that there are as many transfer resources as endpoints. |
511 | * | |
bfad65ee FB |
512 | * This function is called for each endpoint when it is being enabled but is |
513 | * triggered only when called for EP0-out, which always happens first, and which | |
514 | * should only happen in one of the above conditions. | |
c4509601 | 515 | */ |
b07c2db8 | 516 | static int dwc3_gadget_start_config(struct dwc3_ep *dep) |
72246da4 FB |
517 | { |
518 | struct dwc3_gadget_ep_cmd_params params; | |
b07c2db8 | 519 | struct dwc3 *dwc; |
72246da4 | 520 | u32 cmd; |
c4509601 JY |
521 | int i; |
522 | int ret; | |
523 | ||
524 | if (dep->number) | |
525 | return 0; | |
72246da4 FB |
526 | |
527 | memset(¶ms, 0x00, sizeof(params)); | |
c4509601 | 528 | cmd = DWC3_DEPCMD_DEPSTARTCFG; |
b07c2db8 | 529 | dwc = dep->dwc; |
72246da4 | 530 | |
2cd4718d | 531 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
c4509601 JY |
532 | if (ret) |
533 | return ret; | |
534 | ||
535 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
536 | struct dwc3_ep *dep = dwc->eps[i]; | |
72246da4 | 537 | |
c4509601 JY |
538 | if (!dep) |
539 | continue; | |
540 | ||
b07c2db8 | 541 | ret = dwc3_gadget_set_xfer_resource(dep); |
c4509601 JY |
542 | if (ret) |
543 | return ret; | |
72246da4 FB |
544 | } |
545 | ||
546 | return 0; | |
547 | } | |
548 | ||
b07c2db8 | 549 | static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action) |
72246da4 | 550 | { |
39ebb05c JY |
551 | const struct usb_ss_ep_comp_descriptor *comp_desc; |
552 | const struct usb_endpoint_descriptor *desc; | |
72246da4 | 553 | struct dwc3_gadget_ep_cmd_params params; |
b07c2db8 | 554 | struct dwc3 *dwc = dep->dwc; |
72246da4 | 555 | |
39ebb05c JY |
556 | comp_desc = dep->endpoint.comp_desc; |
557 | desc = dep->endpoint.desc; | |
558 | ||
72246da4 FB |
559 | memset(¶ms, 0x00, sizeof(params)); |
560 | ||
dc1c70a7 | 561 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
562 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
563 | ||
564 | /* Burst size is only needed in SuperSpeed mode */ | |
ee5cd41c | 565 | if (dwc->gadget.speed >= USB_SPEED_SUPER) { |
676e3497 | 566 | u32 burst = dep->endpoint.maxburst; |
676e3497 | 567 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1); |
d2e9a13a | 568 | } |
72246da4 | 569 | |
a2d23f08 FB |
570 | params.param0 |= action; |
571 | if (action == DWC3_DEPCFG_ACTION_RESTORE) | |
265b70a7 | 572 | params.param2 |= dep->saved_state; |
265b70a7 | 573 | |
4bc48c97 FB |
574 | if (usb_endpoint_xfer_control(desc)) |
575 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN; | |
13fa2e69 FB |
576 | |
577 | if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc)) | |
578 | params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 579 | |
18b7ede5 | 580 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 | 581 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
548f8b31 | 582 | | DWC3_DEPCFG_XFER_COMPLETE_EN |
dc1c70a7 | 583 | | DWC3_DEPCFG_STREAM_EVENT_EN; |
879631aa FB |
584 | dep->stream_capable = true; |
585 | } | |
586 | ||
0b93a4c8 | 587 | if (!usb_endpoint_xfer_control(desc)) |
dc1c70a7 | 588 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
589 | |
590 | /* | |
591 | * We are doing 1:1 mapping for endpoints, meaning | |
592 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
593 | * so on. We consider the direction bit as part of the physical | |
594 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
595 | */ | |
dc1c70a7 | 596 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
597 | |
598 | /* | |
599 | * We must use the lower 16 TX FIFOs even though | |
600 | * HW might have more | |
601 | */ | |
602 | if (dep->direction) | |
dc1c70a7 | 603 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
604 | |
605 | if (desc->bInterval) { | |
dc1c70a7 | 606 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
72246da4 FB |
607 | dep->interval = 1 << (desc->bInterval - 1); |
608 | } | |
609 | ||
2cd4718d | 610 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms); |
72246da4 FB |
611 | } |
612 | ||
140ca4cf TN |
613 | static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, |
614 | bool interrupt); | |
615 | ||
72246da4 | 616 | /** |
bfad65ee | 617 | * __dwc3_gadget_ep_enable - initializes a hw endpoint |
72246da4 | 618 | * @dep: endpoint to be initialized |
a2d23f08 | 619 | * @action: one of INIT, MODIFY or RESTORE |
72246da4 | 620 | * |
bfad65ee FB |
621 | * Caller should take care of locking. Execute all necessary commands to |
622 | * initialize a HW endpoint so it can be used by a gadget driver. | |
72246da4 | 623 | */ |
a2d23f08 | 624 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) |
72246da4 | 625 | { |
39ebb05c | 626 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
72246da4 | 627 | struct dwc3 *dwc = dep->dwc; |
39ebb05c | 628 | |
72246da4 | 629 | u32 reg; |
b09e99ee | 630 | int ret; |
72246da4 FB |
631 | |
632 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
b07c2db8 | 633 | ret = dwc3_gadget_start_config(dep); |
72246da4 FB |
634 | if (ret) |
635 | return ret; | |
636 | } | |
637 | ||
b07c2db8 | 638 | ret = dwc3_gadget_set_ep_config(dep, action); |
72246da4 FB |
639 | if (ret) |
640 | return ret; | |
641 | ||
642 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
643 | struct dwc3_trb *trb_st_hw; |
644 | struct dwc3_trb *trb_link; | |
72246da4 | 645 | |
72246da4 FB |
646 | dep->type = usb_endpoint_type(desc); |
647 | dep->flags |= DWC3_EP_ENABLED; | |
648 | ||
649 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
650 | reg |= DWC3_DALEPENA_EP(dep->number); | |
651 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
652 | ||
36b68aae | 653 | if (usb_endpoint_xfer_control(desc)) |
2870e501 | 654 | goto out; |
72246da4 | 655 | |
0d25744a JY |
656 | /* Initialize the TRB ring */ |
657 | dep->trb_dequeue = 0; | |
658 | dep->trb_enqueue = 0; | |
659 | memset(dep->trb_pool, 0, | |
660 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM); | |
661 | ||
36b68aae | 662 | /* Link TRB. The HWO bit is never reset */ |
72246da4 FB |
663 | trb_st_hw = &dep->trb_pool[0]; |
664 | ||
f6bafc6a | 665 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
f6bafc6a FB |
666 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
667 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
668 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
669 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
670 | } |
671 | ||
a97ea994 FB |
672 | /* |
673 | * Issue StartTransfer here with no-op TRB so we can always rely on No | |
674 | * Response Update Transfer command. | |
675 | */ | |
140ca4cf | 676 | if (usb_endpoint_xfer_bulk(desc) || |
52fcc0be | 677 | usb_endpoint_xfer_int(desc)) { |
a97ea994 FB |
678 | struct dwc3_gadget_ep_cmd_params params; |
679 | struct dwc3_trb *trb; | |
680 | dma_addr_t trb_dma; | |
681 | u32 cmd; | |
682 | ||
683 | memset(¶ms, 0, sizeof(params)); | |
684 | trb = &dep->trb_pool[0]; | |
685 | trb_dma = dwc3_trb_dma_offset(dep, trb); | |
686 | ||
687 | params.param0 = upper_32_bits(trb_dma); | |
688 | params.param1 = lower_32_bits(trb_dma); | |
689 | ||
690 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
691 | ||
692 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
693 | if (ret < 0) | |
694 | return ret; | |
140ca4cf TN |
695 | |
696 | if (dep->stream_capable) { | |
697 | /* | |
698 | * For streams, at start, there maybe a race where the | |
699 | * host primes the endpoint before the function driver | |
700 | * queues a request to initiate a stream. In that case, | |
701 | * the controller will not see the prime to generate the | |
702 | * ERDY and start stream. To workaround this, issue a | |
703 | * no-op TRB as normal, but end it immediately. As a | |
704 | * result, when the function driver queues the request, | |
705 | * the next START_TRANSFER command will cause the | |
706 | * controller to generate an ERDY to initiate the | |
707 | * stream. | |
708 | */ | |
709 | dwc3_stop_active_transfer(dep, true, true); | |
710 | ||
711 | /* | |
712 | * All stream eps will reinitiate stream on NoStream | |
713 | * rejection until we can determine that the host can | |
714 | * prime after the first transfer. | |
715 | */ | |
716 | dep->flags |= DWC3_EP_FORCE_RESTART_STREAM; | |
717 | } | |
a97ea994 FB |
718 | } |
719 | ||
2870e501 FB |
720 | out: |
721 | trace_dwc3_gadget_ep_enable(dep); | |
722 | ||
72246da4 FB |
723 | return 0; |
724 | } | |
725 | ||
624407f9 | 726 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) |
72246da4 FB |
727 | { |
728 | struct dwc3_request *req; | |
729 | ||
c5353b22 | 730 | dwc3_stop_active_transfer(dep, true, false); |
624407f9 | 731 | |
0e146028 FB |
732 | /* - giveback all requests to gadget driver */ |
733 | while (!list_empty(&dep->started_list)) { | |
734 | req = next_request(&dep->started_list); | |
1591633e | 735 | |
0e146028 | 736 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
ea53b882 FB |
737 | } |
738 | ||
aa3342c8 FB |
739 | while (!list_empty(&dep->pending_list)) { |
740 | req = next_request(&dep->pending_list); | |
72246da4 | 741 | |
d8eca64e FB |
742 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
743 | } | |
744 | ||
745 | while (!list_empty(&dep->cancelled_list)) { | |
746 | req = next_request(&dep->cancelled_list); | |
747 | ||
624407f9 | 748 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 749 | } |
72246da4 FB |
750 | } |
751 | ||
752 | /** | |
bfad65ee | 753 | * __dwc3_gadget_ep_disable - disables a hw endpoint |
72246da4 FB |
754 | * @dep: the endpoint to disable |
755 | * | |
bfad65ee FB |
756 | * This function undoes what __dwc3_gadget_ep_enable did and also removes |
757 | * requests which are currently being processed by the hardware and those which | |
758 | * are not yet scheduled. | |
759 | * | |
624407f9 | 760 | * Caller should take care of locking. |
72246da4 | 761 | */ |
72246da4 FB |
762 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
763 | { | |
764 | struct dwc3 *dwc = dep->dwc; | |
765 | u32 reg; | |
766 | ||
2870e501 | 767 | trace_dwc3_gadget_ep_disable(dep); |
7eaeac5c | 768 | |
624407f9 | 769 | dwc3_remove_requests(dwc, dep); |
72246da4 | 770 | |
687ef981 FB |
771 | /* make sure HW endpoint isn't stalled */ |
772 | if (dep->flags & DWC3_EP_STALL) | |
7a608559 | 773 | __dwc3_gadget_ep_set_halt(dep, 0, false); |
687ef981 | 774 | |
72246da4 FB |
775 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
776 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
777 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
778 | ||
879631aa | 779 | dep->stream_capable = false; |
72246da4 | 780 | dep->type = 0; |
3aec9915 | 781 | dep->flags = 0; |
72246da4 | 782 | |
39ebb05c JY |
783 | /* Clear out the ep descriptors for non-ep0 */ |
784 | if (dep->number > 1) { | |
785 | dep->endpoint.comp_desc = NULL; | |
786 | dep->endpoint.desc = NULL; | |
787 | } | |
788 | ||
72246da4 FB |
789 | return 0; |
790 | } | |
791 | ||
792 | /* -------------------------------------------------------------------------- */ | |
793 | ||
794 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
795 | const struct usb_endpoint_descriptor *desc) | |
796 | { | |
797 | return -EINVAL; | |
798 | } | |
799 | ||
800 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
801 | { | |
802 | return -EINVAL; | |
803 | } | |
804 | ||
805 | /* -------------------------------------------------------------------------- */ | |
806 | ||
807 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
808 | const struct usb_endpoint_descriptor *desc) | |
809 | { | |
810 | struct dwc3_ep *dep; | |
811 | struct dwc3 *dwc; | |
812 | unsigned long flags; | |
813 | int ret; | |
814 | ||
815 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
816 | pr_debug("dwc3: invalid parameters\n"); | |
817 | return -EINVAL; | |
818 | } | |
819 | ||
820 | if (!desc->wMaxPacketSize) { | |
821 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
822 | return -EINVAL; | |
823 | } | |
824 | ||
825 | dep = to_dwc3_ep(ep); | |
826 | dwc = dep->dwc; | |
827 | ||
95ca961c FB |
828 | if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED, |
829 | "%s is already enabled\n", | |
830 | dep->name)) | |
c6f83f38 | 831 | return 0; |
c6f83f38 | 832 | |
72246da4 | 833 | spin_lock_irqsave(&dwc->lock, flags); |
a2d23f08 | 834 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
835 | spin_unlock_irqrestore(&dwc->lock, flags); |
836 | ||
837 | return ret; | |
838 | } | |
839 | ||
840 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
841 | { | |
842 | struct dwc3_ep *dep; | |
843 | struct dwc3 *dwc; | |
844 | unsigned long flags; | |
845 | int ret; | |
846 | ||
847 | if (!ep) { | |
848 | pr_debug("dwc3: invalid parameters\n"); | |
849 | return -EINVAL; | |
850 | } | |
851 | ||
852 | dep = to_dwc3_ep(ep); | |
853 | dwc = dep->dwc; | |
854 | ||
95ca961c FB |
855 | if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED), |
856 | "%s is already disabled\n", | |
857 | dep->name)) | |
72246da4 | 858 | return 0; |
72246da4 | 859 | |
72246da4 FB |
860 | spin_lock_irqsave(&dwc->lock, flags); |
861 | ret = __dwc3_gadget_ep_disable(dep); | |
862 | spin_unlock_irqrestore(&dwc->lock, flags); | |
863 | ||
864 | return ret; | |
865 | } | |
866 | ||
867 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
0bd0f6d2 | 868 | gfp_t gfp_flags) |
72246da4 FB |
869 | { |
870 | struct dwc3_request *req; | |
871 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
72246da4 FB |
872 | |
873 | req = kzalloc(sizeof(*req), gfp_flags); | |
734d5a53 | 874 | if (!req) |
72246da4 | 875 | return NULL; |
72246da4 | 876 | |
31a2f5a7 | 877 | req->direction = dep->direction; |
72246da4 FB |
878 | req->epnum = dep->number; |
879 | req->dep = dep; | |
a3af5e3a | 880 | req->status = DWC3_REQUEST_STATUS_UNKNOWN; |
72246da4 | 881 | |
2c4cbe6e FB |
882 | trace_dwc3_alloc_request(req); |
883 | ||
72246da4 FB |
884 | return &req->request; |
885 | } | |
886 | ||
887 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
888 | struct usb_request *request) | |
889 | { | |
890 | struct dwc3_request *req = to_dwc3_request(request); | |
891 | ||
2c4cbe6e | 892 | trace_dwc3_free_request(req); |
72246da4 FB |
893 | kfree(req); |
894 | } | |
895 | ||
42626919 FB |
896 | /** |
897 | * dwc3_ep_prev_trb - returns the previous TRB in the ring | |
898 | * @dep: The endpoint with the TRB ring | |
899 | * @index: The index of the current TRB in the ring | |
900 | * | |
901 | * Returns the TRB prior to the one pointed to by the index. If the | |
902 | * index is 0, we will wrap backwards, skip the link TRB, and return | |
903 | * the one just before that. | |
904 | */ | |
905 | static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index) | |
906 | { | |
907 | u8 tmp = index; | |
908 | ||
909 | if (!tmp) | |
910 | tmp = DWC3_TRB_NUM - 1; | |
911 | ||
912 | return &dep->trb_pool[tmp - 1]; | |
913 | } | |
914 | ||
915 | static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep) | |
916 | { | |
917 | struct dwc3_trb *tmp; | |
918 | u8 trbs_left; | |
919 | ||
920 | /* | |
921 | * If enqueue & dequeue are equal than it is either full or empty. | |
922 | * | |
923 | * One way to know for sure is if the TRB right before us has HWO bit | |
924 | * set or not. If it has, then we're definitely full and can't fit any | |
925 | * more transfers in our ring. | |
926 | */ | |
927 | if (dep->trb_enqueue == dep->trb_dequeue) { | |
928 | tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue); | |
929 | if (tmp->ctrl & DWC3_TRB_CTRL_HWO) | |
930 | return 0; | |
931 | ||
932 | return DWC3_TRB_NUM - 1; | |
933 | } | |
934 | ||
935 | trbs_left = dep->trb_dequeue - dep->trb_enqueue; | |
936 | trbs_left &= (DWC3_TRB_NUM - 1); | |
937 | ||
938 | if (dep->trb_dequeue < dep->trb_enqueue) | |
939 | trbs_left--; | |
940 | ||
941 | return trbs_left; | |
942 | } | |
2c78c029 | 943 | |
e49d3cf4 FB |
944 | static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb, |
945 | dma_addr_t dma, unsigned length, unsigned chain, unsigned node, | |
3eaecd0c TN |
946 | unsigned stream_id, unsigned short_not_ok, |
947 | unsigned no_interrupt, unsigned is_last) | |
c71fc37c | 948 | { |
6b9018d4 FB |
949 | struct dwc3 *dwc = dep->dwc; |
950 | struct usb_gadget *gadget = &dwc->gadget; | |
951 | enum usb_device_speed speed = gadget->speed; | |
c71fc37c | 952 | |
f6bafc6a FB |
953 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
954 | trb->bpl = lower_32_bits(dma); | |
955 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 956 | |
16e78db7 | 957 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 958 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 959 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
960 | break; |
961 | ||
962 | case USB_ENDPOINT_XFER_ISOC: | |
6b9018d4 | 963 | if (!node) { |
e5ba5ec8 | 964 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; |
6b9018d4 | 965 | |
40d829fb MG |
966 | /* |
967 | * USB Specification 2.0 Section 5.9.2 states that: "If | |
968 | * there is only a single transaction in the microframe, | |
969 | * only a DATA0 data packet PID is used. If there are | |
970 | * two transactions per microframe, DATA1 is used for | |
971 | * the first transaction data packet and DATA0 is used | |
972 | * for the second transaction data packet. If there are | |
973 | * three transactions per microframe, DATA2 is used for | |
974 | * the first transaction data packet, DATA1 is used for | |
975 | * the second, and DATA0 is used for the third." | |
976 | * | |
977 | * IOW, we should satisfy the following cases: | |
978 | * | |
979 | * 1) length <= maxpacket | |
980 | * - DATA0 | |
981 | * | |
982 | * 2) maxpacket < length <= (2 * maxpacket) | |
983 | * - DATA1, DATA0 | |
984 | * | |
985 | * 3) (2 * maxpacket) < length <= (3 * maxpacket) | |
986 | * - DATA2, DATA1, DATA0 | |
987 | */ | |
6b9018d4 FB |
988 | if (speed == USB_SPEED_HIGH) { |
989 | struct usb_ep *ep = &dep->endpoint; | |
ec5bb87e | 990 | unsigned int mult = 2; |
40d829fb MG |
991 | unsigned int maxp = usb_endpoint_maxp(ep->desc); |
992 | ||
993 | if (length <= (2 * maxp)) | |
994 | mult--; | |
995 | ||
996 | if (length <= maxp) | |
997 | mult--; | |
998 | ||
999 | trb->size |= DWC3_TRB_SIZE_PCM1(mult); | |
6b9018d4 FB |
1000 | } |
1001 | } else { | |
e5ba5ec8 | 1002 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; |
6b9018d4 | 1003 | } |
ca4d44ea FB |
1004 | |
1005 | /* always enable Interrupt on Missed ISOC */ | |
1006 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; | |
c71fc37c FB |
1007 | break; |
1008 | ||
1009 | case USB_ENDPOINT_XFER_BULK: | |
1010 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 1011 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
1012 | break; |
1013 | default: | |
1014 | /* | |
1015 | * This is only possible with faulty memory because we | |
1016 | * checked it already :) | |
1017 | */ | |
0a695d4c FB |
1018 | dev_WARN(dwc->dev, "Unknown endpoint type %d\n", |
1019 | usb_endpoint_type(dep->endpoint.desc)); | |
c71fc37c FB |
1020 | } |
1021 | ||
244add8e TJ |
1022 | /* |
1023 | * Enable Continue on Short Packet | |
1024 | * when endpoint is not a stream capable | |
1025 | */ | |
c9508c8c | 1026 | if (usb_endpoint_dir_out(dep->endpoint.desc)) { |
244add8e TJ |
1027 | if (!dep->stream_capable) |
1028 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
f3af3651 | 1029 | |
e49d3cf4 | 1030 | if (short_not_ok) |
c9508c8c FB |
1031 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; |
1032 | } | |
1033 | ||
e49d3cf4 | 1034 | if ((!no_interrupt && !chain) || |
b7a4fbe2 | 1035 | (dwc3_calc_trbs_left(dep) == 1)) |
c9508c8c | 1036 | trb->ctrl |= DWC3_TRB_CTRL_IOC; |
f3af3651 | 1037 | |
e5ba5ec8 PA |
1038 | if (chain) |
1039 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
3eaecd0c TN |
1040 | else if (dep->stream_capable && is_last) |
1041 | trb->ctrl |= DWC3_TRB_CTRL_LST; | |
e5ba5ec8 | 1042 | |
16e78db7 | 1043 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
e49d3cf4 | 1044 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id); |
c71fc37c | 1045 | |
f6bafc6a | 1046 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
2c4cbe6e | 1047 | |
b7a4fbe2 AKV |
1048 | dwc3_ep_inc_enq(dep); |
1049 | ||
2c4cbe6e | 1050 | trace_dwc3_prepare_trb(dep, trb); |
c71fc37c FB |
1051 | } |
1052 | ||
e49d3cf4 FB |
1053 | /** |
1054 | * dwc3_prepare_one_trb - setup one TRB from one request | |
1055 | * @dep: endpoint for which this request is prepared | |
1056 | * @req: dwc3_request pointer | |
1057 | * @chain: should this TRB be chained to the next? | |
1058 | * @node: only for isochronous endpoints. First TRB needs different type. | |
1059 | */ | |
1060 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, | |
1061 | struct dwc3_request *req, unsigned chain, unsigned node) | |
1062 | { | |
1063 | struct dwc3_trb *trb; | |
a31e63b6 AKV |
1064 | unsigned int length; |
1065 | dma_addr_t dma; | |
e49d3cf4 FB |
1066 | unsigned stream_id = req->request.stream_id; |
1067 | unsigned short_not_ok = req->request.short_not_ok; | |
1068 | unsigned no_interrupt = req->request.no_interrupt; | |
3eaecd0c | 1069 | unsigned is_last = req->request.is_last; |
a31e63b6 AKV |
1070 | |
1071 | if (req->request.num_sgs > 0) { | |
1072 | length = sg_dma_len(req->start_sg); | |
1073 | dma = sg_dma_address(req->start_sg); | |
1074 | } else { | |
1075 | length = req->request.length; | |
1076 | dma = req->request.dma; | |
1077 | } | |
e49d3cf4 FB |
1078 | |
1079 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
1080 | ||
1081 | if (!req->trb) { | |
1082 | dwc3_gadget_move_started_request(req); | |
1083 | req->trb = trb; | |
1084 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
e49d3cf4 FB |
1085 | } |
1086 | ||
09fe1f8d FB |
1087 | req->num_trbs++; |
1088 | ||
e49d3cf4 | 1089 | __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node, |
3eaecd0c | 1090 | stream_id, short_not_ok, no_interrupt, is_last); |
e49d3cf4 FB |
1091 | } |
1092 | ||
5ee85d89 | 1093 | static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep, |
7ae7df49 | 1094 | struct dwc3_request *req) |
5ee85d89 | 1095 | { |
a31e63b6 | 1096 | struct scatterlist *sg = req->start_sg; |
5ee85d89 | 1097 | struct scatterlist *s; |
5ee85d89 FB |
1098 | int i; |
1099 | ||
c96e6725 AKV |
1100 | unsigned int remaining = req->request.num_mapped_sgs |
1101 | - req->num_queued_sgs; | |
1102 | ||
1103 | for_each_sg(sg, s, remaining, i) { | |
c6267a51 FB |
1104 | unsigned int length = req->request.length; |
1105 | unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc); | |
1106 | unsigned int rem = length % maxp; | |
5ee85d89 FB |
1107 | unsigned chain = true; |
1108 | ||
dad2aff3 PP |
1109 | /* |
1110 | * IOMMU driver is coalescing the list of sgs which shares a | |
1111 | * page boundary into one and giving it to USB driver. With | |
1112 | * this the number of sgs mapped is not equal to the number of | |
1113 | * sgs passed. So mark the chain bit to false if it isthe last | |
1114 | * mapped sg. | |
1115 | */ | |
1116 | if (i == remaining - 1) | |
5ee85d89 FB |
1117 | chain = false; |
1118 | ||
c6267a51 FB |
1119 | if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) { |
1120 | struct dwc3 *dwc = dep->dwc; | |
1121 | struct dwc3_trb *trb; | |
1122 | ||
1a22ec64 | 1123 | req->needs_extra_trb = true; |
c6267a51 FB |
1124 | |
1125 | /* prepare normal TRB */ | |
1126 | dwc3_prepare_one_trb(dep, req, true, i); | |
1127 | ||
1128 | /* Now prepare one extra TRB to align transfer size */ | |
1129 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
09fe1f8d | 1130 | req->num_trbs++; |
c6267a51 | 1131 | __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, |
2fc6d4be | 1132 | maxp - rem, false, 1, |
c6267a51 FB |
1133 | req->request.stream_id, |
1134 | req->request.short_not_ok, | |
3eaecd0c TN |
1135 | req->request.no_interrupt, |
1136 | req->request.is_last); | |
c6267a51 FB |
1137 | } else { |
1138 | dwc3_prepare_one_trb(dep, req, chain, i); | |
1139 | } | |
5ee85d89 | 1140 | |
a31e63b6 AKV |
1141 | /* |
1142 | * There can be a situation where all sgs in sglist are not | |
1143 | * queued because of insufficient trb number. To handle this | |
1144 | * case, update start_sg to next sg to be queued, so that | |
1145 | * we have free trbs we can continue queuing from where we | |
1146 | * previously stopped | |
1147 | */ | |
1148 | if (chain) | |
1149 | req->start_sg = sg_next(s); | |
1150 | ||
c96e6725 AKV |
1151 | req->num_queued_sgs++; |
1152 | ||
7ae7df49 | 1153 | if (!dwc3_calc_trbs_left(dep)) |
5ee85d89 FB |
1154 | break; |
1155 | } | |
1156 | } | |
1157 | ||
1158 | static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep, | |
7ae7df49 | 1159 | struct dwc3_request *req) |
5ee85d89 | 1160 | { |
c6267a51 FB |
1161 | unsigned int length = req->request.length; |
1162 | unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc); | |
1163 | unsigned int rem = length % maxp; | |
1164 | ||
1e19cdc8 | 1165 | if ((!length || rem) && usb_endpoint_dir_out(dep->endpoint.desc)) { |
c6267a51 FB |
1166 | struct dwc3 *dwc = dep->dwc; |
1167 | struct dwc3_trb *trb; | |
1168 | ||
1a22ec64 | 1169 | req->needs_extra_trb = true; |
c6267a51 FB |
1170 | |
1171 | /* prepare normal TRB */ | |
1172 | dwc3_prepare_one_trb(dep, req, true, 0); | |
1173 | ||
1174 | /* Now prepare one extra TRB to align transfer size */ | |
1175 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
09fe1f8d | 1176 | req->num_trbs++; |
c6267a51 | 1177 | __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem, |
2fc6d4be | 1178 | false, 1, req->request.stream_id, |
c6267a51 | 1179 | req->request.short_not_ok, |
3eaecd0c TN |
1180 | req->request.no_interrupt, |
1181 | req->request.is_last); | |
d6e5a549 | 1182 | } else if (req->request.zero && req->request.length && |
4ea438da | 1183 | (IS_ALIGNED(req->request.length, maxp))) { |
d6e5a549 FB |
1184 | struct dwc3 *dwc = dep->dwc; |
1185 | struct dwc3_trb *trb; | |
1186 | ||
1a22ec64 | 1187 | req->needs_extra_trb = true; |
d6e5a549 FB |
1188 | |
1189 | /* prepare normal TRB */ | |
1190 | dwc3_prepare_one_trb(dep, req, true, 0); | |
1191 | ||
1192 | /* Now prepare one extra TRB to handle ZLP */ | |
1193 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
09fe1f8d | 1194 | req->num_trbs++; |
d6e5a549 | 1195 | __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0, |
2fc6d4be | 1196 | false, 1, req->request.stream_id, |
d6e5a549 | 1197 | req->request.short_not_ok, |
3eaecd0c TN |
1198 | req->request.no_interrupt, |
1199 | req->request.is_last); | |
c6267a51 FB |
1200 | } else { |
1201 | dwc3_prepare_one_trb(dep, req, false, 0); | |
1202 | } | |
5ee85d89 FB |
1203 | } |
1204 | ||
72246da4 FB |
1205 | /* |
1206 | * dwc3_prepare_trbs - setup TRBs from requests | |
1207 | * @dep: endpoint for which requests are being prepared | |
72246da4 | 1208 | * |
1d046793 PZ |
1209 | * The function goes through the requests list and sets up TRBs for the |
1210 | * transfers. The function returns once there are no more TRBs available or | |
1211 | * it runs out of requests. | |
72246da4 | 1212 | */ |
c4233573 | 1213 | static void dwc3_prepare_trbs(struct dwc3_ep *dep) |
72246da4 | 1214 | { |
68e823e2 | 1215 | struct dwc3_request *req, *n; |
72246da4 FB |
1216 | |
1217 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
1218 | ||
d86c5a67 FB |
1219 | /* |
1220 | * We can get in a situation where there's a request in the started list | |
1221 | * but there weren't enough TRBs to fully kick it in the first time | |
1222 | * around, so it has been waiting for more TRBs to be freed up. | |
1223 | * | |
1224 | * In that case, we should check if we have a request with pending_sgs | |
1225 | * in the started list and prepare TRBs for that request first, | |
1226 | * otherwise we will prepare TRBs completely out of order and that will | |
1227 | * break things. | |
1228 | */ | |
1229 | list_for_each_entry(req, &dep->started_list, list) { | |
1230 | if (req->num_pending_sgs > 0) | |
1231 | dwc3_prepare_one_trb_sg(dep, req); | |
1232 | ||
1233 | if (!dwc3_calc_trbs_left(dep)) | |
1234 | return; | |
63c7bb29 TN |
1235 | |
1236 | /* | |
1237 | * Don't prepare beyond a transfer. In DWC_usb32, its transfer | |
1238 | * burst capability may try to read and use TRBs beyond the | |
1239 | * active transfer instead of stopping. | |
1240 | */ | |
1241 | if (dep->stream_capable && req->request.is_last) | |
1242 | return; | |
d86c5a67 FB |
1243 | } |
1244 | ||
aa3342c8 | 1245 | list_for_each_entry_safe(req, n, &dep->pending_list, list) { |
cdb55b39 FB |
1246 | struct dwc3 *dwc = dep->dwc; |
1247 | int ret; | |
1248 | ||
1249 | ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request, | |
1250 | dep->direction); | |
1251 | if (ret) | |
1252 | return; | |
1253 | ||
1254 | req->sg = req->request.sg; | |
a31e63b6 | 1255 | req->start_sg = req->sg; |
c96e6725 | 1256 | req->num_queued_sgs = 0; |
cdb55b39 FB |
1257 | req->num_pending_sgs = req->request.num_mapped_sgs; |
1258 | ||
1f512119 | 1259 | if (req->num_pending_sgs > 0) |
7ae7df49 | 1260 | dwc3_prepare_one_trb_sg(dep, req); |
5ee85d89 | 1261 | else |
7ae7df49 | 1262 | dwc3_prepare_one_trb_linear(dep, req); |
72246da4 | 1263 | |
7ae7df49 | 1264 | if (!dwc3_calc_trbs_left(dep)) |
5ee85d89 | 1265 | return; |
aefe3d23 TN |
1266 | |
1267 | /* | |
1268 | * Don't prepare beyond a transfer. In DWC_usb32, its transfer | |
1269 | * burst capability may try to read and use TRBs beyond the | |
1270 | * active transfer instead of stopping. | |
1271 | */ | |
1272 | if (dep->stream_capable && req->request.is_last) | |
1273 | return; | |
72246da4 | 1274 | } |
72246da4 FB |
1275 | } |
1276 | ||
8d99087c TN |
1277 | static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep); |
1278 | ||
7fdca766 | 1279 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep) |
72246da4 FB |
1280 | { |
1281 | struct dwc3_gadget_ep_cmd_params params; | |
1282 | struct dwc3_request *req; | |
4fae2e3e | 1283 | int starting; |
72246da4 FB |
1284 | int ret; |
1285 | u32 cmd; | |
1286 | ||
ccb94ebf FB |
1287 | if (!dwc3_calc_trbs_left(dep)) |
1288 | return 0; | |
1289 | ||
1912cbc6 | 1290 | starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED); |
72246da4 | 1291 | |
4fae2e3e FB |
1292 | dwc3_prepare_trbs(dep); |
1293 | req = next_request(&dep->started_list); | |
72246da4 FB |
1294 | if (!req) { |
1295 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
1296 | return 0; | |
1297 | } | |
1298 | ||
1299 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 1300 | |
4fae2e3e | 1301 | if (starting) { |
1877d6c9 PA |
1302 | params.param0 = upper_32_bits(req->trb_dma); |
1303 | params.param1 = lower_32_bits(req->trb_dma); | |
7fdca766 FB |
1304 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
1305 | ||
a7351807 AKV |
1306 | if (dep->stream_capable) |
1307 | cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id); | |
1308 | ||
7fdca766 FB |
1309 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
1310 | cmd |= DWC3_DEPCMD_PARAM(dep->frame_number); | |
1877d6c9 | 1311 | } else { |
b6b1c6db FB |
1312 | cmd = DWC3_DEPCMD_UPDATETRANSFER | |
1313 | DWC3_DEPCMD_PARAM(dep->resource_index); | |
1877d6c9 | 1314 | } |
72246da4 | 1315 | |
2cd4718d | 1316 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
72246da4 | 1317 | if (ret < 0) { |
8d99087c TN |
1318 | struct dwc3_request *tmp; |
1319 | ||
1320 | if (ret == -EAGAIN) | |
1321 | return ret; | |
1322 | ||
1323 | dwc3_stop_active_transfer(dep, true, true); | |
1324 | ||
1325 | list_for_each_entry_safe(req, tmp, &dep->started_list, list) | |
1326 | dwc3_gadget_move_cancelled_request(req); | |
1327 | ||
1328 | /* If ep isn't started, then there's no end transfer pending */ | |
1329 | if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING)) | |
1330 | dwc3_gadget_ep_cleanup_cancelled_requests(dep); | |
1331 | ||
72246da4 FB |
1332 | return ret; |
1333 | } | |
1334 | ||
e0d19563 TN |
1335 | if (dep->stream_capable && req->request.is_last) |
1336 | dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE; | |
1337 | ||
72246da4 FB |
1338 | return 0; |
1339 | } | |
1340 | ||
6cb2e4e3 FB |
1341 | static int __dwc3_gadget_get_frame(struct dwc3 *dwc) |
1342 | { | |
1343 | u32 reg; | |
1344 | ||
1345 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1346 | return DWC3_DSTS_SOFFN(reg); | |
1347 | } | |
1348 | ||
d92021f6 TN |
1349 | /** |
1350 | * dwc3_gadget_start_isoc_quirk - workaround invalid frame number | |
1351 | * @dep: isoc endpoint | |
1352 | * | |
1353 | * This function tests for the correct combination of BIT[15:14] from the 16-bit | |
1354 | * microframe number reported by the XferNotReady event for the future frame | |
1355 | * number to start the isoc transfer. | |
1356 | * | |
1357 | * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed | |
1358 | * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the | |
1359 | * XferNotReady event are invalid. The driver uses this number to schedule the | |
1360 | * isochronous transfer and passes it to the START TRANSFER command. Because | |
1361 | * this number is invalid, the command may fail. If BIT[15:14] matches the | |
1362 | * internal 16-bit microframe, the START TRANSFER command will pass and the | |
1363 | * transfer will start at the scheduled time, if it is off by 1, the command | |
1364 | * will still pass, but the transfer will start 2 seconds in the future. For all | |
1365 | * other conditions, the START TRANSFER command will fail with bus-expiry. | |
1366 | * | |
1367 | * In order to workaround this issue, we can test for the correct combination of | |
1368 | * BIT[15:14] by sending START TRANSFER commands with different values of | |
1369 | * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart | |
1370 | * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status. | |
1371 | * As the result, within the 4 possible combinations for BIT[15:14], there will | |
1372 | * be 2 successful and 2 failure START COMMAND status. One of the 2 successful | |
1373 | * command status will result in a 2-second delay start. The smaller BIT[15:14] | |
1374 | * value is the correct combination. | |
1375 | * | |
1376 | * Since there are only 4 outcomes and the results are ordered, we can simply | |
1377 | * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to | |
1378 | * deduce the smaller successful combination. | |
1379 | * | |
1380 | * Let test0 = test status for combination 'b00 and test1 = test status for 'b01 | |
1381 | * of BIT[15:14]. The correct combination is as follow: | |
1382 | * | |
1383 | * if test0 fails and test1 passes, BIT[15:14] is 'b01 | |
1384 | * if test0 fails and test1 fails, BIT[15:14] is 'b10 | |
1385 | * if test0 passes and test1 fails, BIT[15:14] is 'b11 | |
1386 | * if test0 passes and test1 passes, BIT[15:14] is 'b00 | |
1387 | * | |
1388 | * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN | |
1389 | * endpoints. | |
1390 | */ | |
25abad6a | 1391 | static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep) |
d92021f6 TN |
1392 | { |
1393 | int cmd_status = 0; | |
1394 | bool test0; | |
1395 | bool test1; | |
1396 | ||
1397 | while (dep->combo_num < 2) { | |
1398 | struct dwc3_gadget_ep_cmd_params params; | |
1399 | u32 test_frame_number; | |
1400 | u32 cmd; | |
1401 | ||
1402 | /* | |
1403 | * Check if we can start isoc transfer on the next interval or | |
1404 | * 4 uframes in the future with BIT[15:14] as dep->combo_num | |
1405 | */ | |
ca143785 | 1406 | test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK; |
d92021f6 TN |
1407 | test_frame_number |= dep->combo_num << 14; |
1408 | test_frame_number += max_t(u32, 4, dep->interval); | |
1409 | ||
1410 | params.param0 = upper_32_bits(dep->dwc->bounce_addr); | |
1411 | params.param1 = lower_32_bits(dep->dwc->bounce_addr); | |
1412 | ||
1413 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
1414 | cmd |= DWC3_DEPCMD_PARAM(test_frame_number); | |
1415 | cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
1416 | ||
1417 | /* Redo if some other failure beside bus-expiry is received */ | |
1418 | if (cmd_status && cmd_status != -EAGAIN) { | |
1419 | dep->start_cmd_status = 0; | |
1420 | dep->combo_num = 0; | |
25abad6a | 1421 | return 0; |
d92021f6 TN |
1422 | } |
1423 | ||
1424 | /* Store the first test status */ | |
1425 | if (dep->combo_num == 0) | |
1426 | dep->start_cmd_status = cmd_status; | |
1427 | ||
1428 | dep->combo_num++; | |
1429 | ||
1430 | /* | |
1431 | * End the transfer if the START_TRANSFER command is successful | |
1432 | * to wait for the next XferNotReady to test the command again | |
1433 | */ | |
1434 | if (cmd_status == 0) { | |
c5353b22 | 1435 | dwc3_stop_active_transfer(dep, true, true); |
25abad6a | 1436 | return 0; |
d92021f6 TN |
1437 | } |
1438 | } | |
1439 | ||
1440 | /* test0 and test1 are both completed at this point */ | |
1441 | test0 = (dep->start_cmd_status == 0); | |
1442 | test1 = (cmd_status == 0); | |
1443 | ||
1444 | if (!test0 && test1) | |
1445 | dep->combo_num = 1; | |
1446 | else if (!test0 && !test1) | |
1447 | dep->combo_num = 2; | |
1448 | else if (test0 && !test1) | |
1449 | dep->combo_num = 3; | |
1450 | else if (test0 && test1) | |
1451 | dep->combo_num = 0; | |
1452 | ||
ca143785 | 1453 | dep->frame_number &= DWC3_FRNUMBER_MASK; |
d92021f6 TN |
1454 | dep->frame_number |= dep->combo_num << 14; |
1455 | dep->frame_number += max_t(u32, 4, dep->interval); | |
1456 | ||
1457 | /* Reinitialize test variables */ | |
1458 | dep->start_cmd_status = 0; | |
1459 | dep->combo_num = 0; | |
1460 | ||
25abad6a | 1461 | return __dwc3_gadget_kick_transfer(dep); |
d92021f6 TN |
1462 | } |
1463 | ||
25abad6a | 1464 | static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep) |
d6d6ec7b | 1465 | { |
d92021f6 | 1466 | struct dwc3 *dwc = dep->dwc; |
d5370106 FB |
1467 | int ret; |
1468 | int i; | |
d92021f6 | 1469 | |
36f05d36 TN |
1470 | if (list_empty(&dep->pending_list) && |
1471 | list_empty(&dep->started_list)) { | |
f4a53c55 | 1472 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
25abad6a | 1473 | return -EAGAIN; |
d6d6ec7b PA |
1474 | } |
1475 | ||
9af21dd6 TN |
1476 | if (!dwc->dis_start_transfer_quirk && |
1477 | (DWC3_VER_IS_PRIOR(DWC31, 170A) || | |
1478 | DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) { | |
25abad6a FB |
1479 | if (dwc->gadget.speed <= USB_SPEED_HIGH && dep->direction) |
1480 | return dwc3_gadget_start_isoc_quirk(dep); | |
d6d6ec7b PA |
1481 | } |
1482 | ||
d5370106 FB |
1483 | for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) { |
1484 | dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1); | |
1485 | ||
1486 | ret = __dwc3_gadget_kick_transfer(dep); | |
1487 | if (ret != -EAGAIN) | |
1488 | break; | |
1489 | } | |
1490 | ||
36f05d36 TN |
1491 | /* |
1492 | * After a number of unsuccessful start attempts due to bus-expiry | |
1493 | * status, issue END_TRANSFER command and retry on the next XferNotReady | |
1494 | * event. | |
1495 | */ | |
1496 | if (ret == -EAGAIN) { | |
1497 | struct dwc3_gadget_ep_cmd_params params; | |
1498 | u32 cmd; | |
1499 | ||
1500 | cmd = DWC3_DEPCMD_ENDTRANSFER | | |
1501 | DWC3_DEPCMD_CMDIOC | | |
1502 | DWC3_DEPCMD_PARAM(dep->resource_index); | |
1503 | ||
1504 | dep->resource_index = 0; | |
1505 | memset(¶ms, 0, sizeof(params)); | |
1506 | ||
1507 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
1508 | if (!ret) | |
1509 | dep->flags |= DWC3_EP_END_TRANSFER_PENDING; | |
1510 | } | |
1511 | ||
d5370106 | 1512 | return ret; |
d6d6ec7b PA |
1513 | } |
1514 | ||
72246da4 FB |
1515 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1516 | { | |
0fc9a1be | 1517 | struct dwc3 *dwc = dep->dwc; |
0fc9a1be | 1518 | |
bb423984 | 1519 | if (!dep->endpoint.desc) { |
5eb30ced FB |
1520 | dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", |
1521 | dep->name); | |
bb423984 FB |
1522 | return -ESHUTDOWN; |
1523 | } | |
1524 | ||
04fb365c FB |
1525 | if (WARN(req->dep != dep, "request %pK belongs to '%s'\n", |
1526 | &req->request, req->dep->name)) | |
bb423984 | 1527 | return -EINVAL; |
bb423984 | 1528 | |
b2b6d601 FB |
1529 | if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED, |
1530 | "%s: request %pK already in flight\n", | |
1531 | dep->name, &req->request)) | |
1532 | return -EINVAL; | |
1533 | ||
fc8bb91b FB |
1534 | pm_runtime_get(dwc->dev); |
1535 | ||
72246da4 FB |
1536 | req->request.actual = 0; |
1537 | req->request.status = -EINPROGRESS; | |
72246da4 | 1538 | |
fe84f522 FB |
1539 | trace_dwc3_ep_queue(req); |
1540 | ||
aa3342c8 | 1541 | list_add_tail(&req->list, &dep->pending_list); |
a3af5e3a | 1542 | req->status = DWC3_REQUEST_STATUS_QUEUED; |
72246da4 | 1543 | |
e0d19563 TN |
1544 | if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE) |
1545 | return 0; | |
1546 | ||
da10bcdd TN |
1547 | /* Start the transfer only after the END_TRANSFER is completed */ |
1548 | if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) { | |
1549 | dep->flags |= DWC3_EP_DELAY_START; | |
1550 | return 0; | |
1551 | } | |
1552 | ||
d889c23c FB |
1553 | /* |
1554 | * NOTICE: Isochronous endpoints should NEVER be prestarted. We must | |
1555 | * wait for a XferNotReady event so we will know what's the current | |
1556 | * (micro-)frame number. | |
1557 | * | |
1558 | * Without this trick, we are very, very likely gonna get Bus Expiry | |
1559 | * errors which will force us issue EndTransfer command. | |
1560 | */ | |
1561 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
fe990cea FB |
1562 | if (!(dep->flags & DWC3_EP_PENDING_REQUEST) && |
1563 | !(dep->flags & DWC3_EP_TRANSFER_STARTED)) | |
1564 | return 0; | |
1565 | ||
6cb2e4e3 | 1566 | if ((dep->flags & DWC3_EP_PENDING_REQUEST)) { |
fe990cea | 1567 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) { |
25abad6a | 1568 | return __dwc3_gadget_start_isoc(dep); |
6cb2e4e3 | 1569 | } |
08a36b54 | 1570 | } |
64e01080 | 1571 | } |
b997ada5 | 1572 | |
7fdca766 | 1573 | return __dwc3_gadget_kick_transfer(dep); |
72246da4 FB |
1574 | } |
1575 | ||
1576 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, | |
1577 | gfp_t gfp_flags) | |
1578 | { | |
1579 | struct dwc3_request *req = to_dwc3_request(request); | |
1580 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1581 | struct dwc3 *dwc = dep->dwc; | |
1582 | ||
1583 | unsigned long flags; | |
1584 | ||
1585 | int ret; | |
1586 | ||
fdee4eba | 1587 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1588 | ret = __dwc3_gadget_ep_queue(dep, req); |
1589 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1590 | ||
1591 | return ret; | |
1592 | } | |
1593 | ||
7746a8df FB |
1594 | static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req) |
1595 | { | |
1596 | int i; | |
1597 | ||
cb11ea56 TN |
1598 | /* If req->trb is not set, then the request has not started */ |
1599 | if (!req->trb) | |
1600 | return; | |
1601 | ||
7746a8df FB |
1602 | /* |
1603 | * If request was already started, this means we had to | |
1604 | * stop the transfer. With that we also need to ignore | |
1605 | * all TRBs used by the request, however TRBs can only | |
1606 | * be modified after completion of END_TRANSFER | |
1607 | * command. So what we do here is that we wait for | |
1608 | * END_TRANSFER completion and only after that, we jump | |
1609 | * over TRBs by clearing HWO and incrementing dequeue | |
1610 | * pointer. | |
1611 | */ | |
1612 | for (i = 0; i < req->num_trbs; i++) { | |
1613 | struct dwc3_trb *trb; | |
1614 | ||
2dedea03 | 1615 | trb = &dep->trb_pool[dep->trb_dequeue]; |
7746a8df FB |
1616 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; |
1617 | dwc3_ep_inc_deq(dep); | |
1618 | } | |
c7152763 TN |
1619 | |
1620 | req->num_trbs = 0; | |
7746a8df FB |
1621 | } |
1622 | ||
d4f1afe5 FB |
1623 | static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep) |
1624 | { | |
1625 | struct dwc3_request *req; | |
1626 | struct dwc3_request *tmp; | |
1627 | ||
1628 | list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) { | |
1629 | dwc3_gadget_ep_skip_trbs(dep, req); | |
1630 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1631 | } | |
1632 | } | |
1633 | ||
72246da4 FB |
1634 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, |
1635 | struct usb_request *request) | |
1636 | { | |
1637 | struct dwc3_request *req = to_dwc3_request(request); | |
1638 | struct dwc3_request *r = NULL; | |
1639 | ||
1640 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1641 | struct dwc3 *dwc = dep->dwc; | |
1642 | ||
1643 | unsigned long flags; | |
1644 | int ret = 0; | |
1645 | ||
2c4cbe6e FB |
1646 | trace_dwc3_ep_dequeue(req); |
1647 | ||
72246da4 FB |
1648 | spin_lock_irqsave(&dwc->lock, flags); |
1649 | ||
a7027ca6 | 1650 | list_for_each_entry(r, &dep->cancelled_list, list) { |
72246da4 | 1651 | if (r == req) |
fcd2def6 | 1652 | goto out; |
72246da4 FB |
1653 | } |
1654 | ||
aa3342c8 | 1655 | list_for_each_entry(r, &dep->pending_list, list) { |
fcd2def6 TN |
1656 | if (r == req) { |
1657 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1658 | goto out; | |
72246da4 | 1659 | } |
72246da4 FB |
1660 | } |
1661 | ||
fcd2def6 | 1662 | list_for_each_entry(r, &dep->started_list, list) { |
72246da4 | 1663 | if (r == req) { |
a7027ca6 TN |
1664 | struct dwc3_request *t; |
1665 | ||
72246da4 | 1666 | /* wait until it is processed */ |
c5353b22 | 1667 | dwc3_stop_active_transfer(dep, true, true); |
cf3113d8 | 1668 | |
a7027ca6 TN |
1669 | /* |
1670 | * Remove any started request if the transfer is | |
1671 | * cancelled. | |
1672 | */ | |
1673 | list_for_each_entry_safe(r, t, &dep->started_list, list) | |
1674 | dwc3_gadget_move_cancelled_request(r); | |
cf3113d8 | 1675 | |
fcd2def6 | 1676 | goto out; |
72246da4 | 1677 | } |
72246da4 FB |
1678 | } |
1679 | ||
fcd2def6 TN |
1680 | dev_err(dwc->dev, "request %pK was not queued to %s\n", |
1681 | request, ep->name); | |
1682 | ret = -EINVAL; | |
1683 | out: | |
72246da4 FB |
1684 | spin_unlock_irqrestore(&dwc->lock, flags); |
1685 | ||
1686 | return ret; | |
1687 | } | |
1688 | ||
7a608559 | 1689 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) |
72246da4 FB |
1690 | { |
1691 | struct dwc3_gadget_ep_cmd_params params; | |
1692 | struct dwc3 *dwc = dep->dwc; | |
cb11ea56 TN |
1693 | struct dwc3_request *req; |
1694 | struct dwc3_request *tmp; | |
72246da4 FB |
1695 | int ret; |
1696 | ||
5ad02fb8 FB |
1697 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
1698 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); | |
1699 | return -EINVAL; | |
1700 | } | |
1701 | ||
72246da4 FB |
1702 | memset(¶ms, 0x00, sizeof(params)); |
1703 | ||
1704 | if (value) { | |
69450c4d FB |
1705 | struct dwc3_trb *trb; |
1706 | ||
1707 | unsigned transfer_in_flight; | |
1708 | unsigned started; | |
1709 | ||
1710 | if (dep->number > 1) | |
1711 | trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue); | |
1712 | else | |
1713 | trb = &dwc->ep0_trb[dep->trb_enqueue]; | |
1714 | ||
1715 | transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO; | |
1716 | started = !list_empty(&dep->started_list); | |
1717 | ||
1718 | if (!protocol && ((dep->direction && transfer_in_flight) || | |
1719 | (!dep->direction && started))) { | |
7a608559 FB |
1720 | return -EAGAIN; |
1721 | } | |
1722 | ||
2cd4718d FB |
1723 | ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL, |
1724 | ¶ms); | |
72246da4 | 1725 | if (ret) |
3f89204b | 1726 | dev_err(dwc->dev, "failed to set STALL on %s\n", |
72246da4 FB |
1727 | dep->name); |
1728 | else | |
1729 | dep->flags |= DWC3_EP_STALL; | |
1730 | } else { | |
cb11ea56 TN |
1731 | /* |
1732 | * Don't issue CLEAR_STALL command to control endpoints. The | |
1733 | * controller automatically clears the STALL when it receives | |
1734 | * the SETUP token. | |
1735 | */ | |
1736 | if (dep->number <= 1) { | |
1737 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); | |
1738 | return 0; | |
1739 | } | |
2cd4718d | 1740 | |
50c763f8 | 1741 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
cb11ea56 | 1742 | if (ret) { |
3f89204b | 1743 | dev_err(dwc->dev, "failed to clear STALL on %s\n", |
72246da4 | 1744 | dep->name); |
cb11ea56 TN |
1745 | return ret; |
1746 | } | |
1747 | ||
1748 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); | |
1749 | ||
1750 | dwc3_stop_active_transfer(dep, true, true); | |
1751 | ||
1752 | list_for_each_entry_safe(req, tmp, &dep->started_list, list) | |
1753 | dwc3_gadget_move_cancelled_request(req); | |
1754 | ||
1755 | list_for_each_entry_safe(req, tmp, &dep->pending_list, list) | |
1756 | dwc3_gadget_move_cancelled_request(req); | |
1757 | ||
1758 | if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING)) { | |
1759 | dep->flags &= ~DWC3_EP_DELAY_START; | |
1760 | dwc3_gadget_ep_cleanup_cancelled_requests(dep); | |
1761 | } | |
72246da4 | 1762 | } |
5275455a | 1763 | |
72246da4 FB |
1764 | return ret; |
1765 | } | |
1766 | ||
1767 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1768 | { | |
1769 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1770 | struct dwc3 *dwc = dep->dwc; | |
1771 | ||
1772 | unsigned long flags; | |
1773 | ||
1774 | int ret; | |
1775 | ||
1776 | spin_lock_irqsave(&dwc->lock, flags); | |
7a608559 | 1777 | ret = __dwc3_gadget_ep_set_halt(dep, value, false); |
72246da4 FB |
1778 | spin_unlock_irqrestore(&dwc->lock, flags); |
1779 | ||
1780 | return ret; | |
1781 | } | |
1782 | ||
1783 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1784 | { | |
1785 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1786 | struct dwc3 *dwc = dep->dwc; |
1787 | unsigned long flags; | |
95aa4e8d | 1788 | int ret; |
72246da4 | 1789 | |
249a4569 | 1790 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1791 | dep->flags |= DWC3_EP_WEDGE; |
1792 | ||
08f0d966 | 1793 | if (dep->number == 0 || dep->number == 1) |
95aa4e8d | 1794 | ret = __dwc3_gadget_ep0_set_halt(ep, 1); |
08f0d966 | 1795 | else |
7a608559 | 1796 | ret = __dwc3_gadget_ep_set_halt(dep, 1, false); |
95aa4e8d FB |
1797 | spin_unlock_irqrestore(&dwc->lock, flags); |
1798 | ||
1799 | return ret; | |
72246da4 FB |
1800 | } |
1801 | ||
1802 | /* -------------------------------------------------------------------------- */ | |
1803 | ||
1804 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1805 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1806 | .bDescriptorType = USB_DT_ENDPOINT, | |
1807 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1808 | }; | |
1809 | ||
1810 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1811 | .enable = dwc3_gadget_ep0_enable, | |
1812 | .disable = dwc3_gadget_ep0_disable, | |
1813 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1814 | .free_request = dwc3_gadget_ep_free_request, | |
1815 | .queue = dwc3_gadget_ep0_queue, | |
1816 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 1817 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
1818 | .set_wedge = dwc3_gadget_ep_set_wedge, |
1819 | }; | |
1820 | ||
1821 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1822 | .enable = dwc3_gadget_ep_enable, | |
1823 | .disable = dwc3_gadget_ep_disable, | |
1824 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1825 | .free_request = dwc3_gadget_ep_free_request, | |
1826 | .queue = dwc3_gadget_ep_queue, | |
1827 | .dequeue = dwc3_gadget_ep_dequeue, | |
1828 | .set_halt = dwc3_gadget_ep_set_halt, | |
1829 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1830 | }; | |
1831 | ||
1832 | /* -------------------------------------------------------------------------- */ | |
1833 | ||
1834 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1835 | { | |
1836 | struct dwc3 *dwc = gadget_to_dwc(g); | |
72246da4 | 1837 | |
6cb2e4e3 | 1838 | return __dwc3_gadget_get_frame(dwc); |
72246da4 FB |
1839 | } |
1840 | ||
218ef7b6 | 1841 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc) |
72246da4 | 1842 | { |
d6011f6f | 1843 | int retries; |
72246da4 | 1844 | |
218ef7b6 | 1845 | int ret; |
72246da4 FB |
1846 | u32 reg; |
1847 | ||
72246da4 | 1848 | u8 link_state; |
72246da4 | 1849 | |
72246da4 FB |
1850 | /* |
1851 | * According to the Databook Remote wakeup request should | |
1852 | * be issued only when the device is in early suspend state. | |
1853 | * | |
1854 | * We can check that via USB Link State bits in DSTS register. | |
1855 | */ | |
1856 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1857 | ||
72246da4 FB |
1858 | link_state = DWC3_DSTS_USBLNKST(reg); |
1859 | ||
1860 | switch (link_state) { | |
d0550cd2 | 1861 | case DWC3_LINK_STATE_RESET: |
72246da4 FB |
1862 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ |
1863 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
d0550cd2 | 1864 | case DWC3_LINK_STATE_RESUME: |
72246da4 FB |
1865 | break; |
1866 | default: | |
218ef7b6 | 1867 | return -EINVAL; |
72246da4 FB |
1868 | } |
1869 | ||
8598bde7 FB |
1870 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
1871 | if (ret < 0) { | |
1872 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
218ef7b6 | 1873 | return ret; |
8598bde7 | 1874 | } |
72246da4 | 1875 | |
802fde98 | 1876 | /* Recent versions do this automatically */ |
9af21dd6 | 1877 | if (DWC3_VER_IS_PRIOR(DWC3, 194A)) { |
802fde98 | 1878 | /* write zeroes to Link Change Request */ |
fcc023c7 | 1879 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
1880 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
1881 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1882 | } | |
72246da4 | 1883 | |
1d046793 | 1884 | /* poll until Link State changes to ON */ |
d6011f6f | 1885 | retries = 20000; |
72246da4 | 1886 | |
d6011f6f | 1887 | while (retries--) { |
72246da4 FB |
1888 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
1889 | ||
1890 | /* in HS, means ON */ | |
1891 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1892 | break; | |
1893 | } | |
1894 | ||
1895 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1896 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
218ef7b6 | 1897 | return -EINVAL; |
72246da4 FB |
1898 | } |
1899 | ||
218ef7b6 FB |
1900 | return 0; |
1901 | } | |
1902 | ||
1903 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1904 | { | |
1905 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1906 | unsigned long flags; | |
1907 | int ret; | |
1908 | ||
1909 | spin_lock_irqsave(&dwc->lock, flags); | |
1910 | ret = __dwc3_gadget_wakeup(dwc); | |
72246da4 FB |
1911 | spin_unlock_irqrestore(&dwc->lock, flags); |
1912 | ||
1913 | return ret; | |
1914 | } | |
1915 | ||
1916 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1917 | int is_selfpowered) | |
1918 | { | |
1919 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 1920 | unsigned long flags; |
72246da4 | 1921 | |
249a4569 | 1922 | spin_lock_irqsave(&dwc->lock, flags); |
bcdea503 | 1923 | g->is_selfpowered = !!is_selfpowered; |
249a4569 | 1924 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
1925 | |
1926 | return 0; | |
1927 | } | |
1928 | ||
7b2a0368 | 1929 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) |
72246da4 FB |
1930 | { |
1931 | u32 reg; | |
61d58242 | 1932 | u32 timeout = 500; |
72246da4 | 1933 | |
fc8bb91b FB |
1934 | if (pm_runtime_suspended(dwc->dev)) |
1935 | return 0; | |
1936 | ||
72246da4 | 1937 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
8db7ed15 | 1938 | if (is_on) { |
9af21dd6 | 1939 | if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) { |
802fde98 PZ |
1940 | reg &= ~DWC3_DCTL_TRGTULST_MASK; |
1941 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
1942 | } | |
1943 | ||
9af21dd6 | 1944 | if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) |
802fde98 PZ |
1945 | reg &= ~DWC3_DCTL_KEEP_CONNECT; |
1946 | reg |= DWC3_DCTL_RUN_STOP; | |
7b2a0368 FB |
1947 | |
1948 | if (dwc->has_hibernation) | |
1949 | reg |= DWC3_DCTL_KEEP_CONNECT; | |
1950 | ||
9fcb3bd8 | 1951 | dwc->pullups_connected = true; |
8db7ed15 | 1952 | } else { |
72246da4 | 1953 | reg &= ~DWC3_DCTL_RUN_STOP; |
7b2a0368 FB |
1954 | |
1955 | if (dwc->has_hibernation && !suspend) | |
1956 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1957 | ||
9fcb3bd8 | 1958 | dwc->pullups_connected = false; |
8db7ed15 | 1959 | } |
72246da4 | 1960 | |
5b738211 | 1961 | dwc3_gadget_dctl_write_safe(dwc, reg); |
72246da4 FB |
1962 | |
1963 | do { | |
1964 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
b6d4e16e FB |
1965 | reg &= DWC3_DSTS_DEVCTRLHLT; |
1966 | } while (--timeout && !(!is_on ^ !reg)); | |
f2df679b FB |
1967 | |
1968 | if (!timeout) | |
1969 | return -ETIMEDOUT; | |
72246da4 | 1970 | |
6f17f74b | 1971 | return 0; |
72246da4 FB |
1972 | } |
1973 | ||
1974 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1975 | { | |
1976 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1977 | unsigned long flags; | |
6f17f74b | 1978 | int ret; |
72246da4 FB |
1979 | |
1980 | is_on = !!is_on; | |
1981 | ||
bb014736 BW |
1982 | /* |
1983 | * Per databook, when we want to stop the gadget, if a control transfer | |
1984 | * is still in process, complete it and get the core into setup phase. | |
1985 | */ | |
1986 | if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) { | |
1987 | reinit_completion(&dwc->ep0_in_setup); | |
1988 | ||
1989 | ret = wait_for_completion_timeout(&dwc->ep0_in_setup, | |
1990 | msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT)); | |
1991 | if (ret == 0) { | |
1992 | dev_err(dwc->dev, "timed out waiting for SETUP phase\n"); | |
1993 | return -ETIMEDOUT; | |
1994 | } | |
1995 | } | |
1996 | ||
72246da4 | 1997 | spin_lock_irqsave(&dwc->lock, flags); |
7b2a0368 | 1998 | ret = dwc3_gadget_run_stop(dwc, is_on, false); |
72246da4 FB |
1999 | spin_unlock_irqrestore(&dwc->lock, flags); |
2000 | ||
6f17f74b | 2001 | return ret; |
72246da4 FB |
2002 | } |
2003 | ||
8698e2ac FB |
2004 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
2005 | { | |
2006 | u32 reg; | |
2007 | ||
2008 | /* Enable all but Start and End of Frame IRQs */ | |
2009 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
2010 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
2011 | DWC3_DEVTEN_CMDCMPLTEN | | |
2012 | DWC3_DEVTEN_ERRTICERREN | | |
2013 | DWC3_DEVTEN_WKUPEVTEN | | |
8698e2ac FB |
2014 | DWC3_DEVTEN_CONNECTDONEEN | |
2015 | DWC3_DEVTEN_USBRSTEN | | |
2016 | DWC3_DEVTEN_DISCONNEVTEN); | |
2017 | ||
9af21dd6 | 2018 | if (DWC3_VER_IS_PRIOR(DWC3, 250A)) |
799e9dc8 FB |
2019 | reg |= DWC3_DEVTEN_ULSTCNGEN; |
2020 | ||
8698e2ac FB |
2021 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); |
2022 | } | |
2023 | ||
2024 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
2025 | { | |
2026 | /* mask all interrupts */ | |
2027 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
2028 | } | |
2029 | ||
2030 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 2031 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 2032 | |
4e99472b | 2033 | /** |
bfad65ee FB |
2034 | * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG |
2035 | * @dwc: pointer to our context structure | |
4e99472b FB |
2036 | * |
2037 | * The following looks like complex but it's actually very simple. In order to | |
2038 | * calculate the number of packets we can burst at once on OUT transfers, we're | |
2039 | * gonna use RxFIFO size. | |
2040 | * | |
2041 | * To calculate RxFIFO size we need two numbers: | |
2042 | * MDWIDTH = size, in bits, of the internal memory bus | |
2043 | * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits) | |
2044 | * | |
2045 | * Given these two numbers, the formula is simple: | |
2046 | * | |
2047 | * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16; | |
2048 | * | |
2049 | * 24 bytes is for 3x SETUP packets | |
2050 | * 16 bytes is a clock domain crossing tolerance | |
2051 | * | |
2052 | * Given RxFIFO Size, NUMP = RxFIFOSize / 1024; | |
2053 | */ | |
2054 | static void dwc3_gadget_setup_nump(struct dwc3 *dwc) | |
2055 | { | |
2056 | u32 ram2_depth; | |
2057 | u32 mdwidth; | |
2058 | u32 nump; | |
2059 | u32 reg; | |
2060 | ||
2061 | ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7); | |
2062 | mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0); | |
4244ba02 TN |
2063 | if (DWC3_IP_IS(DWC32)) |
2064 | mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6); | |
4e99472b FB |
2065 | |
2066 | nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024; | |
2067 | nump = min_t(u32, nump, 16); | |
2068 | ||
2069 | /* update NumP */ | |
2070 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2071 | reg &= ~DWC3_DCFG_NUMP_MASK; | |
2072 | reg |= nump << DWC3_DCFG_NUMP_SHIFT; | |
2073 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2074 | } | |
2075 | ||
d7be2952 | 2076 | static int __dwc3_gadget_start(struct dwc3 *dwc) |
72246da4 | 2077 | { |
72246da4 | 2078 | struct dwc3_ep *dep; |
72246da4 FB |
2079 | int ret = 0; |
2080 | u32 reg; | |
2081 | ||
cf40b86b JY |
2082 | /* |
2083 | * Use IMOD if enabled via dwc->imod_interval. Otherwise, if | |
2084 | * the core supports IMOD, disable it. | |
2085 | */ | |
2086 | if (dwc->imod_interval) { | |
2087 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); | |
2088 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); | |
2089 | } else if (dwc3_has_imod(dwc)) { | |
2090 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0); | |
2091 | } | |
2092 | ||
2a58f9c1 FB |
2093 | /* |
2094 | * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP | |
2095 | * field instead of letting dwc3 itself calculate that automatically. | |
2096 | * | |
2097 | * This way, we maximize the chances that we'll be able to get several | |
2098 | * bursts of data without going through any sort of endpoint throttling. | |
2099 | */ | |
2100 | reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); | |
9af21dd6 | 2101 | if (DWC3_IP_IS(DWC3)) |
01b0e2cc | 2102 | reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL; |
9af21dd6 TN |
2103 | else |
2104 | reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL; | |
01b0e2cc | 2105 | |
2a58f9c1 FB |
2106 | dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); |
2107 | ||
4e99472b FB |
2108 | dwc3_gadget_setup_nump(dwc); |
2109 | ||
72246da4 FB |
2110 | /* Start with SuperSpeed Default */ |
2111 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
2112 | ||
2113 | dep = dwc->eps[0]; | |
a2d23f08 | 2114 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
2115 | if (ret) { |
2116 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 2117 | goto err0; |
72246da4 FB |
2118 | } |
2119 | ||
2120 | dep = dwc->eps[1]; | |
a2d23f08 | 2121 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
2122 | if (ret) { |
2123 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 2124 | goto err1; |
72246da4 FB |
2125 | } |
2126 | ||
2127 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 2128 | dwc->ep0state = EP0_SETUP_PHASE; |
88b1bb1f | 2129 | dwc->link_state = DWC3_LINK_STATE_SS_DIS; |
72246da4 FB |
2130 | dwc3_ep0_out_start(dwc); |
2131 | ||
8698e2ac FB |
2132 | dwc3_gadget_enable_irq(dwc); |
2133 | ||
72246da4 FB |
2134 | return 0; |
2135 | ||
b0d7ffd4 | 2136 | err1: |
d7be2952 | 2137 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
b0d7ffd4 FB |
2138 | |
2139 | err0: | |
72246da4 FB |
2140 | return ret; |
2141 | } | |
2142 | ||
d7be2952 FB |
2143 | static int dwc3_gadget_start(struct usb_gadget *g, |
2144 | struct usb_gadget_driver *driver) | |
72246da4 FB |
2145 | { |
2146 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2147 | unsigned long flags; | |
d7be2952 | 2148 | int ret = 0; |
8698e2ac | 2149 | int irq; |
72246da4 | 2150 | |
9522def4 | 2151 | irq = dwc->irq_gadget; |
d7be2952 FB |
2152 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, |
2153 | IRQF_SHARED, "dwc3", dwc->ev_buf); | |
2154 | if (ret) { | |
2155 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
2156 | irq, ret); | |
2157 | goto err0; | |
2158 | } | |
2159 | ||
72246da4 | 2160 | spin_lock_irqsave(&dwc->lock, flags); |
d7be2952 FB |
2161 | if (dwc->gadget_driver) { |
2162 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
2163 | dwc->gadget.name, | |
2164 | dwc->gadget_driver->driver.name); | |
2165 | ret = -EBUSY; | |
2166 | goto err1; | |
2167 | } | |
2168 | ||
2169 | dwc->gadget_driver = driver; | |
2170 | ||
fc8bb91b FB |
2171 | if (pm_runtime_active(dwc->dev)) |
2172 | __dwc3_gadget_start(dwc); | |
2173 | ||
d7be2952 FB |
2174 | spin_unlock_irqrestore(&dwc->lock, flags); |
2175 | ||
2176 | return 0; | |
2177 | ||
2178 | err1: | |
2179 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2180 | free_irq(irq, dwc); | |
2181 | ||
2182 | err0: | |
2183 | return ret; | |
2184 | } | |
72246da4 | 2185 | |
d7be2952 FB |
2186 | static void __dwc3_gadget_stop(struct dwc3 *dwc) |
2187 | { | |
8698e2ac | 2188 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
2189 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
2190 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
d7be2952 | 2191 | } |
72246da4 | 2192 | |
d7be2952 FB |
2193 | static int dwc3_gadget_stop(struct usb_gadget *g) |
2194 | { | |
2195 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2196 | unsigned long flags; | |
72246da4 | 2197 | |
d7be2952 | 2198 | spin_lock_irqsave(&dwc->lock, flags); |
76a638f8 BW |
2199 | |
2200 | if (pm_runtime_suspended(dwc->dev)) | |
2201 | goto out; | |
2202 | ||
d7be2952 | 2203 | __dwc3_gadget_stop(dwc); |
76a638f8 | 2204 | |
76a638f8 | 2205 | out: |
d7be2952 | 2206 | dwc->gadget_driver = NULL; |
72246da4 FB |
2207 | spin_unlock_irqrestore(&dwc->lock, flags); |
2208 | ||
3f308d17 | 2209 | free_irq(dwc->irq_gadget, dwc->ev_buf); |
b0d7ffd4 | 2210 | |
72246da4 FB |
2211 | return 0; |
2212 | } | |
802fde98 | 2213 | |
729dcffd AKV |
2214 | static void dwc3_gadget_config_params(struct usb_gadget *g, |
2215 | struct usb_dcd_config_params *params) | |
2216 | { | |
2217 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2218 | ||
54fb5ba6 TN |
2219 | params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED; |
2220 | params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED; | |
2221 | ||
2222 | /* Recommended BESL */ | |
2223 | if (!dwc->dis_enblslpm_quirk) { | |
17b63704 TN |
2224 | /* |
2225 | * If the recommended BESL baseline is 0 or if the BESL deep is | |
2226 | * less than 2, Microsoft's Windows 10 host usb stack will issue | |
2227 | * a usb reset immediately after it receives the extended BOS | |
2228 | * descriptor and the enumeration will fail. To maintain | |
2229 | * compatibility with the Windows' usb stack, let's set the | |
2230 | * recommended BESL baseline to 1 and clamp the BESL deep to be | |
2231 | * within 2 to 15. | |
2232 | */ | |
2233 | params->besl_baseline = 1; | |
54fb5ba6 | 2234 | if (dwc->is_utmi_l1_suspend) |
17b63704 TN |
2235 | params->besl_deep = |
2236 | clamp_t(u8, dwc->hird_threshold, 2, 15); | |
54fb5ba6 TN |
2237 | } |
2238 | ||
729dcffd AKV |
2239 | /* U1 Device exit Latency */ |
2240 | if (dwc->dis_u1_entry_quirk) | |
2241 | params->bU1devExitLat = 0; | |
2242 | else | |
2243 | params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT; | |
2244 | ||
2245 | /* U2 Device exit Latency */ | |
2246 | if (dwc->dis_u2_entry_quirk) | |
2247 | params->bU2DevExitLat = 0; | |
2248 | else | |
2249 | params->bU2DevExitLat = | |
2250 | cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT); | |
2251 | } | |
2252 | ||
7d8d0639 FB |
2253 | static void dwc3_gadget_set_speed(struct usb_gadget *g, |
2254 | enum usb_device_speed speed) | |
2255 | { | |
2256 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2257 | unsigned long flags; | |
2258 | u32 reg; | |
2259 | ||
2260 | spin_lock_irqsave(&dwc->lock, flags); | |
2261 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2262 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
2263 | ||
2264 | /* | |
2265 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
2266 | * which would cause metastability state on Run/Stop | |
2267 | * bit if we try to force the IP to USB2-only mode. | |
2268 | * | |
2269 | * Because of that, we cannot configure the IP to any | |
2270 | * speed other than the SuperSpeed | |
2271 | * | |
2272 | * Refers to: | |
2273 | * | |
2274 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
2275 | * USB 2.0 Mode | |
2276 | */ | |
9af21dd6 | 2277 | if (DWC3_VER_IS_PRIOR(DWC3, 220A) && |
42bf02ec | 2278 | !dwc->dis_metastability_quirk) { |
7d8d0639 FB |
2279 | reg |= DWC3_DCFG_SUPERSPEED; |
2280 | } else { | |
2281 | switch (speed) { | |
2282 | case USB_SPEED_LOW: | |
2283 | reg |= DWC3_DCFG_LOWSPEED; | |
2284 | break; | |
2285 | case USB_SPEED_FULL: | |
2286 | reg |= DWC3_DCFG_FULLSPEED; | |
2287 | break; | |
2288 | case USB_SPEED_HIGH: | |
2289 | reg |= DWC3_DCFG_HIGHSPEED; | |
2290 | break; | |
2291 | case USB_SPEED_SUPER: | |
2292 | reg |= DWC3_DCFG_SUPERSPEED; | |
2293 | break; | |
2294 | case USB_SPEED_SUPER_PLUS: | |
9af21dd6 | 2295 | if (DWC3_IP_IS(DWC3)) |
2f3090c6 | 2296 | reg |= DWC3_DCFG_SUPERSPEED; |
9af21dd6 TN |
2297 | else |
2298 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; | |
7d8d0639 FB |
2299 | break; |
2300 | default: | |
2301 | dev_err(dwc->dev, "invalid speed (%d)\n", speed); | |
2302 | ||
9af21dd6 | 2303 | if (DWC3_IP_IS(DWC3)) |
7d8d0639 | 2304 | reg |= DWC3_DCFG_SUPERSPEED; |
9af21dd6 TN |
2305 | else |
2306 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; | |
7d8d0639 FB |
2307 | } |
2308 | } | |
2309 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2310 | ||
2311 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2312 | } | |
2313 | ||
72246da4 FB |
2314 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
2315 | .get_frame = dwc3_gadget_get_frame, | |
2316 | .wakeup = dwc3_gadget_wakeup, | |
2317 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
2318 | .pullup = dwc3_gadget_pullup, | |
2319 | .udc_start = dwc3_gadget_start, | |
2320 | .udc_stop = dwc3_gadget_stop, | |
7d8d0639 | 2321 | .udc_set_speed = dwc3_gadget_set_speed, |
729dcffd | 2322 | .get_config_params = dwc3_gadget_config_params, |
72246da4 FB |
2323 | }; |
2324 | ||
2325 | /* -------------------------------------------------------------------------- */ | |
2326 | ||
8f1c99cd | 2327 | static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep) |
72246da4 | 2328 | { |
8f1c99cd | 2329 | struct dwc3 *dwc = dep->dwc; |
72246da4 | 2330 | |
8f1c99cd FB |
2331 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
2332 | dep->endpoint.maxburst = 1; | |
2333 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; | |
2334 | if (!dep->direction) | |
2335 | dwc->gadget.ep0 = &dep->endpoint; | |
f3bcfc7e | 2336 | |
8f1c99cd | 2337 | dep->endpoint.caps.type_control = true; |
72246da4 | 2338 | |
8f1c99cd FB |
2339 | return 0; |
2340 | } | |
72246da4 | 2341 | |
8f1c99cd FB |
2342 | static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep) |
2343 | { | |
2344 | struct dwc3 *dwc = dep->dwc; | |
2345 | int mdwidth; | |
8f1c99cd | 2346 | int size; |
72246da4 | 2347 | |
8f1c99cd | 2348 | mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); |
4244ba02 TN |
2349 | if (DWC3_IP_IS(DWC32)) |
2350 | mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6); | |
2351 | ||
8f1c99cd FB |
2352 | /* MDWIDTH is represented in bits, we need it in bytes */ |
2353 | mdwidth /= 8; | |
6a1e3ef4 | 2354 | |
8f1c99cd | 2355 | size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1)); |
9af21dd6 | 2356 | if (DWC3_IP_IS(DWC3)) |
586f4335 | 2357 | size = DWC3_GTXFIFOSIZ_TXFDEP(size); |
9af21dd6 TN |
2358 | else |
2359 | size = DWC31_GTXFIFOSIZ_TXFDEP(size); | |
39ebb05c | 2360 | |
8f1c99cd FB |
2361 | /* FIFO Depth is in MDWDITH bytes. Multiply */ |
2362 | size *= mdwidth; | |
39ebb05c | 2363 | |
8f1c99cd | 2364 | /* |
d94ea531 TN |
2365 | * To meet performance requirement, a minimum TxFIFO size of 3x |
2366 | * MaxPacketSize is recommended for endpoints that support burst and a | |
2367 | * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't | |
2368 | * support burst. Use those numbers and we can calculate the max packet | |
2369 | * limit as below. | |
8f1c99cd | 2370 | */ |
d94ea531 TN |
2371 | if (dwc->maximum_speed >= USB_SPEED_SUPER) |
2372 | size /= 3; | |
2373 | else | |
2374 | size /= 2; | |
28781789 | 2375 | |
8f1c99cd | 2376 | usb_ep_set_maxpacket_limit(&dep->endpoint, size); |
28781789 | 2377 | |
8f1c99cd FB |
2378 | dep->endpoint.max_streams = 15; |
2379 | dep->endpoint.ops = &dwc3_gadget_ep_ops; | |
2380 | list_add_tail(&dep->endpoint.ep_list, | |
2381 | &dwc->gadget.ep_list); | |
2382 | dep->endpoint.caps.type_iso = true; | |
2383 | dep->endpoint.caps.type_bulk = true; | |
2384 | dep->endpoint.caps.type_int = true; | |
28781789 | 2385 | |
8f1c99cd FB |
2386 | return dwc3_alloc_trb_pool(dep); |
2387 | } | |
28781789 | 2388 | |
8f1c99cd FB |
2389 | static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep) |
2390 | { | |
2391 | struct dwc3 *dwc = dep->dwc; | |
d94ea531 TN |
2392 | int mdwidth; |
2393 | int size; | |
2394 | ||
2395 | mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); | |
4244ba02 TN |
2396 | if (DWC3_IP_IS(DWC32)) |
2397 | mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6); | |
d94ea531 TN |
2398 | |
2399 | /* MDWIDTH is represented in bits, convert to bytes */ | |
2400 | mdwidth /= 8; | |
28781789 | 2401 | |
d94ea531 TN |
2402 | /* All OUT endpoints share a single RxFIFO space */ |
2403 | size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0)); | |
9af21dd6 | 2404 | if (DWC3_IP_IS(DWC3)) |
d94ea531 | 2405 | size = DWC3_GRXFIFOSIZ_RXFDEP(size); |
9af21dd6 TN |
2406 | else |
2407 | size = DWC31_GRXFIFOSIZ_RXFDEP(size); | |
d94ea531 TN |
2408 | |
2409 | /* FIFO depth is in MDWDITH bytes */ | |
2410 | size *= mdwidth; | |
2411 | ||
2412 | /* | |
2413 | * To meet performance requirement, a minimum recommended RxFIFO size | |
2414 | * is defined as follow: | |
2415 | * RxFIFO size >= (3 x MaxPacketSize) + | |
2416 | * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin) | |
2417 | * | |
2418 | * Then calculate the max packet limit as below. | |
2419 | */ | |
2420 | size -= (3 * 8) + 16; | |
2421 | if (size < 0) | |
2422 | size = 0; | |
2423 | else | |
2424 | size /= 3; | |
2425 | ||
2426 | usb_ep_set_maxpacket_limit(&dep->endpoint, size); | |
8f1c99cd FB |
2427 | dep->endpoint.max_streams = 15; |
2428 | dep->endpoint.ops = &dwc3_gadget_ep_ops; | |
2429 | list_add_tail(&dep->endpoint.ep_list, | |
2430 | &dwc->gadget.ep_list); | |
2431 | dep->endpoint.caps.type_iso = true; | |
2432 | dep->endpoint.caps.type_bulk = true; | |
2433 | dep->endpoint.caps.type_int = true; | |
72246da4 | 2434 | |
8f1c99cd FB |
2435 | return dwc3_alloc_trb_pool(dep); |
2436 | } | |
72246da4 | 2437 | |
8f1c99cd FB |
2438 | static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum) |
2439 | { | |
2440 | struct dwc3_ep *dep; | |
2441 | bool direction = epnum & 1; | |
2442 | int ret; | |
2443 | u8 num = epnum >> 1; | |
25b8ff68 | 2444 | |
8f1c99cd FB |
2445 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
2446 | if (!dep) | |
2447 | return -ENOMEM; | |
2448 | ||
2449 | dep->dwc = dwc; | |
2450 | dep->number = epnum; | |
2451 | dep->direction = direction; | |
2452 | dep->regs = dwc->regs + DWC3_DEP_BASE(epnum); | |
2453 | dwc->eps[epnum] = dep; | |
d92021f6 TN |
2454 | dep->combo_num = 0; |
2455 | dep->start_cmd_status = 0; | |
8f1c99cd FB |
2456 | |
2457 | snprintf(dep->name, sizeof(dep->name), "ep%u%s", num, | |
2458 | direction ? "in" : "out"); | |
2459 | ||
2460 | dep->endpoint.name = dep->name; | |
2461 | ||
2462 | if (!(dep->number > 1)) { | |
2463 | dep->endpoint.desc = &dwc3_gadget_ep0_desc; | |
2464 | dep->endpoint.comp_desc = NULL; | |
2465 | } | |
2466 | ||
8f1c99cd FB |
2467 | if (num == 0) |
2468 | ret = dwc3_gadget_init_control_endpoint(dep); | |
2469 | else if (direction) | |
2470 | ret = dwc3_gadget_init_in_endpoint(dep); | |
2471 | else | |
2472 | ret = dwc3_gadget_init_out_endpoint(dep); | |
2473 | ||
2474 | if (ret) | |
2475 | return ret; | |
a474d3b7 | 2476 | |
8f1c99cd FB |
2477 | dep->endpoint.caps.dir_in = direction; |
2478 | dep->endpoint.caps.dir_out = !direction; | |
a474d3b7 | 2479 | |
8f1c99cd FB |
2480 | INIT_LIST_HEAD(&dep->pending_list); |
2481 | INIT_LIST_HEAD(&dep->started_list); | |
d5443bbf | 2482 | INIT_LIST_HEAD(&dep->cancelled_list); |
8f1c99cd FB |
2483 | |
2484 | return 0; | |
2485 | } | |
2486 | ||
2487 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total) | |
2488 | { | |
2489 | u8 epnum; | |
2490 | ||
2491 | INIT_LIST_HEAD(&dwc->gadget.ep_list); | |
2492 | ||
2493 | for (epnum = 0; epnum < total; epnum++) { | |
2494 | int ret; | |
2495 | ||
2496 | ret = dwc3_gadget_init_endpoint(dwc, epnum); | |
2497 | if (ret) | |
2498 | return ret; | |
72246da4 FB |
2499 | } |
2500 | ||
2501 | return 0; | |
2502 | } | |
2503 | ||
2504 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) | |
2505 | { | |
2506 | struct dwc3_ep *dep; | |
2507 | u8 epnum; | |
2508 | ||
2509 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2510 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2511 | if (!dep) |
2512 | continue; | |
5bf8fae3 GC |
2513 | /* |
2514 | * Physical endpoints 0 and 1 are special; they form the | |
2515 | * bi-directional USB endpoint 0. | |
2516 | * | |
2517 | * For those two physical endpoints, we don't allocate a TRB | |
2518 | * pool nor do we add them the endpoints list. Due to that, we | |
2519 | * shouldn't do these two operations otherwise we would end up | |
2520 | * with all sorts of bugs when removing dwc3.ko. | |
2521 | */ | |
2522 | if (epnum != 0 && epnum != 1) { | |
2523 | dwc3_free_trb_pool(dep); | |
72246da4 | 2524 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 2525 | } |
72246da4 FB |
2526 | |
2527 | kfree(dep); | |
2528 | } | |
2529 | } | |
2530 | ||
72246da4 | 2531 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 2532 | |
8f608e8a FB |
2533 | static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep, |
2534 | struct dwc3_request *req, struct dwc3_trb *trb, | |
2535 | const struct dwc3_event_depevt *event, int status, int chain) | |
72246da4 | 2536 | { |
72246da4 | 2537 | unsigned int count; |
72246da4 | 2538 | |
dc55c67e | 2539 | dwc3_ep_inc_deq(dep); |
a9c3ca5f | 2540 | |
2c4cbe6e | 2541 | trace_dwc3_complete_trb(dep, trb); |
09fe1f8d | 2542 | req->num_trbs--; |
2c4cbe6e | 2543 | |
e5b36ae2 FB |
2544 | /* |
2545 | * If we're in the middle of series of chained TRBs and we | |
2546 | * receive a short transfer along the way, DWC3 will skip | |
2547 | * through all TRBs including the last TRB in the chain (the | |
2548 | * where CHN bit is zero. DWC3 will also avoid clearing HWO | |
2549 | * bit and SW has to do it manually. | |
2550 | * | |
2551 | * We're going to do that here to avoid problems of HW trying | |
2552 | * to use bogus TRBs for transfers. | |
2553 | */ | |
2554 | if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO)) | |
2555 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; | |
2556 | ||
6abfa0f5 TN |
2557 | /* |
2558 | * For isochronous transfers, the first TRB in a service interval must | |
2559 | * have the Isoc-First type. Track and report its interval frame number. | |
2560 | */ | |
2561 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
2562 | (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) { | |
2563 | unsigned int frame_number; | |
2564 | ||
2565 | frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl); | |
2566 | frame_number &= ~(dep->interval - 1); | |
2567 | req->request.frame_number = frame_number; | |
2568 | } | |
2569 | ||
c6267a51 FB |
2570 | /* |
2571 | * If we're dealing with unaligned size OUT transfer, we will be left | |
2572 | * with one TRB pending in the ring. We need to manually clear HWO bit | |
2573 | * from that TRB. | |
2574 | */ | |
1a22ec64 FB |
2575 | |
2576 | if (req->needs_extra_trb && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) { | |
c6267a51 FB |
2577 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; |
2578 | return 1; | |
2579 | } | |
2580 | ||
e5ba5ec8 | 2581 | count = trb->size & DWC3_TRB_SIZE_MASK; |
e62c5bc5 | 2582 | req->remaining += count; |
e5ba5ec8 | 2583 | |
35b2719e FB |
2584 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
2585 | return 1; | |
2586 | ||
d80fe1b6 | 2587 | if (event->status & DEPEVT_STATUS_SHORT && !chain) |
e5ba5ec8 | 2588 | return 1; |
f99f53f2 | 2589 | |
5ee85897 AKV |
2590 | if ((trb->ctrl & DWC3_TRB_CTRL_IOC) || |
2591 | (trb->ctrl & DWC3_TRB_CTRL_LST)) | |
e5ba5ec8 | 2592 | return 1; |
f99f53f2 | 2593 | |
e5ba5ec8 PA |
2594 | return 0; |
2595 | } | |
2596 | ||
d3692953 FB |
2597 | static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep, |
2598 | struct dwc3_request *req, const struct dwc3_event_depevt *event, | |
2599 | int status) | |
2600 | { | |
2601 | struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue]; | |
2602 | struct scatterlist *sg = req->sg; | |
2603 | struct scatterlist *s; | |
2604 | unsigned int pending = req->num_pending_sgs; | |
2605 | unsigned int i; | |
2606 | int ret = 0; | |
2607 | ||
2608 | for_each_sg(sg, s, pending, i) { | |
2609 | trb = &dep->trb_pool[dep->trb_dequeue]; | |
2610 | ||
d3692953 FB |
2611 | req->sg = sg_next(s); |
2612 | req->num_pending_sgs--; | |
2613 | ||
2614 | ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req, | |
2615 | trb, event, status, true); | |
2616 | if (ret) | |
2617 | break; | |
2618 | } | |
2619 | ||
2620 | return ret; | |
2621 | } | |
2622 | ||
2623 | static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep, | |
2624 | struct dwc3_request *req, const struct dwc3_event_depevt *event, | |
2625 | int status) | |
2626 | { | |
2627 | struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue]; | |
2628 | ||
2629 | return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb, | |
2630 | event, status, false); | |
2631 | } | |
2632 | ||
e0c42ce5 FB |
2633 | static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req) |
2634 | { | |
49e0590e | 2635 | return req->num_pending_sgs == 0; |
e0c42ce5 FB |
2636 | } |
2637 | ||
f38e35dd FB |
2638 | static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep, |
2639 | const struct dwc3_event_depevt *event, | |
2640 | struct dwc3_request *req, int status) | |
2641 | { | |
2642 | int ret; | |
2643 | ||
2644 | if (req->num_pending_sgs) | |
2645 | ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event, | |
2646 | status); | |
2647 | else | |
2648 | ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event, | |
2649 | status); | |
2650 | ||
1a22ec64 | 2651 | if (req->needs_extra_trb) { |
f38e35dd FB |
2652 | ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event, |
2653 | status); | |
1a22ec64 | 2654 | req->needs_extra_trb = false; |
f38e35dd FB |
2655 | } |
2656 | ||
2657 | req->request.actual = req->request.length - req->remaining; | |
2658 | ||
d9feef97 | 2659 | if (!dwc3_gadget_ep_request_completed(req)) |
f38e35dd | 2660 | goto out; |
f38e35dd FB |
2661 | |
2662 | dwc3_gadget_giveback(dep, req, status); | |
2663 | ||
2664 | out: | |
2665 | return ret; | |
2666 | } | |
2667 | ||
12a3a4ad | 2668 | static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep, |
8f608e8a | 2669 | const struct dwc3_event_depevt *event, int status) |
e5ba5ec8 | 2670 | { |
6afbdb57 FB |
2671 | struct dwc3_request *req; |
2672 | struct dwc3_request *tmp; | |
e5ba5ec8 | 2673 | |
6afbdb57 | 2674 | list_for_each_entry_safe(req, tmp, &dep->started_list, list) { |
fee73e61 | 2675 | int ret; |
e5b36ae2 | 2676 | |
f38e35dd FB |
2677 | ret = dwc3_gadget_ep_cleanup_completed_request(dep, event, |
2678 | req, status); | |
58f0218a | 2679 | if (ret) |
72246da4 | 2680 | break; |
31162af4 | 2681 | } |
72246da4 FB |
2682 | } |
2683 | ||
d9feef97 TN |
2684 | static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep) |
2685 | { | |
2686 | struct dwc3_request *req; | |
2687 | ||
2688 | if (!list_empty(&dep->pending_list)) | |
2689 | return true; | |
2690 | ||
2691 | /* | |
2692 | * We only need to check the first entry of the started list. We can | |
2693 | * assume the completed requests are removed from the started list. | |
2694 | */ | |
2695 | req = next_request(&dep->started_list); | |
2696 | if (!req) | |
2697 | return false; | |
2698 | ||
2699 | return !dwc3_gadget_ep_request_completed(req); | |
2700 | } | |
2701 | ||
ee3638b8 FB |
2702 | static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep, |
2703 | const struct dwc3_event_depevt *event) | |
2704 | { | |
f62afb49 | 2705 | dep->frame_number = event->parameters; |
ee3638b8 FB |
2706 | } |
2707 | ||
2e6e9e4b TN |
2708 | static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep, |
2709 | const struct dwc3_event_depevt *event, int status) | |
72246da4 | 2710 | { |
8f608e8a | 2711 | struct dwc3 *dwc = dep->dwc; |
2e6e9e4b | 2712 | bool no_started_trb = true; |
6d8a0196 | 2713 | |
5f2e7975 | 2714 | dwc3_gadget_ep_cleanup_completed_requests(dep, event, status); |
fae2b904 | 2715 | |
b6842d49 TN |
2716 | if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) |
2717 | goto out; | |
2718 | ||
2e6e9e4b | 2719 | if (status == -EXDEV && list_empty(&dep->started_list)) |
c5353b22 | 2720 | dwc3_stop_active_transfer(dep, true, true); |
d9feef97 | 2721 | else if (dwc3_gadget_ep_should_continue(dep)) |
2e6e9e4b TN |
2722 | if (__dwc3_gadget_kick_transfer(dep) == 0) |
2723 | no_started_trb = false; | |
6d8a0196 | 2724 | |
b6842d49 | 2725 | out: |
fae2b904 FB |
2726 | /* |
2727 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
2728 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
2729 | */ | |
9af21dd6 | 2730 | if (DWC3_VER_IS_PRIOR(DWC3, 183A)) { |
fae2b904 FB |
2731 | u32 reg; |
2732 | int i; | |
2733 | ||
2734 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 2735 | dep = dwc->eps[i]; |
fae2b904 FB |
2736 | |
2737 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
2738 | continue; | |
2739 | ||
aa3342c8 | 2740 | if (!list_empty(&dep->started_list)) |
2e6e9e4b | 2741 | return no_started_trb; |
fae2b904 FB |
2742 | } |
2743 | ||
2744 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2745 | reg |= dwc->u1u2; | |
2746 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2747 | ||
2748 | dwc->u1u2 = 0; | |
2749 | } | |
2e6e9e4b TN |
2750 | |
2751 | return no_started_trb; | |
2752 | } | |
2753 | ||
2754 | static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep, | |
2755 | const struct dwc3_event_depevt *event) | |
2756 | { | |
2757 | int status = 0; | |
2758 | ||
2759 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
2760 | dwc3_gadget_endpoint_frame_from_event(dep, event); | |
2761 | ||
2762 | if (event->status & DEPEVT_STATUS_BUSERR) | |
2763 | status = -ECONNRESET; | |
2764 | ||
2765 | if (event->status & DEPEVT_STATUS_MISSED_ISOC) | |
2766 | status = -EXDEV; | |
2767 | ||
2768 | dwc3_gadget_endpoint_trbs_complete(dep, event, status); | |
72246da4 FB |
2769 | } |
2770 | ||
3eaecd0c TN |
2771 | static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep, |
2772 | const struct dwc3_event_depevt *event) | |
2773 | { | |
2774 | int status = 0; | |
2775 | ||
2776 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; | |
2777 | ||
2778 | if (event->status & DEPEVT_STATUS_BUSERR) | |
2779 | status = -ECONNRESET; | |
2780 | ||
e0d19563 TN |
2781 | if (dwc3_gadget_endpoint_trbs_complete(dep, event, status)) |
2782 | dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE; | |
72246da4 FB |
2783 | } |
2784 | ||
8f608e8a FB |
2785 | static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep, |
2786 | const struct dwc3_event_depevt *event) | |
32033865 | 2787 | { |
ee3638b8 | 2788 | dwc3_gadget_endpoint_frame_from_event(dep, event); |
36f05d36 TN |
2789 | |
2790 | /* | |
2791 | * The XferNotReady event is generated only once before the endpoint | |
2792 | * starts. It will be generated again when END_TRANSFER command is | |
2793 | * issued. For some controller versions, the XferNotReady event may be | |
2794 | * generated while the END_TRANSFER command is still in process. Ignore | |
2795 | * it and wait for the next XferNotReady event after the command is | |
2796 | * completed. | |
2797 | */ | |
2798 | if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) | |
2799 | return; | |
2800 | ||
25abad6a | 2801 | (void) __dwc3_gadget_start_isoc(dep); |
32033865 FB |
2802 | } |
2803 | ||
140ca4cf TN |
2804 | static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep, |
2805 | const struct dwc3_event_depevt *event) | |
2806 | { | |
2807 | struct dwc3 *dwc = dep->dwc; | |
2808 | ||
2809 | if (event->status == DEPEVT_STREAMEVT_FOUND) { | |
2810 | dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED; | |
2811 | goto out; | |
2812 | } | |
2813 | ||
2814 | /* Note: NoStream rejection event param value is 0 and not 0xFFFF */ | |
2815 | switch (event->parameters) { | |
2816 | case DEPEVT_STREAM_PRIME: | |
2817 | /* | |
2818 | * If the host can properly transition the endpoint state from | |
2819 | * idle to prime after a NoStream rejection, there's no need to | |
2820 | * force restarting the endpoint to reinitiate the stream. To | |
2821 | * simplify the check, assume the host follows the USB spec if | |
2822 | * it primed the endpoint more than once. | |
2823 | */ | |
2824 | if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) { | |
2825 | if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED) | |
2826 | dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM; | |
2827 | else | |
2828 | dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED; | |
2829 | } | |
2830 | ||
2831 | break; | |
2832 | case DEPEVT_STREAM_NOSTREAM: | |
2833 | if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) || | |
2834 | !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) || | |
2835 | !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)) | |
2836 | break; | |
2837 | ||
2838 | /* | |
2839 | * If the host rejects a stream due to no active stream, by the | |
2840 | * USB and xHCI spec, the endpoint will be put back to idle | |
2841 | * state. When the host is ready (buffer added/updated), it will | |
2842 | * prime the endpoint to inform the usb device controller. This | |
2843 | * triggers the device controller to issue ERDY to restart the | |
2844 | * stream. However, some hosts don't follow this and keep the | |
2845 | * endpoint in the idle state. No prime will come despite host | |
2846 | * streams are updated, and the device controller will not be | |
2847 | * triggered to generate ERDY to move the next stream data. To | |
2848 | * workaround this and maintain compatibility with various | |
2849 | * hosts, force to reinitate the stream until the host is ready | |
2850 | * instead of waiting for the host to prime the endpoint. | |
2851 | */ | |
b10e1c25 TN |
2852 | if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) { |
2853 | unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME; | |
2854 | ||
2855 | dwc3_send_gadget_generic_command(dwc, cmd, dep->number); | |
2856 | } else { | |
2857 | dep->flags |= DWC3_EP_DELAY_START; | |
2858 | dwc3_stop_active_transfer(dep, true, true); | |
2859 | return; | |
2860 | } | |
2861 | break; | |
140ca4cf TN |
2862 | } |
2863 | ||
2864 | out: | |
2865 | dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM; | |
2866 | } | |
2867 | ||
72246da4 FB |
2868 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
2869 | const struct dwc3_event_depevt *event) | |
2870 | { | |
2871 | struct dwc3_ep *dep; | |
2872 | u8 epnum = event->endpoint_number; | |
76a638f8 | 2873 | u8 cmd; |
72246da4 FB |
2874 | |
2875 | dep = dwc->eps[epnum]; | |
2876 | ||
d7fd41c6 | 2877 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
3aec9915 | 2878 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) |
d7fd41c6 JD |
2879 | return; |
2880 | ||
2881 | /* Handle only EPCMDCMPLT when EP disabled */ | |
2882 | if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT) | |
2883 | return; | |
2884 | } | |
3336abb5 | 2885 | |
72246da4 FB |
2886 | if (epnum == 0 || epnum == 1) { |
2887 | dwc3_ep0_interrupt(dwc, event); | |
2888 | return; | |
2889 | } | |
2890 | ||
2891 | switch (event->endpoint_event) { | |
72246da4 | 2892 | case DWC3_DEPEVT_XFERINPROGRESS: |
8f608e8a | 2893 | dwc3_gadget_endpoint_transfer_in_progress(dep, event); |
72246da4 FB |
2894 | break; |
2895 | case DWC3_DEPEVT_XFERNOTREADY: | |
8f608e8a | 2896 | dwc3_gadget_endpoint_transfer_not_ready(dep, event); |
879631aa | 2897 | break; |
72246da4 | 2898 | case DWC3_DEPEVT_EPCMDCMPLT: |
76a638f8 BW |
2899 | cmd = DEPEVT_PARAMETER_CMD(event->parameters); |
2900 | ||
2901 | if (cmd == DWC3_DEPCMD_ENDTRANSFER) { | |
c58d8bfc | 2902 | dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; |
3aec9915 | 2903 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; |
fec9095b | 2904 | dwc3_gadget_ep_cleanup_cancelled_requests(dep); |
da10bcdd TN |
2905 | if ((dep->flags & DWC3_EP_DELAY_START) && |
2906 | !usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
2907 | __dwc3_gadget_kick_transfer(dep); | |
2908 | ||
2909 | dep->flags &= ~DWC3_EP_DELAY_START; | |
76a638f8 BW |
2910 | } |
2911 | break; | |
742a4fff | 2912 | case DWC3_DEPEVT_XFERCOMPLETE: |
3eaecd0c TN |
2913 | dwc3_gadget_endpoint_transfer_complete(dep, event); |
2914 | break; | |
2915 | case DWC3_DEPEVT_STREAMEVT: | |
140ca4cf TN |
2916 | dwc3_gadget_endpoint_stream_event(dep, event); |
2917 | break; | |
76a638f8 | 2918 | case DWC3_DEPEVT_RXTXFIFOEVT: |
72246da4 FB |
2919 | break; |
2920 | } | |
2921 | } | |
2922 | ||
2923 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
2924 | { | |
2925 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
2926 | spin_unlock(&dwc->lock); | |
2927 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
2928 | spin_lock(&dwc->lock); | |
2929 | } | |
2930 | } | |
2931 | ||
bc5ba2e0 FB |
2932 | static void dwc3_suspend_gadget(struct dwc3 *dwc) |
2933 | { | |
73a30bfc | 2934 | if (dwc->gadget_driver && dwc->gadget_driver->suspend) { |
bc5ba2e0 FB |
2935 | spin_unlock(&dwc->lock); |
2936 | dwc->gadget_driver->suspend(&dwc->gadget); | |
2937 | spin_lock(&dwc->lock); | |
2938 | } | |
2939 | } | |
2940 | ||
2941 | static void dwc3_resume_gadget(struct dwc3 *dwc) | |
2942 | { | |
73a30bfc | 2943 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
bc5ba2e0 FB |
2944 | spin_unlock(&dwc->lock); |
2945 | dwc->gadget_driver->resume(&dwc->gadget); | |
5c7b3b02 | 2946 | spin_lock(&dwc->lock); |
8e74475b FB |
2947 | } |
2948 | } | |
2949 | ||
2950 | static void dwc3_reset_gadget(struct dwc3 *dwc) | |
2951 | { | |
2952 | if (!dwc->gadget_driver) | |
2953 | return; | |
2954 | ||
2955 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) { | |
2956 | spin_unlock(&dwc->lock); | |
2957 | usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver); | |
bc5ba2e0 FB |
2958 | spin_lock(&dwc->lock); |
2959 | } | |
2960 | } | |
2961 | ||
c5353b22 FB |
2962 | static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, |
2963 | bool interrupt) | |
72246da4 | 2964 | { |
72246da4 FB |
2965 | struct dwc3_gadget_ep_cmd_params params; |
2966 | u32 cmd; | |
2967 | int ret; | |
2968 | ||
c58d8bfc TN |
2969 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) || |
2970 | (dep->flags & DWC3_EP_END_TRANSFER_PENDING)) | |
3daf74d7 PA |
2971 | return; |
2972 | ||
57911504 PA |
2973 | /* |
2974 | * NOTICE: We are violating what the Databook says about the | |
2975 | * EndTransfer command. Ideally we would _always_ wait for the | |
2976 | * EndTransfer Command Completion IRQ, but that's causing too | |
2977 | * much trouble synchronizing between us and gadget driver. | |
2978 | * | |
2979 | * We have discussed this with the IP Provider and it was | |
cf2f8b63 | 2980 | * suggested to giveback all requests here. |
57911504 PA |
2981 | * |
2982 | * Note also that a similar handling was tested by Synopsys | |
2983 | * (thanks a lot Paul) and nothing bad has come out of it. | |
cf2f8b63 TN |
2984 | * In short, what we're doing is issuing EndTransfer with |
2985 | * CMDIOC bit set and delay kicking transfer until the | |
2986 | * EndTransfer command had completed. | |
06281d46 JY |
2987 | * |
2988 | * As of IP version 3.10a of the DWC_usb3 IP, the controller | |
2989 | * supports a mode to work around the above limitation. The | |
2990 | * software can poll the CMDACT bit in the DEPCMD register | |
2991 | * after issuing a EndTransfer command. This mode is enabled | |
2992 | * by writing GUCTL2[14]. This polling is already done in the | |
2993 | * dwc3_send_gadget_ep_cmd() function so if the mode is | |
2994 | * enabled, the EndTransfer command will have completed upon | |
cf2f8b63 | 2995 | * returning from this function. |
06281d46 JY |
2996 | * |
2997 | * This mode is NOT available on the DWC_usb31 IP. | |
57911504 PA |
2998 | */ |
2999 | ||
3daf74d7 | 3000 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
b992e681 | 3001 | cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; |
c5353b22 | 3002 | cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0; |
b4996a86 | 3003 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 | 3004 | memset(¶ms, 0, sizeof(params)); |
2cd4718d | 3005 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
3daf74d7 | 3006 | WARN_ON_ONCE(ret); |
b4996a86 | 3007 | dep->resource_index = 0; |
06281d46 | 3008 | |
140ca4cf TN |
3009 | /* |
3010 | * The END_TRANSFER command will cause the controller to generate a | |
3011 | * NoStream Event, and it's not due to the host DP NoStream rejection. | |
3012 | * Ignore the next NoStream event. | |
3013 | */ | |
3014 | if (dep->stream_capable) | |
3015 | dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM; | |
3016 | ||
d3abda5a TN |
3017 | if (!interrupt) |
3018 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; | |
c58d8bfc TN |
3019 | else |
3020 | dep->flags |= DWC3_EP_END_TRANSFER_PENDING; | |
72246da4 FB |
3021 | } |
3022 | ||
72246da4 FB |
3023 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) |
3024 | { | |
3025 | u32 epnum; | |
3026 | ||
3027 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
3028 | struct dwc3_ep *dep; | |
72246da4 FB |
3029 | int ret; |
3030 | ||
3031 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
3032 | if (!dep) |
3033 | continue; | |
72246da4 FB |
3034 | |
3035 | if (!(dep->flags & DWC3_EP_STALL)) | |
3036 | continue; | |
3037 | ||
3038 | dep->flags &= ~DWC3_EP_STALL; | |
3039 | ||
50c763f8 | 3040 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 FB |
3041 | WARN_ON_ONCE(ret); |
3042 | } | |
3043 | } | |
3044 | ||
3045 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
3046 | { | |
c4430a26 FB |
3047 | int reg; |
3048 | ||
1b6009ea TN |
3049 | dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET); |
3050 | ||
72246da4 FB |
3051 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
3052 | reg &= ~DWC3_DCTL_INITU1ENA; | |
72246da4 | 3053 | reg &= ~DWC3_DCTL_INITU2ENA; |
5b738211 | 3054 | dwc3_gadget_dctl_write_safe(dwc, reg); |
72246da4 | 3055 | |
72246da4 FB |
3056 | dwc3_disconnect_gadget(dwc); |
3057 | ||
3058 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
df62df56 | 3059 | dwc->setup_packet_pending = false; |
06a374ed | 3060 | usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED); |
fc8bb91b FB |
3061 | |
3062 | dwc->connected = false; | |
72246da4 FB |
3063 | } |
3064 | ||
72246da4 FB |
3065 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
3066 | { | |
3067 | u32 reg; | |
3068 | ||
fc8bb91b FB |
3069 | dwc->connected = true; |
3070 | ||
df62df56 FB |
3071 | /* |
3072 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
3073 | * would cause a missing Disconnect Event if there's a | |
3074 | * pending Setup Packet in the FIFO. | |
3075 | * | |
3076 | * There's no suggested workaround on the official Bug | |
3077 | * report, which states that "unless the driver/application | |
3078 | * is doing any special handling of a disconnect event, | |
3079 | * there is no functional issue". | |
3080 | * | |
3081 | * Unfortunately, it turns out that we _do_ some special | |
3082 | * handling of a disconnect event, namely complete all | |
3083 | * pending transfers, notify gadget driver of the | |
3084 | * disconnection, and so on. | |
3085 | * | |
3086 | * Our suggested workaround is to follow the Disconnect | |
3087 | * Event steps here, instead, based on a setup_packet_pending | |
b5d335e5 FB |
3088 | * flag. Such flag gets set whenever we have a SETUP_PENDING |
3089 | * status for EP0 TRBs and gets cleared on XferComplete for the | |
df62df56 FB |
3090 | * same endpoint. |
3091 | * | |
3092 | * Refers to: | |
3093 | * | |
3094 | * STAR#9000466709: RTL: Device : Disconnect event not | |
3095 | * generated if setup packet pending in FIFO | |
3096 | */ | |
9af21dd6 | 3097 | if (DWC3_VER_IS_PRIOR(DWC3, 188A)) { |
df62df56 FB |
3098 | if (dwc->setup_packet_pending) |
3099 | dwc3_gadget_disconnect_interrupt(dwc); | |
3100 | } | |
3101 | ||
8e74475b | 3102 | dwc3_reset_gadget(dwc); |
72246da4 FB |
3103 | |
3104 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3105 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
5b738211 | 3106 | dwc3_gadget_dctl_write_safe(dwc, reg); |
3b637367 | 3107 | dwc->test_mode = false; |
72246da4 FB |
3108 | dwc3_clear_stall_all_ep(dwc); |
3109 | ||
3110 | /* Reset device address to zero */ | |
3111 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
3112 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
3113 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
3114 | } |
3115 | ||
72246da4 FB |
3116 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
3117 | { | |
72246da4 FB |
3118 | struct dwc3_ep *dep; |
3119 | int ret; | |
3120 | u32 reg; | |
3121 | u8 speed; | |
3122 | ||
72246da4 FB |
3123 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
3124 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
3125 | dwc->speed = speed; | |
3126 | ||
5fb6fdaf JY |
3127 | /* |
3128 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
3129 | * each time on Connect Done. | |
3130 | * | |
3131 | * Currently we always use the reset value. If any platform | |
3132 | * wants to set this to a different value, we need to add a | |
3133 | * setting and update GCTL.RAMCLKSEL here. | |
3134 | */ | |
72246da4 FB |
3135 | |
3136 | switch (speed) { | |
2da9ad76 | 3137 | case DWC3_DSTS_SUPERSPEED_PLUS: |
7580862b JY |
3138 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
3139 | dwc->gadget.ep0->maxpacket = 512; | |
3140 | dwc->gadget.speed = USB_SPEED_SUPER_PLUS; | |
3141 | break; | |
2da9ad76 | 3142 | case DWC3_DSTS_SUPERSPEED: |
05870c5b FB |
3143 | /* |
3144 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
3145 | * would cause a missing USB3 Reset event. | |
3146 | * | |
3147 | * In such situations, we should force a USB3 Reset | |
3148 | * event by calling our dwc3_gadget_reset_interrupt() | |
3149 | * routine. | |
3150 | * | |
3151 | * Refers to: | |
3152 | * | |
3153 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
3154 | * not be generated always when the link enters poll | |
3155 | */ | |
9af21dd6 | 3156 | if (DWC3_VER_IS_PRIOR(DWC3, 190A)) |
05870c5b FB |
3157 | dwc3_gadget_reset_interrupt(dwc); |
3158 | ||
72246da4 FB |
3159 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
3160 | dwc->gadget.ep0->maxpacket = 512; | |
3161 | dwc->gadget.speed = USB_SPEED_SUPER; | |
3162 | break; | |
2da9ad76 | 3163 | case DWC3_DSTS_HIGHSPEED: |
72246da4 FB |
3164 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
3165 | dwc->gadget.ep0->maxpacket = 64; | |
3166 | dwc->gadget.speed = USB_SPEED_HIGH; | |
3167 | break; | |
9418ee15 | 3168 | case DWC3_DSTS_FULLSPEED: |
72246da4 FB |
3169 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
3170 | dwc->gadget.ep0->maxpacket = 64; | |
3171 | dwc->gadget.speed = USB_SPEED_FULL; | |
3172 | break; | |
2da9ad76 | 3173 | case DWC3_DSTS_LOWSPEED: |
72246da4 FB |
3174 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); |
3175 | dwc->gadget.ep0->maxpacket = 8; | |
3176 | dwc->gadget.speed = USB_SPEED_LOW; | |
3177 | break; | |
3178 | } | |
3179 | ||
61800263 TN |
3180 | dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket; |
3181 | ||
2b758350 PA |
3182 | /* Enable USB2 LPM Capability */ |
3183 | ||
9af21dd6 | 3184 | if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) && |
2da9ad76 JY |
3185 | (speed != DWC3_DSTS_SUPERSPEED) && |
3186 | (speed != DWC3_DSTS_SUPERSPEED_PLUS)) { | |
2b758350 PA |
3187 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
3188 | reg |= DWC3_DCFG_LPM_CAP; | |
3189 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
3190 | ||
3191 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3192 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
3193 | ||
16fe4f30 TN |
3194 | reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold | |
3195 | (dwc->is_utmi_l1_suspend << 4)); | |
2b758350 | 3196 | |
80caf7d2 HR |
3197 | /* |
3198 | * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and | |
3199 | * DCFG.LPMCap is set, core responses with an ACK and the | |
3200 | * BESL value in the LPM token is less than or equal to LPM | |
3201 | * NYET threshold. | |
3202 | */ | |
9af21dd6 | 3203 | WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum, |
9165dabb | 3204 | "LPM Erratum not available on dwc3 revisions < 2.40a\n"); |
80caf7d2 | 3205 | |
9af21dd6 | 3206 | if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A)) |
2e487d28 | 3207 | reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold); |
80caf7d2 | 3208 | |
5b738211 | 3209 | dwc3_gadget_dctl_write_safe(dwc, reg); |
356363bf FB |
3210 | } else { |
3211 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3212 | reg &= ~DWC3_DCTL_HIRD_THRES_MASK; | |
5b738211 | 3213 | dwc3_gadget_dctl_write_safe(dwc, reg); |
2b758350 PA |
3214 | } |
3215 | ||
72246da4 | 3216 | dep = dwc->eps[0]; |
a2d23f08 | 3217 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY); |
72246da4 FB |
3218 | if (ret) { |
3219 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
3220 | return; | |
3221 | } | |
3222 | ||
3223 | dep = dwc->eps[1]; | |
a2d23f08 | 3224 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY); |
72246da4 FB |
3225 | if (ret) { |
3226 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
3227 | return; | |
3228 | } | |
3229 | ||
3230 | /* | |
3231 | * Configure PHY via GUSB3PIPECTLn if required. | |
3232 | * | |
3233 | * Update GTXFIFOSIZn | |
3234 | * | |
3235 | * In both cases reset values should be sufficient. | |
3236 | */ | |
3237 | } | |
3238 | ||
3239 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
3240 | { | |
72246da4 FB |
3241 | /* |
3242 | * TODO take core out of low power mode when that's | |
3243 | * implemented. | |
3244 | */ | |
3245 | ||
ad14d4e0 JL |
3246 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
3247 | spin_unlock(&dwc->lock); | |
3248 | dwc->gadget_driver->resume(&dwc->gadget); | |
3249 | spin_lock(&dwc->lock); | |
3250 | } | |
72246da4 FB |
3251 | } |
3252 | ||
3253 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
3254 | unsigned int evtinfo) | |
3255 | { | |
fae2b904 | 3256 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
3257 | unsigned int pwropt; |
3258 | ||
3259 | /* | |
3260 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
3261 | * Hibernation mode enabled which would show up when device detects | |
3262 | * host-initiated U3 exit. | |
3263 | * | |
3264 | * In that case, device will generate a Link State Change Interrupt | |
3265 | * from U3 to RESUME which is only necessary if Hibernation is | |
3266 | * configured in. | |
3267 | * | |
3268 | * There are no functional changes due to such spurious event and we | |
3269 | * just need to ignore it. | |
3270 | * | |
3271 | * Refers to: | |
3272 | * | |
3273 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
3274 | * operational mode | |
3275 | */ | |
3276 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
9af21dd6 | 3277 | if (DWC3_VER_IS_PRIOR(DWC3, 250A) && |
0b0cc1cd FB |
3278 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { |
3279 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
3280 | (next == DWC3_LINK_STATE_RESUME)) { | |
0b0cc1cd FB |
3281 | return; |
3282 | } | |
3283 | } | |
fae2b904 FB |
3284 | |
3285 | /* | |
3286 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
3287 | * on the link partner, the USB session might do multiple entry/exit | |
3288 | * of low power states before a transfer takes place. | |
3289 | * | |
3290 | * Due to this problem, we might experience lower throughput. The | |
3291 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
3292 | * transitioning from U1/U2 to U0 and enable those bits again | |
3293 | * after a transfer completes and there are no pending transfers | |
3294 | * on any of the enabled endpoints. | |
3295 | * | |
3296 | * This is the first half of that workaround. | |
3297 | * | |
3298 | * Refers to: | |
3299 | * | |
3300 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
3301 | * core send LGO_Ux entering U0 | |
3302 | */ | |
9af21dd6 | 3303 | if (DWC3_VER_IS_PRIOR(DWC3, 183A)) { |
fae2b904 FB |
3304 | if (next == DWC3_LINK_STATE_U0) { |
3305 | u32 u1u2; | |
3306 | u32 reg; | |
3307 | ||
3308 | switch (dwc->link_state) { | |
3309 | case DWC3_LINK_STATE_U1: | |
3310 | case DWC3_LINK_STATE_U2: | |
3311 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3312 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
3313 | | DWC3_DCTL_ACCEPTU2ENA | |
3314 | | DWC3_DCTL_INITU1ENA | |
3315 | | DWC3_DCTL_ACCEPTU1ENA); | |
3316 | ||
3317 | if (!dwc->u1u2) | |
3318 | dwc->u1u2 = reg & u1u2; | |
3319 | ||
3320 | reg &= ~u1u2; | |
3321 | ||
5b738211 | 3322 | dwc3_gadget_dctl_write_safe(dwc, reg); |
fae2b904 FB |
3323 | break; |
3324 | default: | |
3325 | /* do nothing */ | |
3326 | break; | |
3327 | } | |
3328 | } | |
3329 | } | |
3330 | ||
bc5ba2e0 FB |
3331 | switch (next) { |
3332 | case DWC3_LINK_STATE_U1: | |
3333 | if (dwc->speed == USB_SPEED_SUPER) | |
3334 | dwc3_suspend_gadget(dwc); | |
3335 | break; | |
3336 | case DWC3_LINK_STATE_U2: | |
3337 | case DWC3_LINK_STATE_U3: | |
3338 | dwc3_suspend_gadget(dwc); | |
3339 | break; | |
3340 | case DWC3_LINK_STATE_RESUME: | |
3341 | dwc3_resume_gadget(dwc); | |
3342 | break; | |
3343 | default: | |
3344 | /* do nothing */ | |
3345 | break; | |
3346 | } | |
3347 | ||
e57ebc1d | 3348 | dwc->link_state = next; |
72246da4 FB |
3349 | } |
3350 | ||
72704f87 BW |
3351 | static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc, |
3352 | unsigned int evtinfo) | |
3353 | { | |
3354 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; | |
3355 | ||
3356 | if (dwc->link_state != next && next == DWC3_LINK_STATE_U3) | |
3357 | dwc3_suspend_gadget(dwc); | |
3358 | ||
3359 | dwc->link_state = next; | |
3360 | } | |
3361 | ||
e1dadd3b FB |
3362 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, |
3363 | unsigned int evtinfo) | |
3364 | { | |
3365 | unsigned int is_ss = evtinfo & BIT(4); | |
3366 | ||
bfad65ee | 3367 | /* |
e1dadd3b FB |
3368 | * WORKAROUND: DWC3 revison 2.20a with hibernation support |
3369 | * have a known issue which can cause USB CV TD.9.23 to fail | |
3370 | * randomly. | |
3371 | * | |
3372 | * Because of this issue, core could generate bogus hibernation | |
3373 | * events which SW needs to ignore. | |
3374 | * | |
3375 | * Refers to: | |
3376 | * | |
3377 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
3378 | * Device Fallback from SuperSpeed | |
3379 | */ | |
3380 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
3381 | return; | |
3382 | ||
3383 | /* enter hibernation here */ | |
3384 | } | |
3385 | ||
72246da4 FB |
3386 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, |
3387 | const struct dwc3_event_devt *event) | |
3388 | { | |
3389 | switch (event->type) { | |
3390 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
3391 | dwc3_gadget_disconnect_interrupt(dwc); | |
3392 | break; | |
3393 | case DWC3_DEVICE_EVENT_RESET: | |
3394 | dwc3_gadget_reset_interrupt(dwc); | |
3395 | break; | |
3396 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
3397 | dwc3_gadget_conndone_interrupt(dwc); | |
3398 | break; | |
3399 | case DWC3_DEVICE_EVENT_WAKEUP: | |
3400 | dwc3_gadget_wakeup_interrupt(dwc); | |
3401 | break; | |
e1dadd3b FB |
3402 | case DWC3_DEVICE_EVENT_HIBER_REQ: |
3403 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
3404 | "unexpected hibernation event\n")) | |
3405 | break; | |
3406 | ||
3407 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
3408 | break; | |
72246da4 FB |
3409 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: |
3410 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
3411 | break; | |
3412 | case DWC3_DEVICE_EVENT_EOPF: | |
72704f87 | 3413 | /* It changed to be suspend event for version 2.30a and above */ |
9af21dd6 | 3414 | if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) { |
72704f87 BW |
3415 | /* |
3416 | * Ignore suspend event until the gadget enters into | |
3417 | * USB_STATE_CONFIGURED state. | |
3418 | */ | |
3419 | if (dwc->gadget.state >= USB_STATE_CONFIGURED) | |
3420 | dwc3_gadget_suspend_interrupt(dwc, | |
3421 | event->event_info); | |
3422 | } | |
72246da4 FB |
3423 | break; |
3424 | case DWC3_DEVICE_EVENT_SOF: | |
72246da4 | 3425 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: |
72246da4 | 3426 | case DWC3_DEVICE_EVENT_CMD_CMPL: |
72246da4 | 3427 | case DWC3_DEVICE_EVENT_OVERFLOW: |
72246da4 FB |
3428 | break; |
3429 | default: | |
e9f2aa87 | 3430 | dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type); |
72246da4 FB |
3431 | } |
3432 | } | |
3433 | ||
3434 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
3435 | const union dwc3_event *event) | |
3436 | { | |
43c96be1 | 3437 | trace_dwc3_event(event->raw, dwc); |
2c4cbe6e | 3438 | |
dfc5e805 FB |
3439 | if (!event->type.is_devspec) |
3440 | dwc3_endpoint_interrupt(dwc, &event->depevt); | |
3441 | else if (event->type.type == DWC3_EVENT_TYPE_DEV) | |
72246da4 | 3442 | dwc3_gadget_interrupt(dwc, &event->devt); |
dfc5e805 | 3443 | else |
72246da4 | 3444 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); |
72246da4 FB |
3445 | } |
3446 | ||
dea520a4 | 3447 | static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt) |
b15a762f | 3448 | { |
dea520a4 | 3449 | struct dwc3 *dwc = evt->dwc; |
b15a762f | 3450 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 3451 | int left; |
e8adfc30 | 3452 | u32 reg; |
b15a762f | 3453 | |
f42f2447 | 3454 | left = evt->count; |
b15a762f | 3455 | |
f42f2447 FB |
3456 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
3457 | return IRQ_NONE; | |
b15a762f | 3458 | |
f42f2447 FB |
3459 | while (left > 0) { |
3460 | union dwc3_event event; | |
b15a762f | 3461 | |
ebbb2d59 | 3462 | event.raw = *(u32 *) (evt->cache + evt->lpos); |
b15a762f | 3463 | |
f42f2447 | 3464 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 3465 | |
f42f2447 FB |
3466 | /* |
3467 | * FIXME we wrap around correctly to the next entry as | |
3468 | * almost all entries are 4 bytes in size. There is one | |
3469 | * entry which has 12 bytes which is a regular entry | |
3470 | * followed by 8 bytes data. ATM I don't know how | |
3471 | * things are organized if we get next to the a | |
3472 | * boundary so I worry about that once we try to handle | |
3473 | * that. | |
3474 | */ | |
caefe6c7 | 3475 | evt->lpos = (evt->lpos + 4) % evt->length; |
f42f2447 | 3476 | left -= 4; |
f42f2447 | 3477 | } |
b15a762f | 3478 | |
f42f2447 FB |
3479 | evt->count = 0; |
3480 | evt->flags &= ~DWC3_EVENT_PENDING; | |
3481 | ret = IRQ_HANDLED; | |
b15a762f | 3482 | |
f42f2447 | 3483 | /* Unmask interrupt */ |
660e9bde | 3484 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
f42f2447 | 3485 | reg &= ~DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 3486 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
b15a762f | 3487 | |
cf40b86b JY |
3488 | if (dwc->imod_interval) { |
3489 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); | |
3490 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); | |
3491 | } | |
3492 | ||
f42f2447 FB |
3493 | return ret; |
3494 | } | |
e8adfc30 | 3495 | |
dea520a4 | 3496 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt) |
f42f2447 | 3497 | { |
dea520a4 FB |
3498 | struct dwc3_event_buffer *evt = _evt; |
3499 | struct dwc3 *dwc = evt->dwc; | |
e5f68b4a | 3500 | unsigned long flags; |
f42f2447 | 3501 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 3502 | |
e5f68b4a | 3503 | spin_lock_irqsave(&dwc->lock, flags); |
dea520a4 | 3504 | ret = dwc3_process_event_buf(evt); |
e5f68b4a | 3505 | spin_unlock_irqrestore(&dwc->lock, flags); |
b15a762f FB |
3506 | |
3507 | return ret; | |
3508 | } | |
3509 | ||
dea520a4 | 3510 | static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) |
72246da4 | 3511 | { |
dea520a4 | 3512 | struct dwc3 *dwc = evt->dwc; |
ebbb2d59 | 3513 | u32 amount; |
72246da4 | 3514 | u32 count; |
e8adfc30 | 3515 | u32 reg; |
72246da4 | 3516 | |
fc8bb91b FB |
3517 | if (pm_runtime_suspended(dwc->dev)) { |
3518 | pm_runtime_get(dwc->dev); | |
3519 | disable_irq_nosync(dwc->irq_gadget); | |
3520 | dwc->pending_events = true; | |
3521 | return IRQ_HANDLED; | |
3522 | } | |
3523 | ||
d325a1de TN |
3524 | /* |
3525 | * With PCIe legacy interrupt, test shows that top-half irq handler can | |
3526 | * be called again after HW interrupt deassertion. Check if bottom-half | |
3527 | * irq event handler completes before caching new event to prevent | |
3528 | * losing events. | |
3529 | */ | |
3530 | if (evt->flags & DWC3_EVENT_PENDING) | |
3531 | return IRQ_HANDLED; | |
3532 | ||
660e9bde | 3533 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); |
72246da4 FB |
3534 | count &= DWC3_GEVNTCOUNT_MASK; |
3535 | if (!count) | |
3536 | return IRQ_NONE; | |
3537 | ||
b15a762f FB |
3538 | evt->count = count; |
3539 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 3540 | |
e8adfc30 | 3541 | /* Mask interrupt */ |
660e9bde | 3542 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
e8adfc30 | 3543 | reg |= DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 3544 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
e8adfc30 | 3545 | |
ebbb2d59 JY |
3546 | amount = min(count, evt->length - evt->lpos); |
3547 | memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount); | |
3548 | ||
3549 | if (amount < count) | |
3550 | memcpy(evt->cache, evt->buf, count - amount); | |
3551 | ||
65aca320 JY |
3552 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count); |
3553 | ||
b15a762f | 3554 | return IRQ_WAKE_THREAD; |
72246da4 FB |
3555 | } |
3556 | ||
dea520a4 | 3557 | static irqreturn_t dwc3_interrupt(int irq, void *_evt) |
72246da4 | 3558 | { |
dea520a4 | 3559 | struct dwc3_event_buffer *evt = _evt; |
72246da4 | 3560 | |
dea520a4 | 3561 | return dwc3_check_event_buf(evt); |
72246da4 FB |
3562 | } |
3563 | ||
6db3812e FB |
3564 | static int dwc3_gadget_get_irq(struct dwc3 *dwc) |
3565 | { | |
3566 | struct platform_device *dwc3_pdev = to_platform_device(dwc->dev); | |
3567 | int irq; | |
3568 | ||
f146b40b | 3569 | irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral"); |
6db3812e FB |
3570 | if (irq > 0) |
3571 | goto out; | |
3572 | ||
3573 | if (irq == -EPROBE_DEFER) | |
3574 | goto out; | |
3575 | ||
f146b40b | 3576 | irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3"); |
6db3812e FB |
3577 | if (irq > 0) |
3578 | goto out; | |
3579 | ||
3580 | if (irq == -EPROBE_DEFER) | |
3581 | goto out; | |
3582 | ||
3583 | irq = platform_get_irq(dwc3_pdev, 0); | |
3584 | if (irq > 0) | |
3585 | goto out; | |
3586 | ||
6db3812e FB |
3587 | if (!irq) |
3588 | irq = -EINVAL; | |
3589 | ||
3590 | out: | |
3591 | return irq; | |
3592 | } | |
3593 | ||
72246da4 | 3594 | /** |
bfad65ee | 3595 | * dwc3_gadget_init - initializes gadget related registers |
1d046793 | 3596 | * @dwc: pointer to our controller context structure |
72246da4 FB |
3597 | * |
3598 | * Returns 0 on success otherwise negative errno. | |
3599 | */ | |
41ac7b3a | 3600 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 3601 | { |
6db3812e FB |
3602 | int ret; |
3603 | int irq; | |
9522def4 | 3604 | |
6db3812e FB |
3605 | irq = dwc3_gadget_get_irq(dwc); |
3606 | if (irq < 0) { | |
3607 | ret = irq; | |
3608 | goto err0; | |
9522def4 RQ |
3609 | } |
3610 | ||
3611 | dwc->irq_gadget = irq; | |
72246da4 | 3612 | |
d64ff406 AB |
3613 | dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev, |
3614 | sizeof(*dwc->ep0_trb) * 2, | |
3615 | &dwc->ep0_trb_addr, GFP_KERNEL); | |
72246da4 FB |
3616 | if (!dwc->ep0_trb) { |
3617 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
3618 | ret = -ENOMEM; | |
7d5e650a | 3619 | goto err0; |
72246da4 FB |
3620 | } |
3621 | ||
4199c5f8 | 3622 | dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL); |
72246da4 | 3623 | if (!dwc->setup_buf) { |
72246da4 | 3624 | ret = -ENOMEM; |
7d5e650a | 3625 | goto err1; |
72246da4 FB |
3626 | } |
3627 | ||
905dc04e FB |
3628 | dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, |
3629 | &dwc->bounce_addr, GFP_KERNEL); | |
3630 | if (!dwc->bounce) { | |
3631 | ret = -ENOMEM; | |
d6e5a549 | 3632 | goto err2; |
905dc04e FB |
3633 | } |
3634 | ||
bb014736 BW |
3635 | init_completion(&dwc->ep0_in_setup); |
3636 | ||
72246da4 | 3637 | dwc->gadget.ops = &dwc3_gadget_ops; |
72246da4 | 3638 | dwc->gadget.speed = USB_SPEED_UNKNOWN; |
eeb720fb | 3639 | dwc->gadget.sg_supported = true; |
72246da4 | 3640 | dwc->gadget.name = "dwc3-gadget"; |
c729969b | 3641 | dwc->gadget.lpm_capable = true; |
72246da4 | 3642 | |
b9e51b2b BM |
3643 | /* |
3644 | * FIXME We might be setting max_speed to <SUPER, however versions | |
3645 | * <2.20a of dwc3 have an issue with metastability (documented | |
3646 | * elsewhere in this driver) which tells us we can't set max speed to | |
3647 | * anything lower than SUPER. | |
3648 | * | |
3649 | * Because gadget.max_speed is only used by composite.c and function | |
3650 | * drivers (i.e. it won't go into dwc3's registers) we are allowing this | |
3651 | * to happen so we avoid sending SuperSpeed Capability descriptor | |
3652 | * together with our BOS descriptor as that could confuse host into | |
3653 | * thinking we can handle super speed. | |
3654 | * | |
3655 | * Note that, in fact, we won't even support GetBOS requests when speed | |
3656 | * is less than super speed because we don't have means, yet, to tell | |
3657 | * composite.c that we are USB 2.0 + LPM ECN. | |
3658 | */ | |
9af21dd6 | 3659 | if (DWC3_VER_IS_PRIOR(DWC3, 220A) && |
42bf02ec | 3660 | !dwc->dis_metastability_quirk) |
5eb30ced | 3661 | dev_info(dwc->dev, "changing max_speed on rev %08x\n", |
b9e51b2b BM |
3662 | dwc->revision); |
3663 | ||
3664 | dwc->gadget.max_speed = dwc->maximum_speed; | |
3665 | ||
72246da4 FB |
3666 | /* |
3667 | * REVISIT: Here we should clear all pending IRQs to be | |
3668 | * sure we're starting from a well known location. | |
3669 | */ | |
3670 | ||
f3bcfc7e | 3671 | ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps); |
72246da4 | 3672 | if (ret) |
d6e5a549 | 3673 | goto err3; |
72246da4 | 3674 | |
72246da4 FB |
3675 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); |
3676 | if (ret) { | |
3677 | dev_err(dwc->dev, "failed to register udc\n"); | |
d6e5a549 | 3678 | goto err4; |
72246da4 FB |
3679 | } |
3680 | ||
169e3b68 RQ |
3681 | dwc3_gadget_set_speed(&dwc->gadget, dwc->maximum_speed); |
3682 | ||
72246da4 FB |
3683 | return 0; |
3684 | ||
7d5e650a | 3685 | err4: |
d6e5a549 | 3686 | dwc3_gadget_free_endpoints(dwc); |
04c03d10 | 3687 | |
7d5e650a | 3688 | err3: |
d6e5a549 FB |
3689 | dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce, |
3690 | dwc->bounce_addr); | |
5812b1c2 | 3691 | |
7d5e650a | 3692 | err2: |
0fc9a1be | 3693 | kfree(dwc->setup_buf); |
72246da4 | 3694 | |
7d5e650a | 3695 | err1: |
d64ff406 | 3696 | dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
3697 | dwc->ep0_trb, dwc->ep0_trb_addr); |
3698 | ||
72246da4 FB |
3699 | err0: |
3700 | return ret; | |
3701 | } | |
3702 | ||
7415f17c FB |
3703 | /* -------------------------------------------------------------------------- */ |
3704 | ||
72246da4 FB |
3705 | void dwc3_gadget_exit(struct dwc3 *dwc) |
3706 | { | |
72246da4 | 3707 | usb_del_gadget_udc(&dwc->gadget); |
72246da4 | 3708 | dwc3_gadget_free_endpoints(dwc); |
905dc04e | 3709 | dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce, |
d6e5a549 | 3710 | dwc->bounce_addr); |
0fc9a1be | 3711 | kfree(dwc->setup_buf); |
d64ff406 | 3712 | dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, |
d6e5a549 | 3713 | dwc->ep0_trb, dwc->ep0_trb_addr); |
72246da4 | 3714 | } |
7415f17c | 3715 | |
0b0231aa | 3716 | int dwc3_gadget_suspend(struct dwc3 *dwc) |
7415f17c | 3717 | { |
9772b47a RQ |
3718 | if (!dwc->gadget_driver) |
3719 | return 0; | |
3720 | ||
1551e35e | 3721 | dwc3_gadget_run_stop(dwc, false, false); |
9f8a67b6 FB |
3722 | dwc3_disconnect_gadget(dwc); |
3723 | __dwc3_gadget_stop(dwc); | |
7415f17c FB |
3724 | |
3725 | return 0; | |
3726 | } | |
3727 | ||
3728 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
3729 | { | |
7415f17c FB |
3730 | int ret; |
3731 | ||
9772b47a RQ |
3732 | if (!dwc->gadget_driver) |
3733 | return 0; | |
3734 | ||
9f8a67b6 FB |
3735 | ret = __dwc3_gadget_start(dwc); |
3736 | if (ret < 0) | |
7415f17c FB |
3737 | goto err0; |
3738 | ||
9f8a67b6 FB |
3739 | ret = dwc3_gadget_run_stop(dwc, true, false); |
3740 | if (ret < 0) | |
7415f17c FB |
3741 | goto err1; |
3742 | ||
7415f17c FB |
3743 | return 0; |
3744 | ||
3745 | err1: | |
9f8a67b6 | 3746 | __dwc3_gadget_stop(dwc); |
7415f17c FB |
3747 | |
3748 | err0: | |
3749 | return ret; | |
3750 | } | |
fc8bb91b FB |
3751 | |
3752 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc) | |
3753 | { | |
3754 | if (dwc->pending_events) { | |
3755 | dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf); | |
3756 | dwc->pending_events = false; | |
3757 | enable_irq(dwc->irq_gadget); | |
3758 | } | |
3759 | } |