Commit | Line | Data |
---|---|---|
5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
bfad65ee | 2 | /* |
72246da4 FB |
3 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link |
4 | * | |
5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
6 | * |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
72246da4 FB |
9 | */ |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/pm_runtime.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | ||
22 | #include <linux/usb/ch9.h> | |
23 | #include <linux/usb/gadget.h> | |
24 | ||
80977dc9 | 25 | #include "debug.h" |
72246da4 FB |
26 | #include "core.h" |
27 | #include "gadget.h" | |
28 | #include "io.h" | |
29 | ||
d5370106 | 30 | #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \ |
f62afb49 FB |
31 | & ~((d)->interval - 1)) |
32 | ||
04a9bfcd | 33 | /** |
bfad65ee | 34 | * dwc3_gadget_set_test_mode - enables usb2 test modes |
04a9bfcd FB |
35 | * @dwc: pointer to our context structure |
36 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
37 | * | |
bfad65ee FB |
38 | * Caller should take care of locking. This function will return 0 on |
39 | * success or -EINVAL if wrong Test Selector is passed. | |
04a9bfcd FB |
40 | */ |
41 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
42 | { | |
43 | u32 reg; | |
44 | ||
45 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
46 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
47 | ||
48 | switch (mode) { | |
49 | case TEST_J: | |
50 | case TEST_K: | |
51 | case TEST_SE0_NAK: | |
52 | case TEST_PACKET: | |
53 | case TEST_FORCE_EN: | |
54 | reg |= mode << 1; | |
55 | break; | |
56 | default: | |
57 | return -EINVAL; | |
58 | } | |
59 | ||
5b738211 | 60 | dwc3_gadget_dctl_write_safe(dwc, reg); |
04a9bfcd FB |
61 | |
62 | return 0; | |
63 | } | |
64 | ||
911f1f88 | 65 | /** |
bfad65ee | 66 | * dwc3_gadget_get_link_state - gets current state of usb link |
911f1f88 PZ |
67 | * @dwc: pointer to our context structure |
68 | * | |
69 | * Caller should take care of locking. This function will | |
70 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
71 | */ | |
72 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
73 | { | |
74 | u32 reg; | |
75 | ||
76 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
77 | ||
78 | return DWC3_DSTS_USBLNKST(reg); | |
79 | } | |
80 | ||
8598bde7 | 81 | /** |
bfad65ee | 82 | * dwc3_gadget_set_link_state - sets usb link to a particular state |
8598bde7 FB |
83 | * @dwc: pointer to our context structure |
84 | * @state: the state to put link into | |
85 | * | |
86 | * Caller should take care of locking. This function will | |
aee63e3c | 87 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
88 | */ |
89 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
90 | { | |
aee63e3c | 91 | int retries = 10000; |
8598bde7 FB |
92 | u32 reg; |
93 | ||
802fde98 PZ |
94 | /* |
95 | * Wait until device controller is ready. Only applies to 1.94a and | |
96 | * later RTL. | |
97 | */ | |
98 | if (dwc->revision >= DWC3_REVISION_194A) { | |
99 | while (--retries) { | |
100 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
101 | if (reg & DWC3_DSTS_DCNRD) | |
102 | udelay(5); | |
103 | else | |
104 | break; | |
105 | } | |
106 | ||
107 | if (retries <= 0) | |
108 | return -ETIMEDOUT; | |
109 | } | |
110 | ||
8598bde7 FB |
111 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
112 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
113 | ||
2e708fa3 TN |
114 | /* set no action before sending new link state change */ |
115 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
116 | ||
8598bde7 FB |
117 | /* set requested state */ |
118 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
119 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
120 | ||
802fde98 PZ |
121 | /* |
122 | * The following code is racy when called from dwc3_gadget_wakeup, | |
123 | * and is not needed, at least on newer versions | |
124 | */ | |
125 | if (dwc->revision >= DWC3_REVISION_194A) | |
126 | return 0; | |
127 | ||
8598bde7 | 128 | /* wait for a change in DSTS */ |
aed430e5 | 129 | retries = 10000; |
8598bde7 FB |
130 | while (--retries) { |
131 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
132 | ||
8598bde7 FB |
133 | if (DWC3_DSTS_USBLNKST(reg) == state) |
134 | return 0; | |
135 | ||
aee63e3c | 136 | udelay(5); |
8598bde7 FB |
137 | } |
138 | ||
8598bde7 FB |
139 | return -ETIMEDOUT; |
140 | } | |
141 | ||
dca0119c | 142 | /** |
bfad65ee FB |
143 | * dwc3_ep_inc_trb - increment a trb index. |
144 | * @index: Pointer to the TRB index to increment. | |
dca0119c JY |
145 | * |
146 | * The index should never point to the link TRB. After incrementing, | |
147 | * if it is point to the link TRB, wrap around to the beginning. The | |
148 | * link TRB is always at the last TRB entry. | |
149 | */ | |
150 | static void dwc3_ep_inc_trb(u8 *index) | |
457e84b6 | 151 | { |
dca0119c JY |
152 | (*index)++; |
153 | if (*index == (DWC3_TRB_NUM - 1)) | |
154 | *index = 0; | |
ef966b9d | 155 | } |
457e84b6 | 156 | |
bfad65ee FB |
157 | /** |
158 | * dwc3_ep_inc_enq - increment endpoint's enqueue pointer | |
159 | * @dep: The endpoint whose enqueue pointer we're incrementing | |
160 | */ | |
dca0119c | 161 | static void dwc3_ep_inc_enq(struct dwc3_ep *dep) |
ef966b9d | 162 | { |
dca0119c | 163 | dwc3_ep_inc_trb(&dep->trb_enqueue); |
ef966b9d | 164 | } |
457e84b6 | 165 | |
bfad65ee FB |
166 | /** |
167 | * dwc3_ep_inc_deq - increment endpoint's dequeue pointer | |
168 | * @dep: The endpoint whose enqueue pointer we're incrementing | |
169 | */ | |
dca0119c | 170 | static void dwc3_ep_inc_deq(struct dwc3_ep *dep) |
ef966b9d | 171 | { |
dca0119c | 172 | dwc3_ep_inc_trb(&dep->trb_dequeue); |
457e84b6 FB |
173 | } |
174 | ||
69102510 | 175 | static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep, |
c91815b5 | 176 | struct dwc3_request *req, int status) |
72246da4 FB |
177 | { |
178 | struct dwc3 *dwc = dep->dwc; | |
179 | ||
72246da4 | 180 | list_del(&req->list); |
e62c5bc5 | 181 | req->remaining = 0; |
bd674224 | 182 | req->needs_extra_trb = false; |
72246da4 FB |
183 | |
184 | if (req->request.status == -EINPROGRESS) | |
185 | req->request.status = status; | |
186 | ||
4a71fcb8 JP |
187 | if (req->trb) |
188 | usb_gadget_unmap_request_by_dev(dwc->sysdev, | |
c91815b5 | 189 | &req->request, req->direction); |
4a71fcb8 JP |
190 | |
191 | req->trb = NULL; | |
2c4cbe6e | 192 | trace_dwc3_gadget_giveback(req); |
72246da4 | 193 | |
c91815b5 FB |
194 | if (dep->number > 1) |
195 | pm_runtime_put(dwc->dev); | |
196 | } | |
197 | ||
198 | /** | |
199 | * dwc3_gadget_giveback - call struct usb_request's ->complete callback | |
200 | * @dep: The endpoint to whom the request belongs to | |
201 | * @req: The request we're giving back | |
202 | * @status: completion code for the request | |
203 | * | |
204 | * Must be called with controller's lock held and interrupts disabled. This | |
205 | * function will unmap @req and call its ->complete() callback to notify upper | |
206 | * layers that it has completed. | |
207 | */ | |
208 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, | |
209 | int status) | |
210 | { | |
211 | struct dwc3 *dwc = dep->dwc; | |
212 | ||
213 | dwc3_gadget_del_and_unmap_request(dep, req, status); | |
a3af5e3a | 214 | req->status = DWC3_REQUEST_STATUS_COMPLETED; |
c91815b5 | 215 | |
72246da4 | 216 | spin_unlock(&dwc->lock); |
304f7e5e | 217 | usb_gadget_giveback_request(&dep->endpoint, &req->request); |
72246da4 FB |
218 | spin_lock(&dwc->lock); |
219 | } | |
220 | ||
bfad65ee FB |
221 | /** |
222 | * dwc3_send_gadget_generic_command - issue a generic command for the controller | |
223 | * @dwc: pointer to the controller context | |
224 | * @cmd: the command to be issued | |
225 | * @param: command parameter | |
226 | * | |
227 | * Caller should take care of locking. Issue @cmd with a given @param to @dwc | |
228 | * and wait for its completion. | |
229 | */ | |
3ece0ec4 | 230 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param) |
b09bb642 FB |
231 | { |
232 | u32 timeout = 500; | |
71f7e702 | 233 | int status = 0; |
0fe886cd | 234 | int ret = 0; |
b09bb642 FB |
235 | u32 reg; |
236 | ||
237 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); | |
238 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
239 | ||
240 | do { | |
241 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
242 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
71f7e702 FB |
243 | status = DWC3_DGCMD_STATUS(reg); |
244 | if (status) | |
0fe886cd FB |
245 | ret = -EINVAL; |
246 | break; | |
b09bb642 | 247 | } |
e3aee486 | 248 | } while (--timeout); |
0fe886cd FB |
249 | |
250 | if (!timeout) { | |
0fe886cd | 251 | ret = -ETIMEDOUT; |
71f7e702 | 252 | status = -ETIMEDOUT; |
0fe886cd FB |
253 | } |
254 | ||
71f7e702 FB |
255 | trace_dwc3_gadget_generic_cmd(cmd, param, status); |
256 | ||
0fe886cd | 257 | return ret; |
b09bb642 FB |
258 | } |
259 | ||
c36d8e94 FB |
260 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc); |
261 | ||
bfad65ee FB |
262 | /** |
263 | * dwc3_send_gadget_ep_cmd - issue an endpoint command | |
264 | * @dep: the endpoint to which the command is going to be issued | |
265 | * @cmd: the command to be issued | |
266 | * @params: parameters to the command | |
267 | * | |
268 | * Caller should handle locking. This function will issue @cmd with given | |
269 | * @params to @dep and wait for its completion. | |
270 | */ | |
2cd4718d FB |
271 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, |
272 | struct dwc3_gadget_ep_cmd_params *params) | |
72246da4 | 273 | { |
8897a761 | 274 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
2cd4718d | 275 | struct dwc3 *dwc = dep->dwc; |
8722e095 | 276 | u32 timeout = 1000; |
87dd9611 | 277 | u32 saved_config = 0; |
72246da4 FB |
278 | u32 reg; |
279 | ||
0933df15 | 280 | int cmd_status = 0; |
c0ca324d | 281 | int ret = -EINVAL; |
72246da4 | 282 | |
2b0f11df | 283 | /* |
87dd9611 TN |
284 | * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or |
285 | * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an | |
286 | * endpoint command. | |
2b0f11df | 287 | * |
87dd9611 TN |
288 | * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY |
289 | * settings. Restore them after the command is completed. | |
290 | * | |
291 | * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2 | |
2b0f11df | 292 | */ |
ab2a92e7 FB |
293 | if (dwc->gadget.speed <= USB_SPEED_HIGH) { |
294 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
295 | if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) { | |
87dd9611 | 296 | saved_config |= DWC3_GUSB2PHYCFG_SUSPHY; |
ab2a92e7 | 297 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; |
ab2a92e7 | 298 | } |
87dd9611 TN |
299 | |
300 | if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) { | |
301 | saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM; | |
302 | reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; | |
303 | } | |
304 | ||
305 | if (saved_config) | |
306 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
2b0f11df FB |
307 | } |
308 | ||
5999914f | 309 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { |
c36d8e94 FB |
310 | int needs_wakeup; |
311 | ||
312 | needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 || | |
313 | dwc->link_state == DWC3_LINK_STATE_U2 || | |
314 | dwc->link_state == DWC3_LINK_STATE_U3); | |
315 | ||
316 | if (unlikely(needs_wakeup)) { | |
317 | ret = __dwc3_gadget_wakeup(dwc); | |
318 | dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n", | |
319 | ret); | |
320 | } | |
321 | } | |
322 | ||
2eb88016 FB |
323 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0); |
324 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1); | |
325 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2); | |
72246da4 | 326 | |
8897a761 FB |
327 | /* |
328 | * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're | |
329 | * not relying on XferNotReady, we can make use of a special "No | |
330 | * Response Update Transfer" command where we should clear both CmdAct | |
331 | * and CmdIOC bits. | |
332 | * | |
333 | * With this, we don't need to wait for command completion and can | |
334 | * straight away issue further commands to the endpoint. | |
335 | * | |
336 | * NOTICE: We're making an assumption that control endpoints will never | |
337 | * make use of Update Transfer command. This is a safe assumption | |
338 | * because we can never have more than one request at a time with | |
339 | * Control Endpoints. If anybody changes that assumption, this chunk | |
340 | * needs to be updated accordingly. | |
341 | */ | |
342 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER && | |
343 | !usb_endpoint_xfer_isoc(desc)) | |
344 | cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT); | |
345 | else | |
346 | cmd |= DWC3_DEPCMD_CMDACT; | |
347 | ||
348 | dwc3_writel(dep->regs, DWC3_DEPCMD, cmd); | |
72246da4 | 349 | do { |
2eb88016 | 350 | reg = dwc3_readl(dep->regs, DWC3_DEPCMD); |
72246da4 | 351 | if (!(reg & DWC3_DEPCMD_CMDACT)) { |
0933df15 | 352 | cmd_status = DWC3_DEPCMD_STATUS(reg); |
7b9cc7a2 | 353 | |
7b9cc7a2 KL |
354 | switch (cmd_status) { |
355 | case 0: | |
356 | ret = 0; | |
357 | break; | |
358 | case DEPEVT_TRANSFER_NO_RESOURCE: | |
f7ac582e TN |
359 | dev_WARN(dwc->dev, "No resource for %s\n", |
360 | dep->name); | |
7b9cc7a2 | 361 | ret = -EINVAL; |
c0ca324d | 362 | break; |
7b9cc7a2 KL |
363 | case DEPEVT_TRANSFER_BUS_EXPIRY: |
364 | /* | |
365 | * SW issues START TRANSFER command to | |
366 | * isochronous ep with future frame interval. If | |
367 | * future interval time has already passed when | |
368 | * core receives the command, it will respond | |
369 | * with an error status of 'Bus Expiry'. | |
370 | * | |
371 | * Instead of always returning -EINVAL, let's | |
372 | * give a hint to the gadget driver that this is | |
373 | * the case by returning -EAGAIN. | |
374 | */ | |
7b9cc7a2 KL |
375 | ret = -EAGAIN; |
376 | break; | |
377 | default: | |
378 | dev_WARN(dwc->dev, "UNKNOWN cmd status\n"); | |
379 | } | |
380 | ||
c0ca324d | 381 | break; |
72246da4 | 382 | } |
f6bb225b | 383 | } while (--timeout); |
72246da4 | 384 | |
f6bb225b | 385 | if (timeout == 0) { |
f6bb225b | 386 | ret = -ETIMEDOUT; |
0933df15 | 387 | cmd_status = -ETIMEDOUT; |
f6bb225b | 388 | } |
c0ca324d | 389 | |
0933df15 FB |
390 | trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status); |
391 | ||
9bc3395c TN |
392 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { |
393 | if (ret == 0) | |
394 | dep->flags |= DWC3_EP_TRANSFER_STARTED; | |
395 | ||
396 | if (ret != -ETIMEDOUT) | |
397 | dwc3_gadget_ep_get_transfer_index(dep); | |
6cb2e4e3 FB |
398 | } |
399 | ||
87dd9611 | 400 | if (saved_config) { |
2b0f11df | 401 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
87dd9611 | 402 | reg |= saved_config; |
2b0f11df FB |
403 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
404 | } | |
405 | ||
c0ca324d | 406 | return ret; |
72246da4 FB |
407 | } |
408 | ||
50c763f8 JY |
409 | static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep) |
410 | { | |
411 | struct dwc3 *dwc = dep->dwc; | |
412 | struct dwc3_gadget_ep_cmd_params params; | |
413 | u32 cmd = DWC3_DEPCMD_CLEARSTALL; | |
414 | ||
415 | /* | |
416 | * As of core revision 2.60a the recommended programming model | |
417 | * is to set the ClearPendIN bit when issuing a Clear Stall EP | |
418 | * command for IN endpoints. This is to prevent an issue where | |
419 | * some (non-compliant) hosts may not send ACK TPs for pending | |
420 | * IN transfers due to a mishandled error condition. Synopsys | |
421 | * STAR 9000614252. | |
422 | */ | |
5e6c88d2 LB |
423 | if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) && |
424 | (dwc->gadget.speed >= USB_SPEED_SUPER)) | |
50c763f8 JY |
425 | cmd |= DWC3_DEPCMD_CLEARPENDIN; |
426 | ||
427 | memset(¶ms, 0, sizeof(params)); | |
428 | ||
2cd4718d | 429 | return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
50c763f8 JY |
430 | } |
431 | ||
72246da4 | 432 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, |
f6bafc6a | 433 | struct dwc3_trb *trb) |
72246da4 | 434 | { |
c439ef87 | 435 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
436 | |
437 | return dep->trb_pool_dma + offset; | |
438 | } | |
439 | ||
440 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
441 | { | |
442 | struct dwc3 *dwc = dep->dwc; | |
443 | ||
444 | if (dep->trb_pool) | |
445 | return 0; | |
446 | ||
d64ff406 | 447 | dep->trb_pool = dma_alloc_coherent(dwc->sysdev, |
72246da4 FB |
448 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, |
449 | &dep->trb_pool_dma, GFP_KERNEL); | |
450 | if (!dep->trb_pool) { | |
451 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
452 | dep->name); | |
453 | return -ENOMEM; | |
454 | } | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
459 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
460 | { | |
461 | struct dwc3 *dwc = dep->dwc; | |
462 | ||
d64ff406 | 463 | dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, |
72246da4 FB |
464 | dep->trb_pool, dep->trb_pool_dma); |
465 | ||
466 | dep->trb_pool = NULL; | |
467 | dep->trb_pool_dma = 0; | |
468 | } | |
469 | ||
20d1d43f FB |
470 | static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep) |
471 | { | |
472 | struct dwc3_gadget_ep_cmd_params params; | |
473 | ||
474 | memset(¶ms, 0x00, sizeof(params)); | |
475 | ||
476 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); | |
477 | ||
478 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE, | |
479 | ¶ms); | |
480 | } | |
c4509601 JY |
481 | |
482 | /** | |
bfad65ee | 483 | * dwc3_gadget_start_config - configure ep resources |
c4509601 JY |
484 | * @dep: endpoint that is being enabled |
485 | * | |
bfad65ee FB |
486 | * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's |
487 | * completion, it will set Transfer Resource for all available endpoints. | |
c4509601 | 488 | * |
bfad65ee FB |
489 | * The assignment of transfer resources cannot perfectly follow the data book |
490 | * due to the fact that the controller driver does not have all knowledge of the | |
491 | * configuration in advance. It is given this information piecemeal by the | |
492 | * composite gadget framework after every SET_CONFIGURATION and | |
493 | * SET_INTERFACE. Trying to follow the databook programming model in this | |
494 | * scenario can cause errors. For two reasons: | |
c4509601 | 495 | * |
bfad65ee FB |
496 | * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every |
497 | * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is | |
498 | * incorrect in the scenario of multiple interfaces. | |
499 | * | |
500 | * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new | |
c4509601 JY |
501 | * endpoint on alt setting (8.1.6). |
502 | * | |
503 | * The following simplified method is used instead: | |
504 | * | |
bfad65ee FB |
505 | * All hardware endpoints can be assigned a transfer resource and this setting |
506 | * will stay persistent until either a core reset or hibernation. So whenever we | |
507 | * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do | |
508 | * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are | |
c4509601 JY |
509 | * guaranteed that there are as many transfer resources as endpoints. |
510 | * | |
bfad65ee FB |
511 | * This function is called for each endpoint when it is being enabled but is |
512 | * triggered only when called for EP0-out, which always happens first, and which | |
513 | * should only happen in one of the above conditions. | |
c4509601 | 514 | */ |
b07c2db8 | 515 | static int dwc3_gadget_start_config(struct dwc3_ep *dep) |
72246da4 FB |
516 | { |
517 | struct dwc3_gadget_ep_cmd_params params; | |
b07c2db8 | 518 | struct dwc3 *dwc; |
72246da4 | 519 | u32 cmd; |
c4509601 JY |
520 | int i; |
521 | int ret; | |
522 | ||
523 | if (dep->number) | |
524 | return 0; | |
72246da4 FB |
525 | |
526 | memset(¶ms, 0x00, sizeof(params)); | |
c4509601 | 527 | cmd = DWC3_DEPCMD_DEPSTARTCFG; |
b07c2db8 | 528 | dwc = dep->dwc; |
72246da4 | 529 | |
2cd4718d | 530 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
c4509601 JY |
531 | if (ret) |
532 | return ret; | |
533 | ||
534 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
535 | struct dwc3_ep *dep = dwc->eps[i]; | |
72246da4 | 536 | |
c4509601 JY |
537 | if (!dep) |
538 | continue; | |
539 | ||
b07c2db8 | 540 | ret = dwc3_gadget_set_xfer_resource(dep); |
c4509601 JY |
541 | if (ret) |
542 | return ret; | |
72246da4 FB |
543 | } |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
b07c2db8 | 548 | static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action) |
72246da4 | 549 | { |
39ebb05c JY |
550 | const struct usb_ss_ep_comp_descriptor *comp_desc; |
551 | const struct usb_endpoint_descriptor *desc; | |
72246da4 | 552 | struct dwc3_gadget_ep_cmd_params params; |
b07c2db8 | 553 | struct dwc3 *dwc = dep->dwc; |
72246da4 | 554 | |
39ebb05c JY |
555 | comp_desc = dep->endpoint.comp_desc; |
556 | desc = dep->endpoint.desc; | |
557 | ||
72246da4 FB |
558 | memset(¶ms, 0x00, sizeof(params)); |
559 | ||
dc1c70a7 | 560 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
561 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
562 | ||
563 | /* Burst size is only needed in SuperSpeed mode */ | |
ee5cd41c | 564 | if (dwc->gadget.speed >= USB_SPEED_SUPER) { |
676e3497 | 565 | u32 burst = dep->endpoint.maxburst; |
676e3497 | 566 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1); |
d2e9a13a | 567 | } |
72246da4 | 568 | |
a2d23f08 FB |
569 | params.param0 |= action; |
570 | if (action == DWC3_DEPCFG_ACTION_RESTORE) | |
265b70a7 | 571 | params.param2 |= dep->saved_state; |
265b70a7 | 572 | |
4bc48c97 FB |
573 | if (usb_endpoint_xfer_control(desc)) |
574 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN; | |
13fa2e69 FB |
575 | |
576 | if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc)) | |
577 | params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 578 | |
18b7ede5 | 579 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 FB |
580 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
581 | | DWC3_DEPCFG_STREAM_EVENT_EN; | |
879631aa FB |
582 | dep->stream_capable = true; |
583 | } | |
584 | ||
0b93a4c8 | 585 | if (!usb_endpoint_xfer_control(desc)) |
dc1c70a7 | 586 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
587 | |
588 | /* | |
589 | * We are doing 1:1 mapping for endpoints, meaning | |
590 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
591 | * so on. We consider the direction bit as part of the physical | |
592 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
593 | */ | |
dc1c70a7 | 594 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
595 | |
596 | /* | |
597 | * We must use the lower 16 TX FIFOs even though | |
598 | * HW might have more | |
599 | */ | |
600 | if (dep->direction) | |
dc1c70a7 | 601 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
602 | |
603 | if (desc->bInterval) { | |
dc1c70a7 | 604 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
72246da4 FB |
605 | dep->interval = 1 << (desc->bInterval - 1); |
606 | } | |
607 | ||
2cd4718d | 608 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms); |
72246da4 FB |
609 | } |
610 | ||
72246da4 | 611 | /** |
bfad65ee | 612 | * __dwc3_gadget_ep_enable - initializes a hw endpoint |
72246da4 | 613 | * @dep: endpoint to be initialized |
a2d23f08 | 614 | * @action: one of INIT, MODIFY or RESTORE |
72246da4 | 615 | * |
bfad65ee FB |
616 | * Caller should take care of locking. Execute all necessary commands to |
617 | * initialize a HW endpoint so it can be used by a gadget driver. | |
72246da4 | 618 | */ |
a2d23f08 | 619 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) |
72246da4 | 620 | { |
39ebb05c | 621 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
72246da4 | 622 | struct dwc3 *dwc = dep->dwc; |
39ebb05c | 623 | |
72246da4 | 624 | u32 reg; |
b09e99ee | 625 | int ret; |
72246da4 FB |
626 | |
627 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
b07c2db8 | 628 | ret = dwc3_gadget_start_config(dep); |
72246da4 FB |
629 | if (ret) |
630 | return ret; | |
631 | } | |
632 | ||
b07c2db8 | 633 | ret = dwc3_gadget_set_ep_config(dep, action); |
72246da4 FB |
634 | if (ret) |
635 | return ret; | |
636 | ||
637 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
638 | struct dwc3_trb *trb_st_hw; |
639 | struct dwc3_trb *trb_link; | |
72246da4 | 640 | |
72246da4 FB |
641 | dep->type = usb_endpoint_type(desc); |
642 | dep->flags |= DWC3_EP_ENABLED; | |
643 | ||
644 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
645 | reg |= DWC3_DALEPENA_EP(dep->number); | |
646 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
647 | ||
36b68aae | 648 | if (usb_endpoint_xfer_control(desc)) |
2870e501 | 649 | goto out; |
72246da4 | 650 | |
0d25744a JY |
651 | /* Initialize the TRB ring */ |
652 | dep->trb_dequeue = 0; | |
653 | dep->trb_enqueue = 0; | |
654 | memset(dep->trb_pool, 0, | |
655 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM); | |
656 | ||
36b68aae | 657 | /* Link TRB. The HWO bit is never reset */ |
72246da4 FB |
658 | trb_st_hw = &dep->trb_pool[0]; |
659 | ||
f6bafc6a | 660 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
f6bafc6a FB |
661 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
662 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
663 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
664 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
665 | } |
666 | ||
a97ea994 FB |
667 | /* |
668 | * Issue StartTransfer here with no-op TRB so we can always rely on No | |
669 | * Response Update Transfer command. | |
670 | */ | |
26d62b4d | 671 | if ((usb_endpoint_xfer_bulk(desc) && !dep->stream_capable) || |
52fcc0be | 672 | usb_endpoint_xfer_int(desc)) { |
a97ea994 FB |
673 | struct dwc3_gadget_ep_cmd_params params; |
674 | struct dwc3_trb *trb; | |
675 | dma_addr_t trb_dma; | |
676 | u32 cmd; | |
677 | ||
678 | memset(¶ms, 0, sizeof(params)); | |
679 | trb = &dep->trb_pool[0]; | |
680 | trb_dma = dwc3_trb_dma_offset(dep, trb); | |
681 | ||
682 | params.param0 = upper_32_bits(trb_dma); | |
683 | params.param1 = lower_32_bits(trb_dma); | |
684 | ||
685 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
686 | ||
687 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
688 | if (ret < 0) | |
689 | return ret; | |
a97ea994 FB |
690 | } |
691 | ||
2870e501 FB |
692 | out: |
693 | trace_dwc3_gadget_ep_enable(dep); | |
694 | ||
72246da4 FB |
695 | return 0; |
696 | } | |
697 | ||
c5353b22 FB |
698 | static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, |
699 | bool interrupt); | |
624407f9 | 700 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) |
72246da4 FB |
701 | { |
702 | struct dwc3_request *req; | |
703 | ||
c5353b22 | 704 | dwc3_stop_active_transfer(dep, true, false); |
624407f9 | 705 | |
0e146028 FB |
706 | /* - giveback all requests to gadget driver */ |
707 | while (!list_empty(&dep->started_list)) { | |
708 | req = next_request(&dep->started_list); | |
1591633e | 709 | |
0e146028 | 710 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
ea53b882 FB |
711 | } |
712 | ||
aa3342c8 FB |
713 | while (!list_empty(&dep->pending_list)) { |
714 | req = next_request(&dep->pending_list); | |
72246da4 | 715 | |
d8eca64e FB |
716 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
717 | } | |
718 | ||
719 | while (!list_empty(&dep->cancelled_list)) { | |
720 | req = next_request(&dep->cancelled_list); | |
721 | ||
624407f9 | 722 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 723 | } |
72246da4 FB |
724 | } |
725 | ||
726 | /** | |
bfad65ee | 727 | * __dwc3_gadget_ep_disable - disables a hw endpoint |
72246da4 FB |
728 | * @dep: the endpoint to disable |
729 | * | |
bfad65ee FB |
730 | * This function undoes what __dwc3_gadget_ep_enable did and also removes |
731 | * requests which are currently being processed by the hardware and those which | |
732 | * are not yet scheduled. | |
733 | * | |
624407f9 | 734 | * Caller should take care of locking. |
72246da4 | 735 | */ |
72246da4 FB |
736 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
737 | { | |
738 | struct dwc3 *dwc = dep->dwc; | |
739 | u32 reg; | |
740 | ||
2870e501 | 741 | trace_dwc3_gadget_ep_disable(dep); |
7eaeac5c | 742 | |
624407f9 | 743 | dwc3_remove_requests(dwc, dep); |
72246da4 | 744 | |
687ef981 FB |
745 | /* make sure HW endpoint isn't stalled */ |
746 | if (dep->flags & DWC3_EP_STALL) | |
7a608559 | 747 | __dwc3_gadget_ep_set_halt(dep, 0, false); |
687ef981 | 748 | |
72246da4 FB |
749 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
750 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
751 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
752 | ||
879631aa | 753 | dep->stream_capable = false; |
72246da4 | 754 | dep->type = 0; |
3aec9915 | 755 | dep->flags = 0; |
72246da4 | 756 | |
39ebb05c JY |
757 | /* Clear out the ep descriptors for non-ep0 */ |
758 | if (dep->number > 1) { | |
759 | dep->endpoint.comp_desc = NULL; | |
760 | dep->endpoint.desc = NULL; | |
761 | } | |
762 | ||
72246da4 FB |
763 | return 0; |
764 | } | |
765 | ||
766 | /* -------------------------------------------------------------------------- */ | |
767 | ||
768 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
769 | const struct usb_endpoint_descriptor *desc) | |
770 | { | |
771 | return -EINVAL; | |
772 | } | |
773 | ||
774 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
775 | { | |
776 | return -EINVAL; | |
777 | } | |
778 | ||
779 | /* -------------------------------------------------------------------------- */ | |
780 | ||
781 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
782 | const struct usb_endpoint_descriptor *desc) | |
783 | { | |
784 | struct dwc3_ep *dep; | |
785 | struct dwc3 *dwc; | |
786 | unsigned long flags; | |
787 | int ret; | |
788 | ||
789 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
790 | pr_debug("dwc3: invalid parameters\n"); | |
791 | return -EINVAL; | |
792 | } | |
793 | ||
794 | if (!desc->wMaxPacketSize) { | |
795 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
796 | return -EINVAL; | |
797 | } | |
798 | ||
799 | dep = to_dwc3_ep(ep); | |
800 | dwc = dep->dwc; | |
801 | ||
95ca961c FB |
802 | if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED, |
803 | "%s is already enabled\n", | |
804 | dep->name)) | |
c6f83f38 | 805 | return 0; |
c6f83f38 | 806 | |
72246da4 | 807 | spin_lock_irqsave(&dwc->lock, flags); |
a2d23f08 | 808 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
809 | spin_unlock_irqrestore(&dwc->lock, flags); |
810 | ||
811 | return ret; | |
812 | } | |
813 | ||
814 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
815 | { | |
816 | struct dwc3_ep *dep; | |
817 | struct dwc3 *dwc; | |
818 | unsigned long flags; | |
819 | int ret; | |
820 | ||
821 | if (!ep) { | |
822 | pr_debug("dwc3: invalid parameters\n"); | |
823 | return -EINVAL; | |
824 | } | |
825 | ||
826 | dep = to_dwc3_ep(ep); | |
827 | dwc = dep->dwc; | |
828 | ||
95ca961c FB |
829 | if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED), |
830 | "%s is already disabled\n", | |
831 | dep->name)) | |
72246da4 | 832 | return 0; |
72246da4 | 833 | |
72246da4 FB |
834 | spin_lock_irqsave(&dwc->lock, flags); |
835 | ret = __dwc3_gadget_ep_disable(dep); | |
836 | spin_unlock_irqrestore(&dwc->lock, flags); | |
837 | ||
838 | return ret; | |
839 | } | |
840 | ||
841 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
0bd0f6d2 | 842 | gfp_t gfp_flags) |
72246da4 FB |
843 | { |
844 | struct dwc3_request *req; | |
845 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
72246da4 FB |
846 | |
847 | req = kzalloc(sizeof(*req), gfp_flags); | |
734d5a53 | 848 | if (!req) |
72246da4 | 849 | return NULL; |
72246da4 | 850 | |
31a2f5a7 | 851 | req->direction = dep->direction; |
72246da4 FB |
852 | req->epnum = dep->number; |
853 | req->dep = dep; | |
a3af5e3a | 854 | req->status = DWC3_REQUEST_STATUS_UNKNOWN; |
72246da4 | 855 | |
2c4cbe6e FB |
856 | trace_dwc3_alloc_request(req); |
857 | ||
72246da4 FB |
858 | return &req->request; |
859 | } | |
860 | ||
861 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
862 | struct usb_request *request) | |
863 | { | |
864 | struct dwc3_request *req = to_dwc3_request(request); | |
865 | ||
2c4cbe6e | 866 | trace_dwc3_free_request(req); |
72246da4 FB |
867 | kfree(req); |
868 | } | |
869 | ||
42626919 FB |
870 | /** |
871 | * dwc3_ep_prev_trb - returns the previous TRB in the ring | |
872 | * @dep: The endpoint with the TRB ring | |
873 | * @index: The index of the current TRB in the ring | |
874 | * | |
875 | * Returns the TRB prior to the one pointed to by the index. If the | |
876 | * index is 0, we will wrap backwards, skip the link TRB, and return | |
877 | * the one just before that. | |
878 | */ | |
879 | static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index) | |
880 | { | |
881 | u8 tmp = index; | |
882 | ||
883 | if (!tmp) | |
884 | tmp = DWC3_TRB_NUM - 1; | |
885 | ||
886 | return &dep->trb_pool[tmp - 1]; | |
887 | } | |
888 | ||
889 | static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep) | |
890 | { | |
891 | struct dwc3_trb *tmp; | |
892 | u8 trbs_left; | |
893 | ||
894 | /* | |
895 | * If enqueue & dequeue are equal than it is either full or empty. | |
896 | * | |
897 | * One way to know for sure is if the TRB right before us has HWO bit | |
898 | * set or not. If it has, then we're definitely full and can't fit any | |
899 | * more transfers in our ring. | |
900 | */ | |
901 | if (dep->trb_enqueue == dep->trb_dequeue) { | |
902 | tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue); | |
903 | if (tmp->ctrl & DWC3_TRB_CTRL_HWO) | |
904 | return 0; | |
905 | ||
906 | return DWC3_TRB_NUM - 1; | |
907 | } | |
908 | ||
909 | trbs_left = dep->trb_dequeue - dep->trb_enqueue; | |
910 | trbs_left &= (DWC3_TRB_NUM - 1); | |
911 | ||
912 | if (dep->trb_dequeue < dep->trb_enqueue) | |
913 | trbs_left--; | |
914 | ||
915 | return trbs_left; | |
916 | } | |
2c78c029 | 917 | |
e49d3cf4 FB |
918 | static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb, |
919 | dma_addr_t dma, unsigned length, unsigned chain, unsigned node, | |
920 | unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt) | |
c71fc37c | 921 | { |
6b9018d4 FB |
922 | struct dwc3 *dwc = dep->dwc; |
923 | struct usb_gadget *gadget = &dwc->gadget; | |
924 | enum usb_device_speed speed = gadget->speed; | |
c71fc37c | 925 | |
f6bafc6a FB |
926 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
927 | trb->bpl = lower_32_bits(dma); | |
928 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 929 | |
16e78db7 | 930 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 931 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 932 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
933 | break; |
934 | ||
935 | case USB_ENDPOINT_XFER_ISOC: | |
6b9018d4 | 936 | if (!node) { |
e5ba5ec8 | 937 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; |
6b9018d4 | 938 | |
40d829fb MG |
939 | /* |
940 | * USB Specification 2.0 Section 5.9.2 states that: "If | |
941 | * there is only a single transaction in the microframe, | |
942 | * only a DATA0 data packet PID is used. If there are | |
943 | * two transactions per microframe, DATA1 is used for | |
944 | * the first transaction data packet and DATA0 is used | |
945 | * for the second transaction data packet. If there are | |
946 | * three transactions per microframe, DATA2 is used for | |
947 | * the first transaction data packet, DATA1 is used for | |
948 | * the second, and DATA0 is used for the third." | |
949 | * | |
950 | * IOW, we should satisfy the following cases: | |
951 | * | |
952 | * 1) length <= maxpacket | |
953 | * - DATA0 | |
954 | * | |
955 | * 2) maxpacket < length <= (2 * maxpacket) | |
956 | * - DATA1, DATA0 | |
957 | * | |
958 | * 3) (2 * maxpacket) < length <= (3 * maxpacket) | |
959 | * - DATA2, DATA1, DATA0 | |
960 | */ | |
6b9018d4 FB |
961 | if (speed == USB_SPEED_HIGH) { |
962 | struct usb_ep *ep = &dep->endpoint; | |
ec5bb87e | 963 | unsigned int mult = 2; |
40d829fb MG |
964 | unsigned int maxp = usb_endpoint_maxp(ep->desc); |
965 | ||
966 | if (length <= (2 * maxp)) | |
967 | mult--; | |
968 | ||
969 | if (length <= maxp) | |
970 | mult--; | |
971 | ||
972 | trb->size |= DWC3_TRB_SIZE_PCM1(mult); | |
6b9018d4 FB |
973 | } |
974 | } else { | |
e5ba5ec8 | 975 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; |
6b9018d4 | 976 | } |
ca4d44ea FB |
977 | |
978 | /* always enable Interrupt on Missed ISOC */ | |
979 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; | |
c71fc37c FB |
980 | break; |
981 | ||
982 | case USB_ENDPOINT_XFER_BULK: | |
983 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 984 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
985 | break; |
986 | default: | |
987 | /* | |
988 | * This is only possible with faulty memory because we | |
989 | * checked it already :) | |
990 | */ | |
0a695d4c FB |
991 | dev_WARN(dwc->dev, "Unknown endpoint type %d\n", |
992 | usb_endpoint_type(dep->endpoint.desc)); | |
c71fc37c FB |
993 | } |
994 | ||
244add8e TJ |
995 | /* |
996 | * Enable Continue on Short Packet | |
997 | * when endpoint is not a stream capable | |
998 | */ | |
c9508c8c | 999 | if (usb_endpoint_dir_out(dep->endpoint.desc)) { |
244add8e TJ |
1000 | if (!dep->stream_capable) |
1001 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
f3af3651 | 1002 | |
e49d3cf4 | 1003 | if (short_not_ok) |
c9508c8c FB |
1004 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; |
1005 | } | |
1006 | ||
e49d3cf4 | 1007 | if ((!no_interrupt && !chain) || |
b7a4fbe2 | 1008 | (dwc3_calc_trbs_left(dep) == 1)) |
c9508c8c | 1009 | trb->ctrl |= DWC3_TRB_CTRL_IOC; |
f3af3651 | 1010 | |
e5ba5ec8 PA |
1011 | if (chain) |
1012 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
1013 | ||
16e78db7 | 1014 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
e49d3cf4 | 1015 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id); |
c71fc37c | 1016 | |
f6bafc6a | 1017 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
2c4cbe6e | 1018 | |
b7a4fbe2 AKV |
1019 | dwc3_ep_inc_enq(dep); |
1020 | ||
2c4cbe6e | 1021 | trace_dwc3_prepare_trb(dep, trb); |
c71fc37c FB |
1022 | } |
1023 | ||
e49d3cf4 FB |
1024 | /** |
1025 | * dwc3_prepare_one_trb - setup one TRB from one request | |
1026 | * @dep: endpoint for which this request is prepared | |
1027 | * @req: dwc3_request pointer | |
1028 | * @chain: should this TRB be chained to the next? | |
1029 | * @node: only for isochronous endpoints. First TRB needs different type. | |
1030 | */ | |
1031 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, | |
1032 | struct dwc3_request *req, unsigned chain, unsigned node) | |
1033 | { | |
1034 | struct dwc3_trb *trb; | |
a31e63b6 AKV |
1035 | unsigned int length; |
1036 | dma_addr_t dma; | |
e49d3cf4 FB |
1037 | unsigned stream_id = req->request.stream_id; |
1038 | unsigned short_not_ok = req->request.short_not_ok; | |
1039 | unsigned no_interrupt = req->request.no_interrupt; | |
a31e63b6 AKV |
1040 | |
1041 | if (req->request.num_sgs > 0) { | |
1042 | length = sg_dma_len(req->start_sg); | |
1043 | dma = sg_dma_address(req->start_sg); | |
1044 | } else { | |
1045 | length = req->request.length; | |
1046 | dma = req->request.dma; | |
1047 | } | |
e49d3cf4 FB |
1048 | |
1049 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
1050 | ||
1051 | if (!req->trb) { | |
1052 | dwc3_gadget_move_started_request(req); | |
1053 | req->trb = trb; | |
1054 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
e49d3cf4 FB |
1055 | } |
1056 | ||
09fe1f8d FB |
1057 | req->num_trbs++; |
1058 | ||
e49d3cf4 FB |
1059 | __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node, |
1060 | stream_id, short_not_ok, no_interrupt); | |
1061 | } | |
1062 | ||
5ee85d89 | 1063 | static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep, |
7ae7df49 | 1064 | struct dwc3_request *req) |
5ee85d89 | 1065 | { |
a31e63b6 | 1066 | struct scatterlist *sg = req->start_sg; |
5ee85d89 | 1067 | struct scatterlist *s; |
5ee85d89 FB |
1068 | int i; |
1069 | ||
c96e6725 AKV |
1070 | unsigned int remaining = req->request.num_mapped_sgs |
1071 | - req->num_queued_sgs; | |
1072 | ||
1073 | for_each_sg(sg, s, remaining, i) { | |
c6267a51 FB |
1074 | unsigned int length = req->request.length; |
1075 | unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc); | |
1076 | unsigned int rem = length % maxp; | |
5ee85d89 FB |
1077 | unsigned chain = true; |
1078 | ||
dad2aff3 PP |
1079 | /* |
1080 | * IOMMU driver is coalescing the list of sgs which shares a | |
1081 | * page boundary into one and giving it to USB driver. With | |
1082 | * this the number of sgs mapped is not equal to the number of | |
1083 | * sgs passed. So mark the chain bit to false if it isthe last | |
1084 | * mapped sg. | |
1085 | */ | |
1086 | if (i == remaining - 1) | |
5ee85d89 FB |
1087 | chain = false; |
1088 | ||
c6267a51 FB |
1089 | if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) { |
1090 | struct dwc3 *dwc = dep->dwc; | |
1091 | struct dwc3_trb *trb; | |
1092 | ||
1a22ec64 | 1093 | req->needs_extra_trb = true; |
c6267a51 FB |
1094 | |
1095 | /* prepare normal TRB */ | |
1096 | dwc3_prepare_one_trb(dep, req, true, i); | |
1097 | ||
1098 | /* Now prepare one extra TRB to align transfer size */ | |
1099 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
09fe1f8d | 1100 | req->num_trbs++; |
c6267a51 | 1101 | __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, |
2fc6d4be | 1102 | maxp - rem, false, 1, |
c6267a51 FB |
1103 | req->request.stream_id, |
1104 | req->request.short_not_ok, | |
1105 | req->request.no_interrupt); | |
1106 | } else { | |
1107 | dwc3_prepare_one_trb(dep, req, chain, i); | |
1108 | } | |
5ee85d89 | 1109 | |
a31e63b6 AKV |
1110 | /* |
1111 | * There can be a situation where all sgs in sglist are not | |
1112 | * queued because of insufficient trb number. To handle this | |
1113 | * case, update start_sg to next sg to be queued, so that | |
1114 | * we have free trbs we can continue queuing from where we | |
1115 | * previously stopped | |
1116 | */ | |
1117 | if (chain) | |
1118 | req->start_sg = sg_next(s); | |
1119 | ||
c96e6725 AKV |
1120 | req->num_queued_sgs++; |
1121 | ||
7ae7df49 | 1122 | if (!dwc3_calc_trbs_left(dep)) |
5ee85d89 FB |
1123 | break; |
1124 | } | |
1125 | } | |
1126 | ||
1127 | static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep, | |
7ae7df49 | 1128 | struct dwc3_request *req) |
5ee85d89 | 1129 | { |
c6267a51 FB |
1130 | unsigned int length = req->request.length; |
1131 | unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc); | |
1132 | unsigned int rem = length % maxp; | |
1133 | ||
1e19cdc8 | 1134 | if ((!length || rem) && usb_endpoint_dir_out(dep->endpoint.desc)) { |
c6267a51 FB |
1135 | struct dwc3 *dwc = dep->dwc; |
1136 | struct dwc3_trb *trb; | |
1137 | ||
1a22ec64 | 1138 | req->needs_extra_trb = true; |
c6267a51 FB |
1139 | |
1140 | /* prepare normal TRB */ | |
1141 | dwc3_prepare_one_trb(dep, req, true, 0); | |
1142 | ||
1143 | /* Now prepare one extra TRB to align transfer size */ | |
1144 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
09fe1f8d | 1145 | req->num_trbs++; |
c6267a51 | 1146 | __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem, |
2fc6d4be | 1147 | false, 1, req->request.stream_id, |
c6267a51 FB |
1148 | req->request.short_not_ok, |
1149 | req->request.no_interrupt); | |
d6e5a549 | 1150 | } else if (req->request.zero && req->request.length && |
4ea438da | 1151 | (IS_ALIGNED(req->request.length, maxp))) { |
d6e5a549 FB |
1152 | struct dwc3 *dwc = dep->dwc; |
1153 | struct dwc3_trb *trb; | |
1154 | ||
1a22ec64 | 1155 | req->needs_extra_trb = true; |
d6e5a549 FB |
1156 | |
1157 | /* prepare normal TRB */ | |
1158 | dwc3_prepare_one_trb(dep, req, true, 0); | |
1159 | ||
1160 | /* Now prepare one extra TRB to handle ZLP */ | |
1161 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
09fe1f8d | 1162 | req->num_trbs++; |
d6e5a549 | 1163 | __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0, |
2fc6d4be | 1164 | false, 1, req->request.stream_id, |
d6e5a549 FB |
1165 | req->request.short_not_ok, |
1166 | req->request.no_interrupt); | |
c6267a51 FB |
1167 | } else { |
1168 | dwc3_prepare_one_trb(dep, req, false, 0); | |
1169 | } | |
5ee85d89 FB |
1170 | } |
1171 | ||
72246da4 FB |
1172 | /* |
1173 | * dwc3_prepare_trbs - setup TRBs from requests | |
1174 | * @dep: endpoint for which requests are being prepared | |
72246da4 | 1175 | * |
1d046793 PZ |
1176 | * The function goes through the requests list and sets up TRBs for the |
1177 | * transfers. The function returns once there are no more TRBs available or | |
1178 | * it runs out of requests. | |
72246da4 | 1179 | */ |
c4233573 | 1180 | static void dwc3_prepare_trbs(struct dwc3_ep *dep) |
72246da4 | 1181 | { |
68e823e2 | 1182 | struct dwc3_request *req, *n; |
72246da4 FB |
1183 | |
1184 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
1185 | ||
d86c5a67 FB |
1186 | /* |
1187 | * We can get in a situation where there's a request in the started list | |
1188 | * but there weren't enough TRBs to fully kick it in the first time | |
1189 | * around, so it has been waiting for more TRBs to be freed up. | |
1190 | * | |
1191 | * In that case, we should check if we have a request with pending_sgs | |
1192 | * in the started list and prepare TRBs for that request first, | |
1193 | * otherwise we will prepare TRBs completely out of order and that will | |
1194 | * break things. | |
1195 | */ | |
1196 | list_for_each_entry(req, &dep->started_list, list) { | |
1197 | if (req->num_pending_sgs > 0) | |
1198 | dwc3_prepare_one_trb_sg(dep, req); | |
1199 | ||
1200 | if (!dwc3_calc_trbs_left(dep)) | |
1201 | return; | |
1202 | } | |
1203 | ||
aa3342c8 | 1204 | list_for_each_entry_safe(req, n, &dep->pending_list, list) { |
cdb55b39 FB |
1205 | struct dwc3 *dwc = dep->dwc; |
1206 | int ret; | |
1207 | ||
1208 | ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request, | |
1209 | dep->direction); | |
1210 | if (ret) | |
1211 | return; | |
1212 | ||
1213 | req->sg = req->request.sg; | |
a31e63b6 | 1214 | req->start_sg = req->sg; |
c96e6725 | 1215 | req->num_queued_sgs = 0; |
cdb55b39 FB |
1216 | req->num_pending_sgs = req->request.num_mapped_sgs; |
1217 | ||
1f512119 | 1218 | if (req->num_pending_sgs > 0) |
7ae7df49 | 1219 | dwc3_prepare_one_trb_sg(dep, req); |
5ee85d89 | 1220 | else |
7ae7df49 | 1221 | dwc3_prepare_one_trb_linear(dep, req); |
72246da4 | 1222 | |
7ae7df49 | 1223 | if (!dwc3_calc_trbs_left(dep)) |
5ee85d89 | 1224 | return; |
72246da4 | 1225 | } |
72246da4 FB |
1226 | } |
1227 | ||
8d99087c TN |
1228 | static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep); |
1229 | ||
7fdca766 | 1230 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep) |
72246da4 FB |
1231 | { |
1232 | struct dwc3_gadget_ep_cmd_params params; | |
1233 | struct dwc3_request *req; | |
4fae2e3e | 1234 | int starting; |
72246da4 FB |
1235 | int ret; |
1236 | u32 cmd; | |
1237 | ||
ccb94ebf FB |
1238 | if (!dwc3_calc_trbs_left(dep)) |
1239 | return 0; | |
1240 | ||
1912cbc6 | 1241 | starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED); |
72246da4 | 1242 | |
4fae2e3e FB |
1243 | dwc3_prepare_trbs(dep); |
1244 | req = next_request(&dep->started_list); | |
72246da4 FB |
1245 | if (!req) { |
1246 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
1247 | return 0; | |
1248 | } | |
1249 | ||
1250 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 1251 | |
4fae2e3e | 1252 | if (starting) { |
1877d6c9 PA |
1253 | params.param0 = upper_32_bits(req->trb_dma); |
1254 | params.param1 = lower_32_bits(req->trb_dma); | |
7fdca766 FB |
1255 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
1256 | ||
a7351807 AKV |
1257 | if (dep->stream_capable) |
1258 | cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id); | |
1259 | ||
7fdca766 FB |
1260 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
1261 | cmd |= DWC3_DEPCMD_PARAM(dep->frame_number); | |
1877d6c9 | 1262 | } else { |
b6b1c6db FB |
1263 | cmd = DWC3_DEPCMD_UPDATETRANSFER | |
1264 | DWC3_DEPCMD_PARAM(dep->resource_index); | |
1877d6c9 | 1265 | } |
72246da4 | 1266 | |
2cd4718d | 1267 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
72246da4 | 1268 | if (ret < 0) { |
8d99087c TN |
1269 | struct dwc3_request *tmp; |
1270 | ||
1271 | if (ret == -EAGAIN) | |
1272 | return ret; | |
1273 | ||
1274 | dwc3_stop_active_transfer(dep, true, true); | |
1275 | ||
1276 | list_for_each_entry_safe(req, tmp, &dep->started_list, list) | |
1277 | dwc3_gadget_move_cancelled_request(req); | |
1278 | ||
1279 | /* If ep isn't started, then there's no end transfer pending */ | |
1280 | if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING)) | |
1281 | dwc3_gadget_ep_cleanup_cancelled_requests(dep); | |
1282 | ||
72246da4 FB |
1283 | return ret; |
1284 | } | |
1285 | ||
72246da4 FB |
1286 | return 0; |
1287 | } | |
1288 | ||
6cb2e4e3 FB |
1289 | static int __dwc3_gadget_get_frame(struct dwc3 *dwc) |
1290 | { | |
1291 | u32 reg; | |
1292 | ||
1293 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1294 | return DWC3_DSTS_SOFFN(reg); | |
1295 | } | |
1296 | ||
d92021f6 TN |
1297 | /** |
1298 | * dwc3_gadget_start_isoc_quirk - workaround invalid frame number | |
1299 | * @dep: isoc endpoint | |
1300 | * | |
1301 | * This function tests for the correct combination of BIT[15:14] from the 16-bit | |
1302 | * microframe number reported by the XferNotReady event for the future frame | |
1303 | * number to start the isoc transfer. | |
1304 | * | |
1305 | * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed | |
1306 | * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the | |
1307 | * XferNotReady event are invalid. The driver uses this number to schedule the | |
1308 | * isochronous transfer and passes it to the START TRANSFER command. Because | |
1309 | * this number is invalid, the command may fail. If BIT[15:14] matches the | |
1310 | * internal 16-bit microframe, the START TRANSFER command will pass and the | |
1311 | * transfer will start at the scheduled time, if it is off by 1, the command | |
1312 | * will still pass, but the transfer will start 2 seconds in the future. For all | |
1313 | * other conditions, the START TRANSFER command will fail with bus-expiry. | |
1314 | * | |
1315 | * In order to workaround this issue, we can test for the correct combination of | |
1316 | * BIT[15:14] by sending START TRANSFER commands with different values of | |
1317 | * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart | |
1318 | * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status. | |
1319 | * As the result, within the 4 possible combinations for BIT[15:14], there will | |
1320 | * be 2 successful and 2 failure START COMMAND status. One of the 2 successful | |
1321 | * command status will result in a 2-second delay start. The smaller BIT[15:14] | |
1322 | * value is the correct combination. | |
1323 | * | |
1324 | * Since there are only 4 outcomes and the results are ordered, we can simply | |
1325 | * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to | |
1326 | * deduce the smaller successful combination. | |
1327 | * | |
1328 | * Let test0 = test status for combination 'b00 and test1 = test status for 'b01 | |
1329 | * of BIT[15:14]. The correct combination is as follow: | |
1330 | * | |
1331 | * if test0 fails and test1 passes, BIT[15:14] is 'b01 | |
1332 | * if test0 fails and test1 fails, BIT[15:14] is 'b10 | |
1333 | * if test0 passes and test1 fails, BIT[15:14] is 'b11 | |
1334 | * if test0 passes and test1 passes, BIT[15:14] is 'b00 | |
1335 | * | |
1336 | * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN | |
1337 | * endpoints. | |
1338 | */ | |
25abad6a | 1339 | static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep) |
d92021f6 TN |
1340 | { |
1341 | int cmd_status = 0; | |
1342 | bool test0; | |
1343 | bool test1; | |
1344 | ||
1345 | while (dep->combo_num < 2) { | |
1346 | struct dwc3_gadget_ep_cmd_params params; | |
1347 | u32 test_frame_number; | |
1348 | u32 cmd; | |
1349 | ||
1350 | /* | |
1351 | * Check if we can start isoc transfer on the next interval or | |
1352 | * 4 uframes in the future with BIT[15:14] as dep->combo_num | |
1353 | */ | |
1354 | test_frame_number = dep->frame_number & 0x3fff; | |
1355 | test_frame_number |= dep->combo_num << 14; | |
1356 | test_frame_number += max_t(u32, 4, dep->interval); | |
1357 | ||
1358 | params.param0 = upper_32_bits(dep->dwc->bounce_addr); | |
1359 | params.param1 = lower_32_bits(dep->dwc->bounce_addr); | |
1360 | ||
1361 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
1362 | cmd |= DWC3_DEPCMD_PARAM(test_frame_number); | |
1363 | cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
1364 | ||
1365 | /* Redo if some other failure beside bus-expiry is received */ | |
1366 | if (cmd_status && cmd_status != -EAGAIN) { | |
1367 | dep->start_cmd_status = 0; | |
1368 | dep->combo_num = 0; | |
25abad6a | 1369 | return 0; |
d92021f6 TN |
1370 | } |
1371 | ||
1372 | /* Store the first test status */ | |
1373 | if (dep->combo_num == 0) | |
1374 | dep->start_cmd_status = cmd_status; | |
1375 | ||
1376 | dep->combo_num++; | |
1377 | ||
1378 | /* | |
1379 | * End the transfer if the START_TRANSFER command is successful | |
1380 | * to wait for the next XferNotReady to test the command again | |
1381 | */ | |
1382 | if (cmd_status == 0) { | |
c5353b22 | 1383 | dwc3_stop_active_transfer(dep, true, true); |
25abad6a | 1384 | return 0; |
d92021f6 TN |
1385 | } |
1386 | } | |
1387 | ||
1388 | /* test0 and test1 are both completed at this point */ | |
1389 | test0 = (dep->start_cmd_status == 0); | |
1390 | test1 = (cmd_status == 0); | |
1391 | ||
1392 | if (!test0 && test1) | |
1393 | dep->combo_num = 1; | |
1394 | else if (!test0 && !test1) | |
1395 | dep->combo_num = 2; | |
1396 | else if (test0 && !test1) | |
1397 | dep->combo_num = 3; | |
1398 | else if (test0 && test1) | |
1399 | dep->combo_num = 0; | |
1400 | ||
1401 | dep->frame_number &= 0x3fff; | |
1402 | dep->frame_number |= dep->combo_num << 14; | |
1403 | dep->frame_number += max_t(u32, 4, dep->interval); | |
1404 | ||
1405 | /* Reinitialize test variables */ | |
1406 | dep->start_cmd_status = 0; | |
1407 | dep->combo_num = 0; | |
1408 | ||
25abad6a | 1409 | return __dwc3_gadget_kick_transfer(dep); |
d92021f6 TN |
1410 | } |
1411 | ||
25abad6a | 1412 | static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep) |
d6d6ec7b | 1413 | { |
d92021f6 | 1414 | struct dwc3 *dwc = dep->dwc; |
d5370106 FB |
1415 | int ret; |
1416 | int i; | |
d92021f6 | 1417 | |
36f05d36 TN |
1418 | if (list_empty(&dep->pending_list) && |
1419 | list_empty(&dep->started_list)) { | |
f4a53c55 | 1420 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
25abad6a | 1421 | return -EAGAIN; |
d6d6ec7b PA |
1422 | } |
1423 | ||
d92021f6 TN |
1424 | if (!dwc->dis_start_transfer_quirk && dwc3_is_usb31(dwc) && |
1425 | (dwc->revision <= DWC3_USB31_REVISION_160A || | |
1426 | (dwc->revision == DWC3_USB31_REVISION_170A && | |
1427 | dwc->version_type >= DWC31_VERSIONTYPE_EA01 && | |
1428 | dwc->version_type <= DWC31_VERSIONTYPE_EA06))) { | |
1429 | ||
25abad6a FB |
1430 | if (dwc->gadget.speed <= USB_SPEED_HIGH && dep->direction) |
1431 | return dwc3_gadget_start_isoc_quirk(dep); | |
d6d6ec7b PA |
1432 | } |
1433 | ||
d5370106 FB |
1434 | for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) { |
1435 | dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1); | |
1436 | ||
1437 | ret = __dwc3_gadget_kick_transfer(dep); | |
1438 | if (ret != -EAGAIN) | |
1439 | break; | |
1440 | } | |
1441 | ||
36f05d36 TN |
1442 | /* |
1443 | * After a number of unsuccessful start attempts due to bus-expiry | |
1444 | * status, issue END_TRANSFER command and retry on the next XferNotReady | |
1445 | * event. | |
1446 | */ | |
1447 | if (ret == -EAGAIN) { | |
1448 | struct dwc3_gadget_ep_cmd_params params; | |
1449 | u32 cmd; | |
1450 | ||
1451 | cmd = DWC3_DEPCMD_ENDTRANSFER | | |
1452 | DWC3_DEPCMD_CMDIOC | | |
1453 | DWC3_DEPCMD_PARAM(dep->resource_index); | |
1454 | ||
1455 | dep->resource_index = 0; | |
1456 | memset(¶ms, 0, sizeof(params)); | |
1457 | ||
1458 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
1459 | if (!ret) | |
1460 | dep->flags |= DWC3_EP_END_TRANSFER_PENDING; | |
1461 | } | |
1462 | ||
d5370106 | 1463 | return ret; |
d6d6ec7b PA |
1464 | } |
1465 | ||
72246da4 FB |
1466 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1467 | { | |
0fc9a1be | 1468 | struct dwc3 *dwc = dep->dwc; |
0fc9a1be | 1469 | |
bb423984 | 1470 | if (!dep->endpoint.desc) { |
5eb30ced FB |
1471 | dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", |
1472 | dep->name); | |
bb423984 FB |
1473 | return -ESHUTDOWN; |
1474 | } | |
1475 | ||
04fb365c FB |
1476 | if (WARN(req->dep != dep, "request %pK belongs to '%s'\n", |
1477 | &req->request, req->dep->name)) | |
bb423984 | 1478 | return -EINVAL; |
bb423984 | 1479 | |
b2b6d601 FB |
1480 | if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED, |
1481 | "%s: request %pK already in flight\n", | |
1482 | dep->name, &req->request)) | |
1483 | return -EINVAL; | |
1484 | ||
fc8bb91b FB |
1485 | pm_runtime_get(dwc->dev); |
1486 | ||
72246da4 FB |
1487 | req->request.actual = 0; |
1488 | req->request.status = -EINPROGRESS; | |
72246da4 | 1489 | |
fe84f522 FB |
1490 | trace_dwc3_ep_queue(req); |
1491 | ||
aa3342c8 | 1492 | list_add_tail(&req->list, &dep->pending_list); |
a3af5e3a | 1493 | req->status = DWC3_REQUEST_STATUS_QUEUED; |
72246da4 | 1494 | |
da10bcdd TN |
1495 | /* Start the transfer only after the END_TRANSFER is completed */ |
1496 | if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) { | |
1497 | dep->flags |= DWC3_EP_DELAY_START; | |
1498 | return 0; | |
1499 | } | |
1500 | ||
d889c23c FB |
1501 | /* |
1502 | * NOTICE: Isochronous endpoints should NEVER be prestarted. We must | |
1503 | * wait for a XferNotReady event so we will know what's the current | |
1504 | * (micro-)frame number. | |
1505 | * | |
1506 | * Without this trick, we are very, very likely gonna get Bus Expiry | |
1507 | * errors which will force us issue EndTransfer command. | |
1508 | */ | |
1509 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
fe990cea FB |
1510 | if (!(dep->flags & DWC3_EP_PENDING_REQUEST) && |
1511 | !(dep->flags & DWC3_EP_TRANSFER_STARTED)) | |
1512 | return 0; | |
1513 | ||
6cb2e4e3 | 1514 | if ((dep->flags & DWC3_EP_PENDING_REQUEST)) { |
fe990cea | 1515 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) { |
25abad6a | 1516 | return __dwc3_gadget_start_isoc(dep); |
6cb2e4e3 | 1517 | } |
08a36b54 | 1518 | } |
64e01080 | 1519 | } |
b997ada5 | 1520 | |
7fdca766 | 1521 | return __dwc3_gadget_kick_transfer(dep); |
72246da4 FB |
1522 | } |
1523 | ||
1524 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, | |
1525 | gfp_t gfp_flags) | |
1526 | { | |
1527 | struct dwc3_request *req = to_dwc3_request(request); | |
1528 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1529 | struct dwc3 *dwc = dep->dwc; | |
1530 | ||
1531 | unsigned long flags; | |
1532 | ||
1533 | int ret; | |
1534 | ||
fdee4eba | 1535 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1536 | ret = __dwc3_gadget_ep_queue(dep, req); |
1537 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1538 | ||
1539 | return ret; | |
1540 | } | |
1541 | ||
7746a8df FB |
1542 | static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req) |
1543 | { | |
1544 | int i; | |
1545 | ||
cb11ea56 TN |
1546 | /* If req->trb is not set, then the request has not started */ |
1547 | if (!req->trb) | |
1548 | return; | |
1549 | ||
7746a8df FB |
1550 | /* |
1551 | * If request was already started, this means we had to | |
1552 | * stop the transfer. With that we also need to ignore | |
1553 | * all TRBs used by the request, however TRBs can only | |
1554 | * be modified after completion of END_TRANSFER | |
1555 | * command. So what we do here is that we wait for | |
1556 | * END_TRANSFER completion and only after that, we jump | |
1557 | * over TRBs by clearing HWO and incrementing dequeue | |
1558 | * pointer. | |
1559 | */ | |
1560 | for (i = 0; i < req->num_trbs; i++) { | |
1561 | struct dwc3_trb *trb; | |
1562 | ||
2dedea03 | 1563 | trb = &dep->trb_pool[dep->trb_dequeue]; |
7746a8df FB |
1564 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; |
1565 | dwc3_ep_inc_deq(dep); | |
1566 | } | |
c7152763 TN |
1567 | |
1568 | req->num_trbs = 0; | |
7746a8df FB |
1569 | } |
1570 | ||
d4f1afe5 FB |
1571 | static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep) |
1572 | { | |
1573 | struct dwc3_request *req; | |
1574 | struct dwc3_request *tmp; | |
1575 | ||
1576 | list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) { | |
1577 | dwc3_gadget_ep_skip_trbs(dep, req); | |
1578 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1579 | } | |
1580 | } | |
1581 | ||
72246da4 FB |
1582 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, |
1583 | struct usb_request *request) | |
1584 | { | |
1585 | struct dwc3_request *req = to_dwc3_request(request); | |
1586 | struct dwc3_request *r = NULL; | |
1587 | ||
1588 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1589 | struct dwc3 *dwc = dep->dwc; | |
1590 | ||
1591 | unsigned long flags; | |
1592 | int ret = 0; | |
1593 | ||
2c4cbe6e FB |
1594 | trace_dwc3_ep_dequeue(req); |
1595 | ||
72246da4 FB |
1596 | spin_lock_irqsave(&dwc->lock, flags); |
1597 | ||
a7027ca6 TN |
1598 | list_for_each_entry(r, &dep->cancelled_list, list) { |
1599 | if (r == req) | |
fcd2def6 | 1600 | goto out; |
a7027ca6 TN |
1601 | } |
1602 | ||
aa3342c8 | 1603 | list_for_each_entry(r, &dep->pending_list, list) { |
fcd2def6 TN |
1604 | if (r == req) { |
1605 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1606 | goto out; | |
1607 | } | |
72246da4 FB |
1608 | } |
1609 | ||
fcd2def6 | 1610 | list_for_each_entry(r, &dep->started_list, list) { |
72246da4 | 1611 | if (r == req) { |
a7027ca6 TN |
1612 | struct dwc3_request *t; |
1613 | ||
72246da4 | 1614 | /* wait until it is processed */ |
c5353b22 | 1615 | dwc3_stop_active_transfer(dep, true, true); |
cf3113d8 | 1616 | |
a7027ca6 TN |
1617 | /* |
1618 | * Remove any started request if the transfer is | |
1619 | * cancelled. | |
1620 | */ | |
1621 | list_for_each_entry_safe(r, t, &dep->started_list, list) | |
1622 | dwc3_gadget_move_cancelled_request(r); | |
1623 | ||
fcd2def6 | 1624 | goto out; |
72246da4 | 1625 | } |
72246da4 FB |
1626 | } |
1627 | ||
fcd2def6 TN |
1628 | dev_err(dwc->dev, "request %pK was not queued to %s\n", |
1629 | request, ep->name); | |
1630 | ret = -EINVAL; | |
1631 | out: | |
72246da4 FB |
1632 | spin_unlock_irqrestore(&dwc->lock, flags); |
1633 | ||
1634 | return ret; | |
1635 | } | |
1636 | ||
7a608559 | 1637 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) |
72246da4 FB |
1638 | { |
1639 | struct dwc3_gadget_ep_cmd_params params; | |
1640 | struct dwc3 *dwc = dep->dwc; | |
cb11ea56 TN |
1641 | struct dwc3_request *req; |
1642 | struct dwc3_request *tmp; | |
72246da4 FB |
1643 | int ret; |
1644 | ||
5ad02fb8 FB |
1645 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
1646 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); | |
1647 | return -EINVAL; | |
1648 | } | |
1649 | ||
72246da4 FB |
1650 | memset(¶ms, 0x00, sizeof(params)); |
1651 | ||
1652 | if (value) { | |
69450c4d FB |
1653 | struct dwc3_trb *trb; |
1654 | ||
1655 | unsigned transfer_in_flight; | |
1656 | unsigned started; | |
1657 | ||
1658 | if (dep->number > 1) | |
1659 | trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue); | |
1660 | else | |
1661 | trb = &dwc->ep0_trb[dep->trb_enqueue]; | |
1662 | ||
1663 | transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO; | |
1664 | started = !list_empty(&dep->started_list); | |
1665 | ||
1666 | if (!protocol && ((dep->direction && transfer_in_flight) || | |
1667 | (!dep->direction && started))) { | |
7a608559 FB |
1668 | return -EAGAIN; |
1669 | } | |
1670 | ||
2cd4718d FB |
1671 | ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL, |
1672 | ¶ms); | |
72246da4 | 1673 | if (ret) |
3f89204b | 1674 | dev_err(dwc->dev, "failed to set STALL on %s\n", |
72246da4 FB |
1675 | dep->name); |
1676 | else | |
1677 | dep->flags |= DWC3_EP_STALL; | |
1678 | } else { | |
cb11ea56 TN |
1679 | /* |
1680 | * Don't issue CLEAR_STALL command to control endpoints. The | |
1681 | * controller automatically clears the STALL when it receives | |
1682 | * the SETUP token. | |
1683 | */ | |
1684 | if (dep->number <= 1) { | |
1685 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); | |
1686 | return 0; | |
1687 | } | |
2cd4718d | 1688 | |
50c763f8 | 1689 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
cb11ea56 | 1690 | if (ret) { |
3f89204b | 1691 | dev_err(dwc->dev, "failed to clear STALL on %s\n", |
72246da4 | 1692 | dep->name); |
cb11ea56 TN |
1693 | return ret; |
1694 | } | |
1695 | ||
1696 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); | |
1697 | ||
1698 | dwc3_stop_active_transfer(dep, true, true); | |
1699 | ||
1700 | list_for_each_entry_safe(req, tmp, &dep->started_list, list) | |
1701 | dwc3_gadget_move_cancelled_request(req); | |
1702 | ||
1703 | list_for_each_entry_safe(req, tmp, &dep->pending_list, list) | |
1704 | dwc3_gadget_move_cancelled_request(req); | |
1705 | ||
1706 | if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING)) { | |
1707 | dep->flags &= ~DWC3_EP_DELAY_START; | |
1708 | dwc3_gadget_ep_cleanup_cancelled_requests(dep); | |
1709 | } | |
72246da4 | 1710 | } |
5275455a | 1711 | |
72246da4 FB |
1712 | return ret; |
1713 | } | |
1714 | ||
1715 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1716 | { | |
1717 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1718 | struct dwc3 *dwc = dep->dwc; | |
1719 | ||
1720 | unsigned long flags; | |
1721 | ||
1722 | int ret; | |
1723 | ||
1724 | spin_lock_irqsave(&dwc->lock, flags); | |
7a608559 | 1725 | ret = __dwc3_gadget_ep_set_halt(dep, value, false); |
72246da4 FB |
1726 | spin_unlock_irqrestore(&dwc->lock, flags); |
1727 | ||
1728 | return ret; | |
1729 | } | |
1730 | ||
1731 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1732 | { | |
1733 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1734 | struct dwc3 *dwc = dep->dwc; |
1735 | unsigned long flags; | |
95aa4e8d | 1736 | int ret; |
72246da4 | 1737 | |
249a4569 | 1738 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1739 | dep->flags |= DWC3_EP_WEDGE; |
1740 | ||
08f0d966 | 1741 | if (dep->number == 0 || dep->number == 1) |
95aa4e8d | 1742 | ret = __dwc3_gadget_ep0_set_halt(ep, 1); |
08f0d966 | 1743 | else |
7a608559 | 1744 | ret = __dwc3_gadget_ep_set_halt(dep, 1, false); |
95aa4e8d FB |
1745 | spin_unlock_irqrestore(&dwc->lock, flags); |
1746 | ||
1747 | return ret; | |
72246da4 FB |
1748 | } |
1749 | ||
1750 | /* -------------------------------------------------------------------------- */ | |
1751 | ||
1752 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1753 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1754 | .bDescriptorType = USB_DT_ENDPOINT, | |
1755 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1756 | }; | |
1757 | ||
1758 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1759 | .enable = dwc3_gadget_ep0_enable, | |
1760 | .disable = dwc3_gadget_ep0_disable, | |
1761 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1762 | .free_request = dwc3_gadget_ep_free_request, | |
1763 | .queue = dwc3_gadget_ep0_queue, | |
1764 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 1765 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
1766 | .set_wedge = dwc3_gadget_ep_set_wedge, |
1767 | }; | |
1768 | ||
1769 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1770 | .enable = dwc3_gadget_ep_enable, | |
1771 | .disable = dwc3_gadget_ep_disable, | |
1772 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1773 | .free_request = dwc3_gadget_ep_free_request, | |
1774 | .queue = dwc3_gadget_ep_queue, | |
1775 | .dequeue = dwc3_gadget_ep_dequeue, | |
1776 | .set_halt = dwc3_gadget_ep_set_halt, | |
1777 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1778 | }; | |
1779 | ||
1780 | /* -------------------------------------------------------------------------- */ | |
1781 | ||
1782 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1783 | { | |
1784 | struct dwc3 *dwc = gadget_to_dwc(g); | |
72246da4 | 1785 | |
6cb2e4e3 | 1786 | return __dwc3_gadget_get_frame(dwc); |
72246da4 FB |
1787 | } |
1788 | ||
218ef7b6 | 1789 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc) |
72246da4 | 1790 | { |
d6011f6f | 1791 | int retries; |
72246da4 | 1792 | |
218ef7b6 | 1793 | int ret; |
72246da4 FB |
1794 | u32 reg; |
1795 | ||
72246da4 | 1796 | u8 link_state; |
72246da4 | 1797 | |
72246da4 FB |
1798 | /* |
1799 | * According to the Databook Remote wakeup request should | |
1800 | * be issued only when the device is in early suspend state. | |
1801 | * | |
1802 | * We can check that via USB Link State bits in DSTS register. | |
1803 | */ | |
1804 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1805 | ||
72246da4 FB |
1806 | link_state = DWC3_DSTS_USBLNKST(reg); |
1807 | ||
1808 | switch (link_state) { | |
d0550cd2 | 1809 | case DWC3_LINK_STATE_RESET: |
72246da4 FB |
1810 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ |
1811 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
d0550cd2 | 1812 | case DWC3_LINK_STATE_RESUME: |
72246da4 FB |
1813 | break; |
1814 | default: | |
218ef7b6 | 1815 | return -EINVAL; |
72246da4 FB |
1816 | } |
1817 | ||
8598bde7 FB |
1818 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
1819 | if (ret < 0) { | |
1820 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
218ef7b6 | 1821 | return ret; |
8598bde7 | 1822 | } |
72246da4 | 1823 | |
802fde98 PZ |
1824 | /* Recent versions do this automatically */ |
1825 | if (dwc->revision < DWC3_REVISION_194A) { | |
1826 | /* write zeroes to Link Change Request */ | |
fcc023c7 | 1827 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
1828 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
1829 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1830 | } | |
72246da4 | 1831 | |
1d046793 | 1832 | /* poll until Link State changes to ON */ |
d6011f6f | 1833 | retries = 20000; |
72246da4 | 1834 | |
d6011f6f | 1835 | while (retries--) { |
72246da4 FB |
1836 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
1837 | ||
1838 | /* in HS, means ON */ | |
1839 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1840 | break; | |
1841 | } | |
1842 | ||
1843 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1844 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
218ef7b6 | 1845 | return -EINVAL; |
72246da4 FB |
1846 | } |
1847 | ||
218ef7b6 FB |
1848 | return 0; |
1849 | } | |
1850 | ||
1851 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1852 | { | |
1853 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1854 | unsigned long flags; | |
1855 | int ret; | |
1856 | ||
1857 | spin_lock_irqsave(&dwc->lock, flags); | |
1858 | ret = __dwc3_gadget_wakeup(dwc); | |
72246da4 FB |
1859 | spin_unlock_irqrestore(&dwc->lock, flags); |
1860 | ||
1861 | return ret; | |
1862 | } | |
1863 | ||
1864 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1865 | int is_selfpowered) | |
1866 | { | |
1867 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 1868 | unsigned long flags; |
72246da4 | 1869 | |
249a4569 | 1870 | spin_lock_irqsave(&dwc->lock, flags); |
bcdea503 | 1871 | g->is_selfpowered = !!is_selfpowered; |
249a4569 | 1872 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
1873 | |
1874 | return 0; | |
1875 | } | |
1876 | ||
7b2a0368 | 1877 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) |
72246da4 FB |
1878 | { |
1879 | u32 reg; | |
61d58242 | 1880 | u32 timeout = 500; |
72246da4 | 1881 | |
fc8bb91b FB |
1882 | if (pm_runtime_suspended(dwc->dev)) |
1883 | return 0; | |
1884 | ||
72246da4 | 1885 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
8db7ed15 | 1886 | if (is_on) { |
802fde98 PZ |
1887 | if (dwc->revision <= DWC3_REVISION_187A) { |
1888 | reg &= ~DWC3_DCTL_TRGTULST_MASK; | |
1889 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
1890 | } | |
1891 | ||
1892 | if (dwc->revision >= DWC3_REVISION_194A) | |
1893 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1894 | reg |= DWC3_DCTL_RUN_STOP; | |
7b2a0368 FB |
1895 | |
1896 | if (dwc->has_hibernation) | |
1897 | reg |= DWC3_DCTL_KEEP_CONNECT; | |
1898 | ||
9fcb3bd8 | 1899 | dwc->pullups_connected = true; |
8db7ed15 | 1900 | } else { |
72246da4 | 1901 | reg &= ~DWC3_DCTL_RUN_STOP; |
7b2a0368 FB |
1902 | |
1903 | if (dwc->has_hibernation && !suspend) | |
1904 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1905 | ||
9fcb3bd8 | 1906 | dwc->pullups_connected = false; |
8db7ed15 | 1907 | } |
72246da4 | 1908 | |
5b738211 | 1909 | dwc3_gadget_dctl_write_safe(dwc, reg); |
72246da4 FB |
1910 | |
1911 | do { | |
1912 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
b6d4e16e FB |
1913 | reg &= DWC3_DSTS_DEVCTRLHLT; |
1914 | } while (--timeout && !(!is_on ^ !reg)); | |
f2df679b FB |
1915 | |
1916 | if (!timeout) | |
1917 | return -ETIMEDOUT; | |
72246da4 | 1918 | |
6f17f74b | 1919 | return 0; |
72246da4 FB |
1920 | } |
1921 | ||
1922 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1923 | { | |
1924 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1925 | unsigned long flags; | |
6f17f74b | 1926 | int ret; |
72246da4 FB |
1927 | |
1928 | is_on = !!is_on; | |
1929 | ||
bb014736 BW |
1930 | /* |
1931 | * Per databook, when we want to stop the gadget, if a control transfer | |
1932 | * is still in process, complete it and get the core into setup phase. | |
1933 | */ | |
1934 | if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) { | |
1935 | reinit_completion(&dwc->ep0_in_setup); | |
1936 | ||
1937 | ret = wait_for_completion_timeout(&dwc->ep0_in_setup, | |
1938 | msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT)); | |
1939 | if (ret == 0) { | |
1940 | dev_err(dwc->dev, "timed out waiting for SETUP phase\n"); | |
1941 | return -ETIMEDOUT; | |
1942 | } | |
1943 | } | |
1944 | ||
72246da4 | 1945 | spin_lock_irqsave(&dwc->lock, flags); |
7b2a0368 | 1946 | ret = dwc3_gadget_run_stop(dwc, is_on, false); |
72246da4 FB |
1947 | spin_unlock_irqrestore(&dwc->lock, flags); |
1948 | ||
6f17f74b | 1949 | return ret; |
72246da4 FB |
1950 | } |
1951 | ||
8698e2ac FB |
1952 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
1953 | { | |
1954 | u32 reg; | |
1955 | ||
1956 | /* Enable all but Start and End of Frame IRQs */ | |
1957 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
1958 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
1959 | DWC3_DEVTEN_CMDCMPLTEN | | |
1960 | DWC3_DEVTEN_ERRTICERREN | | |
1961 | DWC3_DEVTEN_WKUPEVTEN | | |
8698e2ac FB |
1962 | DWC3_DEVTEN_CONNECTDONEEN | |
1963 | DWC3_DEVTEN_USBRSTEN | | |
1964 | DWC3_DEVTEN_DISCONNEVTEN); | |
1965 | ||
799e9dc8 FB |
1966 | if (dwc->revision < DWC3_REVISION_250A) |
1967 | reg |= DWC3_DEVTEN_ULSTCNGEN; | |
1968 | ||
8698e2ac FB |
1969 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); |
1970 | } | |
1971 | ||
1972 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
1973 | { | |
1974 | /* mask all interrupts */ | |
1975 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
1976 | } | |
1977 | ||
1978 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 1979 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 1980 | |
4e99472b | 1981 | /** |
bfad65ee FB |
1982 | * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG |
1983 | * @dwc: pointer to our context structure | |
4e99472b FB |
1984 | * |
1985 | * The following looks like complex but it's actually very simple. In order to | |
1986 | * calculate the number of packets we can burst at once on OUT transfers, we're | |
1987 | * gonna use RxFIFO size. | |
1988 | * | |
1989 | * To calculate RxFIFO size we need two numbers: | |
1990 | * MDWIDTH = size, in bits, of the internal memory bus | |
1991 | * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits) | |
1992 | * | |
1993 | * Given these two numbers, the formula is simple: | |
1994 | * | |
1995 | * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16; | |
1996 | * | |
1997 | * 24 bytes is for 3x SETUP packets | |
1998 | * 16 bytes is a clock domain crossing tolerance | |
1999 | * | |
2000 | * Given RxFIFO Size, NUMP = RxFIFOSize / 1024; | |
2001 | */ | |
2002 | static void dwc3_gadget_setup_nump(struct dwc3 *dwc) | |
2003 | { | |
2004 | u32 ram2_depth; | |
2005 | u32 mdwidth; | |
2006 | u32 nump; | |
2007 | u32 reg; | |
2008 | ||
2009 | ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7); | |
2010 | mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0); | |
2011 | ||
2012 | nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024; | |
2013 | nump = min_t(u32, nump, 16); | |
2014 | ||
2015 | /* update NumP */ | |
2016 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2017 | reg &= ~DWC3_DCFG_NUMP_MASK; | |
2018 | reg |= nump << DWC3_DCFG_NUMP_SHIFT; | |
2019 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2020 | } | |
2021 | ||
d7be2952 | 2022 | static int __dwc3_gadget_start(struct dwc3 *dwc) |
72246da4 | 2023 | { |
72246da4 | 2024 | struct dwc3_ep *dep; |
72246da4 FB |
2025 | int ret = 0; |
2026 | u32 reg; | |
2027 | ||
cf40b86b JY |
2028 | /* |
2029 | * Use IMOD if enabled via dwc->imod_interval. Otherwise, if | |
2030 | * the core supports IMOD, disable it. | |
2031 | */ | |
2032 | if (dwc->imod_interval) { | |
2033 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); | |
2034 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); | |
2035 | } else if (dwc3_has_imod(dwc)) { | |
2036 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0); | |
2037 | } | |
2038 | ||
2a58f9c1 FB |
2039 | /* |
2040 | * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP | |
2041 | * field instead of letting dwc3 itself calculate that automatically. | |
2042 | * | |
2043 | * This way, we maximize the chances that we'll be able to get several | |
2044 | * bursts of data without going through any sort of endpoint throttling. | |
2045 | */ | |
2046 | reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); | |
01b0e2cc TN |
2047 | if (dwc3_is_usb31(dwc)) |
2048 | reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL; | |
2049 | else | |
2050 | reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL; | |
2051 | ||
2a58f9c1 FB |
2052 | dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); |
2053 | ||
4e99472b FB |
2054 | dwc3_gadget_setup_nump(dwc); |
2055 | ||
72246da4 FB |
2056 | /* Start with SuperSpeed Default */ |
2057 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
2058 | ||
2059 | dep = dwc->eps[0]; | |
a2d23f08 | 2060 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
2061 | if (ret) { |
2062 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 2063 | goto err0; |
72246da4 FB |
2064 | } |
2065 | ||
2066 | dep = dwc->eps[1]; | |
a2d23f08 | 2067 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
2068 | if (ret) { |
2069 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 2070 | goto err1; |
72246da4 FB |
2071 | } |
2072 | ||
2073 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 2074 | dwc->ep0state = EP0_SETUP_PHASE; |
88b1bb1f | 2075 | dwc->link_state = DWC3_LINK_STATE_SS_DIS; |
72246da4 FB |
2076 | dwc3_ep0_out_start(dwc); |
2077 | ||
8698e2ac FB |
2078 | dwc3_gadget_enable_irq(dwc); |
2079 | ||
72246da4 FB |
2080 | return 0; |
2081 | ||
b0d7ffd4 | 2082 | err1: |
d7be2952 | 2083 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
b0d7ffd4 FB |
2084 | |
2085 | err0: | |
72246da4 FB |
2086 | return ret; |
2087 | } | |
2088 | ||
d7be2952 FB |
2089 | static int dwc3_gadget_start(struct usb_gadget *g, |
2090 | struct usb_gadget_driver *driver) | |
72246da4 FB |
2091 | { |
2092 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2093 | unsigned long flags; | |
d7be2952 | 2094 | int ret = 0; |
8698e2ac | 2095 | int irq; |
72246da4 | 2096 | |
9522def4 | 2097 | irq = dwc->irq_gadget; |
d7be2952 FB |
2098 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, |
2099 | IRQF_SHARED, "dwc3", dwc->ev_buf); | |
2100 | if (ret) { | |
2101 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
2102 | irq, ret); | |
2103 | goto err0; | |
2104 | } | |
2105 | ||
72246da4 | 2106 | spin_lock_irqsave(&dwc->lock, flags); |
d7be2952 FB |
2107 | if (dwc->gadget_driver) { |
2108 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
2109 | dwc->gadget.name, | |
2110 | dwc->gadget_driver->driver.name); | |
2111 | ret = -EBUSY; | |
2112 | goto err1; | |
2113 | } | |
2114 | ||
2115 | dwc->gadget_driver = driver; | |
2116 | ||
fc8bb91b FB |
2117 | if (pm_runtime_active(dwc->dev)) |
2118 | __dwc3_gadget_start(dwc); | |
2119 | ||
d7be2952 FB |
2120 | spin_unlock_irqrestore(&dwc->lock, flags); |
2121 | ||
2122 | return 0; | |
2123 | ||
2124 | err1: | |
2125 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2126 | free_irq(irq, dwc); | |
2127 | ||
2128 | err0: | |
2129 | return ret; | |
2130 | } | |
72246da4 | 2131 | |
d7be2952 FB |
2132 | static void __dwc3_gadget_stop(struct dwc3 *dwc) |
2133 | { | |
8698e2ac | 2134 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
2135 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
2136 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
d7be2952 | 2137 | } |
72246da4 | 2138 | |
d7be2952 FB |
2139 | static int dwc3_gadget_stop(struct usb_gadget *g) |
2140 | { | |
2141 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2142 | unsigned long flags; | |
72246da4 | 2143 | |
d7be2952 | 2144 | spin_lock_irqsave(&dwc->lock, flags); |
76a638f8 BW |
2145 | |
2146 | if (pm_runtime_suspended(dwc->dev)) | |
2147 | goto out; | |
2148 | ||
d7be2952 | 2149 | __dwc3_gadget_stop(dwc); |
76a638f8 | 2150 | |
76a638f8 | 2151 | out: |
d7be2952 | 2152 | dwc->gadget_driver = NULL; |
72246da4 FB |
2153 | spin_unlock_irqrestore(&dwc->lock, flags); |
2154 | ||
3f308d17 | 2155 | free_irq(dwc->irq_gadget, dwc->ev_buf); |
b0d7ffd4 | 2156 | |
72246da4 FB |
2157 | return 0; |
2158 | } | |
802fde98 | 2159 | |
729dcffd AKV |
2160 | static void dwc3_gadget_config_params(struct usb_gadget *g, |
2161 | struct usb_dcd_config_params *params) | |
2162 | { | |
2163 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2164 | ||
54fb5ba6 TN |
2165 | params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED; |
2166 | params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED; | |
2167 | ||
2168 | /* Recommended BESL */ | |
2169 | if (!dwc->dis_enblslpm_quirk) { | |
17b63704 TN |
2170 | /* |
2171 | * If the recommended BESL baseline is 0 or if the BESL deep is | |
2172 | * less than 2, Microsoft's Windows 10 host usb stack will issue | |
2173 | * a usb reset immediately after it receives the extended BOS | |
2174 | * descriptor and the enumeration will fail. To maintain | |
2175 | * compatibility with the Windows' usb stack, let's set the | |
2176 | * recommended BESL baseline to 1 and clamp the BESL deep to be | |
2177 | * within 2 to 15. | |
2178 | */ | |
2179 | params->besl_baseline = 1; | |
54fb5ba6 | 2180 | if (dwc->is_utmi_l1_suspend) |
17b63704 TN |
2181 | params->besl_deep = |
2182 | clamp_t(u8, dwc->hird_threshold, 2, 15); | |
54fb5ba6 TN |
2183 | } |
2184 | ||
729dcffd AKV |
2185 | /* U1 Device exit Latency */ |
2186 | if (dwc->dis_u1_entry_quirk) | |
2187 | params->bU1devExitLat = 0; | |
2188 | else | |
2189 | params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT; | |
2190 | ||
2191 | /* U2 Device exit Latency */ | |
2192 | if (dwc->dis_u2_entry_quirk) | |
2193 | params->bU2DevExitLat = 0; | |
2194 | else | |
2195 | params->bU2DevExitLat = | |
2196 | cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT); | |
2197 | } | |
2198 | ||
7d8d0639 FB |
2199 | static void dwc3_gadget_set_speed(struct usb_gadget *g, |
2200 | enum usb_device_speed speed) | |
2201 | { | |
2202 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2203 | unsigned long flags; | |
2204 | u32 reg; | |
2205 | ||
2206 | spin_lock_irqsave(&dwc->lock, flags); | |
2207 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2208 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
2209 | ||
2210 | /* | |
2211 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
2212 | * which would cause metastability state on Run/Stop | |
2213 | * bit if we try to force the IP to USB2-only mode. | |
2214 | * | |
2215 | * Because of that, we cannot configure the IP to any | |
2216 | * speed other than the SuperSpeed | |
2217 | * | |
2218 | * Refers to: | |
2219 | * | |
2220 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
2221 | * USB 2.0 Mode | |
2222 | */ | |
42bf02ec RQ |
2223 | if (dwc->revision < DWC3_REVISION_220A && |
2224 | !dwc->dis_metastability_quirk) { | |
7d8d0639 FB |
2225 | reg |= DWC3_DCFG_SUPERSPEED; |
2226 | } else { | |
2227 | switch (speed) { | |
2228 | case USB_SPEED_LOW: | |
2229 | reg |= DWC3_DCFG_LOWSPEED; | |
2230 | break; | |
2231 | case USB_SPEED_FULL: | |
2232 | reg |= DWC3_DCFG_FULLSPEED; | |
2233 | break; | |
2234 | case USB_SPEED_HIGH: | |
2235 | reg |= DWC3_DCFG_HIGHSPEED; | |
2236 | break; | |
2237 | case USB_SPEED_SUPER: | |
2238 | reg |= DWC3_DCFG_SUPERSPEED; | |
2239 | break; | |
2240 | case USB_SPEED_SUPER_PLUS: | |
2f3090c6 TN |
2241 | if (dwc3_is_usb31(dwc)) |
2242 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; | |
2243 | else | |
2244 | reg |= DWC3_DCFG_SUPERSPEED; | |
7d8d0639 FB |
2245 | break; |
2246 | default: | |
2247 | dev_err(dwc->dev, "invalid speed (%d)\n", speed); | |
2248 | ||
2249 | if (dwc->revision & DWC3_REVISION_IS_DWC31) | |
2250 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; | |
2251 | else | |
2252 | reg |= DWC3_DCFG_SUPERSPEED; | |
2253 | } | |
2254 | } | |
2255 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2256 | ||
2257 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2258 | } | |
2259 | ||
72246da4 FB |
2260 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
2261 | .get_frame = dwc3_gadget_get_frame, | |
2262 | .wakeup = dwc3_gadget_wakeup, | |
2263 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
2264 | .pullup = dwc3_gadget_pullup, | |
2265 | .udc_start = dwc3_gadget_start, | |
2266 | .udc_stop = dwc3_gadget_stop, | |
7d8d0639 | 2267 | .udc_set_speed = dwc3_gadget_set_speed, |
729dcffd | 2268 | .get_config_params = dwc3_gadget_config_params, |
72246da4 FB |
2269 | }; |
2270 | ||
2271 | /* -------------------------------------------------------------------------- */ | |
2272 | ||
8f1c99cd | 2273 | static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep) |
72246da4 | 2274 | { |
8f1c99cd | 2275 | struct dwc3 *dwc = dep->dwc; |
72246da4 | 2276 | |
8f1c99cd FB |
2277 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
2278 | dep->endpoint.maxburst = 1; | |
2279 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; | |
2280 | if (!dep->direction) | |
2281 | dwc->gadget.ep0 = &dep->endpoint; | |
f3bcfc7e | 2282 | |
8f1c99cd | 2283 | dep->endpoint.caps.type_control = true; |
72246da4 | 2284 | |
8f1c99cd FB |
2285 | return 0; |
2286 | } | |
72246da4 | 2287 | |
8f1c99cd FB |
2288 | static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep) |
2289 | { | |
2290 | struct dwc3 *dwc = dep->dwc; | |
2291 | int mdwidth; | |
8f1c99cd | 2292 | int size; |
72246da4 | 2293 | |
8f1c99cd FB |
2294 | mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); |
2295 | /* MDWIDTH is represented in bits, we need it in bytes */ | |
2296 | mdwidth /= 8; | |
6a1e3ef4 | 2297 | |
8f1c99cd FB |
2298 | size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1)); |
2299 | if (dwc3_is_usb31(dwc)) | |
586f4335 | 2300 | size = DWC31_GTXFIFOSIZ_TXFDEP(size); |
8f1c99cd | 2301 | else |
586f4335 | 2302 | size = DWC3_GTXFIFOSIZ_TXFDEP(size); |
39ebb05c | 2303 | |
8f1c99cd FB |
2304 | /* FIFO Depth is in MDWDITH bytes. Multiply */ |
2305 | size *= mdwidth; | |
39ebb05c | 2306 | |
8f1c99cd | 2307 | /* |
d94ea531 TN |
2308 | * To meet performance requirement, a minimum TxFIFO size of 3x |
2309 | * MaxPacketSize is recommended for endpoints that support burst and a | |
2310 | * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't | |
2311 | * support burst. Use those numbers and we can calculate the max packet | |
2312 | * limit as below. | |
8f1c99cd | 2313 | */ |
d94ea531 TN |
2314 | if (dwc->maximum_speed >= USB_SPEED_SUPER) |
2315 | size /= 3; | |
2316 | else | |
2317 | size /= 2; | |
28781789 | 2318 | |
8f1c99cd | 2319 | usb_ep_set_maxpacket_limit(&dep->endpoint, size); |
28781789 | 2320 | |
8f1c99cd FB |
2321 | dep->endpoint.max_streams = 15; |
2322 | dep->endpoint.ops = &dwc3_gadget_ep_ops; | |
2323 | list_add_tail(&dep->endpoint.ep_list, | |
2324 | &dwc->gadget.ep_list); | |
2325 | dep->endpoint.caps.type_iso = true; | |
2326 | dep->endpoint.caps.type_bulk = true; | |
2327 | dep->endpoint.caps.type_int = true; | |
28781789 | 2328 | |
8f1c99cd FB |
2329 | return dwc3_alloc_trb_pool(dep); |
2330 | } | |
28781789 | 2331 | |
8f1c99cd FB |
2332 | static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep) |
2333 | { | |
2334 | struct dwc3 *dwc = dep->dwc; | |
d94ea531 TN |
2335 | int mdwidth; |
2336 | int size; | |
2337 | ||
2338 | mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); | |
2339 | ||
2340 | /* MDWIDTH is represented in bits, convert to bytes */ | |
2341 | mdwidth /= 8; | |
28781789 | 2342 | |
d94ea531 TN |
2343 | /* All OUT endpoints share a single RxFIFO space */ |
2344 | size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0)); | |
2345 | if (dwc3_is_usb31(dwc)) | |
2346 | size = DWC31_GRXFIFOSIZ_RXFDEP(size); | |
2347 | else | |
2348 | size = DWC3_GRXFIFOSIZ_RXFDEP(size); | |
2349 | ||
2350 | /* FIFO depth is in MDWDITH bytes */ | |
2351 | size *= mdwidth; | |
2352 | ||
2353 | /* | |
2354 | * To meet performance requirement, a minimum recommended RxFIFO size | |
2355 | * is defined as follow: | |
2356 | * RxFIFO size >= (3 x MaxPacketSize) + | |
2357 | * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin) | |
2358 | * | |
2359 | * Then calculate the max packet limit as below. | |
2360 | */ | |
2361 | size -= (3 * 8) + 16; | |
2362 | if (size < 0) | |
2363 | size = 0; | |
2364 | else | |
2365 | size /= 3; | |
2366 | ||
2367 | usb_ep_set_maxpacket_limit(&dep->endpoint, size); | |
8f1c99cd FB |
2368 | dep->endpoint.max_streams = 15; |
2369 | dep->endpoint.ops = &dwc3_gadget_ep_ops; | |
2370 | list_add_tail(&dep->endpoint.ep_list, | |
2371 | &dwc->gadget.ep_list); | |
2372 | dep->endpoint.caps.type_iso = true; | |
2373 | dep->endpoint.caps.type_bulk = true; | |
2374 | dep->endpoint.caps.type_int = true; | |
72246da4 | 2375 | |
8f1c99cd FB |
2376 | return dwc3_alloc_trb_pool(dep); |
2377 | } | |
72246da4 | 2378 | |
8f1c99cd FB |
2379 | static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum) |
2380 | { | |
2381 | struct dwc3_ep *dep; | |
2382 | bool direction = epnum & 1; | |
2383 | int ret; | |
2384 | u8 num = epnum >> 1; | |
25b8ff68 | 2385 | |
8f1c99cd FB |
2386 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
2387 | if (!dep) | |
2388 | return -ENOMEM; | |
2389 | ||
2390 | dep->dwc = dwc; | |
2391 | dep->number = epnum; | |
2392 | dep->direction = direction; | |
2393 | dep->regs = dwc->regs + DWC3_DEP_BASE(epnum); | |
2394 | dwc->eps[epnum] = dep; | |
d92021f6 TN |
2395 | dep->combo_num = 0; |
2396 | dep->start_cmd_status = 0; | |
8f1c99cd FB |
2397 | |
2398 | snprintf(dep->name, sizeof(dep->name), "ep%u%s", num, | |
2399 | direction ? "in" : "out"); | |
2400 | ||
2401 | dep->endpoint.name = dep->name; | |
2402 | ||
2403 | if (!(dep->number > 1)) { | |
2404 | dep->endpoint.desc = &dwc3_gadget_ep0_desc; | |
2405 | dep->endpoint.comp_desc = NULL; | |
2406 | } | |
2407 | ||
8f1c99cd FB |
2408 | if (num == 0) |
2409 | ret = dwc3_gadget_init_control_endpoint(dep); | |
2410 | else if (direction) | |
2411 | ret = dwc3_gadget_init_in_endpoint(dep); | |
2412 | else | |
2413 | ret = dwc3_gadget_init_out_endpoint(dep); | |
2414 | ||
2415 | if (ret) | |
2416 | return ret; | |
a474d3b7 | 2417 | |
8f1c99cd FB |
2418 | dep->endpoint.caps.dir_in = direction; |
2419 | dep->endpoint.caps.dir_out = !direction; | |
a474d3b7 | 2420 | |
8f1c99cd FB |
2421 | INIT_LIST_HEAD(&dep->pending_list); |
2422 | INIT_LIST_HEAD(&dep->started_list); | |
d5443bbf | 2423 | INIT_LIST_HEAD(&dep->cancelled_list); |
8f1c99cd FB |
2424 | |
2425 | return 0; | |
2426 | } | |
2427 | ||
2428 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total) | |
2429 | { | |
2430 | u8 epnum; | |
2431 | ||
2432 | INIT_LIST_HEAD(&dwc->gadget.ep_list); | |
2433 | ||
2434 | for (epnum = 0; epnum < total; epnum++) { | |
2435 | int ret; | |
2436 | ||
2437 | ret = dwc3_gadget_init_endpoint(dwc, epnum); | |
2438 | if (ret) | |
2439 | return ret; | |
72246da4 FB |
2440 | } |
2441 | ||
2442 | return 0; | |
2443 | } | |
2444 | ||
2445 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) | |
2446 | { | |
2447 | struct dwc3_ep *dep; | |
2448 | u8 epnum; | |
2449 | ||
2450 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2451 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2452 | if (!dep) |
2453 | continue; | |
5bf8fae3 GC |
2454 | /* |
2455 | * Physical endpoints 0 and 1 are special; they form the | |
2456 | * bi-directional USB endpoint 0. | |
2457 | * | |
2458 | * For those two physical endpoints, we don't allocate a TRB | |
2459 | * pool nor do we add them the endpoints list. Due to that, we | |
2460 | * shouldn't do these two operations otherwise we would end up | |
2461 | * with all sorts of bugs when removing dwc3.ko. | |
2462 | */ | |
2463 | if (epnum != 0 && epnum != 1) { | |
2464 | dwc3_free_trb_pool(dep); | |
72246da4 | 2465 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 2466 | } |
72246da4 FB |
2467 | |
2468 | kfree(dep); | |
2469 | } | |
2470 | } | |
2471 | ||
72246da4 | 2472 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 2473 | |
8f608e8a FB |
2474 | static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep, |
2475 | struct dwc3_request *req, struct dwc3_trb *trb, | |
2476 | const struct dwc3_event_depevt *event, int status, int chain) | |
72246da4 | 2477 | { |
72246da4 | 2478 | unsigned int count; |
72246da4 | 2479 | |
dc55c67e | 2480 | dwc3_ep_inc_deq(dep); |
a9c3ca5f | 2481 | |
2c4cbe6e | 2482 | trace_dwc3_complete_trb(dep, trb); |
09fe1f8d | 2483 | req->num_trbs--; |
2c4cbe6e | 2484 | |
e5b36ae2 FB |
2485 | /* |
2486 | * If we're in the middle of series of chained TRBs and we | |
2487 | * receive a short transfer along the way, DWC3 will skip | |
2488 | * through all TRBs including the last TRB in the chain (the | |
2489 | * where CHN bit is zero. DWC3 will also avoid clearing HWO | |
2490 | * bit and SW has to do it manually. | |
2491 | * | |
2492 | * We're going to do that here to avoid problems of HW trying | |
2493 | * to use bogus TRBs for transfers. | |
2494 | */ | |
2495 | if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO)) | |
2496 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; | |
2497 | ||
6abfa0f5 TN |
2498 | /* |
2499 | * For isochronous transfers, the first TRB in a service interval must | |
2500 | * have the Isoc-First type. Track and report its interval frame number. | |
2501 | */ | |
2502 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
2503 | (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) { | |
2504 | unsigned int frame_number; | |
2505 | ||
2506 | frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl); | |
2507 | frame_number &= ~(dep->interval - 1); | |
2508 | req->request.frame_number = frame_number; | |
2509 | } | |
2510 | ||
c6267a51 FB |
2511 | /* |
2512 | * If we're dealing with unaligned size OUT transfer, we will be left | |
2513 | * with one TRB pending in the ring. We need to manually clear HWO bit | |
2514 | * from that TRB. | |
2515 | */ | |
1a22ec64 FB |
2516 | |
2517 | if (req->needs_extra_trb && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) { | |
c6267a51 FB |
2518 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; |
2519 | return 1; | |
2520 | } | |
2521 | ||
e5ba5ec8 | 2522 | count = trb->size & DWC3_TRB_SIZE_MASK; |
e62c5bc5 | 2523 | req->remaining += count; |
e5ba5ec8 | 2524 | |
35b2719e FB |
2525 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
2526 | return 1; | |
2527 | ||
d80fe1b6 | 2528 | if (event->status & DEPEVT_STATUS_SHORT && !chain) |
e5ba5ec8 | 2529 | return 1; |
f99f53f2 | 2530 | |
5ee85897 AKV |
2531 | if ((trb->ctrl & DWC3_TRB_CTRL_IOC) || |
2532 | (trb->ctrl & DWC3_TRB_CTRL_LST)) | |
e5ba5ec8 | 2533 | return 1; |
f99f53f2 | 2534 | |
e5ba5ec8 PA |
2535 | return 0; |
2536 | } | |
2537 | ||
d3692953 FB |
2538 | static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep, |
2539 | struct dwc3_request *req, const struct dwc3_event_depevt *event, | |
2540 | int status) | |
2541 | { | |
2542 | struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue]; | |
2543 | struct scatterlist *sg = req->sg; | |
2544 | struct scatterlist *s; | |
2545 | unsigned int pending = req->num_pending_sgs; | |
2546 | unsigned int i; | |
2547 | int ret = 0; | |
2548 | ||
2549 | for_each_sg(sg, s, pending, i) { | |
2550 | trb = &dep->trb_pool[dep->trb_dequeue]; | |
2551 | ||
2552 | if (trb->ctrl & DWC3_TRB_CTRL_HWO) | |
2553 | break; | |
2554 | ||
2555 | req->sg = sg_next(s); | |
2556 | req->num_pending_sgs--; | |
2557 | ||
2558 | ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req, | |
2559 | trb, event, status, true); | |
2560 | if (ret) | |
2561 | break; | |
2562 | } | |
2563 | ||
2564 | return ret; | |
2565 | } | |
2566 | ||
2567 | static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep, | |
2568 | struct dwc3_request *req, const struct dwc3_event_depevt *event, | |
2569 | int status) | |
2570 | { | |
2571 | struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue]; | |
2572 | ||
2573 | return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb, | |
2574 | event, status, false); | |
2575 | } | |
2576 | ||
e0c42ce5 FB |
2577 | static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req) |
2578 | { | |
49e0590e | 2579 | return req->num_pending_sgs == 0; |
e0c42ce5 FB |
2580 | } |
2581 | ||
f38e35dd FB |
2582 | static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep, |
2583 | const struct dwc3_event_depevt *event, | |
2584 | struct dwc3_request *req, int status) | |
2585 | { | |
2586 | int ret; | |
2587 | ||
2588 | if (req->num_pending_sgs) | |
2589 | ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event, | |
2590 | status); | |
2591 | else | |
2592 | ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event, | |
2593 | status); | |
2594 | ||
1a22ec64 | 2595 | if (req->needs_extra_trb) { |
f38e35dd FB |
2596 | ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event, |
2597 | status); | |
1a22ec64 | 2598 | req->needs_extra_trb = false; |
f38e35dd FB |
2599 | } |
2600 | ||
2601 | req->request.actual = req->request.length - req->remaining; | |
2602 | ||
49e0590e | 2603 | if (!dwc3_gadget_ep_request_completed(req)) { |
f38e35dd FB |
2604 | __dwc3_gadget_kick_transfer(dep); |
2605 | goto out; | |
2606 | } | |
2607 | ||
2608 | dwc3_gadget_giveback(dep, req, status); | |
2609 | ||
2610 | out: | |
2611 | return ret; | |
2612 | } | |
2613 | ||
12a3a4ad | 2614 | static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep, |
8f608e8a | 2615 | const struct dwc3_event_depevt *event, int status) |
e5ba5ec8 | 2616 | { |
6afbdb57 FB |
2617 | struct dwc3_request *req; |
2618 | struct dwc3_request *tmp; | |
e5ba5ec8 | 2619 | |
6afbdb57 | 2620 | list_for_each_entry_safe(req, tmp, &dep->started_list, list) { |
fee73e61 | 2621 | int ret; |
e5b36ae2 | 2622 | |
f38e35dd FB |
2623 | ret = dwc3_gadget_ep_cleanup_completed_request(dep, event, |
2624 | req, status); | |
58f0218a | 2625 | if (ret) |
72246da4 | 2626 | break; |
31162af4 | 2627 | } |
72246da4 FB |
2628 | } |
2629 | ||
ee3638b8 FB |
2630 | static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep, |
2631 | const struct dwc3_event_depevt *event) | |
2632 | { | |
f62afb49 | 2633 | dep->frame_number = event->parameters; |
ee3638b8 FB |
2634 | } |
2635 | ||
8f608e8a FB |
2636 | static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep, |
2637 | const struct dwc3_event_depevt *event) | |
72246da4 | 2638 | { |
8f608e8a | 2639 | struct dwc3 *dwc = dep->dwc; |
72246da4 | 2640 | unsigned status = 0; |
6d8a0196 | 2641 | bool stop = false; |
72246da4 | 2642 | |
ee3638b8 FB |
2643 | dwc3_gadget_endpoint_frame_from_event(dep, event); |
2644 | ||
72246da4 FB |
2645 | if (event->status & DEPEVT_STATUS_BUSERR) |
2646 | status = -ECONNRESET; | |
2647 | ||
6d8a0196 FB |
2648 | if (event->status & DEPEVT_STATUS_MISSED_ISOC) { |
2649 | status = -EXDEV; | |
d513320f FB |
2650 | |
2651 | if (list_empty(&dep->started_list)) | |
2652 | stop = true; | |
6d8a0196 FB |
2653 | } |
2654 | ||
5f2e7975 | 2655 | dwc3_gadget_ep_cleanup_completed_requests(dep, event, status); |
fae2b904 | 2656 | |
a114c4ca | 2657 | if (stop) |
c5353b22 | 2658 | dwc3_stop_active_transfer(dep, true, true); |
6d8a0196 | 2659 | |
fae2b904 FB |
2660 | /* |
2661 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
2662 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
2663 | */ | |
2664 | if (dwc->revision < DWC3_REVISION_183A) { | |
2665 | u32 reg; | |
2666 | int i; | |
2667 | ||
2668 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 2669 | dep = dwc->eps[i]; |
fae2b904 FB |
2670 | |
2671 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
2672 | continue; | |
2673 | ||
aa3342c8 | 2674 | if (!list_empty(&dep->started_list)) |
fae2b904 FB |
2675 | return; |
2676 | } | |
2677 | ||
2678 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2679 | reg |= dwc->u1u2; | |
2680 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2681 | ||
2682 | dwc->u1u2 = 0; | |
2683 | } | |
72246da4 FB |
2684 | } |
2685 | ||
8f608e8a FB |
2686 | static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep, |
2687 | const struct dwc3_event_depevt *event) | |
32033865 | 2688 | { |
ee3638b8 | 2689 | dwc3_gadget_endpoint_frame_from_event(dep, event); |
36f05d36 TN |
2690 | |
2691 | /* | |
2692 | * The XferNotReady event is generated only once before the endpoint | |
2693 | * starts. It will be generated again when END_TRANSFER command is | |
2694 | * issued. For some controller versions, the XferNotReady event may be | |
2695 | * generated while the END_TRANSFER command is still in process. Ignore | |
2696 | * it and wait for the next XferNotReady event after the command is | |
2697 | * completed. | |
2698 | */ | |
2699 | if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) | |
2700 | return; | |
2701 | ||
25abad6a | 2702 | (void) __dwc3_gadget_start_isoc(dep); |
32033865 FB |
2703 | } |
2704 | ||
72246da4 FB |
2705 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
2706 | const struct dwc3_event_depevt *event) | |
2707 | { | |
2708 | struct dwc3_ep *dep; | |
2709 | u8 epnum = event->endpoint_number; | |
76a638f8 | 2710 | u8 cmd; |
72246da4 FB |
2711 | |
2712 | dep = dwc->eps[epnum]; | |
2713 | ||
d7fd41c6 | 2714 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
3aec9915 | 2715 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) |
d7fd41c6 JD |
2716 | return; |
2717 | ||
2718 | /* Handle only EPCMDCMPLT when EP disabled */ | |
2719 | if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT) | |
2720 | return; | |
2721 | } | |
3336abb5 | 2722 | |
72246da4 FB |
2723 | if (epnum == 0 || epnum == 1) { |
2724 | dwc3_ep0_interrupt(dwc, event); | |
2725 | return; | |
2726 | } | |
2727 | ||
2728 | switch (event->endpoint_event) { | |
72246da4 | 2729 | case DWC3_DEPEVT_XFERINPROGRESS: |
8f608e8a | 2730 | dwc3_gadget_endpoint_transfer_in_progress(dep, event); |
72246da4 FB |
2731 | break; |
2732 | case DWC3_DEPEVT_XFERNOTREADY: | |
8f608e8a | 2733 | dwc3_gadget_endpoint_transfer_not_ready(dep, event); |
879631aa | 2734 | break; |
72246da4 | 2735 | case DWC3_DEPEVT_EPCMDCMPLT: |
76a638f8 BW |
2736 | cmd = DEPEVT_PARAMETER_CMD(event->parameters); |
2737 | ||
2738 | if (cmd == DWC3_DEPCMD_ENDTRANSFER) { | |
c58d8bfc | 2739 | dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; |
3aec9915 | 2740 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; |
fec9095b | 2741 | dwc3_gadget_ep_cleanup_cancelled_requests(dep); |
da10bcdd TN |
2742 | if ((dep->flags & DWC3_EP_DELAY_START) && |
2743 | !usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
2744 | __dwc3_gadget_kick_transfer(dep); | |
2745 | ||
2746 | dep->flags &= ~DWC3_EP_DELAY_START; | |
76a638f8 BW |
2747 | } |
2748 | break; | |
a24a6ab1 | 2749 | case DWC3_DEPEVT_STREAMEVT: |
742a4fff | 2750 | case DWC3_DEPEVT_XFERCOMPLETE: |
76a638f8 | 2751 | case DWC3_DEPEVT_RXTXFIFOEVT: |
72246da4 FB |
2752 | break; |
2753 | } | |
2754 | } | |
2755 | ||
2756 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
2757 | { | |
2758 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
2759 | spin_unlock(&dwc->lock); | |
2760 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
2761 | spin_lock(&dwc->lock); | |
2762 | } | |
2763 | } | |
2764 | ||
bc5ba2e0 FB |
2765 | static void dwc3_suspend_gadget(struct dwc3 *dwc) |
2766 | { | |
73a30bfc | 2767 | if (dwc->gadget_driver && dwc->gadget_driver->suspend) { |
bc5ba2e0 FB |
2768 | spin_unlock(&dwc->lock); |
2769 | dwc->gadget_driver->suspend(&dwc->gadget); | |
2770 | spin_lock(&dwc->lock); | |
2771 | } | |
2772 | } | |
2773 | ||
2774 | static void dwc3_resume_gadget(struct dwc3 *dwc) | |
2775 | { | |
73a30bfc | 2776 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
bc5ba2e0 FB |
2777 | spin_unlock(&dwc->lock); |
2778 | dwc->gadget_driver->resume(&dwc->gadget); | |
5c7b3b02 | 2779 | spin_lock(&dwc->lock); |
8e74475b FB |
2780 | } |
2781 | } | |
2782 | ||
2783 | static void dwc3_reset_gadget(struct dwc3 *dwc) | |
2784 | { | |
2785 | if (!dwc->gadget_driver) | |
2786 | return; | |
2787 | ||
2788 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) { | |
2789 | spin_unlock(&dwc->lock); | |
2790 | usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver); | |
bc5ba2e0 FB |
2791 | spin_lock(&dwc->lock); |
2792 | } | |
2793 | } | |
2794 | ||
c5353b22 FB |
2795 | static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, |
2796 | bool interrupt) | |
72246da4 | 2797 | { |
72246da4 FB |
2798 | struct dwc3_gadget_ep_cmd_params params; |
2799 | u32 cmd; | |
2800 | int ret; | |
2801 | ||
c58d8bfc TN |
2802 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) || |
2803 | (dep->flags & DWC3_EP_END_TRANSFER_PENDING)) | |
3daf74d7 PA |
2804 | return; |
2805 | ||
57911504 PA |
2806 | /* |
2807 | * NOTICE: We are violating what the Databook says about the | |
2808 | * EndTransfer command. Ideally we would _always_ wait for the | |
2809 | * EndTransfer Command Completion IRQ, but that's causing too | |
2810 | * much trouble synchronizing between us and gadget driver. | |
2811 | * | |
2812 | * We have discussed this with the IP Provider and it was | |
cf2f8b63 | 2813 | * suggested to giveback all requests here. |
57911504 PA |
2814 | * |
2815 | * Note also that a similar handling was tested by Synopsys | |
2816 | * (thanks a lot Paul) and nothing bad has come out of it. | |
cf2f8b63 TN |
2817 | * In short, what we're doing is issuing EndTransfer with |
2818 | * CMDIOC bit set and delay kicking transfer until the | |
2819 | * EndTransfer command had completed. | |
06281d46 JY |
2820 | * |
2821 | * As of IP version 3.10a of the DWC_usb3 IP, the controller | |
2822 | * supports a mode to work around the above limitation. The | |
2823 | * software can poll the CMDACT bit in the DEPCMD register | |
2824 | * after issuing a EndTransfer command. This mode is enabled | |
2825 | * by writing GUCTL2[14]. This polling is already done in the | |
2826 | * dwc3_send_gadget_ep_cmd() function so if the mode is | |
2827 | * enabled, the EndTransfer command will have completed upon | |
cf2f8b63 | 2828 | * returning from this function. |
06281d46 JY |
2829 | * |
2830 | * This mode is NOT available on the DWC_usb31 IP. | |
57911504 PA |
2831 | */ |
2832 | ||
3daf74d7 | 2833 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
b992e681 | 2834 | cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; |
c5353b22 | 2835 | cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0; |
b4996a86 | 2836 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 | 2837 | memset(¶ms, 0, sizeof(params)); |
2cd4718d | 2838 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
3daf74d7 | 2839 | WARN_ON_ONCE(ret); |
b4996a86 | 2840 | dep->resource_index = 0; |
06281d46 | 2841 | |
d3abda5a TN |
2842 | if (!interrupt) |
2843 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; | |
c58d8bfc TN |
2844 | else |
2845 | dep->flags |= DWC3_EP_END_TRANSFER_PENDING; | |
72246da4 FB |
2846 | } |
2847 | ||
72246da4 FB |
2848 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) |
2849 | { | |
2850 | u32 epnum; | |
2851 | ||
2852 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2853 | struct dwc3_ep *dep; | |
72246da4 FB |
2854 | int ret; |
2855 | ||
2856 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2857 | if (!dep) |
2858 | continue; | |
72246da4 FB |
2859 | |
2860 | if (!(dep->flags & DWC3_EP_STALL)) | |
2861 | continue; | |
2862 | ||
2863 | dep->flags &= ~DWC3_EP_STALL; | |
2864 | ||
50c763f8 | 2865 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 FB |
2866 | WARN_ON_ONCE(ret); |
2867 | } | |
2868 | } | |
2869 | ||
2870 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
2871 | { | |
c4430a26 FB |
2872 | int reg; |
2873 | ||
1b6009ea TN |
2874 | dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET); |
2875 | ||
72246da4 FB |
2876 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
2877 | reg &= ~DWC3_DCTL_INITU1ENA; | |
72246da4 | 2878 | reg &= ~DWC3_DCTL_INITU2ENA; |
5b738211 | 2879 | dwc3_gadget_dctl_write_safe(dwc, reg); |
72246da4 | 2880 | |
72246da4 FB |
2881 | dwc3_disconnect_gadget(dwc); |
2882 | ||
2883 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
df62df56 | 2884 | dwc->setup_packet_pending = false; |
06a374ed | 2885 | usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED); |
fc8bb91b FB |
2886 | |
2887 | dwc->connected = false; | |
72246da4 FB |
2888 | } |
2889 | ||
72246da4 FB |
2890 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
2891 | { | |
2892 | u32 reg; | |
2893 | ||
fc8bb91b FB |
2894 | dwc->connected = true; |
2895 | ||
df62df56 FB |
2896 | /* |
2897 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
2898 | * would cause a missing Disconnect Event if there's a | |
2899 | * pending Setup Packet in the FIFO. | |
2900 | * | |
2901 | * There's no suggested workaround on the official Bug | |
2902 | * report, which states that "unless the driver/application | |
2903 | * is doing any special handling of a disconnect event, | |
2904 | * there is no functional issue". | |
2905 | * | |
2906 | * Unfortunately, it turns out that we _do_ some special | |
2907 | * handling of a disconnect event, namely complete all | |
2908 | * pending transfers, notify gadget driver of the | |
2909 | * disconnection, and so on. | |
2910 | * | |
2911 | * Our suggested workaround is to follow the Disconnect | |
2912 | * Event steps here, instead, based on a setup_packet_pending | |
b5d335e5 FB |
2913 | * flag. Such flag gets set whenever we have a SETUP_PENDING |
2914 | * status for EP0 TRBs and gets cleared on XferComplete for the | |
df62df56 FB |
2915 | * same endpoint. |
2916 | * | |
2917 | * Refers to: | |
2918 | * | |
2919 | * STAR#9000466709: RTL: Device : Disconnect event not | |
2920 | * generated if setup packet pending in FIFO | |
2921 | */ | |
2922 | if (dwc->revision < DWC3_REVISION_188A) { | |
2923 | if (dwc->setup_packet_pending) | |
2924 | dwc3_gadget_disconnect_interrupt(dwc); | |
2925 | } | |
2926 | ||
8e74475b | 2927 | dwc3_reset_gadget(dwc); |
72246da4 FB |
2928 | |
2929 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2930 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
5b738211 | 2931 | dwc3_gadget_dctl_write_safe(dwc, reg); |
3b637367 | 2932 | dwc->test_mode = false; |
72246da4 FB |
2933 | dwc3_clear_stall_all_ep(dwc); |
2934 | ||
2935 | /* Reset device address to zero */ | |
2936 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2937 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
2938 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
2939 | } |
2940 | ||
72246da4 FB |
2941 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
2942 | { | |
72246da4 FB |
2943 | struct dwc3_ep *dep; |
2944 | int ret; | |
2945 | u32 reg; | |
2946 | u8 speed; | |
2947 | ||
72246da4 FB |
2948 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2949 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
2950 | dwc->speed = speed; | |
2951 | ||
5fb6fdaf JY |
2952 | /* |
2953 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
2954 | * each time on Connect Done. | |
2955 | * | |
2956 | * Currently we always use the reset value. If any platform | |
2957 | * wants to set this to a different value, we need to add a | |
2958 | * setting and update GCTL.RAMCLKSEL here. | |
2959 | */ | |
72246da4 FB |
2960 | |
2961 | switch (speed) { | |
2da9ad76 | 2962 | case DWC3_DSTS_SUPERSPEED_PLUS: |
7580862b JY |
2963 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2964 | dwc->gadget.ep0->maxpacket = 512; | |
2965 | dwc->gadget.speed = USB_SPEED_SUPER_PLUS; | |
2966 | break; | |
2da9ad76 | 2967 | case DWC3_DSTS_SUPERSPEED: |
05870c5b FB |
2968 | /* |
2969 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
2970 | * would cause a missing USB3 Reset event. | |
2971 | * | |
2972 | * In such situations, we should force a USB3 Reset | |
2973 | * event by calling our dwc3_gadget_reset_interrupt() | |
2974 | * routine. | |
2975 | * | |
2976 | * Refers to: | |
2977 | * | |
2978 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
2979 | * not be generated always when the link enters poll | |
2980 | */ | |
2981 | if (dwc->revision < DWC3_REVISION_190A) | |
2982 | dwc3_gadget_reset_interrupt(dwc); | |
2983 | ||
72246da4 FB |
2984 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2985 | dwc->gadget.ep0->maxpacket = 512; | |
2986 | dwc->gadget.speed = USB_SPEED_SUPER; | |
2987 | break; | |
2da9ad76 | 2988 | case DWC3_DSTS_HIGHSPEED: |
72246da4 FB |
2989 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
2990 | dwc->gadget.ep0->maxpacket = 64; | |
2991 | dwc->gadget.speed = USB_SPEED_HIGH; | |
2992 | break; | |
9418ee15 | 2993 | case DWC3_DSTS_FULLSPEED: |
72246da4 FB |
2994 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
2995 | dwc->gadget.ep0->maxpacket = 64; | |
2996 | dwc->gadget.speed = USB_SPEED_FULL; | |
2997 | break; | |
2da9ad76 | 2998 | case DWC3_DSTS_LOWSPEED: |
72246da4 FB |
2999 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); |
3000 | dwc->gadget.ep0->maxpacket = 8; | |
3001 | dwc->gadget.speed = USB_SPEED_LOW; | |
3002 | break; | |
3003 | } | |
3004 | ||
61800263 TN |
3005 | dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket; |
3006 | ||
2b758350 PA |
3007 | /* Enable USB2 LPM Capability */ |
3008 | ||
ee5cd41c | 3009 | if ((dwc->revision > DWC3_REVISION_194A) && |
2da9ad76 JY |
3010 | (speed != DWC3_DSTS_SUPERSPEED) && |
3011 | (speed != DWC3_DSTS_SUPERSPEED_PLUS)) { | |
2b758350 PA |
3012 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
3013 | reg |= DWC3_DCFG_LPM_CAP; | |
3014 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
3015 | ||
3016 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3017 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
3018 | ||
16fe4f30 TN |
3019 | reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold | |
3020 | (dwc->is_utmi_l1_suspend << 4)); | |
2b758350 | 3021 | |
80caf7d2 HR |
3022 | /* |
3023 | * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and | |
3024 | * DCFG.LPMCap is set, core responses with an ACK and the | |
3025 | * BESL value in the LPM token is less than or equal to LPM | |
3026 | * NYET threshold. | |
3027 | */ | |
3028 | WARN_ONCE(dwc->revision < DWC3_REVISION_240A | |
3029 | && dwc->has_lpm_erratum, | |
9165dabb | 3030 | "LPM Erratum not available on dwc3 revisions < 2.40a\n"); |
80caf7d2 HR |
3031 | |
3032 | if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A) | |
2e487d28 | 3033 | reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold); |
80caf7d2 | 3034 | |
5b738211 | 3035 | dwc3_gadget_dctl_write_safe(dwc, reg); |
356363bf FB |
3036 | } else { |
3037 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3038 | reg &= ~DWC3_DCTL_HIRD_THRES_MASK; | |
5b738211 | 3039 | dwc3_gadget_dctl_write_safe(dwc, reg); |
2b758350 PA |
3040 | } |
3041 | ||
72246da4 | 3042 | dep = dwc->eps[0]; |
a2d23f08 | 3043 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY); |
72246da4 FB |
3044 | if (ret) { |
3045 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
3046 | return; | |
3047 | } | |
3048 | ||
3049 | dep = dwc->eps[1]; | |
a2d23f08 | 3050 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY); |
72246da4 FB |
3051 | if (ret) { |
3052 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
3053 | return; | |
3054 | } | |
3055 | ||
3056 | /* | |
3057 | * Configure PHY via GUSB3PIPECTLn if required. | |
3058 | * | |
3059 | * Update GTXFIFOSIZn | |
3060 | * | |
3061 | * In both cases reset values should be sufficient. | |
3062 | */ | |
3063 | } | |
3064 | ||
3065 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
3066 | { | |
72246da4 FB |
3067 | /* |
3068 | * TODO take core out of low power mode when that's | |
3069 | * implemented. | |
3070 | */ | |
3071 | ||
ad14d4e0 JL |
3072 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
3073 | spin_unlock(&dwc->lock); | |
3074 | dwc->gadget_driver->resume(&dwc->gadget); | |
3075 | spin_lock(&dwc->lock); | |
3076 | } | |
72246da4 FB |
3077 | } |
3078 | ||
3079 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
3080 | unsigned int evtinfo) | |
3081 | { | |
fae2b904 | 3082 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
3083 | unsigned int pwropt; |
3084 | ||
3085 | /* | |
3086 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
3087 | * Hibernation mode enabled which would show up when device detects | |
3088 | * host-initiated U3 exit. | |
3089 | * | |
3090 | * In that case, device will generate a Link State Change Interrupt | |
3091 | * from U3 to RESUME which is only necessary if Hibernation is | |
3092 | * configured in. | |
3093 | * | |
3094 | * There are no functional changes due to such spurious event and we | |
3095 | * just need to ignore it. | |
3096 | * | |
3097 | * Refers to: | |
3098 | * | |
3099 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
3100 | * operational mode | |
3101 | */ | |
3102 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
3103 | if ((dwc->revision < DWC3_REVISION_250A) && | |
3104 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { | |
3105 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
3106 | (next == DWC3_LINK_STATE_RESUME)) { | |
0b0cc1cd FB |
3107 | return; |
3108 | } | |
3109 | } | |
fae2b904 FB |
3110 | |
3111 | /* | |
3112 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
3113 | * on the link partner, the USB session might do multiple entry/exit | |
3114 | * of low power states before a transfer takes place. | |
3115 | * | |
3116 | * Due to this problem, we might experience lower throughput. The | |
3117 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
3118 | * transitioning from U1/U2 to U0 and enable those bits again | |
3119 | * after a transfer completes and there are no pending transfers | |
3120 | * on any of the enabled endpoints. | |
3121 | * | |
3122 | * This is the first half of that workaround. | |
3123 | * | |
3124 | * Refers to: | |
3125 | * | |
3126 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
3127 | * core send LGO_Ux entering U0 | |
3128 | */ | |
3129 | if (dwc->revision < DWC3_REVISION_183A) { | |
3130 | if (next == DWC3_LINK_STATE_U0) { | |
3131 | u32 u1u2; | |
3132 | u32 reg; | |
3133 | ||
3134 | switch (dwc->link_state) { | |
3135 | case DWC3_LINK_STATE_U1: | |
3136 | case DWC3_LINK_STATE_U2: | |
3137 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3138 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
3139 | | DWC3_DCTL_ACCEPTU2ENA | |
3140 | | DWC3_DCTL_INITU1ENA | |
3141 | | DWC3_DCTL_ACCEPTU1ENA); | |
3142 | ||
3143 | if (!dwc->u1u2) | |
3144 | dwc->u1u2 = reg & u1u2; | |
3145 | ||
3146 | reg &= ~u1u2; | |
3147 | ||
5b738211 | 3148 | dwc3_gadget_dctl_write_safe(dwc, reg); |
fae2b904 FB |
3149 | break; |
3150 | default: | |
3151 | /* do nothing */ | |
3152 | break; | |
3153 | } | |
3154 | } | |
3155 | } | |
3156 | ||
bc5ba2e0 FB |
3157 | switch (next) { |
3158 | case DWC3_LINK_STATE_U1: | |
3159 | if (dwc->speed == USB_SPEED_SUPER) | |
3160 | dwc3_suspend_gadget(dwc); | |
3161 | break; | |
3162 | case DWC3_LINK_STATE_U2: | |
3163 | case DWC3_LINK_STATE_U3: | |
3164 | dwc3_suspend_gadget(dwc); | |
3165 | break; | |
3166 | case DWC3_LINK_STATE_RESUME: | |
3167 | dwc3_resume_gadget(dwc); | |
3168 | break; | |
3169 | default: | |
3170 | /* do nothing */ | |
3171 | break; | |
3172 | } | |
3173 | ||
e57ebc1d | 3174 | dwc->link_state = next; |
72246da4 FB |
3175 | } |
3176 | ||
72704f87 BW |
3177 | static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc, |
3178 | unsigned int evtinfo) | |
3179 | { | |
3180 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; | |
3181 | ||
3182 | if (dwc->link_state != next && next == DWC3_LINK_STATE_U3) | |
3183 | dwc3_suspend_gadget(dwc); | |
3184 | ||
3185 | dwc->link_state = next; | |
3186 | } | |
3187 | ||
e1dadd3b FB |
3188 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, |
3189 | unsigned int evtinfo) | |
3190 | { | |
3191 | unsigned int is_ss = evtinfo & BIT(4); | |
3192 | ||
bfad65ee | 3193 | /* |
e1dadd3b FB |
3194 | * WORKAROUND: DWC3 revison 2.20a with hibernation support |
3195 | * have a known issue which can cause USB CV TD.9.23 to fail | |
3196 | * randomly. | |
3197 | * | |
3198 | * Because of this issue, core could generate bogus hibernation | |
3199 | * events which SW needs to ignore. | |
3200 | * | |
3201 | * Refers to: | |
3202 | * | |
3203 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
3204 | * Device Fallback from SuperSpeed | |
3205 | */ | |
3206 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
3207 | return; | |
3208 | ||
3209 | /* enter hibernation here */ | |
3210 | } | |
3211 | ||
72246da4 FB |
3212 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, |
3213 | const struct dwc3_event_devt *event) | |
3214 | { | |
3215 | switch (event->type) { | |
3216 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
3217 | dwc3_gadget_disconnect_interrupt(dwc); | |
3218 | break; | |
3219 | case DWC3_DEVICE_EVENT_RESET: | |
3220 | dwc3_gadget_reset_interrupt(dwc); | |
3221 | break; | |
3222 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
3223 | dwc3_gadget_conndone_interrupt(dwc); | |
3224 | break; | |
3225 | case DWC3_DEVICE_EVENT_WAKEUP: | |
3226 | dwc3_gadget_wakeup_interrupt(dwc); | |
3227 | break; | |
e1dadd3b FB |
3228 | case DWC3_DEVICE_EVENT_HIBER_REQ: |
3229 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
3230 | "unexpected hibernation event\n")) | |
3231 | break; | |
3232 | ||
3233 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
3234 | break; | |
72246da4 FB |
3235 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: |
3236 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
3237 | break; | |
3238 | case DWC3_DEVICE_EVENT_EOPF: | |
72704f87 | 3239 | /* It changed to be suspend event for version 2.30a and above */ |
5eb30ced | 3240 | if (dwc->revision >= DWC3_REVISION_230A) { |
72704f87 BW |
3241 | /* |
3242 | * Ignore suspend event until the gadget enters into | |
3243 | * USB_STATE_CONFIGURED state. | |
3244 | */ | |
3245 | if (dwc->gadget.state >= USB_STATE_CONFIGURED) | |
3246 | dwc3_gadget_suspend_interrupt(dwc, | |
3247 | event->event_info); | |
3248 | } | |
72246da4 FB |
3249 | break; |
3250 | case DWC3_DEVICE_EVENT_SOF: | |
72246da4 | 3251 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: |
72246da4 | 3252 | case DWC3_DEVICE_EVENT_CMD_CMPL: |
72246da4 | 3253 | case DWC3_DEVICE_EVENT_OVERFLOW: |
72246da4 FB |
3254 | break; |
3255 | default: | |
e9f2aa87 | 3256 | dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type); |
72246da4 FB |
3257 | } |
3258 | } | |
3259 | ||
3260 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
3261 | const union dwc3_event *event) | |
3262 | { | |
43c96be1 | 3263 | trace_dwc3_event(event->raw, dwc); |
2c4cbe6e | 3264 | |
dfc5e805 FB |
3265 | if (!event->type.is_devspec) |
3266 | dwc3_endpoint_interrupt(dwc, &event->depevt); | |
3267 | else if (event->type.type == DWC3_EVENT_TYPE_DEV) | |
72246da4 | 3268 | dwc3_gadget_interrupt(dwc, &event->devt); |
dfc5e805 | 3269 | else |
72246da4 | 3270 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); |
72246da4 FB |
3271 | } |
3272 | ||
dea520a4 | 3273 | static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt) |
b15a762f | 3274 | { |
dea520a4 | 3275 | struct dwc3 *dwc = evt->dwc; |
b15a762f | 3276 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 3277 | int left; |
e8adfc30 | 3278 | u32 reg; |
b15a762f | 3279 | |
f42f2447 | 3280 | left = evt->count; |
b15a762f | 3281 | |
f42f2447 FB |
3282 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
3283 | return IRQ_NONE; | |
b15a762f | 3284 | |
f42f2447 FB |
3285 | while (left > 0) { |
3286 | union dwc3_event event; | |
b15a762f | 3287 | |
ebbb2d59 | 3288 | event.raw = *(u32 *) (evt->cache + evt->lpos); |
b15a762f | 3289 | |
f42f2447 | 3290 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 3291 | |
f42f2447 FB |
3292 | /* |
3293 | * FIXME we wrap around correctly to the next entry as | |
3294 | * almost all entries are 4 bytes in size. There is one | |
3295 | * entry which has 12 bytes which is a regular entry | |
3296 | * followed by 8 bytes data. ATM I don't know how | |
3297 | * things are organized if we get next to the a | |
3298 | * boundary so I worry about that once we try to handle | |
3299 | * that. | |
3300 | */ | |
caefe6c7 | 3301 | evt->lpos = (evt->lpos + 4) % evt->length; |
f42f2447 | 3302 | left -= 4; |
f42f2447 | 3303 | } |
b15a762f | 3304 | |
f42f2447 FB |
3305 | evt->count = 0; |
3306 | evt->flags &= ~DWC3_EVENT_PENDING; | |
3307 | ret = IRQ_HANDLED; | |
b15a762f | 3308 | |
f42f2447 | 3309 | /* Unmask interrupt */ |
660e9bde | 3310 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
f42f2447 | 3311 | reg &= ~DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 3312 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
b15a762f | 3313 | |
cf40b86b JY |
3314 | if (dwc->imod_interval) { |
3315 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); | |
3316 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); | |
3317 | } | |
3318 | ||
f42f2447 FB |
3319 | return ret; |
3320 | } | |
e8adfc30 | 3321 | |
dea520a4 | 3322 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt) |
f42f2447 | 3323 | { |
dea520a4 FB |
3324 | struct dwc3_event_buffer *evt = _evt; |
3325 | struct dwc3 *dwc = evt->dwc; | |
e5f68b4a | 3326 | unsigned long flags; |
f42f2447 | 3327 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 3328 | |
e5f68b4a | 3329 | spin_lock_irqsave(&dwc->lock, flags); |
dea520a4 | 3330 | ret = dwc3_process_event_buf(evt); |
e5f68b4a | 3331 | spin_unlock_irqrestore(&dwc->lock, flags); |
b15a762f FB |
3332 | |
3333 | return ret; | |
3334 | } | |
3335 | ||
dea520a4 | 3336 | static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) |
72246da4 | 3337 | { |
dea520a4 | 3338 | struct dwc3 *dwc = evt->dwc; |
ebbb2d59 | 3339 | u32 amount; |
72246da4 | 3340 | u32 count; |
e8adfc30 | 3341 | u32 reg; |
72246da4 | 3342 | |
fc8bb91b FB |
3343 | if (pm_runtime_suspended(dwc->dev)) { |
3344 | pm_runtime_get(dwc->dev); | |
3345 | disable_irq_nosync(dwc->irq_gadget); | |
3346 | dwc->pending_events = true; | |
3347 | return IRQ_HANDLED; | |
3348 | } | |
3349 | ||
d325a1de TN |
3350 | /* |
3351 | * With PCIe legacy interrupt, test shows that top-half irq handler can | |
3352 | * be called again after HW interrupt deassertion. Check if bottom-half | |
3353 | * irq event handler completes before caching new event to prevent | |
3354 | * losing events. | |
3355 | */ | |
3356 | if (evt->flags & DWC3_EVENT_PENDING) | |
3357 | return IRQ_HANDLED; | |
3358 | ||
660e9bde | 3359 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); |
72246da4 FB |
3360 | count &= DWC3_GEVNTCOUNT_MASK; |
3361 | if (!count) | |
3362 | return IRQ_NONE; | |
3363 | ||
b15a762f FB |
3364 | evt->count = count; |
3365 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 3366 | |
e8adfc30 | 3367 | /* Mask interrupt */ |
660e9bde | 3368 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
e8adfc30 | 3369 | reg |= DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 3370 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
e8adfc30 | 3371 | |
ebbb2d59 JY |
3372 | amount = min(count, evt->length - evt->lpos); |
3373 | memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount); | |
3374 | ||
3375 | if (amount < count) | |
3376 | memcpy(evt->cache, evt->buf, count - amount); | |
3377 | ||
65aca320 JY |
3378 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count); |
3379 | ||
b15a762f | 3380 | return IRQ_WAKE_THREAD; |
72246da4 FB |
3381 | } |
3382 | ||
dea520a4 | 3383 | static irqreturn_t dwc3_interrupt(int irq, void *_evt) |
72246da4 | 3384 | { |
dea520a4 | 3385 | struct dwc3_event_buffer *evt = _evt; |
72246da4 | 3386 | |
dea520a4 | 3387 | return dwc3_check_event_buf(evt); |
72246da4 FB |
3388 | } |
3389 | ||
6db3812e FB |
3390 | static int dwc3_gadget_get_irq(struct dwc3 *dwc) |
3391 | { | |
3392 | struct platform_device *dwc3_pdev = to_platform_device(dwc->dev); | |
3393 | int irq; | |
3394 | ||
f146b40b | 3395 | irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral"); |
6db3812e FB |
3396 | if (irq > 0) |
3397 | goto out; | |
3398 | ||
3399 | if (irq == -EPROBE_DEFER) | |
3400 | goto out; | |
3401 | ||
f146b40b | 3402 | irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3"); |
6db3812e FB |
3403 | if (irq > 0) |
3404 | goto out; | |
3405 | ||
3406 | if (irq == -EPROBE_DEFER) | |
3407 | goto out; | |
3408 | ||
3409 | irq = platform_get_irq(dwc3_pdev, 0); | |
3410 | if (irq > 0) | |
3411 | goto out; | |
3412 | ||
6db3812e FB |
3413 | if (!irq) |
3414 | irq = -EINVAL; | |
3415 | ||
3416 | out: | |
3417 | return irq; | |
3418 | } | |
3419 | ||
72246da4 | 3420 | /** |
bfad65ee | 3421 | * dwc3_gadget_init - initializes gadget related registers |
1d046793 | 3422 | * @dwc: pointer to our controller context structure |
72246da4 FB |
3423 | * |
3424 | * Returns 0 on success otherwise negative errno. | |
3425 | */ | |
41ac7b3a | 3426 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 3427 | { |
6db3812e FB |
3428 | int ret; |
3429 | int irq; | |
9522def4 | 3430 | |
6db3812e FB |
3431 | irq = dwc3_gadget_get_irq(dwc); |
3432 | if (irq < 0) { | |
3433 | ret = irq; | |
3434 | goto err0; | |
9522def4 RQ |
3435 | } |
3436 | ||
3437 | dwc->irq_gadget = irq; | |
72246da4 | 3438 | |
d64ff406 AB |
3439 | dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev, |
3440 | sizeof(*dwc->ep0_trb) * 2, | |
3441 | &dwc->ep0_trb_addr, GFP_KERNEL); | |
72246da4 FB |
3442 | if (!dwc->ep0_trb) { |
3443 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
3444 | ret = -ENOMEM; | |
7d5e650a | 3445 | goto err0; |
72246da4 FB |
3446 | } |
3447 | ||
4199c5f8 | 3448 | dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL); |
72246da4 | 3449 | if (!dwc->setup_buf) { |
72246da4 | 3450 | ret = -ENOMEM; |
7d5e650a | 3451 | goto err1; |
72246da4 FB |
3452 | } |
3453 | ||
905dc04e FB |
3454 | dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, |
3455 | &dwc->bounce_addr, GFP_KERNEL); | |
3456 | if (!dwc->bounce) { | |
3457 | ret = -ENOMEM; | |
d6e5a549 | 3458 | goto err2; |
905dc04e FB |
3459 | } |
3460 | ||
bb014736 BW |
3461 | init_completion(&dwc->ep0_in_setup); |
3462 | ||
72246da4 | 3463 | dwc->gadget.ops = &dwc3_gadget_ops; |
72246da4 | 3464 | dwc->gadget.speed = USB_SPEED_UNKNOWN; |
eeb720fb | 3465 | dwc->gadget.sg_supported = true; |
72246da4 | 3466 | dwc->gadget.name = "dwc3-gadget"; |
c729969b | 3467 | dwc->gadget.lpm_capable = true; |
72246da4 | 3468 | |
b9e51b2b BM |
3469 | /* |
3470 | * FIXME We might be setting max_speed to <SUPER, however versions | |
3471 | * <2.20a of dwc3 have an issue with metastability (documented | |
3472 | * elsewhere in this driver) which tells us we can't set max speed to | |
3473 | * anything lower than SUPER. | |
3474 | * | |
3475 | * Because gadget.max_speed is only used by composite.c and function | |
3476 | * drivers (i.e. it won't go into dwc3's registers) we are allowing this | |
3477 | * to happen so we avoid sending SuperSpeed Capability descriptor | |
3478 | * together with our BOS descriptor as that could confuse host into | |
3479 | * thinking we can handle super speed. | |
3480 | * | |
3481 | * Note that, in fact, we won't even support GetBOS requests when speed | |
3482 | * is less than super speed because we don't have means, yet, to tell | |
3483 | * composite.c that we are USB 2.0 + LPM ECN. | |
3484 | */ | |
42bf02ec RQ |
3485 | if (dwc->revision < DWC3_REVISION_220A && |
3486 | !dwc->dis_metastability_quirk) | |
5eb30ced | 3487 | dev_info(dwc->dev, "changing max_speed on rev %08x\n", |
b9e51b2b BM |
3488 | dwc->revision); |
3489 | ||
3490 | dwc->gadget.max_speed = dwc->maximum_speed; | |
3491 | ||
72246da4 FB |
3492 | /* |
3493 | * REVISIT: Here we should clear all pending IRQs to be | |
3494 | * sure we're starting from a well known location. | |
3495 | */ | |
3496 | ||
f3bcfc7e | 3497 | ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps); |
72246da4 | 3498 | if (ret) |
d6e5a549 | 3499 | goto err3; |
72246da4 | 3500 | |
72246da4 FB |
3501 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); |
3502 | if (ret) { | |
3503 | dev_err(dwc->dev, "failed to register udc\n"); | |
d6e5a549 | 3504 | goto err4; |
72246da4 FB |
3505 | } |
3506 | ||
169e3b68 RQ |
3507 | dwc3_gadget_set_speed(&dwc->gadget, dwc->maximum_speed); |
3508 | ||
72246da4 FB |
3509 | return 0; |
3510 | ||
7d5e650a | 3511 | err4: |
d6e5a549 | 3512 | dwc3_gadget_free_endpoints(dwc); |
04c03d10 | 3513 | |
7d5e650a | 3514 | err3: |
d6e5a549 FB |
3515 | dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce, |
3516 | dwc->bounce_addr); | |
5812b1c2 | 3517 | |
7d5e650a | 3518 | err2: |
0fc9a1be | 3519 | kfree(dwc->setup_buf); |
72246da4 | 3520 | |
7d5e650a | 3521 | err1: |
d64ff406 | 3522 | dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
3523 | dwc->ep0_trb, dwc->ep0_trb_addr); |
3524 | ||
72246da4 FB |
3525 | err0: |
3526 | return ret; | |
3527 | } | |
3528 | ||
7415f17c FB |
3529 | /* -------------------------------------------------------------------------- */ |
3530 | ||
72246da4 FB |
3531 | void dwc3_gadget_exit(struct dwc3 *dwc) |
3532 | { | |
72246da4 | 3533 | usb_del_gadget_udc(&dwc->gadget); |
72246da4 | 3534 | dwc3_gadget_free_endpoints(dwc); |
905dc04e | 3535 | dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce, |
d6e5a549 | 3536 | dwc->bounce_addr); |
0fc9a1be | 3537 | kfree(dwc->setup_buf); |
d64ff406 | 3538 | dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, |
d6e5a549 | 3539 | dwc->ep0_trb, dwc->ep0_trb_addr); |
72246da4 | 3540 | } |
7415f17c | 3541 | |
0b0231aa | 3542 | int dwc3_gadget_suspend(struct dwc3 *dwc) |
7415f17c | 3543 | { |
9772b47a RQ |
3544 | if (!dwc->gadget_driver) |
3545 | return 0; | |
3546 | ||
1551e35e | 3547 | dwc3_gadget_run_stop(dwc, false, false); |
9f8a67b6 FB |
3548 | dwc3_disconnect_gadget(dwc); |
3549 | __dwc3_gadget_stop(dwc); | |
7415f17c FB |
3550 | |
3551 | return 0; | |
3552 | } | |
3553 | ||
3554 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
3555 | { | |
7415f17c FB |
3556 | int ret; |
3557 | ||
9772b47a RQ |
3558 | if (!dwc->gadget_driver) |
3559 | return 0; | |
3560 | ||
9f8a67b6 FB |
3561 | ret = __dwc3_gadget_start(dwc); |
3562 | if (ret < 0) | |
7415f17c FB |
3563 | goto err0; |
3564 | ||
9f8a67b6 FB |
3565 | ret = dwc3_gadget_run_stop(dwc, true, false); |
3566 | if (ret < 0) | |
7415f17c FB |
3567 | goto err1; |
3568 | ||
7415f17c FB |
3569 | return 0; |
3570 | ||
3571 | err1: | |
9f8a67b6 | 3572 | __dwc3_gadget_stop(dwc); |
7415f17c FB |
3573 | |
3574 | err0: | |
3575 | return ret; | |
3576 | } | |
fc8bb91b FB |
3577 | |
3578 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc) | |
3579 | { | |
3580 | if (dwc->pending_events) { | |
3581 | dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf); | |
3582 | dwc->pending_events = false; | |
3583 | enable_irq(dwc->irq_gadget); | |
3584 | } | |
3585 | } |