Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
bfad65ee | 2 | /* |
72246da4 FB |
3 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link |
4 | * | |
10623b87 | 5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com |
72246da4 FB |
6 | * |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
72246da4 FB |
9 | */ |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/pm_runtime.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | ||
22 | #include <linux/usb/ch9.h> | |
23 | #include <linux/usb/gadget.h> | |
24 | ||
80977dc9 | 25 | #include "debug.h" |
72246da4 FB |
26 | #include "core.h" |
27 | #include "gadget.h" | |
28 | #include "io.h" | |
29 | ||
d5370106 | 30 | #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \ |
f62afb49 FB |
31 | & ~((d)->interval - 1)) |
32 | ||
04a9bfcd | 33 | /** |
bfad65ee | 34 | * dwc3_gadget_set_test_mode - enables usb2 test modes |
04a9bfcd FB |
35 | * @dwc: pointer to our context structure |
36 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
37 | * | |
bfad65ee FB |
38 | * Caller should take care of locking. This function will return 0 on |
39 | * success or -EINVAL if wrong Test Selector is passed. | |
04a9bfcd FB |
40 | */ |
41 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
42 | { | |
43 | u32 reg; | |
44 | ||
45 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
46 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
47 | ||
48 | switch (mode) { | |
62fb45d3 GKH |
49 | case USB_TEST_J: |
50 | case USB_TEST_K: | |
51 | case USB_TEST_SE0_NAK: | |
52 | case USB_TEST_PACKET: | |
53 | case USB_TEST_FORCE_ENABLE: | |
04a9bfcd FB |
54 | reg |= mode << 1; |
55 | break; | |
56 | default: | |
57 | return -EINVAL; | |
58 | } | |
59 | ||
5b738211 | 60 | dwc3_gadget_dctl_write_safe(dwc, reg); |
04a9bfcd FB |
61 | |
62 | return 0; | |
63 | } | |
64 | ||
911f1f88 | 65 | /** |
bfad65ee | 66 | * dwc3_gadget_get_link_state - gets current state of usb link |
911f1f88 PZ |
67 | * @dwc: pointer to our context structure |
68 | * | |
69 | * Caller should take care of locking. This function will | |
70 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
71 | */ | |
72 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
73 | { | |
74 | u32 reg; | |
75 | ||
76 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
77 | ||
78 | return DWC3_DSTS_USBLNKST(reg); | |
79 | } | |
80 | ||
8598bde7 | 81 | /** |
bfad65ee | 82 | * dwc3_gadget_set_link_state - sets usb link to a particular state |
8598bde7 FB |
83 | * @dwc: pointer to our context structure |
84 | * @state: the state to put link into | |
85 | * | |
86 | * Caller should take care of locking. This function will | |
aee63e3c | 87 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
88 | */ |
89 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
90 | { | |
aee63e3c | 91 | int retries = 10000; |
8598bde7 FB |
92 | u32 reg; |
93 | ||
802fde98 PZ |
94 | /* |
95 | * Wait until device controller is ready. Only applies to 1.94a and | |
96 | * later RTL. | |
97 | */ | |
9af21dd6 | 98 | if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) { |
802fde98 PZ |
99 | while (--retries) { |
100 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
101 | if (reg & DWC3_DSTS_DCNRD) | |
102 | udelay(5); | |
103 | else | |
104 | break; | |
105 | } | |
106 | ||
107 | if (retries <= 0) | |
108 | return -ETIMEDOUT; | |
109 | } | |
110 | ||
8598bde7 FB |
111 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
112 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
113 | ||
2e708fa3 TN |
114 | /* set no action before sending new link state change */ |
115 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
116 | ||
8598bde7 FB |
117 | /* set requested state */ |
118 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
119 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
120 | ||
802fde98 PZ |
121 | /* |
122 | * The following code is racy when called from dwc3_gadget_wakeup, | |
123 | * and is not needed, at least on newer versions | |
124 | */ | |
9af21dd6 | 125 | if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) |
802fde98 PZ |
126 | return 0; |
127 | ||
8598bde7 | 128 | /* wait for a change in DSTS */ |
aed430e5 | 129 | retries = 10000; |
8598bde7 FB |
130 | while (--retries) { |
131 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
132 | ||
8598bde7 FB |
133 | if (DWC3_DSTS_USBLNKST(reg) == state) |
134 | return 0; | |
135 | ||
aee63e3c | 136 | udelay(5); |
8598bde7 FB |
137 | } |
138 | ||
8598bde7 FB |
139 | return -ETIMEDOUT; |
140 | } | |
141 | ||
dca0119c | 142 | /** |
bfad65ee FB |
143 | * dwc3_ep_inc_trb - increment a trb index. |
144 | * @index: Pointer to the TRB index to increment. | |
dca0119c JY |
145 | * |
146 | * The index should never point to the link TRB. After incrementing, | |
147 | * if it is point to the link TRB, wrap around to the beginning. The | |
148 | * link TRB is always at the last TRB entry. | |
149 | */ | |
150 | static void dwc3_ep_inc_trb(u8 *index) | |
457e84b6 | 151 | { |
dca0119c JY |
152 | (*index)++; |
153 | if (*index == (DWC3_TRB_NUM - 1)) | |
154 | *index = 0; | |
ef966b9d | 155 | } |
457e84b6 | 156 | |
bfad65ee FB |
157 | /** |
158 | * dwc3_ep_inc_enq - increment endpoint's enqueue pointer | |
159 | * @dep: The endpoint whose enqueue pointer we're incrementing | |
160 | */ | |
dca0119c | 161 | static void dwc3_ep_inc_enq(struct dwc3_ep *dep) |
ef966b9d | 162 | { |
dca0119c | 163 | dwc3_ep_inc_trb(&dep->trb_enqueue); |
ef966b9d | 164 | } |
457e84b6 | 165 | |
bfad65ee FB |
166 | /** |
167 | * dwc3_ep_inc_deq - increment endpoint's dequeue pointer | |
168 | * @dep: The endpoint whose enqueue pointer we're incrementing | |
169 | */ | |
dca0119c | 170 | static void dwc3_ep_inc_deq(struct dwc3_ep *dep) |
ef966b9d | 171 | { |
dca0119c | 172 | dwc3_ep_inc_trb(&dep->trb_dequeue); |
457e84b6 FB |
173 | } |
174 | ||
69102510 | 175 | static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep, |
c91815b5 | 176 | struct dwc3_request *req, int status) |
72246da4 FB |
177 | { |
178 | struct dwc3 *dwc = dep->dwc; | |
179 | ||
72246da4 | 180 | list_del(&req->list); |
e62c5bc5 | 181 | req->remaining = 0; |
bd674224 | 182 | req->needs_extra_trb = false; |
72246da4 FB |
183 | |
184 | if (req->request.status == -EINPROGRESS) | |
185 | req->request.status = status; | |
186 | ||
4a71fcb8 JP |
187 | if (req->trb) |
188 | usb_gadget_unmap_request_by_dev(dwc->sysdev, | |
c91815b5 | 189 | &req->request, req->direction); |
4a71fcb8 JP |
190 | |
191 | req->trb = NULL; | |
2c4cbe6e | 192 | trace_dwc3_gadget_giveback(req); |
72246da4 | 193 | |
c91815b5 FB |
194 | if (dep->number > 1) |
195 | pm_runtime_put(dwc->dev); | |
196 | } | |
197 | ||
198 | /** | |
199 | * dwc3_gadget_giveback - call struct usb_request's ->complete callback | |
200 | * @dep: The endpoint to whom the request belongs to | |
201 | * @req: The request we're giving back | |
202 | * @status: completion code for the request | |
203 | * | |
204 | * Must be called with controller's lock held and interrupts disabled. This | |
205 | * function will unmap @req and call its ->complete() callback to notify upper | |
206 | * layers that it has completed. | |
207 | */ | |
208 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, | |
209 | int status) | |
210 | { | |
211 | struct dwc3 *dwc = dep->dwc; | |
212 | ||
213 | dwc3_gadget_del_and_unmap_request(dep, req, status); | |
a3af5e3a | 214 | req->status = DWC3_REQUEST_STATUS_COMPLETED; |
c91815b5 | 215 | |
72246da4 | 216 | spin_unlock(&dwc->lock); |
304f7e5e | 217 | usb_gadget_giveback_request(&dep->endpoint, &req->request); |
72246da4 FB |
218 | spin_lock(&dwc->lock); |
219 | } | |
220 | ||
bfad65ee FB |
221 | /** |
222 | * dwc3_send_gadget_generic_command - issue a generic command for the controller | |
223 | * @dwc: pointer to the controller context | |
224 | * @cmd: the command to be issued | |
225 | * @param: command parameter | |
226 | * | |
227 | * Caller should take care of locking. Issue @cmd with a given @param to @dwc | |
228 | * and wait for its completion. | |
229 | */ | |
e319bd62 FB |
230 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, |
231 | u32 param) | |
b09bb642 FB |
232 | { |
233 | u32 timeout = 500; | |
71f7e702 | 234 | int status = 0; |
0fe886cd | 235 | int ret = 0; |
b09bb642 FB |
236 | u32 reg; |
237 | ||
238 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); | |
239 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
240 | ||
241 | do { | |
242 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
243 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
71f7e702 FB |
244 | status = DWC3_DGCMD_STATUS(reg); |
245 | if (status) | |
0fe886cd FB |
246 | ret = -EINVAL; |
247 | break; | |
b09bb642 | 248 | } |
e3aee486 | 249 | } while (--timeout); |
0fe886cd FB |
250 | |
251 | if (!timeout) { | |
0fe886cd | 252 | ret = -ETIMEDOUT; |
71f7e702 | 253 | status = -ETIMEDOUT; |
0fe886cd FB |
254 | } |
255 | ||
71f7e702 FB |
256 | trace_dwc3_gadget_generic_cmd(cmd, param, status); |
257 | ||
0fe886cd | 258 | return ret; |
b09bb642 FB |
259 | } |
260 | ||
c36d8e94 FB |
261 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc); |
262 | ||
bfad65ee FB |
263 | /** |
264 | * dwc3_send_gadget_ep_cmd - issue an endpoint command | |
265 | * @dep: the endpoint to which the command is going to be issued | |
266 | * @cmd: the command to be issued | |
267 | * @params: parameters to the command | |
268 | * | |
269 | * Caller should handle locking. This function will issue @cmd with given | |
270 | * @params to @dep and wait for its completion. | |
271 | */ | |
e319bd62 | 272 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, |
2cd4718d | 273 | struct dwc3_gadget_ep_cmd_params *params) |
72246da4 | 274 | { |
8897a761 | 275 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
2cd4718d | 276 | struct dwc3 *dwc = dep->dwc; |
1c0e69ae | 277 | u32 timeout = 5000; |
87dd9611 | 278 | u32 saved_config = 0; |
72246da4 FB |
279 | u32 reg; |
280 | ||
0933df15 | 281 | int cmd_status = 0; |
c0ca324d | 282 | int ret = -EINVAL; |
72246da4 | 283 | |
2b0f11df | 284 | /* |
87dd9611 TN |
285 | * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or |
286 | * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an | |
287 | * endpoint command. | |
2b0f11df | 288 | * |
87dd9611 TN |
289 | * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY |
290 | * settings. Restore them after the command is completed. | |
291 | * | |
292 | * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2 | |
2b0f11df | 293 | */ |
e81a7018 | 294 | if (dwc->gadget->speed <= USB_SPEED_HIGH) { |
ab2a92e7 FB |
295 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
296 | if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) { | |
87dd9611 | 297 | saved_config |= DWC3_GUSB2PHYCFG_SUSPHY; |
ab2a92e7 | 298 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; |
ab2a92e7 | 299 | } |
87dd9611 TN |
300 | |
301 | if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) { | |
302 | saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM; | |
303 | reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; | |
304 | } | |
305 | ||
306 | if (saved_config) | |
307 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
2b0f11df FB |
308 | } |
309 | ||
5999914f | 310 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { |
c560e763 | 311 | int link_state; |
c36d8e94 | 312 | |
c560e763 TN |
313 | link_state = dwc3_gadget_get_link_state(dwc); |
314 | if (link_state == DWC3_LINK_STATE_U1 || | |
315 | link_state == DWC3_LINK_STATE_U2 || | |
316 | link_state == DWC3_LINK_STATE_U3) { | |
c36d8e94 FB |
317 | ret = __dwc3_gadget_wakeup(dwc); |
318 | dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n", | |
319 | ret); | |
320 | } | |
321 | } | |
322 | ||
2eb88016 FB |
323 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0); |
324 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1); | |
325 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2); | |
72246da4 | 326 | |
8897a761 FB |
327 | /* |
328 | * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're | |
329 | * not relying on XferNotReady, we can make use of a special "No | |
330 | * Response Update Transfer" command where we should clear both CmdAct | |
331 | * and CmdIOC bits. | |
332 | * | |
333 | * With this, we don't need to wait for command completion and can | |
334 | * straight away issue further commands to the endpoint. | |
335 | * | |
336 | * NOTICE: We're making an assumption that control endpoints will never | |
337 | * make use of Update Transfer command. This is a safe assumption | |
338 | * because we can never have more than one request at a time with | |
339 | * Control Endpoints. If anybody changes that assumption, this chunk | |
340 | * needs to be updated accordingly. | |
341 | */ | |
342 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER && | |
343 | !usb_endpoint_xfer_isoc(desc)) | |
344 | cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT); | |
345 | else | |
346 | cmd |= DWC3_DEPCMD_CMDACT; | |
347 | ||
348 | dwc3_writel(dep->regs, DWC3_DEPCMD, cmd); | |
72246da4 | 349 | do { |
2eb88016 | 350 | reg = dwc3_readl(dep->regs, DWC3_DEPCMD); |
72246da4 | 351 | if (!(reg & DWC3_DEPCMD_CMDACT)) { |
0933df15 | 352 | cmd_status = DWC3_DEPCMD_STATUS(reg); |
7b9cc7a2 | 353 | |
7b9cc7a2 KL |
354 | switch (cmd_status) { |
355 | case 0: | |
356 | ret = 0; | |
357 | break; | |
358 | case DEPEVT_TRANSFER_NO_RESOURCE: | |
f7ac582e TN |
359 | dev_WARN(dwc->dev, "No resource for %s\n", |
360 | dep->name); | |
7b9cc7a2 | 361 | ret = -EINVAL; |
c0ca324d | 362 | break; |
7b9cc7a2 KL |
363 | case DEPEVT_TRANSFER_BUS_EXPIRY: |
364 | /* | |
365 | * SW issues START TRANSFER command to | |
366 | * isochronous ep with future frame interval. If | |
367 | * future interval time has already passed when | |
368 | * core receives the command, it will respond | |
369 | * with an error status of 'Bus Expiry'. | |
370 | * | |
371 | * Instead of always returning -EINVAL, let's | |
372 | * give a hint to the gadget driver that this is | |
373 | * the case by returning -EAGAIN. | |
374 | */ | |
7b9cc7a2 KL |
375 | ret = -EAGAIN; |
376 | break; | |
377 | default: | |
378 | dev_WARN(dwc->dev, "UNKNOWN cmd status\n"); | |
379 | } | |
380 | ||
c0ca324d | 381 | break; |
72246da4 | 382 | } |
f6bb225b | 383 | } while (--timeout); |
72246da4 | 384 | |
f6bb225b | 385 | if (timeout == 0) { |
f6bb225b | 386 | ret = -ETIMEDOUT; |
0933df15 | 387 | cmd_status = -ETIMEDOUT; |
f6bb225b | 388 | } |
c0ca324d | 389 | |
0933df15 FB |
390 | trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status); |
391 | ||
9bc3395c TN |
392 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { |
393 | if (ret == 0) | |
394 | dep->flags |= DWC3_EP_TRANSFER_STARTED; | |
395 | ||
396 | if (ret != -ETIMEDOUT) | |
397 | dwc3_gadget_ep_get_transfer_index(dep); | |
6cb2e4e3 FB |
398 | } |
399 | ||
87dd9611 | 400 | if (saved_config) { |
2b0f11df | 401 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
87dd9611 | 402 | reg |= saved_config; |
2b0f11df FB |
403 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
404 | } | |
405 | ||
c0ca324d | 406 | return ret; |
72246da4 FB |
407 | } |
408 | ||
50c763f8 JY |
409 | static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep) |
410 | { | |
411 | struct dwc3 *dwc = dep->dwc; | |
412 | struct dwc3_gadget_ep_cmd_params params; | |
413 | u32 cmd = DWC3_DEPCMD_CLEARSTALL; | |
414 | ||
415 | /* | |
416 | * As of core revision 2.60a the recommended programming model | |
417 | * is to set the ClearPendIN bit when issuing a Clear Stall EP | |
418 | * command for IN endpoints. This is to prevent an issue where | |
419 | * some (non-compliant) hosts may not send ACK TPs for pending | |
420 | * IN transfers due to a mishandled error condition. Synopsys | |
421 | * STAR 9000614252. | |
422 | */ | |
9af21dd6 TN |
423 | if (dep->direction && |
424 | !DWC3_VER_IS_PRIOR(DWC3, 260A) && | |
e81a7018 | 425 | (dwc->gadget->speed >= USB_SPEED_SUPER)) |
50c763f8 JY |
426 | cmd |= DWC3_DEPCMD_CLEARPENDIN; |
427 | ||
428 | memset(¶ms, 0, sizeof(params)); | |
429 | ||
2cd4718d | 430 | return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
50c763f8 JY |
431 | } |
432 | ||
72246da4 | 433 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, |
f6bafc6a | 434 | struct dwc3_trb *trb) |
72246da4 | 435 | { |
c439ef87 | 436 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
437 | |
438 | return dep->trb_pool_dma + offset; | |
439 | } | |
440 | ||
441 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
442 | { | |
443 | struct dwc3 *dwc = dep->dwc; | |
444 | ||
445 | if (dep->trb_pool) | |
446 | return 0; | |
447 | ||
d64ff406 | 448 | dep->trb_pool = dma_alloc_coherent(dwc->sysdev, |
72246da4 FB |
449 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, |
450 | &dep->trb_pool_dma, GFP_KERNEL); | |
451 | if (!dep->trb_pool) { | |
452 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
453 | dep->name); | |
454 | return -ENOMEM; | |
455 | } | |
456 | ||
457 | return 0; | |
458 | } | |
459 | ||
460 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
461 | { | |
462 | struct dwc3 *dwc = dep->dwc; | |
463 | ||
d64ff406 | 464 | dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, |
72246da4 FB |
465 | dep->trb_pool, dep->trb_pool_dma); |
466 | ||
467 | dep->trb_pool = NULL; | |
468 | dep->trb_pool_dma = 0; | |
469 | } | |
470 | ||
20d1d43f FB |
471 | static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep) |
472 | { | |
473 | struct dwc3_gadget_ep_cmd_params params; | |
474 | ||
475 | memset(¶ms, 0x00, sizeof(params)); | |
476 | ||
477 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); | |
478 | ||
479 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE, | |
480 | ¶ms); | |
481 | } | |
c4509601 JY |
482 | |
483 | /** | |
bfad65ee | 484 | * dwc3_gadget_start_config - configure ep resources |
c4509601 JY |
485 | * @dep: endpoint that is being enabled |
486 | * | |
bfad65ee FB |
487 | * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's |
488 | * completion, it will set Transfer Resource for all available endpoints. | |
c4509601 | 489 | * |
bfad65ee FB |
490 | * The assignment of transfer resources cannot perfectly follow the data book |
491 | * due to the fact that the controller driver does not have all knowledge of the | |
492 | * configuration in advance. It is given this information piecemeal by the | |
493 | * composite gadget framework after every SET_CONFIGURATION and | |
494 | * SET_INTERFACE. Trying to follow the databook programming model in this | |
495 | * scenario can cause errors. For two reasons: | |
c4509601 | 496 | * |
bfad65ee FB |
497 | * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every |
498 | * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is | |
499 | * incorrect in the scenario of multiple interfaces. | |
500 | * | |
501 | * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new | |
c4509601 JY |
502 | * endpoint on alt setting (8.1.6). |
503 | * | |
504 | * The following simplified method is used instead: | |
505 | * | |
bfad65ee FB |
506 | * All hardware endpoints can be assigned a transfer resource and this setting |
507 | * will stay persistent until either a core reset or hibernation. So whenever we | |
508 | * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do | |
509 | * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are | |
c4509601 JY |
510 | * guaranteed that there are as many transfer resources as endpoints. |
511 | * | |
bfad65ee FB |
512 | * This function is called for each endpoint when it is being enabled but is |
513 | * triggered only when called for EP0-out, which always happens first, and which | |
514 | * should only happen in one of the above conditions. | |
c4509601 | 515 | */ |
b07c2db8 | 516 | static int dwc3_gadget_start_config(struct dwc3_ep *dep) |
72246da4 FB |
517 | { |
518 | struct dwc3_gadget_ep_cmd_params params; | |
b07c2db8 | 519 | struct dwc3 *dwc; |
72246da4 | 520 | u32 cmd; |
c4509601 JY |
521 | int i; |
522 | int ret; | |
523 | ||
524 | if (dep->number) | |
525 | return 0; | |
72246da4 FB |
526 | |
527 | memset(¶ms, 0x00, sizeof(params)); | |
c4509601 | 528 | cmd = DWC3_DEPCMD_DEPSTARTCFG; |
b07c2db8 | 529 | dwc = dep->dwc; |
72246da4 | 530 | |
2cd4718d | 531 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
c4509601 JY |
532 | if (ret) |
533 | return ret; | |
534 | ||
535 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
536 | struct dwc3_ep *dep = dwc->eps[i]; | |
72246da4 | 537 | |
c4509601 JY |
538 | if (!dep) |
539 | continue; | |
540 | ||
b07c2db8 | 541 | ret = dwc3_gadget_set_xfer_resource(dep); |
c4509601 JY |
542 | if (ret) |
543 | return ret; | |
72246da4 FB |
544 | } |
545 | ||
546 | return 0; | |
547 | } | |
548 | ||
b07c2db8 | 549 | static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action) |
72246da4 | 550 | { |
39ebb05c JY |
551 | const struct usb_ss_ep_comp_descriptor *comp_desc; |
552 | const struct usb_endpoint_descriptor *desc; | |
72246da4 | 553 | struct dwc3_gadget_ep_cmd_params params; |
b07c2db8 | 554 | struct dwc3 *dwc = dep->dwc; |
72246da4 | 555 | |
39ebb05c JY |
556 | comp_desc = dep->endpoint.comp_desc; |
557 | desc = dep->endpoint.desc; | |
558 | ||
72246da4 FB |
559 | memset(¶ms, 0x00, sizeof(params)); |
560 | ||
dc1c70a7 | 561 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
562 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
563 | ||
564 | /* Burst size is only needed in SuperSpeed mode */ | |
e81a7018 | 565 | if (dwc->gadget->speed >= USB_SPEED_SUPER) { |
676e3497 | 566 | u32 burst = dep->endpoint.maxburst; |
e319bd62 | 567 | |
676e3497 | 568 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1); |
d2e9a13a | 569 | } |
72246da4 | 570 | |
a2d23f08 FB |
571 | params.param0 |= action; |
572 | if (action == DWC3_DEPCFG_ACTION_RESTORE) | |
265b70a7 | 573 | params.param2 |= dep->saved_state; |
265b70a7 | 574 | |
4bc48c97 FB |
575 | if (usb_endpoint_xfer_control(desc)) |
576 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN; | |
13fa2e69 FB |
577 | |
578 | if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc)) | |
579 | params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 580 | |
18b7ede5 | 581 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 | 582 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
548f8b31 | 583 | | DWC3_DEPCFG_XFER_COMPLETE_EN |
dc1c70a7 | 584 | | DWC3_DEPCFG_STREAM_EVENT_EN; |
879631aa FB |
585 | dep->stream_capable = true; |
586 | } | |
587 | ||
0b93a4c8 | 588 | if (!usb_endpoint_xfer_control(desc)) |
dc1c70a7 | 589 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
590 | |
591 | /* | |
592 | * We are doing 1:1 mapping for endpoints, meaning | |
593 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
594 | * so on. We consider the direction bit as part of the physical | |
595 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
596 | */ | |
dc1c70a7 | 597 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
598 | |
599 | /* | |
600 | * We must use the lower 16 TX FIFOs even though | |
601 | * HW might have more | |
602 | */ | |
603 | if (dep->direction) | |
dc1c70a7 | 604 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
605 | |
606 | if (desc->bInterval) { | |
a1679af8 TN |
607 | u8 bInterval_m1; |
608 | ||
609 | /* | |
610 | * Valid range for DEPCFG.bInterval_m1 is from 0 to 13, and it | |
611 | * must be set to 0 when the controller operates in full-speed. | |
612 | */ | |
613 | bInterval_m1 = min_t(u8, desc->bInterval - 1, 13); | |
614 | if (dwc->gadget->speed == USB_SPEED_FULL) | |
615 | bInterval_m1 = 0; | |
616 | ||
4b049f55 TN |
617 | if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT && |
618 | dwc->gadget->speed == USB_SPEED_FULL) | |
619 | dep->interval = desc->bInterval; | |
620 | else | |
621 | dep->interval = 1 << (desc->bInterval - 1); | |
622 | ||
a1679af8 | 623 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1); |
72246da4 FB |
624 | } |
625 | ||
2cd4718d | 626 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms); |
72246da4 FB |
627 | } |
628 | ||
140ca4cf TN |
629 | static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, |
630 | bool interrupt); | |
631 | ||
72246da4 | 632 | /** |
bfad65ee | 633 | * __dwc3_gadget_ep_enable - initializes a hw endpoint |
72246da4 | 634 | * @dep: endpoint to be initialized |
a2d23f08 | 635 | * @action: one of INIT, MODIFY or RESTORE |
72246da4 | 636 | * |
bfad65ee FB |
637 | * Caller should take care of locking. Execute all necessary commands to |
638 | * initialize a HW endpoint so it can be used by a gadget driver. | |
72246da4 | 639 | */ |
a2d23f08 | 640 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) |
72246da4 | 641 | { |
39ebb05c | 642 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
72246da4 | 643 | struct dwc3 *dwc = dep->dwc; |
39ebb05c | 644 | |
72246da4 | 645 | u32 reg; |
b09e99ee | 646 | int ret; |
72246da4 FB |
647 | |
648 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
b07c2db8 | 649 | ret = dwc3_gadget_start_config(dep); |
72246da4 FB |
650 | if (ret) |
651 | return ret; | |
652 | } | |
653 | ||
b07c2db8 | 654 | ret = dwc3_gadget_set_ep_config(dep, action); |
72246da4 FB |
655 | if (ret) |
656 | return ret; | |
657 | ||
658 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
659 | struct dwc3_trb *trb_st_hw; |
660 | struct dwc3_trb *trb_link; | |
72246da4 | 661 | |
72246da4 FB |
662 | dep->type = usb_endpoint_type(desc); |
663 | dep->flags |= DWC3_EP_ENABLED; | |
664 | ||
665 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
666 | reg |= DWC3_DALEPENA_EP(dep->number); | |
667 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
668 | ||
36b68aae | 669 | if (usb_endpoint_xfer_control(desc)) |
2870e501 | 670 | goto out; |
72246da4 | 671 | |
0d25744a JY |
672 | /* Initialize the TRB ring */ |
673 | dep->trb_dequeue = 0; | |
674 | dep->trb_enqueue = 0; | |
675 | memset(dep->trb_pool, 0, | |
676 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM); | |
677 | ||
36b68aae | 678 | /* Link TRB. The HWO bit is never reset */ |
72246da4 FB |
679 | trb_st_hw = &dep->trb_pool[0]; |
680 | ||
f6bafc6a | 681 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
f6bafc6a FB |
682 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
683 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
684 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
685 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
686 | } |
687 | ||
a97ea994 FB |
688 | /* |
689 | * Issue StartTransfer here with no-op TRB so we can always rely on No | |
690 | * Response Update Transfer command. | |
691 | */ | |
140ca4cf | 692 | if (usb_endpoint_xfer_bulk(desc) || |
52fcc0be | 693 | usb_endpoint_xfer_int(desc)) { |
a97ea994 FB |
694 | struct dwc3_gadget_ep_cmd_params params; |
695 | struct dwc3_trb *trb; | |
696 | dma_addr_t trb_dma; | |
697 | u32 cmd; | |
698 | ||
699 | memset(¶ms, 0, sizeof(params)); | |
700 | trb = &dep->trb_pool[0]; | |
701 | trb_dma = dwc3_trb_dma_offset(dep, trb); | |
702 | ||
703 | params.param0 = upper_32_bits(trb_dma); | |
704 | params.param1 = lower_32_bits(trb_dma); | |
705 | ||
706 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
707 | ||
708 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
709 | if (ret < 0) | |
710 | return ret; | |
140ca4cf TN |
711 | |
712 | if (dep->stream_capable) { | |
713 | /* | |
714 | * For streams, at start, there maybe a race where the | |
715 | * host primes the endpoint before the function driver | |
716 | * queues a request to initiate a stream. In that case, | |
717 | * the controller will not see the prime to generate the | |
718 | * ERDY and start stream. To workaround this, issue a | |
719 | * no-op TRB as normal, but end it immediately. As a | |
720 | * result, when the function driver queues the request, | |
721 | * the next START_TRANSFER command will cause the | |
722 | * controller to generate an ERDY to initiate the | |
723 | * stream. | |
724 | */ | |
725 | dwc3_stop_active_transfer(dep, true, true); | |
726 | ||
727 | /* | |
728 | * All stream eps will reinitiate stream on NoStream | |
729 | * rejection until we can determine that the host can | |
730 | * prime after the first transfer. | |
731 | */ | |
732 | dep->flags |= DWC3_EP_FORCE_RESTART_STREAM; | |
733 | } | |
a97ea994 FB |
734 | } |
735 | ||
2870e501 FB |
736 | out: |
737 | trace_dwc3_gadget_ep_enable(dep); | |
738 | ||
72246da4 FB |
739 | return 0; |
740 | } | |
741 | ||
624407f9 | 742 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) |
72246da4 FB |
743 | { |
744 | struct dwc3_request *req; | |
745 | ||
c5353b22 | 746 | dwc3_stop_active_transfer(dep, true, false); |
624407f9 | 747 | |
0e146028 FB |
748 | /* - giveback all requests to gadget driver */ |
749 | while (!list_empty(&dep->started_list)) { | |
750 | req = next_request(&dep->started_list); | |
1591633e | 751 | |
0e146028 | 752 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
ea53b882 FB |
753 | } |
754 | ||
aa3342c8 FB |
755 | while (!list_empty(&dep->pending_list)) { |
756 | req = next_request(&dep->pending_list); | |
72246da4 | 757 | |
d8eca64e FB |
758 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
759 | } | |
760 | ||
761 | while (!list_empty(&dep->cancelled_list)) { | |
762 | req = next_request(&dep->cancelled_list); | |
763 | ||
624407f9 | 764 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 765 | } |
72246da4 FB |
766 | } |
767 | ||
768 | /** | |
bfad65ee | 769 | * __dwc3_gadget_ep_disable - disables a hw endpoint |
72246da4 FB |
770 | * @dep: the endpoint to disable |
771 | * | |
bfad65ee FB |
772 | * This function undoes what __dwc3_gadget_ep_enable did and also removes |
773 | * requests which are currently being processed by the hardware and those which | |
774 | * are not yet scheduled. | |
775 | * | |
624407f9 | 776 | * Caller should take care of locking. |
72246da4 | 777 | */ |
72246da4 FB |
778 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
779 | { | |
780 | struct dwc3 *dwc = dep->dwc; | |
781 | u32 reg; | |
782 | ||
2870e501 | 783 | trace_dwc3_gadget_ep_disable(dep); |
7eaeac5c | 784 | |
687ef981 FB |
785 | /* make sure HW endpoint isn't stalled */ |
786 | if (dep->flags & DWC3_EP_STALL) | |
7a608559 | 787 | __dwc3_gadget_ep_set_halt(dep, 0, false); |
687ef981 | 788 | |
72246da4 FB |
789 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
790 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
791 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
792 | ||
39ebb05c JY |
793 | /* Clear out the ep descriptors for non-ep0 */ |
794 | if (dep->number > 1) { | |
795 | dep->endpoint.comp_desc = NULL; | |
796 | dep->endpoint.desc = NULL; | |
797 | } | |
798 | ||
f09ddcfc WC |
799 | dwc3_remove_requests(dwc, dep); |
800 | ||
5aef6297 WC |
801 | dep->stream_capable = false; |
802 | dep->type = 0; | |
803 | dep->flags = 0; | |
804 | ||
72246da4 FB |
805 | return 0; |
806 | } | |
807 | ||
808 | /* -------------------------------------------------------------------------- */ | |
809 | ||
810 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
811 | const struct usb_endpoint_descriptor *desc) | |
812 | { | |
813 | return -EINVAL; | |
814 | } | |
815 | ||
816 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
817 | { | |
818 | return -EINVAL; | |
819 | } | |
820 | ||
821 | /* -------------------------------------------------------------------------- */ | |
822 | ||
823 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
824 | const struct usb_endpoint_descriptor *desc) | |
825 | { | |
826 | struct dwc3_ep *dep; | |
827 | struct dwc3 *dwc; | |
828 | unsigned long flags; | |
829 | int ret; | |
830 | ||
831 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
832 | pr_debug("dwc3: invalid parameters\n"); | |
833 | return -EINVAL; | |
834 | } | |
835 | ||
836 | if (!desc->wMaxPacketSize) { | |
837 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
838 | return -EINVAL; | |
839 | } | |
840 | ||
841 | dep = to_dwc3_ep(ep); | |
842 | dwc = dep->dwc; | |
843 | ||
95ca961c FB |
844 | if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED, |
845 | "%s is already enabled\n", | |
846 | dep->name)) | |
c6f83f38 | 847 | return 0; |
c6f83f38 | 848 | |
72246da4 | 849 | spin_lock_irqsave(&dwc->lock, flags); |
a2d23f08 | 850 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
851 | spin_unlock_irqrestore(&dwc->lock, flags); |
852 | ||
853 | return ret; | |
854 | } | |
855 | ||
856 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
857 | { | |
858 | struct dwc3_ep *dep; | |
859 | struct dwc3 *dwc; | |
860 | unsigned long flags; | |
861 | int ret; | |
862 | ||
863 | if (!ep) { | |
864 | pr_debug("dwc3: invalid parameters\n"); | |
865 | return -EINVAL; | |
866 | } | |
867 | ||
868 | dep = to_dwc3_ep(ep); | |
869 | dwc = dep->dwc; | |
870 | ||
95ca961c FB |
871 | if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED), |
872 | "%s is already disabled\n", | |
873 | dep->name)) | |
72246da4 | 874 | return 0; |
72246da4 | 875 | |
72246da4 FB |
876 | spin_lock_irqsave(&dwc->lock, flags); |
877 | ret = __dwc3_gadget_ep_disable(dep); | |
878 | spin_unlock_irqrestore(&dwc->lock, flags); | |
879 | ||
880 | return ret; | |
881 | } | |
882 | ||
883 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
0bd0f6d2 | 884 | gfp_t gfp_flags) |
72246da4 FB |
885 | { |
886 | struct dwc3_request *req; | |
887 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
72246da4 FB |
888 | |
889 | req = kzalloc(sizeof(*req), gfp_flags); | |
734d5a53 | 890 | if (!req) |
72246da4 | 891 | return NULL; |
72246da4 | 892 | |
31a2f5a7 | 893 | req->direction = dep->direction; |
72246da4 FB |
894 | req->epnum = dep->number; |
895 | req->dep = dep; | |
a3af5e3a | 896 | req->status = DWC3_REQUEST_STATUS_UNKNOWN; |
72246da4 | 897 | |
2c4cbe6e FB |
898 | trace_dwc3_alloc_request(req); |
899 | ||
72246da4 FB |
900 | return &req->request; |
901 | } | |
902 | ||
903 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
904 | struct usb_request *request) | |
905 | { | |
906 | struct dwc3_request *req = to_dwc3_request(request); | |
907 | ||
2c4cbe6e | 908 | trace_dwc3_free_request(req); |
72246da4 FB |
909 | kfree(req); |
910 | } | |
911 | ||
42626919 FB |
912 | /** |
913 | * dwc3_ep_prev_trb - returns the previous TRB in the ring | |
914 | * @dep: The endpoint with the TRB ring | |
915 | * @index: The index of the current TRB in the ring | |
916 | * | |
917 | * Returns the TRB prior to the one pointed to by the index. If the | |
918 | * index is 0, we will wrap backwards, skip the link TRB, and return | |
919 | * the one just before that. | |
920 | */ | |
921 | static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index) | |
922 | { | |
923 | u8 tmp = index; | |
924 | ||
925 | if (!tmp) | |
926 | tmp = DWC3_TRB_NUM - 1; | |
927 | ||
928 | return &dep->trb_pool[tmp - 1]; | |
929 | } | |
930 | ||
931 | static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep) | |
932 | { | |
933 | struct dwc3_trb *tmp; | |
934 | u8 trbs_left; | |
935 | ||
936 | /* | |
937 | * If enqueue & dequeue are equal than it is either full or empty. | |
938 | * | |
939 | * One way to know for sure is if the TRB right before us has HWO bit | |
940 | * set or not. If it has, then we're definitely full and can't fit any | |
941 | * more transfers in our ring. | |
942 | */ | |
943 | if (dep->trb_enqueue == dep->trb_dequeue) { | |
944 | tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue); | |
945 | if (tmp->ctrl & DWC3_TRB_CTRL_HWO) | |
946 | return 0; | |
947 | ||
948 | return DWC3_TRB_NUM - 1; | |
949 | } | |
950 | ||
951 | trbs_left = dep->trb_dequeue - dep->trb_enqueue; | |
952 | trbs_left &= (DWC3_TRB_NUM - 1); | |
953 | ||
954 | if (dep->trb_dequeue < dep->trb_enqueue) | |
955 | trbs_left--; | |
956 | ||
957 | return trbs_left; | |
958 | } | |
2c78c029 | 959 | |
e49d3cf4 | 960 | static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb, |
e319bd62 FB |
961 | dma_addr_t dma, unsigned int length, unsigned int chain, |
962 | unsigned int node, unsigned int stream_id, | |
963 | unsigned int short_not_ok, unsigned int no_interrupt, | |
f9cc581b | 964 | unsigned int is_last, bool must_interrupt) |
c71fc37c | 965 | { |
6b9018d4 | 966 | struct dwc3 *dwc = dep->dwc; |
e81a7018 | 967 | struct usb_gadget *gadget = dwc->gadget; |
6b9018d4 | 968 | enum usb_device_speed speed = gadget->speed; |
c71fc37c | 969 | |
f6bafc6a FB |
970 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
971 | trb->bpl = lower_32_bits(dma); | |
972 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 973 | |
16e78db7 | 974 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 975 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 976 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
977 | break; |
978 | ||
979 | case USB_ENDPOINT_XFER_ISOC: | |
6b9018d4 | 980 | if (!node) { |
e5ba5ec8 | 981 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; |
6b9018d4 | 982 | |
40d829fb MG |
983 | /* |
984 | * USB Specification 2.0 Section 5.9.2 states that: "If | |
985 | * there is only a single transaction in the microframe, | |
986 | * only a DATA0 data packet PID is used. If there are | |
987 | * two transactions per microframe, DATA1 is used for | |
988 | * the first transaction data packet and DATA0 is used | |
989 | * for the second transaction data packet. If there are | |
990 | * three transactions per microframe, DATA2 is used for | |
991 | * the first transaction data packet, DATA1 is used for | |
992 | * the second, and DATA0 is used for the third." | |
993 | * | |
994 | * IOW, we should satisfy the following cases: | |
995 | * | |
996 | * 1) length <= maxpacket | |
997 | * - DATA0 | |
998 | * | |
999 | * 2) maxpacket < length <= (2 * maxpacket) | |
1000 | * - DATA1, DATA0 | |
1001 | * | |
1002 | * 3) (2 * maxpacket) < length <= (3 * maxpacket) | |
1003 | * - DATA2, DATA1, DATA0 | |
1004 | */ | |
6b9018d4 FB |
1005 | if (speed == USB_SPEED_HIGH) { |
1006 | struct usb_ep *ep = &dep->endpoint; | |
ec5bb87e | 1007 | unsigned int mult = 2; |
40d829fb MG |
1008 | unsigned int maxp = usb_endpoint_maxp(ep->desc); |
1009 | ||
1010 | if (length <= (2 * maxp)) | |
1011 | mult--; | |
1012 | ||
1013 | if (length <= maxp) | |
1014 | mult--; | |
1015 | ||
1016 | trb->size |= DWC3_TRB_SIZE_PCM1(mult); | |
6b9018d4 FB |
1017 | } |
1018 | } else { | |
e5ba5ec8 | 1019 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; |
6b9018d4 | 1020 | } |
ca4d44ea FB |
1021 | |
1022 | /* always enable Interrupt on Missed ISOC */ | |
1023 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; | |
c71fc37c FB |
1024 | break; |
1025 | ||
1026 | case USB_ENDPOINT_XFER_BULK: | |
1027 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 1028 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
1029 | break; |
1030 | default: | |
1031 | /* | |
1032 | * This is only possible with faulty memory because we | |
1033 | * checked it already :) | |
1034 | */ | |
0a695d4c FB |
1035 | dev_WARN(dwc->dev, "Unknown endpoint type %d\n", |
1036 | usb_endpoint_type(dep->endpoint.desc)); | |
c71fc37c FB |
1037 | } |
1038 | ||
244add8e TJ |
1039 | /* |
1040 | * Enable Continue on Short Packet | |
1041 | * when endpoint is not a stream capable | |
1042 | */ | |
c9508c8c | 1043 | if (usb_endpoint_dir_out(dep->endpoint.desc)) { |
244add8e TJ |
1044 | if (!dep->stream_capable) |
1045 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
f3af3651 | 1046 | |
e49d3cf4 | 1047 | if (short_not_ok) |
c9508c8c FB |
1048 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; |
1049 | } | |
1050 | ||
8dbbe48c | 1051 | if ((!no_interrupt && !chain) || must_interrupt) |
c9508c8c | 1052 | trb->ctrl |= DWC3_TRB_CTRL_IOC; |
f3af3651 | 1053 | |
e5ba5ec8 PA |
1054 | if (chain) |
1055 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
3eaecd0c TN |
1056 | else if (dep->stream_capable && is_last) |
1057 | trb->ctrl |= DWC3_TRB_CTRL_LST; | |
e5ba5ec8 | 1058 | |
16e78db7 | 1059 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
e49d3cf4 | 1060 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id); |
c71fc37c | 1061 | |
f6bafc6a | 1062 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
2c4cbe6e | 1063 | |
b7a4fbe2 AKV |
1064 | dwc3_ep_inc_enq(dep); |
1065 | ||
2c4cbe6e | 1066 | trace_dwc3_prepare_trb(dep, trb); |
c71fc37c FB |
1067 | } |
1068 | ||
e49d3cf4 FB |
1069 | /** |
1070 | * dwc3_prepare_one_trb - setup one TRB from one request | |
1071 | * @dep: endpoint for which this request is prepared | |
1072 | * @req: dwc3_request pointer | |
5d187c04 | 1073 | * @trb_length: buffer size of the TRB |
e49d3cf4 FB |
1074 | * @chain: should this TRB be chained to the next? |
1075 | * @node: only for isochronous endpoints. First TRB needs different type. | |
2b80357b | 1076 | * @use_bounce_buffer: set to use bounce buffer |
f9cc581b | 1077 | * @must_interrupt: set to interrupt on TRB completion |
e49d3cf4 FB |
1078 | */ |
1079 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, | |
5d187c04 | 1080 | struct dwc3_request *req, unsigned int trb_length, |
f9cc581b TN |
1081 | unsigned int chain, unsigned int node, bool use_bounce_buffer, |
1082 | bool must_interrupt) | |
e49d3cf4 FB |
1083 | { |
1084 | struct dwc3_trb *trb; | |
a31e63b6 | 1085 | dma_addr_t dma; |
e319bd62 FB |
1086 | unsigned int stream_id = req->request.stream_id; |
1087 | unsigned int short_not_ok = req->request.short_not_ok; | |
1088 | unsigned int no_interrupt = req->request.no_interrupt; | |
1089 | unsigned int is_last = req->request.is_last; | |
a31e63b6 | 1090 | |
2b80357b TN |
1091 | if (use_bounce_buffer) |
1092 | dma = dep->dwc->bounce_addr; | |
1093 | else if (req->request.num_sgs > 0) | |
a31e63b6 | 1094 | dma = sg_dma_address(req->start_sg); |
5d187c04 | 1095 | else |
a31e63b6 | 1096 | dma = req->request.dma; |
e49d3cf4 FB |
1097 | |
1098 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
1099 | ||
1100 | if (!req->trb) { | |
1101 | dwc3_gadget_move_started_request(req); | |
1102 | req->trb = trb; | |
1103 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
e49d3cf4 FB |
1104 | } |
1105 | ||
09fe1f8d FB |
1106 | req->num_trbs++; |
1107 | ||
5d187c04 | 1108 | __dwc3_prepare_one_trb(dep, trb, dma, trb_length, chain, node, |
f9cc581b TN |
1109 | stream_id, short_not_ok, no_interrupt, is_last, |
1110 | must_interrupt); | |
1111 | } | |
1112 | ||
1113 | static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req) | |
1114 | { | |
1115 | unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc); | |
1116 | unsigned int rem = req->request.length % maxp; | |
1117 | ||
1118 | if ((req->request.length && req->request.zero && !rem && | |
1119 | !usb_endpoint_xfer_isoc(dep->endpoint.desc)) || | |
1120 | (!req->direction && rem)) | |
1121 | return true; | |
1122 | ||
1123 | return false; | |
e49d3cf4 FB |
1124 | } |
1125 | ||
cb1b3997 TN |
1126 | /** |
1127 | * dwc3_prepare_last_sg - prepare TRBs for the last SG entry | |
1128 | * @dep: The endpoint that the request belongs to | |
1129 | * @req: The request to prepare | |
1130 | * @entry_length: The last SG entry size | |
1131 | * @node: Indicates whether this is not the first entry (for isoc only) | |
1132 | * | |
1133 | * Return the number of TRBs prepared. | |
1134 | */ | |
1135 | static int dwc3_prepare_last_sg(struct dwc3_ep *dep, | |
1136 | struct dwc3_request *req, unsigned int entry_length, | |
1137 | unsigned int node) | |
1138 | { | |
1139 | unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc); | |
1140 | unsigned int rem = req->request.length % maxp; | |
1141 | unsigned int num_trbs = 1; | |
1142 | ||
f9cc581b | 1143 | if (dwc3_needs_extra_trb(dep, req)) |
cb1b3997 TN |
1144 | num_trbs++; |
1145 | ||
1146 | if (dwc3_calc_trbs_left(dep) < num_trbs) | |
1147 | return 0; | |
1148 | ||
1149 | req->needs_extra_trb = num_trbs > 1; | |
1150 | ||
1151 | /* Prepare a normal TRB */ | |
1152 | if (req->direction || req->request.length) | |
1153 | dwc3_prepare_one_trb(dep, req, entry_length, | |
f9cc581b | 1154 | req->needs_extra_trb, node, false, false); |
cb1b3997 TN |
1155 | |
1156 | /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */ | |
1157 | if ((!req->direction && !req->request.length) || req->needs_extra_trb) | |
1158 | dwc3_prepare_one_trb(dep, req, | |
1159 | req->direction ? 0 : maxp - rem, | |
f9cc581b | 1160 | false, 1, true, false); |
cb1b3997 TN |
1161 | |
1162 | return num_trbs; | |
1163 | } | |
1164 | ||
7f2958d9 | 1165 | static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep, |
7ae7df49 | 1166 | struct dwc3_request *req) |
5ee85d89 | 1167 | { |
a31e63b6 | 1168 | struct scatterlist *sg = req->start_sg; |
5ee85d89 | 1169 | struct scatterlist *s; |
5ee85d89 | 1170 | int i; |
5d187c04 | 1171 | unsigned int length = req->request.length; |
c96e6725 AKV |
1172 | unsigned int remaining = req->request.num_mapped_sgs |
1173 | - req->num_queued_sgs; | |
13111fcb | 1174 | unsigned int num_trbs = req->num_trbs; |
f9cc581b | 1175 | bool needs_extra_trb = dwc3_needs_extra_trb(dep, req); |
c96e6725 | 1176 | |
5d187c04 TN |
1177 | /* |
1178 | * If we resume preparing the request, then get the remaining length of | |
1179 | * the request and resume where we left off. | |
1180 | */ | |
1181 | for_each_sg(req->request.sg, s, req->num_queued_sgs, i) | |
1182 | length -= sg_dma_len(s); | |
1183 | ||
c96e6725 | 1184 | for_each_sg(sg, s, remaining, i) { |
8dbbe48c | 1185 | unsigned int num_trbs_left = dwc3_calc_trbs_left(dep); |
5d187c04 | 1186 | unsigned int trb_length; |
f9cc581b | 1187 | bool must_interrupt = false; |
cb1b3997 | 1188 | bool last_sg = false; |
5ee85d89 | 1189 | |
5d187c04 TN |
1190 | trb_length = min_t(unsigned int, length, sg_dma_len(s)); |
1191 | ||
1192 | length -= trb_length; | |
1193 | ||
dad2aff3 PP |
1194 | /* |
1195 | * IOMMU driver is coalescing the list of sgs which shares a | |
1196 | * page boundary into one and giving it to USB driver. With | |
1197 | * this the number of sgs mapped is not equal to the number of | |
1198 | * sgs passed. So mark the chain bit to false if it isthe last | |
1199 | * mapped sg. | |
1200 | */ | |
5d187c04 | 1201 | if ((i == remaining - 1) || !length) |
cb1b3997 | 1202 | last_sg = true; |
5ee85d89 | 1203 | |
8dbbe48c | 1204 | if (!num_trbs_left) |
13111fcb TN |
1205 | break; |
1206 | ||
cb1b3997 TN |
1207 | if (last_sg) { |
1208 | if (!dwc3_prepare_last_sg(dep, req, trb_length, i)) | |
f9cc581b | 1209 | break; |
c6267a51 | 1210 | } else { |
f9cc581b TN |
1211 | /* |
1212 | * Look ahead to check if we have enough TRBs for the | |
8dbbe48c TN |
1213 | * next SG entry. If not, set interrupt on this TRB to |
1214 | * resume preparing the next SG entry when more TRBs are | |
f9cc581b TN |
1215 | * free. |
1216 | */ | |
8dbbe48c TN |
1217 | if (num_trbs_left == 1 || (needs_extra_trb && |
1218 | num_trbs_left <= 2 && | |
1219 | sg_dma_len(sg_next(s)) >= length)) | |
f9cc581b TN |
1220 | must_interrupt = true; |
1221 | ||
1222 | dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false, | |
1223 | must_interrupt); | |
c6267a51 | 1224 | } |
5ee85d89 | 1225 | |
a31e63b6 AKV |
1226 | /* |
1227 | * There can be a situation where all sgs in sglist are not | |
1228 | * queued because of insufficient trb number. To handle this | |
1229 | * case, update start_sg to next sg to be queued, so that | |
1230 | * we have free trbs we can continue queuing from where we | |
1231 | * previously stopped | |
1232 | */ | |
cb1b3997 | 1233 | if (!last_sg) |
a31e63b6 AKV |
1234 | req->start_sg = sg_next(s); |
1235 | ||
c96e6725 AKV |
1236 | req->num_queued_sgs++; |
1237 | ||
5d187c04 TN |
1238 | /* |
1239 | * The number of pending SG entries may not correspond to the | |
1240 | * number of mapped SG entries. If all the data are queued, then | |
1241 | * don't include unused SG entries. | |
1242 | */ | |
1243 | if (length == 0) { | |
1244 | req->num_pending_sgs -= req->request.num_mapped_sgs - req->num_queued_sgs; | |
1245 | break; | |
1246 | } | |
1247 | ||
8dbbe48c | 1248 | if (must_interrupt) |
5ee85d89 FB |
1249 | break; |
1250 | } | |
13111fcb | 1251 | |
13111fcb | 1252 | return req->num_trbs - num_trbs; |
5ee85d89 FB |
1253 | } |
1254 | ||
7f2958d9 | 1255 | static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep, |
7ae7df49 | 1256 | struct dwc3_request *req) |
5ee85d89 | 1257 | { |
cb1b3997 | 1258 | return dwc3_prepare_last_sg(dep, req, req->request.length, 0); |
5ee85d89 FB |
1259 | } |
1260 | ||
72246da4 FB |
1261 | /* |
1262 | * dwc3_prepare_trbs - setup TRBs from requests | |
1263 | * @dep: endpoint for which requests are being prepared | |
72246da4 | 1264 | * |
1d046793 PZ |
1265 | * The function goes through the requests list and sets up TRBs for the |
1266 | * transfers. The function returns once there are no more TRBs available or | |
1267 | * it runs out of requests. | |
490410b2 TN |
1268 | * |
1269 | * Returns the number of TRBs prepared or negative errno. | |
72246da4 | 1270 | */ |
490410b2 | 1271 | static int dwc3_prepare_trbs(struct dwc3_ep *dep) |
72246da4 | 1272 | { |
68e823e2 | 1273 | struct dwc3_request *req, *n; |
490410b2 | 1274 | int ret = 0; |
72246da4 FB |
1275 | |
1276 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
1277 | ||
d86c5a67 FB |
1278 | /* |
1279 | * We can get in a situation where there's a request in the started list | |
1280 | * but there weren't enough TRBs to fully kick it in the first time | |
1281 | * around, so it has been waiting for more TRBs to be freed up. | |
1282 | * | |
1283 | * In that case, we should check if we have a request with pending_sgs | |
1284 | * in the started list and prepare TRBs for that request first, | |
1285 | * otherwise we will prepare TRBs completely out of order and that will | |
1286 | * break things. | |
1287 | */ | |
1288 | list_for_each_entry(req, &dep->started_list, list) { | |
490410b2 | 1289 | if (req->num_pending_sgs > 0) { |
7f2958d9 | 1290 | ret = dwc3_prepare_trbs_sg(dep, req); |
346a15cd | 1291 | if (!ret || req->num_pending_sgs) |
490410b2 TN |
1292 | return ret; |
1293 | } | |
d86c5a67 FB |
1294 | |
1295 | if (!dwc3_calc_trbs_left(dep)) | |
490410b2 | 1296 | return ret; |
63c7bb29 TN |
1297 | |
1298 | /* | |
1299 | * Don't prepare beyond a transfer. In DWC_usb32, its transfer | |
1300 | * burst capability may try to read and use TRBs beyond the | |
1301 | * active transfer instead of stopping. | |
1302 | */ | |
1303 | if (dep->stream_capable && req->request.is_last) | |
490410b2 | 1304 | return ret; |
d86c5a67 FB |
1305 | } |
1306 | ||
aa3342c8 | 1307 | list_for_each_entry_safe(req, n, &dep->pending_list, list) { |
cdb55b39 | 1308 | struct dwc3 *dwc = dep->dwc; |
cdb55b39 FB |
1309 | |
1310 | ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request, | |
1311 | dep->direction); | |
1312 | if (ret) | |
490410b2 | 1313 | return ret; |
cdb55b39 FB |
1314 | |
1315 | req->sg = req->request.sg; | |
a31e63b6 | 1316 | req->start_sg = req->sg; |
c96e6725 | 1317 | req->num_queued_sgs = 0; |
cdb55b39 FB |
1318 | req->num_pending_sgs = req->request.num_mapped_sgs; |
1319 | ||
346a15cd | 1320 | if (req->num_pending_sgs > 0) { |
7f2958d9 | 1321 | ret = dwc3_prepare_trbs_sg(dep, req); |
346a15cd TN |
1322 | if (req->num_pending_sgs) |
1323 | return ret; | |
1324 | } else { | |
7f2958d9 | 1325 | ret = dwc3_prepare_trbs_linear(dep, req); |
346a15cd | 1326 | } |
72246da4 | 1327 | |
490410b2 TN |
1328 | if (!ret || !dwc3_calc_trbs_left(dep)) |
1329 | return ret; | |
aefe3d23 TN |
1330 | |
1331 | /* | |
1332 | * Don't prepare beyond a transfer. In DWC_usb32, its transfer | |
1333 | * burst capability may try to read and use TRBs beyond the | |
1334 | * active transfer instead of stopping. | |
1335 | */ | |
1336 | if (dep->stream_capable && req->request.is_last) | |
490410b2 | 1337 | return ret; |
72246da4 | 1338 | } |
490410b2 TN |
1339 | |
1340 | return ret; | |
72246da4 FB |
1341 | } |
1342 | ||
8d99087c TN |
1343 | static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep); |
1344 | ||
7fdca766 | 1345 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep) |
72246da4 FB |
1346 | { |
1347 | struct dwc3_gadget_ep_cmd_params params; | |
1348 | struct dwc3_request *req; | |
4fae2e3e | 1349 | int starting; |
72246da4 FB |
1350 | int ret; |
1351 | u32 cmd; | |
1352 | ||
d72ecc08 TN |
1353 | /* |
1354 | * Note that it's normal to have no new TRBs prepared (i.e. ret == 0). | |
1355 | * This happens when we need to stop and restart a transfer such as in | |
1356 | * the case of reinitiating a stream or retrying an isoc transfer. | |
1357 | */ | |
490410b2 | 1358 | ret = dwc3_prepare_trbs(dep); |
d72ecc08 | 1359 | if (ret < 0) |
490410b2 | 1360 | return ret; |
ccb94ebf | 1361 | |
1912cbc6 | 1362 | starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED); |
72246da4 | 1363 | |
2338484d TN |
1364 | /* |
1365 | * If there's no new TRB prepared and we don't need to restart a | |
1366 | * transfer, there's no need to update the transfer. | |
1367 | */ | |
1368 | if (!ret && !starting) | |
1369 | return ret; | |
1370 | ||
4fae2e3e | 1371 | req = next_request(&dep->started_list); |
72246da4 FB |
1372 | if (!req) { |
1373 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
1374 | return 0; | |
1375 | } | |
1376 | ||
1377 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 1378 | |
4fae2e3e | 1379 | if (starting) { |
1877d6c9 PA |
1380 | params.param0 = upper_32_bits(req->trb_dma); |
1381 | params.param1 = lower_32_bits(req->trb_dma); | |
7fdca766 FB |
1382 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
1383 | ||
a7351807 AKV |
1384 | if (dep->stream_capable) |
1385 | cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id); | |
1386 | ||
7fdca766 FB |
1387 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
1388 | cmd |= DWC3_DEPCMD_PARAM(dep->frame_number); | |
1877d6c9 | 1389 | } else { |
b6b1c6db FB |
1390 | cmd = DWC3_DEPCMD_UPDATETRANSFER | |
1391 | DWC3_DEPCMD_PARAM(dep->resource_index); | |
1877d6c9 | 1392 | } |
72246da4 | 1393 | |
2cd4718d | 1394 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
72246da4 | 1395 | if (ret < 0) { |
8d99087c TN |
1396 | struct dwc3_request *tmp; |
1397 | ||
1398 | if (ret == -EAGAIN) | |
1399 | return ret; | |
1400 | ||
1401 | dwc3_stop_active_transfer(dep, true, true); | |
1402 | ||
1403 | list_for_each_entry_safe(req, tmp, &dep->started_list, list) | |
04dd6e76 | 1404 | dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED); |
8d99087c TN |
1405 | |
1406 | /* If ep isn't started, then there's no end transfer pending */ | |
1407 | if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING)) | |
1408 | dwc3_gadget_ep_cleanup_cancelled_requests(dep); | |
1409 | ||
72246da4 FB |
1410 | return ret; |
1411 | } | |
1412 | ||
e0d19563 TN |
1413 | if (dep->stream_capable && req->request.is_last) |
1414 | dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE; | |
1415 | ||
72246da4 FB |
1416 | return 0; |
1417 | } | |
1418 | ||
6cb2e4e3 FB |
1419 | static int __dwc3_gadget_get_frame(struct dwc3 *dwc) |
1420 | { | |
1421 | u32 reg; | |
1422 | ||
1423 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1424 | return DWC3_DSTS_SOFFN(reg); | |
1425 | } | |
1426 | ||
d92021f6 TN |
1427 | /** |
1428 | * dwc3_gadget_start_isoc_quirk - workaround invalid frame number | |
1429 | * @dep: isoc endpoint | |
1430 | * | |
1431 | * This function tests for the correct combination of BIT[15:14] from the 16-bit | |
1432 | * microframe number reported by the XferNotReady event for the future frame | |
1433 | * number to start the isoc transfer. | |
1434 | * | |
1435 | * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed | |
1436 | * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the | |
1437 | * XferNotReady event are invalid. The driver uses this number to schedule the | |
1438 | * isochronous transfer and passes it to the START TRANSFER command. Because | |
1439 | * this number is invalid, the command may fail. If BIT[15:14] matches the | |
1440 | * internal 16-bit microframe, the START TRANSFER command will pass and the | |
1441 | * transfer will start at the scheduled time, if it is off by 1, the command | |
1442 | * will still pass, but the transfer will start 2 seconds in the future. For all | |
1443 | * other conditions, the START TRANSFER command will fail with bus-expiry. | |
1444 | * | |
1445 | * In order to workaround this issue, we can test for the correct combination of | |
1446 | * BIT[15:14] by sending START TRANSFER commands with different values of | |
1447 | * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart | |
1448 | * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status. | |
1449 | * As the result, within the 4 possible combinations for BIT[15:14], there will | |
1450 | * be 2 successful and 2 failure START COMMAND status. One of the 2 successful | |
1451 | * command status will result in a 2-second delay start. The smaller BIT[15:14] | |
1452 | * value is the correct combination. | |
1453 | * | |
1454 | * Since there are only 4 outcomes and the results are ordered, we can simply | |
1455 | * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to | |
1456 | * deduce the smaller successful combination. | |
1457 | * | |
1458 | * Let test0 = test status for combination 'b00 and test1 = test status for 'b01 | |
1459 | * of BIT[15:14]. The correct combination is as follow: | |
1460 | * | |
1461 | * if test0 fails and test1 passes, BIT[15:14] is 'b01 | |
1462 | * if test0 fails and test1 fails, BIT[15:14] is 'b10 | |
1463 | * if test0 passes and test1 fails, BIT[15:14] is 'b11 | |
1464 | * if test0 passes and test1 passes, BIT[15:14] is 'b00 | |
1465 | * | |
1466 | * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN | |
1467 | * endpoints. | |
1468 | */ | |
25abad6a | 1469 | static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep) |
d92021f6 TN |
1470 | { |
1471 | int cmd_status = 0; | |
1472 | bool test0; | |
1473 | bool test1; | |
1474 | ||
1475 | while (dep->combo_num < 2) { | |
1476 | struct dwc3_gadget_ep_cmd_params params; | |
1477 | u32 test_frame_number; | |
1478 | u32 cmd; | |
1479 | ||
1480 | /* | |
1481 | * Check if we can start isoc transfer on the next interval or | |
1482 | * 4 uframes in the future with BIT[15:14] as dep->combo_num | |
1483 | */ | |
ca143785 | 1484 | test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK; |
d92021f6 TN |
1485 | test_frame_number |= dep->combo_num << 14; |
1486 | test_frame_number += max_t(u32, 4, dep->interval); | |
1487 | ||
1488 | params.param0 = upper_32_bits(dep->dwc->bounce_addr); | |
1489 | params.param1 = lower_32_bits(dep->dwc->bounce_addr); | |
1490 | ||
1491 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
1492 | cmd |= DWC3_DEPCMD_PARAM(test_frame_number); | |
1493 | cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
1494 | ||
1495 | /* Redo if some other failure beside bus-expiry is received */ | |
1496 | if (cmd_status && cmd_status != -EAGAIN) { | |
1497 | dep->start_cmd_status = 0; | |
1498 | dep->combo_num = 0; | |
25abad6a | 1499 | return 0; |
d92021f6 TN |
1500 | } |
1501 | ||
1502 | /* Store the first test status */ | |
1503 | if (dep->combo_num == 0) | |
1504 | dep->start_cmd_status = cmd_status; | |
1505 | ||
1506 | dep->combo_num++; | |
1507 | ||
1508 | /* | |
1509 | * End the transfer if the START_TRANSFER command is successful | |
1510 | * to wait for the next XferNotReady to test the command again | |
1511 | */ | |
1512 | if (cmd_status == 0) { | |
c5353b22 | 1513 | dwc3_stop_active_transfer(dep, true, true); |
25abad6a | 1514 | return 0; |
d92021f6 TN |
1515 | } |
1516 | } | |
1517 | ||
1518 | /* test0 and test1 are both completed at this point */ | |
1519 | test0 = (dep->start_cmd_status == 0); | |
1520 | test1 = (cmd_status == 0); | |
1521 | ||
1522 | if (!test0 && test1) | |
1523 | dep->combo_num = 1; | |
1524 | else if (!test0 && !test1) | |
1525 | dep->combo_num = 2; | |
1526 | else if (test0 && !test1) | |
1527 | dep->combo_num = 3; | |
1528 | else if (test0 && test1) | |
1529 | dep->combo_num = 0; | |
1530 | ||
ca143785 | 1531 | dep->frame_number &= DWC3_FRNUMBER_MASK; |
d92021f6 TN |
1532 | dep->frame_number |= dep->combo_num << 14; |
1533 | dep->frame_number += max_t(u32, 4, dep->interval); | |
1534 | ||
1535 | /* Reinitialize test variables */ | |
1536 | dep->start_cmd_status = 0; | |
1537 | dep->combo_num = 0; | |
1538 | ||
25abad6a | 1539 | return __dwc3_gadget_kick_transfer(dep); |
d92021f6 TN |
1540 | } |
1541 | ||
25abad6a | 1542 | static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep) |
d6d6ec7b | 1543 | { |
c5a7092f | 1544 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
d92021f6 | 1545 | struct dwc3 *dwc = dep->dwc; |
d5370106 FB |
1546 | int ret; |
1547 | int i; | |
d92021f6 | 1548 | |
36f05d36 TN |
1549 | if (list_empty(&dep->pending_list) && |
1550 | list_empty(&dep->started_list)) { | |
f4a53c55 | 1551 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
25abad6a | 1552 | return -EAGAIN; |
d6d6ec7b PA |
1553 | } |
1554 | ||
9af21dd6 TN |
1555 | if (!dwc->dis_start_transfer_quirk && |
1556 | (DWC3_VER_IS_PRIOR(DWC31, 170A) || | |
1557 | DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) { | |
e81a7018 | 1558 | if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction) |
25abad6a | 1559 | return dwc3_gadget_start_isoc_quirk(dep); |
d6d6ec7b PA |
1560 | } |
1561 | ||
c5a7092f | 1562 | if (desc->bInterval <= 14 && |
e81a7018 | 1563 | dwc->gadget->speed >= USB_SPEED_HIGH) { |
c5a7092f MO |
1564 | u32 frame = __dwc3_gadget_get_frame(dwc); |
1565 | bool rollover = frame < | |
1566 | (dep->frame_number & DWC3_FRNUMBER_MASK); | |
1567 | ||
1568 | /* | |
1569 | * frame_number is set from XferNotReady and may be already | |
1570 | * out of date. DSTS only provides the lower 14 bit of the | |
1571 | * current frame number. So add the upper two bits of | |
1572 | * frame_number and handle a possible rollover. | |
1573 | * This will provide the correct frame_number unless more than | |
1574 | * rollover has happened since XferNotReady. | |
1575 | */ | |
1576 | ||
1577 | dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) | | |
1578 | frame; | |
1579 | if (rollover) | |
1580 | dep->frame_number += BIT(14); | |
1581 | } | |
1582 | ||
d5370106 FB |
1583 | for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) { |
1584 | dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1); | |
1585 | ||
1586 | ret = __dwc3_gadget_kick_transfer(dep); | |
1587 | if (ret != -EAGAIN) | |
1588 | break; | |
1589 | } | |
1590 | ||
36f05d36 TN |
1591 | /* |
1592 | * After a number of unsuccessful start attempts due to bus-expiry | |
1593 | * status, issue END_TRANSFER command and retry on the next XferNotReady | |
1594 | * event. | |
1595 | */ | |
1596 | if (ret == -EAGAIN) { | |
1597 | struct dwc3_gadget_ep_cmd_params params; | |
1598 | u32 cmd; | |
1599 | ||
1600 | cmd = DWC3_DEPCMD_ENDTRANSFER | | |
1601 | DWC3_DEPCMD_CMDIOC | | |
1602 | DWC3_DEPCMD_PARAM(dep->resource_index); | |
1603 | ||
1604 | dep->resource_index = 0; | |
1605 | memset(¶ms, 0, sizeof(params)); | |
1606 | ||
1607 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
1608 | if (!ret) | |
1609 | dep->flags |= DWC3_EP_END_TRANSFER_PENDING; | |
1610 | } | |
1611 | ||
d5370106 | 1612 | return ret; |
d6d6ec7b PA |
1613 | } |
1614 | ||
72246da4 FB |
1615 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1616 | { | |
0fc9a1be | 1617 | struct dwc3 *dwc = dep->dwc; |
0fc9a1be | 1618 | |
f09ddcfc | 1619 | if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) { |
5eb30ced FB |
1620 | dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", |
1621 | dep->name); | |
bb423984 FB |
1622 | return -ESHUTDOWN; |
1623 | } | |
1624 | ||
04fb365c FB |
1625 | if (WARN(req->dep != dep, "request %pK belongs to '%s'\n", |
1626 | &req->request, req->dep->name)) | |
bb423984 | 1627 | return -EINVAL; |
bb423984 | 1628 | |
b2b6d601 FB |
1629 | if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED, |
1630 | "%s: request %pK already in flight\n", | |
1631 | dep->name, &req->request)) | |
1632 | return -EINVAL; | |
1633 | ||
fc8bb91b FB |
1634 | pm_runtime_get(dwc->dev); |
1635 | ||
72246da4 FB |
1636 | req->request.actual = 0; |
1637 | req->request.status = -EINPROGRESS; | |
72246da4 | 1638 | |
fe84f522 FB |
1639 | trace_dwc3_ep_queue(req); |
1640 | ||
aa3342c8 | 1641 | list_add_tail(&req->list, &dep->pending_list); |
a3af5e3a | 1642 | req->status = DWC3_REQUEST_STATUS_QUEUED; |
72246da4 | 1643 | |
e0d19563 TN |
1644 | if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE) |
1645 | return 0; | |
1646 | ||
c503672a TN |
1647 | /* |
1648 | * Start the transfer only after the END_TRANSFER is completed | |
1649 | * and endpoint STALL is cleared. | |
1650 | */ | |
1651 | if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) || | |
1652 | (dep->flags & DWC3_EP_WEDGE) || | |
1653 | (dep->flags & DWC3_EP_STALL)) { | |
da10bcdd TN |
1654 | dep->flags |= DWC3_EP_DELAY_START; |
1655 | return 0; | |
1656 | } | |
1657 | ||
d889c23c FB |
1658 | /* |
1659 | * NOTICE: Isochronous endpoints should NEVER be prestarted. We must | |
1660 | * wait for a XferNotReady event so we will know what's the current | |
1661 | * (micro-)frame number. | |
1662 | * | |
1663 | * Without this trick, we are very, very likely gonna get Bus Expiry | |
1664 | * errors which will force us issue EndTransfer command. | |
1665 | */ | |
1666 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
fe990cea FB |
1667 | if (!(dep->flags & DWC3_EP_PENDING_REQUEST) && |
1668 | !(dep->flags & DWC3_EP_TRANSFER_STARTED)) | |
1669 | return 0; | |
1670 | ||
6cb2e4e3 | 1671 | if ((dep->flags & DWC3_EP_PENDING_REQUEST)) { |
e319bd62 | 1672 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) |
25abad6a | 1673 | return __dwc3_gadget_start_isoc(dep); |
08a36b54 | 1674 | } |
64e01080 | 1675 | } |
b997ada5 | 1676 | |
7fdca766 | 1677 | return __dwc3_gadget_kick_transfer(dep); |
72246da4 FB |
1678 | } |
1679 | ||
1680 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, | |
1681 | gfp_t gfp_flags) | |
1682 | { | |
1683 | struct dwc3_request *req = to_dwc3_request(request); | |
1684 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1685 | struct dwc3 *dwc = dep->dwc; | |
1686 | ||
1687 | unsigned long flags; | |
1688 | ||
1689 | int ret; | |
1690 | ||
fdee4eba | 1691 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1692 | ret = __dwc3_gadget_ep_queue(dep, req); |
1693 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1694 | ||
1695 | return ret; | |
1696 | } | |
1697 | ||
7746a8df FB |
1698 | static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req) |
1699 | { | |
1700 | int i; | |
1701 | ||
cb11ea56 TN |
1702 | /* If req->trb is not set, then the request has not started */ |
1703 | if (!req->trb) | |
1704 | return; | |
1705 | ||
7746a8df FB |
1706 | /* |
1707 | * If request was already started, this means we had to | |
1708 | * stop the transfer. With that we also need to ignore | |
1709 | * all TRBs used by the request, however TRBs can only | |
1710 | * be modified after completion of END_TRANSFER | |
1711 | * command. So what we do here is that we wait for | |
1712 | * END_TRANSFER completion and only after that, we jump | |
1713 | * over TRBs by clearing HWO and incrementing dequeue | |
1714 | * pointer. | |
1715 | */ | |
1716 | for (i = 0; i < req->num_trbs; i++) { | |
1717 | struct dwc3_trb *trb; | |
1718 | ||
2dedea03 | 1719 | trb = &dep->trb_pool[dep->trb_dequeue]; |
7746a8df FB |
1720 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; |
1721 | dwc3_ep_inc_deq(dep); | |
1722 | } | |
c7152763 TN |
1723 | |
1724 | req->num_trbs = 0; | |
7746a8df FB |
1725 | } |
1726 | ||
d4f1afe5 FB |
1727 | static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep) |
1728 | { | |
1729 | struct dwc3_request *req; | |
1730 | struct dwc3_request *tmp; | |
04dd6e76 | 1731 | struct dwc3 *dwc = dep->dwc; |
d4f1afe5 FB |
1732 | |
1733 | list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) { | |
1734 | dwc3_gadget_ep_skip_trbs(dep, req); | |
04dd6e76 RC |
1735 | switch (req->status) { |
1736 | case DWC3_REQUEST_STATUS_DISCONNECTED: | |
1737 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); | |
1738 | break; | |
1739 | case DWC3_REQUEST_STATUS_DEQUEUED: | |
1740 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1741 | break; | |
1742 | case DWC3_REQUEST_STATUS_STALLED: | |
1743 | dwc3_gadget_giveback(dep, req, -EPIPE); | |
1744 | break; | |
1745 | default: | |
1746 | dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status); | |
1747 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1748 | break; | |
1749 | } | |
d4f1afe5 FB |
1750 | } |
1751 | } | |
1752 | ||
72246da4 FB |
1753 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, |
1754 | struct usb_request *request) | |
1755 | { | |
1756 | struct dwc3_request *req = to_dwc3_request(request); | |
1757 | struct dwc3_request *r = NULL; | |
1758 | ||
1759 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1760 | struct dwc3 *dwc = dep->dwc; | |
1761 | ||
1762 | unsigned long flags; | |
1763 | int ret = 0; | |
1764 | ||
2c4cbe6e FB |
1765 | trace_dwc3_ep_dequeue(req); |
1766 | ||
72246da4 FB |
1767 | spin_lock_irqsave(&dwc->lock, flags); |
1768 | ||
a7027ca6 | 1769 | list_for_each_entry(r, &dep->cancelled_list, list) { |
72246da4 | 1770 | if (r == req) |
fcd2def6 | 1771 | goto out; |
72246da4 FB |
1772 | } |
1773 | ||
aa3342c8 | 1774 | list_for_each_entry(r, &dep->pending_list, list) { |
fcd2def6 TN |
1775 | if (r == req) { |
1776 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1777 | goto out; | |
72246da4 | 1778 | } |
72246da4 FB |
1779 | } |
1780 | ||
fcd2def6 | 1781 | list_for_each_entry(r, &dep->started_list, list) { |
72246da4 | 1782 | if (r == req) { |
a7027ca6 TN |
1783 | struct dwc3_request *t; |
1784 | ||
72246da4 | 1785 | /* wait until it is processed */ |
c5353b22 | 1786 | dwc3_stop_active_transfer(dep, true, true); |
cf3113d8 | 1787 | |
a7027ca6 TN |
1788 | /* |
1789 | * Remove any started request if the transfer is | |
1790 | * cancelled. | |
1791 | */ | |
1792 | list_for_each_entry_safe(r, t, &dep->started_list, list) | |
04dd6e76 RC |
1793 | dwc3_gadget_move_cancelled_request(r, |
1794 | DWC3_REQUEST_STATUS_DEQUEUED); | |
cf3113d8 | 1795 | |
a5c7682a TN |
1796 | dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE; |
1797 | ||
fcd2def6 | 1798 | goto out; |
72246da4 | 1799 | } |
72246da4 FB |
1800 | } |
1801 | ||
fcd2def6 TN |
1802 | dev_err(dwc->dev, "request %pK was not queued to %s\n", |
1803 | request, ep->name); | |
1804 | ret = -EINVAL; | |
1805 | out: | |
72246da4 FB |
1806 | spin_unlock_irqrestore(&dwc->lock, flags); |
1807 | ||
1808 | return ret; | |
1809 | } | |
1810 | ||
7a608559 | 1811 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) |
72246da4 FB |
1812 | { |
1813 | struct dwc3_gadget_ep_cmd_params params; | |
1814 | struct dwc3 *dwc = dep->dwc; | |
cb11ea56 TN |
1815 | struct dwc3_request *req; |
1816 | struct dwc3_request *tmp; | |
72246da4 FB |
1817 | int ret; |
1818 | ||
5ad02fb8 FB |
1819 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
1820 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); | |
1821 | return -EINVAL; | |
1822 | } | |
1823 | ||
72246da4 FB |
1824 | memset(¶ms, 0x00, sizeof(params)); |
1825 | ||
1826 | if (value) { | |
69450c4d FB |
1827 | struct dwc3_trb *trb; |
1828 | ||
e319bd62 FB |
1829 | unsigned int transfer_in_flight; |
1830 | unsigned int started; | |
69450c4d FB |
1831 | |
1832 | if (dep->number > 1) | |
1833 | trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue); | |
1834 | else | |
1835 | trb = &dwc->ep0_trb[dep->trb_enqueue]; | |
1836 | ||
1837 | transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO; | |
1838 | started = !list_empty(&dep->started_list); | |
1839 | ||
1840 | if (!protocol && ((dep->direction && transfer_in_flight) || | |
1841 | (!dep->direction && started))) { | |
7a608559 FB |
1842 | return -EAGAIN; |
1843 | } | |
1844 | ||
2cd4718d FB |
1845 | ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL, |
1846 | ¶ms); | |
72246da4 | 1847 | if (ret) |
3f89204b | 1848 | dev_err(dwc->dev, "failed to set STALL on %s\n", |
72246da4 FB |
1849 | dep->name); |
1850 | else | |
1851 | dep->flags |= DWC3_EP_STALL; | |
1852 | } else { | |
cb11ea56 TN |
1853 | /* |
1854 | * Don't issue CLEAR_STALL command to control endpoints. The | |
1855 | * controller automatically clears the STALL when it receives | |
1856 | * the SETUP token. | |
1857 | */ | |
1858 | if (dep->number <= 1) { | |
1859 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); | |
1860 | return 0; | |
1861 | } | |
2cd4718d | 1862 | |
d97c78a1 TN |
1863 | dwc3_stop_active_transfer(dep, true, true); |
1864 | ||
1865 | list_for_each_entry_safe(req, tmp, &dep->started_list, list) | |
04dd6e76 | 1866 | dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED); |
d97c78a1 TN |
1867 | |
1868 | if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) { | |
1869 | dep->flags |= DWC3_EP_PENDING_CLEAR_STALL; | |
1870 | return 0; | |
1871 | } | |
1872 | ||
1873 | dwc3_gadget_ep_cleanup_cancelled_requests(dep); | |
1874 | ||
50c763f8 | 1875 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
cb11ea56 | 1876 | if (ret) { |
3f89204b | 1877 | dev_err(dwc->dev, "failed to clear STALL on %s\n", |
72246da4 | 1878 | dep->name); |
cb11ea56 TN |
1879 | return ret; |
1880 | } | |
1881 | ||
1882 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); | |
1883 | ||
c503672a TN |
1884 | if ((dep->flags & DWC3_EP_DELAY_START) && |
1885 | !usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
1886 | __dwc3_gadget_kick_transfer(dep); | |
1887 | ||
1888 | dep->flags &= ~DWC3_EP_DELAY_START; | |
72246da4 | 1889 | } |
5275455a | 1890 | |
72246da4 FB |
1891 | return ret; |
1892 | } | |
1893 | ||
1894 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1895 | { | |
1896 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1897 | struct dwc3 *dwc = dep->dwc; | |
1898 | ||
1899 | unsigned long flags; | |
1900 | ||
1901 | int ret; | |
1902 | ||
1903 | spin_lock_irqsave(&dwc->lock, flags); | |
7a608559 | 1904 | ret = __dwc3_gadget_ep_set_halt(dep, value, false); |
72246da4 FB |
1905 | spin_unlock_irqrestore(&dwc->lock, flags); |
1906 | ||
1907 | return ret; | |
1908 | } | |
1909 | ||
1910 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1911 | { | |
1912 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1913 | struct dwc3 *dwc = dep->dwc; |
1914 | unsigned long flags; | |
95aa4e8d | 1915 | int ret; |
72246da4 | 1916 | |
249a4569 | 1917 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1918 | dep->flags |= DWC3_EP_WEDGE; |
1919 | ||
08f0d966 | 1920 | if (dep->number == 0 || dep->number == 1) |
95aa4e8d | 1921 | ret = __dwc3_gadget_ep0_set_halt(ep, 1); |
08f0d966 | 1922 | else |
7a608559 | 1923 | ret = __dwc3_gadget_ep_set_halt(dep, 1, false); |
95aa4e8d FB |
1924 | spin_unlock_irqrestore(&dwc->lock, flags); |
1925 | ||
1926 | return ret; | |
72246da4 FB |
1927 | } |
1928 | ||
1929 | /* -------------------------------------------------------------------------- */ | |
1930 | ||
1931 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1932 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1933 | .bDescriptorType = USB_DT_ENDPOINT, | |
1934 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1935 | }; | |
1936 | ||
1937 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1938 | .enable = dwc3_gadget_ep0_enable, | |
1939 | .disable = dwc3_gadget_ep0_disable, | |
1940 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1941 | .free_request = dwc3_gadget_ep_free_request, | |
1942 | .queue = dwc3_gadget_ep0_queue, | |
1943 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 1944 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
1945 | .set_wedge = dwc3_gadget_ep_set_wedge, |
1946 | }; | |
1947 | ||
1948 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1949 | .enable = dwc3_gadget_ep_enable, | |
1950 | .disable = dwc3_gadget_ep_disable, | |
1951 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1952 | .free_request = dwc3_gadget_ep_free_request, | |
1953 | .queue = dwc3_gadget_ep_queue, | |
1954 | .dequeue = dwc3_gadget_ep_dequeue, | |
1955 | .set_halt = dwc3_gadget_ep_set_halt, | |
1956 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1957 | }; | |
1958 | ||
1959 | /* -------------------------------------------------------------------------- */ | |
1960 | ||
1961 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1962 | { | |
1963 | struct dwc3 *dwc = gadget_to_dwc(g); | |
72246da4 | 1964 | |
6cb2e4e3 | 1965 | return __dwc3_gadget_get_frame(dwc); |
72246da4 FB |
1966 | } |
1967 | ||
218ef7b6 | 1968 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc) |
72246da4 | 1969 | { |
d6011f6f | 1970 | int retries; |
72246da4 | 1971 | |
218ef7b6 | 1972 | int ret; |
72246da4 FB |
1973 | u32 reg; |
1974 | ||
72246da4 | 1975 | u8 link_state; |
72246da4 | 1976 | |
72246da4 FB |
1977 | /* |
1978 | * According to the Databook Remote wakeup request should | |
1979 | * be issued only when the device is in early suspend state. | |
1980 | * | |
1981 | * We can check that via USB Link State bits in DSTS register. | |
1982 | */ | |
1983 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1984 | ||
72246da4 FB |
1985 | link_state = DWC3_DSTS_USBLNKST(reg); |
1986 | ||
1987 | switch (link_state) { | |
d0550cd2 | 1988 | case DWC3_LINK_STATE_RESET: |
72246da4 FB |
1989 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ |
1990 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
c560e763 TN |
1991 | case DWC3_LINK_STATE_U2: /* in HS, means Sleep (L1) */ |
1992 | case DWC3_LINK_STATE_U1: | |
d0550cd2 | 1993 | case DWC3_LINK_STATE_RESUME: |
72246da4 FB |
1994 | break; |
1995 | default: | |
218ef7b6 | 1996 | return -EINVAL; |
72246da4 FB |
1997 | } |
1998 | ||
8598bde7 FB |
1999 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
2000 | if (ret < 0) { | |
2001 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
218ef7b6 | 2002 | return ret; |
8598bde7 | 2003 | } |
72246da4 | 2004 | |
802fde98 | 2005 | /* Recent versions do this automatically */ |
9af21dd6 | 2006 | if (DWC3_VER_IS_PRIOR(DWC3, 194A)) { |
802fde98 | 2007 | /* write zeroes to Link Change Request */ |
fcc023c7 | 2008 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
2009 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
2010 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2011 | } | |
72246da4 | 2012 | |
1d046793 | 2013 | /* poll until Link State changes to ON */ |
d6011f6f | 2014 | retries = 20000; |
72246da4 | 2015 | |
d6011f6f | 2016 | while (retries--) { |
72246da4 FB |
2017 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2018 | ||
2019 | /* in HS, means ON */ | |
2020 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
2021 | break; | |
2022 | } | |
2023 | ||
2024 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
2025 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
218ef7b6 | 2026 | return -EINVAL; |
72246da4 FB |
2027 | } |
2028 | ||
218ef7b6 FB |
2029 | return 0; |
2030 | } | |
2031 | ||
2032 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
2033 | { | |
2034 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2035 | unsigned long flags; | |
2036 | int ret; | |
2037 | ||
2038 | spin_lock_irqsave(&dwc->lock, flags); | |
2039 | ret = __dwc3_gadget_wakeup(dwc); | |
72246da4 FB |
2040 | spin_unlock_irqrestore(&dwc->lock, flags); |
2041 | ||
2042 | return ret; | |
2043 | } | |
2044 | ||
2045 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
2046 | int is_selfpowered) | |
2047 | { | |
2048 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 2049 | unsigned long flags; |
72246da4 | 2050 | |
249a4569 | 2051 | spin_lock_irqsave(&dwc->lock, flags); |
bcdea503 | 2052 | g->is_selfpowered = !!is_selfpowered; |
249a4569 | 2053 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
2054 | |
2055 | return 0; | |
2056 | } | |
2057 | ||
ae7e8610 WC |
2058 | static void dwc3_stop_active_transfers(struct dwc3 *dwc) |
2059 | { | |
2060 | u32 epnum; | |
2061 | ||
2062 | for (epnum = 2; epnum < dwc->num_eps; epnum++) { | |
2063 | struct dwc3_ep *dep; | |
2064 | ||
2065 | dep = dwc->eps[epnum]; | |
2066 | if (!dep) | |
2067 | continue; | |
2068 | ||
2069 | dwc3_remove_requests(dwc, dep); | |
2070 | } | |
2071 | } | |
2072 | ||
072cab8a TN |
2073 | static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc) |
2074 | { | |
2075 | enum usb_ssp_rate ssp_rate = dwc->gadget_ssp_rate; | |
2076 | u32 reg; | |
2077 | ||
2078 | if (ssp_rate == USB_SSP_GEN_UNKNOWN) | |
2079 | ssp_rate = dwc->max_ssp_rate; | |
2080 | ||
2081 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2082 | reg &= ~DWC3_DCFG_SPEED_MASK; | |
2083 | reg &= ~DWC3_DCFG_NUMLANES(~0); | |
2084 | ||
2085 | if (ssp_rate == USB_SSP_GEN_1x2) | |
2086 | reg |= DWC3_DCFG_SUPERSPEED; | |
2087 | else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2) | |
2088 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; | |
2089 | ||
2090 | if (ssp_rate != USB_SSP_GEN_2x1 && | |
2091 | dwc->max_ssp_rate != USB_SSP_GEN_2x1) | |
2092 | reg |= DWC3_DCFG_NUMLANES(1); | |
2093 | ||
2094 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2095 | } | |
2096 | ||
7c9a2598 WC |
2097 | static void __dwc3_gadget_set_speed(struct dwc3 *dwc) |
2098 | { | |
450b9e9f | 2099 | enum usb_device_speed speed; |
7c9a2598 WC |
2100 | u32 reg; |
2101 | ||
450b9e9f | 2102 | speed = dwc->gadget_max_speed; |
93f1d43c | 2103 | if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed) |
450b9e9f TN |
2104 | speed = dwc->maximum_speed; |
2105 | ||
2106 | if (speed == USB_SPEED_SUPER_PLUS && | |
072cab8a TN |
2107 | DWC3_IP_IS(DWC32)) { |
2108 | __dwc3_gadget_set_ssp_rate(dwc); | |
2109 | return; | |
2110 | } | |
2111 | ||
7c9a2598 WC |
2112 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
2113 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
2114 | ||
2115 | /* | |
2116 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
2117 | * which would cause metastability state on Run/Stop | |
2118 | * bit if we try to force the IP to USB2-only mode. | |
2119 | * | |
2120 | * Because of that, we cannot configure the IP to any | |
2121 | * speed other than the SuperSpeed | |
2122 | * | |
2123 | * Refers to: | |
2124 | * | |
2125 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
2126 | * USB 2.0 Mode | |
2127 | */ | |
2128 | if (DWC3_VER_IS_PRIOR(DWC3, 220A) && | |
2129 | !dwc->dis_metastability_quirk) { | |
2130 | reg |= DWC3_DCFG_SUPERSPEED; | |
2131 | } else { | |
450b9e9f | 2132 | switch (speed) { |
7c9a2598 WC |
2133 | case USB_SPEED_FULL: |
2134 | reg |= DWC3_DCFG_FULLSPEED; | |
2135 | break; | |
2136 | case USB_SPEED_HIGH: | |
2137 | reg |= DWC3_DCFG_HIGHSPEED; | |
2138 | break; | |
2139 | case USB_SPEED_SUPER: | |
2140 | reg |= DWC3_DCFG_SUPERSPEED; | |
2141 | break; | |
2142 | case USB_SPEED_SUPER_PLUS: | |
2143 | if (DWC3_IP_IS(DWC3)) | |
2144 | reg |= DWC3_DCFG_SUPERSPEED; | |
2145 | else | |
2146 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; | |
2147 | break; | |
2148 | default: | |
450b9e9f | 2149 | dev_err(dwc->dev, "invalid speed (%d)\n", speed); |
7c9a2598 WC |
2150 | |
2151 | if (DWC3_IP_IS(DWC3)) | |
2152 | reg |= DWC3_DCFG_SUPERSPEED; | |
2153 | else | |
2154 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; | |
2155 | } | |
2156 | } | |
f551037c TN |
2157 | |
2158 | if (DWC3_IP_IS(DWC32) && | |
450b9e9f TN |
2159 | speed > USB_SPEED_UNKNOWN && |
2160 | speed < USB_SPEED_SUPER_PLUS) | |
f551037c TN |
2161 | reg &= ~DWC3_DCFG_NUMLANES(~0); |
2162 | ||
7c9a2598 WC |
2163 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
2164 | } | |
2165 | ||
7b2a0368 | 2166 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) |
72246da4 FB |
2167 | { |
2168 | u32 reg; | |
61d58242 | 2169 | u32 timeout = 500; |
72246da4 | 2170 | |
fc8bb91b FB |
2171 | if (pm_runtime_suspended(dwc->dev)) |
2172 | return 0; | |
2173 | ||
72246da4 | 2174 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
8db7ed15 | 2175 | if (is_on) { |
9af21dd6 | 2176 | if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) { |
802fde98 PZ |
2177 | reg &= ~DWC3_DCTL_TRGTULST_MASK; |
2178 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
2179 | } | |
2180 | ||
9af21dd6 | 2181 | if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) |
802fde98 PZ |
2182 | reg &= ~DWC3_DCTL_KEEP_CONNECT; |
2183 | reg |= DWC3_DCTL_RUN_STOP; | |
7b2a0368 FB |
2184 | |
2185 | if (dwc->has_hibernation) | |
2186 | reg |= DWC3_DCTL_KEEP_CONNECT; | |
2187 | ||
7c9a2598 | 2188 | __dwc3_gadget_set_speed(dwc); |
9fcb3bd8 | 2189 | dwc->pullups_connected = true; |
8db7ed15 | 2190 | } else { |
72246da4 | 2191 | reg &= ~DWC3_DCTL_RUN_STOP; |
7b2a0368 FB |
2192 | |
2193 | if (dwc->has_hibernation && !suspend) | |
2194 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
2195 | ||
9fcb3bd8 | 2196 | dwc->pullups_connected = false; |
8db7ed15 | 2197 | } |
72246da4 | 2198 | |
5b738211 | 2199 | dwc3_gadget_dctl_write_safe(dwc, reg); |
72246da4 FB |
2200 | |
2201 | do { | |
2202 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
b6d4e16e FB |
2203 | reg &= DWC3_DSTS_DEVCTRLHLT; |
2204 | } while (--timeout && !(!is_on ^ !reg)); | |
f2df679b FB |
2205 | |
2206 | if (!timeout) | |
2207 | return -ETIMEDOUT; | |
72246da4 | 2208 | |
6f17f74b | 2209 | return 0; |
72246da4 FB |
2210 | } |
2211 | ||
ae7e8610 WC |
2212 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc); |
2213 | static void __dwc3_gadget_stop(struct dwc3 *dwc); | |
a1383b35 | 2214 | static int __dwc3_gadget_start(struct dwc3 *dwc); |
ae7e8610 | 2215 | |
72246da4 FB |
2216 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) |
2217 | { | |
2218 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2219 | unsigned long flags; | |
6f17f74b | 2220 | int ret; |
72246da4 FB |
2221 | |
2222 | is_on = !!is_on; | |
2223 | ||
bb014736 BW |
2224 | /* |
2225 | * Per databook, when we want to stop the gadget, if a control transfer | |
2226 | * is still in process, complete it and get the core into setup phase. | |
2227 | */ | |
2228 | if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) { | |
2229 | reinit_completion(&dwc->ep0_in_setup); | |
2230 | ||
2231 | ret = wait_for_completion_timeout(&dwc->ep0_in_setup, | |
2232 | msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT)); | |
2233 | if (ret == 0) { | |
2234 | dev_err(dwc->dev, "timed out waiting for SETUP phase\n"); | |
2235 | return -ETIMEDOUT; | |
2236 | } | |
2237 | } | |
2238 | ||
77adb8bd WC |
2239 | /* |
2240 | * Check the return value for successful resume, or error. For a | |
2241 | * successful resume, the DWC3 runtime PM resume routine will handle | |
2242 | * the run stop sequence, so avoid duplicate operations here. | |
2243 | */ | |
2244 | ret = pm_runtime_get_sync(dwc->dev); | |
2245 | if (!ret || ret < 0) { | |
2246 | pm_runtime_put(dwc->dev); | |
2247 | return 0; | |
2248 | } | |
2249 | ||
ae7e8610 WC |
2250 | /* |
2251 | * Synchronize any pending event handling before executing the controller | |
2252 | * halt routine. | |
2253 | */ | |
2254 | if (!is_on) { | |
2255 | dwc3_gadget_disable_irq(dwc); | |
2256 | synchronize_irq(dwc->irq_gadget); | |
2257 | } | |
2258 | ||
72246da4 | 2259 | spin_lock_irqsave(&dwc->lock, flags); |
ae7e8610 WC |
2260 | |
2261 | if (!is_on) { | |
2262 | u32 count; | |
2263 | ||
f09ddcfc | 2264 | dwc->connected = false; |
ae7e8610 WC |
2265 | /* |
2266 | * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a | |
2267 | * Section 4.1.8 Table 4-7, it states that for a device-initiated | |
2268 | * disconnect, the SW needs to ensure that it sends "a DEPENDXFER | |
2269 | * command for any active transfers" before clearing the RunStop | |
2270 | * bit. | |
2271 | */ | |
2272 | dwc3_stop_active_transfers(dwc); | |
2273 | __dwc3_gadget_stop(dwc); | |
2274 | ||
2275 | /* | |
2276 | * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a | |
2277 | * Section 1.3.4, it mentions that for the DEVCTRLHLT bit, the | |
2278 | * "software needs to acknowledge the events that are generated | |
2279 | * (by writing to GEVNTCOUNTn) while it is waiting for this bit | |
2280 | * to be set to '1'." | |
2281 | */ | |
2282 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); | |
2283 | count &= DWC3_GEVNTCOUNT_MASK; | |
2284 | if (count > 0) { | |
2285 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count); | |
2286 | dwc->ev_buf->lpos = (dwc->ev_buf->lpos + count) % | |
2287 | dwc->ev_buf->length; | |
2288 | } | |
a1383b35 WC |
2289 | } else { |
2290 | __dwc3_gadget_start(dwc); | |
ae7e8610 WC |
2291 | } |
2292 | ||
7b2a0368 | 2293 | ret = dwc3_gadget_run_stop(dwc, is_on, false); |
72246da4 | 2294 | spin_unlock_irqrestore(&dwc->lock, flags); |
77adb8bd | 2295 | pm_runtime_put(dwc->dev); |
72246da4 | 2296 | |
6f17f74b | 2297 | return ret; |
72246da4 FB |
2298 | } |
2299 | ||
8698e2ac FB |
2300 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
2301 | { | |
2302 | u32 reg; | |
2303 | ||
2304 | /* Enable all but Start and End of Frame IRQs */ | |
132ee0da | 2305 | reg = (DWC3_DEVTEN_EVNTOVERFLOWEN | |
8698e2ac FB |
2306 | DWC3_DEVTEN_CMDCMPLTEN | |
2307 | DWC3_DEVTEN_ERRTICERREN | | |
2308 | DWC3_DEVTEN_WKUPEVTEN | | |
8698e2ac FB |
2309 | DWC3_DEVTEN_CONNECTDONEEN | |
2310 | DWC3_DEVTEN_USBRSTEN | | |
2311 | DWC3_DEVTEN_DISCONNEVTEN); | |
2312 | ||
9af21dd6 | 2313 | if (DWC3_VER_IS_PRIOR(DWC3, 250A)) |
799e9dc8 FB |
2314 | reg |= DWC3_DEVTEN_ULSTCNGEN; |
2315 | ||
8698e2ac FB |
2316 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); |
2317 | } | |
2318 | ||
2319 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
2320 | { | |
2321 | /* mask all interrupts */ | |
2322 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
2323 | } | |
2324 | ||
2325 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 2326 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 2327 | |
4e99472b | 2328 | /** |
bfad65ee FB |
2329 | * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG |
2330 | * @dwc: pointer to our context structure | |
4e99472b FB |
2331 | * |
2332 | * The following looks like complex but it's actually very simple. In order to | |
2333 | * calculate the number of packets we can burst at once on OUT transfers, we're | |
2334 | * gonna use RxFIFO size. | |
2335 | * | |
2336 | * To calculate RxFIFO size we need two numbers: | |
2337 | * MDWIDTH = size, in bits, of the internal memory bus | |
2338 | * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits) | |
2339 | * | |
2340 | * Given these two numbers, the formula is simple: | |
2341 | * | |
2342 | * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16; | |
2343 | * | |
2344 | * 24 bytes is for 3x SETUP packets | |
2345 | * 16 bytes is a clock domain crossing tolerance | |
2346 | * | |
2347 | * Given RxFIFO Size, NUMP = RxFIFOSize / 1024; | |
2348 | */ | |
2349 | static void dwc3_gadget_setup_nump(struct dwc3 *dwc) | |
2350 | { | |
2351 | u32 ram2_depth; | |
2352 | u32 mdwidth; | |
2353 | u32 nump; | |
2354 | u32 reg; | |
2355 | ||
2356 | ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7); | |
d00be779 | 2357 | mdwidth = dwc3_mdwidth(dwc); |
4e99472b FB |
2358 | |
2359 | nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024; | |
2360 | nump = min_t(u32, nump, 16); | |
2361 | ||
2362 | /* update NumP */ | |
2363 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2364 | reg &= ~DWC3_DCFG_NUMP_MASK; | |
2365 | reg |= nump << DWC3_DCFG_NUMP_SHIFT; | |
2366 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2367 | } | |
2368 | ||
d7be2952 | 2369 | static int __dwc3_gadget_start(struct dwc3 *dwc) |
72246da4 | 2370 | { |
72246da4 | 2371 | struct dwc3_ep *dep; |
72246da4 FB |
2372 | int ret = 0; |
2373 | u32 reg; | |
2374 | ||
cf40b86b JY |
2375 | /* |
2376 | * Use IMOD if enabled via dwc->imod_interval. Otherwise, if | |
2377 | * the core supports IMOD, disable it. | |
2378 | */ | |
2379 | if (dwc->imod_interval) { | |
2380 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); | |
2381 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); | |
2382 | } else if (dwc3_has_imod(dwc)) { | |
2383 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0); | |
2384 | } | |
2385 | ||
2a58f9c1 FB |
2386 | /* |
2387 | * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP | |
2388 | * field instead of letting dwc3 itself calculate that automatically. | |
2389 | * | |
2390 | * This way, we maximize the chances that we'll be able to get several | |
2391 | * bursts of data without going through any sort of endpoint throttling. | |
2392 | */ | |
2393 | reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); | |
9af21dd6 | 2394 | if (DWC3_IP_IS(DWC3)) |
01b0e2cc | 2395 | reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL; |
9af21dd6 TN |
2396 | else |
2397 | reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL; | |
01b0e2cc | 2398 | |
2a58f9c1 FB |
2399 | dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); |
2400 | ||
4e99472b FB |
2401 | dwc3_gadget_setup_nump(dwc); |
2402 | ||
e66bbfb0 TN |
2403 | /* |
2404 | * Currently the controller handles single stream only. So, Ignore | |
2405 | * Packet Pending bit for stream selection and don't search for another | |
2406 | * stream if the host sends Data Packet with PP=0 (for OUT direction) or | |
2407 | * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves | |
2408 | * the stream performance. | |
2409 | */ | |
2410 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2411 | reg |= DWC3_DCFG_IGNSTRMPP; | |
2412 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2413 | ||
72246da4 FB |
2414 | /* Start with SuperSpeed Default */ |
2415 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
2416 | ||
2417 | dep = dwc->eps[0]; | |
a2d23f08 | 2418 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
2419 | if (ret) { |
2420 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 2421 | goto err0; |
72246da4 FB |
2422 | } |
2423 | ||
2424 | dep = dwc->eps[1]; | |
a2d23f08 | 2425 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
2426 | if (ret) { |
2427 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 2428 | goto err1; |
72246da4 FB |
2429 | } |
2430 | ||
2431 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 2432 | dwc->ep0state = EP0_SETUP_PHASE; |
88b1bb1f | 2433 | dwc->link_state = DWC3_LINK_STATE_SS_DIS; |
72246da4 FB |
2434 | dwc3_ep0_out_start(dwc); |
2435 | ||
8698e2ac FB |
2436 | dwc3_gadget_enable_irq(dwc); |
2437 | ||
72246da4 FB |
2438 | return 0; |
2439 | ||
b0d7ffd4 | 2440 | err1: |
d7be2952 | 2441 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
b0d7ffd4 FB |
2442 | |
2443 | err0: | |
72246da4 FB |
2444 | return ret; |
2445 | } | |
2446 | ||
d7be2952 FB |
2447 | static int dwc3_gadget_start(struct usb_gadget *g, |
2448 | struct usb_gadget_driver *driver) | |
72246da4 FB |
2449 | { |
2450 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2451 | unsigned long flags; | |
8cf9045b | 2452 | int ret; |
8698e2ac | 2453 | int irq; |
72246da4 | 2454 | |
9522def4 | 2455 | irq = dwc->irq_gadget; |
d7be2952 FB |
2456 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, |
2457 | IRQF_SHARED, "dwc3", dwc->ev_buf); | |
2458 | if (ret) { | |
2459 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
2460 | irq, ret); | |
8cf9045b | 2461 | return ret; |
d7be2952 FB |
2462 | } |
2463 | ||
72246da4 | 2464 | spin_lock_irqsave(&dwc->lock, flags); |
d7be2952 | 2465 | dwc->gadget_driver = driver; |
d7be2952 FB |
2466 | spin_unlock_irqrestore(&dwc->lock, flags); |
2467 | ||
2468 | return 0; | |
d7be2952 | 2469 | } |
72246da4 | 2470 | |
d7be2952 FB |
2471 | static void __dwc3_gadget_stop(struct dwc3 *dwc) |
2472 | { | |
8698e2ac | 2473 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
2474 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
2475 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
d7be2952 | 2476 | } |
72246da4 | 2477 | |
d7be2952 FB |
2478 | static int dwc3_gadget_stop(struct usb_gadget *g) |
2479 | { | |
2480 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2481 | unsigned long flags; | |
72246da4 | 2482 | |
d7be2952 | 2483 | spin_lock_irqsave(&dwc->lock, flags); |
d7be2952 | 2484 | dwc->gadget_driver = NULL; |
72246da4 FB |
2485 | spin_unlock_irqrestore(&dwc->lock, flags); |
2486 | ||
3f308d17 | 2487 | free_irq(dwc->irq_gadget, dwc->ev_buf); |
b0d7ffd4 | 2488 | |
72246da4 FB |
2489 | return 0; |
2490 | } | |
802fde98 | 2491 | |
729dcffd AKV |
2492 | static void dwc3_gadget_config_params(struct usb_gadget *g, |
2493 | struct usb_dcd_config_params *params) | |
2494 | { | |
2495 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2496 | ||
54fb5ba6 TN |
2497 | params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED; |
2498 | params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED; | |
2499 | ||
2500 | /* Recommended BESL */ | |
2501 | if (!dwc->dis_enblslpm_quirk) { | |
17b63704 TN |
2502 | /* |
2503 | * If the recommended BESL baseline is 0 or if the BESL deep is | |
2504 | * less than 2, Microsoft's Windows 10 host usb stack will issue | |
2505 | * a usb reset immediately after it receives the extended BOS | |
2506 | * descriptor and the enumeration will fail. To maintain | |
2507 | * compatibility with the Windows' usb stack, let's set the | |
2508 | * recommended BESL baseline to 1 and clamp the BESL deep to be | |
2509 | * within 2 to 15. | |
2510 | */ | |
2511 | params->besl_baseline = 1; | |
54fb5ba6 | 2512 | if (dwc->is_utmi_l1_suspend) |
17b63704 TN |
2513 | params->besl_deep = |
2514 | clamp_t(u8, dwc->hird_threshold, 2, 15); | |
54fb5ba6 TN |
2515 | } |
2516 | ||
729dcffd AKV |
2517 | /* U1 Device exit Latency */ |
2518 | if (dwc->dis_u1_entry_quirk) | |
2519 | params->bU1devExitLat = 0; | |
2520 | else | |
2521 | params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT; | |
2522 | ||
2523 | /* U2 Device exit Latency */ | |
2524 | if (dwc->dis_u2_entry_quirk) | |
2525 | params->bU2DevExitLat = 0; | |
2526 | else | |
2527 | params->bU2DevExitLat = | |
2528 | cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT); | |
2529 | } | |
2530 | ||
7d8d0639 FB |
2531 | static void dwc3_gadget_set_speed(struct usb_gadget *g, |
2532 | enum usb_device_speed speed) | |
2533 | { | |
2534 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2535 | unsigned long flags; | |
7d8d0639 FB |
2536 | |
2537 | spin_lock_irqsave(&dwc->lock, flags); | |
7c9a2598 | 2538 | dwc->gadget_max_speed = speed; |
7d8d0639 FB |
2539 | spin_unlock_irqrestore(&dwc->lock, flags); |
2540 | } | |
2541 | ||
072cab8a TN |
2542 | static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g, |
2543 | enum usb_ssp_rate rate) | |
2544 | { | |
2545 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2546 | unsigned long flags; | |
2547 | ||
2548 | spin_lock_irqsave(&dwc->lock, flags); | |
cdb651b6 | 2549 | dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS; |
072cab8a TN |
2550 | dwc->gadget_ssp_rate = rate; |
2551 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2552 | } | |
2553 | ||
82c46b8e WC |
2554 | static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA) |
2555 | { | |
2556 | struct dwc3 *dwc = gadget_to_dwc(g); | |
99288de3 RC |
2557 | union power_supply_propval val = {0}; |
2558 | int ret; | |
82c46b8e WC |
2559 | |
2560 | if (dwc->usb2_phy) | |
2561 | return usb_phy_set_power(dwc->usb2_phy, mA); | |
2562 | ||
99288de3 RC |
2563 | if (!dwc->usb_psy) |
2564 | return -EOPNOTSUPP; | |
2565 | ||
8a5b5c3c | 2566 | val.intval = 1000 * mA; |
99288de3 RC |
2567 | ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val); |
2568 | ||
2569 | return ret; | |
82c46b8e WC |
2570 | } |
2571 | ||
72246da4 FB |
2572 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
2573 | .get_frame = dwc3_gadget_get_frame, | |
2574 | .wakeup = dwc3_gadget_wakeup, | |
2575 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
2576 | .pullup = dwc3_gadget_pullup, | |
2577 | .udc_start = dwc3_gadget_start, | |
2578 | .udc_stop = dwc3_gadget_stop, | |
7d8d0639 | 2579 | .udc_set_speed = dwc3_gadget_set_speed, |
072cab8a | 2580 | .udc_set_ssp_rate = dwc3_gadget_set_ssp_rate, |
729dcffd | 2581 | .get_config_params = dwc3_gadget_config_params, |
82c46b8e | 2582 | .vbus_draw = dwc3_gadget_vbus_draw, |
72246da4 FB |
2583 | }; |
2584 | ||
2585 | /* -------------------------------------------------------------------------- */ | |
2586 | ||
8f1c99cd | 2587 | static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep) |
72246da4 | 2588 | { |
8f1c99cd | 2589 | struct dwc3 *dwc = dep->dwc; |
72246da4 | 2590 | |
8f1c99cd FB |
2591 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
2592 | dep->endpoint.maxburst = 1; | |
2593 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; | |
2594 | if (!dep->direction) | |
e81a7018 | 2595 | dwc->gadget->ep0 = &dep->endpoint; |
f3bcfc7e | 2596 | |
8f1c99cd | 2597 | dep->endpoint.caps.type_control = true; |
72246da4 | 2598 | |
8f1c99cd FB |
2599 | return 0; |
2600 | } | |
72246da4 | 2601 | |
8f1c99cd FB |
2602 | static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep) |
2603 | { | |
2604 | struct dwc3 *dwc = dep->dwc; | |
d00be779 | 2605 | u32 mdwidth; |
8f1c99cd | 2606 | int size; |
72246da4 | 2607 | |
d00be779 | 2608 | mdwidth = dwc3_mdwidth(dwc); |
4244ba02 | 2609 | |
8f1c99cd FB |
2610 | /* MDWIDTH is represented in bits, we need it in bytes */ |
2611 | mdwidth /= 8; | |
6a1e3ef4 | 2612 | |
8f1c99cd | 2613 | size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1)); |
9af21dd6 | 2614 | if (DWC3_IP_IS(DWC3)) |
586f4335 | 2615 | size = DWC3_GTXFIFOSIZ_TXFDEP(size); |
9af21dd6 TN |
2616 | else |
2617 | size = DWC31_GTXFIFOSIZ_TXFDEP(size); | |
39ebb05c | 2618 | |
8f1c99cd FB |
2619 | /* FIFO Depth is in MDWDITH bytes. Multiply */ |
2620 | size *= mdwidth; | |
39ebb05c | 2621 | |
8f1c99cd | 2622 | /* |
d94ea531 TN |
2623 | * To meet performance requirement, a minimum TxFIFO size of 3x |
2624 | * MaxPacketSize is recommended for endpoints that support burst and a | |
2625 | * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't | |
2626 | * support burst. Use those numbers and we can calculate the max packet | |
2627 | * limit as below. | |
8f1c99cd | 2628 | */ |
d94ea531 TN |
2629 | if (dwc->maximum_speed >= USB_SPEED_SUPER) |
2630 | size /= 3; | |
2631 | else | |
2632 | size /= 2; | |
28781789 | 2633 | |
8f1c99cd | 2634 | usb_ep_set_maxpacket_limit(&dep->endpoint, size); |
28781789 | 2635 | |
e0a93d98 | 2636 | dep->endpoint.max_streams = 16; |
8f1c99cd FB |
2637 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
2638 | list_add_tail(&dep->endpoint.ep_list, | |
e81a7018 | 2639 | &dwc->gadget->ep_list); |
8f1c99cd FB |
2640 | dep->endpoint.caps.type_iso = true; |
2641 | dep->endpoint.caps.type_bulk = true; | |
2642 | dep->endpoint.caps.type_int = true; | |
28781789 | 2643 | |
8f1c99cd FB |
2644 | return dwc3_alloc_trb_pool(dep); |
2645 | } | |
28781789 | 2646 | |
8f1c99cd FB |
2647 | static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep) |
2648 | { | |
2649 | struct dwc3 *dwc = dep->dwc; | |
d00be779 | 2650 | u32 mdwidth; |
d94ea531 TN |
2651 | int size; |
2652 | ||
d00be779 | 2653 | mdwidth = dwc3_mdwidth(dwc); |
d94ea531 TN |
2654 | |
2655 | /* MDWIDTH is represented in bits, convert to bytes */ | |
2656 | mdwidth /= 8; | |
28781789 | 2657 | |
d94ea531 TN |
2658 | /* All OUT endpoints share a single RxFIFO space */ |
2659 | size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0)); | |
9af21dd6 | 2660 | if (DWC3_IP_IS(DWC3)) |
d94ea531 | 2661 | size = DWC3_GRXFIFOSIZ_RXFDEP(size); |
9af21dd6 TN |
2662 | else |
2663 | size = DWC31_GRXFIFOSIZ_RXFDEP(size); | |
d94ea531 TN |
2664 | |
2665 | /* FIFO depth is in MDWDITH bytes */ | |
2666 | size *= mdwidth; | |
2667 | ||
2668 | /* | |
2669 | * To meet performance requirement, a minimum recommended RxFIFO size | |
2670 | * is defined as follow: | |
2671 | * RxFIFO size >= (3 x MaxPacketSize) + | |
2672 | * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin) | |
2673 | * | |
2674 | * Then calculate the max packet limit as below. | |
2675 | */ | |
2676 | size -= (3 * 8) + 16; | |
2677 | if (size < 0) | |
2678 | size = 0; | |
2679 | else | |
2680 | size /= 3; | |
2681 | ||
2682 | usb_ep_set_maxpacket_limit(&dep->endpoint, size); | |
e0a93d98 | 2683 | dep->endpoint.max_streams = 16; |
8f1c99cd FB |
2684 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
2685 | list_add_tail(&dep->endpoint.ep_list, | |
e81a7018 | 2686 | &dwc->gadget->ep_list); |
8f1c99cd FB |
2687 | dep->endpoint.caps.type_iso = true; |
2688 | dep->endpoint.caps.type_bulk = true; | |
2689 | dep->endpoint.caps.type_int = true; | |
72246da4 | 2690 | |
8f1c99cd FB |
2691 | return dwc3_alloc_trb_pool(dep); |
2692 | } | |
72246da4 | 2693 | |
8f1c99cd FB |
2694 | static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum) |
2695 | { | |
2696 | struct dwc3_ep *dep; | |
2697 | bool direction = epnum & 1; | |
2698 | int ret; | |
2699 | u8 num = epnum >> 1; | |
25b8ff68 | 2700 | |
8f1c99cd FB |
2701 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
2702 | if (!dep) | |
2703 | return -ENOMEM; | |
2704 | ||
2705 | dep->dwc = dwc; | |
2706 | dep->number = epnum; | |
2707 | dep->direction = direction; | |
2708 | dep->regs = dwc->regs + DWC3_DEP_BASE(epnum); | |
2709 | dwc->eps[epnum] = dep; | |
d92021f6 TN |
2710 | dep->combo_num = 0; |
2711 | dep->start_cmd_status = 0; | |
8f1c99cd FB |
2712 | |
2713 | snprintf(dep->name, sizeof(dep->name), "ep%u%s", num, | |
2714 | direction ? "in" : "out"); | |
2715 | ||
2716 | dep->endpoint.name = dep->name; | |
2717 | ||
2718 | if (!(dep->number > 1)) { | |
2719 | dep->endpoint.desc = &dwc3_gadget_ep0_desc; | |
2720 | dep->endpoint.comp_desc = NULL; | |
2721 | } | |
2722 | ||
8f1c99cd FB |
2723 | if (num == 0) |
2724 | ret = dwc3_gadget_init_control_endpoint(dep); | |
2725 | else if (direction) | |
2726 | ret = dwc3_gadget_init_in_endpoint(dep); | |
2727 | else | |
2728 | ret = dwc3_gadget_init_out_endpoint(dep); | |
2729 | ||
2730 | if (ret) | |
2731 | return ret; | |
a474d3b7 | 2732 | |
8f1c99cd FB |
2733 | dep->endpoint.caps.dir_in = direction; |
2734 | dep->endpoint.caps.dir_out = !direction; | |
a474d3b7 | 2735 | |
8f1c99cd FB |
2736 | INIT_LIST_HEAD(&dep->pending_list); |
2737 | INIT_LIST_HEAD(&dep->started_list); | |
d5443bbf | 2738 | INIT_LIST_HEAD(&dep->cancelled_list); |
8f1c99cd FB |
2739 | |
2740 | return 0; | |
2741 | } | |
2742 | ||
2743 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total) | |
2744 | { | |
2745 | u8 epnum; | |
2746 | ||
e81a7018 | 2747 | INIT_LIST_HEAD(&dwc->gadget->ep_list); |
8f1c99cd FB |
2748 | |
2749 | for (epnum = 0; epnum < total; epnum++) { | |
2750 | int ret; | |
2751 | ||
2752 | ret = dwc3_gadget_init_endpoint(dwc, epnum); | |
2753 | if (ret) | |
2754 | return ret; | |
72246da4 FB |
2755 | } |
2756 | ||
2757 | return 0; | |
2758 | } | |
2759 | ||
2760 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) | |
2761 | { | |
2762 | struct dwc3_ep *dep; | |
2763 | u8 epnum; | |
2764 | ||
2765 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2766 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2767 | if (!dep) |
2768 | continue; | |
5bf8fae3 GC |
2769 | /* |
2770 | * Physical endpoints 0 and 1 are special; they form the | |
2771 | * bi-directional USB endpoint 0. | |
2772 | * | |
2773 | * For those two physical endpoints, we don't allocate a TRB | |
2774 | * pool nor do we add them the endpoints list. Due to that, we | |
2775 | * shouldn't do these two operations otherwise we would end up | |
2776 | * with all sorts of bugs when removing dwc3.ko. | |
2777 | */ | |
2778 | if (epnum != 0 && epnum != 1) { | |
2779 | dwc3_free_trb_pool(dep); | |
72246da4 | 2780 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 2781 | } |
72246da4 FB |
2782 | |
2783 | kfree(dep); | |
2784 | } | |
2785 | } | |
2786 | ||
72246da4 | 2787 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 2788 | |
8f608e8a FB |
2789 | static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep, |
2790 | struct dwc3_request *req, struct dwc3_trb *trb, | |
2791 | const struct dwc3_event_depevt *event, int status, int chain) | |
72246da4 | 2792 | { |
72246da4 | 2793 | unsigned int count; |
72246da4 | 2794 | |
dc55c67e | 2795 | dwc3_ep_inc_deq(dep); |
a9c3ca5f | 2796 | |
2c4cbe6e | 2797 | trace_dwc3_complete_trb(dep, trb); |
09fe1f8d | 2798 | req->num_trbs--; |
2c4cbe6e | 2799 | |
e5b36ae2 FB |
2800 | /* |
2801 | * If we're in the middle of series of chained TRBs and we | |
2802 | * receive a short transfer along the way, DWC3 will skip | |
2803 | * through all TRBs including the last TRB in the chain (the | |
2804 | * where CHN bit is zero. DWC3 will also avoid clearing HWO | |
2805 | * bit and SW has to do it manually. | |
2806 | * | |
2807 | * We're going to do that here to avoid problems of HW trying | |
2808 | * to use bogus TRBs for transfers. | |
2809 | */ | |
2810 | if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO)) | |
2811 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; | |
2812 | ||
6abfa0f5 TN |
2813 | /* |
2814 | * For isochronous transfers, the first TRB in a service interval must | |
2815 | * have the Isoc-First type. Track and report its interval frame number. | |
2816 | */ | |
2817 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
2818 | (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) { | |
2819 | unsigned int frame_number; | |
2820 | ||
2821 | frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl); | |
2822 | frame_number &= ~(dep->interval - 1); | |
2823 | req->request.frame_number = frame_number; | |
2824 | } | |
2825 | ||
c6267a51 | 2826 | /* |
a2841f41 TN |
2827 | * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If |
2828 | * this TRB points to the bounce buffer address, it's a MPS alignment | |
2829 | * TRB. Don't add it to req->remaining calculation. | |
c6267a51 | 2830 | */ |
a2841f41 TN |
2831 | if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) && |
2832 | trb->bph == upper_32_bits(dep->dwc->bounce_addr)) { | |
c6267a51 FB |
2833 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; |
2834 | return 1; | |
2835 | } | |
2836 | ||
e5ba5ec8 | 2837 | count = trb->size & DWC3_TRB_SIZE_MASK; |
e62c5bc5 | 2838 | req->remaining += count; |
e5ba5ec8 | 2839 | |
35b2719e FB |
2840 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
2841 | return 1; | |
2842 | ||
d80fe1b6 | 2843 | if (event->status & DEPEVT_STATUS_SHORT && !chain) |
e5ba5ec8 | 2844 | return 1; |
f99f53f2 | 2845 | |
5ee85897 AKV |
2846 | if ((trb->ctrl & DWC3_TRB_CTRL_IOC) || |
2847 | (trb->ctrl & DWC3_TRB_CTRL_LST)) | |
e5ba5ec8 | 2848 | return 1; |
f99f53f2 | 2849 | |
e5ba5ec8 PA |
2850 | return 0; |
2851 | } | |
2852 | ||
d3692953 FB |
2853 | static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep, |
2854 | struct dwc3_request *req, const struct dwc3_event_depevt *event, | |
2855 | int status) | |
2856 | { | |
2857 | struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue]; | |
2858 | struct scatterlist *sg = req->sg; | |
2859 | struct scatterlist *s; | |
2860 | unsigned int pending = req->num_pending_sgs; | |
2861 | unsigned int i; | |
2862 | int ret = 0; | |
2863 | ||
2864 | for_each_sg(sg, s, pending, i) { | |
2865 | trb = &dep->trb_pool[dep->trb_dequeue]; | |
2866 | ||
d3692953 FB |
2867 | req->sg = sg_next(s); |
2868 | req->num_pending_sgs--; | |
2869 | ||
2870 | ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req, | |
2871 | trb, event, status, true); | |
2872 | if (ret) | |
2873 | break; | |
2874 | } | |
2875 | ||
2876 | return ret; | |
2877 | } | |
2878 | ||
2879 | static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep, | |
2880 | struct dwc3_request *req, const struct dwc3_event_depevt *event, | |
2881 | int status) | |
2882 | { | |
2883 | struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue]; | |
2884 | ||
2885 | return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb, | |
2886 | event, status, false); | |
2887 | } | |
2888 | ||
e0c42ce5 FB |
2889 | static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req) |
2890 | { | |
49e0590e | 2891 | return req->num_pending_sgs == 0; |
e0c42ce5 FB |
2892 | } |
2893 | ||
f38e35dd FB |
2894 | static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep, |
2895 | const struct dwc3_event_depevt *event, | |
2896 | struct dwc3_request *req, int status) | |
2897 | { | |
2898 | int ret; | |
2899 | ||
2900 | if (req->num_pending_sgs) | |
2901 | ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event, | |
2902 | status); | |
2903 | else | |
2904 | ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event, | |
2905 | status); | |
2906 | ||
690e5c2d TN |
2907 | req->request.actual = req->request.length - req->remaining; |
2908 | ||
2909 | if (!dwc3_gadget_ep_request_completed(req)) | |
2910 | goto out; | |
2911 | ||
1a22ec64 | 2912 | if (req->needs_extra_trb) { |
f38e35dd FB |
2913 | ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event, |
2914 | status); | |
1a22ec64 | 2915 | req->needs_extra_trb = false; |
f38e35dd FB |
2916 | } |
2917 | ||
f38e35dd FB |
2918 | dwc3_gadget_giveback(dep, req, status); |
2919 | ||
2920 | out: | |
2921 | return ret; | |
2922 | } | |
2923 | ||
12a3a4ad | 2924 | static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep, |
8f608e8a | 2925 | const struct dwc3_event_depevt *event, int status) |
e5ba5ec8 | 2926 | { |
6afbdb57 FB |
2927 | struct dwc3_request *req; |
2928 | struct dwc3_request *tmp; | |
e5ba5ec8 | 2929 | |
6afbdb57 | 2930 | list_for_each_entry_safe(req, tmp, &dep->started_list, list) { |
fee73e61 | 2931 | int ret; |
e5b36ae2 | 2932 | |
f38e35dd FB |
2933 | ret = dwc3_gadget_ep_cleanup_completed_request(dep, event, |
2934 | req, status); | |
58f0218a | 2935 | if (ret) |
72246da4 | 2936 | break; |
31162af4 | 2937 | } |
72246da4 FB |
2938 | } |
2939 | ||
d9feef97 TN |
2940 | static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep) |
2941 | { | |
2942 | struct dwc3_request *req; | |
02fa4b98 WC |
2943 | struct dwc3 *dwc = dep->dwc; |
2944 | ||
2945 | if (!dep->endpoint.desc || !dwc->pullups_connected || | |
2946 | !dwc->connected) | |
2947 | return false; | |
d9feef97 TN |
2948 | |
2949 | if (!list_empty(&dep->pending_list)) | |
2950 | return true; | |
2951 | ||
2952 | /* | |
2953 | * We only need to check the first entry of the started list. We can | |
2954 | * assume the completed requests are removed from the started list. | |
2955 | */ | |
2956 | req = next_request(&dep->started_list); | |
2957 | if (!req) | |
2958 | return false; | |
2959 | ||
2960 | return !dwc3_gadget_ep_request_completed(req); | |
2961 | } | |
2962 | ||
ee3638b8 FB |
2963 | static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep, |
2964 | const struct dwc3_event_depevt *event) | |
2965 | { | |
f62afb49 | 2966 | dep->frame_number = event->parameters; |
ee3638b8 FB |
2967 | } |
2968 | ||
2e6e9e4b TN |
2969 | static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep, |
2970 | const struct dwc3_event_depevt *event, int status) | |
72246da4 | 2971 | { |
8f608e8a | 2972 | struct dwc3 *dwc = dep->dwc; |
2e6e9e4b | 2973 | bool no_started_trb = true; |
6d8a0196 | 2974 | |
5f2e7975 | 2975 | dwc3_gadget_ep_cleanup_completed_requests(dep, event, status); |
fae2b904 | 2976 | |
b6842d49 TN |
2977 | if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) |
2978 | goto out; | |
2979 | ||
f5e46aa4 MG |
2980 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && |
2981 | list_empty(&dep->started_list) && | |
2982 | (list_empty(&dep->pending_list) || status == -EXDEV)) | |
c5353b22 | 2983 | dwc3_stop_active_transfer(dep, true, true); |
d9feef97 | 2984 | else if (dwc3_gadget_ep_should_continue(dep)) |
2e6e9e4b TN |
2985 | if (__dwc3_gadget_kick_transfer(dep) == 0) |
2986 | no_started_trb = false; | |
6d8a0196 | 2987 | |
b6842d49 | 2988 | out: |
fae2b904 FB |
2989 | /* |
2990 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
2991 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
2992 | */ | |
9af21dd6 | 2993 | if (DWC3_VER_IS_PRIOR(DWC3, 183A)) { |
fae2b904 FB |
2994 | u32 reg; |
2995 | int i; | |
2996 | ||
2997 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 2998 | dep = dwc->eps[i]; |
fae2b904 FB |
2999 | |
3000 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
3001 | continue; | |
3002 | ||
aa3342c8 | 3003 | if (!list_empty(&dep->started_list)) |
2e6e9e4b | 3004 | return no_started_trb; |
fae2b904 FB |
3005 | } |
3006 | ||
3007 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3008 | reg |= dwc->u1u2; | |
3009 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
3010 | ||
3011 | dwc->u1u2 = 0; | |
3012 | } | |
2e6e9e4b TN |
3013 | |
3014 | return no_started_trb; | |
3015 | } | |
3016 | ||
3017 | static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep, | |
3018 | const struct dwc3_event_depevt *event) | |
3019 | { | |
3020 | int status = 0; | |
3021 | ||
3022 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
3023 | dwc3_gadget_endpoint_frame_from_event(dep, event); | |
3024 | ||
3025 | if (event->status & DEPEVT_STATUS_BUSERR) | |
3026 | status = -ECONNRESET; | |
3027 | ||
3028 | if (event->status & DEPEVT_STATUS_MISSED_ISOC) | |
3029 | status = -EXDEV; | |
3030 | ||
3031 | dwc3_gadget_endpoint_trbs_complete(dep, event, status); | |
72246da4 FB |
3032 | } |
3033 | ||
3eaecd0c TN |
3034 | static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep, |
3035 | const struct dwc3_event_depevt *event) | |
3036 | { | |
3037 | int status = 0; | |
3038 | ||
3039 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; | |
3040 | ||
3041 | if (event->status & DEPEVT_STATUS_BUSERR) | |
3042 | status = -ECONNRESET; | |
3043 | ||
e0d19563 TN |
3044 | if (dwc3_gadget_endpoint_trbs_complete(dep, event, status)) |
3045 | dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE; | |
72246da4 FB |
3046 | } |
3047 | ||
8f608e8a FB |
3048 | static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep, |
3049 | const struct dwc3_event_depevt *event) | |
32033865 | 3050 | { |
ee3638b8 | 3051 | dwc3_gadget_endpoint_frame_from_event(dep, event); |
36f05d36 TN |
3052 | |
3053 | /* | |
3054 | * The XferNotReady event is generated only once before the endpoint | |
3055 | * starts. It will be generated again when END_TRANSFER command is | |
3056 | * issued. For some controller versions, the XferNotReady event may be | |
3057 | * generated while the END_TRANSFER command is still in process. Ignore | |
3058 | * it and wait for the next XferNotReady event after the command is | |
3059 | * completed. | |
3060 | */ | |
3061 | if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) | |
3062 | return; | |
3063 | ||
25abad6a | 3064 | (void) __dwc3_gadget_start_isoc(dep); |
32033865 FB |
3065 | } |
3066 | ||
8266b08e TN |
3067 | static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep, |
3068 | const struct dwc3_event_depevt *event) | |
3069 | { | |
3070 | u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters); | |
3071 | ||
3072 | if (cmd != DWC3_DEPCMD_ENDTRANSFER) | |
3073 | return; | |
3074 | ||
3075 | dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; | |
3076 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; | |
3077 | dwc3_gadget_ep_cleanup_cancelled_requests(dep); | |
3078 | ||
3079 | if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) { | |
3080 | struct dwc3 *dwc = dep->dwc; | |
3081 | ||
3082 | dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL; | |
3083 | if (dwc3_send_clear_stall_ep_cmd(dep)) { | |
3084 | struct usb_ep *ep0 = &dwc->eps[0]->endpoint; | |
3085 | ||
3086 | dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name); | |
3087 | if (dwc->delayed_status) | |
3088 | __dwc3_gadget_ep0_set_halt(ep0, 1); | |
3089 | return; | |
3090 | } | |
3091 | ||
3092 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); | |
3093 | if (dwc->delayed_status) | |
3094 | dwc3_ep0_send_delayed_status(dwc); | |
3095 | } | |
3096 | ||
3097 | if ((dep->flags & DWC3_EP_DELAY_START) && | |
3098 | !usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
3099 | __dwc3_gadget_kick_transfer(dep); | |
3100 | ||
3101 | dep->flags &= ~DWC3_EP_DELAY_START; | |
3102 | } | |
3103 | ||
140ca4cf TN |
3104 | static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep, |
3105 | const struct dwc3_event_depevt *event) | |
3106 | { | |
3107 | struct dwc3 *dwc = dep->dwc; | |
3108 | ||
3109 | if (event->status == DEPEVT_STREAMEVT_FOUND) { | |
3110 | dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED; | |
3111 | goto out; | |
3112 | } | |
3113 | ||
3114 | /* Note: NoStream rejection event param value is 0 and not 0xFFFF */ | |
3115 | switch (event->parameters) { | |
3116 | case DEPEVT_STREAM_PRIME: | |
3117 | /* | |
3118 | * If the host can properly transition the endpoint state from | |
3119 | * idle to prime after a NoStream rejection, there's no need to | |
3120 | * force restarting the endpoint to reinitiate the stream. To | |
3121 | * simplify the check, assume the host follows the USB spec if | |
3122 | * it primed the endpoint more than once. | |
3123 | */ | |
3124 | if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) { | |
3125 | if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED) | |
3126 | dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM; | |
3127 | else | |
3128 | dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED; | |
3129 | } | |
3130 | ||
3131 | break; | |
3132 | case DEPEVT_STREAM_NOSTREAM: | |
3133 | if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) || | |
3134 | !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) || | |
3135 | !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)) | |
3136 | break; | |
3137 | ||
3138 | /* | |
3139 | * If the host rejects a stream due to no active stream, by the | |
3140 | * USB and xHCI spec, the endpoint will be put back to idle | |
3141 | * state. When the host is ready (buffer added/updated), it will | |
3142 | * prime the endpoint to inform the usb device controller. This | |
3143 | * triggers the device controller to issue ERDY to restart the | |
3144 | * stream. However, some hosts don't follow this and keep the | |
3145 | * endpoint in the idle state. No prime will come despite host | |
3146 | * streams are updated, and the device controller will not be | |
3147 | * triggered to generate ERDY to move the next stream data. To | |
3148 | * workaround this and maintain compatibility with various | |
3149 | * hosts, force to reinitate the stream until the host is ready | |
3150 | * instead of waiting for the host to prime the endpoint. | |
3151 | */ | |
b10e1c25 TN |
3152 | if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) { |
3153 | unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME; | |
3154 | ||
3155 | dwc3_send_gadget_generic_command(dwc, cmd, dep->number); | |
3156 | } else { | |
3157 | dep->flags |= DWC3_EP_DELAY_START; | |
3158 | dwc3_stop_active_transfer(dep, true, true); | |
3159 | return; | |
3160 | } | |
3161 | break; | |
140ca4cf TN |
3162 | } |
3163 | ||
3164 | out: | |
3165 | dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM; | |
3166 | } | |
3167 | ||
72246da4 FB |
3168 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
3169 | const struct dwc3_event_depevt *event) | |
3170 | { | |
3171 | struct dwc3_ep *dep; | |
3172 | u8 epnum = event->endpoint_number; | |
3173 | ||
3174 | dep = dwc->eps[epnum]; | |
3175 | ||
d7fd41c6 | 3176 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
3aec9915 | 3177 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) |
d7fd41c6 JD |
3178 | return; |
3179 | ||
3180 | /* Handle only EPCMDCMPLT when EP disabled */ | |
3181 | if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT) | |
3182 | return; | |
3183 | } | |
3336abb5 | 3184 | |
72246da4 FB |
3185 | if (epnum == 0 || epnum == 1) { |
3186 | dwc3_ep0_interrupt(dwc, event); | |
3187 | return; | |
3188 | } | |
3189 | ||
3190 | switch (event->endpoint_event) { | |
72246da4 | 3191 | case DWC3_DEPEVT_XFERINPROGRESS: |
8f608e8a | 3192 | dwc3_gadget_endpoint_transfer_in_progress(dep, event); |
72246da4 FB |
3193 | break; |
3194 | case DWC3_DEPEVT_XFERNOTREADY: | |
8f608e8a | 3195 | dwc3_gadget_endpoint_transfer_not_ready(dep, event); |
879631aa | 3196 | break; |
72246da4 | 3197 | case DWC3_DEPEVT_EPCMDCMPLT: |
8266b08e | 3198 | dwc3_gadget_endpoint_command_complete(dep, event); |
76a638f8 | 3199 | break; |
742a4fff | 3200 | case DWC3_DEPEVT_XFERCOMPLETE: |
3eaecd0c TN |
3201 | dwc3_gadget_endpoint_transfer_complete(dep, event); |
3202 | break; | |
3203 | case DWC3_DEPEVT_STREAMEVT: | |
140ca4cf TN |
3204 | dwc3_gadget_endpoint_stream_event(dep, event); |
3205 | break; | |
76a638f8 | 3206 | case DWC3_DEPEVT_RXTXFIFOEVT: |
72246da4 FB |
3207 | break; |
3208 | } | |
3209 | } | |
3210 | ||
3211 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
3212 | { | |
3213 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
3214 | spin_unlock(&dwc->lock); | |
e81a7018 | 3215 | dwc->gadget_driver->disconnect(dwc->gadget); |
72246da4 FB |
3216 | spin_lock(&dwc->lock); |
3217 | } | |
3218 | } | |
3219 | ||
bc5ba2e0 FB |
3220 | static void dwc3_suspend_gadget(struct dwc3 *dwc) |
3221 | { | |
73a30bfc | 3222 | if (dwc->gadget_driver && dwc->gadget_driver->suspend) { |
bc5ba2e0 | 3223 | spin_unlock(&dwc->lock); |
e81a7018 | 3224 | dwc->gadget_driver->suspend(dwc->gadget); |
bc5ba2e0 FB |
3225 | spin_lock(&dwc->lock); |
3226 | } | |
3227 | } | |
3228 | ||
3229 | static void dwc3_resume_gadget(struct dwc3 *dwc) | |
3230 | { | |
73a30bfc | 3231 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
bc5ba2e0 | 3232 | spin_unlock(&dwc->lock); |
e81a7018 | 3233 | dwc->gadget_driver->resume(dwc->gadget); |
5c7b3b02 | 3234 | spin_lock(&dwc->lock); |
8e74475b FB |
3235 | } |
3236 | } | |
3237 | ||
3238 | static void dwc3_reset_gadget(struct dwc3 *dwc) | |
3239 | { | |
3240 | if (!dwc->gadget_driver) | |
3241 | return; | |
3242 | ||
e81a7018 | 3243 | if (dwc->gadget->speed != USB_SPEED_UNKNOWN) { |
8e74475b | 3244 | spin_unlock(&dwc->lock); |
e81a7018 | 3245 | usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver); |
bc5ba2e0 FB |
3246 | spin_lock(&dwc->lock); |
3247 | } | |
3248 | } | |
3249 | ||
c5353b22 FB |
3250 | static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, |
3251 | bool interrupt) | |
72246da4 | 3252 | { |
72246da4 FB |
3253 | struct dwc3_gadget_ep_cmd_params params; |
3254 | u32 cmd; | |
3255 | int ret; | |
3256 | ||
c58d8bfc TN |
3257 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) || |
3258 | (dep->flags & DWC3_EP_END_TRANSFER_PENDING)) | |
3daf74d7 PA |
3259 | return; |
3260 | ||
57911504 PA |
3261 | /* |
3262 | * NOTICE: We are violating what the Databook says about the | |
3263 | * EndTransfer command. Ideally we would _always_ wait for the | |
3264 | * EndTransfer Command Completion IRQ, but that's causing too | |
3265 | * much trouble synchronizing between us and gadget driver. | |
3266 | * | |
3267 | * We have discussed this with the IP Provider and it was | |
cf2f8b63 | 3268 | * suggested to giveback all requests here. |
57911504 PA |
3269 | * |
3270 | * Note also that a similar handling was tested by Synopsys | |
3271 | * (thanks a lot Paul) and nothing bad has come out of it. | |
cf2f8b63 TN |
3272 | * In short, what we're doing is issuing EndTransfer with |
3273 | * CMDIOC bit set and delay kicking transfer until the | |
3274 | * EndTransfer command had completed. | |
06281d46 JY |
3275 | * |
3276 | * As of IP version 3.10a of the DWC_usb3 IP, the controller | |
3277 | * supports a mode to work around the above limitation. The | |
3278 | * software can poll the CMDACT bit in the DEPCMD register | |
3279 | * after issuing a EndTransfer command. This mode is enabled | |
3280 | * by writing GUCTL2[14]. This polling is already done in the | |
3281 | * dwc3_send_gadget_ep_cmd() function so if the mode is | |
3282 | * enabled, the EndTransfer command will have completed upon | |
cf2f8b63 | 3283 | * returning from this function. |
06281d46 JY |
3284 | * |
3285 | * This mode is NOT available on the DWC_usb31 IP. | |
57911504 PA |
3286 | */ |
3287 | ||
3daf74d7 | 3288 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
b992e681 | 3289 | cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; |
c5353b22 | 3290 | cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0; |
b4996a86 | 3291 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 | 3292 | memset(¶ms, 0, sizeof(params)); |
2cd4718d | 3293 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
3daf74d7 | 3294 | WARN_ON_ONCE(ret); |
b4996a86 | 3295 | dep->resource_index = 0; |
06281d46 | 3296 | |
140ca4cf TN |
3297 | /* |
3298 | * The END_TRANSFER command will cause the controller to generate a | |
3299 | * NoStream Event, and it's not due to the host DP NoStream rejection. | |
3300 | * Ignore the next NoStream event. | |
3301 | */ | |
3302 | if (dep->stream_capable) | |
3303 | dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM; | |
3304 | ||
d3abda5a TN |
3305 | if (!interrupt) |
3306 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; | |
c58d8bfc TN |
3307 | else |
3308 | dep->flags |= DWC3_EP_END_TRANSFER_PENDING; | |
72246da4 FB |
3309 | } |
3310 | ||
72246da4 FB |
3311 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) |
3312 | { | |
3313 | u32 epnum; | |
3314 | ||
3315 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
3316 | struct dwc3_ep *dep; | |
72246da4 FB |
3317 | int ret; |
3318 | ||
3319 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
3320 | if (!dep) |
3321 | continue; | |
72246da4 FB |
3322 | |
3323 | if (!(dep->flags & DWC3_EP_STALL)) | |
3324 | continue; | |
3325 | ||
3326 | dep->flags &= ~DWC3_EP_STALL; | |
3327 | ||
50c763f8 | 3328 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 FB |
3329 | WARN_ON_ONCE(ret); |
3330 | } | |
3331 | } | |
3332 | ||
3333 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
3334 | { | |
c4430a26 FB |
3335 | int reg; |
3336 | ||
1b6009ea TN |
3337 | dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET); |
3338 | ||
72246da4 FB |
3339 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
3340 | reg &= ~DWC3_DCTL_INITU1ENA; | |
72246da4 | 3341 | reg &= ~DWC3_DCTL_INITU2ENA; |
5b738211 | 3342 | dwc3_gadget_dctl_write_safe(dwc, reg); |
72246da4 | 3343 | |
72246da4 FB |
3344 | dwc3_disconnect_gadget(dwc); |
3345 | ||
e81a7018 | 3346 | dwc->gadget->speed = USB_SPEED_UNKNOWN; |
df62df56 | 3347 | dwc->setup_packet_pending = false; |
e81a7018 | 3348 | usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED); |
fc8bb91b FB |
3349 | |
3350 | dwc->connected = false; | |
72246da4 FB |
3351 | } |
3352 | ||
72246da4 FB |
3353 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
3354 | { | |
3355 | u32 reg; | |
3356 | ||
71ca43f3 WC |
3357 | /* |
3358 | * Ideally, dwc3_reset_gadget() would trigger the function | |
3359 | * drivers to stop any active transfers through ep disable. | |
3360 | * However, for functions which defer ep disable, such as mass | |
3361 | * storage, we will need to rely on the call to stop active | |
3362 | * transfers here, and avoid allowing of request queuing. | |
3363 | */ | |
3364 | dwc->connected = false; | |
3365 | ||
df62df56 FB |
3366 | /* |
3367 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
3368 | * would cause a missing Disconnect Event if there's a | |
3369 | * pending Setup Packet in the FIFO. | |
3370 | * | |
3371 | * There's no suggested workaround on the official Bug | |
3372 | * report, which states that "unless the driver/application | |
3373 | * is doing any special handling of a disconnect event, | |
3374 | * there is no functional issue". | |
3375 | * | |
3376 | * Unfortunately, it turns out that we _do_ some special | |
3377 | * handling of a disconnect event, namely complete all | |
3378 | * pending transfers, notify gadget driver of the | |
3379 | * disconnection, and so on. | |
3380 | * | |
3381 | * Our suggested workaround is to follow the Disconnect | |
3382 | * Event steps here, instead, based on a setup_packet_pending | |
b5d335e5 FB |
3383 | * flag. Such flag gets set whenever we have a SETUP_PENDING |
3384 | * status for EP0 TRBs and gets cleared on XferComplete for the | |
df62df56 FB |
3385 | * same endpoint. |
3386 | * | |
3387 | * Refers to: | |
3388 | * | |
3389 | * STAR#9000466709: RTL: Device : Disconnect event not | |
3390 | * generated if setup packet pending in FIFO | |
3391 | */ | |
9af21dd6 | 3392 | if (DWC3_VER_IS_PRIOR(DWC3, 188A)) { |
df62df56 FB |
3393 | if (dwc->setup_packet_pending) |
3394 | dwc3_gadget_disconnect_interrupt(dwc); | |
3395 | } | |
3396 | ||
8e74475b | 3397 | dwc3_reset_gadget(dwc); |
ae7e8610 WC |
3398 | /* |
3399 | * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a | |
3400 | * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW | |
3401 | * needs to ensure that it sends "a DEPENDXFER command for any active | |
3402 | * transfers." | |
3403 | */ | |
3404 | dwc3_stop_active_transfers(dwc); | |
f09ddcfc | 3405 | dwc->connected = true; |
72246da4 FB |
3406 | |
3407 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3408 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
5b738211 | 3409 | dwc3_gadget_dctl_write_safe(dwc, reg); |
3b637367 | 3410 | dwc->test_mode = false; |
72246da4 FB |
3411 | dwc3_clear_stall_all_ep(dwc); |
3412 | ||
3413 | /* Reset device address to zero */ | |
3414 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
3415 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
3416 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
3417 | } |
3418 | ||
72246da4 FB |
3419 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
3420 | { | |
72246da4 FB |
3421 | struct dwc3_ep *dep; |
3422 | int ret; | |
3423 | u32 reg; | |
f551037c | 3424 | u8 lanes = 1; |
72246da4 FB |
3425 | u8 speed; |
3426 | ||
72246da4 FB |
3427 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
3428 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
3429 | dwc->speed = speed; | |
3430 | ||
f551037c TN |
3431 | if (DWC3_IP_IS(DWC32)) |
3432 | lanes = DWC3_DSTS_CONNLANES(reg) + 1; | |
3433 | ||
3434 | dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN; | |
3435 | ||
5fb6fdaf JY |
3436 | /* |
3437 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
3438 | * each time on Connect Done. | |
3439 | * | |
3440 | * Currently we always use the reset value. If any platform | |
3441 | * wants to set this to a different value, we need to add a | |
3442 | * setting and update GCTL.RAMCLKSEL here. | |
3443 | */ | |
72246da4 FB |
3444 | |
3445 | switch (speed) { | |
2da9ad76 | 3446 | case DWC3_DSTS_SUPERSPEED_PLUS: |
7580862b | 3447 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
e81a7018 PC |
3448 | dwc->gadget->ep0->maxpacket = 512; |
3449 | dwc->gadget->speed = USB_SPEED_SUPER_PLUS; | |
f551037c TN |
3450 | |
3451 | if (lanes > 1) | |
3452 | dwc->gadget->ssp_rate = USB_SSP_GEN_2x2; | |
3453 | else | |
3454 | dwc->gadget->ssp_rate = USB_SSP_GEN_2x1; | |
7580862b | 3455 | break; |
2da9ad76 | 3456 | case DWC3_DSTS_SUPERSPEED: |
05870c5b FB |
3457 | /* |
3458 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
3459 | * would cause a missing USB3 Reset event. | |
3460 | * | |
3461 | * In such situations, we should force a USB3 Reset | |
3462 | * event by calling our dwc3_gadget_reset_interrupt() | |
3463 | * routine. | |
3464 | * | |
3465 | * Refers to: | |
3466 | * | |
3467 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
3468 | * not be generated always when the link enters poll | |
3469 | */ | |
9af21dd6 | 3470 | if (DWC3_VER_IS_PRIOR(DWC3, 190A)) |
05870c5b FB |
3471 | dwc3_gadget_reset_interrupt(dwc); |
3472 | ||
72246da4 | 3473 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
e81a7018 PC |
3474 | dwc->gadget->ep0->maxpacket = 512; |
3475 | dwc->gadget->speed = USB_SPEED_SUPER; | |
f551037c TN |
3476 | |
3477 | if (lanes > 1) { | |
3478 | dwc->gadget->speed = USB_SPEED_SUPER_PLUS; | |
3479 | dwc->gadget->ssp_rate = USB_SSP_GEN_1x2; | |
3480 | } | |
72246da4 | 3481 | break; |
2da9ad76 | 3482 | case DWC3_DSTS_HIGHSPEED: |
72246da4 | 3483 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
e81a7018 PC |
3484 | dwc->gadget->ep0->maxpacket = 64; |
3485 | dwc->gadget->speed = USB_SPEED_HIGH; | |
72246da4 | 3486 | break; |
9418ee15 | 3487 | case DWC3_DSTS_FULLSPEED: |
72246da4 | 3488 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
e81a7018 PC |
3489 | dwc->gadget->ep0->maxpacket = 64; |
3490 | dwc->gadget->speed = USB_SPEED_FULL; | |
72246da4 | 3491 | break; |
72246da4 FB |
3492 | } |
3493 | ||
e81a7018 | 3494 | dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket; |
61800263 | 3495 | |
2b758350 PA |
3496 | /* Enable USB2 LPM Capability */ |
3497 | ||
9af21dd6 | 3498 | if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) && |
475e8be5 | 3499 | !dwc->usb2_gadget_lpm_disable && |
2da9ad76 JY |
3500 | (speed != DWC3_DSTS_SUPERSPEED) && |
3501 | (speed != DWC3_DSTS_SUPERSPEED_PLUS)) { | |
2b758350 PA |
3502 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
3503 | reg |= DWC3_DCFG_LPM_CAP; | |
3504 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
3505 | ||
3506 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3507 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
3508 | ||
16fe4f30 TN |
3509 | reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold | |
3510 | (dwc->is_utmi_l1_suspend << 4)); | |
2b758350 | 3511 | |
80caf7d2 HR |
3512 | /* |
3513 | * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and | |
3514 | * DCFG.LPMCap is set, core responses with an ACK and the | |
3515 | * BESL value in the LPM token is less than or equal to LPM | |
3516 | * NYET threshold. | |
3517 | */ | |
9af21dd6 | 3518 | WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum, |
9165dabb | 3519 | "LPM Erratum not available on dwc3 revisions < 2.40a\n"); |
80caf7d2 | 3520 | |
9af21dd6 | 3521 | if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A)) |
2e487d28 | 3522 | reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold); |
80caf7d2 | 3523 | |
5b738211 | 3524 | dwc3_gadget_dctl_write_safe(dwc, reg); |
356363bf | 3525 | } else { |
475e8be5 TN |
3526 | if (dwc->usb2_gadget_lpm_disable) { |
3527 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
3528 | reg &= ~DWC3_DCFG_LPM_CAP; | |
3529 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
3530 | } | |
3531 | ||
356363bf FB |
3532 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
3533 | reg &= ~DWC3_DCTL_HIRD_THRES_MASK; | |
5b738211 | 3534 | dwc3_gadget_dctl_write_safe(dwc, reg); |
2b758350 PA |
3535 | } |
3536 | ||
72246da4 | 3537 | dep = dwc->eps[0]; |
a2d23f08 | 3538 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY); |
72246da4 FB |
3539 | if (ret) { |
3540 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
3541 | return; | |
3542 | } | |
3543 | ||
3544 | dep = dwc->eps[1]; | |
a2d23f08 | 3545 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY); |
72246da4 FB |
3546 | if (ret) { |
3547 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
3548 | return; | |
3549 | } | |
3550 | ||
3551 | /* | |
3552 | * Configure PHY via GUSB3PIPECTLn if required. | |
3553 | * | |
3554 | * Update GTXFIFOSIZn | |
3555 | * | |
3556 | * In both cases reset values should be sufficient. | |
3557 | */ | |
3558 | } | |
3559 | ||
3560 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
3561 | { | |
72246da4 FB |
3562 | /* |
3563 | * TODO take core out of low power mode when that's | |
3564 | * implemented. | |
3565 | */ | |
3566 | ||
ad14d4e0 JL |
3567 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
3568 | spin_unlock(&dwc->lock); | |
e81a7018 | 3569 | dwc->gadget_driver->resume(dwc->gadget); |
ad14d4e0 JL |
3570 | spin_lock(&dwc->lock); |
3571 | } | |
72246da4 FB |
3572 | } |
3573 | ||
3574 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
3575 | unsigned int evtinfo) | |
3576 | { | |
fae2b904 | 3577 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
3578 | unsigned int pwropt; |
3579 | ||
3580 | /* | |
3581 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
3582 | * Hibernation mode enabled which would show up when device detects | |
3583 | * host-initiated U3 exit. | |
3584 | * | |
3585 | * In that case, device will generate a Link State Change Interrupt | |
3586 | * from U3 to RESUME which is only necessary if Hibernation is | |
3587 | * configured in. | |
3588 | * | |
3589 | * There are no functional changes due to such spurious event and we | |
3590 | * just need to ignore it. | |
3591 | * | |
3592 | * Refers to: | |
3593 | * | |
3594 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
3595 | * operational mode | |
3596 | */ | |
3597 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
9af21dd6 | 3598 | if (DWC3_VER_IS_PRIOR(DWC3, 250A) && |
0b0cc1cd FB |
3599 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { |
3600 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
3601 | (next == DWC3_LINK_STATE_RESUME)) { | |
0b0cc1cd FB |
3602 | return; |
3603 | } | |
3604 | } | |
fae2b904 FB |
3605 | |
3606 | /* | |
3607 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
3608 | * on the link partner, the USB session might do multiple entry/exit | |
3609 | * of low power states before a transfer takes place. | |
3610 | * | |
3611 | * Due to this problem, we might experience lower throughput. The | |
3612 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
3613 | * transitioning from U1/U2 to U0 and enable those bits again | |
3614 | * after a transfer completes and there are no pending transfers | |
3615 | * on any of the enabled endpoints. | |
3616 | * | |
3617 | * This is the first half of that workaround. | |
3618 | * | |
3619 | * Refers to: | |
3620 | * | |
3621 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
3622 | * core send LGO_Ux entering U0 | |
3623 | */ | |
9af21dd6 | 3624 | if (DWC3_VER_IS_PRIOR(DWC3, 183A)) { |
fae2b904 FB |
3625 | if (next == DWC3_LINK_STATE_U0) { |
3626 | u32 u1u2; | |
3627 | u32 reg; | |
3628 | ||
3629 | switch (dwc->link_state) { | |
3630 | case DWC3_LINK_STATE_U1: | |
3631 | case DWC3_LINK_STATE_U2: | |
3632 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3633 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
3634 | | DWC3_DCTL_ACCEPTU2ENA | |
3635 | | DWC3_DCTL_INITU1ENA | |
3636 | | DWC3_DCTL_ACCEPTU1ENA); | |
3637 | ||
3638 | if (!dwc->u1u2) | |
3639 | dwc->u1u2 = reg & u1u2; | |
3640 | ||
3641 | reg &= ~u1u2; | |
3642 | ||
5b738211 | 3643 | dwc3_gadget_dctl_write_safe(dwc, reg); |
fae2b904 FB |
3644 | break; |
3645 | default: | |
3646 | /* do nothing */ | |
3647 | break; | |
3648 | } | |
3649 | } | |
3650 | } | |
3651 | ||
bc5ba2e0 FB |
3652 | switch (next) { |
3653 | case DWC3_LINK_STATE_U1: | |
3654 | if (dwc->speed == USB_SPEED_SUPER) | |
3655 | dwc3_suspend_gadget(dwc); | |
3656 | break; | |
3657 | case DWC3_LINK_STATE_U2: | |
3658 | case DWC3_LINK_STATE_U3: | |
3659 | dwc3_suspend_gadget(dwc); | |
3660 | break; | |
3661 | case DWC3_LINK_STATE_RESUME: | |
3662 | dwc3_resume_gadget(dwc); | |
3663 | break; | |
3664 | default: | |
3665 | /* do nothing */ | |
3666 | break; | |
3667 | } | |
3668 | ||
e57ebc1d | 3669 | dwc->link_state = next; |
72246da4 FB |
3670 | } |
3671 | ||
72704f87 BW |
3672 | static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc, |
3673 | unsigned int evtinfo) | |
3674 | { | |
3675 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; | |
3676 | ||
3677 | if (dwc->link_state != next && next == DWC3_LINK_STATE_U3) | |
3678 | dwc3_suspend_gadget(dwc); | |
3679 | ||
3680 | dwc->link_state = next; | |
3681 | } | |
3682 | ||
e1dadd3b FB |
3683 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, |
3684 | unsigned int evtinfo) | |
3685 | { | |
3686 | unsigned int is_ss = evtinfo & BIT(4); | |
3687 | ||
bfad65ee | 3688 | /* |
e1dadd3b FB |
3689 | * WORKAROUND: DWC3 revison 2.20a with hibernation support |
3690 | * have a known issue which can cause USB CV TD.9.23 to fail | |
3691 | * randomly. | |
3692 | * | |
3693 | * Because of this issue, core could generate bogus hibernation | |
3694 | * events which SW needs to ignore. | |
3695 | * | |
3696 | * Refers to: | |
3697 | * | |
3698 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
3699 | * Device Fallback from SuperSpeed | |
3700 | */ | |
3701 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
3702 | return; | |
3703 | ||
3704 | /* enter hibernation here */ | |
3705 | } | |
3706 | ||
72246da4 FB |
3707 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, |
3708 | const struct dwc3_event_devt *event) | |
3709 | { | |
3710 | switch (event->type) { | |
3711 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
3712 | dwc3_gadget_disconnect_interrupt(dwc); | |
3713 | break; | |
3714 | case DWC3_DEVICE_EVENT_RESET: | |
3715 | dwc3_gadget_reset_interrupt(dwc); | |
3716 | break; | |
3717 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
3718 | dwc3_gadget_conndone_interrupt(dwc); | |
3719 | break; | |
3720 | case DWC3_DEVICE_EVENT_WAKEUP: | |
3721 | dwc3_gadget_wakeup_interrupt(dwc); | |
3722 | break; | |
e1dadd3b FB |
3723 | case DWC3_DEVICE_EVENT_HIBER_REQ: |
3724 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
3725 | "unexpected hibernation event\n")) | |
3726 | break; | |
3727 | ||
3728 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
3729 | break; | |
72246da4 FB |
3730 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: |
3731 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
3732 | break; | |
3733 | case DWC3_DEVICE_EVENT_EOPF: | |
72704f87 | 3734 | /* It changed to be suspend event for version 2.30a and above */ |
9af21dd6 | 3735 | if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) { |
72704f87 BW |
3736 | /* |
3737 | * Ignore suspend event until the gadget enters into | |
3738 | * USB_STATE_CONFIGURED state. | |
3739 | */ | |
e81a7018 | 3740 | if (dwc->gadget->state >= USB_STATE_CONFIGURED) |
72704f87 BW |
3741 | dwc3_gadget_suspend_interrupt(dwc, |
3742 | event->event_info); | |
3743 | } | |
72246da4 FB |
3744 | break; |
3745 | case DWC3_DEVICE_EVENT_SOF: | |
72246da4 | 3746 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: |
72246da4 | 3747 | case DWC3_DEVICE_EVENT_CMD_CMPL: |
72246da4 | 3748 | case DWC3_DEVICE_EVENT_OVERFLOW: |
72246da4 FB |
3749 | break; |
3750 | default: | |
e9f2aa87 | 3751 | dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type); |
72246da4 FB |
3752 | } |
3753 | } | |
3754 | ||
3755 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
3756 | const union dwc3_event *event) | |
3757 | { | |
43c96be1 | 3758 | trace_dwc3_event(event->raw, dwc); |
2c4cbe6e | 3759 | |
dfc5e805 FB |
3760 | if (!event->type.is_devspec) |
3761 | dwc3_endpoint_interrupt(dwc, &event->depevt); | |
3762 | else if (event->type.type == DWC3_EVENT_TYPE_DEV) | |
72246da4 | 3763 | dwc3_gadget_interrupt(dwc, &event->devt); |
dfc5e805 | 3764 | else |
72246da4 | 3765 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); |
72246da4 FB |
3766 | } |
3767 | ||
dea520a4 | 3768 | static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt) |
b15a762f | 3769 | { |
dea520a4 | 3770 | struct dwc3 *dwc = evt->dwc; |
b15a762f | 3771 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 3772 | int left; |
e8adfc30 | 3773 | u32 reg; |
b15a762f | 3774 | |
f42f2447 | 3775 | left = evt->count; |
b15a762f | 3776 | |
f42f2447 FB |
3777 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
3778 | return IRQ_NONE; | |
b15a762f | 3779 | |
f42f2447 FB |
3780 | while (left > 0) { |
3781 | union dwc3_event event; | |
b15a762f | 3782 | |
ebbb2d59 | 3783 | event.raw = *(u32 *) (evt->cache + evt->lpos); |
b15a762f | 3784 | |
f42f2447 | 3785 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 3786 | |
f42f2447 FB |
3787 | /* |
3788 | * FIXME we wrap around correctly to the next entry as | |
3789 | * almost all entries are 4 bytes in size. There is one | |
3790 | * entry which has 12 bytes which is a regular entry | |
3791 | * followed by 8 bytes data. ATM I don't know how | |
3792 | * things are organized if we get next to the a | |
3793 | * boundary so I worry about that once we try to handle | |
3794 | * that. | |
3795 | */ | |
caefe6c7 | 3796 | evt->lpos = (evt->lpos + 4) % evt->length; |
f42f2447 | 3797 | left -= 4; |
f42f2447 | 3798 | } |
b15a762f | 3799 | |
f42f2447 FB |
3800 | evt->count = 0; |
3801 | evt->flags &= ~DWC3_EVENT_PENDING; | |
3802 | ret = IRQ_HANDLED; | |
b15a762f | 3803 | |
f42f2447 | 3804 | /* Unmask interrupt */ |
660e9bde | 3805 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
f42f2447 | 3806 | reg &= ~DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 3807 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
b15a762f | 3808 | |
cf40b86b JY |
3809 | if (dwc->imod_interval) { |
3810 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); | |
3811 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); | |
3812 | } | |
3813 | ||
f42f2447 FB |
3814 | return ret; |
3815 | } | |
e8adfc30 | 3816 | |
dea520a4 | 3817 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt) |
f42f2447 | 3818 | { |
dea520a4 FB |
3819 | struct dwc3_event_buffer *evt = _evt; |
3820 | struct dwc3 *dwc = evt->dwc; | |
e5f68b4a | 3821 | unsigned long flags; |
f42f2447 | 3822 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 3823 | |
e5f68b4a | 3824 | spin_lock_irqsave(&dwc->lock, flags); |
dea520a4 | 3825 | ret = dwc3_process_event_buf(evt); |
e5f68b4a | 3826 | spin_unlock_irqrestore(&dwc->lock, flags); |
b15a762f FB |
3827 | |
3828 | return ret; | |
3829 | } | |
3830 | ||
dea520a4 | 3831 | static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) |
72246da4 | 3832 | { |
dea520a4 | 3833 | struct dwc3 *dwc = evt->dwc; |
ebbb2d59 | 3834 | u32 amount; |
72246da4 | 3835 | u32 count; |
e8adfc30 | 3836 | u32 reg; |
72246da4 | 3837 | |
fc8bb91b FB |
3838 | if (pm_runtime_suspended(dwc->dev)) { |
3839 | pm_runtime_get(dwc->dev); | |
3840 | disable_irq_nosync(dwc->irq_gadget); | |
3841 | dwc->pending_events = true; | |
3842 | return IRQ_HANDLED; | |
3843 | } | |
3844 | ||
d325a1de TN |
3845 | /* |
3846 | * With PCIe legacy interrupt, test shows that top-half irq handler can | |
3847 | * be called again after HW interrupt deassertion. Check if bottom-half | |
3848 | * irq event handler completes before caching new event to prevent | |
3849 | * losing events. | |
3850 | */ | |
3851 | if (evt->flags & DWC3_EVENT_PENDING) | |
3852 | return IRQ_HANDLED; | |
3853 | ||
660e9bde | 3854 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); |
72246da4 FB |
3855 | count &= DWC3_GEVNTCOUNT_MASK; |
3856 | if (!count) | |
3857 | return IRQ_NONE; | |
3858 | ||
b15a762f FB |
3859 | evt->count = count; |
3860 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 3861 | |
e8adfc30 | 3862 | /* Mask interrupt */ |
660e9bde | 3863 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
e8adfc30 | 3864 | reg |= DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 3865 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
e8adfc30 | 3866 | |
ebbb2d59 JY |
3867 | amount = min(count, evt->length - evt->lpos); |
3868 | memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount); | |
3869 | ||
3870 | if (amount < count) | |
3871 | memcpy(evt->cache, evt->buf, count - amount); | |
3872 | ||
65aca320 JY |
3873 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count); |
3874 | ||
b15a762f | 3875 | return IRQ_WAKE_THREAD; |
72246da4 FB |
3876 | } |
3877 | ||
dea520a4 | 3878 | static irqreturn_t dwc3_interrupt(int irq, void *_evt) |
72246da4 | 3879 | { |
dea520a4 | 3880 | struct dwc3_event_buffer *evt = _evt; |
72246da4 | 3881 | |
dea520a4 | 3882 | return dwc3_check_event_buf(evt); |
72246da4 FB |
3883 | } |
3884 | ||
6db3812e FB |
3885 | static int dwc3_gadget_get_irq(struct dwc3 *dwc) |
3886 | { | |
3887 | struct platform_device *dwc3_pdev = to_platform_device(dwc->dev); | |
3888 | int irq; | |
3889 | ||
f146b40b | 3890 | irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral"); |
6db3812e FB |
3891 | if (irq > 0) |
3892 | goto out; | |
3893 | ||
3894 | if (irq == -EPROBE_DEFER) | |
3895 | goto out; | |
3896 | ||
f146b40b | 3897 | irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3"); |
6db3812e FB |
3898 | if (irq > 0) |
3899 | goto out; | |
3900 | ||
3901 | if (irq == -EPROBE_DEFER) | |
3902 | goto out; | |
3903 | ||
3904 | irq = platform_get_irq(dwc3_pdev, 0); | |
3905 | if (irq > 0) | |
3906 | goto out; | |
3907 | ||
6db3812e FB |
3908 | if (!irq) |
3909 | irq = -EINVAL; | |
3910 | ||
3911 | out: | |
3912 | return irq; | |
3913 | } | |
3914 | ||
e81a7018 PC |
3915 | static void dwc_gadget_release(struct device *dev) |
3916 | { | |
3917 | struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev); | |
3918 | ||
3919 | kfree(gadget); | |
3920 | } | |
3921 | ||
72246da4 | 3922 | /** |
bfad65ee | 3923 | * dwc3_gadget_init - initializes gadget related registers |
1d046793 | 3924 | * @dwc: pointer to our controller context structure |
72246da4 FB |
3925 | * |
3926 | * Returns 0 on success otherwise negative errno. | |
3927 | */ | |
41ac7b3a | 3928 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 3929 | { |
6db3812e FB |
3930 | int ret; |
3931 | int irq; | |
e81a7018 | 3932 | struct device *dev; |
9522def4 | 3933 | |
6db3812e FB |
3934 | irq = dwc3_gadget_get_irq(dwc); |
3935 | if (irq < 0) { | |
3936 | ret = irq; | |
3937 | goto err0; | |
9522def4 RQ |
3938 | } |
3939 | ||
3940 | dwc->irq_gadget = irq; | |
72246da4 | 3941 | |
d64ff406 AB |
3942 | dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev, |
3943 | sizeof(*dwc->ep0_trb) * 2, | |
3944 | &dwc->ep0_trb_addr, GFP_KERNEL); | |
72246da4 FB |
3945 | if (!dwc->ep0_trb) { |
3946 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
3947 | ret = -ENOMEM; | |
7d5e650a | 3948 | goto err0; |
72246da4 FB |
3949 | } |
3950 | ||
4199c5f8 | 3951 | dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL); |
72246da4 | 3952 | if (!dwc->setup_buf) { |
72246da4 | 3953 | ret = -ENOMEM; |
7d5e650a | 3954 | goto err1; |
72246da4 FB |
3955 | } |
3956 | ||
905dc04e FB |
3957 | dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, |
3958 | &dwc->bounce_addr, GFP_KERNEL); | |
3959 | if (!dwc->bounce) { | |
3960 | ret = -ENOMEM; | |
d6e5a549 | 3961 | goto err2; |
905dc04e FB |
3962 | } |
3963 | ||
bb014736 | 3964 | init_completion(&dwc->ep0_in_setup); |
e81a7018 PC |
3965 | dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL); |
3966 | if (!dwc->gadget) { | |
3967 | ret = -ENOMEM; | |
3968 | goto err3; | |
3969 | } | |
bb014736 | 3970 | |
e81a7018 PC |
3971 | |
3972 | usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release); | |
3973 | dev = &dwc->gadget->dev; | |
3974 | dev->platform_data = dwc; | |
3975 | dwc->gadget->ops = &dwc3_gadget_ops; | |
3976 | dwc->gadget->speed = USB_SPEED_UNKNOWN; | |
f551037c | 3977 | dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN; |
e81a7018 PC |
3978 | dwc->gadget->sg_supported = true; |
3979 | dwc->gadget->name = "dwc3-gadget"; | |
475e8be5 | 3980 | dwc->gadget->lpm_capable = !dwc->usb2_gadget_lpm_disable; |
72246da4 | 3981 | |
b9e51b2b BM |
3982 | /* |
3983 | * FIXME We might be setting max_speed to <SUPER, however versions | |
3984 | * <2.20a of dwc3 have an issue with metastability (documented | |
3985 | * elsewhere in this driver) which tells us we can't set max speed to | |
3986 | * anything lower than SUPER. | |
3987 | * | |
3988 | * Because gadget.max_speed is only used by composite.c and function | |
3989 | * drivers (i.e. it won't go into dwc3's registers) we are allowing this | |
3990 | * to happen so we avoid sending SuperSpeed Capability descriptor | |
3991 | * together with our BOS descriptor as that could confuse host into | |
3992 | * thinking we can handle super speed. | |
3993 | * | |
3994 | * Note that, in fact, we won't even support GetBOS requests when speed | |
3995 | * is less than super speed because we don't have means, yet, to tell | |
3996 | * composite.c that we are USB 2.0 + LPM ECN. | |
3997 | */ | |
9af21dd6 | 3998 | if (DWC3_VER_IS_PRIOR(DWC3, 220A) && |
42bf02ec | 3999 | !dwc->dis_metastability_quirk) |
5eb30ced | 4000 | dev_info(dwc->dev, "changing max_speed on rev %08x\n", |
b9e51b2b BM |
4001 | dwc->revision); |
4002 | ||
e81a7018 | 4003 | dwc->gadget->max_speed = dwc->maximum_speed; |
67848146 | 4004 | dwc->gadget->max_ssp_rate = dwc->max_ssp_rate; |
b9e51b2b | 4005 | |
72246da4 FB |
4006 | /* |
4007 | * REVISIT: Here we should clear all pending IRQs to be | |
4008 | * sure we're starting from a well known location. | |
4009 | */ | |
4010 | ||
f3bcfc7e | 4011 | ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps); |
72246da4 | 4012 | if (ret) |
e81a7018 | 4013 | goto err4; |
72246da4 | 4014 | |
e81a7018 | 4015 | ret = usb_add_gadget(dwc->gadget); |
72246da4 | 4016 | if (ret) { |
e81a7018 PC |
4017 | dev_err(dwc->dev, "failed to add gadget\n"); |
4018 | goto err5; | |
72246da4 FB |
4019 | } |
4020 | ||
072cab8a TN |
4021 | if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS) |
4022 | dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate); | |
4023 | else | |
4024 | dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed); | |
169e3b68 | 4025 | |
72246da4 FB |
4026 | return 0; |
4027 | ||
e81a7018 | 4028 | err5: |
d6e5a549 | 4029 | dwc3_gadget_free_endpoints(dwc); |
e81a7018 PC |
4030 | err4: |
4031 | usb_put_gadget(dwc->gadget); | |
7d5e650a | 4032 | err3: |
d6e5a549 FB |
4033 | dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce, |
4034 | dwc->bounce_addr); | |
5812b1c2 | 4035 | |
7d5e650a | 4036 | err2: |
0fc9a1be | 4037 | kfree(dwc->setup_buf); |
72246da4 | 4038 | |
7d5e650a | 4039 | err1: |
d64ff406 | 4040 | dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
4041 | dwc->ep0_trb, dwc->ep0_trb_addr); |
4042 | ||
72246da4 FB |
4043 | err0: |
4044 | return ret; | |
4045 | } | |
4046 | ||
7415f17c FB |
4047 | /* -------------------------------------------------------------------------- */ |
4048 | ||
72246da4 FB |
4049 | void dwc3_gadget_exit(struct dwc3 *dwc) |
4050 | { | |
e81a7018 | 4051 | usb_del_gadget_udc(dwc->gadget); |
72246da4 | 4052 | dwc3_gadget_free_endpoints(dwc); |
905dc04e | 4053 | dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce, |
d6e5a549 | 4054 | dwc->bounce_addr); |
0fc9a1be | 4055 | kfree(dwc->setup_buf); |
d64ff406 | 4056 | dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, |
d6e5a549 | 4057 | dwc->ep0_trb, dwc->ep0_trb_addr); |
72246da4 | 4058 | } |
7415f17c | 4059 | |
0b0231aa | 4060 | int dwc3_gadget_suspend(struct dwc3 *dwc) |
7415f17c | 4061 | { |
9772b47a RQ |
4062 | if (!dwc->gadget_driver) |
4063 | return 0; | |
4064 | ||
1551e35e | 4065 | dwc3_gadget_run_stop(dwc, false, false); |
9f8a67b6 FB |
4066 | dwc3_disconnect_gadget(dwc); |
4067 | __dwc3_gadget_stop(dwc); | |
7415f17c FB |
4068 | |
4069 | return 0; | |
4070 | } | |
4071 | ||
4072 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
4073 | { | |
7415f17c FB |
4074 | int ret; |
4075 | ||
9772b47a RQ |
4076 | if (!dwc->gadget_driver) |
4077 | return 0; | |
4078 | ||
9f8a67b6 FB |
4079 | ret = __dwc3_gadget_start(dwc); |
4080 | if (ret < 0) | |
7415f17c FB |
4081 | goto err0; |
4082 | ||
9f8a67b6 FB |
4083 | ret = dwc3_gadget_run_stop(dwc, true, false); |
4084 | if (ret < 0) | |
7415f17c FB |
4085 | goto err1; |
4086 | ||
7415f17c FB |
4087 | return 0; |
4088 | ||
4089 | err1: | |
9f8a67b6 | 4090 | __dwc3_gadget_stop(dwc); |
7415f17c FB |
4091 | |
4092 | err0: | |
4093 | return ret; | |
4094 | } | |
fc8bb91b FB |
4095 | |
4096 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc) | |
4097 | { | |
4098 | if (dwc->pending_events) { | |
4099 | dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf); | |
4100 | dwc->pending_events = false; | |
4101 | enable_irq(dwc->irq_gadget); | |
4102 | } | |
4103 | } |