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usb: dwc3: Update maximum_speed for SuperSpeedPlus
[linux-2.6-block.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4
FB		 17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
80977dc9 33#include "debug.h"
72246da4
FB		 34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
04a9bfcd
FB		 38/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
911f1f88
PZ		 71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
8598bde7
FB		 87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
aee63e3c 93 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
aee63e3c 97 int retries = 10000;
8598bde7
FB		 98 u32 reg;
99
802fde98
PZ		 100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
8598bde7
FB		 117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
802fde98
PZ		 124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
8598bde7 131 /* wait for a change in DSTS */
aed430e5 132 retries = 10000;
8598bde7
FB		 133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
8598bde7
FB		 136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
aee63e3c 139 udelay(5);
8598bde7
FB		 140 }
141
73815280
FB		 142 dwc3_trace(trace_dwc3_gadget,
143 "link state change request timed out");
8598bde7
FB		 144
145 return -ETIMEDOUT;
146}
147
457e84b6
FB		 148/**
149 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
150 * @dwc: pointer to our context structure
151 *
152 * This function will a best effort FIFO allocation in order
153 * to improve FIFO usage and throughput, while still allowing
154 * us to enable as many endpoints as possible.
155 *
156 * Keep in mind that this operation will be highly dependent
157 * on the configured size for RAM1 - which contains TxFifo -,
158 * the amount of endpoints enabled on coreConsultant tool, and
159 * the width of the Master Bus.
160 *
161 * In the ideal world, we would always be able to satisfy the
162 * following equation:
163 *
164 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
165 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
166 *
167 * Unfortunately, due to many variables that's not always the case.
168 */
169int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
170{
171 int last_fifo_depth = 0;
172 int ram1_depth;
173 int fifo_size;
174 int mdwidth;
175 int num;
176
177 if (!dwc->needs_fifo_resize)
178 return 0;
179
180 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
181 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
182
183 /* MDWIDTH is represented in bits, we need it in bytes */
184 mdwidth >>= 3;
185
186 /*
187 * FIXME For now we will only allocate 1 wMaxPacketSize space
188 * for each enabled endpoint, later patches will come to
189 * improve this algorithm so that we better use the internal
190 * FIFO space
191 */
32702e96
JP		 192 for (num = 0; num < dwc->num_in_eps; num++) {
193 /* bit0 indicates direction; 1 means IN ep */
194 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
2e81c36a 195 int mult = 1;
457e84b6
FB		 196 int tmp;
197
457e84b6
FB		 198 if (!(dep->flags & DWC3_EP_ENABLED))
199 continue;
200
16e78db7
IS		 201 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
202 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
2e81c36a
FB		 203 mult = 3;
204
205 /*
206 * REVISIT: the following assumes we will always have enough
207 * space available on the FIFO RAM for all possible use cases.
208 * Make sure that's true somehow and change FIFO allocation
209 * accordingly.
210 *
211 * If we have Bulk or Isochronous endpoints, we want
212 * them to be able to be very, very fast. So we're giving
213 * those endpoints a fifo_size which is enough for 3 full
214 * packets
215 */
216 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
457e84b6
FB		 217 tmp += mdwidth;
218
219 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
2e81c36a 220
457e84b6
FB		 221 fifo_size |= (last_fifo_depth << 16);
222
73815280 223 dwc3_trace(trace_dwc3_gadget, "%s: Fifo Addr %04x Size %d",
457e84b6
FB		 224 dep->name, last_fifo_depth, fifo_size & 0xffff);
225
32702e96 226 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
457e84b6
FB		 227
228 last_fifo_depth += (fifo_size & 0xffff);
229 }
230
231 return 0;
232}
233
72246da4
FB		 234void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
235 int status)
236{
237 struct dwc3 *dwc = dep->dwc;
e5ba5ec8 238 int i;
72246da4
FB		 239
240 if (req->queued) {
e5ba5ec8
PA		 241 i = 0;
242 do {
eeb720fb 243 dep->busy_slot++;
e5ba5ec8
PA		 244 /*
245 * Skip LINK TRB. We can't use req->trb and check for
246 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
247 * just completed (not the LINK TRB).
248 */
249 if (((dep->busy_slot & DWC3_TRB_MASK) ==
250 DWC3_TRB_NUM- 1) &&
16e78db7 251 usb_endpoint_xfer_isoc(dep->endpoint.desc))
e5ba5ec8
PA		 252 dep->busy_slot++;
253 } while(++i < req->request.num_mapped_sgs);
c9fda7d6 254 req->queued = false;
72246da4
FB		 255 }
256 list_del(&req->list);
eeb720fb 257 req->trb = NULL;
72246da4
FB		 258
259 if (req->request.status == -EINPROGRESS)
260 req->request.status = status;
261
0416e494
PA		 262 if (dwc->ep0_bounced && dep->number == 0)
263 dwc->ep0_bounced = false;
264 else
265 usb_gadget_unmap_request(&dwc->gadget, &req->request,
266 req->direction);
72246da4 267
2c4cbe6e 268 trace_dwc3_gadget_giveback(req);
72246da4
FB		 269
270 spin_unlock(&dwc->lock);
304f7e5e 271 usb_gadget_giveback_request(&dep->endpoint, &req->request);
72246da4
FB		 272 spin_lock(&dwc->lock);
273}
274
3ece0ec4 275int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
b09bb642
FB		 276{
277 u32 timeout = 500;
278 u32 reg;
279
2c4cbe6e 280 trace_dwc3_gadget_generic_cmd(cmd, param);
427c3df6 281
b09bb642
FB		 282 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
283 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
284
285 do {
286 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
287 if (!(reg & DWC3_DGCMD_CMDACT)) {
73815280
FB		 288 dwc3_trace(trace_dwc3_gadget,
289 "Command Complete --> %d",
b09bb642 290 DWC3_DGCMD_STATUS(reg));
891b1dc0
SSB		 291 if (DWC3_DGCMD_STATUS(reg))
292 return -EINVAL;
b09bb642
FB		 293 return 0;
294 }
295
296 /*
297 * We can't sleep here, because it's also called from
298 * interrupt context.
299 */
300 timeout--;
73815280
FB		 301 if (!timeout) {
302 dwc3_trace(trace_dwc3_gadget,
303 "Command Timed Out");
b09bb642 304 return -ETIMEDOUT;
73815280 305 }
b09bb642
FB		 306 udelay(1);
307 } while (1);
308}
309
72246da4
FB		 310int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
311 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
312{
313 struct dwc3_ep *dep = dwc->eps[ep];
61d58242 314 u32 timeout = 500;
72246da4
FB		 315 u32 reg;
316
2c4cbe6e 317 trace_dwc3_gadget_ep_cmd(dep, cmd, params);
72246da4 318
dc1c70a7
FB		 319 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
320 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
321 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
72246da4
FB		 322
323 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
324 do {
325 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
326 if (!(reg & DWC3_DEPCMD_CMDACT)) {
73815280
FB		 327 dwc3_trace(trace_dwc3_gadget,
328 "Command Complete --> %d",
164f6e14 329 DWC3_DEPCMD_STATUS(reg));
76e838c9
SSB		 330 if (DWC3_DEPCMD_STATUS(reg))
331 return -EINVAL;
72246da4
FB		 332 return 0;
333 }
334
335 /*
72246da4
FB		 336 * We can't sleep here, because it is also called from
337 * interrupt context.
338 */
339 timeout--;
73815280
FB		 340 if (!timeout) {
341 dwc3_trace(trace_dwc3_gadget,
342 "Command Timed Out");
72246da4 343 return -ETIMEDOUT;
73815280 344 }
72246da4 345
61d58242 346 udelay(1);
72246da4
FB		 347 } while (1);
348}
349
350static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 351 struct dwc3_trb *trb)
72246da4 352{
c439ef87 353 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 354
355 return dep->trb_pool_dma + offset;
356}
357
358static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
359{
360 struct dwc3 *dwc = dep->dwc;
361
362 if (dep->trb_pool)
363 return 0;
364
72246da4
FB		 365 dep->trb_pool = dma_alloc_coherent(dwc->dev,
366 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
367 &dep->trb_pool_dma, GFP_KERNEL);
368 if (!dep->trb_pool) {
369 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
370 dep->name);
371 return -ENOMEM;
372 }
373
374 return 0;
375}
376
377static void dwc3_free_trb_pool(struct dwc3_ep *dep)
378{
379 struct dwc3 *dwc = dep->dwc;
380
381 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
382 dep->trb_pool, dep->trb_pool_dma);
383
384 dep->trb_pool = NULL;
385 dep->trb_pool_dma = 0;
386}
387
c4509601
JY		 388static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
389
390/**
391 * dwc3_gadget_start_config - Configure EP resources
392 * @dwc: pointer to our controller context structure
393 * @dep: endpoint that is being enabled
394 *
395 * The assignment of transfer resources cannot perfectly follow the
396 * data book due to the fact that the controller driver does not have
397 * all knowledge of the configuration in advance. It is given this
398 * information piecemeal by the composite gadget framework after every
399 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
400 * programming model in this scenario can cause errors. For two
401 * reasons:
402 *
403 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
404 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
405 * multiple interfaces.
406 *
407 * 2) The databook does not mention doing more DEPXFERCFG for new
408 * endpoint on alt setting (8.1.6).
409 *
410 * The following simplified method is used instead:
411 *
412 * All hardware endpoints can be assigned a transfer resource and this
413 * setting will stay persistent until either a core reset or
414 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
415 * do DEPXFERCFG for every hardware endpoint as well. We are
416 * guaranteed that there are as many transfer resources as endpoints.
417 *
418 * This function is called for each endpoint when it is being enabled
419 * but is triggered only when called for EP0-out, which always happens
420 * first, and which should only happen in one of the above conditions.
421 */
72246da4
FB		 422static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
423{
424 struct dwc3_gadget_ep_cmd_params params;
425 u32 cmd;
c4509601
JY		 426 int i;
427 int ret;
428
429 if (dep->number)
430 return 0;
72246da4
FB		 431
432 memset(&params, 0x00, sizeof(params));
c4509601 433 cmd = DWC3_DEPCMD_DEPSTARTCFG;
72246da4 434
c4509601
JY		 435 ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
436 if (ret)
437 return ret;
438
439 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
440 struct dwc3_ep *dep = dwc->eps[i];
72246da4 441
c4509601
JY		 442 if (!dep)
443 continue;
444
445 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
446 if (ret)
447 return ret;
72246da4
FB		 448 }
449
450 return 0;
451}
452
453static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
c90bfaec 454 const struct usb_endpoint_descriptor *desc,
4b345c9a 455 const struct usb_ss_ep_comp_descriptor *comp_desc,
265b70a7 456 bool ignore, bool restore)
72246da4
FB		 457{
458 struct dwc3_gadget_ep_cmd_params params;
459
460 memset(&params, 0x00, sizeof(params));
461
dc1c70a7 462 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
d2e9a13a
CP		 463 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
464
465 /* Burst size is only needed in SuperSpeed mode */
ee5cd41c 466 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
d2e9a13a
CP		 467 u32 burst = dep->endpoint.maxburst - 1;
468
469 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
470 }
72246da4 471
4b345c9a
FB		 472 if (ignore)
473 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
474
265b70a7
PZ		 475 if (restore) {
476 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
477 params.param2 |= dep->saved_state;
478 }
479
dc1c70a7
FB		 480 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
481 | DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 482
18b7ede5 483 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 484 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
485 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 486 dep->stream_capable = true;
487 }
488
0b93a4c8 489 if (!usb_endpoint_xfer_control(desc))
dc1c70a7 490 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 491
492 /*
493 * We are doing 1:1 mapping for endpoints, meaning
494 * Physical Endpoints 2 maps to Logical Endpoint 2 and
495 * so on. We consider the direction bit as part of the physical
496 * endpoint number. So USB endpoint 0x81 is 0x03.
497 */
dc1c70a7 498 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 499
500 /*
501 * We must use the lower 16 TX FIFOs even though
502 * HW might have more
503 */
504 if (dep->direction)
dc1c70a7 505 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 506
507 if (desc->bInterval) {
dc1c70a7 508 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 509 dep->interval = 1 << (desc->bInterval - 1);
510 }
511
512 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
513 DWC3_DEPCMD_SETEPCONFIG, &params);
514}
515
516static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
517{
518 struct dwc3_gadget_ep_cmd_params params;
519
520 memset(&params, 0x00, sizeof(params));
521
dc1c70a7 522 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4
FB		 523
524 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
525 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
526}
527
528/**
529 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
530 * @dep: endpoint to be initialized
531 * @desc: USB Endpoint Descriptor
532 *
533 * Caller should take care of locking
534 */
535static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
c90bfaec 536 const struct usb_endpoint_descriptor *desc,
4b345c9a 537 const struct usb_ss_ep_comp_descriptor *comp_desc,
265b70a7 538 bool ignore, bool restore)
72246da4
FB		 539{
540 struct dwc3 *dwc = dep->dwc;
541 u32 reg;
b09e99ee 542 int ret;
72246da4 543
73815280 544 dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
ff62d6b6 545
72246da4
FB		 546 if (!(dep->flags & DWC3_EP_ENABLED)) {
547 ret = dwc3_gadget_start_config(dwc, dep);
548 if (ret)
549 return ret;
550 }
551
265b70a7
PZ		 552 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
553 restore);
72246da4
FB		 554 if (ret)
555 return ret;
556
557 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 558 struct dwc3_trb *trb_st_hw;
559 struct dwc3_trb *trb_link;
72246da4 560
16e78db7 561 dep->endpoint.desc = desc;
c90bfaec 562 dep->comp_desc = comp_desc;
72246da4
FB		 563 dep->type = usb_endpoint_type(desc);
564 dep->flags |= DWC3_EP_ENABLED;
565
566 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
567 reg |= DWC3_DALEPENA_EP(dep->number);
568 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
569
570 if (!usb_endpoint_xfer_isoc(desc))
571 return 0;
572
1d046793 573 /* Link TRB for ISOC. The HWO bit is never reset */
72246da4
FB		 574 trb_st_hw = &dep->trb_pool[0];
575
f6bafc6a 576 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
1200a82a 577 memset(trb_link, 0, sizeof(*trb_link));
72246da4 578
f6bafc6a
FB		 579 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
580 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
581 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
582 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 583 }
584
aa739974
FB		 585 switch (usb_endpoint_type(desc)) {
586 case USB_ENDPOINT_XFER_CONTROL:
587 strlcat(dep->name, "-control", sizeof(dep->name));
588 break;
589 case USB_ENDPOINT_XFER_ISOC:
590 strlcat(dep->name, "-isoc", sizeof(dep->name));
591 break;
592 case USB_ENDPOINT_XFER_BULK:
593 strlcat(dep->name, "-bulk", sizeof(dep->name));
594 break;
595 case USB_ENDPOINT_XFER_INT:
596 strlcat(dep->name, "-int", sizeof(dep->name));
597 break;
598 default:
599 dev_err(dwc->dev, "invalid endpoint transfer type\n");
600 }
601
72246da4
FB		 602 return 0;
603}
604
b992e681 605static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
624407f9 606static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 607{
608 struct dwc3_request *req;
609
ea53b882 610 if (!list_empty(&dep->req_queued)) {
b992e681 611 dwc3_stop_active_transfer(dwc, dep->number, true);
624407f9 612
57911504 613 /* - giveback all requests to gadget driver */
1591633e
PA		 614 while (!list_empty(&dep->req_queued)) {
615 req = next_request(&dep->req_queued);
616
617 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
618 }
ea53b882
FB		 619 }
620
72246da4
FB		 621 while (!list_empty(&dep->request_list)) {
622 req = next_request(&dep->request_list);
623
624407f9 624 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 625 }
72246da4
FB		 626}
627
628/**
629 * __dwc3_gadget_ep_disable - Disables a HW endpoint
630 * @dep: the endpoint to disable
631 *
624407f9
SAS		 632 * This function also removes requests which are currently processed ny the
633 * hardware and those which are not yet scheduled.
634 * Caller should take care of locking.
72246da4 635 */
72246da4
FB		 636static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
637{
638 struct dwc3 *dwc = dep->dwc;
639 u32 reg;
640
7eaeac5c
FB		 641 dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
642
624407f9 643 dwc3_remove_requests(dwc, dep);
72246da4 644
687ef981
FB		 645 /* make sure HW endpoint isn't stalled */
646 if (dep->flags & DWC3_EP_STALL)
7a608559 647 __dwc3_gadget_ep_set_halt(dep, 0, false);
687ef981 648
72246da4
FB		 649 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
650 reg &= ~DWC3_DALEPENA_EP(dep->number);
651 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
652
879631aa 653 dep->stream_capable = false;
f9c56cdd 654 dep->endpoint.desc = NULL;
c90bfaec 655 dep->comp_desc = NULL;
72246da4 656 dep->type = 0;
879631aa 657 dep->flags = 0;
72246da4 658
aa739974
FB		 659 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
660 dep->number >> 1,
661 (dep->number & 1) ? "in" : "out");
662
72246da4
FB		 663 return 0;
664}
665
666/* -------------------------------------------------------------------------- */
667
668static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
669 const struct usb_endpoint_descriptor *desc)
670{
671 return -EINVAL;
672}
673
674static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
675{
676 return -EINVAL;
677}
678
679/* -------------------------------------------------------------------------- */
680
681static int dwc3_gadget_ep_enable(struct usb_ep *ep,
682 const struct usb_endpoint_descriptor *desc)
683{
684 struct dwc3_ep *dep;
685 struct dwc3 *dwc;
686 unsigned long flags;
687 int ret;
688
689 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
690 pr_debug("dwc3: invalid parameters\n");
691 return -EINVAL;
692 }
693
694 if (!desc->wMaxPacketSize) {
695 pr_debug("dwc3: missing wMaxPacketSize\n");
696 return -EINVAL;
697 }
698
699 dep = to_dwc3_ep(ep);
700 dwc = dep->dwc;
701
95ca961c
FB		 702 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
703 "%s is already enabled\n",
704 dep->name))
c6f83f38 705 return 0;
c6f83f38 706
72246da4 707 spin_lock_irqsave(&dwc->lock, flags);
265b70a7 708 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
72246da4
FB		 709 spin_unlock_irqrestore(&dwc->lock, flags);
710
711 return ret;
712}
713
714static int dwc3_gadget_ep_disable(struct usb_ep *ep)
715{
716 struct dwc3_ep *dep;
717 struct dwc3 *dwc;
718 unsigned long flags;
719 int ret;
720
721 if (!ep) {
722 pr_debug("dwc3: invalid parameters\n");
723 return -EINVAL;
724 }
725
726 dep = to_dwc3_ep(ep);
727 dwc = dep->dwc;
728
95ca961c
FB		 729 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
730 "%s is already disabled\n",
731 dep->name))
72246da4 732 return 0;
72246da4 733
72246da4
FB		 734 spin_lock_irqsave(&dwc->lock, flags);
735 ret = __dwc3_gadget_ep_disable(dep);
736 spin_unlock_irqrestore(&dwc->lock, flags);
737
738 return ret;
739}
740
741static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
742 gfp_t gfp_flags)
743{
744 struct dwc3_request *req;
745 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4
FB		 746
747 req = kzalloc(sizeof(*req), gfp_flags);
734d5a53 748 if (!req)
72246da4 749 return NULL;
72246da4
FB		 750
751 req->epnum = dep->number;
752 req->dep = dep;
72246da4 753
2c4cbe6e
FB		 754 trace_dwc3_alloc_request(req);
755
72246da4
FB		 756 return &req->request;
757}
758
759static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
760 struct usb_request *request)
761{
762 struct dwc3_request *req = to_dwc3_request(request);
763
2c4cbe6e 764 trace_dwc3_free_request(req);
72246da4
FB		 765 kfree(req);
766}
767
c71fc37c
FB		 768/**
769 * dwc3_prepare_one_trb - setup one TRB from one request
770 * @dep: endpoint for which this request is prepared
771 * @req: dwc3_request pointer
772 */
68e823e2 773static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
eeb720fb 774 struct dwc3_request *req, dma_addr_t dma,
e5ba5ec8 775 unsigned length, unsigned last, unsigned chain, unsigned node)
c71fc37c 776{
f6bafc6a 777 struct dwc3_trb *trb;
c71fc37c 778
73815280 779 dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
eeb720fb
FB		 780 dep->name, req, (unsigned long long) dma,
781 length, last ? " last" : "",
782 chain ? " chain" : "");
783
915e202a
PA		 784
785 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
c71fc37c 786
eeb720fb
FB		 787 if (!req->trb) {
788 dwc3_gadget_move_request_queued(req);
f6bafc6a
FB		 789 req->trb = trb;
790 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
e5ba5ec8 791 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
eeb720fb 792 }
c71fc37c 793
e5ba5ec8 794 dep->free_slot++;
5cd8c48d
ZJC		 795 /* Skip the LINK-TRB on ISOC */
796 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
797 usb_endpoint_xfer_isoc(dep->endpoint.desc))
798 dep->free_slot++;
e5ba5ec8 799
f6bafc6a
FB		 800 trb->size = DWC3_TRB_SIZE_LENGTH(length);
801 trb->bpl = lower_32_bits(dma);
802 trb->bph = upper_32_bits(dma);
c71fc37c 803
16e78db7 804 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 805 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 806 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 807 break;
808
809 case USB_ENDPOINT_XFER_ISOC:
e5ba5ec8
PA		 810 if (!node)
811 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
812 else
813 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
c71fc37c
FB		 814 break;
815
816 case USB_ENDPOINT_XFER_BULK:
817 case USB_ENDPOINT_XFER_INT:
f6bafc6a 818 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 819 break;
820 default:
821 /*
822 * This is only possible with faulty memory because we
823 * checked it already :)
824 */
825 BUG();
826 }
827
f3af3651
FB		 828 if (!req->request.no_interrupt && !chain)
829 trb->ctrl |= DWC3_TRB_CTRL_IOC;
830
16e78db7 831 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
f6bafc6a
FB		 832 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
833 trb->ctrl |= DWC3_TRB_CTRL_CSP;
e5ba5ec8
PA		 834 } else if (last) {
835 trb->ctrl |= DWC3_TRB_CTRL_LST;
f6bafc6a 836 }
c71fc37c 837
e5ba5ec8
PA		 838 if (chain)
839 trb->ctrl |= DWC3_TRB_CTRL_CHN;
840
16e78db7 841 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
f6bafc6a 842 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
c71fc37c 843
f6bafc6a 844 trb->ctrl |= DWC3_TRB_CTRL_HWO;
2c4cbe6e
FB		 845
846 trace_dwc3_prepare_trb(dep, trb);
c71fc37c
FB		 847}
848
72246da4
FB		 849/*
850 * dwc3_prepare_trbs - setup TRBs from requests
851 * @dep: endpoint for which requests are being prepared
852 * @starting: true if the endpoint is idle and no requests are queued.
853 *
1d046793
PZ		 854 * The function goes through the requests list and sets up TRBs for the
855 * transfers. The function returns once there are no more TRBs available or
856 * it runs out of requests.
72246da4 857 */
68e823e2 858static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
72246da4 859{
68e823e2 860 struct dwc3_request *req, *n;
72246da4 861 u32 trbs_left;
8d62cd65 862 u32 max;
c71fc37c 863 unsigned int last_one = 0;
72246da4
FB		 864
865 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
866
867 /* the first request must not be queued */
868 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
c71fc37c 869
8d62cd65 870 /* Can't wrap around on a non-isoc EP since there's no link TRB */
16e78db7 871 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8d62cd65
PZ		 872 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
873 if (trbs_left > max)
874 trbs_left = max;
875 }
876
72246da4 877 /*
1d046793
PZ		 878 * If busy & slot are equal than it is either full or empty. If we are
879 * starting to process requests then we are empty. Otherwise we are
72246da4
FB		 880 * full and don't do anything
881 */
882 if (!trbs_left) {
883 if (!starting)
68e823e2 884 return;
72246da4
FB		 885 trbs_left = DWC3_TRB_NUM;
886 /*
887 * In case we start from scratch, we queue the ISOC requests
888 * starting from slot 1. This is done because we use ring
889 * buffer and have no LST bit to stop us. Instead, we place
1d046793 890 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
72246da4
FB		 891 * after the first request so we start at slot 1 and have
892 * 7 requests proceed before we hit the first IOC.
893 * Other transfer types don't use the ring buffer and are
894 * processed from the first TRB until the last one. Since we
895 * don't wrap around we have to start at the beginning.
896 */
16e78db7 897 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 898 dep->busy_slot = 1;
899 dep->free_slot = 1;
900 } else {
901 dep->busy_slot = 0;
902 dep->free_slot = 0;
903 }
904 }
905
906 /* The last TRB is a link TRB, not used for xfer */
16e78db7 907 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
68e823e2 908 return;
72246da4
FB		 909
910 list_for_each_entry_safe(req, n, &dep->request_list, list) {
eeb720fb
FB		 911 unsigned length;
912 dma_addr_t dma;
e5ba5ec8 913 last_one = false;
72246da4 914
eeb720fb
FB		 915 if (req->request.num_mapped_sgs > 0) {
916 struct usb_request *request = &req->request;
917 struct scatterlist *sg = request->sg;
918 struct scatterlist *s;
919 int i;
72246da4 920
eeb720fb
FB		 921 for_each_sg(sg, s, request->num_mapped_sgs, i) {
922 unsigned chain = true;
72246da4 923
eeb720fb
FB		 924 length = sg_dma_len(s);
925 dma = sg_dma_address(s);
72246da4 926
1d046793
PZ		 927 if (i == (request->num_mapped_sgs - 1) ||
928 sg_is_last(s)) {
ec512fb8 929 if (list_empty(&dep->request_list))
e5ba5ec8 930 last_one = true;
eeb720fb
FB		 931 chain = false;
932 }
72246da4 933
eeb720fb
FB		 934 trbs_left--;
935 if (!trbs_left)
936 last_one = true;
72246da4 937
eeb720fb
FB		 938 if (last_one)
939 chain = false;
72246da4 940
eeb720fb 941 dwc3_prepare_one_trb(dep, req, dma, length,
e5ba5ec8 942 last_one, chain, i);
72246da4 943
eeb720fb
FB		 944 if (last_one)
945 break;
946 }
39e60635
AV		 947
948 if (last_one)
949 break;
72246da4 950 } else {
eeb720fb
FB		 951 dma = req->request.dma;
952 length = req->request.length;
953 trbs_left--;
72246da4 954
eeb720fb
FB		 955 if (!trbs_left)
956 last_one = 1;
879631aa 957
eeb720fb
FB		 958 /* Is this the last request? */
959 if (list_is_last(&req->list, &dep->request_list))
960 last_one = 1;
72246da4 961
eeb720fb 962 dwc3_prepare_one_trb(dep, req, dma, length,
e5ba5ec8 963 last_one, false, 0);
72246da4 964
eeb720fb
FB		 965 if (last_one)
966 break;
72246da4 967 }
72246da4 968 }
72246da4
FB		 969}
970
971static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
972 int start_new)
973{
974 struct dwc3_gadget_ep_cmd_params params;
975 struct dwc3_request *req;
976 struct dwc3 *dwc = dep->dwc;
977 int ret;
978 u32 cmd;
979
980 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
73815280 981 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
72246da4
FB		 982 return -EBUSY;
983 }
72246da4
FB		 984
985 /*
986 * If we are getting here after a short-out-packet we don't enqueue any
987 * new requests as we try to set the IOC bit only on the last request.
988 */
989 if (start_new) {
990 if (list_empty(&dep->req_queued))
991 dwc3_prepare_trbs(dep, start_new);
992
993 /* req points to the first request which will be sent */
994 req = next_request(&dep->req_queued);
995 } else {
68e823e2
FB		 996 dwc3_prepare_trbs(dep, start_new);
997
72246da4 998 /*
1d046793 999 * req points to the first request where HWO changed from 0 to 1
72246da4 1000 */
68e823e2 1001 req = next_request(&dep->req_queued);
72246da4
FB		 1002 }
1003 if (!req) {
1004 dep->flags |= DWC3_EP_PENDING_REQUEST;
1005 return 0;
1006 }
1007
1008 memset(&params, 0, sizeof(params));
72246da4 1009
1877d6c9
PA		 1010 if (start_new) {
1011 params.param0 = upper_32_bits(req->trb_dma);
1012 params.param1 = lower_32_bits(req->trb_dma);
72246da4 1013 cmd = DWC3_DEPCMD_STARTTRANSFER;
1877d6c9 1014 } else {
72246da4 1015 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1877d6c9 1016 }
72246da4
FB		 1017
1018 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1019 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1020 if (ret < 0) {
72246da4
FB		 1021 /*
1022 * FIXME we need to iterate over the list of requests
1023 * here and stop, unmap, free and del each of the linked
1d046793 1024 * requests instead of what we do now.
72246da4 1025 */
0fc9a1be
FB		 1026 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1027 req->direction);
72246da4
FB		 1028 list_del(&req->list);
1029 return ret;
1030 }
1031
1032 dep->flags |= DWC3_EP_BUSY;
25b8ff68 1033
f898ae09 1034 if (start_new) {
b4996a86 1035 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
f898ae09 1036 dep->number);
b4996a86 1037 WARN_ON_ONCE(!dep->resource_index);
f898ae09 1038 }
25b8ff68 1039
72246da4
FB		 1040 return 0;
1041}
1042
d6d6ec7b
PA		 1043static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1044 struct dwc3_ep *dep, u32 cur_uf)
1045{
1046 u32 uf;
1047
1048 if (list_empty(&dep->request_list)) {
73815280
FB		 1049 dwc3_trace(trace_dwc3_gadget,
1050 "ISOC ep %s run out for requests",
1051 dep->name);
f4a53c55 1052 dep->flags |= DWC3_EP_PENDING_REQUEST;
d6d6ec7b
PA		 1053 return;
1054 }
1055
1056 /* 4 micro frames in the future */
1057 uf = cur_uf + dep->interval * 4;
1058
1059 __dwc3_gadget_kick_transfer(dep, uf, 1);
1060}
1061
1062static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1063 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1064{
1065 u32 cur_uf, mask;
1066
1067 mask = ~(dep->interval - 1);
1068 cur_uf = event->parameters & mask;
1069
1070 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1071}
1072
72246da4
FB		 1073static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1074{
0fc9a1be
FB		 1075 struct dwc3 *dwc = dep->dwc;
1076 int ret;
1077
bb423984 1078 if (!dep->endpoint.desc) {
ec5e795c
FB		 1079 dwc3_trace(trace_dwc3_gadget,
1080 "trying to queue request %p to disabled %s\n",
bb423984
FB		 1081 &req->request, dep->endpoint.name);
1082 return -ESHUTDOWN;
1083 }
1084
1085 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1086 &req->request, req->dep->name)) {
ec5e795c
FB		 1087 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1088 &req->request, req->dep->name);
bb423984
FB		 1089 return -EINVAL;
1090 }
1091
72246da4
FB		 1092 req->request.actual = 0;
1093 req->request.status = -EINPROGRESS;
1094 req->direction = dep->direction;
1095 req->epnum = dep->number;
1096
fe84f522
FB		 1097 trace_dwc3_ep_queue(req);
1098
72246da4
FB		 1099 /*
1100 * We only add to our list of requests now and
1101 * start consuming the list once we get XferNotReady
1102 * IRQ.
1103 *
1104 * That way, we avoid doing anything that we don't need
1105 * to do now and defer it until the point we receive a
1106 * particular token from the Host side.
1107 *
1108 * This will also avoid Host cancelling URBs due to too
1d046793 1109 * many NAKs.
72246da4 1110 */
0fc9a1be
FB		 1111 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1112 dep->direction);
1113 if (ret)
1114 return ret;
1115
72246da4
FB		 1116 list_add_tail(&req->list, &dep->request_list);
1117
1d6a3918
FB		 1118 /*
1119 * If there are no pending requests and the endpoint isn't already
1120 * busy, we will just start the request straight away.
1121 *
1122 * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1123 * little bit faster.
1124 */
1125 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
62e345ae 1126 !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1d6a3918
FB		 1127 !(dep->flags & DWC3_EP_BUSY)) {
1128 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
a8f32817 1129 goto out;
1d6a3918
FB		 1130 }
1131
72246da4 1132 /*
b511e5e7 1133 * There are a few special cases:
72246da4 1134 *
f898ae09
PZ		 1135 * 1. XferNotReady with empty list of requests. We need to kick the
1136 * transfer here in that situation, otherwise we will be NAKing
1137 * forever. If we get XferNotReady before gadget driver has a
1138 * chance to queue a request, we will ACK the IRQ but won't be
1139 * able to receive the data until the next request is queued.
1140 * The following code is handling exactly that.
72246da4 1141 *
72246da4
FB		 1142 */
1143 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
f4a53c55
PA		 1144 /*
1145 * If xfernotready is already elapsed and it is a case
1146 * of isoc transfer, then issue END TRANSFER, so that
1147 * you can receive xfernotready again and can have
1148 * notion of current microframe.
1149 */
1150 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
cdc359dd 1151 if (list_empty(&dep->req_queued)) {
b992e681 1152 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 1153 dep->flags = DWC3_EP_ENABLED;
1154 }
f4a53c55
PA		 1155 return 0;
1156 }
1157
b511e5e7 1158 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
89185916
FB		 1159 if (!ret)
1160 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1161
a8f32817 1162 goto out;
b511e5e7 1163 }
72246da4 1164
b511e5e7
FB		 1165 /*
1166 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1167 * kick the transfer here after queuing a request, otherwise the
1168 * core may not see the modified TRB(s).
1169 */
1170 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
79c9046e
PA		 1171 (dep->flags & DWC3_EP_BUSY) &&
1172 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
b4996a86
FB		 1173 WARN_ON_ONCE(!dep->resource_index);
1174 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
b511e5e7 1175 false);
a8f32817 1176 goto out;
a0925324 1177 }
72246da4 1178
b997ada5
FB		 1179 /*
1180 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1181 * right away, otherwise host will not know we have streams to be
1182 * handled.
1183 */
a8f32817 1184 if (dep->stream_capable)
b997ada5 1185 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
b997ada5 1186
a8f32817
FB		 1187out:
1188 if (ret && ret != -EBUSY)
ec5e795c
FB		 1189 dwc3_trace(trace_dwc3_gadget,
1190 "%s: failed to kick transfers\n",
a8f32817
FB		 1191 dep->name);
1192 if (ret == -EBUSY)
1193 ret = 0;
1194
1195 return ret;
72246da4
FB		 1196}
1197
04c03d10
FB		 1198static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1199 struct usb_request *request)
1200{
1201 dwc3_gadget_ep_free_request(ep, request);
1202}
1203
1204static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1205{
1206 struct dwc3_request *req;
1207 struct usb_request *request;
1208 struct usb_ep *ep = &dep->endpoint;
1209
1210 dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1211 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1212 if (!request)
1213 return -ENOMEM;
1214
1215 request->length = 0;
1216 request->buf = dwc->zlp_buf;
1217 request->complete = __dwc3_gadget_ep_zlp_complete;
1218
1219 req = to_dwc3_request(request);
1220
1221 return __dwc3_gadget_ep_queue(dep, req);
1222}
1223
72246da4
FB		 1224static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1225 gfp_t gfp_flags)
1226{
1227 struct dwc3_request *req = to_dwc3_request(request);
1228 struct dwc3_ep *dep = to_dwc3_ep(ep);
1229 struct dwc3 *dwc = dep->dwc;
1230
1231 unsigned long flags;
1232
1233 int ret;
1234
fdee4eba 1235 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1236 ret = __dwc3_gadget_ep_queue(dep, req);
04c03d10
FB		 1237
1238 /*
1239 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1240 * setting request->zero, instead of doing magic, we will just queue an
1241 * extra usb_request ourselves so that it gets handled the same way as
1242 * any other request.
1243 */
d9261898
JY		 1244 if (ret == 0 && request->zero && request->length &&
1245 (request->length % ep->maxpacket == 0))
04c03d10
FB		 1246 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1247
72246da4
FB		 1248 spin_unlock_irqrestore(&dwc->lock, flags);
1249
1250 return ret;
1251}
1252
1253static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1254 struct usb_request *request)
1255{
1256 struct dwc3_request *req = to_dwc3_request(request);
1257 struct dwc3_request *r = NULL;
1258
1259 struct dwc3_ep *dep = to_dwc3_ep(ep);
1260 struct dwc3 *dwc = dep->dwc;
1261
1262 unsigned long flags;
1263 int ret = 0;
1264
2c4cbe6e
FB		 1265 trace_dwc3_ep_dequeue(req);
1266
72246da4
FB		 1267 spin_lock_irqsave(&dwc->lock, flags);
1268
1269 list_for_each_entry(r, &dep->request_list, list) {
1270 if (r == req)
1271 break;
1272 }
1273
1274 if (r != req) {
1275 list_for_each_entry(r, &dep->req_queued, list) {
1276 if (r == req)
1277 break;
1278 }
1279 if (r == req) {
1280 /* wait until it is processed */
b992e681 1281 dwc3_stop_active_transfer(dwc, dep->number, true);
e8d4e8be 1282 goto out1;
72246da4
FB		 1283 }
1284 dev_err(dwc->dev, "request %p was not queued to %s\n",
1285 request, ep->name);
1286 ret = -EINVAL;
1287 goto out0;
1288 }
1289
e8d4e8be 1290out1:
72246da4
FB		 1291 /* giveback the request */
1292 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1293
1294out0:
1295 spin_unlock_irqrestore(&dwc->lock, flags);
1296
1297 return ret;
1298}
1299
7a608559 1300int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
72246da4
FB		 1301{
1302 struct dwc3_gadget_ep_cmd_params params;
1303 struct dwc3 *dwc = dep->dwc;
1304 int ret;
1305
5ad02fb8
FB		 1306 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1307 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1308 return -EINVAL;
1309 }
1310
72246da4
FB		 1311 memset(&params, 0x00, sizeof(params));
1312
1313 if (value) {
7a608559
FB		 1314 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1315 (!list_empty(&dep->req_queued) ||
1316 !list_empty(&dep->request_list)))) {
ec5e795c
FB		 1317 dwc3_trace(trace_dwc3_gadget,
1318 "%s: pending request, cannot halt\n",
7a608559
FB		 1319 dep->name);
1320 return -EAGAIN;
1321 }
1322
72246da4
FB		 1323 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1324 DWC3_DEPCMD_SETSTALL, &params);
1325 if (ret)
3f89204b 1326 dev_err(dwc->dev, "failed to set STALL on %s\n",
72246da4
FB		 1327 dep->name);
1328 else
1329 dep->flags |= DWC3_EP_STALL;
1330 } else {
1331 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1332 DWC3_DEPCMD_CLEARSTALL, &params);
1333 if (ret)
3f89204b 1334 dev_err(dwc->dev, "failed to clear STALL on %s\n",
72246da4
FB		 1335 dep->name);
1336 else
a535d81c 1337 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
72246da4 1338 }
5275455a 1339
72246da4
FB		 1340 return ret;
1341}
1342
1343static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1344{
1345 struct dwc3_ep *dep = to_dwc3_ep(ep);
1346 struct dwc3 *dwc = dep->dwc;
1347
1348 unsigned long flags;
1349
1350 int ret;
1351
1352 spin_lock_irqsave(&dwc->lock, flags);
7a608559 1353 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
72246da4
FB		 1354 spin_unlock_irqrestore(&dwc->lock, flags);
1355
1356 return ret;
1357}
1358
1359static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1360{
1361 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1362 struct dwc3 *dwc = dep->dwc;
1363 unsigned long flags;
95aa4e8d 1364 int ret;
72246da4 1365
249a4569 1366 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1367 dep->flags |= DWC3_EP_WEDGE;
1368
08f0d966 1369 if (dep->number == 0 || dep->number == 1)
95aa4e8d 1370 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
08f0d966 1371 else
7a608559 1372 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
95aa4e8d
FB		 1373 spin_unlock_irqrestore(&dwc->lock, flags);
1374
1375 return ret;
72246da4
FB		 1376}
1377
1378/* -------------------------------------------------------------------------- */
1379
1380static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1381 .bLength = USB_DT_ENDPOINT_SIZE,
1382 .bDescriptorType = USB_DT_ENDPOINT,
1383 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1384};
1385
1386static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1387 .enable = dwc3_gadget_ep0_enable,
1388 .disable = dwc3_gadget_ep0_disable,
1389 .alloc_request = dwc3_gadget_ep_alloc_request,
1390 .free_request = dwc3_gadget_ep_free_request,
1391 .queue = dwc3_gadget_ep0_queue,
1392 .dequeue = dwc3_gadget_ep_dequeue,
08f0d966 1393 .set_halt = dwc3_gadget_ep0_set_halt,
72246da4
FB		 1394 .set_wedge = dwc3_gadget_ep_set_wedge,
1395};
1396
1397static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1398 .enable = dwc3_gadget_ep_enable,
1399 .disable = dwc3_gadget_ep_disable,
1400 .alloc_request = dwc3_gadget_ep_alloc_request,
1401 .free_request = dwc3_gadget_ep_free_request,
1402 .queue = dwc3_gadget_ep_queue,
1403 .dequeue = dwc3_gadget_ep_dequeue,
1404 .set_halt = dwc3_gadget_ep_set_halt,
1405 .set_wedge = dwc3_gadget_ep_set_wedge,
1406};
1407
1408/* -------------------------------------------------------------------------- */
1409
1410static int dwc3_gadget_get_frame(struct usb_gadget *g)
1411{
1412 struct dwc3 *dwc = gadget_to_dwc(g);
1413 u32 reg;
1414
1415 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1416 return DWC3_DSTS_SOFFN(reg);
1417}
1418
1419static int dwc3_gadget_wakeup(struct usb_gadget *g)
1420{
1421 struct dwc3 *dwc = gadget_to_dwc(g);
1422
1423 unsigned long timeout;
1424 unsigned long flags;
1425
1426 u32 reg;
1427
1428 int ret = 0;
1429
1430 u8 link_state;
1431 u8 speed;
1432
1433 spin_lock_irqsave(&dwc->lock, flags);
1434
1435 /*
1436 * According to the Databook Remote wakeup request should
1437 * be issued only when the device is in early suspend state.
1438 *
1439 * We can check that via USB Link State bits in DSTS register.
1440 */
1441 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1442
1443 speed = reg & DWC3_DSTS_CONNECTSPD;
ee5cd41c
JY		 1444 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1445 (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
ec5e795c 1446 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
72246da4
FB		 1447 ret = -EINVAL;
1448 goto out;
1449 }
1450
1451 link_state = DWC3_DSTS_USBLNKST(reg);
1452
1453 switch (link_state) {
1454 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1455 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1456 break;
1457 default:
ec5e795c
FB		 1458 dwc3_trace(trace_dwc3_gadget,
1459 "can't wakeup from '%s'\n",
1460 dwc3_gadget_link_string(link_state));
72246da4
FB		 1461 ret = -EINVAL;
1462 goto out;
1463 }
1464
8598bde7
FB		 1465 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1466 if (ret < 0) {
1467 dev_err(dwc->dev, "failed to put link in Recovery\n");
1468 goto out;
1469 }
72246da4 1470
802fde98
PZ		 1471 /* Recent versions do this automatically */
1472 if (dwc->revision < DWC3_REVISION_194A) {
1473 /* write zeroes to Link Change Request */
fcc023c7 1474 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1475 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1476 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1477 }
72246da4 1478
1d046793 1479 /* poll until Link State changes to ON */
72246da4
FB		 1480 timeout = jiffies + msecs_to_jiffies(100);
1481
1d046793 1482 while (!time_after(jiffies, timeout)) {
72246da4
FB		 1483 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1484
1485 /* in HS, means ON */
1486 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1487 break;
1488 }
1489
1490 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1491 dev_err(dwc->dev, "failed to send remote wakeup\n");
1492 ret = -EINVAL;
1493 }
1494
1495out:
1496 spin_unlock_irqrestore(&dwc->lock, flags);
1497
1498 return ret;
1499}
1500
1501static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1502 int is_selfpowered)
1503{
1504 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1505 unsigned long flags;
72246da4 1506
249a4569 1507 spin_lock_irqsave(&dwc->lock, flags);
bcdea503 1508 g->is_selfpowered = !!is_selfpowered;
249a4569 1509 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1510
1511 return 0;
1512}
1513
7b2a0368 1514static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
72246da4
FB		 1515{
1516 u32 reg;
61d58242 1517 u32 timeout = 500;
72246da4
FB		 1518
1519 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1520 if (is_on) {
802fde98
PZ		 1521 if (dwc->revision <= DWC3_REVISION_187A) {
1522 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1523 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1524 }
1525
1526 if (dwc->revision >= DWC3_REVISION_194A)
1527 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1528 reg |= DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1529
1530 if (dwc->has_hibernation)
1531 reg |= DWC3_DCTL_KEEP_CONNECT;
1532
9fcb3bd8 1533 dwc->pullups_connected = true;
8db7ed15 1534 } else {
72246da4 1535 reg &= ~DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1536
1537 if (dwc->has_hibernation && !suspend)
1538 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1539
9fcb3bd8 1540 dwc->pullups_connected = false;
8db7ed15 1541 }
72246da4
FB		 1542
1543 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1544
1545 do {
1546 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1547 if (is_on) {
1548 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1549 break;
1550 } else {
1551 if (reg & DWC3_DSTS_DEVCTRLHLT)
1552 break;
1553 }
72246da4
FB		 1554 timeout--;
1555 if (!timeout)
6f17f74b 1556 return -ETIMEDOUT;
61d58242 1557 udelay(1);
72246da4
FB		 1558 } while (1);
1559
73815280 1560 dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
72246da4
FB		 1561 dwc->gadget_driver
1562 ? dwc->gadget_driver->function : "no-function",
1563 is_on ? "connect" : "disconnect");
6f17f74b
PA		 1564
1565 return 0;
72246da4
FB		 1566}
1567
1568static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1569{
1570 struct dwc3 *dwc = gadget_to_dwc(g);
1571 unsigned long flags;
6f17f74b 1572 int ret;
72246da4
FB		 1573
1574 is_on = !!is_on;
1575
1576 spin_lock_irqsave(&dwc->lock, flags);
7b2a0368 1577 ret = dwc3_gadget_run_stop(dwc, is_on, false);
72246da4
FB		 1578 spin_unlock_irqrestore(&dwc->lock, flags);
1579
6f17f74b 1580 return ret;
72246da4
FB		 1581}
1582
8698e2ac
FB		 1583static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1584{
1585 u32 reg;
1586
1587 /* Enable all but Start and End of Frame IRQs */
1588 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1589 DWC3_DEVTEN_EVNTOVERFLOWEN |
1590 DWC3_DEVTEN_CMDCMPLTEN |
1591 DWC3_DEVTEN_ERRTICERREN |
1592 DWC3_DEVTEN_WKUPEVTEN |
1593 DWC3_DEVTEN_ULSTCNGEN |
1594 DWC3_DEVTEN_CONNECTDONEEN |
1595 DWC3_DEVTEN_USBRSTEN |
1596 DWC3_DEVTEN_DISCONNEVTEN);
1597
1598 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1599}
1600
1601static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1602{
1603 /* mask all interrupts */
1604 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1605}
1606
1607static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
b15a762f 1608static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
8698e2ac 1609
72246da4
FB		 1610static int dwc3_gadget_start(struct usb_gadget *g,
1611 struct usb_gadget_driver *driver)
1612{
1613 struct dwc3 *dwc = gadget_to_dwc(g);
1614 struct dwc3_ep *dep;
1615 unsigned long flags;
1616 int ret = 0;
8698e2ac 1617 int irq;
72246da4
FB		 1618 u32 reg;
1619
b0d7ffd4
FB		 1620 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1621 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
e8adfc30 1622 IRQF_SHARED, "dwc3", dwc);
b0d7ffd4
FB		 1623 if (ret) {
1624 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1625 irq, ret);
1626 goto err0;
1627 }
1628
72246da4
FB		 1629 spin_lock_irqsave(&dwc->lock, flags);
1630
1631 if (dwc->gadget_driver) {
1632 dev_err(dwc->dev, "%s is already bound to %s\n",
1633 dwc->gadget.name,
1634 dwc->gadget_driver->driver.name);
1635 ret = -EBUSY;
b0d7ffd4 1636 goto err1;
72246da4
FB		 1637 }
1638
1639 dwc->gadget_driver = driver;
72246da4 1640
72246da4
FB		 1641 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1642 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1643
1644 /**
1645 * WORKAROUND: DWC3 revision < 2.20a have an issue
1646 * which would cause metastability state on Run/Stop
1647 * bit if we try to force the IP to USB2-only mode.
1648 *
1649 * Because of that, we cannot configure the IP to any
1650 * speed other than the SuperSpeed
1651 *
1652 * Refers to:
1653 *
1654 * STAR#9000525659: Clock Domain Crossing on DCTL in
1655 * USB 2.0 Mode
1656 */
f7e846f0 1657 if (dwc->revision < DWC3_REVISION_220A) {
07e7f47b 1658 reg |= DWC3_DCFG_SUPERSPEED;
f7e846f0
FB		 1659 } else {
1660 switch (dwc->maximum_speed) {
1661 case USB_SPEED_LOW:
1662 reg |= DWC3_DSTS_LOWSPEED;
1663 break;
1664 case USB_SPEED_FULL:
1665 reg |= DWC3_DSTS_FULLSPEED1;
1666 break;
1667 case USB_SPEED_HIGH:
1668 reg |= DWC3_DSTS_HIGHSPEED;
1669 break;
1670 case USB_SPEED_SUPER: /* FALLTHROUGH */
1671 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1672 default:
1673 reg |= DWC3_DSTS_SUPERSPEED;
1674 }
1675 }
72246da4
FB		 1676 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1677
1678 /* Start with SuperSpeed Default */
1679 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1680
1681 dep = dwc->eps[0];
265b70a7
PZ		 1682 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1683 false);
72246da4
FB		 1684 if (ret) {
1685 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
b0d7ffd4 1686 goto err2;
72246da4
FB		 1687 }
1688
1689 dep = dwc->eps[1];
265b70a7
PZ		 1690 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1691 false);
72246da4
FB		 1692 if (ret) {
1693 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
b0d7ffd4 1694 goto err3;
72246da4
FB		 1695 }
1696
1697 /* begin to receive SETUP packets */
c7fcdeb2 1698 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1699 dwc3_ep0_out_start(dwc);
1700
8698e2ac
FB		 1701 dwc3_gadget_enable_irq(dwc);
1702
72246da4
FB		 1703 spin_unlock_irqrestore(&dwc->lock, flags);
1704
1705 return 0;
1706
b0d7ffd4 1707err3:
72246da4
FB		 1708 __dwc3_gadget_ep_disable(dwc->eps[0]);
1709
b0d7ffd4 1710err2:
cdcedd69 1711 dwc->gadget_driver = NULL;
b0d7ffd4
FB		 1712
1713err1:
72246da4
FB		 1714 spin_unlock_irqrestore(&dwc->lock, flags);
1715
b0d7ffd4
FB		 1716 free_irq(irq, dwc);
1717
1718err0:
72246da4
FB		 1719 return ret;
1720}
1721
22835b80 1722static int dwc3_gadget_stop(struct usb_gadget *g)
72246da4
FB		 1723{
1724 struct dwc3 *dwc = gadget_to_dwc(g);
1725 unsigned long flags;
8698e2ac 1726 int irq;
72246da4
FB		 1727
1728 spin_lock_irqsave(&dwc->lock, flags);
1729
8698e2ac 1730 dwc3_gadget_disable_irq(dwc);
72246da4
FB		 1731 __dwc3_gadget_ep_disable(dwc->eps[0]);
1732 __dwc3_gadget_ep_disable(dwc->eps[1]);
1733
1734 dwc->gadget_driver = NULL;
72246da4
FB		 1735
1736 spin_unlock_irqrestore(&dwc->lock, flags);
1737
b0d7ffd4
FB		 1738 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1739 free_irq(irq, dwc);
1740
72246da4
FB		 1741 return 0;
1742}
802fde98 1743
72246da4
FB		 1744static const struct usb_gadget_ops dwc3_gadget_ops = {
1745 .get_frame = dwc3_gadget_get_frame,
1746 .wakeup = dwc3_gadget_wakeup,
1747 .set_selfpowered = dwc3_gadget_set_selfpowered,
1748 .pullup = dwc3_gadget_pullup,
1749 .udc_start = dwc3_gadget_start,
1750 .udc_stop = dwc3_gadget_stop,
1751};
1752
1753/* -------------------------------------------------------------------------- */
1754
6a1e3ef4
FB		 1755static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1756 u8 num, u32 direction)
72246da4
FB		 1757{
1758 struct dwc3_ep *dep;
6a1e3ef4 1759 u8 i;
72246da4 1760
6a1e3ef4
FB		 1761 for (i = 0; i < num; i++) {
1762 u8 epnum = (i << 1) | (!!direction);
72246da4 1763
72246da4 1764 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
734d5a53 1765 if (!dep)
72246da4 1766 return -ENOMEM;
72246da4
FB		 1767
1768 dep->dwc = dwc;
1769 dep->number = epnum;
9aa62ae4 1770 dep->direction = !!direction;
72246da4
FB		 1771 dwc->eps[epnum] = dep;
1772
1773 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1774 (epnum & 1) ? "in" : "out");
6a1e3ef4 1775
72246da4 1776 dep->endpoint.name = dep->name;
72246da4 1777
73815280 1778 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
653df35e 1779
72246da4 1780 if (epnum == 0 || epnum == 1) {
e117e742 1781 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
6048e4c6 1782 dep->endpoint.maxburst = 1;
72246da4
FB		 1783 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1784 if (!epnum)
1785 dwc->gadget.ep0 = &dep->endpoint;
1786 } else {
1787 int ret;
1788
e117e742 1789 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
12d36c16 1790 dep->endpoint.max_streams = 15;
72246da4
FB		 1791 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1792 list_add_tail(&dep->endpoint.ep_list,
1793 &dwc->gadget.ep_list);
1794
1795 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 1796 if (ret)
72246da4 1797 return ret;
72246da4 1798 }
25b8ff68 1799
a474d3b7
RB		 1800 if (epnum == 0 || epnum == 1) {
1801 dep->endpoint.caps.type_control = true;
1802 } else {
1803 dep->endpoint.caps.type_iso = true;
1804 dep->endpoint.caps.type_bulk = true;
1805 dep->endpoint.caps.type_int = true;
1806 }
1807
1808 dep->endpoint.caps.dir_in = !!direction;
1809 dep->endpoint.caps.dir_out = !direction;
1810
72246da4
FB		 1811 INIT_LIST_HEAD(&dep->request_list);
1812 INIT_LIST_HEAD(&dep->req_queued);
1813 }
1814
1815 return 0;
1816}
1817
6a1e3ef4
FB		 1818static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1819{
1820 int ret;
1821
1822 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1823
1824 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1825 if (ret < 0) {
73815280
FB		 1826 dwc3_trace(trace_dwc3_gadget,
1827 "failed to allocate OUT endpoints");
6a1e3ef4
FB		 1828 return ret;
1829 }
1830
1831 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1832 if (ret < 0) {
73815280
FB		 1833 dwc3_trace(trace_dwc3_gadget,
1834 "failed to allocate IN endpoints");
6a1e3ef4
FB		 1835 return ret;
1836 }
1837
1838 return 0;
1839}
1840
72246da4
FB		 1841static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1842{
1843 struct dwc3_ep *dep;
1844 u8 epnum;
1845
1846 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1847 dep = dwc->eps[epnum];
6a1e3ef4
FB		 1848 if (!dep)
1849 continue;
5bf8fae3
GC		 1850 /*
1851 * Physical endpoints 0 and 1 are special; they form the
1852 * bi-directional USB endpoint 0.
1853 *
1854 * For those two physical endpoints, we don't allocate a TRB
1855 * pool nor do we add them the endpoints list. Due to that, we
1856 * shouldn't do these two operations otherwise we would end up
1857 * with all sorts of bugs when removing dwc3.ko.
1858 */
1859 if (epnum != 0 && epnum != 1) {
1860 dwc3_free_trb_pool(dep);
72246da4 1861 list_del(&dep->endpoint.ep_list);
5bf8fae3 1862 }
72246da4
FB		 1863
1864 kfree(dep);
1865 }
1866}
1867
72246da4 1868/* -------------------------------------------------------------------------- */
e5caff68 1869
e5ba5ec8
PA		 1870static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1871 struct dwc3_request *req, struct dwc3_trb *trb,
72246da4
FB		 1872 const struct dwc3_event_depevt *event, int status)
1873{
72246da4
FB		 1874 unsigned int count;
1875 unsigned int s_pkt = 0;
d6d6ec7b 1876 unsigned int trb_status;
72246da4 1877
2c4cbe6e
FB		 1878 trace_dwc3_complete_trb(dep, trb);
1879
e5ba5ec8
PA		 1880 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1881 /*
1882 * We continue despite the error. There is not much we
1883 * can do. If we don't clean it up we loop forever. If
1884 * we skip the TRB then it gets overwritten after a
1885 * while since we use them in a ring buffer. A BUG()
1886 * would help. Lets hope that if this occurs, someone
1887 * fixes the root cause instead of looking away :)
1888 */
1889 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1890 dep->name, trb);
1891 count = trb->size & DWC3_TRB_SIZE_MASK;
1892
1893 if (dep->direction) {
1894 if (count) {
1895 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1896 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
ec5e795c
FB		 1897 dwc3_trace(trace_dwc3_gadget,
1898 "%s: incomplete IN transfer\n",
e5ba5ec8
PA		 1899 dep->name);
1900 /*
1901 * If missed isoc occurred and there is
1902 * no request queued then issue END
1903 * TRANSFER, so that core generates
1904 * next xfernotready and we will issue
1905 * a fresh START TRANSFER.
1906 * If there are still queued request
1907 * then wait, do not issue either END
1908 * or UPDATE TRANSFER, just attach next
1909 * request in request_list during
1910 * giveback.If any future queued request
1911 * is successfully transferred then we
1912 * will issue UPDATE TRANSFER for all
1913 * request in the request_list.
1914 */
1915 dep->flags |= DWC3_EP_MISSED_ISOC;
1916 } else {
1917 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1918 dep->name);
1919 status = -ECONNRESET;
1920 }
1921 } else {
1922 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1923 }
1924 } else {
1925 if (count && (event->status & DEPEVT_STATUS_SHORT))
1926 s_pkt = 1;
1927 }
1928
1929 /*
1930 * We assume here we will always receive the entire data block
1931 * which we should receive. Meaning, if we program RX to
1932 * receive 4K but we receive only 2K, we assume that's all we
1933 * should receive and we simply bounce the request back to the
1934 * gadget driver for further processing.
1935 */
1936 req->request.actual += req->request.length - count;
1937 if (s_pkt)
1938 return 1;
1939 if ((event->status & DEPEVT_STATUS_LST) &&
1940 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1941 DWC3_TRB_CTRL_HWO)))
1942 return 1;
1943 if ((event->status & DEPEVT_STATUS_IOC) &&
1944 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1945 return 1;
1946 return 0;
1947}
1948
1949static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1950 const struct dwc3_event_depevt *event, int status)
1951{
1952 struct dwc3_request *req;
1953 struct dwc3_trb *trb;
1954 unsigned int slot;
1955 unsigned int i;
1956 int ret;
1957
72246da4 1958 do {
d115d705 1959 req = next_request(&dep->req_queued);
ac7bdcc1 1960 if (WARN_ON_ONCE(!req))
d115d705 1961 return 1;
ac7bdcc1 1962
d115d705
VS		 1963 i = 0;
1964 do {
1965 slot = req->start_slot + i;
1966 if ((slot == DWC3_TRB_NUM - 1) &&
e5ba5ec8 1967 usb_endpoint_xfer_isoc(dep->endpoint.desc))
d115d705
VS		 1968 slot++;
1969 slot %= DWC3_TRB_NUM;
1970 trb = &dep->trb_pool[slot];
1971
1972 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1973 event, status);
1974 if (ret)
1975 break;
1976 } while (++i < req->request.num_mapped_sgs);
1977
1978 dwc3_gadget_giveback(dep, req, status);
e5ba5ec8
PA		 1979
1980 if (ret)
72246da4 1981 break;
d115d705 1982 } while (1);
72246da4 1983
cdc359dd
PA		 1984 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1985 list_empty(&dep->req_queued)) {
1986 if (list_empty(&dep->request_list)) {
1987 /*
1988 * If there is no entry in request list then do
1989 * not issue END TRANSFER now. Just set PENDING
1990 * flag, so that END TRANSFER is issued when an
1991 * entry is added into request list.
1992 */
1993 dep->flags = DWC3_EP_PENDING_REQUEST;
1994 } else {
b992e681 1995 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 1996 dep->flags = DWC3_EP_ENABLED;
1997 }
7efea86c
PA		 1998 return 1;
1999 }
2000
72246da4
FB		 2001 return 1;
2002}
2003
2004static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
029d97ff 2005 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
72246da4
FB		 2006{
2007 unsigned status = 0;
2008 int clean_busy;
e18b7975
FB		 2009 u32 is_xfer_complete;
2010
2011 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
72246da4
FB		 2012
2013 if (event->status & DEPEVT_STATUS_BUSERR)
2014 status = -ECONNRESET;
2015
1d046793 2016 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
e18b7975
FB		 2017 if (clean_busy && (is_xfer_complete ||
2018 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
72246da4 2019 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 2020
2021 /*
2022 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2023 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2024 */
2025 if (dwc->revision < DWC3_REVISION_183A) {
2026 u32 reg;
2027 int i;
2028
2029 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
348e026f 2030 dep = dwc->eps[i];
fae2b904
FB		 2031
2032 if (!(dep->flags & DWC3_EP_ENABLED))
2033 continue;
2034
2035 if (!list_empty(&dep->req_queued))
2036 return;
2037 }
2038
2039 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2040 reg |= dwc->u1u2;
2041 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2042
2043 dwc->u1u2 = 0;
2044 }
8a1a9c9e 2045
e6e709b7 2046 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8a1a9c9e
FB		 2047 int ret;
2048
e6e709b7 2049 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
8a1a9c9e
FB		 2050 if (!ret || ret == -EBUSY)
2051 return;
2052 }
72246da4
FB		 2053}
2054
72246da4
FB		 2055static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2056 const struct dwc3_event_depevt *event)
2057{
2058 struct dwc3_ep *dep;
2059 u8 epnum = event->endpoint_number;
2060
2061 dep = dwc->eps[epnum];
2062
3336abb5
FB		 2063 if (!(dep->flags & DWC3_EP_ENABLED))
2064 return;
2065
72246da4
FB		 2066 if (epnum == 0 || epnum == 1) {
2067 dwc3_ep0_interrupt(dwc, event);
2068 return;
2069 }
2070
2071 switch (event->endpoint_event) {
2072 case DWC3_DEPEVT_XFERCOMPLETE:
b4996a86 2073 dep->resource_index = 0;
c2df85ca 2074
16e78db7 2075 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
ec5e795c
FB		 2076 dwc3_trace(trace_dwc3_gadget,
2077 "%s is an Isochronous endpoint\n",
72246da4
FB		 2078 dep->name);
2079 return;
2080 }
2081
029d97ff 2082 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2083 break;
2084 case DWC3_DEPEVT_XFERINPROGRESS:
029d97ff 2085 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2086 break;
2087 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 2088 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 2089 dwc3_gadget_start_isoc(dwc, dep, event);
2090 } else {
6bb4fe12 2091 int active;
72246da4
FB		 2092 int ret;
2093
6bb4fe12
FB		 2094 active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2095
73815280 2096 dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
6bb4fe12 2097 dep->name, active ? "Transfer Active"
72246da4
FB		 2098 : "Transfer Not Active");
2099
6bb4fe12 2100 ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
72246da4
FB		 2101 if (!ret || ret == -EBUSY)
2102 return;
2103
ec5e795c
FB		 2104 dwc3_trace(trace_dwc3_gadget,
2105 "%s: failed to kick transfers\n",
72246da4
FB		 2106 dep->name);
2107 }
2108
879631aa
FB		 2109 break;
2110 case DWC3_DEPEVT_STREAMEVT:
16e78db7 2111 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 2112 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2113 dep->name);
2114 return;
2115 }
2116
2117 switch (event->status) {
2118 case DEPEVT_STREAMEVT_FOUND:
73815280
FB		 2119 dwc3_trace(trace_dwc3_gadget,
2120 "Stream %d found and started",
879631aa
FB		 2121 event->parameters);
2122
2123 break;
2124 case DEPEVT_STREAMEVT_NOTFOUND:
2125 /* FALLTHROUGH */
2126 default:
ec5e795c
FB		 2127 dwc3_trace(trace_dwc3_gadget,
2128 "unable to find suitable stream\n");
879631aa 2129 }
72246da4
FB		 2130 break;
2131 case DWC3_DEPEVT_RXTXFIFOEVT:
ec5e795c 2132 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
72246da4 2133 break;
72246da4 2134 case DWC3_DEPEVT_EPCMDCMPLT:
73815280 2135 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
72246da4
FB		 2136 break;
2137 }
2138}
2139
2140static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2141{
2142 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2143 spin_unlock(&dwc->lock);
2144 dwc->gadget_driver->disconnect(&dwc->gadget);
2145 spin_lock(&dwc->lock);
2146 }
2147}
2148
bc5ba2e0
FB		 2149static void dwc3_suspend_gadget(struct dwc3 *dwc)
2150{
73a30bfc 2151 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
bc5ba2e0
FB		 2152 spin_unlock(&dwc->lock);
2153 dwc->gadget_driver->suspend(&dwc->gadget);
2154 spin_lock(&dwc->lock);
2155 }
2156}
2157
2158static void dwc3_resume_gadget(struct dwc3 *dwc)
2159{
73a30bfc 2160 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
bc5ba2e0
FB		 2161 spin_unlock(&dwc->lock);
2162 dwc->gadget_driver->resume(&dwc->gadget);
5c7b3b02 2163 spin_lock(&dwc->lock);
8e74475b
FB		 2164 }
2165}
2166
2167static void dwc3_reset_gadget(struct dwc3 *dwc)
2168{
2169 if (!dwc->gadget_driver)
2170 return;
2171
2172 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2173 spin_unlock(&dwc->lock);
2174 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
bc5ba2e0
FB		 2175 spin_lock(&dwc->lock);
2176 }
2177}
2178
b992e681 2179static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
72246da4
FB		 2180{
2181 struct dwc3_ep *dep;
2182 struct dwc3_gadget_ep_cmd_params params;
2183 u32 cmd;
2184 int ret;
2185
2186 dep = dwc->eps[epnum];
2187
b4996a86 2188 if (!dep->resource_index)
3daf74d7
PA		 2189 return;
2190
57911504
PA		 2191 /*
2192 * NOTICE: We are violating what the Databook says about the
2193 * EndTransfer command. Ideally we would _always_ wait for the
2194 * EndTransfer Command Completion IRQ, but that's causing too
2195 * much trouble synchronizing between us and gadget driver.
2196 *
2197 * We have discussed this with the IP Provider and it was
2198 * suggested to giveback all requests here, but give HW some
2199 * extra time to synchronize with the interconnect. We're using
dc93b41a 2200 * an arbitrary 100us delay for that.
57911504
PA		 2201 *
2202 * Note also that a similar handling was tested by Synopsys
2203 * (thanks a lot Paul) and nothing bad has come out of it.
2204 * In short, what we're doing is:
2205 *
2206 * - Issue EndTransfer WITH CMDIOC bit set
2207 * - Wait 100us
2208 */
2209
3daf74d7 2210 cmd = DWC3_DEPCMD_ENDTRANSFER;
b992e681
PZ		 2211 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2212 cmd |= DWC3_DEPCMD_CMDIOC;
b4996a86 2213 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3daf74d7
PA		 2214 memset(&params, 0, sizeof(params));
2215 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2216 WARN_ON_ONCE(ret);
b4996a86 2217 dep->resource_index = 0;
041d81f4 2218 dep->flags &= ~DWC3_EP_BUSY;
57911504 2219 udelay(100);
72246da4
FB		 2220}
2221
2222static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2223{
2224 u32 epnum;
2225
2226 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2227 struct dwc3_ep *dep;
2228
2229 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2230 if (!dep)
2231 continue;
2232
72246da4
FB		 2233 if (!(dep->flags & DWC3_EP_ENABLED))
2234 continue;
2235
624407f9 2236 dwc3_remove_requests(dwc, dep);
72246da4
FB		 2237 }
2238}
2239
2240static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2241{
2242 u32 epnum;
2243
2244 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2245 struct dwc3_ep *dep;
2246 struct dwc3_gadget_ep_cmd_params params;
2247 int ret;
2248
2249 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2250 if (!dep)
2251 continue;
72246da4
FB		 2252
2253 if (!(dep->flags & DWC3_EP_STALL))
2254 continue;
2255
2256 dep->flags &= ~DWC3_EP_STALL;
2257
2258 memset(&params, 0, sizeof(params));
2259 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2260 DWC3_DEPCMD_CLEARSTALL, &params);
2261 WARN_ON_ONCE(ret);
2262 }
2263}
2264
2265static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2266{
c4430a26
FB		 2267 int reg;
2268
72246da4
FB		 2269 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2270 reg &= ~DWC3_DCTL_INITU1ENA;
2271 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2272
2273 reg &= ~DWC3_DCTL_INITU2ENA;
2274 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 2275
72246da4
FB		 2276 dwc3_disconnect_gadget(dwc);
2277
2278 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 2279 dwc->setup_packet_pending = false;
06a374ed 2280 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
72246da4
FB		 2281}
2282
72246da4
FB		 2283static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2284{
2285 u32 reg;
2286
df62df56
FB		 2287 /*
2288 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2289 * would cause a missing Disconnect Event if there's a
2290 * pending Setup Packet in the FIFO.
2291 *
2292 * There's no suggested workaround on the official Bug
2293 * report, which states that "unless the driver/application
2294 * is doing any special handling of a disconnect event,
2295 * there is no functional issue".
2296 *
2297 * Unfortunately, it turns out that we _do_ some special
2298 * handling of a disconnect event, namely complete all
2299 * pending transfers, notify gadget driver of the
2300 * disconnection, and so on.
2301 *
2302 * Our suggested workaround is to follow the Disconnect
2303 * Event steps here, instead, based on a setup_packet_pending
b5d335e5
FB		 2304 * flag. Such flag gets set whenever we have a SETUP_PENDING
2305 * status for EP0 TRBs and gets cleared on XferComplete for the
df62df56
FB		 2306 * same endpoint.
2307 *
2308 * Refers to:
2309 *
2310 * STAR#9000466709: RTL: Device : Disconnect event not
2311 * generated if setup packet pending in FIFO
2312 */
2313 if (dwc->revision < DWC3_REVISION_188A) {
2314 if (dwc->setup_packet_pending)
2315 dwc3_gadget_disconnect_interrupt(dwc);
2316 }
2317
8e74475b 2318 dwc3_reset_gadget(dwc);
72246da4
FB		 2319
2320 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2321 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2322 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2323 dwc->test_mode = false;
72246da4
FB		 2324
2325 dwc3_stop_active_transfers(dwc);
2326 dwc3_clear_stall_all_ep(dwc);
2327
2328 /* Reset device address to zero */
2329 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2330 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2331 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2332}
2333
2334static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2335{
2336 u32 reg;
2337 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2338
2339 /*
2340 * We change the clock only at SS but I dunno why I would want to do
2341 * this. Maybe it becomes part of the power saving plan.
2342 */
2343
ee5cd41c
JY		 2344 if ((speed != DWC3_DSTS_SUPERSPEED) &&
2345 (speed != DWC3_DSTS_SUPERSPEED_PLUS))
72246da4
FB		 2346 return;
2347
2348 /*
2349 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2350 * each time on Connect Done.
2351 */
2352 if (!usb30_clock)
2353 return;
2354
2355 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2356 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2357 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2358}
2359
72246da4
FB		 2360static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2361{
72246da4
FB		 2362 struct dwc3_ep *dep;
2363 int ret;
2364 u32 reg;
2365 u8 speed;
2366
72246da4
FB		 2367 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2368 speed = reg & DWC3_DSTS_CONNECTSPD;
2369 dwc->speed = speed;
2370
2371 dwc3_update_ram_clk_sel(dwc, speed);
2372
2373 switch (speed) {
2374 case DWC3_DCFG_SUPERSPEED:
05870c5b
FB		 2375 /*
2376 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2377 * would cause a missing USB3 Reset event.
2378 *
2379 * In such situations, we should force a USB3 Reset
2380 * event by calling our dwc3_gadget_reset_interrupt()
2381 * routine.
2382 *
2383 * Refers to:
2384 *
2385 * STAR#9000483510: RTL: SS : USB3 reset event may
2386 * not be generated always when the link enters poll
2387 */
2388 if (dwc->revision < DWC3_REVISION_190A)
2389 dwc3_gadget_reset_interrupt(dwc);
2390
72246da4
FB		 2391 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2392 dwc->gadget.ep0->maxpacket = 512;
2393 dwc->gadget.speed = USB_SPEED_SUPER;
2394 break;
2395 case DWC3_DCFG_HIGHSPEED:
2396 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2397 dwc->gadget.ep0->maxpacket = 64;
2398 dwc->gadget.speed = USB_SPEED_HIGH;
2399 break;
2400 case DWC3_DCFG_FULLSPEED2:
2401 case DWC3_DCFG_FULLSPEED1:
2402 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2403 dwc->gadget.ep0->maxpacket = 64;
2404 dwc->gadget.speed = USB_SPEED_FULL;
2405 break;
2406 case DWC3_DCFG_LOWSPEED:
2407 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2408 dwc->gadget.ep0->maxpacket = 8;
2409 dwc->gadget.speed = USB_SPEED_LOW;
2410 break;
2411 }
2412
2b758350
PA		 2413 /* Enable USB2 LPM Capability */
2414
ee5cd41c
JY		 2415 if ((dwc->revision > DWC3_REVISION_194A) &&
2416 (speed != DWC3_DCFG_SUPERSPEED) &&
2417 (speed != DWC3_DCFG_SUPERSPEED_PLUS)) {
2b758350
PA		 2418 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2419 reg |= DWC3_DCFG_LPM_CAP;
2420 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2421
2422 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2423 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2424
460d098c 2425 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2b758350 2426
80caf7d2
HR		 2427 /*
2428 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2429 * DCFG.LPMCap is set, core responses with an ACK and the
2430 * BESL value in the LPM token is less than or equal to LPM
2431 * NYET threshold.
2432 */
2433 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2434 && dwc->has_lpm_erratum,
2435 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2436
2437 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2438 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2439
356363bf
FB		 2440 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2441 } else {
2442 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2443 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2b758350
PA		 2444 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2445 }
2446
72246da4 2447 dep = dwc->eps[0];
265b70a7
PZ		 2448 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2449 false);
72246da4
FB		 2450 if (ret) {
2451 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2452 return;
2453 }
2454
2455 dep = dwc->eps[1];
265b70a7
PZ		 2456 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2457 false);
72246da4
FB		 2458 if (ret) {
2459 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2460 return;
2461 }
2462
2463 /*
2464 * Configure PHY via GUSB3PIPECTLn if required.
2465 *
2466 * Update GTXFIFOSIZn
2467 *
2468 * In both cases reset values should be sufficient.
2469 */
2470}
2471
2472static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2473{
72246da4
FB		 2474 /*
2475 * TODO take core out of low power mode when that's
2476 * implemented.
2477 */
2478
2479 dwc->gadget_driver->resume(&dwc->gadget);
2480}
2481
2482static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2483 unsigned int evtinfo)
2484{
fae2b904 2485 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
0b0cc1cd
FB		 2486 unsigned int pwropt;
2487
2488 /*
2489 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2490 * Hibernation mode enabled which would show up when device detects
2491 * host-initiated U3 exit.
2492 *
2493 * In that case, device will generate a Link State Change Interrupt
2494 * from U3 to RESUME which is only necessary if Hibernation is
2495 * configured in.
2496 *
2497 * There are no functional changes due to such spurious event and we
2498 * just need to ignore it.
2499 *
2500 * Refers to:
2501 *
2502 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2503 * operational mode
2504 */
2505 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2506 if ((dwc->revision < DWC3_REVISION_250A) &&
2507 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2508 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2509 (next == DWC3_LINK_STATE_RESUME)) {
73815280
FB		 2510 dwc3_trace(trace_dwc3_gadget,
2511 "ignoring transition U3 -> Resume");
0b0cc1cd
FB		 2512 return;
2513 }
2514 }
fae2b904
FB		 2515
2516 /*
2517 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2518 * on the link partner, the USB session might do multiple entry/exit
2519 * of low power states before a transfer takes place.
2520 *
2521 * Due to this problem, we might experience lower throughput. The
2522 * suggested workaround is to disable DCTL[12:9] bits if we're
2523 * transitioning from U1/U2 to U0 and enable those bits again
2524 * after a transfer completes and there are no pending transfers
2525 * on any of the enabled endpoints.
2526 *
2527 * This is the first half of that workaround.
2528 *
2529 * Refers to:
2530 *
2531 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2532 * core send LGO_Ux entering U0
2533 */
2534 if (dwc->revision < DWC3_REVISION_183A) {
2535 if (next == DWC3_LINK_STATE_U0) {
2536 u32 u1u2;
2537 u32 reg;
2538
2539 switch (dwc->link_state) {
2540 case DWC3_LINK_STATE_U1:
2541 case DWC3_LINK_STATE_U2:
2542 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2543 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2544 | DWC3_DCTL_ACCEPTU2ENA
2545 | DWC3_DCTL_INITU1ENA
2546 | DWC3_DCTL_ACCEPTU1ENA);
2547
2548 if (!dwc->u1u2)
2549 dwc->u1u2 = reg & u1u2;
2550
2551 reg &= ~u1u2;
2552
2553 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2554 break;
2555 default:
2556 /* do nothing */
2557 break;
2558 }
2559 }
2560 }
2561
bc5ba2e0
FB		 2562 switch (next) {
2563 case DWC3_LINK_STATE_U1:
2564 if (dwc->speed == USB_SPEED_SUPER)
2565 dwc3_suspend_gadget(dwc);
2566 break;
2567 case DWC3_LINK_STATE_U2:
2568 case DWC3_LINK_STATE_U3:
2569 dwc3_suspend_gadget(dwc);
2570 break;
2571 case DWC3_LINK_STATE_RESUME:
2572 dwc3_resume_gadget(dwc);
2573 break;
2574 default:
2575 /* do nothing */
2576 break;
2577 }
2578
e57ebc1d 2579 dwc->link_state = next;
72246da4
FB		 2580}
2581
e1dadd3b
FB		 2582static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2583 unsigned int evtinfo)
2584{
2585 unsigned int is_ss = evtinfo & BIT(4);
2586
2587 /**
2588 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2589 * have a known issue which can cause USB CV TD.9.23 to fail
2590 * randomly.
2591 *
2592 * Because of this issue, core could generate bogus hibernation
2593 * events which SW needs to ignore.
2594 *
2595 * Refers to:
2596 *
2597 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2598 * Device Fallback from SuperSpeed
2599 */
2600 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2601 return;
2602
2603 /* enter hibernation here */
2604}
2605
72246da4
FB		 2606static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2607 const struct dwc3_event_devt *event)
2608{
2609 switch (event->type) {
2610 case DWC3_DEVICE_EVENT_DISCONNECT:
2611 dwc3_gadget_disconnect_interrupt(dwc);
2612 break;
2613 case DWC3_DEVICE_EVENT_RESET:
2614 dwc3_gadget_reset_interrupt(dwc);
2615 break;
2616 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2617 dwc3_gadget_conndone_interrupt(dwc);
2618 break;
2619 case DWC3_DEVICE_EVENT_WAKEUP:
2620 dwc3_gadget_wakeup_interrupt(dwc);
2621 break;
e1dadd3b
FB		 2622 case DWC3_DEVICE_EVENT_HIBER_REQ:
2623 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2624 "unexpected hibernation event\n"))
2625 break;
2626
2627 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2628 break;
72246da4
FB		 2629 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2630 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2631 break;
2632 case DWC3_DEVICE_EVENT_EOPF:
73815280 2633 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
72246da4
FB		 2634 break;
2635 case DWC3_DEVICE_EVENT_SOF:
73815280 2636 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
72246da4
FB		 2637 break;
2638 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
73815280 2639 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
72246da4
FB		 2640 break;
2641 case DWC3_DEVICE_EVENT_CMD_CMPL:
73815280 2642 dwc3_trace(trace_dwc3_gadget, "Command Complete");
72246da4
FB		 2643 break;
2644 case DWC3_DEVICE_EVENT_OVERFLOW:
73815280 2645 dwc3_trace(trace_dwc3_gadget, "Overflow");
72246da4
FB		 2646 break;
2647 default:
e9f2aa87 2648 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
72246da4
FB		 2649 }
2650}
2651
2652static void dwc3_process_event_entry(struct dwc3 *dwc,
2653 const union dwc3_event *event)
2654{
2c4cbe6e
FB		 2655 trace_dwc3_event(event->raw);
2656
72246da4
FB		 2657 /* Endpoint IRQ, handle it and return early */
2658 if (event->type.is_devspec == 0) {
2659 /* depevt */
2660 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2661 }
2662
2663 switch (event->type.type) {
2664 case DWC3_EVENT_TYPE_DEV:
2665 dwc3_gadget_interrupt(dwc, &event->devt);
2666 break;
2667 /* REVISIT what to do with Carkit and I2C events ? */
2668 default:
2669 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2670 }
2671}
2672
f42f2447 2673static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
b15a762f 2674{
f42f2447 2675 struct dwc3_event_buffer *evt;
b15a762f 2676 irqreturn_t ret = IRQ_NONE;
f42f2447 2677 int left;
e8adfc30 2678 u32 reg;
b15a762f 2679
f42f2447
FB		 2680 evt = dwc->ev_buffs[buf];
2681 left = evt->count;
b15a762f 2682
f42f2447
FB		 2683 if (!(evt->flags & DWC3_EVENT_PENDING))
2684 return IRQ_NONE;
b15a762f 2685
f42f2447
FB		 2686 while (left > 0) {
2687 union dwc3_event event;
b15a762f 2688
f42f2447 2689 event.raw = *(u32 *) (evt->buf + evt->lpos);
b15a762f 2690
f42f2447 2691 dwc3_process_event_entry(dwc, &event);
b15a762f 2692
f42f2447
FB		 2693 /*
2694 * FIXME we wrap around correctly to the next entry as
2695 * almost all entries are 4 bytes in size. There is one
2696 * entry which has 12 bytes which is a regular entry
2697 * followed by 8 bytes data. ATM I don't know how
2698 * things are organized if we get next to the a
2699 * boundary so I worry about that once we try to handle
2700 * that.
2701 */
2702 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2703 left -= 4;
b15a762f 2704
f42f2447
FB		 2705 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2706 }
b15a762f 2707
f42f2447
FB		 2708 evt->count = 0;
2709 evt->flags &= ~DWC3_EVENT_PENDING;
2710 ret = IRQ_HANDLED;
b15a762f 2711
f42f2447
FB		 2712 /* Unmask interrupt */
2713 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2714 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2715 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
b15a762f 2716
f42f2447
FB		 2717 return ret;
2718}
e8adfc30 2719
f42f2447
FB		 2720static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2721{
2722 struct dwc3 *dwc = _dwc;
e5f68b4a 2723 unsigned long flags;
f42f2447
FB		 2724 irqreturn_t ret = IRQ_NONE;
2725 int i;
2726
e5f68b4a 2727 spin_lock_irqsave(&dwc->lock, flags);
f42f2447
FB		 2728
2729 for (i = 0; i < dwc->num_event_buffers; i++)
2730 ret |= dwc3_process_event_buf(dwc, i);
b15a762f 2731
e5f68b4a 2732 spin_unlock_irqrestore(&dwc->lock, flags);
b15a762f
FB		 2733
2734 return ret;
2735}
2736
7f97aa98 2737static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
72246da4
FB		 2738{
2739 struct dwc3_event_buffer *evt;
72246da4 2740 u32 count;
e8adfc30 2741 u32 reg;
72246da4 2742
b15a762f
FB		 2743 evt = dwc->ev_buffs[buf];
2744
72246da4
FB		 2745 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2746 count &= DWC3_GEVNTCOUNT_MASK;
2747 if (!count)
2748 return IRQ_NONE;
2749
b15a762f
FB		 2750 evt->count = count;
2751 evt->flags |= DWC3_EVENT_PENDING;
72246da4 2752
e8adfc30
FB		 2753 /* Mask interrupt */
2754 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2755 reg |= DWC3_GEVNTSIZ_INTMASK;
2756 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2757
b15a762f 2758 return IRQ_WAKE_THREAD;
72246da4
FB		 2759}
2760
2761static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2762{
2763 struct dwc3 *dwc = _dwc;
2764 int i;
2765 irqreturn_t ret = IRQ_NONE;
2766
9f622b2a 2767 for (i = 0; i < dwc->num_event_buffers; i++) {
72246da4
FB		 2768 irqreturn_t status;
2769
7f97aa98 2770 status = dwc3_check_event_buf(dwc, i);
b15a762f 2771 if (status == IRQ_WAKE_THREAD)
72246da4
FB		 2772 ret = status;
2773 }
2774
72246da4
FB		 2775 return ret;
2776}
2777
2778/**
2779 * dwc3_gadget_init - Initializes gadget related registers
1d046793 2780 * @dwc: pointer to our controller context structure
72246da4
FB		 2781 *
2782 * Returns 0 on success otherwise negative errno.
2783 */
41ac7b3a 2784int dwc3_gadget_init(struct dwc3 *dwc)
72246da4 2785{
72246da4 2786 int ret;
72246da4
FB		 2787
2788 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2789 &dwc->ctrl_req_addr, GFP_KERNEL);
2790 if (!dwc->ctrl_req) {
2791 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2792 ret = -ENOMEM;
2793 goto err0;
2794 }
2795
2abd9d5f 2796 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 2797 &dwc->ep0_trb_addr, GFP_KERNEL);
2798 if (!dwc->ep0_trb) {
2799 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2800 ret = -ENOMEM;
2801 goto err1;
2802 }
2803
3ef35faf 2804 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
72246da4 2805 if (!dwc->setup_buf) {
72246da4
FB		 2806 ret = -ENOMEM;
2807 goto err2;
2808 }
2809
5812b1c2 2810 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
3ef35faf
FB		 2811 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2812 GFP_KERNEL);
5812b1c2
FB		 2813 if (!dwc->ep0_bounce) {
2814 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2815 ret = -ENOMEM;
2816 goto err3;
2817 }
2818
04c03d10
FB		 2819 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2820 if (!dwc->zlp_buf) {
2821 ret = -ENOMEM;
2822 goto err4;
2823 }
2824
72246da4 2825 dwc->gadget.ops = &dwc3_gadget_ops;
72246da4 2826 dwc->gadget.speed = USB_SPEED_UNKNOWN;
eeb720fb 2827 dwc->gadget.sg_supported = true;
72246da4 2828 dwc->gadget.name = "dwc3-gadget";
6a4290cc 2829 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
72246da4 2830
b9e51b2b
BM		 2831 /*
2832 * FIXME We might be setting max_speed to <SUPER, however versions
2833 * <2.20a of dwc3 have an issue with metastability (documented
2834 * elsewhere in this driver) which tells us we can't set max speed to
2835 * anything lower than SUPER.
2836 *
2837 * Because gadget.max_speed is only used by composite.c and function
2838 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2839 * to happen so we avoid sending SuperSpeed Capability descriptor
2840 * together with our BOS descriptor as that could confuse host into
2841 * thinking we can handle super speed.
2842 *
2843 * Note that, in fact, we won't even support GetBOS requests when speed
2844 * is less than super speed because we don't have means, yet, to tell
2845 * composite.c that we are USB 2.0 + LPM ECN.
2846 */
2847 if (dwc->revision < DWC3_REVISION_220A)
2848 dwc3_trace(trace_dwc3_gadget,
2849 "Changing max_speed on rev %08x\n",
2850 dwc->revision);
2851
2852 dwc->gadget.max_speed = dwc->maximum_speed;
2853
a4b9d94b
DC		 2854 /*
2855 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2856 * on ep out.
2857 */
2858 dwc->gadget.quirk_ep_out_aligned_size = true;
2859
72246da4
FB		 2860 /*
2861 * REVISIT: Here we should clear all pending IRQs to be
2862 * sure we're starting from a well known location.
2863 */
2864
2865 ret = dwc3_gadget_init_endpoints(dwc);
2866 if (ret)
04c03d10 2867 goto err5;
72246da4 2868
72246da4
FB		 2869 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2870 if (ret) {
2871 dev_err(dwc->dev, "failed to register udc\n");
04c03d10 2872 goto err5;
72246da4
FB		 2873 }
2874
2875 return 0;
2876
04c03d10
FB		 2877err5:
2878 kfree(dwc->zlp_buf);
2879
5812b1c2 2880err4:
e1f80467 2881 dwc3_gadget_free_endpoints(dwc);
3ef35faf
FB		 2882 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2883 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 2884
72246da4 2885err3:
0fc9a1be 2886 kfree(dwc->setup_buf);
72246da4
FB		 2887
2888err2:
2889 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2890 dwc->ep0_trb, dwc->ep0_trb_addr);
2891
2892err1:
2893 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2894 dwc->ctrl_req, dwc->ctrl_req_addr);
2895
2896err0:
2897 return ret;
2898}
2899
7415f17c
FB		 2900/* -------------------------------------------------------------------------- */
2901
72246da4
FB		 2902void dwc3_gadget_exit(struct dwc3 *dwc)
2903{
72246da4 2904 usb_del_gadget_udc(&dwc->gadget);
72246da4 2905
72246da4
FB		 2906 dwc3_gadget_free_endpoints(dwc);
2907
3ef35faf
FB		 2908 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2909 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 2910
0fc9a1be 2911 kfree(dwc->setup_buf);
04c03d10 2912 kfree(dwc->zlp_buf);
72246da4
FB		 2913
2914 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2915 dwc->ep0_trb, dwc->ep0_trb_addr);
2916
2917 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2918 dwc->ctrl_req, dwc->ctrl_req_addr);
72246da4 2919}
7415f17c 2920
0b0231aa 2921int dwc3_gadget_suspend(struct dwc3 *dwc)
7415f17c 2922{
7b2a0368 2923 if (dwc->pullups_connected) {
7415f17c 2924 dwc3_gadget_disable_irq(dwc);
7b2a0368
FB		 2925 dwc3_gadget_run_stop(dwc, true, true);
2926 }
7415f17c 2927
7415f17c
FB		 2928 __dwc3_gadget_ep_disable(dwc->eps[0]);
2929 __dwc3_gadget_ep_disable(dwc->eps[1]);
2930
2931 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2932
2933 return 0;
2934}
2935
2936int dwc3_gadget_resume(struct dwc3 *dwc)
2937{
2938 struct dwc3_ep *dep;
2939 int ret;
2940
2941 /* Start with SuperSpeed Default */
2942 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2943
2944 dep = dwc->eps[0];
265b70a7
PZ		 2945 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2946 false);
7415f17c
FB		 2947 if (ret)
2948 goto err0;
2949
2950 dep = dwc->eps[1];
265b70a7
PZ		 2951 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2952 false);
7415f17c
FB		 2953 if (ret)
2954 goto err1;
2955
2956 /* begin to receive SETUP packets */
2957 dwc->ep0state = EP0_SETUP_PHASE;
2958 dwc3_ep0_out_start(dwc);
2959
2960 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2961
0b0231aa
FB		 2962 if (dwc->pullups_connected) {
2963 dwc3_gadget_enable_irq(dwc);
2964 dwc3_gadget_run_stop(dwc, true, false);
2965 }
2966
7415f17c
FB		 2967 return 0;
2968
2969err1:
2970 __dwc3_gadget_ep_disable(dwc->eps[0]);
2971
2972err0:
2973 return ret;
2974}
Linux 6.x block layer and io_uring tree(s)