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usb: dwc3: ep0: giveback requests on stall_and_restart
[linux-2.6-block.git] / drivers / usb / dwc3 / ep0.c
CommitLineData
72246da4
FB		 1/**
2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 * All rights reserved.
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The names of the above-listed copyright holders may not be used
20 * to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * ALTERNATIVELY, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2, as published by the Free
25 * Software Foundation.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 */
39
40#include <linux/kernel.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/io.h>
47#include <linux/list.h>
48#include <linux/dma-mapping.h>
49
50#include <linux/usb/ch9.h>
51#include <linux/usb/gadget.h>
52
53#include "core.h"
54#include "gadget.h"
55#include "io.h"
56
57static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
58 const struct dwc3_event_depevt *event);
59
60static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
61{
62 switch (state) {
63 case EP0_UNCONNECTED:
64 return "Unconnected";
c7fcdeb2
FB		 65 case EP0_SETUP_PHASE:
66 return "Setup Phase";
67 case EP0_DATA_PHASE:
68 return "Data Phase";
69 case EP0_STATUS_PHASE:
70 return "Status Phase";
72246da4
FB		 71 default:
72 return "UNKNOWN";
73 }
74}
75
76static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
c7fcdeb2 77 u32 len, u32 type)
72246da4
FB		 78{
79 struct dwc3_gadget_ep_cmd_params params;
80 struct dwc3_trb_hw *trb_hw;
81 struct dwc3_trb trb;
82 struct dwc3_ep *dep;
83
84 int ret;
85
86 dep = dwc->eps[epnum];
c7fcdeb2
FB		 87 if (dep->flags & DWC3_EP_BUSY) {
88 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
89 return 0;
90 }
72246da4
FB		 91
92 trb_hw = dwc->ep0_trb;
93 memset(&trb, 0, sizeof(trb));
94
c7fcdeb2 95 trb.trbctl = type;
72246da4
FB		 96 trb.bplh = buf_dma;
97 trb.length = len;
98
99 trb.hwo = 1;
100 trb.lst = 1;
101 trb.ioc = 1;
102 trb.isp_imi = 1;
103
104 dwc3_trb_to_hw(&trb, trb_hw);
105
106 memset(&params, 0, sizeof(params));
107 params.param0.depstrtxfer.transfer_desc_addr_high =
108 upper_32_bits(dwc->ep0_trb_addr);
109 params.param1.depstrtxfer.transfer_desc_addr_low =
110 lower_32_bits(dwc->ep0_trb_addr);
111
112 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
113 DWC3_DEPCMD_STARTTRANSFER, &params);
114 if (ret < 0) {
115 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
116 return ret;
117 }
118
c7fcdeb2 119 dep->flags |= DWC3_EP_BUSY;
72246da4
FB		 120 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
121 dep->number);
122
1ddcb218
FB		 123 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
124
72246da4
FB		 125 return 0;
126}
127
128static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
129 struct dwc3_request *req)
130{
c7fcdeb2 131 int ret = 0;
72246da4
FB		 132
133 req->request.actual = 0;
134 req->request.status = -EINPROGRESS;
72246da4
FB		 135 req->epnum = dep->number;
136
137 list_add_tail(&req->list, &dep->request_list);
a6829706 138
c7fcdeb2
FB		 139 /*
140 * Gadget driver might not be quick enough to queue a request
141 * before we get a Transfer Not Ready event on this endpoint.
142 *
143 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
144 * flag is set, it's telling us that as soon as Gadget queues the
145 * required request, we should kick the transfer here because the
146 * IRQ we were waiting for is long gone.
147 */
148 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
149 struct dwc3 *dwc = dep->dwc;
150 unsigned direction;
151 u32 type;
152
153 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
154
155 if (dwc->ep0state == EP0_STATUS_PHASE) {
156 type = dwc->three_stage_setup
157 ? DWC3_TRBCTL_CONTROL_STATUS3
158 : DWC3_TRBCTL_CONTROL_STATUS2;
159 } else if (dwc->ep0state == EP0_DATA_PHASE) {
160 type = DWC3_TRBCTL_CONTROL_DATA;
161 } else {
162 /* should never happen */
163 WARN_ON(1);
164 return 0;
165 }
72246da4 166
c7fcdeb2
FB		 167 ret = dwc3_ep0_start_trans(dwc, direction,
168 req->request.dma, req->request.length, type);
169 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
170 DWC3_EP0_DIR_IN);
72246da4
FB		 171 }
172
173 return ret;
174}
175
176int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
177 gfp_t gfp_flags)
178{
179 struct dwc3_request *req = to_dwc3_request(request);
180 struct dwc3_ep *dep = to_dwc3_ep(ep);
181 struct dwc3 *dwc = dep->dwc;
182
183 unsigned long flags;
184
185 int ret;
186
72246da4
FB		 187 spin_lock_irqsave(&dwc->lock, flags);
188 if (!dep->desc) {
189 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
190 request, dep->name);
191 ret = -ESHUTDOWN;
192 goto out;
193 }
194
195 /* we share one TRB for ep0/1 */
196 if (!list_empty(&dwc->eps[0]->request_list) ||
197 !list_empty(&dwc->eps[1]->request_list) ||
198 dwc->ep0_status_pending) {
199 ret = -EBUSY;
200 goto out;
201 }
202
203 dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
204 request, dep->name, request->length,
205 dwc3_ep0_state_string(dwc->ep0state));
206
207 ret = __dwc3_gadget_ep0_queue(dep, req);
208
209out:
210 spin_unlock_irqrestore(&dwc->lock, flags);
211
212 return ret;
213}
214
215static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
216{
d742220b
FB		 217 struct dwc3_ep *dep = dwc->eps[0];
218
72246da4
FB		 219 /* stall is always issued on EP0 */
220 __dwc3_gadget_ep_set_halt(dwc->eps[0], 1);
76cb323f 221 dwc->eps[0]->flags = DWC3_EP_ENABLED;
d742220b
FB		 222
223 if (!list_empty(&dep->request_list)) {
224 struct dwc3_request *req;
225
226 req = next_request(&dep->request_list);
227 dwc3_gadget_giveback(dep, req, -ECONNRESET);
228 }
229
c7fcdeb2 230 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 231 dwc3_ep0_out_start(dwc);
232}
233
234void dwc3_ep0_out_start(struct dwc3 *dwc)
235{
72246da4
FB		 236 int ret;
237
c7fcdeb2
FB		 238 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
239 DWC3_TRBCTL_CONTROL_SETUP);
72246da4
FB		 240 WARN_ON(ret < 0);
241}
242
72246da4
FB		 243static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
244{
245 struct dwc3_ep *dep;
246 u32 windex = le16_to_cpu(wIndex_le);
247 u32 epnum;
248
249 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
250 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
251 epnum |= 1;
252
253 dep = dwc->eps[epnum];
254 if (dep->flags & DWC3_EP_ENABLED)
255 return dep;
256
257 return NULL;
258}
259
260static void dwc3_ep0_send_status_response(struct dwc3 *dwc)
261{
b673cf30 262 dwc3_ep0_start_trans(dwc, 1, dwc->setup_buf_addr,
c7fcdeb2
FB		 263 dwc->ep0_usb_req.length,
264 DWC3_TRBCTL_CONTROL_DATA);
72246da4
FB		 265}
266
267/*
268 * ch 9.4.5
269 */
270static int dwc3_ep0_handle_status(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
271{
272 struct dwc3_ep *dep;
273 u32 recip;
274 u16 usb_status = 0;
275 __le16 *response_pkt;
276
277 recip = ctrl->bRequestType & USB_RECIP_MASK;
278 switch (recip) {
279 case USB_RECIP_DEVICE:
280 /*
281 * We are self-powered. U1/U2/LTM will be set later
282 * once we handle this states. RemoteWakeup is 0 on SS
283 */
284 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
285 break;
286
287 case USB_RECIP_INTERFACE:
288 /*
289 * Function Remote Wake Capable D0
290 * Function Remote Wakeup D1
291 */
292 break;
293
294 case USB_RECIP_ENDPOINT:
295 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
296 if (!dep)
297 return -EINVAL;
298
299 if (dep->flags & DWC3_EP_STALL)
300 usb_status = 1 << USB_ENDPOINT_HALT;
301 break;
302 default:
303 return -EINVAL;
304 };
305
306 response_pkt = (__le16 *) dwc->setup_buf;
307 *response_pkt = cpu_to_le16(usb_status);
308 dwc->ep0_usb_req.length = sizeof(*response_pkt);
1ddcb218 309 dwc->ep0_status_pending = 1;
72246da4
FB		 310
311 return 0;
312}
313
314static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
315 struct usb_ctrlrequest *ctrl, int set)
316{
317 struct dwc3_ep *dep;
318 u32 recip;
319 u32 wValue;
320 u32 wIndex;
321 u32 reg;
322 int ret;
323 u32 mode;
324
325 wValue = le16_to_cpu(ctrl->wValue);
326 wIndex = le16_to_cpu(ctrl->wIndex);
327 recip = ctrl->bRequestType & USB_RECIP_MASK;
328 switch (recip) {
329 case USB_RECIP_DEVICE:
330
331 /*
332 * 9.4.1 says only only for SS, in AddressState only for
333 * default control pipe
334 */
335 switch (wValue) {
336 case USB_DEVICE_U1_ENABLE:
337 case USB_DEVICE_U2_ENABLE:
338 case USB_DEVICE_LTM_ENABLE:
339 if (dwc->dev_state != DWC3_CONFIGURED_STATE)
340 return -EINVAL;
341 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
342 return -EINVAL;
343 }
344
345 /* XXX add U[12] & LTM */
346 switch (wValue) {
347 case USB_DEVICE_REMOTE_WAKEUP:
348 break;
349 case USB_DEVICE_U1_ENABLE:
350 break;
351 case USB_DEVICE_U2_ENABLE:
352 break;
353 case USB_DEVICE_LTM_ENABLE:
354 break;
355
356 case USB_DEVICE_TEST_MODE:
357 if ((wIndex & 0xff) != 0)
358 return -EINVAL;
359 if (!set)
360 return -EINVAL;
361
362 mode = wIndex >> 8;
363 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
364 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
365
366 switch (mode) {
367 case TEST_J:
368 case TEST_K:
369 case TEST_SE0_NAK:
370 case TEST_PACKET:
371 case TEST_FORCE_EN:
372 reg |= mode << 1;
373 break;
374 default:
375 return -EINVAL;
376 }
377 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
378 break;
379 default:
380 return -EINVAL;
381 }
382 break;
383
384 case USB_RECIP_INTERFACE:
385 switch (wValue) {
386 case USB_INTRF_FUNC_SUSPEND:
387 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
388 /* XXX enable Low power suspend */
389 ;
390 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
391 /* XXX enable remote wakeup */
392 ;
393 break;
394 default:
395 return -EINVAL;
396 }
397 break;
398
399 case USB_RECIP_ENDPOINT:
400 switch (wValue) {
401 case USB_ENDPOINT_HALT:
402
403 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
404 if (!dep)
405 return -EINVAL;
406 ret = __dwc3_gadget_ep_set_halt(dep, set);
407 if (ret)
408 return -EINVAL;
409 break;
410 default:
411 return -EINVAL;
412 }
413 break;
414
415 default:
416 return -EINVAL;
417 };
418
72246da4
FB		 419 return 0;
420}
421
422static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
423{
424 int ret = 0;
425 u32 addr;
426 u32 reg;
427
428 addr = le16_to_cpu(ctrl->wValue);
429 if (addr > 127)
430 return -EINVAL;
431
432 switch (dwc->dev_state) {
433 case DWC3_DEFAULT_STATE:
434 case DWC3_ADDRESS_STATE:
435 /*
436 * Not sure if we should program DevAddr now or later
437 */
438 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
439 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
440 reg |= DWC3_DCFG_DEVADDR(addr);
441 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
442
443 if (addr)
444 dwc->dev_state = DWC3_ADDRESS_STATE;
445 else
446 dwc->dev_state = DWC3_DEFAULT_STATE;
447 break;
448
449 case DWC3_CONFIGURED_STATE:
450 ret = -EINVAL;
451 break;
452 }
c7fcdeb2 453
72246da4
FB		 454 return ret;
455}
456
457static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
458{
459 int ret;
460
461 spin_unlock(&dwc->lock);
462 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
463 spin_lock(&dwc->lock);
464 return ret;
465}
466
467static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
468{
469 u32 cfg;
470 int ret;
471
472 cfg = le16_to_cpu(ctrl->wValue);
473
474 switch (dwc->dev_state) {
475 case DWC3_DEFAULT_STATE:
476 return -EINVAL;
477 break;
478
479 case DWC3_ADDRESS_STATE:
480 ret = dwc3_ep0_delegate_req(dwc, ctrl);
481 /* if the cfg matches and the cfg is non zero */
482 if (!ret && cfg)
483 dwc->dev_state = DWC3_CONFIGURED_STATE;
484 break;
485
486 case DWC3_CONFIGURED_STATE:
487 ret = dwc3_ep0_delegate_req(dwc, ctrl);
488 if (!cfg)
489 dwc->dev_state = DWC3_ADDRESS_STATE;
490 break;
491 }
492 return 0;
493}
494
495static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
496{
497 int ret;
498
499 switch (ctrl->bRequest) {
500 case USB_REQ_GET_STATUS:
501 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
502 ret = dwc3_ep0_handle_status(dwc, ctrl);
503 break;
504 case USB_REQ_CLEAR_FEATURE:
505 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
506 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
507 break;
508 case USB_REQ_SET_FEATURE:
509 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
510 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
511 break;
512 case USB_REQ_SET_ADDRESS:
513 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
514 ret = dwc3_ep0_set_address(dwc, ctrl);
515 break;
516 case USB_REQ_SET_CONFIGURATION:
517 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
518 ret = dwc3_ep0_set_config(dwc, ctrl);
519 break;
520 default:
521 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
522 ret = dwc3_ep0_delegate_req(dwc, ctrl);
523 break;
524 };
525
526 return ret;
527}
528
529static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
530 const struct dwc3_event_depevt *event)
531{
532 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
533 int ret;
534 u32 len;
535
536 if (!dwc->gadget_driver)
537 goto err;
538
539 len = le16_to_cpu(ctrl->wLength);
1ddcb218 540 if (!len) {
72246da4 541 dwc->three_stage_setup = 0;
1ddcb218
FB		 542 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
543 } else {
72246da4 544 dwc->three_stage_setup = 1;
1ddcb218
FB		 545 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
546 }
72246da4
FB		 547
548 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
549 ret = dwc3_ep0_std_request(dwc, ctrl);
550 else
551 ret = dwc3_ep0_delegate_req(dwc, ctrl);
552
553 if (ret >= 0)
554 return;
555
556err:
557 dwc3_ep0_stall_and_restart(dwc);
558}
559
560static void dwc3_ep0_complete_data(struct dwc3 *dwc,
561 const struct dwc3_event_depevt *event)
562{
563 struct dwc3_request *r = NULL;
564 struct usb_request *ur;
565 struct dwc3_trb trb;
566 struct dwc3_ep *dep;
c611ccb4 567 u32 transferred;
72246da4
FB		 568 u8 epnum;
569
570 epnum = event->endpoint_number;
571 dep = dwc->eps[epnum];
572
1ddcb218
FB		 573 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
574
72246da4 575 if (!dwc->ep0_status_pending) {
c7fcdeb2 576 r = next_request(&dwc->eps[0]->request_list);
72246da4
FB		 577 ur = &r->request;
578 } else {
579 ur = &dwc->ep0_usb_req;
580 dwc->ep0_status_pending = 0;
581 }
582
583 dwc3_trb_to_nat(dwc->ep0_trb, &trb);
584
a6829706
FB		 585 if (dwc->ep0_bounced) {
586 struct dwc3_ep *ep0 = dwc->eps[0];
587
c7fcdeb2
FB		 588 transferred = min_t(u32, ur->length,
589 ep0->endpoint.maxpacket - trb.length);
a6829706
FB		 590 memcpy(ur->buf, dwc->ep0_bounce, transferred);
591 dwc->ep0_bounced = false;
592 } else {
593 transferred = ur->length - trb.length;
594 ur->actual += transferred;
595 }
72246da4
FB		 596
597 if ((epnum & 1) && ur->actual < ur->length) {
598 /* for some reason we did not get everything out */
599
600 dwc3_ep0_stall_and_restart(dwc);
601 dwc3_gadget_giveback(dep, r, -ECONNRESET);
602 } else {
603 /*
604 * handle the case where we have to send a zero packet. This
605 * seems to be case when req.length > maxpacket. Could it be?
606 */
72246da4
FB		 607 if (r)
608 dwc3_gadget_giveback(dep, r, 0);
609 }
610}
611
612static void dwc3_ep0_complete_req(struct dwc3 *dwc,
613 const struct dwc3_event_depevt *event)
614{
615 struct dwc3_request *r;
616 struct dwc3_ep *dep;
72246da4 617
c7fcdeb2 618 dep = dwc->eps[0];
72246da4
FB		 619
620 if (!list_empty(&dep->request_list)) {
621 r = next_request(&dep->request_list);
622
623 dwc3_gadget_giveback(dep, r, 0);
624 }
625
c7fcdeb2 626 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 627 dwc3_ep0_out_start(dwc);
628}
629
630static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
631 const struct dwc3_event_depevt *event)
632{
c7fcdeb2
FB		 633 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
634
635 dep->flags &= ~DWC3_EP_BUSY;
636
72246da4 637 switch (dwc->ep0state) {
c7fcdeb2
FB		 638 case EP0_SETUP_PHASE:
639 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
72246da4
FB		 640 dwc3_ep0_inspect_setup(dwc, event);
641 break;
642
c7fcdeb2
FB		 643 case EP0_DATA_PHASE:
644 dev_vdbg(dwc->dev, "Data Phase\n");
72246da4
FB		 645 dwc3_ep0_complete_data(dwc, event);
646 break;
647
c7fcdeb2
FB		 648 case EP0_STATUS_PHASE:
649 dev_vdbg(dwc->dev, "Status Phase\n");
72246da4
FB		 650 dwc3_ep0_complete_req(dwc, event);
651 break;
c7fcdeb2
FB		 652 default:
653 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
654 }
655}
72246da4 656
c7fcdeb2
FB		 657static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
658 const struct dwc3_event_depevt *event)
659{
660 dwc->ep0state = EP0_SETUP_PHASE;
661 dwc3_ep0_out_start(dwc);
662}
663
664static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
665 const struct dwc3_event_depevt *event)
666{
667 struct dwc3_ep *dep;
668 struct dwc3_request *req;
669 int ret;
670
671 dep = dwc->eps[0];
672 dwc->ep0state = EP0_DATA_PHASE;
673
1ddcb218
FB		 674 if (dwc->ep0_status_pending) {
675 dwc3_ep0_send_status_response(dwc);
676 return;
677 }
678
c7fcdeb2
FB		 679 if (list_empty(&dep->request_list)) {
680 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
681 dep->flags |= DWC3_EP_PENDING_REQUEST;
682
683 if (event->endpoint_number)
684 dep->flags |= DWC3_EP0_DIR_IN;
685 return;
72246da4 686 }
c7fcdeb2
FB		 687
688 req = next_request(&dep->request_list);
689 req->direction = !!event->endpoint_number;
690
691 dwc->ep0state = EP0_DATA_PHASE;
692 if (req->request.length == 0) {
693 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
694 dwc->ctrl_req_addr, 0,
695 DWC3_TRBCTL_CONTROL_DATA);
696 } else if ((req->request.length % dep->endpoint.maxpacket)
697 && (event->endpoint_number == 0)) {
698 dwc3_map_buffer_to_dma(req);
699
700 WARN_ON(req->request.length > dep->endpoint.maxpacket);
701
702 dwc->ep0_bounced = true;
703
704 /*
705 * REVISIT in case request length is bigger than EP0
706 * wMaxPacketSize, we will need two chained TRBs to handle
707 * the transfer.
708 */
709 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
710 dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
711 DWC3_TRBCTL_CONTROL_DATA);
712 } else {
713 dwc3_map_buffer_to_dma(req);
714
715 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
716 req->request.dma, req->request.length,
717 DWC3_TRBCTL_CONTROL_DATA);
718 }
719
720 WARN_ON(ret < 0);
72246da4
FB		 721}
722
c7fcdeb2 723static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
72246da4
FB		 724 const struct dwc3_event_depevt *event)
725{
c7fcdeb2
FB		 726 u32 type;
727 int ret;
72246da4 728
c7fcdeb2 729 dwc->ep0state = EP0_STATUS_PHASE;
72246da4 730
c7fcdeb2
FB		 731 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
732 : DWC3_TRBCTL_CONTROL_STATUS2;
733
734 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
735 dwc->ctrl_req_addr, 0, type);
736
737 WARN_ON(ret < 0);
738}
739
740static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
741 const struct dwc3_event_depevt *event)
742{
743 switch (event->status) {
744 case DEPEVT_STATUS_CONTROL_SETUP:
745 dev_vdbg(dwc->dev, "Control Setup\n");
746 dwc3_ep0_do_control_setup(dwc, event);
747 break;
1ddcb218 748
c7fcdeb2
FB		 749 case DEPEVT_STATUS_CONTROL_DATA:
750 dev_vdbg(dwc->dev, "Control Data\n");
1ddcb218
FB		 751
752 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
753 dev_vdbg(dwc->dev, "Expected %d got %d\n",
754 DEPEVT_STATUS_CONTROL_DATA,
755 event->status);
756
757 dwc3_ep0_stall_and_restart(dwc);
758 return;
759 }
760
c7fcdeb2
FB		 761 dwc3_ep0_do_control_data(dwc, event);
762 break;
1ddcb218 763
c7fcdeb2
FB		 764 case DEPEVT_STATUS_CONTROL_STATUS:
765 dev_vdbg(dwc->dev, "Control Status\n");
1ddcb218
FB		 766
767 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
768 dev_vdbg(dwc->dev, "Expected %d got %d\n",
769 DEPEVT_STATUS_CONTROL_STATUS,
770 event->status);
771
772 dwc3_ep0_stall_and_restart(dwc);
773 return;
774 }
c7fcdeb2 775 dwc3_ep0_do_control_status(dwc, event);
72246da4
FB		 776 }
777}
778
779void dwc3_ep0_interrupt(struct dwc3 *dwc,
780 const const struct dwc3_event_depevt *event)
781{
782 u8 epnum = event->endpoint_number;
783
784 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
785 dwc3_ep_event_string(event->endpoint_event),
786 epnum, (epnum & 1) ? "in" : "out",
787 dwc3_ep0_state_string(dwc->ep0state));
788
789 switch (event->endpoint_event) {
790 case DWC3_DEPEVT_XFERCOMPLETE:
791 dwc3_ep0_xfer_complete(dwc, event);
792 break;
793
794 case DWC3_DEPEVT_XFERNOTREADY:
795 dwc3_ep0_xfernotready(dwc, event);
796 break;
797
798 case DWC3_DEPEVT_XFERINPROGRESS:
799 case DWC3_DEPEVT_RXTXFIFOEVT:
800 case DWC3_DEPEVT_STREAMEVT:
801 case DWC3_DEPEVT_EPCMDCMPLT:
802 break;
803 }
804}
Linux 6.x block layer and io_uring tree(s)