[linux-2.6-block.git] / drivers / usb / dwc3 / ep0.c

/**
 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 * All rights reserved.
 *
 * Authors: Felipe Balbi <balbi@ti.com>,
 *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The names of the above-listed copyright holders may not be used
 *    to endorse or promote products derived from this software without
 *    specific prior written permission.
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2, as published by the Free
 * Software Foundation.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/list.h>
#include <linux/dma-mapping.h>

#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>

#include "core.h"
#include "gadget.h"
#include "io.h"

static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
		const struct dwc3_event_depevt *event);

static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
{
	switch (state) {
	case EP0_UNCONNECTED:
		return "Unconnected";
	case EP0_SETUP_PHASE:
		return "Setup Phase";
	case EP0_DATA_PHASE:
		return "Data Phase";
	case EP0_STATUS_PHASE:
		return "Status Phase";
	case EP0_STALL:
		return "Stall";
	default:
		return "UNKNOWN";
	}
}

static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
		u32 len, u32 type)
{
	struct dwc3_gadget_ep_cmd_params params;
	struct dwc3_trb_hw		*trb_hw;
	struct dwc3_trb			trb;
	struct dwc3_ep			*dep;

	int				ret;

	dep = dwc->eps[epnum];
	if (dep->flags & DWC3_EP_BUSY) {
		dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
		return 0;
	}

	trb_hw = dwc->ep0_trb;
	memset(&trb, 0, sizeof(trb));

	trb.trbctl = type;
	trb.bplh = buf_dma;
	trb.length = len;

	trb.hwo	= 1;
	trb.lst	= 1;
	trb.ioc	= 1;
	trb.isp_imi = 1;

	dwc3_trb_to_hw(&trb, trb_hw);

	memset(&params, 0, sizeof(params));
	params.param0.depstrtxfer.transfer_desc_addr_high =
		upper_32_bits(dwc->ep0_trb_addr);
	params.param1.depstrtxfer.transfer_desc_addr_low =
		lower_32_bits(dwc->ep0_trb_addr);

	ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
			DWC3_DEPCMD_STARTTRANSFER, &params);
	if (ret < 0) {
		dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
		return ret;
	}

	dep->flags |= DWC3_EP_BUSY;
	dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
			dep->number);

	return 0;
}

static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
		struct dwc3_request *req)
{
	int			ret = 0;

	req->request.actual	= 0;
	req->request.status	= -EINPROGRESS;
	req->epnum		= dep->number;

	list_add_tail(&req->list, &dep->request_list);

	/*
	 * Gadget driver might not be quick enough to queue a request
	 * before we get a Transfer Not Ready event on this endpoint.
	 *
	 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
	 * flag is set, it's telling us that as soon as Gadget queues the
	 * required request, we should kick the transfer here because the
	 * IRQ we were waiting for is long gone.
	 */
	if (dep->flags & DWC3_EP_PENDING_REQUEST) {
		struct dwc3	*dwc = dep->dwc;
		unsigned	direction;
		u32		type;

		direction = !!(dep->flags & DWC3_EP0_DIR_IN);

		if (dwc->ep0state == EP0_STATUS_PHASE) {
			type = dwc->three_stage_setup
				? DWC3_TRBCTL_CONTROL_STATUS3
				: DWC3_TRBCTL_CONTROL_STATUS2;
		} else if (dwc->ep0state == EP0_DATA_PHASE) {
			type = DWC3_TRBCTL_CONTROL_DATA;
		} else {
			/* should never happen */
			WARN_ON(1);
			return 0;
		}

		ret = dwc3_ep0_start_trans(dwc, direction,
				req->request.dma, req->request.length, type);
		dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
				DWC3_EP0_DIR_IN);
	}

	return ret;
}

int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
		gfp_t gfp_flags)
{
	struct dwc3_request		*req = to_dwc3_request(request);
	struct dwc3_ep			*dep = to_dwc3_ep(ep);
	struct dwc3			*dwc = dep->dwc;

	unsigned long			flags;

	int				ret;

	spin_lock_irqsave(&dwc->lock, flags);
	if (!dep->desc) {
		dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
				request, dep->name);
		ret = -ESHUTDOWN;
		goto out;
	}

	/* we share one TRB for ep0/1 */
	if (!list_empty(&dwc->eps[0]->request_list) ||
			!list_empty(&dwc->eps[1]->request_list) ||
			dwc->ep0_status_pending) {
		ret = -EBUSY;
		goto out;
	}

	dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
			request, dep->name, request->length,
			dwc3_ep0_state_string(dwc->ep0state));

	ret = __dwc3_gadget_ep0_queue(dep, req);

out:
	spin_unlock_irqrestore(&dwc->lock, flags);

	return ret;
}

static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
{
	/* stall is always issued on EP0 */
	__dwc3_gadget_ep_set_halt(dwc->eps[0], 1);
	dwc->eps[0]->flags &= ~DWC3_EP_STALL;
	dwc->ep0state = EP0_SETUP_PHASE;
	dwc3_ep0_out_start(dwc);
}

void dwc3_ep0_out_start(struct dwc3 *dwc)
{
	int				ret;

	ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
			DWC3_TRBCTL_CONTROL_SETUP);
	WARN_ON(ret < 0);
}

static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
{
	struct dwc3_ep		*dep;
	u32			windex = le16_to_cpu(wIndex_le);
	u32			epnum;

	epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
	if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
		epnum |= 1;

	dep = dwc->eps[epnum];
	if (dep->flags & DWC3_EP_ENABLED)
		return dep;

	return NULL;
}

static void dwc3_ep0_send_status_response(struct dwc3 *dwc)
{
	dwc3_ep0_start_trans(dwc, 1, dwc->setup_buf_addr,
			dwc->ep0_usb_req.length,
			DWC3_TRBCTL_CONTROL_DATA);
	dwc->ep0_status_pending = 1;
}

/*
 * ch 9.4.5
 */
static int dwc3_ep0_handle_status(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
{
	struct dwc3_ep		*dep;
	u32			recip;
	u16			usb_status = 0;
	__le16			*response_pkt;

	recip = ctrl->bRequestType & USB_RECIP_MASK;
	switch (recip) {
	case USB_RECIP_DEVICE:
		/*
		 * We are self-powered. U1/U2/LTM will be set later
		 * once we handle this states. RemoteWakeup is 0 on SS
		 */
		usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
		break;

	case USB_RECIP_INTERFACE:
		/*
		 * Function Remote Wake Capable	D0
		 * Function Remote Wakeup	D1
		 */
		break;

	case USB_RECIP_ENDPOINT:
		dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
		if (!dep)
		       return -EINVAL;

		if (dep->flags & DWC3_EP_STALL)
			usb_status = 1 << USB_ENDPOINT_HALT;
		break;
	default:
		return -EINVAL;
	};

	response_pkt = (__le16 *) dwc->setup_buf;
	*response_pkt = cpu_to_le16(usb_status);
	dwc->ep0_usb_req.length = sizeof(*response_pkt);
	dwc3_ep0_send_status_response(dwc);

	return 0;
}

static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
		struct usb_ctrlrequest *ctrl, int set)
{
	struct dwc3_ep		*dep;
	u32			recip;
	u32			wValue;
	u32			wIndex;
	u32			reg;
	int			ret;
	u32			mode;

	wValue = le16_to_cpu(ctrl->wValue);
	wIndex = le16_to_cpu(ctrl->wIndex);
	recip = ctrl->bRequestType & USB_RECIP_MASK;
	switch (recip) {
	case USB_RECIP_DEVICE:

		/*
		 * 9.4.1 says only only for SS, in AddressState only for
		 * default control pipe
		 */
		switch (wValue) {
		case USB_DEVICE_U1_ENABLE:
		case USB_DEVICE_U2_ENABLE:
		case USB_DEVICE_LTM_ENABLE:
			if (dwc->dev_state != DWC3_CONFIGURED_STATE)
				return -EINVAL;
			if (dwc->speed != DWC3_DSTS_SUPERSPEED)
				return -EINVAL;
		}

		/* XXX add U[12] & LTM */
		switch (wValue) {
		case USB_DEVICE_REMOTE_WAKEUP:
			break;
		case USB_DEVICE_U1_ENABLE:
			break;
		case USB_DEVICE_U2_ENABLE:
			break;
		case USB_DEVICE_LTM_ENABLE:
			break;

		case USB_DEVICE_TEST_MODE:
			if ((wIndex & 0xff) != 0)
				return -EINVAL;
			if (!set)
				return -EINVAL;

			mode = wIndex >> 8;
			reg = dwc3_readl(dwc->regs, DWC3_DCTL);
			reg &= ~DWC3_DCTL_TSTCTRL_MASK;

			switch (mode) {
			case TEST_J:
			case TEST_K:
			case TEST_SE0_NAK:
			case TEST_PACKET:
			case TEST_FORCE_EN:
				reg |= mode << 1;
				break;
			default:
				return -EINVAL;
			}
			dwc3_writel(dwc->regs, DWC3_DCTL, reg);
			break;
		default:
			return -EINVAL;
		}
		break;

	case USB_RECIP_INTERFACE:
		switch (wValue) {
		case USB_INTRF_FUNC_SUSPEND:
			if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
				/* XXX enable Low power suspend */
				;
			if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
				/* XXX enable remote wakeup */
				;
			break;
		default:
			return -EINVAL;
		}
		break;

	case USB_RECIP_ENDPOINT:
		switch (wValue) {
		case USB_ENDPOINT_HALT:

			dep =  dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
			if (!dep)
				return -EINVAL;
			ret = __dwc3_gadget_ep_set_halt(dep, set);
			if (ret)
				return -EINVAL;
			break;
		default:
			return -EINVAL;
		}
		break;

	default:
		return -EINVAL;
	};

	return 0;
}

static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
{
	int ret = 0;
	u32 addr;
	u32 reg;

	addr = le16_to_cpu(ctrl->wValue);
	if (addr > 127)
		return -EINVAL;

	switch (dwc->dev_state) {
	case DWC3_DEFAULT_STATE:
	case DWC3_ADDRESS_STATE:
		/*
		 * Not sure if we should program DevAddr now or later
		 */
		reg = dwc3_readl(dwc->regs, DWC3_DCFG);
		reg &= ~(DWC3_DCFG_DEVADDR_MASK);
		reg |= DWC3_DCFG_DEVADDR(addr);
		dwc3_writel(dwc->regs, DWC3_DCFG, reg);

		if (addr)
			dwc->dev_state = DWC3_ADDRESS_STATE;
		else
			dwc->dev_state = DWC3_DEFAULT_STATE;
		break;

	case DWC3_CONFIGURED_STATE:
		ret = -EINVAL;
		break;
	}

	return ret;
}

static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
{
	int ret;

	spin_unlock(&dwc->lock);
	ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
	spin_lock(&dwc->lock);
	return ret;
}

static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
{
	u32 cfg;
	int ret;

	cfg = le16_to_cpu(ctrl->wValue);

	switch (dwc->dev_state) {
	case DWC3_DEFAULT_STATE:
		return -EINVAL;
		break;

	case DWC3_ADDRESS_STATE:
		ret = dwc3_ep0_delegate_req(dwc, ctrl);
		/* if the cfg matches and the cfg is non zero */
		if (!ret && cfg)
			dwc->dev_state = DWC3_CONFIGURED_STATE;
		break;

	case DWC3_CONFIGURED_STATE:
		ret = dwc3_ep0_delegate_req(dwc, ctrl);
		if (!cfg)
			dwc->dev_state = DWC3_ADDRESS_STATE;
		break;
	}
	return 0;
}

static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
{
	int ret;

	switch (ctrl->bRequest) {
	case USB_REQ_GET_STATUS:
		dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
		ret = dwc3_ep0_handle_status(dwc, ctrl);
		break;
	case USB_REQ_CLEAR_FEATURE:
		dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
		ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
		break;
	case USB_REQ_SET_FEATURE:
		dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
		ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
		break;
	case USB_REQ_SET_ADDRESS:
		dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
		ret = dwc3_ep0_set_address(dwc, ctrl);
		break;
	case USB_REQ_SET_CONFIGURATION:
		dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
		ret = dwc3_ep0_set_config(dwc, ctrl);
		break;
	default:
		dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
		ret = dwc3_ep0_delegate_req(dwc, ctrl);
		break;
	};

	return ret;
}

static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
		const struct dwc3_event_depevt *event)
{
	struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
	int ret;
	u32 len;

	if (!dwc->gadget_driver)
		goto err;

	len = le16_to_cpu(ctrl->wLength);
	if (!len)
		dwc->three_stage_setup = 0;
	else
		dwc->three_stage_setup = 1;

	if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
		ret = dwc3_ep0_std_request(dwc, ctrl);
	else
		ret = dwc3_ep0_delegate_req(dwc, ctrl);

	if (ret >= 0)
		return;

err:
	dwc3_ep0_stall_and_restart(dwc);
}

static void dwc3_ep0_complete_data(struct dwc3 *dwc,
		const struct dwc3_event_depevt *event)
{
	struct dwc3_request	*r = NULL;
	struct usb_request	*ur;
	struct dwc3_trb		trb;
	struct dwc3_ep		*dep;
	u32			transferred;
	u8			epnum;

	epnum = event->endpoint_number;
	dep = dwc->eps[epnum];

	if (!dwc->ep0_status_pending) {
		r = next_request(&dwc->eps[0]->request_list);
		ur = &r->request;
	} else {
		ur = &dwc->ep0_usb_req;
		dwc->ep0_status_pending = 0;
	}

	dwc3_trb_to_nat(dwc->ep0_trb, &trb);

	if (dwc->ep0_bounced) {
		struct dwc3_ep	*ep0 = dwc->eps[0];

		transferred = min_t(u32, ur->length,
				ep0->endpoint.maxpacket - trb.length);
		memcpy(ur->buf, dwc->ep0_bounce, transferred);
		dwc->ep0_bounced = false;
	} else {
		transferred = ur->length - trb.length;
		ur->actual += transferred;
	}

	if ((epnum & 1) && ur->actual < ur->length) {
		/* for some reason we did not get everything out */

		dwc3_ep0_stall_and_restart(dwc);
		dwc3_gadget_giveback(dep, r, -ECONNRESET);
	} else {
		/*
		 * handle the case where we have to send a zero packet. This
		 * seems to be case when req.length > maxpacket. Could it be?
		 */
		if (r)
			dwc3_gadget_giveback(dep, r, 0);
	}
}

static void dwc3_ep0_complete_req(struct dwc3 *dwc,
		const struct dwc3_event_depevt *event)
{
	struct dwc3_request	*r;
	struct dwc3_ep		*dep;

	dep = dwc->eps[0];

	if (!list_empty(&dep->request_list)) {
		r = next_request(&dep->request_list);

		dwc3_gadget_giveback(dep, r, 0);
	}

	dwc->ep0state = EP0_SETUP_PHASE;
	dwc3_ep0_out_start(dwc);
}

static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
			const struct dwc3_event_depevt *event)
{
	struct dwc3_ep		*dep = dwc->eps[event->endpoint_number];

	dep->flags &= ~DWC3_EP_BUSY;

	switch (dwc->ep0state) {
	case EP0_SETUP_PHASE:
		dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
		dwc3_ep0_inspect_setup(dwc, event);
		break;

	case EP0_DATA_PHASE:
		dev_vdbg(dwc->dev, "Data Phase\n");
		dwc3_ep0_complete_data(dwc, event);
		break;

	case EP0_STATUS_PHASE:
		dev_vdbg(dwc->dev, "Status Phase\n");
		dwc3_ep0_complete_req(dwc, event);
		break;
	default:
		WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
	}
}

static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
		const struct dwc3_event_depevt *event)
{
	dwc->ep0state = EP0_SETUP_PHASE;
	dwc3_ep0_out_start(dwc);
}

static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
		const struct dwc3_event_depevt *event)
{
	struct dwc3_ep		*dep;
	struct dwc3_request	*req;
	int			ret;

	dep = dwc->eps[0];
	dwc->ep0state = EP0_DATA_PHASE;

	if (list_empty(&dep->request_list)) {
		dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
		dep->flags |= DWC3_EP_PENDING_REQUEST;

		if (event->endpoint_number)
			dep->flags |= DWC3_EP0_DIR_IN;
		return;
	}

	req = next_request(&dep->request_list);
	req->direction = !!event->endpoint_number;

	dwc->ep0state = EP0_DATA_PHASE;
	if (req->request.length == 0) {
		ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
				dwc->ctrl_req_addr, 0,
				DWC3_TRBCTL_CONTROL_DATA);
	} else if ((req->request.length % dep->endpoint.maxpacket)
			&& (event->endpoint_number == 0)) {
		dwc3_map_buffer_to_dma(req);

		WARN_ON(req->request.length > dep->endpoint.maxpacket);

		dwc->ep0_bounced = true;

		/*
		 * REVISIT in case request length is bigger than EP0
		 * wMaxPacketSize, we will need two chained TRBs to handle
		 * the transfer.
		 */
		ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
				dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
				DWC3_TRBCTL_CONTROL_DATA);
	} else {
		dwc3_map_buffer_to_dma(req);

		ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
				req->request.dma, req->request.length,
				DWC3_TRBCTL_CONTROL_DATA);
	}

	WARN_ON(ret < 0);
}

static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
		const struct dwc3_event_depevt *event)
{
	u32			type;
	int			ret;

	dwc->ep0state = EP0_STATUS_PHASE;

	type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
		: DWC3_TRBCTL_CONTROL_STATUS2;

	ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
			dwc->ctrl_req_addr, 0, type);

	WARN_ON(ret < 0);
}

static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
		const struct dwc3_event_depevt *event)
{
	switch (event->status) {
	case DEPEVT_STATUS_CONTROL_SETUP:
		dev_vdbg(dwc->dev, "Control Setup\n");
		dwc3_ep0_do_control_setup(dwc, event);
		break;
	case DEPEVT_STATUS_CONTROL_DATA:
		dev_vdbg(dwc->dev, "Control Data\n");
		dwc3_ep0_do_control_data(dwc, event);
		break;
	case DEPEVT_STATUS_CONTROL_STATUS:
		dev_vdbg(dwc->dev, "Control Status\n");
		dwc3_ep0_do_control_status(dwc, event);
	}
}

void dwc3_ep0_interrupt(struct dwc3 *dwc,
		const const struct dwc3_event_depevt *event)
{
	u8			epnum = event->endpoint_number;

	dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
			dwc3_ep_event_string(event->endpoint_event),
			epnum, (epnum & 1) ? "in" : "out",
			dwc3_ep0_state_string(dwc->ep0state));

	switch (event->endpoint_event) {
	case DWC3_DEPEVT_XFERCOMPLETE:
		dwc3_ep0_xfer_complete(dwc, event);
		break;

	case DWC3_DEPEVT_XFERNOTREADY:
		dwc3_ep0_xfernotready(dwc, event);
		break;

	case DWC3_DEPEVT_XFERINPROGRESS:
	case DWC3_DEPEVT_RXTXFIFOEVT:
	case DWC3_DEPEVT_STREAMEVT:
	case DWC3_DEPEVT_EPCMDCMPLT:
		break;
	}
}
Commit	Line	Data
72246da4 FB	1	/**
	2	* ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
	3	*
	4	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
	5	* All rights reserved.
	6	*
	7	* Authors: Felipe Balbi <balbi@ti.com>,
	8	* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
	9	*
	10	* Redistribution and use in source and binary forms, with or without
	11	* modification, are permitted provided that the following conditions
	12	* are met:
	13	* 1. Redistributions of source code must retain the above copyright
	14	* notice, this list of conditions, and the following disclaimer,
	15	* without modification.
	16	* 2. Redistributions in binary form must reproduce the above copyright
	17	* notice, this list of conditions and the following disclaimer in the
	18	* documentation and/or other materials provided with the distribution.
	19	* 3. The names of the above-listed copyright holders may not be used
	20	* to endorse or promote products derived from this software without
	21	* specific prior written permission.
	22	*
	23	* ALTERNATIVELY, this software may be distributed under the terms of the
	24	* GNU General Public License ("GPL") version 2, as published by the Free
	25	* Software Foundation.
	26	*
	27	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
	28	* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
	29	* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
	30	* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
	31	* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
	32	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
	33	* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
	34	* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
	35	* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
	36	* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	37	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	38	*/
	39
	40	#include <linux/kernel.h>
	41	#include <linux/slab.h>
	42	#include <linux/spinlock.h>
	43	#include <linux/platform_device.h>
	44	#include <linux/pm_runtime.h>
	45	#include <linux/interrupt.h>
	46	#include <linux/io.h>
	47	#include <linux/list.h>
	48	#include <linux/dma-mapping.h>
	49
	50	#include <linux/usb/ch9.h>
	51	#include <linux/usb/gadget.h>
	52
	53	#include "core.h"
	54	#include "gadget.h"
	55	#include "io.h"
	56
	57	static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
	58	const struct dwc3_event_depevt *event);
	59
	60	static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
	61	{
	62	switch (state) {
	63	case EP0_UNCONNECTED:
	64	return "Unconnected";
c7fcdeb2 FB	65	case EP0_SETUP_PHASE:
	66	return "Setup Phase";
	67	case EP0_DATA_PHASE:
	68	return "Data Phase";
	69	case EP0_STATUS_PHASE:
	70	return "Status Phase";
72246da4 FB	71	case EP0_STALL:
	72	return "Stall";
	73	default:
	74	return "UNKNOWN";
	75	}
	76	}
	77
	78	static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
c7fcdeb2	79	u32 len, u32 type)
72246da4 FB	80	{
	81	struct dwc3_gadget_ep_cmd_params params;
	82	struct dwc3_trb_hw *trb_hw;
	83	struct dwc3_trb trb;
	84	struct dwc3_ep *dep;
	85
	86	int ret;
	87
	88	dep = dwc->eps[epnum];
c7fcdeb2 FB	89	if (dep->flags & DWC3_EP_BUSY) {
	90	dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
	91	return 0;
	92	}
72246da4 FB	93
	94	trb_hw = dwc->ep0_trb;
	95	memset(&trb, 0, sizeof(trb));
	96
c7fcdeb2	97	trb.trbctl = type;
72246da4 FB	98	trb.bplh = buf_dma;
	99	trb.length = len;
	100
	101	trb.hwo = 1;
	102	trb.lst = 1;
	103	trb.ioc = 1;
	104	trb.isp_imi = 1;
	105
	106	dwc3_trb_to_hw(&trb, trb_hw);
	107
	108	memset(&params, 0, sizeof(params));
	109	params.param0.depstrtxfer.transfer_desc_addr_high =
	110	upper_32_bits(dwc->ep0_trb_addr);
	111	params.param1.depstrtxfer.transfer_desc_addr_low =
	112	lower_32_bits(dwc->ep0_trb_addr);
	113
	114	ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
	115	DWC3_DEPCMD_STARTTRANSFER, &params);
	116	if (ret < 0) {
	117	dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
	118	return ret;
	119	}
	120
c7fcdeb2	121	dep->flags \|= DWC3_EP_BUSY;
72246da4 FB	122	dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
	123	dep->number);
	124
	125	return 0;
	126	}
	127
	128	static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
	129	struct dwc3_request *req)
	130	{
c7fcdeb2	131	int ret = 0;
72246da4 FB	132
	133	req->request.actual = 0;
	134	req->request.status = -EINPROGRESS;
72246da4 FB	135	req->epnum = dep->number;
	136
	137	list_add_tail(&req->list, &dep->request_list);
a6829706	138
c7fcdeb2 FB	139	/*
	140	* Gadget driver might not be quick enough to queue a request
	141	* before we get a Transfer Not Ready event on this endpoint.
	142	*
	143	* In that case, we will set DWC3_EP_PENDING_REQUEST. When that
	144	* flag is set, it's telling us that as soon as Gadget queues the
	145	* required request, we should kick the transfer here because the
	146	* IRQ we were waiting for is long gone.
	147	*/
	148	if (dep->flags & DWC3_EP_PENDING_REQUEST) {
	149	struct dwc3 *dwc = dep->dwc;
	150	unsigned direction;
	151	u32 type;
	152
	153	direction = !!(dep->flags & DWC3_EP0_DIR_IN);
	154
	155	if (dwc->ep0state == EP0_STATUS_PHASE) {
	156	type = dwc->three_stage_setup
	157	? DWC3_TRBCTL_CONTROL_STATUS3
	158	: DWC3_TRBCTL_CONTROL_STATUS2;
	159	} else if (dwc->ep0state == EP0_DATA_PHASE) {
	160	type = DWC3_TRBCTL_CONTROL_DATA;
	161	} else {
	162	/* should never happen */
	163	WARN_ON(1);
	164	return 0;
	165	}
72246da4	166
c7fcdeb2 FB	167	ret = dwc3_ep0_start_trans(dwc, direction,
	168	req->request.dma, req->request.length, type);
	169	dep->flags &= ~(DWC3_EP_PENDING_REQUEST \|
	170	DWC3_EP0_DIR_IN);
72246da4 FB	171	}
	172
	173	return ret;
	174	}
	175
	176	int dwc3_gadget_ep0_queue(struct usb_ep ep, struct usb_request request,
	177	gfp_t gfp_flags)
	178	{
	179	struct dwc3_request *req = to_dwc3_request(request);
	180	struct dwc3_ep *dep = to_dwc3_ep(ep);
	181	struct dwc3 *dwc = dep->dwc;
	182
	183	unsigned long flags;
	184
	185	int ret;
	186
72246da4 FB	187	spin_lock_irqsave(&dwc->lock, flags);
	188	if (!dep->desc) {
	189	dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
	190	request, dep->name);
	191	ret = -ESHUTDOWN;
	192	goto out;
	193	}
	194
	195	/* we share one TRB for ep0/1 */
	196	if (!list_empty(&dwc->eps[0]->request_list) \|\|
	197	!list_empty(&dwc->eps[1]->request_list) \|\|
	198	dwc->ep0_status_pending) {
	199	ret = -EBUSY;
	200	goto out;
	201	}
	202
	203	dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
	204	request, dep->name, request->length,
	205	dwc3_ep0_state_string(dwc->ep0state));
	206
	207	ret = __dwc3_gadget_ep0_queue(dep, req);
	208
	209	out:
	210	spin_unlock_irqrestore(&dwc->lock, flags);
	211
	212	return ret;
	213	}
	214
	215	static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
	216	{
	217	/* stall is always issued on EP0 */
	218	__dwc3_gadget_ep_set_halt(dwc->eps[0], 1);
	219	dwc->eps[0]->flags &= ~DWC3_EP_STALL;
c7fcdeb2	220	dwc->ep0state = EP0_SETUP_PHASE;
72246da4 FB	221	dwc3_ep0_out_start(dwc);
	222	}
	223
	224	void dwc3_ep0_out_start(struct dwc3 *dwc)
	225	{
72246da4 FB	226	int ret;
72246da4 FB	227
c7fcdeb2 FB	228	ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
c7fcdeb2 FB	229	DWC3_TRBCTL_CONTROL_SETUP);
72246da4 FB	230	WARN_ON(ret < 0);
	231	}
	232
72246da4 FB	233	static struct dwc3_ep dwc3_wIndex_to_dep(struct dwc3 dwc, __le16 wIndex_le)
	234	{
	235	struct dwc3_ep *dep;
	236	u32 windex = le16_to_cpu(wIndex_le);
	237	u32 epnum;
	238
	239	epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
	240	if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
	241	epnum \|= 1;
	242
	243	dep = dwc->eps[epnum];
	244	if (dep->flags & DWC3_EP_ENABLED)
	245	return dep;
	246
	247	return NULL;
	248	}
	249
	250	static void dwc3_ep0_send_status_response(struct dwc3 *dwc)
	251	{
b673cf30	252	dwc3_ep0_start_trans(dwc, 1, dwc->setup_buf_addr,
c7fcdeb2 FB	253	dwc->ep0_usb_req.length,
c7fcdeb2 FB	254	DWC3_TRBCTL_CONTROL_DATA);
72246da4 FB	255	dwc->ep0_status_pending = 1;
	256	}
	257
	258	/*
	259	* ch 9.4.5
	260	*/
	261	static int dwc3_ep0_handle_status(struct dwc3 dwc, struct usb_ctrlrequest ctrl)
	262	{
	263	struct dwc3_ep *dep;
	264	u32 recip;
	265	u16 usb_status = 0;
	266	__le16 *response_pkt;
	267
	268	recip = ctrl->bRequestType & USB_RECIP_MASK;
	269	switch (recip) {
	270	case USB_RECIP_DEVICE:
	271	/*
	272	* We are self-powered. U1/U2/LTM will be set later
	273	* once we handle this states. RemoteWakeup is 0 on SS
	274	*/
	275	usb_status \|= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
	276	break;
	277
	278	case USB_RECIP_INTERFACE:
	279	/*
	280	* Function Remote Wake Capable D0
	281	* Function Remote Wakeup D1
	282	*/
	283	break;
	284
	285	case USB_RECIP_ENDPOINT:
	286	dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
	287	if (!dep)
	288	return -EINVAL;
	289
	290	if (dep->flags & DWC3_EP_STALL)
	291	usb_status = 1 << USB_ENDPOINT_HALT;
	292	break;
	293	default:
	294	return -EINVAL;
	295	};
	296
	297	response_pkt = (__le16 *) dwc->setup_buf;
	298	*response_pkt = cpu_to_le16(usb_status);
	299	dwc->ep0_usb_req.length = sizeof(*response_pkt);
	300	dwc3_ep0_send_status_response(dwc);
	301
	302	return 0;
	303	}
	304
	305	static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
	306	struct usb_ctrlrequest *ctrl, int set)
	307	{
	308	struct dwc3_ep *dep;
	309	u32 recip;
	310	u32 wValue;
	311	u32 wIndex;
	312	u32 reg;
	313	int ret;
	314	u32 mode;
	315
	316	wValue = le16_to_cpu(ctrl->wValue);
	317	wIndex = le16_to_cpu(ctrl->wIndex);
	318	recip = ctrl->bRequestType & USB_RECIP_MASK;
319	switch (recip) {
320	case USB_RECIP_DEVICE:
321
322	/*
323	* 9.4.1 says only only for SS, in AddressState only for
324	* default control pipe
325	*/
326	switch (wValue) {
327	case USB_DEVICE_U1_ENABLE:
328	case USB_DEVICE_U2_ENABLE:
329	case USB_DEVICE_LTM_ENABLE:
330	if (dwc->dev_state != DWC3_CONFIGURED_STATE)
331	return -EINVAL;
332	if (dwc->speed != DWC3_DSTS_SUPERSPEED)
333	return -EINVAL;
334	}
335
336	/* XXX add U[12] & LTM */
337	switch (wValue) {
338	case USB_DEVICE_REMOTE_WAKEUP:
339	break;
340	case USB_DEVICE_U1_ENABLE:
341	break;
342	case USB_DEVICE_U2_ENABLE:
343	break;
344	case USB_DEVICE_LTM_ENABLE:
345	break;
346
347	case USB_DEVICE_TEST_MODE:
348	if ((wIndex & 0xff) != 0)
349	return -EINVAL;
350	if (!set)
351	return -EINVAL;
352
353	mode = wIndex >> 8;
354	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
355	reg &= ~DWC3_DCTL_TSTCTRL_MASK;
356
357	switch (mode) {
358	case TEST_J:
359	case TEST_K:
360	case TEST_SE0_NAK:
361	case TEST_PACKET:
362	case TEST_FORCE_EN:
363	reg \|= mode << 1;
364	break;
365	default:
366	return -EINVAL;
367	}
368	dwc3_writel(dwc->regs, DWC3_DCTL, reg);
369	break;
370	default:
371	return -EINVAL;
372	}
373	break;
374
375	case USB_RECIP_INTERFACE:
376	switch (wValue) {
377	case USB_INTRF_FUNC_SUSPEND:
378	if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
379	/* XXX enable Low power suspend */
380	;
381	if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
382	/* XXX enable remote wakeup */
383	;
384	break;
385	default:
386	return -EINVAL;
387	}
388	break;
389
390	case USB_RECIP_ENDPOINT:
391	switch (wValue) {
392	case USB_ENDPOINT_HALT:
393
394	dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
395	if (!dep)
396	return -EINVAL;
397	ret = __dwc3_gadget_ep_set_halt(dep, set);
398	if (ret)
399	return -EINVAL;
400	break;
401	default:
402	return -EINVAL;
403	}
404	break;
405
406	default:
407	return -EINVAL;
408	};
409
72246da4 FB	410	return 0;
	411	}
	412
	413	static int dwc3_ep0_set_address(struct dwc3 dwc, struct usb_ctrlrequest ctrl)
	414	{
	415	int ret = 0;
	416	u32 addr;
	417	u32 reg;
	418
	419	addr = le16_to_cpu(ctrl->wValue);
	420	if (addr > 127)
	421	return -EINVAL;
	422
	423	switch (dwc->dev_state) {
	424	case DWC3_DEFAULT_STATE:
	425	case DWC3_ADDRESS_STATE:
	426	/*
	427	* Not sure if we should program DevAddr now or later
	428	*/
	429	reg = dwc3_readl(dwc->regs, DWC3_DCFG);
	430	reg &= ~(DWC3_DCFG_DEVADDR_MASK);
	431	reg \|= DWC3_DCFG_DEVADDR(addr);
	432	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
	433
	434	if (addr)
	435	dwc->dev_state = DWC3_ADDRESS_STATE;
	436	else
	437	dwc->dev_state = DWC3_DEFAULT_STATE;
	438	break;
	439
	440	case DWC3_CONFIGURED_STATE:
	441	ret = -EINVAL;
	442	break;
	443	}
c7fcdeb2	444
72246da4 FB	445	return ret;
	446	}
	447
	448	static int dwc3_ep0_delegate_req(struct dwc3 dwc, struct usb_ctrlrequest ctrl)
	449	{
	450	int ret;
	451
	452	spin_unlock(&dwc->lock);
	453	ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
	454	spin_lock(&dwc->lock);
	455	return ret;
	456	}
	457
	458	static int dwc3_ep0_set_config(struct dwc3 dwc, struct usb_ctrlrequest ctrl)
	459	{
	460	u32 cfg;
	461	int ret;
	462
	463	cfg = le16_to_cpu(ctrl->wValue);
	464
	465	switch (dwc->dev_state) {
	466	case DWC3_DEFAULT_STATE:
	467	return -EINVAL;
	468	break;
	469
	470	case DWC3_ADDRESS_STATE:
	471	ret = dwc3_ep0_delegate_req(dwc, ctrl);
	472	/* if the cfg matches and the cfg is non zero */
	473	if (!ret && cfg)
	474	dwc->dev_state = DWC3_CONFIGURED_STATE;
	475	break;
	476
	477	case DWC3_CONFIGURED_STATE:
	478	ret = dwc3_ep0_delegate_req(dwc, ctrl);
	479	if (!cfg)
	480	dwc->dev_state = DWC3_ADDRESS_STATE;
	481	break;
	482	}
	483	return 0;
	484	}
	485
	486	static int dwc3_ep0_std_request(struct dwc3 dwc, struct usb_ctrlrequest ctrl)
	487	{
	488	int ret;
	489
	490	switch (ctrl->bRequest) {
	491	case USB_REQ_GET_STATUS:
	492	dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
	493	ret = dwc3_ep0_handle_status(dwc, ctrl);
	494	break;
	495	case USB_REQ_CLEAR_FEATURE:
	496	dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
	497	ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
	498	break;
	499	case USB_REQ_SET_FEATURE:
	500	dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
	501	ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
	502	break;
	503	case USB_REQ_SET_ADDRESS:
	504	dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
	505	ret = dwc3_ep0_set_address(dwc, ctrl);
	506	break;
	507	case USB_REQ_SET_CONFIGURATION:
	508	dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
509	ret = dwc3_ep0_set_config(dwc, ctrl);
510	break;
511	default:
512	dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
513	ret = dwc3_ep0_delegate_req(dwc, ctrl);
514	break;
515	};
516
517	return ret;
518	}
519
520	static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
521	const struct dwc3_event_depevt *event)
522	{
523	struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
524	int ret;
525	u32 len;
526
527	if (!dwc->gadget_driver)
528	goto err;
529
530	len = le16_to_cpu(ctrl->wLength);
c7fcdeb2	531	if (!len)
72246da4	532	dwc->three_stage_setup = 0;
c7fcdeb2	533	else
72246da4	534	dwc->three_stage_setup = 1;
72246da4 FB	535
	536	if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
	537	ret = dwc3_ep0_std_request(dwc, ctrl);
	538	else
	539	ret = dwc3_ep0_delegate_req(dwc, ctrl);
	540
	541	if (ret >= 0)
	542	return;
	543
	544	err:
	545	dwc3_ep0_stall_and_restart(dwc);
	546	}
	547
	548	static void dwc3_ep0_complete_data(struct dwc3 *dwc,
	549	const struct dwc3_event_depevt *event)
	550	{
	551	struct dwc3_request *r = NULL;
	552	struct usb_request *ur;
	553	struct dwc3_trb trb;
	554	struct dwc3_ep *dep;
c611ccb4	555	u32 transferred;
72246da4 FB	556	u8 epnum;
	557
	558	epnum = event->endpoint_number;
	559	dep = dwc->eps[epnum];
	560
	561	if (!dwc->ep0_status_pending) {
c7fcdeb2	562	r = next_request(&dwc->eps[0]->request_list);
72246da4 FB	563	ur = &r->request;
	564	} else {
	565	ur = &dwc->ep0_usb_req;
	566	dwc->ep0_status_pending = 0;
	567	}
	568
	569	dwc3_trb_to_nat(dwc->ep0_trb, &trb);
	570
a6829706 FB	571	if (dwc->ep0_bounced) {
	572	struct dwc3_ep *ep0 = dwc->eps[0];
	573
c7fcdeb2 FB	574	transferred = min_t(u32, ur->length,
c7fcdeb2 FB	575	ep0->endpoint.maxpacket - trb.length);
a6829706 FB	576	memcpy(ur->buf, dwc->ep0_bounce, transferred);
	577	dwc->ep0_bounced = false;
	578	} else {
	579	transferred = ur->length - trb.length;
	580	ur->actual += transferred;
	581	}
72246da4 FB	582
	583	if ((epnum & 1) && ur->actual < ur->length) {
	584	/* for some reason we did not get everything out */
	585
	586	dwc3_ep0_stall_and_restart(dwc);
	587	dwc3_gadget_giveback(dep, r, -ECONNRESET);
	588	} else {
	589	/*
	590	* handle the case where we have to send a zero packet. This
	591	* seems to be case when req.length > maxpacket. Could it be?
	592	*/
72246da4 FB	593	if (r)
	594	dwc3_gadget_giveback(dep, r, 0);
	595	}
	596	}
	597
	598	static void dwc3_ep0_complete_req(struct dwc3 *dwc,
	599	const struct dwc3_event_depevt *event)
	600	{
	601	struct dwc3_request *r;
	602	struct dwc3_ep *dep;
72246da4	603
c7fcdeb2	604	dep = dwc->eps[0];
72246da4 FB	605
	606	if (!list_empty(&dep->request_list)) {
	607	r = next_request(&dep->request_list);
	608
	609	dwc3_gadget_giveback(dep, r, 0);
	610	}
	611
c7fcdeb2	612	dwc->ep0state = EP0_SETUP_PHASE;
72246da4 FB	613	dwc3_ep0_out_start(dwc);
	614	}
	615
	616	static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
	617	const struct dwc3_event_depevt *event)
	618	{
c7fcdeb2 FB	619	struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
	620
	621	dep->flags &= ~DWC3_EP_BUSY;
	622
72246da4	623	switch (dwc->ep0state) {
c7fcdeb2 FB	624	case EP0_SETUP_PHASE:
c7fcdeb2 FB	625	dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
72246da4 FB	626	dwc3_ep0_inspect_setup(dwc, event);
	627	break;
	628
c7fcdeb2 FB	629	case EP0_DATA_PHASE:
c7fcdeb2 FB	630	dev_vdbg(dwc->dev, "Data Phase\n");
72246da4 FB	631	dwc3_ep0_complete_data(dwc, event);
	632	break;
	633
c7fcdeb2 FB	634	case EP0_STATUS_PHASE:
c7fcdeb2 FB	635	dev_vdbg(dwc->dev, "Status Phase\n");
72246da4 FB	636	dwc3_ep0_complete_req(dwc, event);
72246da4 FB	637	break;
c7fcdeb2 FB	638	default:
	639	WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
	640	}
	641	}
72246da4	642
c7fcdeb2 FB	643	static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
	644	const struct dwc3_event_depevt *event)
	645	{
	646	dwc->ep0state = EP0_SETUP_PHASE;
	647	dwc3_ep0_out_start(dwc);
	648	}
	649
	650	static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
	651	const struct dwc3_event_depevt *event)
	652	{
	653	struct dwc3_ep *dep;
	654	struct dwc3_request *req;
	655	int ret;
	656
	657	dep = dwc->eps[0];
	658	dwc->ep0state = EP0_DATA_PHASE;
	659
	660	if (list_empty(&dep->request_list)) {
	661	dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
	662	dep->flags \|= DWC3_EP_PENDING_REQUEST;
	663
	664	if (event->endpoint_number)
	665	dep->flags \|= DWC3_EP0_DIR_IN;
	666	return;
72246da4	667	}
c7fcdeb2 FB	668
	669	req = next_request(&dep->request_list);
	670	req->direction = !!event->endpoint_number;
	671
	672	dwc->ep0state = EP0_DATA_PHASE;
	673	if (req->request.length == 0) {
	674	ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
	675	dwc->ctrl_req_addr, 0,
	676	DWC3_TRBCTL_CONTROL_DATA);
	677	} else if ((req->request.length % dep->endpoint.maxpacket)
	678	&& (event->endpoint_number == 0)) {
	679	dwc3_map_buffer_to_dma(req);
	680
	681	WARN_ON(req->request.length > dep->endpoint.maxpacket);
	682
	683	dwc->ep0_bounced = true;
	684
	685	/*
	686	* REVISIT in case request length is bigger than EP0
	687	* wMaxPacketSize, we will need two chained TRBs to handle
	688	* the transfer.
	689	*/
	690	ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
	691	dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
	692	DWC3_TRBCTL_CONTROL_DATA);
	693	} else {
	694	dwc3_map_buffer_to_dma(req);
	695
	696	ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
	697	req->request.dma, req->request.length,
	698	DWC3_TRBCTL_CONTROL_DATA);
	699	}
	700
	701	WARN_ON(ret < 0);
72246da4 FB	702	}
72246da4 FB	703
c7fcdeb2	704	static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
72246da4 FB	705	const struct dwc3_event_depevt *event)
72246da4 FB	706	{
c7fcdeb2 FB	707	u32 type;
c7fcdeb2 FB	708	int ret;
72246da4	709
c7fcdeb2	710	dwc->ep0state = EP0_STATUS_PHASE;
72246da4	711
c7fcdeb2 FB	712	type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
	713	: DWC3_TRBCTL_CONTROL_STATUS2;
	714
	715	ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
	716	dwc->ctrl_req_addr, 0, type);
	717
	718	WARN_ON(ret < 0);
	719	}
	720
	721	static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
	722	const struct dwc3_event_depevt *event)
	723	{
	724	switch (event->status) {
	725	case DEPEVT_STATUS_CONTROL_SETUP:
	726	dev_vdbg(dwc->dev, "Control Setup\n");
	727	dwc3_ep0_do_control_setup(dwc, event);
	728	break;
	729	case DEPEVT_STATUS_CONTROL_DATA:
	730	dev_vdbg(dwc->dev, "Control Data\n");
	731	dwc3_ep0_do_control_data(dwc, event);
	732	break;
	733	case DEPEVT_STATUS_CONTROL_STATUS:
	734	dev_vdbg(dwc->dev, "Control Status\n");
	735	dwc3_ep0_do_control_status(dwc, event);
72246da4 FB	736	}
	737	}
	738
	739	void dwc3_ep0_interrupt(struct dwc3 *dwc,
	740	const const struct dwc3_event_depevt *event)
	741	{
	742	u8 epnum = event->endpoint_number;
	743
	744	dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
	745	dwc3_ep_event_string(event->endpoint_event),
	746	epnum, (epnum & 1) ? "in" : "out",
	747	dwc3_ep0_state_string(dwc->ep0state));
	748
	749	switch (event->endpoint_event) {
	750	case DWC3_DEPEVT_XFERCOMPLETE:
	751	dwc3_ep0_xfer_complete(dwc, event);
	752	break;
	753
	754	case DWC3_DEPEVT_XFERNOTREADY:
	755	dwc3_ep0_xfernotready(dwc, event);
	756	break;
	757
	758	case DWC3_DEPEVT_XFERINPROGRESS:
	759	case DWC3_DEPEVT_RXTXFIFOEVT:
	760	case DWC3_DEPEVT_STREAMEVT:
	761	case DWC3_DEPEVT_EPCMDCMPLT:
	762	break;
	763	}
	764	}