Commit | Line | Data |
---|---|---|
bfad65ee | 1 | /* |
72246da4 FB |
2 | * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/pm_runtime.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/list.h> | |
27 | #include <linux/dma-mapping.h> | |
28 | ||
29 | #include <linux/usb/ch9.h> | |
30 | #include <linux/usb/gadget.h> | |
5bdb1dcc | 31 | #include <linux/usb/composite.h> |
72246da4 FB |
32 | |
33 | #include "core.h" | |
80977dc9 | 34 | #include "debug.h" |
72246da4 FB |
35 | #include "gadget.h" |
36 | #include "io.h" | |
37 | ||
788a23f4 | 38 | static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); |
a0807881 FB |
39 | static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, |
40 | struct dwc3_ep *dep, struct dwc3_request *req); | |
5bdb1dcc | 41 | |
d686a5ff | 42 | static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep, |
7931ec86 | 43 | dma_addr_t buf_dma, u32 len, u32 type, bool chain) |
72246da4 | 44 | { |
f6bafc6a | 45 | struct dwc3_trb *trb; |
d686a5ff | 46 | struct dwc3 *dwc; |
72246da4 | 47 | |
d686a5ff | 48 | dwc = dep->dwc; |
53fd8818 | 49 | trb = &dwc->ep0_trb[dep->trb_enqueue]; |
2abd9d5f KVA |
50 | |
51 | if (chain) | |
53fd8818 | 52 | dep->trb_enqueue++; |
72246da4 | 53 | |
f6bafc6a FB |
54 | trb->bpl = lower_32_bits(buf_dma); |
55 | trb->bph = upper_32_bits(buf_dma); | |
56 | trb->size = len; | |
57 | trb->ctrl = type; | |
72246da4 | 58 | |
f6bafc6a | 59 | trb->ctrl |= (DWC3_TRB_CTRL_HWO |
f6bafc6a | 60 | | DWC3_TRB_CTRL_ISP_IMI); |
72246da4 | 61 | |
2abd9d5f KVA |
62 | if (chain) |
63 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
64 | else | |
65 | trb->ctrl |= (DWC3_TRB_CTRL_IOC | |
66 | | DWC3_TRB_CTRL_LST); | |
67 | ||
7931ec86 FB |
68 | trace_dwc3_prepare_trb(dep, trb); |
69 | } | |
70 | ||
d686a5ff | 71 | static int dwc3_ep0_start_trans(struct dwc3_ep *dep) |
7931ec86 FB |
72 | { |
73 | struct dwc3_gadget_ep_cmd_params params; | |
d686a5ff | 74 | struct dwc3 *dwc; |
7931ec86 FB |
75 | int ret; |
76 | ||
7931ec86 | 77 | if (dep->flags & DWC3_EP_BUSY) |
2abd9d5f KVA |
78 | return 0; |
79 | ||
d686a5ff FB |
80 | dwc = dep->dwc; |
81 | ||
72246da4 | 82 | memset(¶ms, 0, sizeof(params)); |
dc1c70a7 FB |
83 | params.param0 = upper_32_bits(dwc->ep0_trb_addr); |
84 | params.param1 = lower_32_bits(dwc->ep0_trb_addr); | |
72246da4 | 85 | |
2cd4718d | 86 | ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms); |
8566cd1a | 87 | if (ret < 0) |
72246da4 | 88 | return ret; |
72246da4 | 89 | |
c7fcdeb2 | 90 | dep->flags |= DWC3_EP_BUSY; |
2eb88016 | 91 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep); |
1ddcb218 FB |
92 | dwc->ep0_next_event = DWC3_EP0_COMPLETE; |
93 | ||
72246da4 FB |
94 | return 0; |
95 | } | |
96 | ||
97 | static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, | |
98 | struct dwc3_request *req) | |
99 | { | |
5bdb1dcc | 100 | struct dwc3 *dwc = dep->dwc; |
72246da4 FB |
101 | |
102 | req->request.actual = 0; | |
103 | req->request.status = -EINPROGRESS; | |
72246da4 FB |
104 | req->epnum = dep->number; |
105 | ||
aa3342c8 | 106 | list_add_tail(&req->list, &dep->pending_list); |
a6829706 | 107 | |
c7fcdeb2 FB |
108 | /* |
109 | * Gadget driver might not be quick enough to queue a request | |
110 | * before we get a Transfer Not Ready event on this endpoint. | |
111 | * | |
112 | * In that case, we will set DWC3_EP_PENDING_REQUEST. When that | |
113 | * flag is set, it's telling us that as soon as Gadget queues the | |
114 | * required request, we should kick the transfer here because the | |
115 | * IRQ we were waiting for is long gone. | |
116 | */ | |
117 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
c7fcdeb2 | 118 | unsigned direction; |
c7fcdeb2 FB |
119 | |
120 | direction = !!(dep->flags & DWC3_EP0_DIR_IN); | |
121 | ||
68d8a781 FB |
122 | if (dwc->ep0state != EP0_DATA_PHASE) { |
123 | dev_WARN(dwc->dev, "Unexpected pending request\n"); | |
c7fcdeb2 FB |
124 | return 0; |
125 | } | |
72246da4 | 126 | |
a0807881 FB |
127 | __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); |
128 | ||
c7fcdeb2 FB |
129 | dep->flags &= ~(DWC3_EP_PENDING_REQUEST | |
130 | DWC3_EP0_DIR_IN); | |
d9b33c60 FB |
131 | |
132 | return 0; | |
133 | } | |
134 | ||
135 | /* | |
136 | * In case gadget driver asked us to delay the STATUS phase, | |
137 | * handle it here. | |
138 | */ | |
139 | if (dwc->delayed_status) { | |
7125d584 FB |
140 | unsigned direction; |
141 | ||
142 | direction = !dwc->ep0_expect_in; | |
5bdb1dcc | 143 | dwc->delayed_status = false; |
7c81290e | 144 | usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED); |
68d3e668 FB |
145 | |
146 | if (dwc->ep0state == EP0_STATUS_PHASE) | |
7125d584 | 147 | __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); |
d9b33c60 FB |
148 | |
149 | return 0; | |
72246da4 FB |
150 | } |
151 | ||
fca8892a FB |
152 | /* |
153 | * Unfortunately we have uncovered a limitation wrt the Data Phase. | |
154 | * | |
155 | * Section 9.4 says we can wait for the XferNotReady(DATA) event to | |
156 | * come before issueing Start Transfer command, but if we do, we will | |
157 | * miss situations where the host starts another SETUP phase instead of | |
158 | * the DATA phase. Such cases happen at least on TD.7.6 of the Link | |
159 | * Layer Compliance Suite. | |
160 | * | |
161 | * The problem surfaces due to the fact that in case of back-to-back | |
162 | * SETUP packets there will be no XferNotReady(DATA) generated and we | |
163 | * will be stuck waiting for XferNotReady(DATA) forever. | |
164 | * | |
165 | * By looking at tables 9-13 and 9-14 of the Databook, we can see that | |
166 | * it tells us to start Data Phase right away. It also mentions that if | |
167 | * we receive a SETUP phase instead of the DATA phase, core will issue | |
168 | * XferComplete for the DATA phase, before actually initiating it in | |
169 | * the wire, with the TRB's status set to "SETUP_PENDING". Such status | |
170 | * can only be used to print some debugging logs, as the core expects | |
171 | * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, | |
172 | * just so it completes right away, without transferring anything and, | |
173 | * only then, we can go back to the SETUP phase. | |
174 | * | |
175 | * Because of this scenario, SNPS decided to change the programming | |
176 | * model of control transfers and support on-demand transfers only for | |
177 | * the STATUS phase. To fix the issue we have now, we will always wait | |
178 | * for gadget driver to queue the DATA phase's struct usb_request, then | |
179 | * start it right away. | |
180 | * | |
181 | * If we're actually in a 2-stage transfer, we will wait for | |
182 | * XferNotReady(STATUS). | |
183 | */ | |
184 | if (dwc->three_stage_setup) { | |
185 | unsigned direction; | |
186 | ||
187 | direction = dwc->ep0_expect_in; | |
188 | dwc->ep0state = EP0_DATA_PHASE; | |
189 | ||
190 | __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); | |
191 | ||
192 | dep->flags &= ~DWC3_EP0_DIR_IN; | |
193 | } | |
194 | ||
35f75696 | 195 | return 0; |
72246da4 FB |
196 | } |
197 | ||
198 | int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, | |
199 | gfp_t gfp_flags) | |
200 | { | |
201 | struct dwc3_request *req = to_dwc3_request(request); | |
202 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
203 | struct dwc3 *dwc = dep->dwc; | |
204 | ||
205 | unsigned long flags; | |
206 | ||
207 | int ret; | |
208 | ||
72246da4 | 209 | spin_lock_irqsave(&dwc->lock, flags); |
16e78db7 | 210 | if (!dep->endpoint.desc) { |
5eb30ced FB |
211 | dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", |
212 | dep->name); | |
72246da4 FB |
213 | ret = -ESHUTDOWN; |
214 | goto out; | |
215 | } | |
216 | ||
217 | /* we share one TRB for ep0/1 */ | |
aa3342c8 | 218 | if (!list_empty(&dep->pending_list)) { |
72246da4 FB |
219 | ret = -EBUSY; |
220 | goto out; | |
221 | } | |
222 | ||
72246da4 FB |
223 | ret = __dwc3_gadget_ep0_queue(dep, req); |
224 | ||
225 | out: | |
226 | spin_unlock_irqrestore(&dwc->lock, flags); | |
227 | ||
228 | return ret; | |
229 | } | |
230 | ||
231 | static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) | |
232 | { | |
2dfe37d4 FB |
233 | struct dwc3_ep *dep; |
234 | ||
235 | /* reinitialize physical ep1 */ | |
236 | dep = dwc->eps[1]; | |
237 | dep->flags = DWC3_EP_ENABLED; | |
d742220b | 238 | |
72246da4 | 239 | /* stall is always issued on EP0 */ |
2dfe37d4 | 240 | dep = dwc->eps[0]; |
7a608559 | 241 | __dwc3_gadget_ep_set_halt(dep, 1, false); |
c2da2ff0 | 242 | dep->flags = DWC3_EP_ENABLED; |
5bdb1dcc | 243 | dwc->delayed_status = false; |
d742220b | 244 | |
aa3342c8 | 245 | if (!list_empty(&dep->pending_list)) { |
d742220b FB |
246 | struct dwc3_request *req; |
247 | ||
aa3342c8 | 248 | req = next_request(&dep->pending_list); |
d742220b FB |
249 | dwc3_gadget_giveback(dep, req, -ECONNRESET); |
250 | } | |
251 | ||
c7fcdeb2 | 252 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
253 | dwc3_ep0_out_start(dwc); |
254 | } | |
255 | ||
33fb691b | 256 | int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) |
08f0d966 PA |
257 | { |
258 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
259 | struct dwc3 *dwc = dep->dwc; | |
260 | ||
261 | dwc3_ep0_stall_and_restart(dwc); | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
33fb691b FB |
266 | int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) |
267 | { | |
268 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
269 | struct dwc3 *dwc = dep->dwc; | |
270 | unsigned long flags; | |
271 | int ret; | |
272 | ||
273 | spin_lock_irqsave(&dwc->lock, flags); | |
274 | ret = __dwc3_gadget_ep0_set_halt(ep, value); | |
275 | spin_unlock_irqrestore(&dwc->lock, flags); | |
276 | ||
277 | return ret; | |
278 | } | |
279 | ||
72246da4 FB |
280 | void dwc3_ep0_out_start(struct dwc3 *dwc) |
281 | { | |
d686a5ff | 282 | struct dwc3_ep *dep; |
72246da4 FB |
283 | int ret; |
284 | ||
bb014736 BW |
285 | complete(&dwc->ep0_in_setup); |
286 | ||
d686a5ff FB |
287 | dep = dwc->eps[0]; |
288 | dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8, | |
368ca113 | 289 | DWC3_TRBCTL_CONTROL_SETUP, false); |
d686a5ff | 290 | ret = dwc3_ep0_start_trans(dep); |
72246da4 FB |
291 | WARN_ON(ret < 0); |
292 | } | |
293 | ||
72246da4 FB |
294 | static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) |
295 | { | |
296 | struct dwc3_ep *dep; | |
297 | u32 windex = le16_to_cpu(wIndex_le); | |
298 | u32 epnum; | |
299 | ||
300 | epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; | |
301 | if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) | |
302 | epnum |= 1; | |
303 | ||
304 | dep = dwc->eps[epnum]; | |
305 | if (dep->flags & DWC3_EP_ENABLED) | |
306 | return dep; | |
307 | ||
308 | return NULL; | |
309 | } | |
310 | ||
8ee6270c | 311 | static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) |
72246da4 | 312 | { |
72246da4 | 313 | } |
72246da4 FB |
314 | /* |
315 | * ch 9.4.5 | |
316 | */ | |
25b8ff68 FB |
317 | static int dwc3_ep0_handle_status(struct dwc3 *dwc, |
318 | struct usb_ctrlrequest *ctrl) | |
72246da4 FB |
319 | { |
320 | struct dwc3_ep *dep; | |
321 | u32 recip; | |
9b0a1f95 | 322 | u32 value; |
e6a3b5e2 | 323 | u32 reg; |
72246da4 FB |
324 | u16 usb_status = 0; |
325 | __le16 *response_pkt; | |
326 | ||
9b0a1f95 FB |
327 | /* We don't support PTM_STATUS */ |
328 | value = le16_to_cpu(ctrl->wValue); | |
329 | if (value != 0) | |
330 | return -EINVAL; | |
331 | ||
72246da4 FB |
332 | recip = ctrl->bRequestType & USB_RECIP_MASK; |
333 | switch (recip) { | |
334 | case USB_RECIP_DEVICE: | |
335 | /* | |
e6a3b5e2 | 336 | * LTM will be set once we know how to set this in HW. |
72246da4 | 337 | */ |
bcdea503 | 338 | usb_status |= dwc->gadget.is_selfpowered; |
e6a3b5e2 | 339 | |
ee5cd41c JY |
340 | if ((dwc->speed == DWC3_DSTS_SUPERSPEED) || |
341 | (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) { | |
e6a3b5e2 SAS |
342 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
343 | if (reg & DWC3_DCTL_INITU1ENA) | |
344 | usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; | |
345 | if (reg & DWC3_DCTL_INITU2ENA) | |
346 | usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; | |
347 | } | |
348 | ||
72246da4 FB |
349 | break; |
350 | ||
351 | case USB_RECIP_INTERFACE: | |
352 | /* | |
353 | * Function Remote Wake Capable D0 | |
354 | * Function Remote Wakeup D1 | |
355 | */ | |
356 | break; | |
357 | ||
358 | case USB_RECIP_ENDPOINT: | |
359 | dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); | |
360 | if (!dep) | |
25b8ff68 | 361 | return -EINVAL; |
72246da4 FB |
362 | |
363 | if (dep->flags & DWC3_EP_STALL) | |
364 | usb_status = 1 << USB_ENDPOINT_HALT; | |
365 | break; | |
366 | default: | |
367 | return -EINVAL; | |
2b84f92b | 368 | } |
72246da4 FB |
369 | |
370 | response_pkt = (__le16 *) dwc->setup_buf; | |
371 | *response_pkt = cpu_to_le16(usb_status); | |
e2617796 FB |
372 | |
373 | dep = dwc->eps[0]; | |
374 | dwc->ep0_usb_req.dep = dep; | |
e0ce0b0a | 375 | dwc->ep0_usb_req.request.length = sizeof(*response_pkt); |
0fc9a1be | 376 | dwc->ep0_usb_req.request.buf = dwc->setup_buf; |
e0ce0b0a | 377 | dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; |
e2617796 FB |
378 | |
379 | return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); | |
72246da4 FB |
380 | } |
381 | ||
39e07ffb FB |
382 | static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state, |
383 | int set) | |
384 | { | |
385 | u32 reg; | |
386 | ||
387 | if (state != USB_STATE_CONFIGURED) | |
388 | return -EINVAL; | |
389 | if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && | |
390 | (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) | |
391 | return -EINVAL; | |
392 | ||
393 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
394 | if (set) | |
395 | reg |= DWC3_DCTL_INITU1ENA; | |
396 | else | |
397 | reg &= ~DWC3_DCTL_INITU1ENA; | |
398 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
403 | static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state, | |
404 | int set) | |
405 | { | |
406 | u32 reg; | |
407 | ||
408 | ||
409 | if (state != USB_STATE_CONFIGURED) | |
410 | return -EINVAL; | |
411 | if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && | |
412 | (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) | |
413 | return -EINVAL; | |
414 | ||
415 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
416 | if (set) | |
417 | reg |= DWC3_DCTL_INITU2ENA; | |
418 | else | |
419 | reg &= ~DWC3_DCTL_INITU2ENA; | |
420 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
421 | ||
422 | return 0; | |
423 | } | |
424 | ||
425 | static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state, | |
426 | u32 wIndex, int set) | |
427 | { | |
428 | if ((wIndex & 0xff) != 0) | |
429 | return -EINVAL; | |
430 | if (!set) | |
431 | return -EINVAL; | |
432 | ||
433 | switch (wIndex >> 8) { | |
434 | case TEST_J: | |
435 | case TEST_K: | |
436 | case TEST_SE0_NAK: | |
437 | case TEST_PACKET: | |
438 | case TEST_FORCE_EN: | |
439 | dwc->test_mode_nr = wIndex >> 8; | |
440 | dwc->test_mode = true; | |
441 | break; | |
442 | default: | |
443 | return -EINVAL; | |
444 | } | |
445 | ||
446 | return 0; | |
447 | } | |
448 | ||
449 | static int dwc3_ep0_handle_device(struct dwc3 *dwc, | |
72246da4 FB |
450 | struct usb_ctrlrequest *ctrl, int set) |
451 | { | |
39e07ffb | 452 | enum usb_device_state state; |
72246da4 FB |
453 | u32 wValue; |
454 | u32 wIndex; | |
39e07ffb | 455 | int ret = 0; |
72246da4 FB |
456 | |
457 | wValue = le16_to_cpu(ctrl->wValue); | |
458 | wIndex = le16_to_cpu(ctrl->wIndex); | |
fdba5aa5 FB |
459 | state = dwc->gadget.state; |
460 | ||
39e07ffb FB |
461 | switch (wValue) { |
462 | case USB_DEVICE_REMOTE_WAKEUP: | |
463 | break; | |
464 | /* | |
465 | * 9.4.1 says only only for SS, in AddressState only for | |
466 | * default control pipe | |
467 | */ | |
468 | case USB_DEVICE_U1_ENABLE: | |
469 | ret = dwc3_ep0_handle_u1(dwc, state, set); | |
470 | break; | |
471 | case USB_DEVICE_U2_ENABLE: | |
472 | ret = dwc3_ep0_handle_u2(dwc, state, set); | |
473 | break; | |
474 | case USB_DEVICE_LTM_ENABLE: | |
475 | ret = -EINVAL; | |
476 | break; | |
477 | case USB_DEVICE_TEST_MODE: | |
478 | ret = dwc3_ep0_handle_test(dwc, state, wIndex, set); | |
479 | break; | |
480 | default: | |
481 | ret = -EINVAL; | |
482 | } | |
72246da4 | 483 | |
39e07ffb FB |
484 | return ret; |
485 | } | |
72246da4 | 486 | |
39e07ffb FB |
487 | static int dwc3_ep0_handle_intf(struct dwc3 *dwc, |
488 | struct usb_ctrlrequest *ctrl, int set) | |
489 | { | |
490 | enum usb_device_state state; | |
491 | u32 wValue; | |
492 | u32 wIndex; | |
493 | int ret = 0; | |
e6a3b5e2 | 494 | |
39e07ffb FB |
495 | wValue = le16_to_cpu(ctrl->wValue); |
496 | wIndex = le16_to_cpu(ctrl->wIndex); | |
497 | state = dwc->gadget.state; | |
e6a3b5e2 | 498 | |
39e07ffb FB |
499 | switch (wValue) { |
500 | case USB_INTRF_FUNC_SUSPEND: | |
1c404b51 AB |
501 | /* |
502 | * REVISIT: Ideally we would enable some low power mode here, | |
503 | * however it's unclear what we should be doing here. | |
504 | * | |
505 | * For now, we're not doing anything, just making sure we return | |
506 | * 0 so USB Command Verifier tests pass without any errors. | |
507 | */ | |
39e07ffb FB |
508 | break; |
509 | default: | |
510 | ret = -EINVAL; | |
511 | } | |
e6a3b5e2 | 512 | |
39e07ffb FB |
513 | return ret; |
514 | } | |
515 | ||
516 | static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc, | |
517 | struct usb_ctrlrequest *ctrl, int set) | |
518 | { | |
519 | struct dwc3_ep *dep; | |
520 | enum usb_device_state state; | |
521 | u32 wValue; | |
522 | u32 wIndex; | |
523 | int ret; | |
524 | ||
525 | wValue = le16_to_cpu(ctrl->wValue); | |
526 | wIndex = le16_to_cpu(ctrl->wIndex); | |
527 | state = dwc->gadget.state; | |
528 | ||
529 | switch (wValue) { | |
530 | case USB_ENDPOINT_HALT: | |
531 | dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); | |
532 | if (!dep) | |
e6a3b5e2 | 533 | return -EINVAL; |
72246da4 | 534 | |
39e07ffb | 535 | if (set == 0 && (dep->flags & DWC3_EP_WEDGE)) |
ecb07797 | 536 | break; |
39e07ffb FB |
537 | |
538 | ret = __dwc3_gadget_ep_set_halt(dep, set, true); | |
539 | if (ret) | |
ecb07797 | 540 | return -EINVAL; |
72246da4 | 541 | break; |
39e07ffb FB |
542 | default: |
543 | return -EINVAL; | |
544 | } | |
545 | ||
546 | return 0; | |
547 | } | |
548 | ||
549 | static int dwc3_ep0_handle_feature(struct dwc3 *dwc, | |
550 | struct usb_ctrlrequest *ctrl, int set) | |
551 | { | |
552 | u32 recip; | |
553 | int ret; | |
554 | enum usb_device_state state; | |
555 | ||
556 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
557 | state = dwc->gadget.state; | |
72246da4 | 558 | |
39e07ffb FB |
559 | switch (recip) { |
560 | case USB_RECIP_DEVICE: | |
561 | ret = dwc3_ep0_handle_device(dwc, ctrl, set); | |
562 | break; | |
72246da4 | 563 | case USB_RECIP_INTERFACE: |
39e07ffb | 564 | ret = dwc3_ep0_handle_intf(dwc, ctrl, set); |
72246da4 | 565 | break; |
72246da4 | 566 | case USB_RECIP_ENDPOINT: |
39e07ffb | 567 | ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set); |
72246da4 | 568 | break; |
72246da4 | 569 | default: |
39e07ffb | 570 | ret = -EINVAL; |
2b84f92b | 571 | } |
72246da4 | 572 | |
39e07ffb | 573 | return ret; |
72246da4 FB |
574 | } |
575 | ||
576 | static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
577 | { | |
fdba5aa5 | 578 | enum usb_device_state state = dwc->gadget.state; |
72246da4 FB |
579 | u32 addr; |
580 | u32 reg; | |
581 | ||
582 | addr = le16_to_cpu(ctrl->wValue); | |
f96a6ec1 | 583 | if (addr > 127) { |
5eb30ced | 584 | dev_err(dwc->dev, "invalid device address %d\n", addr); |
72246da4 | 585 | return -EINVAL; |
f96a6ec1 FB |
586 | } |
587 | ||
fdba5aa5 | 588 | if (state == USB_STATE_CONFIGURED) { |
5eb30ced | 589 | dev_err(dwc->dev, "can't SetAddress() from Configured State\n"); |
f96a6ec1 FB |
590 | return -EINVAL; |
591 | } | |
72246da4 | 592 | |
2646021e FB |
593 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
594 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
595 | reg |= DWC3_DCFG_DEVADDR(addr); | |
596 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 | 597 | |
fdba5aa5 | 598 | if (addr) |
14cd592f | 599 | usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS); |
fdba5aa5 | 600 | else |
14cd592f | 601 | usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); |
c7fcdeb2 | 602 | |
2646021e | 603 | return 0; |
72246da4 FB |
604 | } |
605 | ||
606 | static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
607 | { | |
608 | int ret; | |
609 | ||
610 | spin_unlock(&dwc->lock); | |
611 | ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); | |
612 | spin_lock(&dwc->lock); | |
613 | return ret; | |
614 | } | |
615 | ||
616 | static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
617 | { | |
fdba5aa5 | 618 | enum usb_device_state state = dwc->gadget.state; |
72246da4 FB |
619 | u32 cfg; |
620 | int ret; | |
e274a31e | 621 | u32 reg; |
72246da4 FB |
622 | |
623 | cfg = le16_to_cpu(ctrl->wValue); | |
624 | ||
fdba5aa5 FB |
625 | switch (state) { |
626 | case USB_STATE_DEFAULT: | |
72246da4 | 627 | return -EINVAL; |
72246da4 | 628 | |
fdba5aa5 | 629 | case USB_STATE_ADDRESS: |
72246da4 FB |
630 | ret = dwc3_ep0_delegate_req(dwc, ctrl); |
631 | /* if the cfg matches and the cfg is non zero */ | |
457e84b6 | 632 | if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { |
7c81290e FB |
633 | |
634 | /* | |
635 | * only change state if set_config has already | |
636 | * been processed. If gadget driver returns | |
637 | * USB_GADGET_DELAYED_STATUS, we will wait | |
638 | * to change the state on the next usb_ep_queue() | |
639 | */ | |
640 | if (ret == 0) | |
641 | usb_gadget_set_state(&dwc->gadget, | |
642 | USB_STATE_CONFIGURED); | |
14cd592f | 643 | |
e274a31e PA |
644 | /* |
645 | * Enable transition to U1/U2 state when | |
646 | * nothing is pending from application. | |
647 | */ | |
648 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
649 | reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); | |
650 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
457e84b6 | 651 | } |
72246da4 FB |
652 | break; |
653 | ||
fdba5aa5 | 654 | case USB_STATE_CONFIGURED: |
72246da4 | 655 | ret = dwc3_ep0_delegate_req(dwc, ctrl); |
7a42d835 | 656 | if (!cfg && !ret) |
14cd592f FB |
657 | usb_gadget_set_state(&dwc->gadget, |
658 | USB_STATE_ADDRESS); | |
72246da4 | 659 | break; |
5bdb1dcc SAS |
660 | default: |
661 | ret = -EINVAL; | |
72246da4 | 662 | } |
5bdb1dcc | 663 | return ret; |
72246da4 FB |
664 | } |
665 | ||
865e09e7 FB |
666 | static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) |
667 | { | |
668 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
669 | struct dwc3 *dwc = dep->dwc; | |
670 | ||
671 | u32 param = 0; | |
672 | u32 reg; | |
673 | ||
674 | struct timing { | |
675 | u8 u1sel; | |
676 | u8 u1pel; | |
501058ed JY |
677 | __le16 u2sel; |
678 | __le16 u2pel; | |
865e09e7 FB |
679 | } __packed timing; |
680 | ||
681 | int ret; | |
682 | ||
683 | memcpy(&timing, req->buf, sizeof(timing)); | |
684 | ||
685 | dwc->u1sel = timing.u1sel; | |
686 | dwc->u1pel = timing.u1pel; | |
c8cf7af4 FB |
687 | dwc->u2sel = le16_to_cpu(timing.u2sel); |
688 | dwc->u2pel = le16_to_cpu(timing.u2pel); | |
865e09e7 FB |
689 | |
690 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
691 | if (reg & DWC3_DCTL_INITU2ENA) | |
692 | param = dwc->u2pel; | |
693 | if (reg & DWC3_DCTL_INITU1ENA) | |
694 | param = dwc->u1pel; | |
695 | ||
696 | /* | |
697 | * According to Synopsys Databook, if parameter is | |
698 | * greater than 125, a value of zero should be | |
699 | * programmed in the register. | |
700 | */ | |
701 | if (param > 125) | |
702 | param = 0; | |
703 | ||
704 | /* now that we have the time, issue DGCMD Set Sel */ | |
705 | ret = dwc3_send_gadget_generic_command(dwc, | |
706 | DWC3_DGCMD_SET_PERIODIC_PAR, param); | |
707 | WARN_ON(ret < 0); | |
708 | } | |
709 | ||
710 | static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
711 | { | |
712 | struct dwc3_ep *dep; | |
fdba5aa5 | 713 | enum usb_device_state state = dwc->gadget.state; |
865e09e7 FB |
714 | u16 wLength; |
715 | u16 wValue; | |
716 | ||
fdba5aa5 | 717 | if (state == USB_STATE_DEFAULT) |
865e09e7 FB |
718 | return -EINVAL; |
719 | ||
720 | wValue = le16_to_cpu(ctrl->wValue); | |
721 | wLength = le16_to_cpu(ctrl->wLength); | |
722 | ||
723 | if (wLength != 6) { | |
724 | dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", | |
725 | wLength); | |
726 | return -EINVAL; | |
727 | } | |
728 | ||
729 | /* | |
730 | * To handle Set SEL we need to receive 6 bytes from Host. So let's | |
731 | * queue a usb_request for 6 bytes. | |
732 | * | |
733 | * Remember, though, this controller can't handle non-wMaxPacketSize | |
734 | * aligned transfers on the OUT direction, so we queue a request for | |
735 | * wMaxPacketSize instead. | |
736 | */ | |
737 | dep = dwc->eps[0]; | |
738 | dwc->ep0_usb_req.dep = dep; | |
739 | dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; | |
740 | dwc->ep0_usb_req.request.buf = dwc->setup_buf; | |
741 | dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; | |
742 | ||
743 | return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); | |
744 | } | |
745 | ||
c12a0d86 FB |
746 | static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) |
747 | { | |
748 | u16 wLength; | |
749 | u16 wValue; | |
750 | u16 wIndex; | |
751 | ||
752 | wValue = le16_to_cpu(ctrl->wValue); | |
753 | wLength = le16_to_cpu(ctrl->wLength); | |
754 | wIndex = le16_to_cpu(ctrl->wIndex); | |
755 | ||
756 | if (wIndex || wLength) | |
757 | return -EINVAL; | |
758 | ||
759 | /* | |
760 | * REVISIT It's unclear from Databook what to do with this | |
761 | * value. For now, just cache it. | |
762 | */ | |
763 | dwc->isoch_delay = wValue; | |
764 | ||
765 | return 0; | |
766 | } | |
767 | ||
72246da4 FB |
768 | static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) |
769 | { | |
770 | int ret; | |
771 | ||
772 | switch (ctrl->bRequest) { | |
773 | case USB_REQ_GET_STATUS: | |
72246da4 FB |
774 | ret = dwc3_ep0_handle_status(dwc, ctrl); |
775 | break; | |
776 | case USB_REQ_CLEAR_FEATURE: | |
72246da4 FB |
777 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); |
778 | break; | |
779 | case USB_REQ_SET_FEATURE: | |
72246da4 FB |
780 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); |
781 | break; | |
782 | case USB_REQ_SET_ADDRESS: | |
72246da4 FB |
783 | ret = dwc3_ep0_set_address(dwc, ctrl); |
784 | break; | |
785 | case USB_REQ_SET_CONFIGURATION: | |
72246da4 FB |
786 | ret = dwc3_ep0_set_config(dwc, ctrl); |
787 | break; | |
865e09e7 | 788 | case USB_REQ_SET_SEL: |
865e09e7 FB |
789 | ret = dwc3_ep0_set_sel(dwc, ctrl); |
790 | break; | |
c12a0d86 | 791 | case USB_REQ_SET_ISOCH_DELAY: |
c12a0d86 FB |
792 | ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); |
793 | break; | |
72246da4 | 794 | default: |
72246da4 FB |
795 | ret = dwc3_ep0_delegate_req(dwc, ctrl); |
796 | break; | |
2b84f92b | 797 | } |
72246da4 FB |
798 | |
799 | return ret; | |
800 | } | |
801 | ||
802 | static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, | |
803 | const struct dwc3_event_depevt *event) | |
804 | { | |
7d5e650a | 805 | struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb; |
ef21ede6 | 806 | int ret = -EINVAL; |
72246da4 FB |
807 | u32 len; |
808 | ||
809 | if (!dwc->gadget_driver) | |
ef21ede6 | 810 | goto out; |
72246da4 | 811 | |
2c4cbe6e FB |
812 | trace_dwc3_ctrl_req(ctrl); |
813 | ||
72246da4 | 814 | len = le16_to_cpu(ctrl->wLength); |
1ddcb218 | 815 | if (!len) { |
d95b09b9 FB |
816 | dwc->three_stage_setup = false; |
817 | dwc->ep0_expect_in = false; | |
1ddcb218 FB |
818 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
819 | } else { | |
d95b09b9 FB |
820 | dwc->three_stage_setup = true; |
821 | dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); | |
1ddcb218 FB |
822 | dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; |
823 | } | |
72246da4 FB |
824 | |
825 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) | |
826 | ret = dwc3_ep0_std_request(dwc, ctrl); | |
827 | else | |
828 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
829 | ||
5bdb1dcc SAS |
830 | if (ret == USB_GADGET_DELAYED_STATUS) |
831 | dwc->delayed_status = true; | |
832 | ||
ef21ede6 FB |
833 | out: |
834 | if (ret < 0) | |
835 | dwc3_ep0_stall_and_restart(dwc); | |
72246da4 FB |
836 | } |
837 | ||
838 | static void dwc3_ep0_complete_data(struct dwc3 *dwc, | |
839 | const struct dwc3_event_depevt *event) | |
840 | { | |
841 | struct dwc3_request *r = NULL; | |
842 | struct usb_request *ur; | |
f6bafc6a | 843 | struct dwc3_trb *trb; |
c2da2ff0 | 844 | struct dwc3_ep *ep0; |
8a344220 KVA |
845 | unsigned maxp; |
846 | unsigned remaining_ur_length; | |
847 | void *buf; | |
848 | u32 transferred = 0; | |
fca8892a | 849 | u32 status; |
f6bafc6a | 850 | u32 length; |
72246da4 FB |
851 | u8 epnum; |
852 | ||
853 | epnum = event->endpoint_number; | |
c2da2ff0 | 854 | ep0 = dwc->eps[0]; |
72246da4 | 855 | |
1ddcb218 | 856 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
f6bafc6a | 857 | trb = dwc->ep0_trb; |
ccb072de FB |
858 | trace_dwc3_complete_trb(ep0, trb); |
859 | ||
aa3342c8 | 860 | r = next_request(&ep0->pending_list); |
520fe763 FB |
861 | if (!r) |
862 | return; | |
863 | ||
fca8892a FB |
864 | status = DWC3_TRB_SIZE_TRBSTS(trb->size); |
865 | if (status == DWC3_TRBSTS_SETUP_PENDING) { | |
b5d335e5 | 866 | dwc->setup_packet_pending = true; |
fca8892a FB |
867 | if (r) |
868 | dwc3_gadget_giveback(ep0, r, -ECONNRESET); | |
869 | ||
870 | return; | |
871 | } | |
872 | ||
6856d30c | 873 | ur = &r->request; |
8a344220 KVA |
874 | buf = ur->buf; |
875 | remaining_ur_length = ur->length; | |
6856d30c | 876 | |
f6bafc6a | 877 | length = trb->size & DWC3_TRB_SIZE_MASK; |
8a344220 | 878 | maxp = ep0->endpoint.maxpacket; |
4199c5f8 FB |
879 | transferred = ur->length - length; |
880 | ur->actual += transferred; | |
8a344220 | 881 | |
d6e5a549 FB |
882 | if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) && |
883 | ur->length && ur->zero) || dwc->ep0_bounced) { | |
4199c5f8 FB |
884 | trb++; |
885 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; | |
d6e5a549 | 886 | trace_dwc3_complete_trb(ep0, trb); |
4199c5f8 FB |
887 | ep0->trb_enqueue = 0; |
888 | dwc->ep0_bounced = false; | |
a6829706 | 889 | } |
72246da4 | 890 | |
d6e5a549 | 891 | if ((epnum & 1) && ur->actual < ur->length) |
72246da4 | 892 | dwc3_ep0_stall_and_restart(dwc); |
d6e5a549 | 893 | else |
36f84ffb | 894 | dwc3_gadget_giveback(ep0, r, 0); |
72246da4 FB |
895 | } |
896 | ||
85a78101 | 897 | static void dwc3_ep0_complete_status(struct dwc3 *dwc, |
72246da4 FB |
898 | const struct dwc3_event_depevt *event) |
899 | { | |
900 | struct dwc3_request *r; | |
901 | struct dwc3_ep *dep; | |
fca8892a FB |
902 | struct dwc3_trb *trb; |
903 | u32 status; | |
72246da4 | 904 | |
c7fcdeb2 | 905 | dep = dwc->eps[0]; |
fca8892a | 906 | trb = dwc->ep0_trb; |
72246da4 | 907 | |
ccb072de FB |
908 | trace_dwc3_complete_trb(dep, trb); |
909 | ||
aa3342c8 FB |
910 | if (!list_empty(&dep->pending_list)) { |
911 | r = next_request(&dep->pending_list); | |
72246da4 FB |
912 | |
913 | dwc3_gadget_giveback(dep, r, 0); | |
914 | } | |
915 | ||
3b637367 GC |
916 | if (dwc->test_mode) { |
917 | int ret; | |
918 | ||
919 | ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); | |
920 | if (ret < 0) { | |
5eb30ced | 921 | dev_err(dwc->dev, "invalid test #%d\n", |
3b637367 GC |
922 | dwc->test_mode_nr); |
923 | dwc3_ep0_stall_and_restart(dwc); | |
5c81abab | 924 | return; |
3b637367 GC |
925 | } |
926 | } | |
927 | ||
fca8892a | 928 | status = DWC3_TRB_SIZE_TRBSTS(trb->size); |
5eb30ced | 929 | if (status == DWC3_TRBSTS_SETUP_PENDING) |
b5d335e5 | 930 | dwc->setup_packet_pending = true; |
fca8892a | 931 | |
c7fcdeb2 | 932 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
933 | dwc3_ep0_out_start(dwc); |
934 | } | |
935 | ||
936 | static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, | |
937 | const struct dwc3_event_depevt *event) | |
938 | { | |
c7fcdeb2 FB |
939 | struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; |
940 | ||
941 | dep->flags &= ~DWC3_EP_BUSY; | |
b4996a86 | 942 | dep->resource_index = 0; |
df62df56 | 943 | dwc->setup_packet_pending = false; |
c7fcdeb2 | 944 | |
72246da4 | 945 | switch (dwc->ep0state) { |
c7fcdeb2 | 946 | case EP0_SETUP_PHASE: |
72246da4 FB |
947 | dwc3_ep0_inspect_setup(dwc, event); |
948 | break; | |
949 | ||
c7fcdeb2 | 950 | case EP0_DATA_PHASE: |
72246da4 FB |
951 | dwc3_ep0_complete_data(dwc, event); |
952 | break; | |
953 | ||
c7fcdeb2 | 954 | case EP0_STATUS_PHASE: |
85a78101 | 955 | dwc3_ep0_complete_status(dwc, event); |
72246da4 | 956 | break; |
c7fcdeb2 FB |
957 | default: |
958 | WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); | |
959 | } | |
960 | } | |
72246da4 | 961 | |
a0807881 FB |
962 | static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, |
963 | struct dwc3_ep *dep, struct dwc3_request *req) | |
c7fcdeb2 | 964 | { |
c7fcdeb2 FB |
965 | int ret; |
966 | ||
a0807881 | 967 | req->direction = !!dep->number; |
c7fcdeb2 | 968 | |
c7fcdeb2 | 969 | if (req->request.length == 0) { |
d686a5ff | 970 | dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, |
368ca113 | 971 | DWC3_TRBCTL_CONTROL_DATA, false); |
d686a5ff | 972 | ret = dwc3_ep0_start_trans(dep); |
c74c6d4a | 973 | } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) |
a0807881 | 974 | && (dep->number == 0)) { |
c390b036 | 975 | u32 maxpacket; |
4199c5f8 | 976 | u32 rem; |
a0807881 | 977 | |
d64ff406 AB |
978 | ret = usb_gadget_map_request_by_dev(dwc->sysdev, |
979 | &req->request, dep->number); | |
5eb30ced | 980 | if (ret) |
0fc9a1be | 981 | return; |
c7fcdeb2 | 982 | |
c390b036 | 983 | maxpacket = dep->endpoint.maxpacket; |
4199c5f8 | 984 | rem = req->request.length % maxpacket; |
c7fcdeb2 FB |
985 | dwc->ep0_bounced = true; |
986 | ||
4199c5f8 FB |
987 | /* prepare normal TRB */ |
988 | dwc3_ep0_prepare_one_trb(dep, req->request.dma, | |
989 | req->request.length, | |
990 | DWC3_TRBCTL_CONTROL_DATA, | |
991 | true); | |
992 | ||
55168470 FB |
993 | req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1]; |
994 | ||
4199c5f8 FB |
995 | /* Now prepare one extra TRB to align transfer size */ |
996 | dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, | |
997 | maxpacket - rem, | |
998 | DWC3_TRBCTL_CONTROL_DATA, | |
d686a5ff FB |
999 | false); |
1000 | ret = dwc3_ep0_start_trans(dep); | |
d6e5a549 FB |
1001 | } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) && |
1002 | req->request.length && req->request.zero) { | |
1003 | u32 maxpacket; | |
1004 | u32 rem; | |
1005 | ||
1006 | ret = usb_gadget_map_request_by_dev(dwc->sysdev, | |
1007 | &req->request, dep->number); | |
1008 | if (ret) | |
1009 | return; | |
1010 | ||
1011 | maxpacket = dep->endpoint.maxpacket; | |
1012 | rem = req->request.length % maxpacket; | |
1013 | ||
1014 | /* prepare normal TRB */ | |
1015 | dwc3_ep0_prepare_one_trb(dep, req->request.dma, | |
1016 | req->request.length, | |
1017 | DWC3_TRBCTL_CONTROL_DATA, | |
1018 | true); | |
1019 | ||
55168470 FB |
1020 | req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1]; |
1021 | ||
d6e5a549 FB |
1022 | /* Now prepare one extra TRB to align transfer size */ |
1023 | dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, | |
1024 | 0, DWC3_TRBCTL_CONTROL_DATA, | |
1025 | false); | |
1026 | ret = dwc3_ep0_start_trans(dep); | |
c7fcdeb2 | 1027 | } else { |
d64ff406 AB |
1028 | ret = usb_gadget_map_request_by_dev(dwc->sysdev, |
1029 | &req->request, dep->number); | |
5eb30ced | 1030 | if (ret) |
0fc9a1be | 1031 | return; |
c7fcdeb2 | 1032 | |
d686a5ff | 1033 | dwc3_ep0_prepare_one_trb(dep, req->request.dma, |
368ca113 KVA |
1034 | req->request.length, DWC3_TRBCTL_CONTROL_DATA, |
1035 | false); | |
55168470 FB |
1036 | |
1037 | req->trb = &dwc->ep0_trb[dep->trb_enqueue]; | |
1038 | ||
d686a5ff | 1039 | ret = dwc3_ep0_start_trans(dep); |
c7fcdeb2 FB |
1040 | } |
1041 | ||
1042 | WARN_ON(ret < 0); | |
72246da4 FB |
1043 | } |
1044 | ||
f0f2b2a2 | 1045 | static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) |
72246da4 | 1046 | { |
f0f2b2a2 | 1047 | struct dwc3 *dwc = dep->dwc; |
c7fcdeb2 | 1048 | u32 type; |
72246da4 | 1049 | |
c7fcdeb2 FB |
1050 | type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 |
1051 | : DWC3_TRBCTL_CONTROL_STATUS2; | |
1052 | ||
d686a5ff FB |
1053 | dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false); |
1054 | return dwc3_ep0_start_trans(dep); | |
f0f2b2a2 | 1055 | } |
c7fcdeb2 | 1056 | |
788a23f4 | 1057 | static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) |
f0f2b2a2 | 1058 | { |
f0f2b2a2 | 1059 | WARN_ON(dwc3_ep0_start_control_status(dep)); |
c7fcdeb2 FB |
1060 | } |
1061 | ||
788a23f4 FB |
1062 | static void dwc3_ep0_do_control_status(struct dwc3 *dwc, |
1063 | const struct dwc3_event_depevt *event) | |
1064 | { | |
1065 | struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; | |
1066 | ||
1067 | __dwc3_ep0_do_control_status(dwc, dep); | |
1068 | } | |
1069 | ||
2e3db064 FB |
1070 | static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) |
1071 | { | |
1072 | struct dwc3_gadget_ep_cmd_params params; | |
1073 | u32 cmd; | |
1074 | int ret; | |
1075 | ||
1076 | if (!dep->resource_index) | |
1077 | return; | |
1078 | ||
1079 | cmd = DWC3_DEPCMD_ENDTRANSFER; | |
1080 | cmd |= DWC3_DEPCMD_CMDIOC; | |
1081 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); | |
1082 | memset(¶ms, 0, sizeof(params)); | |
2cd4718d | 1083 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
2e3db064 FB |
1084 | WARN_ON_ONCE(ret); |
1085 | dep->resource_index = 0; | |
1086 | } | |
1087 | ||
c7fcdeb2 FB |
1088 | static void dwc3_ep0_xfernotready(struct dwc3 *dwc, |
1089 | const struct dwc3_event_depevt *event) | |
1090 | { | |
1091 | switch (event->status) { | |
c7fcdeb2 | 1092 | case DEPEVT_STATUS_CONTROL_DATA: |
55f3fba6 | 1093 | /* |
2e3db064 FB |
1094 | * We already have a DATA transfer in the controller's cache, |
1095 | * if we receive a XferNotReady(DATA) we will ignore it, unless | |
1096 | * it's for the wrong direction. | |
55f3fba6 | 1097 | * |
2e3db064 FB |
1098 | * In that case, we must issue END_TRANSFER command to the Data |
1099 | * Phase we already have started and issue SetStall on the | |
1100 | * control endpoint. | |
55f3fba6 FB |
1101 | */ |
1102 | if (dwc->ep0_expect_in != event->endpoint_number) { | |
2e3db064 FB |
1103 | struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; |
1104 | ||
5eb30ced | 1105 | dev_err(dwc->dev, "unexpected direction for Data Phase\n"); |
2e3db064 | 1106 | dwc3_ep0_end_control_data(dwc, dep); |
55f3fba6 FB |
1107 | dwc3_ep0_stall_and_restart(dwc); |
1108 | return; | |
1109 | } | |
1110 | ||
c7fcdeb2 | 1111 | break; |
1ddcb218 | 1112 | |
c7fcdeb2 | 1113 | case DEPEVT_STATUS_CONTROL_STATUS: |
77fa6df8 FB |
1114 | if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) |
1115 | return; | |
1116 | ||
f0f2b2a2 SAS |
1117 | dwc->ep0state = EP0_STATUS_PHASE; |
1118 | ||
5bdb1dcc | 1119 | if (dwc->delayed_status) { |
53896798 BW |
1120 | struct dwc3_ep *dep = dwc->eps[0]; |
1121 | ||
5bdb1dcc | 1122 | WARN_ON_ONCE(event->endpoint_number != 1); |
53896798 BW |
1123 | /* |
1124 | * We should handle the delay STATUS phase here if the | |
1125 | * request for handling delay STATUS has been queued | |
1126 | * into the list. | |
1127 | */ | |
1128 | if (!list_empty(&dep->pending_list)) { | |
1129 | dwc->delayed_status = false; | |
1130 | usb_gadget_set_state(&dwc->gadget, | |
1131 | USB_STATE_CONFIGURED); | |
1132 | dwc3_ep0_do_control_status(dwc, event); | |
1133 | } | |
1134 | ||
5bdb1dcc SAS |
1135 | return; |
1136 | } | |
1137 | ||
788a23f4 | 1138 | dwc3_ep0_do_control_status(dwc, event); |
72246da4 FB |
1139 | } |
1140 | } | |
1141 | ||
1142 | void dwc3_ep0_interrupt(struct dwc3 *dwc, | |
8becf270 | 1143 | const struct dwc3_event_depevt *event) |
72246da4 | 1144 | { |
72246da4 FB |
1145 | switch (event->endpoint_event) { |
1146 | case DWC3_DEPEVT_XFERCOMPLETE: | |
1147 | dwc3_ep0_xfer_complete(dwc, event); | |
1148 | break; | |
1149 | ||
1150 | case DWC3_DEPEVT_XFERNOTREADY: | |
1151 | dwc3_ep0_xfernotready(dwc, event); | |
1152 | break; | |
1153 | ||
1154 | case DWC3_DEPEVT_XFERINPROGRESS: | |
1155 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
1156 | case DWC3_DEPEVT_STREAMEVT: | |
1157 | case DWC3_DEPEVT_EPCMDCMPLT: | |
1158 | break; | |
1159 | } | |
1160 | } |