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72246da4 FB |
1 | /** |
2 | * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
9 | * Redistribution and use in source and binary forms, with or without | |
10 | * modification, are permitted provided that the following conditions | |
11 | * are met: | |
12 | * 1. Redistributions of source code must retain the above copyright | |
13 | * notice, this list of conditions, and the following disclaimer, | |
14 | * without modification. | |
15 | * 2. Redistributions in binary form must reproduce the above copyright | |
16 | * notice, this list of conditions and the following disclaimer in the | |
17 | * documentation and/or other materials provided with the distribution. | |
18 | * 3. The names of the above-listed copyright holders may not be used | |
19 | * to endorse or promote products derived from this software without | |
20 | * specific prior written permission. | |
21 | * | |
22 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
23 | * GNU General Public License ("GPL") version 2, as published by the Free | |
24 | * Software Foundation. | |
25 | * | |
26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
27 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
28 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
29 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
30 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
31 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
32 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
33 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
34 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
35 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
36 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
37 | */ | |
38 | ||
39 | #include <linux/kernel.h> | |
40 | #include <linux/slab.h> | |
41 | #include <linux/spinlock.h> | |
42 | #include <linux/platform_device.h> | |
43 | #include <linux/pm_runtime.h> | |
44 | #include <linux/interrupt.h> | |
45 | #include <linux/io.h> | |
46 | #include <linux/list.h> | |
47 | #include <linux/dma-mapping.h> | |
48 | ||
49 | #include <linux/usb/ch9.h> | |
50 | #include <linux/usb/gadget.h> | |
5bdb1dcc | 51 | #include <linux/usb/composite.h> |
72246da4 FB |
52 | |
53 | #include "core.h" | |
54 | #include "gadget.h" | |
55 | #include "io.h" | |
56 | ||
5bdb1dcc | 57 | static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum); |
a0807881 FB |
58 | static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, |
59 | struct dwc3_ep *dep, struct dwc3_request *req); | |
5bdb1dcc | 60 | |
72246da4 FB |
61 | static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) |
62 | { | |
63 | switch (state) { | |
64 | case EP0_UNCONNECTED: | |
65 | return "Unconnected"; | |
c7fcdeb2 FB |
66 | case EP0_SETUP_PHASE: |
67 | return "Setup Phase"; | |
68 | case EP0_DATA_PHASE: | |
69 | return "Data Phase"; | |
70 | case EP0_STATUS_PHASE: | |
71 | return "Status Phase"; | |
72246da4 FB |
72 | default: |
73 | return "UNKNOWN"; | |
74 | } | |
75 | } | |
76 | ||
77 | static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, | |
c7fcdeb2 | 78 | u32 len, u32 type) |
72246da4 FB |
79 | { |
80 | struct dwc3_gadget_ep_cmd_params params; | |
f6bafc6a | 81 | struct dwc3_trb *trb; |
72246da4 FB |
82 | struct dwc3_ep *dep; |
83 | ||
84 | int ret; | |
85 | ||
86 | dep = dwc->eps[epnum]; | |
c7fcdeb2 FB |
87 | if (dep->flags & DWC3_EP_BUSY) { |
88 | dev_vdbg(dwc->dev, "%s: still busy\n", dep->name); | |
89 | return 0; | |
90 | } | |
72246da4 | 91 | |
f6bafc6a | 92 | trb = dwc->ep0_trb; |
72246da4 | 93 | |
f6bafc6a FB |
94 | trb->bpl = lower_32_bits(buf_dma); |
95 | trb->bph = upper_32_bits(buf_dma); | |
96 | trb->size = len; | |
97 | trb->ctrl = type; | |
72246da4 | 98 | |
f6bafc6a FB |
99 | trb->ctrl |= (DWC3_TRB_CTRL_HWO |
100 | | DWC3_TRB_CTRL_LST | |
101 | | DWC3_TRB_CTRL_IOC | |
102 | | DWC3_TRB_CTRL_ISP_IMI); | |
72246da4 FB |
103 | |
104 | memset(¶ms, 0, sizeof(params)); | |
dc1c70a7 FB |
105 | params.param0 = upper_32_bits(dwc->ep0_trb_addr); |
106 | params.param1 = lower_32_bits(dwc->ep0_trb_addr); | |
72246da4 FB |
107 | |
108 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
109 | DWC3_DEPCMD_STARTTRANSFER, ¶ms); | |
110 | if (ret < 0) { | |
111 | dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); | |
112 | return ret; | |
113 | } | |
114 | ||
c7fcdeb2 | 115 | dep->flags |= DWC3_EP_BUSY; |
72246da4 FB |
116 | dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc, |
117 | dep->number); | |
118 | ||
1ddcb218 FB |
119 | dwc->ep0_next_event = DWC3_EP0_COMPLETE; |
120 | ||
72246da4 FB |
121 | return 0; |
122 | } | |
123 | ||
124 | static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, | |
125 | struct dwc3_request *req) | |
126 | { | |
5bdb1dcc | 127 | struct dwc3 *dwc = dep->dwc; |
c7fcdeb2 | 128 | int ret = 0; |
72246da4 FB |
129 | |
130 | req->request.actual = 0; | |
131 | req->request.status = -EINPROGRESS; | |
72246da4 FB |
132 | req->epnum = dep->number; |
133 | ||
134 | list_add_tail(&req->list, &dep->request_list); | |
a6829706 | 135 | |
c7fcdeb2 FB |
136 | /* |
137 | * Gadget driver might not be quick enough to queue a request | |
138 | * before we get a Transfer Not Ready event on this endpoint. | |
139 | * | |
140 | * In that case, we will set DWC3_EP_PENDING_REQUEST. When that | |
141 | * flag is set, it's telling us that as soon as Gadget queues the | |
142 | * required request, we should kick the transfer here because the | |
143 | * IRQ we were waiting for is long gone. | |
144 | */ | |
145 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
c7fcdeb2 | 146 | unsigned direction; |
c7fcdeb2 FB |
147 | |
148 | direction = !!(dep->flags & DWC3_EP0_DIR_IN); | |
149 | ||
68d8a781 FB |
150 | if (dwc->ep0state != EP0_DATA_PHASE) { |
151 | dev_WARN(dwc->dev, "Unexpected pending request\n"); | |
c7fcdeb2 FB |
152 | return 0; |
153 | } | |
72246da4 | 154 | |
a0807881 FB |
155 | __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); |
156 | ||
c7fcdeb2 FB |
157 | dep->flags &= ~(DWC3_EP_PENDING_REQUEST | |
158 | DWC3_EP0_DIR_IN); | |
68d3e668 | 159 | } else if (dwc->delayed_status) { |
5bdb1dcc | 160 | dwc->delayed_status = false; |
68d3e668 FB |
161 | |
162 | if (dwc->ep0state == EP0_STATUS_PHASE) | |
163 | dwc3_ep0_do_control_status(dwc, 1); | |
164 | else | |
165 | dev_dbg(dwc->dev, "too early for delayed status\n"); | |
72246da4 FB |
166 | } |
167 | ||
168 | return ret; | |
169 | } | |
170 | ||
171 | int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, | |
172 | gfp_t gfp_flags) | |
173 | { | |
174 | struct dwc3_request *req = to_dwc3_request(request); | |
175 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
176 | struct dwc3 *dwc = dep->dwc; | |
177 | ||
178 | unsigned long flags; | |
179 | ||
180 | int ret; | |
181 | ||
72246da4 | 182 | spin_lock_irqsave(&dwc->lock, flags); |
16e78db7 | 183 | if (!dep->endpoint.desc) { |
72246da4 FB |
184 | dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", |
185 | request, dep->name); | |
186 | ret = -ESHUTDOWN; | |
187 | goto out; | |
188 | } | |
189 | ||
190 | /* we share one TRB for ep0/1 */ | |
c2da2ff0 | 191 | if (!list_empty(&dep->request_list)) { |
72246da4 FB |
192 | ret = -EBUSY; |
193 | goto out; | |
194 | } | |
195 | ||
196 | dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n", | |
197 | request, dep->name, request->length, | |
198 | dwc3_ep0_state_string(dwc->ep0state)); | |
199 | ||
200 | ret = __dwc3_gadget_ep0_queue(dep, req); | |
201 | ||
202 | out: | |
203 | spin_unlock_irqrestore(&dwc->lock, flags); | |
204 | ||
205 | return ret; | |
206 | } | |
207 | ||
208 | static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) | |
209 | { | |
d742220b FB |
210 | struct dwc3_ep *dep = dwc->eps[0]; |
211 | ||
72246da4 | 212 | /* stall is always issued on EP0 */ |
c2da2ff0 SAS |
213 | __dwc3_gadget_ep_set_halt(dep, 1); |
214 | dep->flags = DWC3_EP_ENABLED; | |
5bdb1dcc | 215 | dwc->delayed_status = false; |
d742220b FB |
216 | |
217 | if (!list_empty(&dep->request_list)) { | |
218 | struct dwc3_request *req; | |
219 | ||
220 | req = next_request(&dep->request_list); | |
221 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
222 | } | |
223 | ||
c7fcdeb2 | 224 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
225 | dwc3_ep0_out_start(dwc); |
226 | } | |
227 | ||
228 | void dwc3_ep0_out_start(struct dwc3 *dwc) | |
229 | { | |
72246da4 FB |
230 | int ret; |
231 | ||
c7fcdeb2 FB |
232 | ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, |
233 | DWC3_TRBCTL_CONTROL_SETUP); | |
72246da4 FB |
234 | WARN_ON(ret < 0); |
235 | } | |
236 | ||
72246da4 FB |
237 | static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) |
238 | { | |
239 | struct dwc3_ep *dep; | |
240 | u32 windex = le16_to_cpu(wIndex_le); | |
241 | u32 epnum; | |
242 | ||
243 | epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; | |
244 | if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) | |
245 | epnum |= 1; | |
246 | ||
247 | dep = dwc->eps[epnum]; | |
248 | if (dep->flags & DWC3_EP_ENABLED) | |
249 | return dep; | |
250 | ||
251 | return NULL; | |
252 | } | |
253 | ||
8ee6270c | 254 | static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) |
72246da4 | 255 | { |
72246da4 | 256 | } |
72246da4 FB |
257 | /* |
258 | * ch 9.4.5 | |
259 | */ | |
25b8ff68 FB |
260 | static int dwc3_ep0_handle_status(struct dwc3 *dwc, |
261 | struct usb_ctrlrequest *ctrl) | |
72246da4 FB |
262 | { |
263 | struct dwc3_ep *dep; | |
264 | u32 recip; | |
e6a3b5e2 | 265 | u32 reg; |
72246da4 FB |
266 | u16 usb_status = 0; |
267 | __le16 *response_pkt; | |
268 | ||
269 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
270 | switch (recip) { | |
271 | case USB_RECIP_DEVICE: | |
272 | /* | |
e6a3b5e2 | 273 | * LTM will be set once we know how to set this in HW. |
72246da4 FB |
274 | */ |
275 | usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED; | |
e6a3b5e2 SAS |
276 | |
277 | if (dwc->speed == DWC3_DSTS_SUPERSPEED) { | |
278 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
279 | if (reg & DWC3_DCTL_INITU1ENA) | |
280 | usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; | |
281 | if (reg & DWC3_DCTL_INITU2ENA) | |
282 | usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; | |
283 | } | |
284 | ||
72246da4 FB |
285 | break; |
286 | ||
287 | case USB_RECIP_INTERFACE: | |
288 | /* | |
289 | * Function Remote Wake Capable D0 | |
290 | * Function Remote Wakeup D1 | |
291 | */ | |
292 | break; | |
293 | ||
294 | case USB_RECIP_ENDPOINT: | |
295 | dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); | |
296 | if (!dep) | |
25b8ff68 | 297 | return -EINVAL; |
72246da4 FB |
298 | |
299 | if (dep->flags & DWC3_EP_STALL) | |
300 | usb_status = 1 << USB_ENDPOINT_HALT; | |
301 | break; | |
302 | default: | |
303 | return -EINVAL; | |
304 | }; | |
305 | ||
306 | response_pkt = (__le16 *) dwc->setup_buf; | |
307 | *response_pkt = cpu_to_le16(usb_status); | |
e2617796 FB |
308 | |
309 | dep = dwc->eps[0]; | |
310 | dwc->ep0_usb_req.dep = dep; | |
e0ce0b0a | 311 | dwc->ep0_usb_req.request.length = sizeof(*response_pkt); |
0fc9a1be | 312 | dwc->ep0_usb_req.request.buf = dwc->setup_buf; |
e0ce0b0a | 313 | dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; |
e2617796 FB |
314 | |
315 | return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); | |
72246da4 FB |
316 | } |
317 | ||
318 | static int dwc3_ep0_handle_feature(struct dwc3 *dwc, | |
319 | struct usb_ctrlrequest *ctrl, int set) | |
320 | { | |
321 | struct dwc3_ep *dep; | |
322 | u32 recip; | |
323 | u32 wValue; | |
324 | u32 wIndex; | |
e6a3b5e2 | 325 | u32 reg; |
72246da4 | 326 | int ret; |
72246da4 FB |
327 | |
328 | wValue = le16_to_cpu(ctrl->wValue); | |
329 | wIndex = le16_to_cpu(ctrl->wIndex); | |
330 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
331 | switch (recip) { | |
332 | case USB_RECIP_DEVICE: | |
333 | ||
e6a3b5e2 SAS |
334 | switch (wValue) { |
335 | case USB_DEVICE_REMOTE_WAKEUP: | |
336 | break; | |
72246da4 FB |
337 | /* |
338 | * 9.4.1 says only only for SS, in AddressState only for | |
339 | * default control pipe | |
340 | */ | |
72246da4 | 341 | case USB_DEVICE_U1_ENABLE: |
72246da4 FB |
342 | if (dwc->dev_state != DWC3_CONFIGURED_STATE) |
343 | return -EINVAL; | |
344 | if (dwc->speed != DWC3_DSTS_SUPERSPEED) | |
345 | return -EINVAL; | |
72246da4 | 346 | |
e6a3b5e2 SAS |
347 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
348 | if (set) | |
349 | reg |= DWC3_DCTL_INITU1ENA; | |
350 | else | |
351 | reg &= ~DWC3_DCTL_INITU1ENA; | |
352 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 353 | break; |
e6a3b5e2 | 354 | |
72246da4 | 355 | case USB_DEVICE_U2_ENABLE: |
e6a3b5e2 SAS |
356 | if (dwc->dev_state != DWC3_CONFIGURED_STATE) |
357 | return -EINVAL; | |
358 | if (dwc->speed != DWC3_DSTS_SUPERSPEED) | |
359 | return -EINVAL; | |
360 | ||
361 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
362 | if (set) | |
363 | reg |= DWC3_DCTL_INITU2ENA; | |
364 | else | |
365 | reg &= ~DWC3_DCTL_INITU2ENA; | |
366 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 367 | break; |
e6a3b5e2 | 368 | |
72246da4 | 369 | case USB_DEVICE_LTM_ENABLE: |
e6a3b5e2 | 370 | return -EINVAL; |
72246da4 FB |
371 | break; |
372 | ||
373 | case USB_DEVICE_TEST_MODE: | |
374 | if ((wIndex & 0xff) != 0) | |
375 | return -EINVAL; | |
376 | if (!set) | |
377 | return -EINVAL; | |
378 | ||
3b637367 GC |
379 | dwc->test_mode_nr = wIndex >> 8; |
380 | dwc->test_mode = true; | |
ecb07797 GC |
381 | break; |
382 | default: | |
383 | return -EINVAL; | |
72246da4 FB |
384 | } |
385 | break; | |
386 | ||
387 | case USB_RECIP_INTERFACE: | |
388 | switch (wValue) { | |
389 | case USB_INTRF_FUNC_SUSPEND: | |
390 | if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) | |
391 | /* XXX enable Low power suspend */ | |
392 | ; | |
393 | if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) | |
394 | /* XXX enable remote wakeup */ | |
395 | ; | |
396 | break; | |
397 | default: | |
398 | return -EINVAL; | |
399 | } | |
400 | break; | |
401 | ||
402 | case USB_RECIP_ENDPOINT: | |
403 | switch (wValue) { | |
404 | case USB_ENDPOINT_HALT: | |
1d046793 | 405 | dep = dwc3_wIndex_to_dep(dwc, wIndex); |
72246da4 FB |
406 | if (!dep) |
407 | return -EINVAL; | |
408 | ret = __dwc3_gadget_ep_set_halt(dep, set); | |
409 | if (ret) | |
410 | return -EINVAL; | |
411 | break; | |
412 | default: | |
413 | return -EINVAL; | |
414 | } | |
415 | break; | |
416 | ||
417 | default: | |
418 | return -EINVAL; | |
419 | }; | |
420 | ||
72246da4 FB |
421 | return 0; |
422 | } | |
423 | ||
424 | static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
425 | { | |
72246da4 FB |
426 | u32 addr; |
427 | u32 reg; | |
428 | ||
429 | addr = le16_to_cpu(ctrl->wValue); | |
f96a6ec1 FB |
430 | if (addr > 127) { |
431 | dev_dbg(dwc->dev, "invalid device address %d\n", addr); | |
72246da4 | 432 | return -EINVAL; |
f96a6ec1 FB |
433 | } |
434 | ||
435 | if (dwc->dev_state == DWC3_CONFIGURED_STATE) { | |
436 | dev_dbg(dwc->dev, "trying to set address when configured\n"); | |
437 | return -EINVAL; | |
438 | } | |
72246da4 | 439 | |
2646021e FB |
440 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
441 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
442 | reg |= DWC3_DCFG_DEVADDR(addr); | |
443 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 | 444 | |
2646021e FB |
445 | if (addr) |
446 | dwc->dev_state = DWC3_ADDRESS_STATE; | |
447 | else | |
448 | dwc->dev_state = DWC3_DEFAULT_STATE; | |
c7fcdeb2 | 449 | |
2646021e | 450 | return 0; |
72246da4 FB |
451 | } |
452 | ||
453 | static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
454 | { | |
455 | int ret; | |
456 | ||
457 | spin_unlock(&dwc->lock); | |
458 | ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); | |
459 | spin_lock(&dwc->lock); | |
460 | return ret; | |
461 | } | |
462 | ||
463 | static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
464 | { | |
465 | u32 cfg; | |
466 | int ret; | |
467 | ||
b23c8439 | 468 | dwc->start_config_issued = false; |
72246da4 FB |
469 | cfg = le16_to_cpu(ctrl->wValue); |
470 | ||
471 | switch (dwc->dev_state) { | |
472 | case DWC3_DEFAULT_STATE: | |
473 | return -EINVAL; | |
474 | break; | |
475 | ||
476 | case DWC3_ADDRESS_STATE: | |
477 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
478 | /* if the cfg matches and the cfg is non zero */ | |
457e84b6 | 479 | if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { |
72246da4 | 480 | dwc->dev_state = DWC3_CONFIGURED_STATE; |
457e84b6 FB |
481 | dwc->resize_fifos = true; |
482 | dev_dbg(dwc->dev, "resize fifos flag SET\n"); | |
483 | } | |
72246da4 FB |
484 | break; |
485 | ||
486 | case DWC3_CONFIGURED_STATE: | |
487 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
488 | if (!cfg) | |
489 | dwc->dev_state = DWC3_ADDRESS_STATE; | |
490 | break; | |
5bdb1dcc SAS |
491 | default: |
492 | ret = -EINVAL; | |
72246da4 | 493 | } |
5bdb1dcc | 494 | return ret; |
72246da4 FB |
495 | } |
496 | ||
865e09e7 FB |
497 | static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) |
498 | { | |
499 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
500 | struct dwc3 *dwc = dep->dwc; | |
501 | ||
502 | u32 param = 0; | |
503 | u32 reg; | |
504 | ||
505 | struct timing { | |
506 | u8 u1sel; | |
507 | u8 u1pel; | |
508 | u16 u2sel; | |
509 | u16 u2pel; | |
510 | } __packed timing; | |
511 | ||
512 | int ret; | |
513 | ||
514 | memcpy(&timing, req->buf, sizeof(timing)); | |
515 | ||
516 | dwc->u1sel = timing.u1sel; | |
517 | dwc->u1pel = timing.u1pel; | |
518 | dwc->u2sel = timing.u2sel; | |
519 | dwc->u2pel = timing.u2pel; | |
520 | ||
521 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
522 | if (reg & DWC3_DCTL_INITU2ENA) | |
523 | param = dwc->u2pel; | |
524 | if (reg & DWC3_DCTL_INITU1ENA) | |
525 | param = dwc->u1pel; | |
526 | ||
527 | /* | |
528 | * According to Synopsys Databook, if parameter is | |
529 | * greater than 125, a value of zero should be | |
530 | * programmed in the register. | |
531 | */ | |
532 | if (param > 125) | |
533 | param = 0; | |
534 | ||
535 | /* now that we have the time, issue DGCMD Set Sel */ | |
536 | ret = dwc3_send_gadget_generic_command(dwc, | |
537 | DWC3_DGCMD_SET_PERIODIC_PAR, param); | |
538 | WARN_ON(ret < 0); | |
539 | } | |
540 | ||
541 | static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
542 | { | |
543 | struct dwc3_ep *dep; | |
544 | u16 wLength; | |
545 | u16 wValue; | |
546 | ||
547 | if (dwc->dev_state == DWC3_DEFAULT_STATE) | |
548 | return -EINVAL; | |
549 | ||
550 | wValue = le16_to_cpu(ctrl->wValue); | |
551 | wLength = le16_to_cpu(ctrl->wLength); | |
552 | ||
553 | if (wLength != 6) { | |
554 | dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", | |
555 | wLength); | |
556 | return -EINVAL; | |
557 | } | |
558 | ||
559 | /* | |
560 | * To handle Set SEL we need to receive 6 bytes from Host. So let's | |
561 | * queue a usb_request for 6 bytes. | |
562 | * | |
563 | * Remember, though, this controller can't handle non-wMaxPacketSize | |
564 | * aligned transfers on the OUT direction, so we queue a request for | |
565 | * wMaxPacketSize instead. | |
566 | */ | |
567 | dep = dwc->eps[0]; | |
568 | dwc->ep0_usb_req.dep = dep; | |
569 | dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; | |
570 | dwc->ep0_usb_req.request.buf = dwc->setup_buf; | |
571 | dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; | |
572 | ||
573 | return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); | |
574 | } | |
575 | ||
c12a0d86 FB |
576 | static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) |
577 | { | |
578 | u16 wLength; | |
579 | u16 wValue; | |
580 | u16 wIndex; | |
581 | ||
582 | wValue = le16_to_cpu(ctrl->wValue); | |
583 | wLength = le16_to_cpu(ctrl->wLength); | |
584 | wIndex = le16_to_cpu(ctrl->wIndex); | |
585 | ||
586 | if (wIndex || wLength) | |
587 | return -EINVAL; | |
588 | ||
589 | /* | |
590 | * REVISIT It's unclear from Databook what to do with this | |
591 | * value. For now, just cache it. | |
592 | */ | |
593 | dwc->isoch_delay = wValue; | |
594 | ||
595 | return 0; | |
596 | } | |
597 | ||
72246da4 FB |
598 | static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) |
599 | { | |
600 | int ret; | |
601 | ||
602 | switch (ctrl->bRequest) { | |
603 | case USB_REQ_GET_STATUS: | |
604 | dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n"); | |
605 | ret = dwc3_ep0_handle_status(dwc, ctrl); | |
606 | break; | |
607 | case USB_REQ_CLEAR_FEATURE: | |
608 | dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n"); | |
609 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); | |
610 | break; | |
611 | case USB_REQ_SET_FEATURE: | |
612 | dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n"); | |
613 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); | |
614 | break; | |
615 | case USB_REQ_SET_ADDRESS: | |
616 | dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n"); | |
617 | ret = dwc3_ep0_set_address(dwc, ctrl); | |
618 | break; | |
619 | case USB_REQ_SET_CONFIGURATION: | |
620 | dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n"); | |
621 | ret = dwc3_ep0_set_config(dwc, ctrl); | |
622 | break; | |
865e09e7 FB |
623 | case USB_REQ_SET_SEL: |
624 | dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n"); | |
625 | ret = dwc3_ep0_set_sel(dwc, ctrl); | |
626 | break; | |
c12a0d86 FB |
627 | case USB_REQ_SET_ISOCH_DELAY: |
628 | dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n"); | |
629 | ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); | |
630 | break; | |
72246da4 FB |
631 | default: |
632 | dev_vdbg(dwc->dev, "Forwarding to gadget driver\n"); | |
633 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
634 | break; | |
635 | }; | |
636 | ||
637 | return ret; | |
638 | } | |
639 | ||
640 | static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, | |
641 | const struct dwc3_event_depevt *event) | |
642 | { | |
643 | struct usb_ctrlrequest *ctrl = dwc->ctrl_req; | |
644 | int ret; | |
645 | u32 len; | |
646 | ||
647 | if (!dwc->gadget_driver) | |
648 | goto err; | |
649 | ||
650 | len = le16_to_cpu(ctrl->wLength); | |
1ddcb218 | 651 | if (!len) { |
d95b09b9 FB |
652 | dwc->three_stage_setup = false; |
653 | dwc->ep0_expect_in = false; | |
1ddcb218 FB |
654 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
655 | } else { | |
d95b09b9 FB |
656 | dwc->three_stage_setup = true; |
657 | dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); | |
1ddcb218 FB |
658 | dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; |
659 | } | |
72246da4 FB |
660 | |
661 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) | |
662 | ret = dwc3_ep0_std_request(dwc, ctrl); | |
663 | else | |
664 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
665 | ||
5bdb1dcc SAS |
666 | if (ret == USB_GADGET_DELAYED_STATUS) |
667 | dwc->delayed_status = true; | |
668 | ||
72246da4 FB |
669 | if (ret >= 0) |
670 | return; | |
671 | ||
672 | err: | |
673 | dwc3_ep0_stall_and_restart(dwc); | |
674 | } | |
675 | ||
676 | static void dwc3_ep0_complete_data(struct dwc3 *dwc, | |
677 | const struct dwc3_event_depevt *event) | |
678 | { | |
679 | struct dwc3_request *r = NULL; | |
680 | struct usb_request *ur; | |
f6bafc6a | 681 | struct dwc3_trb *trb; |
c2da2ff0 | 682 | struct dwc3_ep *ep0; |
c611ccb4 | 683 | u32 transferred; |
f6bafc6a | 684 | u32 length; |
72246da4 FB |
685 | u8 epnum; |
686 | ||
687 | epnum = event->endpoint_number; | |
c2da2ff0 | 688 | ep0 = dwc->eps[0]; |
72246da4 | 689 | |
1ddcb218 FB |
690 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
691 | ||
c2da2ff0 | 692 | r = next_request(&ep0->request_list); |
8ee6270c | 693 | ur = &r->request; |
72246da4 | 694 | |
f6bafc6a FB |
695 | trb = dwc->ep0_trb; |
696 | length = trb->size & DWC3_TRB_SIZE_MASK; | |
72246da4 | 697 | |
a6829706 | 698 | if (dwc->ep0_bounced) { |
566ccdda MS |
699 | unsigned transfer_size = ur->length; |
700 | unsigned maxp = ep0->endpoint.maxpacket; | |
701 | ||
702 | transfer_size += (maxp - (transfer_size % maxp)); | |
c7fcdeb2 | 703 | transferred = min_t(u32, ur->length, |
566ccdda | 704 | transfer_size - length); |
a6829706 FB |
705 | memcpy(ur->buf, dwc->ep0_bounce, transferred); |
706 | dwc->ep0_bounced = false; | |
707 | } else { | |
f6bafc6a | 708 | transferred = ur->length - length; |
a6829706 | 709 | } |
72246da4 | 710 | |
cd423dd3 FB |
711 | ur->actual += transferred; |
712 | ||
72246da4 FB |
713 | if ((epnum & 1) && ur->actual < ur->length) { |
714 | /* for some reason we did not get everything out */ | |
715 | ||
716 | dwc3_ep0_stall_and_restart(dwc); | |
72246da4 FB |
717 | } else { |
718 | /* | |
719 | * handle the case where we have to send a zero packet. This | |
720 | * seems to be case when req.length > maxpacket. Could it be? | |
721 | */ | |
72246da4 | 722 | if (r) |
c2da2ff0 | 723 | dwc3_gadget_giveback(ep0, r, 0); |
72246da4 FB |
724 | } |
725 | } | |
726 | ||
727 | static void dwc3_ep0_complete_req(struct dwc3 *dwc, | |
728 | const struct dwc3_event_depevt *event) | |
729 | { | |
730 | struct dwc3_request *r; | |
731 | struct dwc3_ep *dep; | |
72246da4 | 732 | |
c7fcdeb2 | 733 | dep = dwc->eps[0]; |
72246da4 FB |
734 | |
735 | if (!list_empty(&dep->request_list)) { | |
736 | r = next_request(&dep->request_list); | |
737 | ||
738 | dwc3_gadget_giveback(dep, r, 0); | |
739 | } | |
740 | ||
3b637367 GC |
741 | if (dwc->test_mode) { |
742 | int ret; | |
743 | ||
744 | ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); | |
745 | if (ret < 0) { | |
746 | dev_dbg(dwc->dev, "Invalid Test #%d\n", | |
747 | dwc->test_mode_nr); | |
748 | dwc3_ep0_stall_and_restart(dwc); | |
749 | } | |
750 | } | |
751 | ||
c7fcdeb2 | 752 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
753 | dwc3_ep0_out_start(dwc); |
754 | } | |
755 | ||
756 | static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, | |
757 | const struct dwc3_event_depevt *event) | |
758 | { | |
c7fcdeb2 FB |
759 | struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; |
760 | ||
761 | dep->flags &= ~DWC3_EP_BUSY; | |
c2df85ca | 762 | dep->res_trans_idx = 0; |
df62df56 | 763 | dwc->setup_packet_pending = false; |
c7fcdeb2 | 764 | |
72246da4 | 765 | switch (dwc->ep0state) { |
c7fcdeb2 FB |
766 | case EP0_SETUP_PHASE: |
767 | dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n"); | |
72246da4 FB |
768 | dwc3_ep0_inspect_setup(dwc, event); |
769 | break; | |
770 | ||
c7fcdeb2 FB |
771 | case EP0_DATA_PHASE: |
772 | dev_vdbg(dwc->dev, "Data Phase\n"); | |
72246da4 FB |
773 | dwc3_ep0_complete_data(dwc, event); |
774 | break; | |
775 | ||
c7fcdeb2 FB |
776 | case EP0_STATUS_PHASE: |
777 | dev_vdbg(dwc->dev, "Status Phase\n"); | |
72246da4 FB |
778 | dwc3_ep0_complete_req(dwc, event); |
779 | break; | |
c7fcdeb2 FB |
780 | default: |
781 | WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); | |
782 | } | |
783 | } | |
72246da4 | 784 | |
c7fcdeb2 FB |
785 | static void dwc3_ep0_do_control_setup(struct dwc3 *dwc, |
786 | const struct dwc3_event_depevt *event) | |
787 | { | |
c7fcdeb2 FB |
788 | dwc3_ep0_out_start(dwc); |
789 | } | |
790 | ||
a0807881 FB |
791 | static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, |
792 | struct dwc3_ep *dep, struct dwc3_request *req) | |
c7fcdeb2 | 793 | { |
c7fcdeb2 FB |
794 | int ret; |
795 | ||
a0807881 | 796 | req->direction = !!dep->number; |
c7fcdeb2 | 797 | |
c7fcdeb2 | 798 | if (req->request.length == 0) { |
a0807881 | 799 | ret = dwc3_ep0_start_trans(dwc, dep->number, |
c7fcdeb2 FB |
800 | dwc->ctrl_req_addr, 0, |
801 | DWC3_TRBCTL_CONTROL_DATA); | |
802 | } else if ((req->request.length % dep->endpoint.maxpacket) | |
a0807881 FB |
803 | && (dep->number == 0)) { |
804 | u32 transfer_size; | |
805 | ||
0fc9a1be | 806 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
a0807881 | 807 | dep->number); |
0fc9a1be FB |
808 | if (ret) { |
809 | dev_dbg(dwc->dev, "failed to map request\n"); | |
810 | return; | |
811 | } | |
c7fcdeb2 | 812 | |
4552a0ca | 813 | WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE); |
c7fcdeb2 | 814 | |
a0807881 FB |
815 | transfer_size = roundup(req->request.length, |
816 | (u32) dep->endpoint.maxpacket); | |
817 | ||
c7fcdeb2 FB |
818 | dwc->ep0_bounced = true; |
819 | ||
820 | /* | |
4552a0ca FB |
821 | * REVISIT in case request length is bigger than |
822 | * DWC3_EP0_BOUNCE_SIZE we will need two chained | |
823 | * TRBs to handle the transfer. | |
c7fcdeb2 | 824 | */ |
a0807881 FB |
825 | ret = dwc3_ep0_start_trans(dwc, dep->number, |
826 | dwc->ep0_bounce_addr, transfer_size, | |
c7fcdeb2 FB |
827 | DWC3_TRBCTL_CONTROL_DATA); |
828 | } else { | |
0fc9a1be | 829 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
a0807881 | 830 | dep->number); |
0fc9a1be FB |
831 | if (ret) { |
832 | dev_dbg(dwc->dev, "failed to map request\n"); | |
833 | return; | |
834 | } | |
c7fcdeb2 | 835 | |
a0807881 FB |
836 | ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma, |
837 | req->request.length, DWC3_TRBCTL_CONTROL_DATA); | |
c7fcdeb2 FB |
838 | } |
839 | ||
840 | WARN_ON(ret < 0); | |
72246da4 FB |
841 | } |
842 | ||
a0807881 FB |
843 | static void dwc3_ep0_do_control_data(struct dwc3 *dwc, |
844 | const struct dwc3_event_depevt *event) | |
845 | { | |
846 | struct dwc3_ep *dep; | |
847 | struct dwc3_request *req; | |
848 | ||
849 | dep = dwc->eps[0]; | |
850 | ||
851 | if (list_empty(&dep->request_list)) { | |
852 | dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n"); | |
853 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
854 | ||
855 | if (event->endpoint_number) | |
856 | dep->flags |= DWC3_EP0_DIR_IN; | |
857 | return; | |
858 | } | |
859 | ||
860 | req = next_request(&dep->request_list); | |
861 | dep = dwc->eps[event->endpoint_number]; | |
862 | ||
863 | __dwc3_ep0_do_control_data(dwc, dep, req); | |
864 | } | |
865 | ||
f0f2b2a2 | 866 | static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) |
72246da4 | 867 | { |
f0f2b2a2 | 868 | struct dwc3 *dwc = dep->dwc; |
c7fcdeb2 | 869 | u32 type; |
72246da4 | 870 | |
c7fcdeb2 FB |
871 | type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 |
872 | : DWC3_TRBCTL_CONTROL_STATUS2; | |
873 | ||
f0f2b2a2 | 874 | return dwc3_ep0_start_trans(dwc, dep->number, |
c7fcdeb2 | 875 | dwc->ctrl_req_addr, 0, type); |
f0f2b2a2 | 876 | } |
c7fcdeb2 | 877 | |
f0f2b2a2 SAS |
878 | static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum) |
879 | { | |
880 | struct dwc3_ep *dep = dwc->eps[epnum]; | |
881 | ||
457e84b6 FB |
882 | if (dwc->resize_fifos) { |
883 | dev_dbg(dwc->dev, "starting to resize fifos\n"); | |
884 | dwc3_gadget_resize_tx_fifos(dwc); | |
885 | dwc->resize_fifos = 0; | |
886 | } | |
887 | ||
f0f2b2a2 | 888 | WARN_ON(dwc3_ep0_start_control_status(dep)); |
c7fcdeb2 FB |
889 | } |
890 | ||
891 | static void dwc3_ep0_xfernotready(struct dwc3 *dwc, | |
892 | const struct dwc3_event_depevt *event) | |
893 | { | |
df62df56 FB |
894 | dwc->setup_packet_pending = true; |
895 | ||
9cc9bcd5 FB |
896 | /* |
897 | * This part is very tricky: If we has just handled | |
898 | * XferNotReady(Setup) and we're now expecting a | |
899 | * XferComplete but, instead, we receive another | |
900 | * XferNotReady(Setup), we should STALL and restart | |
901 | * the state machine. | |
902 | * | |
903 | * In all other cases, we just continue waiting | |
904 | * for the XferComplete event. | |
905 | * | |
906 | * We are a little bit unsafe here because we're | |
907 | * not trying to ensure that last event was, indeed, | |
908 | * XferNotReady(Setup). | |
909 | * | |
910 | * Still, we don't expect any condition where that | |
911 | * should happen and, even if it does, it would be | |
912 | * another error condition. | |
913 | */ | |
914 | if (dwc->ep0_next_event == DWC3_EP0_COMPLETE) { | |
915 | switch (event->status) { | |
916 | case DEPEVT_STATUS_CONTROL_SETUP: | |
917 | dev_vdbg(dwc->dev, "Unexpected XferNotReady(Setup)\n"); | |
918 | dwc3_ep0_stall_and_restart(dwc); | |
919 | break; | |
920 | case DEPEVT_STATUS_CONTROL_DATA: | |
921 | /* FALLTHROUGH */ | |
922 | case DEPEVT_STATUS_CONTROL_STATUS: | |
923 | /* FALLTHROUGH */ | |
924 | default: | |
925 | dev_vdbg(dwc->dev, "waiting for XferComplete\n"); | |
926 | } | |
927 | ||
928 | return; | |
929 | } | |
930 | ||
c7fcdeb2 FB |
931 | switch (event->status) { |
932 | case DEPEVT_STATUS_CONTROL_SETUP: | |
933 | dev_vdbg(dwc->dev, "Control Setup\n"); | |
f0f2b2a2 SAS |
934 | |
935 | dwc->ep0state = EP0_SETUP_PHASE; | |
936 | ||
c7fcdeb2 FB |
937 | dwc3_ep0_do_control_setup(dwc, event); |
938 | break; | |
1ddcb218 | 939 | |
c7fcdeb2 FB |
940 | case DEPEVT_STATUS_CONTROL_DATA: |
941 | dev_vdbg(dwc->dev, "Control Data\n"); | |
1ddcb218 | 942 | |
f0f2b2a2 SAS |
943 | dwc->ep0state = EP0_DATA_PHASE; |
944 | ||
1ddcb218 FB |
945 | if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) { |
946 | dev_vdbg(dwc->dev, "Expected %d got %d\n", | |
25355be6 FB |
947 | dwc->ep0_next_event, |
948 | DWC3_EP0_NRDY_DATA); | |
1ddcb218 FB |
949 | |
950 | dwc3_ep0_stall_and_restart(dwc); | |
951 | return; | |
952 | } | |
953 | ||
55f3fba6 FB |
954 | /* |
955 | * One of the possible error cases is when Host _does_ | |
956 | * request for Data Phase, but it does so on the wrong | |
957 | * direction. | |
958 | * | |
959 | * Here, we already know ep0_next_event is DATA (see above), | |
960 | * so we only need to check for direction. | |
961 | */ | |
962 | if (dwc->ep0_expect_in != event->endpoint_number) { | |
963 | dev_vdbg(dwc->dev, "Wrong direction for Data phase\n"); | |
964 | dwc3_ep0_stall_and_restart(dwc); | |
965 | return; | |
966 | } | |
967 | ||
c7fcdeb2 FB |
968 | dwc3_ep0_do_control_data(dwc, event); |
969 | break; | |
1ddcb218 | 970 | |
c7fcdeb2 FB |
971 | case DEPEVT_STATUS_CONTROL_STATUS: |
972 | dev_vdbg(dwc->dev, "Control Status\n"); | |
1ddcb218 | 973 | |
f0f2b2a2 SAS |
974 | dwc->ep0state = EP0_STATUS_PHASE; |
975 | ||
1ddcb218 FB |
976 | if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) { |
977 | dev_vdbg(dwc->dev, "Expected %d got %d\n", | |
25355be6 FB |
978 | dwc->ep0_next_event, |
979 | DWC3_EP0_NRDY_STATUS); | |
1ddcb218 FB |
980 | |
981 | dwc3_ep0_stall_and_restart(dwc); | |
982 | return; | |
983 | } | |
5bdb1dcc SAS |
984 | |
985 | if (dwc->delayed_status) { | |
986 | WARN_ON_ONCE(event->endpoint_number != 1); | |
987 | dev_vdbg(dwc->dev, "Mass Storage delayed status\n"); | |
988 | return; | |
989 | } | |
990 | ||
f0f2b2a2 | 991 | dwc3_ep0_do_control_status(dwc, event->endpoint_number); |
72246da4 FB |
992 | } |
993 | } | |
994 | ||
995 | void dwc3_ep0_interrupt(struct dwc3 *dwc, | |
8becf270 | 996 | const struct dwc3_event_depevt *event) |
72246da4 FB |
997 | { |
998 | u8 epnum = event->endpoint_number; | |
999 | ||
1000 | dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n", | |
1001 | dwc3_ep_event_string(event->endpoint_event), | |
b147f357 | 1002 | epnum >> 1, (epnum & 1) ? "in" : "out", |
72246da4 FB |
1003 | dwc3_ep0_state_string(dwc->ep0state)); |
1004 | ||
1005 | switch (event->endpoint_event) { | |
1006 | case DWC3_DEPEVT_XFERCOMPLETE: | |
1007 | dwc3_ep0_xfer_complete(dwc, event); | |
1008 | break; | |
1009 | ||
1010 | case DWC3_DEPEVT_XFERNOTREADY: | |
1011 | dwc3_ep0_xfernotready(dwc, event); | |
1012 | break; | |
1013 | ||
1014 | case DWC3_DEPEVT_XFERINPROGRESS: | |
1015 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
1016 | case DWC3_DEPEVT_STREAMEVT: | |
1017 | case DWC3_DEPEVT_EPCMDCMPLT: | |
1018 | break; | |
1019 | } | |
1020 | } |