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usb: dwc3: core: drop DWC3_EVENT_BUFFERS_MAX
[linux-2.6-block.git] / drivers / usb / dwc3 / ep0.c
CommitLineData
72246da4
FB		 1/**
2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/kernel.h>
40#include <linux/slab.h>
41#include <linux/spinlock.h>
42#include <linux/platform_device.h>
43#include <linux/pm_runtime.h>
44#include <linux/interrupt.h>
45#include <linux/io.h>
46#include <linux/list.h>
47#include <linux/dma-mapping.h>
48
49#include <linux/usb/ch9.h>
50#include <linux/usb/gadget.h>
51
52#include "core.h"
53#include "gadget.h"
54#include "io.h"
55
56static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
57 const struct dwc3_event_depevt *event);
58
59static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
60{
61 switch (state) {
62 case EP0_UNCONNECTED:
63 return "Unconnected";
c7fcdeb2
FB		 64 case EP0_SETUP_PHASE:
65 return "Setup Phase";
66 case EP0_DATA_PHASE:
67 return "Data Phase";
68 case EP0_STATUS_PHASE:
69 return "Status Phase";
72246da4
FB		 70 default:
71 return "UNKNOWN";
72 }
73}
74
75static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
c7fcdeb2 76 u32 len, u32 type)
72246da4
FB		 77{
78 struct dwc3_gadget_ep_cmd_params params;
79 struct dwc3_trb_hw *trb_hw;
80 struct dwc3_trb trb;
81 struct dwc3_ep *dep;
82
83 int ret;
84
85 dep = dwc->eps[epnum];
c7fcdeb2
FB		 86 if (dep->flags & DWC3_EP_BUSY) {
87 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
88 return 0;
89 }
72246da4
FB		 90
91 trb_hw = dwc->ep0_trb;
92 memset(&trb, 0, sizeof(trb));
93
c7fcdeb2 94 trb.trbctl = type;
72246da4
FB		 95 trb.bplh = buf_dma;
96 trb.length = len;
97
98 trb.hwo = 1;
99 trb.lst = 1;
100 trb.ioc = 1;
101 trb.isp_imi = 1;
102
103 dwc3_trb_to_hw(&trb, trb_hw);
104
105 memset(&params, 0, sizeof(params));
dc1c70a7
FB		 106 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
107 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
72246da4
FB		 108
109 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
110 DWC3_DEPCMD_STARTTRANSFER, &params);
111 if (ret < 0) {
112 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
113 return ret;
114 }
115
c7fcdeb2 116 dep->flags |= DWC3_EP_BUSY;
72246da4
FB		 117 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
118 dep->number);
119
1ddcb218
FB		 120 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
121
72246da4
FB		 122 return 0;
123}
124
125static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
126 struct dwc3_request *req)
127{
c7fcdeb2 128 int ret = 0;
72246da4
FB		 129
130 req->request.actual = 0;
131 req->request.status = -EINPROGRESS;
72246da4
FB		 132 req->epnum = dep->number;
133
134 list_add_tail(&req->list, &dep->request_list);
a6829706 135
c7fcdeb2
FB		 136 /*
137 * Gadget driver might not be quick enough to queue a request
138 * before we get a Transfer Not Ready event on this endpoint.
139 *
140 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
141 * flag is set, it's telling us that as soon as Gadget queues the
142 * required request, we should kick the transfer here because the
143 * IRQ we were waiting for is long gone.
144 */
145 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
146 struct dwc3 *dwc = dep->dwc;
147 unsigned direction;
148 u32 type;
149
150 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
151
152 if (dwc->ep0state == EP0_STATUS_PHASE) {
153 type = dwc->three_stage_setup
154 ? DWC3_TRBCTL_CONTROL_STATUS3
155 : DWC3_TRBCTL_CONTROL_STATUS2;
156 } else if (dwc->ep0state == EP0_DATA_PHASE) {
157 type = DWC3_TRBCTL_CONTROL_DATA;
158 } else {
159 /* should never happen */
160 WARN_ON(1);
161 return 0;
162 }
72246da4 163
c7fcdeb2
FB		 164 ret = dwc3_ep0_start_trans(dwc, direction,
165 req->request.dma, req->request.length, type);
166 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
167 DWC3_EP0_DIR_IN);
72246da4
FB		 168 }
169
170 return ret;
171}
172
173int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
174 gfp_t gfp_flags)
175{
176 struct dwc3_request *req = to_dwc3_request(request);
177 struct dwc3_ep *dep = to_dwc3_ep(ep);
178 struct dwc3 *dwc = dep->dwc;
179
180 unsigned long flags;
181
182 int ret;
183
72246da4
FB		 184 spin_lock_irqsave(&dwc->lock, flags);
185 if (!dep->desc) {
186 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
187 request, dep->name);
188 ret = -ESHUTDOWN;
189 goto out;
190 }
191
192 /* we share one TRB for ep0/1 */
193 if (!list_empty(&dwc->eps[0]->request_list) ||
8ee6270c 194 !list_empty(&dwc->eps[1]->request_list)) {
72246da4
FB		 195 ret = -EBUSY;
196 goto out;
197 }
198
199 dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
200 request, dep->name, request->length,
201 dwc3_ep0_state_string(dwc->ep0state));
202
203 ret = __dwc3_gadget_ep0_queue(dep, req);
204
205out:
206 spin_unlock_irqrestore(&dwc->lock, flags);
207
208 return ret;
209}
210
211static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
212{
d742220b
FB		 213 struct dwc3_ep *dep = dwc->eps[0];
214
72246da4
FB		 215 /* stall is always issued on EP0 */
216 __dwc3_gadget_ep_set_halt(dwc->eps[0], 1);
76cb323f 217 dwc->eps[0]->flags = DWC3_EP_ENABLED;
d742220b
FB		 218
219 if (!list_empty(&dep->request_list)) {
220 struct dwc3_request *req;
221
222 req = next_request(&dep->request_list);
223 dwc3_gadget_giveback(dep, req, -ECONNRESET);
224 }
225
c7fcdeb2 226 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 227 dwc3_ep0_out_start(dwc);
228}
229
230void dwc3_ep0_out_start(struct dwc3 *dwc)
231{
72246da4
FB		 232 int ret;
233
c7fcdeb2
FB		 234 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
235 DWC3_TRBCTL_CONTROL_SETUP);
72246da4
FB		 236 WARN_ON(ret < 0);
237}
238
72246da4
FB		 239static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
240{
241 struct dwc3_ep *dep;
242 u32 windex = le16_to_cpu(wIndex_le);
243 u32 epnum;
244
245 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
246 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
247 epnum |= 1;
248
249 dep = dwc->eps[epnum];
250 if (dep->flags & DWC3_EP_ENABLED)
251 return dep;
252
253 return NULL;
254}
255
8ee6270c 256static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
72246da4 257{
72246da4 258}
72246da4
FB		 259/*
260 * ch 9.4.5
261 */
262static int dwc3_ep0_handle_status(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
263{
264 struct dwc3_ep *dep;
265 u32 recip;
266 u16 usb_status = 0;
267 __le16 *response_pkt;
268
269 recip = ctrl->bRequestType & USB_RECIP_MASK;
270 switch (recip) {
271 case USB_RECIP_DEVICE:
272 /*
273 * We are self-powered. U1/U2/LTM will be set later
274 * once we handle this states. RemoteWakeup is 0 on SS
275 */
276 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
277 break;
278
279 case USB_RECIP_INTERFACE:
280 /*
281 * Function Remote Wake Capable D0
282 * Function Remote Wakeup D1
283 */
284 break;
285
286 case USB_RECIP_ENDPOINT:
287 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
288 if (!dep)
289 return -EINVAL;
290
291 if (dep->flags & DWC3_EP_STALL)
292 usb_status = 1 << USB_ENDPOINT_HALT;
293 break;
294 default:
295 return -EINVAL;
296 };
297
298 response_pkt = (__le16 *) dwc->setup_buf;
299 *response_pkt = cpu_to_le16(usb_status);
300 dwc->ep0_usb_req.length = sizeof(*response_pkt);
8ee6270c
SAS		 301 dwc->ep0_usb_req.dma = dwc->setup_buf_addr;
302 dwc->ep0_usb_req.complete = dwc3_ep0_status_cmpl;
303 return usb_ep_queue(&dwc->eps[1]->endpoint, &dwc->ep0_usb_req,
304 GFP_ATOMIC);
72246da4
FB		 305}
306
307static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
308 struct usb_ctrlrequest *ctrl, int set)
309{
310 struct dwc3_ep *dep;
311 u32 recip;
312 u32 wValue;
313 u32 wIndex;
314 u32 reg;
315 int ret;
316 u32 mode;
317
318 wValue = le16_to_cpu(ctrl->wValue);
319 wIndex = le16_to_cpu(ctrl->wIndex);
320 recip = ctrl->bRequestType & USB_RECIP_MASK;
321 switch (recip) {
322 case USB_RECIP_DEVICE:
323
324 /*
325 * 9.4.1 says only only for SS, in AddressState only for
326 * default control pipe
327 */
328 switch (wValue) {
329 case USB_DEVICE_U1_ENABLE:
330 case USB_DEVICE_U2_ENABLE:
331 case USB_DEVICE_LTM_ENABLE:
332 if (dwc->dev_state != DWC3_CONFIGURED_STATE)
333 return -EINVAL;
334 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
335 return -EINVAL;
336 }
337
338 /* XXX add U[12] & LTM */
339 switch (wValue) {
340 case USB_DEVICE_REMOTE_WAKEUP:
341 break;
342 case USB_DEVICE_U1_ENABLE:
343 break;
344 case USB_DEVICE_U2_ENABLE:
345 break;
346 case USB_DEVICE_LTM_ENABLE:
347 break;
348
349 case USB_DEVICE_TEST_MODE:
350 if ((wIndex & 0xff) != 0)
351 return -EINVAL;
352 if (!set)
353 return -EINVAL;
354
355 mode = wIndex >> 8;
356 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
357 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
358
359 switch (mode) {
360 case TEST_J:
361 case TEST_K:
362 case TEST_SE0_NAK:
363 case TEST_PACKET:
364 case TEST_FORCE_EN:
365 reg |= mode << 1;
366 break;
367 default:
368 return -EINVAL;
369 }
370 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
371 break;
372 default:
373 return -EINVAL;
374 }
375 break;
376
377 case USB_RECIP_INTERFACE:
378 switch (wValue) {
379 case USB_INTRF_FUNC_SUSPEND:
380 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
381 /* XXX enable Low power suspend */
382 ;
383 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
384 /* XXX enable remote wakeup */
385 ;
386 break;
387 default:
388 return -EINVAL;
389 }
390 break;
391
392 case USB_RECIP_ENDPOINT:
393 switch (wValue) {
394 case USB_ENDPOINT_HALT:
395
396 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
397 if (!dep)
398 return -EINVAL;
399 ret = __dwc3_gadget_ep_set_halt(dep, set);
400 if (ret)
401 return -EINVAL;
402 break;
403 default:
404 return -EINVAL;
405 }
406 break;
407
408 default:
409 return -EINVAL;
410 };
411
72246da4
FB		 412 return 0;
413}
414
415static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
416{
72246da4
FB		 417 u32 addr;
418 u32 reg;
419
420 addr = le16_to_cpu(ctrl->wValue);
f96a6ec1
FB		 421 if (addr > 127) {
422 dev_dbg(dwc->dev, "invalid device address %d\n", addr);
72246da4 423 return -EINVAL;
f96a6ec1
FB		 424 }
425
426 if (dwc->dev_state == DWC3_CONFIGURED_STATE) {
427 dev_dbg(dwc->dev, "trying to set address when configured\n");
428 return -EINVAL;
429 }
72246da4 430
2646021e
FB		 431 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
432 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
433 reg |= DWC3_DCFG_DEVADDR(addr);
434 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4 435
2646021e
FB		 436 if (addr)
437 dwc->dev_state = DWC3_ADDRESS_STATE;
438 else
439 dwc->dev_state = DWC3_DEFAULT_STATE;
c7fcdeb2 440
2646021e 441 return 0;
72246da4
FB		 442}
443
444static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
445{
446 int ret;
447
448 spin_unlock(&dwc->lock);
449 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
450 spin_lock(&dwc->lock);
451 return ret;
452}
453
454static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
455{
456 u32 cfg;
457 int ret;
458
b23c8439 459 dwc->start_config_issued = false;
72246da4
FB		 460 cfg = le16_to_cpu(ctrl->wValue);
461
462 switch (dwc->dev_state) {
463 case DWC3_DEFAULT_STATE:
464 return -EINVAL;
465 break;
466
467 case DWC3_ADDRESS_STATE:
468 ret = dwc3_ep0_delegate_req(dwc, ctrl);
469 /* if the cfg matches and the cfg is non zero */
470 if (!ret && cfg)
471 dwc->dev_state = DWC3_CONFIGURED_STATE;
472 break;
473
474 case DWC3_CONFIGURED_STATE:
475 ret = dwc3_ep0_delegate_req(dwc, ctrl);
476 if (!cfg)
477 dwc->dev_state = DWC3_ADDRESS_STATE;
478 break;
479 }
480 return 0;
481}
482
483static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
484{
485 int ret;
486
487 switch (ctrl->bRequest) {
488 case USB_REQ_GET_STATUS:
489 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
490 ret = dwc3_ep0_handle_status(dwc, ctrl);
491 break;
492 case USB_REQ_CLEAR_FEATURE:
493 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
494 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
495 break;
496 case USB_REQ_SET_FEATURE:
497 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
498 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
499 break;
500 case USB_REQ_SET_ADDRESS:
501 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
502 ret = dwc3_ep0_set_address(dwc, ctrl);
503 break;
504 case USB_REQ_SET_CONFIGURATION:
505 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
506 ret = dwc3_ep0_set_config(dwc, ctrl);
507 break;
508 default:
509 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
510 ret = dwc3_ep0_delegate_req(dwc, ctrl);
511 break;
512 };
513
514 return ret;
515}
516
517static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
518 const struct dwc3_event_depevt *event)
519{
520 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
521 int ret;
522 u32 len;
523
524 if (!dwc->gadget_driver)
525 goto err;
526
527 len = le16_to_cpu(ctrl->wLength);
1ddcb218 528 if (!len) {
d95b09b9
FB		 529 dwc->three_stage_setup = false;
530 dwc->ep0_expect_in = false;
1ddcb218
FB		 531 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
532 } else {
d95b09b9
FB		 533 dwc->three_stage_setup = true;
534 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
1ddcb218
FB		 535 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
536 }
72246da4
FB		 537
538 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
539 ret = dwc3_ep0_std_request(dwc, ctrl);
540 else
541 ret = dwc3_ep0_delegate_req(dwc, ctrl);
542
543 if (ret >= 0)
544 return;
545
546err:
547 dwc3_ep0_stall_and_restart(dwc);
548}
549
550static void dwc3_ep0_complete_data(struct dwc3 *dwc,
551 const struct dwc3_event_depevt *event)
552{
553 struct dwc3_request *r = NULL;
554 struct usb_request *ur;
555 struct dwc3_trb trb;
556 struct dwc3_ep *dep;
c611ccb4 557 u32 transferred;
72246da4
FB		 558 u8 epnum;
559
560 epnum = event->endpoint_number;
561 dep = dwc->eps[epnum];
562
1ddcb218
FB		 563 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
564
8ee6270c
SAS		 565 r = next_request(&dwc->eps[0]->request_list);
566 ur = &r->request;
72246da4
FB		 567
568 dwc3_trb_to_nat(dwc->ep0_trb, &trb);
569
a6829706
FB		 570 if (dwc->ep0_bounced) {
571 struct dwc3_ep *ep0 = dwc->eps[0];
572
c7fcdeb2
FB		 573 transferred = min_t(u32, ur->length,
574 ep0->endpoint.maxpacket - trb.length);
a6829706
FB		 575 memcpy(ur->buf, dwc->ep0_bounce, transferred);
576 dwc->ep0_bounced = false;
577 } else {
578 transferred = ur->length - trb.length;
579 ur->actual += transferred;
580 }
72246da4
FB		 581
582 if ((epnum & 1) && ur->actual < ur->length) {
583 /* for some reason we did not get everything out */
584
585 dwc3_ep0_stall_and_restart(dwc);
72246da4
FB		 586 } else {
587 /*
588 * handle the case where we have to send a zero packet. This
589 * seems to be case when req.length > maxpacket. Could it be?
590 */
72246da4
FB		 591 if (r)
592 dwc3_gadget_giveback(dep, r, 0);
593 }
594}
595
596static void dwc3_ep0_complete_req(struct dwc3 *dwc,
597 const struct dwc3_event_depevt *event)
598{
599 struct dwc3_request *r;
600 struct dwc3_ep *dep;
72246da4 601
c7fcdeb2 602 dep = dwc->eps[0];
72246da4
FB		 603
604 if (!list_empty(&dep->request_list)) {
605 r = next_request(&dep->request_list);
606
607 dwc3_gadget_giveback(dep, r, 0);
608 }
609
c7fcdeb2 610 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 611 dwc3_ep0_out_start(dwc);
612}
613
614static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
615 const struct dwc3_event_depevt *event)
616{
c7fcdeb2
FB		 617 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
618
619 dep->flags &= ~DWC3_EP_BUSY;
620
72246da4 621 switch (dwc->ep0state) {
c7fcdeb2
FB		 622 case EP0_SETUP_PHASE:
623 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
72246da4
FB		 624 dwc3_ep0_inspect_setup(dwc, event);
625 break;
626
c7fcdeb2
FB		 627 case EP0_DATA_PHASE:
628 dev_vdbg(dwc->dev, "Data Phase\n");
72246da4
FB		 629 dwc3_ep0_complete_data(dwc, event);
630 break;
631
c7fcdeb2
FB		 632 case EP0_STATUS_PHASE:
633 dev_vdbg(dwc->dev, "Status Phase\n");
72246da4
FB		 634 dwc3_ep0_complete_req(dwc, event);
635 break;
c7fcdeb2
FB		 636 default:
637 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
638 }
639}
72246da4 640
c7fcdeb2
FB		 641static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
642 const struct dwc3_event_depevt *event)
643{
644 dwc->ep0state = EP0_SETUP_PHASE;
645 dwc3_ep0_out_start(dwc);
646}
647
648static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
649 const struct dwc3_event_depevt *event)
650{
651 struct dwc3_ep *dep;
652 struct dwc3_request *req;
653 int ret;
654
655 dep = dwc->eps[0];
656 dwc->ep0state = EP0_DATA_PHASE;
657
658 if (list_empty(&dep->request_list)) {
659 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
660 dep->flags |= DWC3_EP_PENDING_REQUEST;
661
662 if (event->endpoint_number)
663 dep->flags |= DWC3_EP0_DIR_IN;
664 return;
72246da4 665 }
c7fcdeb2
FB		 666
667 req = next_request(&dep->request_list);
668 req->direction = !!event->endpoint_number;
669
670 dwc->ep0state = EP0_DATA_PHASE;
671 if (req->request.length == 0) {
672 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
673 dwc->ctrl_req_addr, 0,
674 DWC3_TRBCTL_CONTROL_DATA);
675 } else if ((req->request.length % dep->endpoint.maxpacket)
676 && (event->endpoint_number == 0)) {
677 dwc3_map_buffer_to_dma(req);
678
679 WARN_ON(req->request.length > dep->endpoint.maxpacket);
680
681 dwc->ep0_bounced = true;
682
683 /*
684 * REVISIT in case request length is bigger than EP0
685 * wMaxPacketSize, we will need two chained TRBs to handle
686 * the transfer.
687 */
688 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
689 dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
690 DWC3_TRBCTL_CONTROL_DATA);
691 } else {
692 dwc3_map_buffer_to_dma(req);
693
694 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
695 req->request.dma, req->request.length,
696 DWC3_TRBCTL_CONTROL_DATA);
697 }
698
699 WARN_ON(ret < 0);
72246da4
FB		 700}
701
c7fcdeb2 702static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
72246da4
FB		 703 const struct dwc3_event_depevt *event)
704{
c7fcdeb2
FB		 705 u32 type;
706 int ret;
72246da4 707
c7fcdeb2 708 dwc->ep0state = EP0_STATUS_PHASE;
72246da4 709
c7fcdeb2
FB		 710 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
711 : DWC3_TRBCTL_CONTROL_STATUS2;
712
713 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
714 dwc->ctrl_req_addr, 0, type);
715
716 WARN_ON(ret < 0);
717}
718
719static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
720 const struct dwc3_event_depevt *event)
721{
9cc9bcd5
FB		 722 /*
723 * This part is very tricky: If we has just handled
724 * XferNotReady(Setup) and we're now expecting a
725 * XferComplete but, instead, we receive another
726 * XferNotReady(Setup), we should STALL and restart
727 * the state machine.
728 *
729 * In all other cases, we just continue waiting
730 * for the XferComplete event.
731 *
732 * We are a little bit unsafe here because we're
733 * not trying to ensure that last event was, indeed,
734 * XferNotReady(Setup).
735 *
736 * Still, we don't expect any condition where that
737 * should happen and, even if it does, it would be
738 * another error condition.
739 */
740 if (dwc->ep0_next_event == DWC3_EP0_COMPLETE) {
741 switch (event->status) {
742 case DEPEVT_STATUS_CONTROL_SETUP:
743 dev_vdbg(dwc->dev, "Unexpected XferNotReady(Setup)\n");
744 dwc3_ep0_stall_and_restart(dwc);
745 break;
746 case DEPEVT_STATUS_CONTROL_DATA:
747 /* FALLTHROUGH */
748 case DEPEVT_STATUS_CONTROL_STATUS:
749 /* FALLTHROUGH */
750 default:
751 dev_vdbg(dwc->dev, "waiting for XferComplete\n");
752 }
753
754 return;
755 }
756
c7fcdeb2
FB		 757 switch (event->status) {
758 case DEPEVT_STATUS_CONTROL_SETUP:
759 dev_vdbg(dwc->dev, "Control Setup\n");
760 dwc3_ep0_do_control_setup(dwc, event);
761 break;
1ddcb218 762
c7fcdeb2
FB		 763 case DEPEVT_STATUS_CONTROL_DATA:
764 dev_vdbg(dwc->dev, "Control Data\n");
1ddcb218
FB		 765
766 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
767 dev_vdbg(dwc->dev, "Expected %d got %d\n",
25355be6
FB		 768 dwc->ep0_next_event,
769 DWC3_EP0_NRDY_DATA);
1ddcb218
FB		 770
771 dwc3_ep0_stall_and_restart(dwc);
772 return;
773 }
774
55f3fba6
FB		 775 /*
776 * One of the possible error cases is when Host _does_
777 * request for Data Phase, but it does so on the wrong
778 * direction.
779 *
780 * Here, we already know ep0_next_event is DATA (see above),
781 * so we only need to check for direction.
782 */
783 if (dwc->ep0_expect_in != event->endpoint_number) {
784 dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
785 dwc3_ep0_stall_and_restart(dwc);
786 return;
787 }
788
c7fcdeb2
FB		 789 dwc3_ep0_do_control_data(dwc, event);
790 break;
1ddcb218 791
c7fcdeb2
FB		 792 case DEPEVT_STATUS_CONTROL_STATUS:
793 dev_vdbg(dwc->dev, "Control Status\n");
1ddcb218
FB		 794
795 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
796 dev_vdbg(dwc->dev, "Expected %d got %d\n",
25355be6
FB		 797 dwc->ep0_next_event,
798 DWC3_EP0_NRDY_STATUS);
1ddcb218
FB		 799
800 dwc3_ep0_stall_and_restart(dwc);
801 return;
802 }
c7fcdeb2 803 dwc3_ep0_do_control_status(dwc, event);
72246da4
FB		 804 }
805}
806
807void dwc3_ep0_interrupt(struct dwc3 *dwc,
808 const const struct dwc3_event_depevt *event)
809{
810 u8 epnum = event->endpoint_number;
811
812 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
813 dwc3_ep_event_string(event->endpoint_event),
b147f357 814 epnum >> 1, (epnum & 1) ? "in" : "out",
72246da4
FB		 815 dwc3_ep0_state_string(dwc->ep0state));
816
817 switch (event->endpoint_event) {
818 case DWC3_DEPEVT_XFERCOMPLETE:
819 dwc3_ep0_xfer_complete(dwc, event);
820 break;
821
822 case DWC3_DEPEVT_XFERNOTREADY:
823 dwc3_ep0_xfernotready(dwc, event);
824 break;
825
826 case DWC3_DEPEVT_XFERINPROGRESS:
827 case DWC3_DEPEVT_RXTXFIFOEVT:
828 case DWC3_DEPEVT_STREAMEVT:
829 case DWC3_DEPEVT_EPCMDCMPLT:
830 break;
831 }
832}
Linux 6.x block layer and io_uring tree(s)