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72246da4 FB |
1 | /** |
2 | * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
9 | * Redistribution and use in source and binary forms, with or without | |
10 | * modification, are permitted provided that the following conditions | |
11 | * are met: | |
12 | * 1. Redistributions of source code must retain the above copyright | |
13 | * notice, this list of conditions, and the following disclaimer, | |
14 | * without modification. | |
15 | * 2. Redistributions in binary form must reproduce the above copyright | |
16 | * notice, this list of conditions and the following disclaimer in the | |
17 | * documentation and/or other materials provided with the distribution. | |
18 | * 3. The names of the above-listed copyright holders may not be used | |
19 | * to endorse or promote products derived from this software without | |
20 | * specific prior written permission. | |
21 | * | |
22 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
23 | * GNU General Public License ("GPL") version 2, as published by the Free | |
24 | * Software Foundation. | |
25 | * | |
26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
27 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
28 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
29 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
30 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
31 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
32 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
33 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
34 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
35 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
36 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
37 | */ | |
38 | ||
39 | #include <linux/kernel.h> | |
40 | #include <linux/slab.h> | |
41 | #include <linux/spinlock.h> | |
42 | #include <linux/platform_device.h> | |
43 | #include <linux/pm_runtime.h> | |
44 | #include <linux/interrupt.h> | |
45 | #include <linux/io.h> | |
46 | #include <linux/list.h> | |
47 | #include <linux/dma-mapping.h> | |
48 | ||
49 | #include <linux/usb/ch9.h> | |
50 | #include <linux/usb/gadget.h> | |
5bdb1dcc | 51 | #include <linux/usb/composite.h> |
72246da4 FB |
52 | |
53 | #include "core.h" | |
54 | #include "gadget.h" | |
55 | #include "io.h" | |
56 | ||
788a23f4 | 57 | static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); |
a0807881 FB |
58 | static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, |
59 | struct dwc3_ep *dep, struct dwc3_request *req); | |
5bdb1dcc | 60 | |
72246da4 FB |
61 | static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) |
62 | { | |
63 | switch (state) { | |
64 | case EP0_UNCONNECTED: | |
65 | return "Unconnected"; | |
c7fcdeb2 FB |
66 | case EP0_SETUP_PHASE: |
67 | return "Setup Phase"; | |
68 | case EP0_DATA_PHASE: | |
69 | return "Data Phase"; | |
70 | case EP0_STATUS_PHASE: | |
71 | return "Status Phase"; | |
72246da4 FB |
72 | default: |
73 | return "UNKNOWN"; | |
74 | } | |
75 | } | |
76 | ||
77 | static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, | |
c7fcdeb2 | 78 | u32 len, u32 type) |
72246da4 FB |
79 | { |
80 | struct dwc3_gadget_ep_cmd_params params; | |
f6bafc6a | 81 | struct dwc3_trb *trb; |
72246da4 FB |
82 | struct dwc3_ep *dep; |
83 | ||
84 | int ret; | |
85 | ||
86 | dep = dwc->eps[epnum]; | |
c7fcdeb2 FB |
87 | if (dep->flags & DWC3_EP_BUSY) { |
88 | dev_vdbg(dwc->dev, "%s: still busy\n", dep->name); | |
89 | return 0; | |
90 | } | |
72246da4 | 91 | |
f6bafc6a | 92 | trb = dwc->ep0_trb; |
72246da4 | 93 | |
f6bafc6a FB |
94 | trb->bpl = lower_32_bits(buf_dma); |
95 | trb->bph = upper_32_bits(buf_dma); | |
96 | trb->size = len; | |
97 | trb->ctrl = type; | |
72246da4 | 98 | |
f6bafc6a FB |
99 | trb->ctrl |= (DWC3_TRB_CTRL_HWO |
100 | | DWC3_TRB_CTRL_LST | |
101 | | DWC3_TRB_CTRL_IOC | |
102 | | DWC3_TRB_CTRL_ISP_IMI); | |
72246da4 FB |
103 | |
104 | memset(¶ms, 0, sizeof(params)); | |
dc1c70a7 FB |
105 | params.param0 = upper_32_bits(dwc->ep0_trb_addr); |
106 | params.param1 = lower_32_bits(dwc->ep0_trb_addr); | |
72246da4 FB |
107 | |
108 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
109 | DWC3_DEPCMD_STARTTRANSFER, ¶ms); | |
110 | if (ret < 0) { | |
111 | dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); | |
112 | return ret; | |
113 | } | |
114 | ||
c7fcdeb2 | 115 | dep->flags |= DWC3_EP_BUSY; |
b4996a86 | 116 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, |
72246da4 FB |
117 | dep->number); |
118 | ||
1ddcb218 FB |
119 | dwc->ep0_next_event = DWC3_EP0_COMPLETE; |
120 | ||
72246da4 FB |
121 | return 0; |
122 | } | |
123 | ||
124 | static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, | |
125 | struct dwc3_request *req) | |
126 | { | |
5bdb1dcc | 127 | struct dwc3 *dwc = dep->dwc; |
72246da4 FB |
128 | |
129 | req->request.actual = 0; | |
130 | req->request.status = -EINPROGRESS; | |
72246da4 FB |
131 | req->epnum = dep->number; |
132 | ||
133 | list_add_tail(&req->list, &dep->request_list); | |
a6829706 | 134 | |
c7fcdeb2 FB |
135 | /* |
136 | * Gadget driver might not be quick enough to queue a request | |
137 | * before we get a Transfer Not Ready event on this endpoint. | |
138 | * | |
139 | * In that case, we will set DWC3_EP_PENDING_REQUEST. When that | |
140 | * flag is set, it's telling us that as soon as Gadget queues the | |
141 | * required request, we should kick the transfer here because the | |
142 | * IRQ we were waiting for is long gone. | |
143 | */ | |
144 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
c7fcdeb2 | 145 | unsigned direction; |
c7fcdeb2 FB |
146 | |
147 | direction = !!(dep->flags & DWC3_EP0_DIR_IN); | |
148 | ||
68d8a781 FB |
149 | if (dwc->ep0state != EP0_DATA_PHASE) { |
150 | dev_WARN(dwc->dev, "Unexpected pending request\n"); | |
c7fcdeb2 FB |
151 | return 0; |
152 | } | |
72246da4 | 153 | |
a0807881 FB |
154 | __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); |
155 | ||
c7fcdeb2 FB |
156 | dep->flags &= ~(DWC3_EP_PENDING_REQUEST | |
157 | DWC3_EP0_DIR_IN); | |
d9b33c60 FB |
158 | |
159 | return 0; | |
160 | } | |
161 | ||
162 | /* | |
163 | * In case gadget driver asked us to delay the STATUS phase, | |
164 | * handle it here. | |
165 | */ | |
166 | if (dwc->delayed_status) { | |
5bdb1dcc | 167 | dwc->delayed_status = false; |
68d3e668 FB |
168 | |
169 | if (dwc->ep0state == EP0_STATUS_PHASE) | |
788a23f4 | 170 | __dwc3_ep0_do_control_status(dwc, dwc->eps[1]); |
68d3e668 FB |
171 | else |
172 | dev_dbg(dwc->dev, "too early for delayed status\n"); | |
d9b33c60 FB |
173 | |
174 | return 0; | |
72246da4 FB |
175 | } |
176 | ||
fca8892a FB |
177 | /* |
178 | * Unfortunately we have uncovered a limitation wrt the Data Phase. | |
179 | * | |
180 | * Section 9.4 says we can wait for the XferNotReady(DATA) event to | |
181 | * come before issueing Start Transfer command, but if we do, we will | |
182 | * miss situations where the host starts another SETUP phase instead of | |
183 | * the DATA phase. Such cases happen at least on TD.7.6 of the Link | |
184 | * Layer Compliance Suite. | |
185 | * | |
186 | * The problem surfaces due to the fact that in case of back-to-back | |
187 | * SETUP packets there will be no XferNotReady(DATA) generated and we | |
188 | * will be stuck waiting for XferNotReady(DATA) forever. | |
189 | * | |
190 | * By looking at tables 9-13 and 9-14 of the Databook, we can see that | |
191 | * it tells us to start Data Phase right away. It also mentions that if | |
192 | * we receive a SETUP phase instead of the DATA phase, core will issue | |
193 | * XferComplete for the DATA phase, before actually initiating it in | |
194 | * the wire, with the TRB's status set to "SETUP_PENDING". Such status | |
195 | * can only be used to print some debugging logs, as the core expects | |
196 | * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, | |
197 | * just so it completes right away, without transferring anything and, | |
198 | * only then, we can go back to the SETUP phase. | |
199 | * | |
200 | * Because of this scenario, SNPS decided to change the programming | |
201 | * model of control transfers and support on-demand transfers only for | |
202 | * the STATUS phase. To fix the issue we have now, we will always wait | |
203 | * for gadget driver to queue the DATA phase's struct usb_request, then | |
204 | * start it right away. | |
205 | * | |
206 | * If we're actually in a 2-stage transfer, we will wait for | |
207 | * XferNotReady(STATUS). | |
208 | */ | |
209 | if (dwc->three_stage_setup) { | |
210 | unsigned direction; | |
211 | ||
212 | direction = dwc->ep0_expect_in; | |
213 | dwc->ep0state = EP0_DATA_PHASE; | |
214 | ||
215 | __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); | |
216 | ||
217 | dep->flags &= ~DWC3_EP0_DIR_IN; | |
218 | } | |
219 | ||
35f75696 | 220 | return 0; |
72246da4 FB |
221 | } |
222 | ||
223 | int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, | |
224 | gfp_t gfp_flags) | |
225 | { | |
226 | struct dwc3_request *req = to_dwc3_request(request); | |
227 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
228 | struct dwc3 *dwc = dep->dwc; | |
229 | ||
230 | unsigned long flags; | |
231 | ||
232 | int ret; | |
233 | ||
72246da4 | 234 | spin_lock_irqsave(&dwc->lock, flags); |
16e78db7 | 235 | if (!dep->endpoint.desc) { |
72246da4 FB |
236 | dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", |
237 | request, dep->name); | |
238 | ret = -ESHUTDOWN; | |
239 | goto out; | |
240 | } | |
241 | ||
242 | /* we share one TRB for ep0/1 */ | |
c2da2ff0 | 243 | if (!list_empty(&dep->request_list)) { |
72246da4 FB |
244 | ret = -EBUSY; |
245 | goto out; | |
246 | } | |
247 | ||
248 | dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n", | |
249 | request, dep->name, request->length, | |
250 | dwc3_ep0_state_string(dwc->ep0state)); | |
251 | ||
252 | ret = __dwc3_gadget_ep0_queue(dep, req); | |
253 | ||
254 | out: | |
255 | spin_unlock_irqrestore(&dwc->lock, flags); | |
256 | ||
257 | return ret; | |
258 | } | |
259 | ||
260 | static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) | |
261 | { | |
d742220b FB |
262 | struct dwc3_ep *dep = dwc->eps[0]; |
263 | ||
72246da4 | 264 | /* stall is always issued on EP0 */ |
c2da2ff0 SAS |
265 | __dwc3_gadget_ep_set_halt(dep, 1); |
266 | dep->flags = DWC3_EP_ENABLED; | |
5bdb1dcc | 267 | dwc->delayed_status = false; |
d742220b FB |
268 | |
269 | if (!list_empty(&dep->request_list)) { | |
270 | struct dwc3_request *req; | |
271 | ||
272 | req = next_request(&dep->request_list); | |
273 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
274 | } | |
275 | ||
c7fcdeb2 | 276 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
277 | dwc3_ep0_out_start(dwc); |
278 | } | |
279 | ||
08f0d966 PA |
280 | int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) |
281 | { | |
282 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
283 | struct dwc3 *dwc = dep->dwc; | |
284 | ||
285 | dwc3_ep0_stall_and_restart(dwc); | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
72246da4 FB |
290 | void dwc3_ep0_out_start(struct dwc3 *dwc) |
291 | { | |
72246da4 FB |
292 | int ret; |
293 | ||
c7fcdeb2 FB |
294 | ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, |
295 | DWC3_TRBCTL_CONTROL_SETUP); | |
72246da4 FB |
296 | WARN_ON(ret < 0); |
297 | } | |
298 | ||
72246da4 FB |
299 | static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) |
300 | { | |
301 | struct dwc3_ep *dep; | |
302 | u32 windex = le16_to_cpu(wIndex_le); | |
303 | u32 epnum; | |
304 | ||
305 | epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; | |
306 | if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) | |
307 | epnum |= 1; | |
308 | ||
309 | dep = dwc->eps[epnum]; | |
310 | if (dep->flags & DWC3_EP_ENABLED) | |
311 | return dep; | |
312 | ||
313 | return NULL; | |
314 | } | |
315 | ||
8ee6270c | 316 | static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) |
72246da4 | 317 | { |
72246da4 | 318 | } |
72246da4 FB |
319 | /* |
320 | * ch 9.4.5 | |
321 | */ | |
25b8ff68 FB |
322 | static int dwc3_ep0_handle_status(struct dwc3 *dwc, |
323 | struct usb_ctrlrequest *ctrl) | |
72246da4 FB |
324 | { |
325 | struct dwc3_ep *dep; | |
326 | u32 recip; | |
e6a3b5e2 | 327 | u32 reg; |
72246da4 FB |
328 | u16 usb_status = 0; |
329 | __le16 *response_pkt; | |
330 | ||
331 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
332 | switch (recip) { | |
333 | case USB_RECIP_DEVICE: | |
334 | /* | |
e6a3b5e2 | 335 | * LTM will be set once we know how to set this in HW. |
72246da4 FB |
336 | */ |
337 | usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED; | |
e6a3b5e2 SAS |
338 | |
339 | if (dwc->speed == DWC3_DSTS_SUPERSPEED) { | |
340 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
341 | if (reg & DWC3_DCTL_INITU1ENA) | |
342 | usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; | |
343 | if (reg & DWC3_DCTL_INITU2ENA) | |
344 | usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; | |
345 | } | |
346 | ||
72246da4 FB |
347 | break; |
348 | ||
349 | case USB_RECIP_INTERFACE: | |
350 | /* | |
351 | * Function Remote Wake Capable D0 | |
352 | * Function Remote Wakeup D1 | |
353 | */ | |
354 | break; | |
355 | ||
356 | case USB_RECIP_ENDPOINT: | |
357 | dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); | |
358 | if (!dep) | |
25b8ff68 | 359 | return -EINVAL; |
72246da4 FB |
360 | |
361 | if (dep->flags & DWC3_EP_STALL) | |
362 | usb_status = 1 << USB_ENDPOINT_HALT; | |
363 | break; | |
364 | default: | |
365 | return -EINVAL; | |
366 | }; | |
367 | ||
368 | response_pkt = (__le16 *) dwc->setup_buf; | |
369 | *response_pkt = cpu_to_le16(usb_status); | |
e2617796 FB |
370 | |
371 | dep = dwc->eps[0]; | |
372 | dwc->ep0_usb_req.dep = dep; | |
e0ce0b0a | 373 | dwc->ep0_usb_req.request.length = sizeof(*response_pkt); |
0fc9a1be | 374 | dwc->ep0_usb_req.request.buf = dwc->setup_buf; |
e0ce0b0a | 375 | dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; |
e2617796 FB |
376 | |
377 | return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); | |
72246da4 FB |
378 | } |
379 | ||
380 | static int dwc3_ep0_handle_feature(struct dwc3 *dwc, | |
381 | struct usb_ctrlrequest *ctrl, int set) | |
382 | { | |
383 | struct dwc3_ep *dep; | |
384 | u32 recip; | |
385 | u32 wValue; | |
386 | u32 wIndex; | |
e6a3b5e2 | 387 | u32 reg; |
72246da4 | 388 | int ret; |
72246da4 FB |
389 | |
390 | wValue = le16_to_cpu(ctrl->wValue); | |
391 | wIndex = le16_to_cpu(ctrl->wIndex); | |
392 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
393 | switch (recip) { | |
394 | case USB_RECIP_DEVICE: | |
395 | ||
e6a3b5e2 SAS |
396 | switch (wValue) { |
397 | case USB_DEVICE_REMOTE_WAKEUP: | |
398 | break; | |
72246da4 FB |
399 | /* |
400 | * 9.4.1 says only only for SS, in AddressState only for | |
401 | * default control pipe | |
402 | */ | |
72246da4 | 403 | case USB_DEVICE_U1_ENABLE: |
72246da4 FB |
404 | if (dwc->dev_state != DWC3_CONFIGURED_STATE) |
405 | return -EINVAL; | |
406 | if (dwc->speed != DWC3_DSTS_SUPERSPEED) | |
407 | return -EINVAL; | |
72246da4 | 408 | |
e6a3b5e2 SAS |
409 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
410 | if (set) | |
411 | reg |= DWC3_DCTL_INITU1ENA; | |
412 | else | |
413 | reg &= ~DWC3_DCTL_INITU1ENA; | |
414 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 415 | break; |
e6a3b5e2 | 416 | |
72246da4 | 417 | case USB_DEVICE_U2_ENABLE: |
e6a3b5e2 SAS |
418 | if (dwc->dev_state != DWC3_CONFIGURED_STATE) |
419 | return -EINVAL; | |
420 | if (dwc->speed != DWC3_DSTS_SUPERSPEED) | |
421 | return -EINVAL; | |
422 | ||
423 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
424 | if (set) | |
425 | reg |= DWC3_DCTL_INITU2ENA; | |
426 | else | |
427 | reg &= ~DWC3_DCTL_INITU2ENA; | |
428 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 429 | break; |
e6a3b5e2 | 430 | |
72246da4 | 431 | case USB_DEVICE_LTM_ENABLE: |
e6a3b5e2 | 432 | return -EINVAL; |
72246da4 FB |
433 | break; |
434 | ||
435 | case USB_DEVICE_TEST_MODE: | |
436 | if ((wIndex & 0xff) != 0) | |
437 | return -EINVAL; | |
438 | if (!set) | |
439 | return -EINVAL; | |
440 | ||
3b637367 GC |
441 | dwc->test_mode_nr = wIndex >> 8; |
442 | dwc->test_mode = true; | |
ecb07797 GC |
443 | break; |
444 | default: | |
445 | return -EINVAL; | |
72246da4 FB |
446 | } |
447 | break; | |
448 | ||
449 | case USB_RECIP_INTERFACE: | |
450 | switch (wValue) { | |
451 | case USB_INTRF_FUNC_SUSPEND: | |
452 | if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) | |
453 | /* XXX enable Low power suspend */ | |
454 | ; | |
455 | if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) | |
456 | /* XXX enable remote wakeup */ | |
457 | ; | |
458 | break; | |
459 | default: | |
460 | return -EINVAL; | |
461 | } | |
462 | break; | |
463 | ||
464 | case USB_RECIP_ENDPOINT: | |
465 | switch (wValue) { | |
466 | case USB_ENDPOINT_HALT: | |
1d046793 | 467 | dep = dwc3_wIndex_to_dep(dwc, wIndex); |
72246da4 FB |
468 | if (!dep) |
469 | return -EINVAL; | |
470 | ret = __dwc3_gadget_ep_set_halt(dep, set); | |
471 | if (ret) | |
472 | return -EINVAL; | |
473 | break; | |
474 | default: | |
475 | return -EINVAL; | |
476 | } | |
477 | break; | |
478 | ||
479 | default: | |
480 | return -EINVAL; | |
481 | }; | |
482 | ||
72246da4 FB |
483 | return 0; |
484 | } | |
485 | ||
486 | static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
487 | { | |
72246da4 FB |
488 | u32 addr; |
489 | u32 reg; | |
490 | ||
491 | addr = le16_to_cpu(ctrl->wValue); | |
f96a6ec1 FB |
492 | if (addr > 127) { |
493 | dev_dbg(dwc->dev, "invalid device address %d\n", addr); | |
72246da4 | 494 | return -EINVAL; |
f96a6ec1 FB |
495 | } |
496 | ||
497 | if (dwc->dev_state == DWC3_CONFIGURED_STATE) { | |
498 | dev_dbg(dwc->dev, "trying to set address when configured\n"); | |
499 | return -EINVAL; | |
500 | } | |
72246da4 | 501 | |
2646021e FB |
502 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
503 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
504 | reg |= DWC3_DCFG_DEVADDR(addr); | |
505 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 | 506 | |
2646021e FB |
507 | if (addr) |
508 | dwc->dev_state = DWC3_ADDRESS_STATE; | |
509 | else | |
510 | dwc->dev_state = DWC3_DEFAULT_STATE; | |
c7fcdeb2 | 511 | |
2646021e | 512 | return 0; |
72246da4 FB |
513 | } |
514 | ||
515 | static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
516 | { | |
517 | int ret; | |
518 | ||
519 | spin_unlock(&dwc->lock); | |
520 | ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); | |
521 | spin_lock(&dwc->lock); | |
522 | return ret; | |
523 | } | |
524 | ||
525 | static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
526 | { | |
527 | u32 cfg; | |
528 | int ret; | |
e274a31e | 529 | u32 reg; |
72246da4 | 530 | |
b23c8439 | 531 | dwc->start_config_issued = false; |
72246da4 FB |
532 | cfg = le16_to_cpu(ctrl->wValue); |
533 | ||
534 | switch (dwc->dev_state) { | |
535 | case DWC3_DEFAULT_STATE: | |
536 | return -EINVAL; | |
537 | break; | |
538 | ||
539 | case DWC3_ADDRESS_STATE: | |
540 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
541 | /* if the cfg matches and the cfg is non zero */ | |
457e84b6 | 542 | if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { |
72246da4 | 543 | dwc->dev_state = DWC3_CONFIGURED_STATE; |
e274a31e PA |
544 | /* |
545 | * Enable transition to U1/U2 state when | |
546 | * nothing is pending from application. | |
547 | */ | |
548 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
549 | reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); | |
550 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
551 | ||
457e84b6 FB |
552 | dwc->resize_fifos = true; |
553 | dev_dbg(dwc->dev, "resize fifos flag SET\n"); | |
554 | } | |
72246da4 FB |
555 | break; |
556 | ||
557 | case DWC3_CONFIGURED_STATE: | |
558 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
559 | if (!cfg) | |
560 | dwc->dev_state = DWC3_ADDRESS_STATE; | |
561 | break; | |
5bdb1dcc SAS |
562 | default: |
563 | ret = -EINVAL; | |
72246da4 | 564 | } |
5bdb1dcc | 565 | return ret; |
72246da4 FB |
566 | } |
567 | ||
865e09e7 FB |
568 | static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) |
569 | { | |
570 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
571 | struct dwc3 *dwc = dep->dwc; | |
572 | ||
573 | u32 param = 0; | |
574 | u32 reg; | |
575 | ||
576 | struct timing { | |
577 | u8 u1sel; | |
578 | u8 u1pel; | |
579 | u16 u2sel; | |
580 | u16 u2pel; | |
581 | } __packed timing; | |
582 | ||
583 | int ret; | |
584 | ||
585 | memcpy(&timing, req->buf, sizeof(timing)); | |
586 | ||
587 | dwc->u1sel = timing.u1sel; | |
588 | dwc->u1pel = timing.u1pel; | |
c8cf7af4 FB |
589 | dwc->u2sel = le16_to_cpu(timing.u2sel); |
590 | dwc->u2pel = le16_to_cpu(timing.u2pel); | |
865e09e7 FB |
591 | |
592 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
593 | if (reg & DWC3_DCTL_INITU2ENA) | |
594 | param = dwc->u2pel; | |
595 | if (reg & DWC3_DCTL_INITU1ENA) | |
596 | param = dwc->u1pel; | |
597 | ||
598 | /* | |
599 | * According to Synopsys Databook, if parameter is | |
600 | * greater than 125, a value of zero should be | |
601 | * programmed in the register. | |
602 | */ | |
603 | if (param > 125) | |
604 | param = 0; | |
605 | ||
606 | /* now that we have the time, issue DGCMD Set Sel */ | |
607 | ret = dwc3_send_gadget_generic_command(dwc, | |
608 | DWC3_DGCMD_SET_PERIODIC_PAR, param); | |
609 | WARN_ON(ret < 0); | |
610 | } | |
611 | ||
612 | static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
613 | { | |
614 | struct dwc3_ep *dep; | |
615 | u16 wLength; | |
616 | u16 wValue; | |
617 | ||
618 | if (dwc->dev_state == DWC3_DEFAULT_STATE) | |
619 | return -EINVAL; | |
620 | ||
621 | wValue = le16_to_cpu(ctrl->wValue); | |
622 | wLength = le16_to_cpu(ctrl->wLength); | |
623 | ||
624 | if (wLength != 6) { | |
625 | dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", | |
626 | wLength); | |
627 | return -EINVAL; | |
628 | } | |
629 | ||
630 | /* | |
631 | * To handle Set SEL we need to receive 6 bytes from Host. So let's | |
632 | * queue a usb_request for 6 bytes. | |
633 | * | |
634 | * Remember, though, this controller can't handle non-wMaxPacketSize | |
635 | * aligned transfers on the OUT direction, so we queue a request for | |
636 | * wMaxPacketSize instead. | |
637 | */ | |
638 | dep = dwc->eps[0]; | |
639 | dwc->ep0_usb_req.dep = dep; | |
640 | dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; | |
641 | dwc->ep0_usb_req.request.buf = dwc->setup_buf; | |
642 | dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; | |
643 | ||
644 | return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); | |
645 | } | |
646 | ||
c12a0d86 FB |
647 | static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) |
648 | { | |
649 | u16 wLength; | |
650 | u16 wValue; | |
651 | u16 wIndex; | |
652 | ||
653 | wValue = le16_to_cpu(ctrl->wValue); | |
654 | wLength = le16_to_cpu(ctrl->wLength); | |
655 | wIndex = le16_to_cpu(ctrl->wIndex); | |
656 | ||
657 | if (wIndex || wLength) | |
658 | return -EINVAL; | |
659 | ||
660 | /* | |
661 | * REVISIT It's unclear from Databook what to do with this | |
662 | * value. For now, just cache it. | |
663 | */ | |
664 | dwc->isoch_delay = wValue; | |
665 | ||
666 | return 0; | |
667 | } | |
668 | ||
72246da4 FB |
669 | static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) |
670 | { | |
671 | int ret; | |
672 | ||
673 | switch (ctrl->bRequest) { | |
674 | case USB_REQ_GET_STATUS: | |
675 | dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n"); | |
676 | ret = dwc3_ep0_handle_status(dwc, ctrl); | |
677 | break; | |
678 | case USB_REQ_CLEAR_FEATURE: | |
679 | dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n"); | |
680 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); | |
681 | break; | |
682 | case USB_REQ_SET_FEATURE: | |
683 | dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n"); | |
684 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); | |
685 | break; | |
686 | case USB_REQ_SET_ADDRESS: | |
687 | dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n"); | |
688 | ret = dwc3_ep0_set_address(dwc, ctrl); | |
689 | break; | |
690 | case USB_REQ_SET_CONFIGURATION: | |
691 | dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n"); | |
692 | ret = dwc3_ep0_set_config(dwc, ctrl); | |
693 | break; | |
865e09e7 FB |
694 | case USB_REQ_SET_SEL: |
695 | dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n"); | |
696 | ret = dwc3_ep0_set_sel(dwc, ctrl); | |
697 | break; | |
c12a0d86 FB |
698 | case USB_REQ_SET_ISOCH_DELAY: |
699 | dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n"); | |
700 | ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); | |
701 | break; | |
72246da4 FB |
702 | default: |
703 | dev_vdbg(dwc->dev, "Forwarding to gadget driver\n"); | |
704 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
705 | break; | |
706 | }; | |
707 | ||
708 | return ret; | |
709 | } | |
710 | ||
711 | static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, | |
712 | const struct dwc3_event_depevt *event) | |
713 | { | |
714 | struct usb_ctrlrequest *ctrl = dwc->ctrl_req; | |
ef21ede6 | 715 | int ret = -EINVAL; |
72246da4 FB |
716 | u32 len; |
717 | ||
718 | if (!dwc->gadget_driver) | |
ef21ede6 | 719 | goto out; |
72246da4 FB |
720 | |
721 | len = le16_to_cpu(ctrl->wLength); | |
1ddcb218 | 722 | if (!len) { |
d95b09b9 FB |
723 | dwc->three_stage_setup = false; |
724 | dwc->ep0_expect_in = false; | |
1ddcb218 FB |
725 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
726 | } else { | |
d95b09b9 FB |
727 | dwc->three_stage_setup = true; |
728 | dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); | |
1ddcb218 FB |
729 | dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; |
730 | } | |
72246da4 FB |
731 | |
732 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) | |
733 | ret = dwc3_ep0_std_request(dwc, ctrl); | |
734 | else | |
735 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
736 | ||
5bdb1dcc SAS |
737 | if (ret == USB_GADGET_DELAYED_STATUS) |
738 | dwc->delayed_status = true; | |
739 | ||
ef21ede6 FB |
740 | out: |
741 | if (ret < 0) | |
742 | dwc3_ep0_stall_and_restart(dwc); | |
72246da4 FB |
743 | } |
744 | ||
745 | static void dwc3_ep0_complete_data(struct dwc3 *dwc, | |
746 | const struct dwc3_event_depevt *event) | |
747 | { | |
748 | struct dwc3_request *r = NULL; | |
749 | struct usb_request *ur; | |
f6bafc6a | 750 | struct dwc3_trb *trb; |
c2da2ff0 | 751 | struct dwc3_ep *ep0; |
c611ccb4 | 752 | u32 transferred; |
fca8892a | 753 | u32 status; |
f6bafc6a | 754 | u32 length; |
72246da4 FB |
755 | u8 epnum; |
756 | ||
757 | epnum = event->endpoint_number; | |
c2da2ff0 | 758 | ep0 = dwc->eps[0]; |
72246da4 | 759 | |
1ddcb218 FB |
760 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
761 | ||
c2da2ff0 | 762 | r = next_request(&ep0->request_list); |
8ee6270c | 763 | ur = &r->request; |
72246da4 | 764 | |
f6bafc6a | 765 | trb = dwc->ep0_trb; |
fca8892a FB |
766 | |
767 | status = DWC3_TRB_SIZE_TRBSTS(trb->size); | |
768 | if (status == DWC3_TRBSTS_SETUP_PENDING) { | |
769 | dev_dbg(dwc->dev, "Setup Pending received\n"); | |
770 | ||
771 | if (r) | |
772 | dwc3_gadget_giveback(ep0, r, -ECONNRESET); | |
773 | ||
774 | return; | |
775 | } | |
776 | ||
f6bafc6a | 777 | length = trb->size & DWC3_TRB_SIZE_MASK; |
72246da4 | 778 | |
a6829706 | 779 | if (dwc->ep0_bounced) { |
566ccdda MS |
780 | unsigned transfer_size = ur->length; |
781 | unsigned maxp = ep0->endpoint.maxpacket; | |
782 | ||
783 | transfer_size += (maxp - (transfer_size % maxp)); | |
c7fcdeb2 | 784 | transferred = min_t(u32, ur->length, |
566ccdda | 785 | transfer_size - length); |
a6829706 FB |
786 | memcpy(ur->buf, dwc->ep0_bounce, transferred); |
787 | dwc->ep0_bounced = false; | |
788 | } else { | |
f6bafc6a | 789 | transferred = ur->length - length; |
a6829706 | 790 | } |
72246da4 | 791 | |
cd423dd3 FB |
792 | ur->actual += transferred; |
793 | ||
72246da4 FB |
794 | if ((epnum & 1) && ur->actual < ur->length) { |
795 | /* for some reason we did not get everything out */ | |
796 | ||
797 | dwc3_ep0_stall_and_restart(dwc); | |
72246da4 FB |
798 | } else { |
799 | /* | |
800 | * handle the case where we have to send a zero packet. This | |
801 | * seems to be case when req.length > maxpacket. Could it be? | |
802 | */ | |
72246da4 | 803 | if (r) |
c2da2ff0 | 804 | dwc3_gadget_giveback(ep0, r, 0); |
72246da4 FB |
805 | } |
806 | } | |
807 | ||
85a78101 | 808 | static void dwc3_ep0_complete_status(struct dwc3 *dwc, |
72246da4 FB |
809 | const struct dwc3_event_depevt *event) |
810 | { | |
811 | struct dwc3_request *r; | |
812 | struct dwc3_ep *dep; | |
fca8892a FB |
813 | struct dwc3_trb *trb; |
814 | u32 status; | |
72246da4 | 815 | |
c7fcdeb2 | 816 | dep = dwc->eps[0]; |
fca8892a | 817 | trb = dwc->ep0_trb; |
72246da4 FB |
818 | |
819 | if (!list_empty(&dep->request_list)) { | |
820 | r = next_request(&dep->request_list); | |
821 | ||
822 | dwc3_gadget_giveback(dep, r, 0); | |
823 | } | |
824 | ||
3b637367 GC |
825 | if (dwc->test_mode) { |
826 | int ret; | |
827 | ||
828 | ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); | |
829 | if (ret < 0) { | |
830 | dev_dbg(dwc->dev, "Invalid Test #%d\n", | |
831 | dwc->test_mode_nr); | |
832 | dwc3_ep0_stall_and_restart(dwc); | |
5c81abab | 833 | return; |
3b637367 GC |
834 | } |
835 | } | |
836 | ||
fca8892a FB |
837 | status = DWC3_TRB_SIZE_TRBSTS(trb->size); |
838 | if (status == DWC3_TRBSTS_SETUP_PENDING) | |
839 | dev_dbg(dwc->dev, "Setup Pending received\n"); | |
840 | ||
c7fcdeb2 | 841 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
842 | dwc3_ep0_out_start(dwc); |
843 | } | |
844 | ||
845 | static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, | |
846 | const struct dwc3_event_depevt *event) | |
847 | { | |
c7fcdeb2 FB |
848 | struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; |
849 | ||
850 | dep->flags &= ~DWC3_EP_BUSY; | |
b4996a86 | 851 | dep->resource_index = 0; |
df62df56 | 852 | dwc->setup_packet_pending = false; |
c7fcdeb2 | 853 | |
72246da4 | 854 | switch (dwc->ep0state) { |
c7fcdeb2 FB |
855 | case EP0_SETUP_PHASE: |
856 | dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n"); | |
72246da4 FB |
857 | dwc3_ep0_inspect_setup(dwc, event); |
858 | break; | |
859 | ||
c7fcdeb2 FB |
860 | case EP0_DATA_PHASE: |
861 | dev_vdbg(dwc->dev, "Data Phase\n"); | |
72246da4 FB |
862 | dwc3_ep0_complete_data(dwc, event); |
863 | break; | |
864 | ||
c7fcdeb2 FB |
865 | case EP0_STATUS_PHASE: |
866 | dev_vdbg(dwc->dev, "Status Phase\n"); | |
85a78101 | 867 | dwc3_ep0_complete_status(dwc, event); |
72246da4 | 868 | break; |
c7fcdeb2 FB |
869 | default: |
870 | WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); | |
871 | } | |
872 | } | |
72246da4 | 873 | |
a0807881 FB |
874 | static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, |
875 | struct dwc3_ep *dep, struct dwc3_request *req) | |
c7fcdeb2 | 876 | { |
c7fcdeb2 FB |
877 | int ret; |
878 | ||
a0807881 | 879 | req->direction = !!dep->number; |
c7fcdeb2 | 880 | |
c7fcdeb2 | 881 | if (req->request.length == 0) { |
a0807881 | 882 | ret = dwc3_ep0_start_trans(dwc, dep->number, |
c7fcdeb2 FB |
883 | dwc->ctrl_req_addr, 0, |
884 | DWC3_TRBCTL_CONTROL_DATA); | |
c74c6d4a | 885 | } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) |
a0807881 FB |
886 | && (dep->number == 0)) { |
887 | u32 transfer_size; | |
888 | ||
0fc9a1be | 889 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
a0807881 | 890 | dep->number); |
0fc9a1be FB |
891 | if (ret) { |
892 | dev_dbg(dwc->dev, "failed to map request\n"); | |
893 | return; | |
894 | } | |
c7fcdeb2 | 895 | |
4552a0ca | 896 | WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE); |
c7fcdeb2 | 897 | |
a0807881 FB |
898 | transfer_size = roundup(req->request.length, |
899 | (u32) dep->endpoint.maxpacket); | |
900 | ||
c7fcdeb2 FB |
901 | dwc->ep0_bounced = true; |
902 | ||
903 | /* | |
4552a0ca FB |
904 | * REVISIT in case request length is bigger than |
905 | * DWC3_EP0_BOUNCE_SIZE we will need two chained | |
906 | * TRBs to handle the transfer. | |
c7fcdeb2 | 907 | */ |
a0807881 FB |
908 | ret = dwc3_ep0_start_trans(dwc, dep->number, |
909 | dwc->ep0_bounce_addr, transfer_size, | |
c7fcdeb2 FB |
910 | DWC3_TRBCTL_CONTROL_DATA); |
911 | } else { | |
0fc9a1be | 912 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
a0807881 | 913 | dep->number); |
0fc9a1be FB |
914 | if (ret) { |
915 | dev_dbg(dwc->dev, "failed to map request\n"); | |
916 | return; | |
917 | } | |
c7fcdeb2 | 918 | |
a0807881 FB |
919 | ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma, |
920 | req->request.length, DWC3_TRBCTL_CONTROL_DATA); | |
c7fcdeb2 FB |
921 | } |
922 | ||
923 | WARN_ON(ret < 0); | |
72246da4 FB |
924 | } |
925 | ||
f0f2b2a2 | 926 | static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) |
72246da4 | 927 | { |
f0f2b2a2 | 928 | struct dwc3 *dwc = dep->dwc; |
c7fcdeb2 | 929 | u32 type; |
72246da4 | 930 | |
c7fcdeb2 FB |
931 | type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 |
932 | : DWC3_TRBCTL_CONTROL_STATUS2; | |
933 | ||
f0f2b2a2 | 934 | return dwc3_ep0_start_trans(dwc, dep->number, |
c7fcdeb2 | 935 | dwc->ctrl_req_addr, 0, type); |
f0f2b2a2 | 936 | } |
c7fcdeb2 | 937 | |
788a23f4 | 938 | static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) |
f0f2b2a2 | 939 | { |
457e84b6 FB |
940 | if (dwc->resize_fifos) { |
941 | dev_dbg(dwc->dev, "starting to resize fifos\n"); | |
942 | dwc3_gadget_resize_tx_fifos(dwc); | |
943 | dwc->resize_fifos = 0; | |
944 | } | |
945 | ||
f0f2b2a2 | 946 | WARN_ON(dwc3_ep0_start_control_status(dep)); |
c7fcdeb2 FB |
947 | } |
948 | ||
788a23f4 FB |
949 | static void dwc3_ep0_do_control_status(struct dwc3 *dwc, |
950 | const struct dwc3_event_depevt *event) | |
951 | { | |
952 | struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; | |
953 | ||
954 | __dwc3_ep0_do_control_status(dwc, dep); | |
955 | } | |
956 | ||
2e3db064 FB |
957 | static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) |
958 | { | |
959 | struct dwc3_gadget_ep_cmd_params params; | |
960 | u32 cmd; | |
961 | int ret; | |
962 | ||
963 | if (!dep->resource_index) | |
964 | return; | |
965 | ||
966 | cmd = DWC3_DEPCMD_ENDTRANSFER; | |
967 | cmd |= DWC3_DEPCMD_CMDIOC; | |
968 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); | |
969 | memset(¶ms, 0, sizeof(params)); | |
970 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
971 | WARN_ON_ONCE(ret); | |
972 | dep->resource_index = 0; | |
973 | } | |
974 | ||
c7fcdeb2 FB |
975 | static void dwc3_ep0_xfernotready(struct dwc3 *dwc, |
976 | const struct dwc3_event_depevt *event) | |
977 | { | |
df62df56 FB |
978 | dwc->setup_packet_pending = true; |
979 | ||
c7fcdeb2 | 980 | switch (event->status) { |
c7fcdeb2 FB |
981 | case DEPEVT_STATUS_CONTROL_DATA: |
982 | dev_vdbg(dwc->dev, "Control Data\n"); | |
1ddcb218 | 983 | |
55f3fba6 | 984 | /* |
2e3db064 FB |
985 | * We already have a DATA transfer in the controller's cache, |
986 | * if we receive a XferNotReady(DATA) we will ignore it, unless | |
987 | * it's for the wrong direction. | |
55f3fba6 | 988 | * |
2e3db064 FB |
989 | * In that case, we must issue END_TRANSFER command to the Data |
990 | * Phase we already have started and issue SetStall on the | |
991 | * control endpoint. | |
55f3fba6 FB |
992 | */ |
993 | if (dwc->ep0_expect_in != event->endpoint_number) { | |
2e3db064 FB |
994 | struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; |
995 | ||
55f3fba6 | 996 | dev_vdbg(dwc->dev, "Wrong direction for Data phase\n"); |
2e3db064 | 997 | dwc3_ep0_end_control_data(dwc, dep); |
55f3fba6 FB |
998 | dwc3_ep0_stall_and_restart(dwc); |
999 | return; | |
1000 | } | |
1001 | ||
c7fcdeb2 | 1002 | break; |
1ddcb218 | 1003 | |
c7fcdeb2 | 1004 | case DEPEVT_STATUS_CONTROL_STATUS: |
77fa6df8 FB |
1005 | if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) |
1006 | return; | |
1007 | ||
c7fcdeb2 | 1008 | dev_vdbg(dwc->dev, "Control Status\n"); |
1ddcb218 | 1009 | |
f0f2b2a2 SAS |
1010 | dwc->ep0state = EP0_STATUS_PHASE; |
1011 | ||
5bdb1dcc SAS |
1012 | if (dwc->delayed_status) { |
1013 | WARN_ON_ONCE(event->endpoint_number != 1); | |
1014 | dev_vdbg(dwc->dev, "Mass Storage delayed status\n"); | |
1015 | return; | |
1016 | } | |
1017 | ||
788a23f4 | 1018 | dwc3_ep0_do_control_status(dwc, event); |
72246da4 FB |
1019 | } |
1020 | } | |
1021 | ||
1022 | void dwc3_ep0_interrupt(struct dwc3 *dwc, | |
8becf270 | 1023 | const struct dwc3_event_depevt *event) |
72246da4 FB |
1024 | { |
1025 | u8 epnum = event->endpoint_number; | |
1026 | ||
1027 | dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n", | |
1028 | dwc3_ep_event_string(event->endpoint_event), | |
b147f357 | 1029 | epnum >> 1, (epnum & 1) ? "in" : "out", |
72246da4 FB |
1030 | dwc3_ep0_state_string(dwc->ep0state)); |
1031 | ||
1032 | switch (event->endpoint_event) { | |
1033 | case DWC3_DEPEVT_XFERCOMPLETE: | |
1034 | dwc3_ep0_xfer_complete(dwc, event); | |
1035 | break; | |
1036 | ||
1037 | case DWC3_DEPEVT_XFERNOTREADY: | |
1038 | dwc3_ep0_xfernotready(dwc, event); | |
1039 | break; | |
1040 | ||
1041 | case DWC3_DEPEVT_XFERINPROGRESS: | |
1042 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
1043 | case DWC3_DEPEVT_STREAMEVT: | |
1044 | case DWC3_DEPEVT_EPCMDCMPLT: | |
1045 | break; | |
1046 | } | |
1047 | } |