Commit | Line | Data |
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72246da4 FB |
1 | /** |
2 | * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/pm_runtime.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/list.h> | |
27 | #include <linux/dma-mapping.h> | |
28 | ||
29 | #include <linux/usb/ch9.h> | |
30 | #include <linux/usb/gadget.h> | |
5bdb1dcc | 31 | #include <linux/usb/composite.h> |
72246da4 FB |
32 | |
33 | #include "core.h" | |
80977dc9 | 34 | #include "debug.h" |
72246da4 FB |
35 | #include "gadget.h" |
36 | #include "io.h" | |
37 | ||
788a23f4 | 38 | static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); |
a0807881 FB |
39 | static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, |
40 | struct dwc3_ep *dep, struct dwc3_request *req); | |
5bdb1dcc | 41 | |
72246da4 FB |
42 | static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) |
43 | { | |
44 | switch (state) { | |
45 | case EP0_UNCONNECTED: | |
46 | return "Unconnected"; | |
c7fcdeb2 FB |
47 | case EP0_SETUP_PHASE: |
48 | return "Setup Phase"; | |
49 | case EP0_DATA_PHASE: | |
50 | return "Data Phase"; | |
51 | case EP0_STATUS_PHASE: | |
52 | return "Status Phase"; | |
72246da4 FB |
53 | default: |
54 | return "UNKNOWN"; | |
55 | } | |
56 | } | |
57 | ||
58 | static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, | |
c7fcdeb2 | 59 | u32 len, u32 type) |
72246da4 FB |
60 | { |
61 | struct dwc3_gadget_ep_cmd_params params; | |
f6bafc6a | 62 | struct dwc3_trb *trb; |
72246da4 FB |
63 | struct dwc3_ep *dep; |
64 | ||
65 | int ret; | |
66 | ||
67 | dep = dwc->eps[epnum]; | |
c7fcdeb2 | 68 | if (dep->flags & DWC3_EP_BUSY) { |
2c4cbe6e | 69 | dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name); |
c7fcdeb2 FB |
70 | return 0; |
71 | } | |
72246da4 | 72 | |
f6bafc6a | 73 | trb = dwc->ep0_trb; |
72246da4 | 74 | |
f6bafc6a FB |
75 | trb->bpl = lower_32_bits(buf_dma); |
76 | trb->bph = upper_32_bits(buf_dma); | |
77 | trb->size = len; | |
78 | trb->ctrl = type; | |
72246da4 | 79 | |
f6bafc6a FB |
80 | trb->ctrl |= (DWC3_TRB_CTRL_HWO |
81 | | DWC3_TRB_CTRL_LST | |
82 | | DWC3_TRB_CTRL_IOC | |
83 | | DWC3_TRB_CTRL_ISP_IMI); | |
72246da4 FB |
84 | |
85 | memset(¶ms, 0, sizeof(params)); | |
dc1c70a7 FB |
86 | params.param0 = upper_32_bits(dwc->ep0_trb_addr); |
87 | params.param1 = lower_32_bits(dwc->ep0_trb_addr); | |
72246da4 FB |
88 | |
89 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
90 | DWC3_DEPCMD_STARTTRANSFER, ¶ms); | |
91 | if (ret < 0) { | |
2c4cbe6e FB |
92 | dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed", |
93 | dep->name); | |
72246da4 FB |
94 | return ret; |
95 | } | |
96 | ||
c7fcdeb2 | 97 | dep->flags |= DWC3_EP_BUSY; |
b4996a86 | 98 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, |
72246da4 FB |
99 | dep->number); |
100 | ||
1ddcb218 FB |
101 | dwc->ep0_next_event = DWC3_EP0_COMPLETE; |
102 | ||
72246da4 FB |
103 | return 0; |
104 | } | |
105 | ||
106 | static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, | |
107 | struct dwc3_request *req) | |
108 | { | |
5bdb1dcc | 109 | struct dwc3 *dwc = dep->dwc; |
72246da4 FB |
110 | |
111 | req->request.actual = 0; | |
112 | req->request.status = -EINPROGRESS; | |
72246da4 FB |
113 | req->epnum = dep->number; |
114 | ||
115 | list_add_tail(&req->list, &dep->request_list); | |
a6829706 | 116 | |
c7fcdeb2 FB |
117 | /* |
118 | * Gadget driver might not be quick enough to queue a request | |
119 | * before we get a Transfer Not Ready event on this endpoint. | |
120 | * | |
121 | * In that case, we will set DWC3_EP_PENDING_REQUEST. When that | |
122 | * flag is set, it's telling us that as soon as Gadget queues the | |
123 | * required request, we should kick the transfer here because the | |
124 | * IRQ we were waiting for is long gone. | |
125 | */ | |
126 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
c7fcdeb2 | 127 | unsigned direction; |
c7fcdeb2 FB |
128 | |
129 | direction = !!(dep->flags & DWC3_EP0_DIR_IN); | |
130 | ||
68d8a781 FB |
131 | if (dwc->ep0state != EP0_DATA_PHASE) { |
132 | dev_WARN(dwc->dev, "Unexpected pending request\n"); | |
c7fcdeb2 FB |
133 | return 0; |
134 | } | |
72246da4 | 135 | |
a0807881 FB |
136 | __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); |
137 | ||
c7fcdeb2 FB |
138 | dep->flags &= ~(DWC3_EP_PENDING_REQUEST | |
139 | DWC3_EP0_DIR_IN); | |
d9b33c60 FB |
140 | |
141 | return 0; | |
142 | } | |
143 | ||
144 | /* | |
145 | * In case gadget driver asked us to delay the STATUS phase, | |
146 | * handle it here. | |
147 | */ | |
148 | if (dwc->delayed_status) { | |
7125d584 FB |
149 | unsigned direction; |
150 | ||
151 | direction = !dwc->ep0_expect_in; | |
5bdb1dcc | 152 | dwc->delayed_status = false; |
7c81290e | 153 | usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED); |
68d3e668 FB |
154 | |
155 | if (dwc->ep0state == EP0_STATUS_PHASE) | |
7125d584 | 156 | __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); |
68d3e668 | 157 | else |
2c4cbe6e FB |
158 | dwc3_trace(trace_dwc3_ep0, |
159 | "too early for delayed status"); | |
d9b33c60 FB |
160 | |
161 | return 0; | |
72246da4 FB |
162 | } |
163 | ||
fca8892a FB |
164 | /* |
165 | * Unfortunately we have uncovered a limitation wrt the Data Phase. | |
166 | * | |
167 | * Section 9.4 says we can wait for the XferNotReady(DATA) event to | |
168 | * come before issueing Start Transfer command, but if we do, we will | |
169 | * miss situations where the host starts another SETUP phase instead of | |
170 | * the DATA phase. Such cases happen at least on TD.7.6 of the Link | |
171 | * Layer Compliance Suite. | |
172 | * | |
173 | * The problem surfaces due to the fact that in case of back-to-back | |
174 | * SETUP packets there will be no XferNotReady(DATA) generated and we | |
175 | * will be stuck waiting for XferNotReady(DATA) forever. | |
176 | * | |
177 | * By looking at tables 9-13 and 9-14 of the Databook, we can see that | |
178 | * it tells us to start Data Phase right away. It also mentions that if | |
179 | * we receive a SETUP phase instead of the DATA phase, core will issue | |
180 | * XferComplete for the DATA phase, before actually initiating it in | |
181 | * the wire, with the TRB's status set to "SETUP_PENDING". Such status | |
182 | * can only be used to print some debugging logs, as the core expects | |
183 | * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, | |
184 | * just so it completes right away, without transferring anything and, | |
185 | * only then, we can go back to the SETUP phase. | |
186 | * | |
187 | * Because of this scenario, SNPS decided to change the programming | |
188 | * model of control transfers and support on-demand transfers only for | |
189 | * the STATUS phase. To fix the issue we have now, we will always wait | |
190 | * for gadget driver to queue the DATA phase's struct usb_request, then | |
191 | * start it right away. | |
192 | * | |
193 | * If we're actually in a 2-stage transfer, we will wait for | |
194 | * XferNotReady(STATUS). | |
195 | */ | |
196 | if (dwc->three_stage_setup) { | |
197 | unsigned direction; | |
198 | ||
199 | direction = dwc->ep0_expect_in; | |
200 | dwc->ep0state = EP0_DATA_PHASE; | |
201 | ||
202 | __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); | |
203 | ||
204 | dep->flags &= ~DWC3_EP0_DIR_IN; | |
205 | } | |
206 | ||
35f75696 | 207 | return 0; |
72246da4 FB |
208 | } |
209 | ||
210 | int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, | |
211 | gfp_t gfp_flags) | |
212 | { | |
213 | struct dwc3_request *req = to_dwc3_request(request); | |
214 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
215 | struct dwc3 *dwc = dep->dwc; | |
216 | ||
217 | unsigned long flags; | |
218 | ||
219 | int ret; | |
220 | ||
72246da4 | 221 | spin_lock_irqsave(&dwc->lock, flags); |
16e78db7 | 222 | if (!dep->endpoint.desc) { |
2c4cbe6e FB |
223 | dwc3_trace(trace_dwc3_ep0, |
224 | "trying to queue request %p to disabled %s", | |
72246da4 FB |
225 | request, dep->name); |
226 | ret = -ESHUTDOWN; | |
227 | goto out; | |
228 | } | |
229 | ||
230 | /* we share one TRB for ep0/1 */ | |
c2da2ff0 | 231 | if (!list_empty(&dep->request_list)) { |
72246da4 FB |
232 | ret = -EBUSY; |
233 | goto out; | |
234 | } | |
235 | ||
2c4cbe6e FB |
236 | dwc3_trace(trace_dwc3_ep0, |
237 | "queueing request %p to %s length %d state '%s'", | |
72246da4 FB |
238 | request, dep->name, request->length, |
239 | dwc3_ep0_state_string(dwc->ep0state)); | |
240 | ||
241 | ret = __dwc3_gadget_ep0_queue(dep, req); | |
242 | ||
243 | out: | |
244 | spin_unlock_irqrestore(&dwc->lock, flags); | |
245 | ||
246 | return ret; | |
247 | } | |
248 | ||
249 | static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) | |
250 | { | |
2dfe37d4 FB |
251 | struct dwc3_ep *dep; |
252 | ||
253 | /* reinitialize physical ep1 */ | |
254 | dep = dwc->eps[1]; | |
255 | dep->flags = DWC3_EP_ENABLED; | |
d742220b | 256 | |
72246da4 | 257 | /* stall is always issued on EP0 */ |
2dfe37d4 | 258 | dep = dwc->eps[0]; |
7a608559 | 259 | __dwc3_gadget_ep_set_halt(dep, 1, false); |
c2da2ff0 | 260 | dep->flags = DWC3_EP_ENABLED; |
5bdb1dcc | 261 | dwc->delayed_status = false; |
d742220b FB |
262 | |
263 | if (!list_empty(&dep->request_list)) { | |
264 | struct dwc3_request *req; | |
265 | ||
266 | req = next_request(&dep->request_list); | |
267 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
268 | } | |
269 | ||
c7fcdeb2 | 270 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
271 | dwc3_ep0_out_start(dwc); |
272 | } | |
273 | ||
33fb691b | 274 | int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) |
08f0d966 PA |
275 | { |
276 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
277 | struct dwc3 *dwc = dep->dwc; | |
278 | ||
279 | dwc3_ep0_stall_and_restart(dwc); | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
33fb691b FB |
284 | int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) |
285 | { | |
286 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
287 | struct dwc3 *dwc = dep->dwc; | |
288 | unsigned long flags; | |
289 | int ret; | |
290 | ||
291 | spin_lock_irqsave(&dwc->lock, flags); | |
292 | ret = __dwc3_gadget_ep0_set_halt(ep, value); | |
293 | spin_unlock_irqrestore(&dwc->lock, flags); | |
294 | ||
295 | return ret; | |
296 | } | |
297 | ||
72246da4 FB |
298 | void dwc3_ep0_out_start(struct dwc3 *dwc) |
299 | { | |
72246da4 FB |
300 | int ret; |
301 | ||
c7fcdeb2 FB |
302 | ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, |
303 | DWC3_TRBCTL_CONTROL_SETUP); | |
72246da4 FB |
304 | WARN_ON(ret < 0); |
305 | } | |
306 | ||
72246da4 FB |
307 | static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) |
308 | { | |
309 | struct dwc3_ep *dep; | |
310 | u32 windex = le16_to_cpu(wIndex_le); | |
311 | u32 epnum; | |
312 | ||
313 | epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; | |
314 | if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) | |
315 | epnum |= 1; | |
316 | ||
317 | dep = dwc->eps[epnum]; | |
318 | if (dep->flags & DWC3_EP_ENABLED) | |
319 | return dep; | |
320 | ||
321 | return NULL; | |
322 | } | |
323 | ||
8ee6270c | 324 | static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) |
72246da4 | 325 | { |
72246da4 | 326 | } |
72246da4 FB |
327 | /* |
328 | * ch 9.4.5 | |
329 | */ | |
25b8ff68 FB |
330 | static int dwc3_ep0_handle_status(struct dwc3 *dwc, |
331 | struct usb_ctrlrequest *ctrl) | |
72246da4 FB |
332 | { |
333 | struct dwc3_ep *dep; | |
334 | u32 recip; | |
e6a3b5e2 | 335 | u32 reg; |
72246da4 FB |
336 | u16 usb_status = 0; |
337 | __le16 *response_pkt; | |
338 | ||
339 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
340 | switch (recip) { | |
341 | case USB_RECIP_DEVICE: | |
342 | /* | |
e6a3b5e2 | 343 | * LTM will be set once we know how to set this in HW. |
72246da4 FB |
344 | */ |
345 | usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED; | |
e6a3b5e2 SAS |
346 | |
347 | if (dwc->speed == DWC3_DSTS_SUPERSPEED) { | |
348 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
349 | if (reg & DWC3_DCTL_INITU1ENA) | |
350 | usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; | |
351 | if (reg & DWC3_DCTL_INITU2ENA) | |
352 | usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; | |
353 | } | |
354 | ||
72246da4 FB |
355 | break; |
356 | ||
357 | case USB_RECIP_INTERFACE: | |
358 | /* | |
359 | * Function Remote Wake Capable D0 | |
360 | * Function Remote Wakeup D1 | |
361 | */ | |
362 | break; | |
363 | ||
364 | case USB_RECIP_ENDPOINT: | |
365 | dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); | |
366 | if (!dep) | |
25b8ff68 | 367 | return -EINVAL; |
72246da4 FB |
368 | |
369 | if (dep->flags & DWC3_EP_STALL) | |
370 | usb_status = 1 << USB_ENDPOINT_HALT; | |
371 | break; | |
372 | default: | |
373 | return -EINVAL; | |
2b84f92b | 374 | } |
72246da4 FB |
375 | |
376 | response_pkt = (__le16 *) dwc->setup_buf; | |
377 | *response_pkt = cpu_to_le16(usb_status); | |
e2617796 FB |
378 | |
379 | dep = dwc->eps[0]; | |
380 | dwc->ep0_usb_req.dep = dep; | |
e0ce0b0a | 381 | dwc->ep0_usb_req.request.length = sizeof(*response_pkt); |
0fc9a1be | 382 | dwc->ep0_usb_req.request.buf = dwc->setup_buf; |
e0ce0b0a | 383 | dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; |
e2617796 FB |
384 | |
385 | return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); | |
72246da4 FB |
386 | } |
387 | ||
388 | static int dwc3_ep0_handle_feature(struct dwc3 *dwc, | |
389 | struct usb_ctrlrequest *ctrl, int set) | |
390 | { | |
391 | struct dwc3_ep *dep; | |
392 | u32 recip; | |
393 | u32 wValue; | |
394 | u32 wIndex; | |
e6a3b5e2 | 395 | u32 reg; |
72246da4 | 396 | int ret; |
fdba5aa5 | 397 | enum usb_device_state state; |
72246da4 FB |
398 | |
399 | wValue = le16_to_cpu(ctrl->wValue); | |
400 | wIndex = le16_to_cpu(ctrl->wIndex); | |
401 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
fdba5aa5 FB |
402 | state = dwc->gadget.state; |
403 | ||
72246da4 FB |
404 | switch (recip) { |
405 | case USB_RECIP_DEVICE: | |
406 | ||
e6a3b5e2 SAS |
407 | switch (wValue) { |
408 | case USB_DEVICE_REMOTE_WAKEUP: | |
409 | break; | |
72246da4 FB |
410 | /* |
411 | * 9.4.1 says only only for SS, in AddressState only for | |
412 | * default control pipe | |
413 | */ | |
72246da4 | 414 | case USB_DEVICE_U1_ENABLE: |
fdba5aa5 | 415 | if (state != USB_STATE_CONFIGURED) |
72246da4 FB |
416 | return -EINVAL; |
417 | if (dwc->speed != DWC3_DSTS_SUPERSPEED) | |
418 | return -EINVAL; | |
72246da4 | 419 | |
e6a3b5e2 SAS |
420 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
421 | if (set) | |
422 | reg |= DWC3_DCTL_INITU1ENA; | |
423 | else | |
424 | reg &= ~DWC3_DCTL_INITU1ENA; | |
425 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 426 | break; |
e6a3b5e2 | 427 | |
72246da4 | 428 | case USB_DEVICE_U2_ENABLE: |
fdba5aa5 | 429 | if (state != USB_STATE_CONFIGURED) |
e6a3b5e2 SAS |
430 | return -EINVAL; |
431 | if (dwc->speed != DWC3_DSTS_SUPERSPEED) | |
432 | return -EINVAL; | |
433 | ||
434 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
435 | if (set) | |
436 | reg |= DWC3_DCTL_INITU2ENA; | |
437 | else | |
438 | reg &= ~DWC3_DCTL_INITU2ENA; | |
439 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 440 | break; |
e6a3b5e2 | 441 | |
72246da4 | 442 | case USB_DEVICE_LTM_ENABLE: |
e6a3b5e2 | 443 | return -EINVAL; |
72246da4 FB |
444 | break; |
445 | ||
446 | case USB_DEVICE_TEST_MODE: | |
447 | if ((wIndex & 0xff) != 0) | |
448 | return -EINVAL; | |
449 | if (!set) | |
450 | return -EINVAL; | |
451 | ||
3b637367 GC |
452 | dwc->test_mode_nr = wIndex >> 8; |
453 | dwc->test_mode = true; | |
ecb07797 GC |
454 | break; |
455 | default: | |
456 | return -EINVAL; | |
72246da4 FB |
457 | } |
458 | break; | |
459 | ||
460 | case USB_RECIP_INTERFACE: | |
461 | switch (wValue) { | |
462 | case USB_INTRF_FUNC_SUSPEND: | |
463 | if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) | |
464 | /* XXX enable Low power suspend */ | |
465 | ; | |
466 | if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) | |
467 | /* XXX enable remote wakeup */ | |
468 | ; | |
469 | break; | |
470 | default: | |
471 | return -EINVAL; | |
472 | } | |
473 | break; | |
474 | ||
475 | case USB_RECIP_ENDPOINT: | |
476 | switch (wValue) { | |
477 | case USB_ENDPOINT_HALT: | |
1d046793 | 478 | dep = dwc3_wIndex_to_dep(dwc, wIndex); |
72246da4 FB |
479 | if (!dep) |
480 | return -EINVAL; | |
a535d81c AS |
481 | if (set == 0 && (dep->flags & DWC3_EP_WEDGE)) |
482 | break; | |
7a608559 | 483 | ret = __dwc3_gadget_ep_set_halt(dep, set, true); |
72246da4 FB |
484 | if (ret) |
485 | return -EINVAL; | |
486 | break; | |
487 | default: | |
488 | return -EINVAL; | |
489 | } | |
490 | break; | |
491 | ||
492 | default: | |
493 | return -EINVAL; | |
2b84f92b | 494 | } |
72246da4 | 495 | |
72246da4 FB |
496 | return 0; |
497 | } | |
498 | ||
499 | static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
500 | { | |
fdba5aa5 | 501 | enum usb_device_state state = dwc->gadget.state; |
72246da4 FB |
502 | u32 addr; |
503 | u32 reg; | |
504 | ||
505 | addr = le16_to_cpu(ctrl->wValue); | |
f96a6ec1 | 506 | if (addr > 127) { |
2c4cbe6e | 507 | dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr); |
72246da4 | 508 | return -EINVAL; |
f96a6ec1 FB |
509 | } |
510 | ||
fdba5aa5 | 511 | if (state == USB_STATE_CONFIGURED) { |
2c4cbe6e FB |
512 | dwc3_trace(trace_dwc3_ep0, |
513 | "trying to set address when configured"); | |
f96a6ec1 FB |
514 | return -EINVAL; |
515 | } | |
72246da4 | 516 | |
2646021e FB |
517 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
518 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
519 | reg |= DWC3_DCFG_DEVADDR(addr); | |
520 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 | 521 | |
fdba5aa5 | 522 | if (addr) |
14cd592f | 523 | usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS); |
fdba5aa5 | 524 | else |
14cd592f | 525 | usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); |
c7fcdeb2 | 526 | |
2646021e | 527 | return 0; |
72246da4 FB |
528 | } |
529 | ||
530 | static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
531 | { | |
532 | int ret; | |
533 | ||
534 | spin_unlock(&dwc->lock); | |
535 | ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); | |
536 | spin_lock(&dwc->lock); | |
537 | return ret; | |
538 | } | |
539 | ||
540 | static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
541 | { | |
fdba5aa5 | 542 | enum usb_device_state state = dwc->gadget.state; |
72246da4 FB |
543 | u32 cfg; |
544 | int ret; | |
e274a31e | 545 | u32 reg; |
72246da4 | 546 | |
b23c8439 | 547 | dwc->start_config_issued = false; |
72246da4 FB |
548 | cfg = le16_to_cpu(ctrl->wValue); |
549 | ||
fdba5aa5 FB |
550 | switch (state) { |
551 | case USB_STATE_DEFAULT: | |
72246da4 FB |
552 | return -EINVAL; |
553 | break; | |
554 | ||
fdba5aa5 | 555 | case USB_STATE_ADDRESS: |
72246da4 FB |
556 | ret = dwc3_ep0_delegate_req(dwc, ctrl); |
557 | /* if the cfg matches and the cfg is non zero */ | |
457e84b6 | 558 | if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { |
7c81290e FB |
559 | |
560 | /* | |
561 | * only change state if set_config has already | |
562 | * been processed. If gadget driver returns | |
563 | * USB_GADGET_DELAYED_STATUS, we will wait | |
564 | * to change the state on the next usb_ep_queue() | |
565 | */ | |
566 | if (ret == 0) | |
567 | usb_gadget_set_state(&dwc->gadget, | |
568 | USB_STATE_CONFIGURED); | |
14cd592f | 569 | |
e274a31e PA |
570 | /* |
571 | * Enable transition to U1/U2 state when | |
572 | * nothing is pending from application. | |
573 | */ | |
574 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
575 | reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); | |
576 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
577 | ||
457e84b6 | 578 | dwc->resize_fifos = true; |
2c4cbe6e | 579 | dwc3_trace(trace_dwc3_ep0, "resize FIFOs flag SET"); |
457e84b6 | 580 | } |
72246da4 FB |
581 | break; |
582 | ||
fdba5aa5 | 583 | case USB_STATE_CONFIGURED: |
72246da4 | 584 | ret = dwc3_ep0_delegate_req(dwc, ctrl); |
7a42d835 | 585 | if (!cfg && !ret) |
14cd592f FB |
586 | usb_gadget_set_state(&dwc->gadget, |
587 | USB_STATE_ADDRESS); | |
72246da4 | 588 | break; |
5bdb1dcc SAS |
589 | default: |
590 | ret = -EINVAL; | |
72246da4 | 591 | } |
5bdb1dcc | 592 | return ret; |
72246da4 FB |
593 | } |
594 | ||
865e09e7 FB |
595 | static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) |
596 | { | |
597 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
598 | struct dwc3 *dwc = dep->dwc; | |
599 | ||
600 | u32 param = 0; | |
601 | u32 reg; | |
602 | ||
603 | struct timing { | |
604 | u8 u1sel; | |
605 | u8 u1pel; | |
606 | u16 u2sel; | |
607 | u16 u2pel; | |
608 | } __packed timing; | |
609 | ||
610 | int ret; | |
611 | ||
612 | memcpy(&timing, req->buf, sizeof(timing)); | |
613 | ||
614 | dwc->u1sel = timing.u1sel; | |
615 | dwc->u1pel = timing.u1pel; | |
c8cf7af4 FB |
616 | dwc->u2sel = le16_to_cpu(timing.u2sel); |
617 | dwc->u2pel = le16_to_cpu(timing.u2pel); | |
865e09e7 FB |
618 | |
619 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
620 | if (reg & DWC3_DCTL_INITU2ENA) | |
621 | param = dwc->u2pel; | |
622 | if (reg & DWC3_DCTL_INITU1ENA) | |
623 | param = dwc->u1pel; | |
624 | ||
625 | /* | |
626 | * According to Synopsys Databook, if parameter is | |
627 | * greater than 125, a value of zero should be | |
628 | * programmed in the register. | |
629 | */ | |
630 | if (param > 125) | |
631 | param = 0; | |
632 | ||
633 | /* now that we have the time, issue DGCMD Set Sel */ | |
634 | ret = dwc3_send_gadget_generic_command(dwc, | |
635 | DWC3_DGCMD_SET_PERIODIC_PAR, param); | |
636 | WARN_ON(ret < 0); | |
637 | } | |
638 | ||
639 | static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
640 | { | |
641 | struct dwc3_ep *dep; | |
fdba5aa5 | 642 | enum usb_device_state state = dwc->gadget.state; |
865e09e7 FB |
643 | u16 wLength; |
644 | u16 wValue; | |
645 | ||
fdba5aa5 | 646 | if (state == USB_STATE_DEFAULT) |
865e09e7 FB |
647 | return -EINVAL; |
648 | ||
649 | wValue = le16_to_cpu(ctrl->wValue); | |
650 | wLength = le16_to_cpu(ctrl->wLength); | |
651 | ||
652 | if (wLength != 6) { | |
653 | dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", | |
654 | wLength); | |
655 | return -EINVAL; | |
656 | } | |
657 | ||
658 | /* | |
659 | * To handle Set SEL we need to receive 6 bytes from Host. So let's | |
660 | * queue a usb_request for 6 bytes. | |
661 | * | |
662 | * Remember, though, this controller can't handle non-wMaxPacketSize | |
663 | * aligned transfers on the OUT direction, so we queue a request for | |
664 | * wMaxPacketSize instead. | |
665 | */ | |
666 | dep = dwc->eps[0]; | |
667 | dwc->ep0_usb_req.dep = dep; | |
668 | dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; | |
669 | dwc->ep0_usb_req.request.buf = dwc->setup_buf; | |
670 | dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; | |
671 | ||
672 | return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); | |
673 | } | |
674 | ||
c12a0d86 FB |
675 | static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) |
676 | { | |
677 | u16 wLength; | |
678 | u16 wValue; | |
679 | u16 wIndex; | |
680 | ||
681 | wValue = le16_to_cpu(ctrl->wValue); | |
682 | wLength = le16_to_cpu(ctrl->wLength); | |
683 | wIndex = le16_to_cpu(ctrl->wIndex); | |
684 | ||
685 | if (wIndex || wLength) | |
686 | return -EINVAL; | |
687 | ||
688 | /* | |
689 | * REVISIT It's unclear from Databook what to do with this | |
690 | * value. For now, just cache it. | |
691 | */ | |
692 | dwc->isoch_delay = wValue; | |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
72246da4 FB |
697 | static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) |
698 | { | |
699 | int ret; | |
700 | ||
701 | switch (ctrl->bRequest) { | |
702 | case USB_REQ_GET_STATUS: | |
2c4cbe6e | 703 | dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS\n"); |
72246da4 FB |
704 | ret = dwc3_ep0_handle_status(dwc, ctrl); |
705 | break; | |
706 | case USB_REQ_CLEAR_FEATURE: | |
2c4cbe6e | 707 | dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE\n"); |
72246da4 FB |
708 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); |
709 | break; | |
710 | case USB_REQ_SET_FEATURE: | |
2c4cbe6e | 711 | dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE\n"); |
72246da4 FB |
712 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); |
713 | break; | |
714 | case USB_REQ_SET_ADDRESS: | |
2c4cbe6e | 715 | dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS\n"); |
72246da4 FB |
716 | ret = dwc3_ep0_set_address(dwc, ctrl); |
717 | break; | |
718 | case USB_REQ_SET_CONFIGURATION: | |
2c4cbe6e | 719 | dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION\n"); |
72246da4 FB |
720 | ret = dwc3_ep0_set_config(dwc, ctrl); |
721 | break; | |
865e09e7 | 722 | case USB_REQ_SET_SEL: |
2c4cbe6e | 723 | dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL\n"); |
865e09e7 FB |
724 | ret = dwc3_ep0_set_sel(dwc, ctrl); |
725 | break; | |
c12a0d86 | 726 | case USB_REQ_SET_ISOCH_DELAY: |
2c4cbe6e | 727 | dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY\n"); |
c12a0d86 FB |
728 | ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); |
729 | break; | |
72246da4 | 730 | default: |
2c4cbe6e | 731 | dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver\n"); |
72246da4 FB |
732 | ret = dwc3_ep0_delegate_req(dwc, ctrl); |
733 | break; | |
2b84f92b | 734 | } |
72246da4 FB |
735 | |
736 | return ret; | |
737 | } | |
738 | ||
739 | static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, | |
740 | const struct dwc3_event_depevt *event) | |
741 | { | |
742 | struct usb_ctrlrequest *ctrl = dwc->ctrl_req; | |
ef21ede6 | 743 | int ret = -EINVAL; |
72246da4 FB |
744 | u32 len; |
745 | ||
746 | if (!dwc->gadget_driver) | |
ef21ede6 | 747 | goto out; |
72246da4 | 748 | |
2c4cbe6e FB |
749 | trace_dwc3_ctrl_req(ctrl); |
750 | ||
72246da4 | 751 | len = le16_to_cpu(ctrl->wLength); |
1ddcb218 | 752 | if (!len) { |
d95b09b9 FB |
753 | dwc->three_stage_setup = false; |
754 | dwc->ep0_expect_in = false; | |
1ddcb218 FB |
755 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
756 | } else { | |
d95b09b9 FB |
757 | dwc->three_stage_setup = true; |
758 | dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); | |
1ddcb218 FB |
759 | dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; |
760 | } | |
72246da4 FB |
761 | |
762 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) | |
763 | ret = dwc3_ep0_std_request(dwc, ctrl); | |
764 | else | |
765 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
766 | ||
5bdb1dcc SAS |
767 | if (ret == USB_GADGET_DELAYED_STATUS) |
768 | dwc->delayed_status = true; | |
769 | ||
ef21ede6 FB |
770 | out: |
771 | if (ret < 0) | |
772 | dwc3_ep0_stall_and_restart(dwc); | |
72246da4 FB |
773 | } |
774 | ||
775 | static void dwc3_ep0_complete_data(struct dwc3 *dwc, | |
776 | const struct dwc3_event_depevt *event) | |
777 | { | |
778 | struct dwc3_request *r = NULL; | |
779 | struct usb_request *ur; | |
f6bafc6a | 780 | struct dwc3_trb *trb; |
c2da2ff0 | 781 | struct dwc3_ep *ep0; |
c611ccb4 | 782 | u32 transferred; |
fca8892a | 783 | u32 status; |
f6bafc6a | 784 | u32 length; |
72246da4 FB |
785 | u8 epnum; |
786 | ||
787 | epnum = event->endpoint_number; | |
c2da2ff0 | 788 | ep0 = dwc->eps[0]; |
72246da4 | 789 | |
1ddcb218 FB |
790 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
791 | ||
f6bafc6a | 792 | trb = dwc->ep0_trb; |
fca8892a FB |
793 | |
794 | status = DWC3_TRB_SIZE_TRBSTS(trb->size); | |
795 | if (status == DWC3_TRBSTS_SETUP_PENDING) { | |
2c4cbe6e | 796 | dwc3_trace(trace_dwc3_ep0, "Setup Pending received"); |
fca8892a FB |
797 | |
798 | if (r) | |
799 | dwc3_gadget_giveback(ep0, r, -ECONNRESET); | |
800 | ||
801 | return; | |
802 | } | |
803 | ||
6856d30c FB |
804 | r = next_request(&ep0->request_list); |
805 | if (!r) | |
806 | return; | |
807 | ||
808 | ur = &r->request; | |
809 | ||
f6bafc6a | 810 | length = trb->size & DWC3_TRB_SIZE_MASK; |
72246da4 | 811 | |
a6829706 | 812 | if (dwc->ep0_bounced) { |
566ccdda MS |
813 | unsigned transfer_size = ur->length; |
814 | unsigned maxp = ep0->endpoint.maxpacket; | |
815 | ||
816 | transfer_size += (maxp - (transfer_size % maxp)); | |
c7fcdeb2 | 817 | transferred = min_t(u32, ur->length, |
566ccdda | 818 | transfer_size - length); |
a6829706 | 819 | memcpy(ur->buf, dwc->ep0_bounce, transferred); |
a6829706 | 820 | } else { |
f6bafc6a | 821 | transferred = ur->length - length; |
a6829706 | 822 | } |
72246da4 | 823 | |
cd423dd3 FB |
824 | ur->actual += transferred; |
825 | ||
72246da4 FB |
826 | if ((epnum & 1) && ur->actual < ur->length) { |
827 | /* for some reason we did not get everything out */ | |
828 | ||
829 | dwc3_ep0_stall_and_restart(dwc); | |
72246da4 | 830 | } else { |
36f84ffb FB |
831 | dwc3_gadget_giveback(ep0, r, 0); |
832 | ||
833 | if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) && | |
834 | ur->length && ur->zero) { | |
835 | int ret; | |
836 | ||
837 | dwc->ep0_next_event = DWC3_EP0_COMPLETE; | |
838 | ||
839 | ret = dwc3_ep0_start_trans(dwc, epnum, | |
840 | dwc->ctrl_req_addr, 0, | |
841 | DWC3_TRBCTL_CONTROL_DATA); | |
842 | WARN_ON(ret < 0); | |
843 | } | |
72246da4 FB |
844 | } |
845 | } | |
846 | ||
85a78101 | 847 | static void dwc3_ep0_complete_status(struct dwc3 *dwc, |
72246da4 FB |
848 | const struct dwc3_event_depevt *event) |
849 | { | |
850 | struct dwc3_request *r; | |
851 | struct dwc3_ep *dep; | |
fca8892a FB |
852 | struct dwc3_trb *trb; |
853 | u32 status; | |
72246da4 | 854 | |
c7fcdeb2 | 855 | dep = dwc->eps[0]; |
fca8892a | 856 | trb = dwc->ep0_trb; |
72246da4 FB |
857 | |
858 | if (!list_empty(&dep->request_list)) { | |
859 | r = next_request(&dep->request_list); | |
860 | ||
861 | dwc3_gadget_giveback(dep, r, 0); | |
862 | } | |
863 | ||
3b637367 GC |
864 | if (dwc->test_mode) { |
865 | int ret; | |
866 | ||
867 | ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); | |
868 | if (ret < 0) { | |
2c4cbe6e | 869 | dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d", |
3b637367 GC |
870 | dwc->test_mode_nr); |
871 | dwc3_ep0_stall_and_restart(dwc); | |
5c81abab | 872 | return; |
3b637367 GC |
873 | } |
874 | } | |
875 | ||
fca8892a FB |
876 | status = DWC3_TRB_SIZE_TRBSTS(trb->size); |
877 | if (status == DWC3_TRBSTS_SETUP_PENDING) | |
2c4cbe6e | 878 | dwc3_trace(trace_dwc3_ep0, "Setup Pending received\n"); |
fca8892a | 879 | |
c7fcdeb2 | 880 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
881 | dwc3_ep0_out_start(dwc); |
882 | } | |
883 | ||
884 | static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, | |
885 | const struct dwc3_event_depevt *event) | |
886 | { | |
c7fcdeb2 FB |
887 | struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; |
888 | ||
889 | dep->flags &= ~DWC3_EP_BUSY; | |
b4996a86 | 890 | dep->resource_index = 0; |
df62df56 | 891 | dwc->setup_packet_pending = false; |
c7fcdeb2 | 892 | |
72246da4 | 893 | switch (dwc->ep0state) { |
c7fcdeb2 | 894 | case EP0_SETUP_PHASE: |
2c4cbe6e | 895 | dwc3_trace(trace_dwc3_ep0, "Setup Phase"); |
72246da4 FB |
896 | dwc3_ep0_inspect_setup(dwc, event); |
897 | break; | |
898 | ||
c7fcdeb2 | 899 | case EP0_DATA_PHASE: |
2c4cbe6e | 900 | dwc3_trace(trace_dwc3_ep0, "Data Phase"); |
72246da4 FB |
901 | dwc3_ep0_complete_data(dwc, event); |
902 | break; | |
903 | ||
c7fcdeb2 | 904 | case EP0_STATUS_PHASE: |
2c4cbe6e | 905 | dwc3_trace(trace_dwc3_ep0, "Status Phase"); |
85a78101 | 906 | dwc3_ep0_complete_status(dwc, event); |
72246da4 | 907 | break; |
c7fcdeb2 FB |
908 | default: |
909 | WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); | |
910 | } | |
911 | } | |
72246da4 | 912 | |
a0807881 FB |
913 | static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, |
914 | struct dwc3_ep *dep, struct dwc3_request *req) | |
c7fcdeb2 | 915 | { |
c7fcdeb2 FB |
916 | int ret; |
917 | ||
a0807881 | 918 | req->direction = !!dep->number; |
c7fcdeb2 | 919 | |
c7fcdeb2 | 920 | if (req->request.length == 0) { |
a0807881 | 921 | ret = dwc3_ep0_start_trans(dwc, dep->number, |
c7fcdeb2 FB |
922 | dwc->ctrl_req_addr, 0, |
923 | DWC3_TRBCTL_CONTROL_DATA); | |
c74c6d4a | 924 | } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) |
a0807881 | 925 | && (dep->number == 0)) { |
c390b036 AM |
926 | u32 transfer_size; |
927 | u32 maxpacket; | |
a0807881 | 928 | |
0fc9a1be | 929 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
a0807881 | 930 | dep->number); |
0fc9a1be FB |
931 | if (ret) { |
932 | dev_dbg(dwc->dev, "failed to map request\n"); | |
933 | return; | |
934 | } | |
c7fcdeb2 | 935 | |
4552a0ca | 936 | WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE); |
c7fcdeb2 | 937 | |
c390b036 AM |
938 | maxpacket = dep->endpoint.maxpacket; |
939 | transfer_size = roundup(req->request.length, maxpacket); | |
a0807881 | 940 | |
c7fcdeb2 FB |
941 | dwc->ep0_bounced = true; |
942 | ||
943 | /* | |
4552a0ca FB |
944 | * REVISIT in case request length is bigger than |
945 | * DWC3_EP0_BOUNCE_SIZE we will need two chained | |
946 | * TRBs to handle the transfer. | |
c7fcdeb2 | 947 | */ |
a0807881 FB |
948 | ret = dwc3_ep0_start_trans(dwc, dep->number, |
949 | dwc->ep0_bounce_addr, transfer_size, | |
c7fcdeb2 FB |
950 | DWC3_TRBCTL_CONTROL_DATA); |
951 | } else { | |
0fc9a1be | 952 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
a0807881 | 953 | dep->number); |
0fc9a1be FB |
954 | if (ret) { |
955 | dev_dbg(dwc->dev, "failed to map request\n"); | |
956 | return; | |
957 | } | |
c7fcdeb2 | 958 | |
a0807881 FB |
959 | ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma, |
960 | req->request.length, DWC3_TRBCTL_CONTROL_DATA); | |
c7fcdeb2 FB |
961 | } |
962 | ||
963 | WARN_ON(ret < 0); | |
72246da4 FB |
964 | } |
965 | ||
f0f2b2a2 | 966 | static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) |
72246da4 | 967 | { |
f0f2b2a2 | 968 | struct dwc3 *dwc = dep->dwc; |
c7fcdeb2 | 969 | u32 type; |
72246da4 | 970 | |
c7fcdeb2 FB |
971 | type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 |
972 | : DWC3_TRBCTL_CONTROL_STATUS2; | |
973 | ||
f0f2b2a2 | 974 | return dwc3_ep0_start_trans(dwc, dep->number, |
c7fcdeb2 | 975 | dwc->ctrl_req_addr, 0, type); |
f0f2b2a2 | 976 | } |
c7fcdeb2 | 977 | |
788a23f4 | 978 | static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) |
f0f2b2a2 | 979 | { |
457e84b6 | 980 | if (dwc->resize_fifos) { |
2c4cbe6e | 981 | dwc3_trace(trace_dwc3_ep0, "Resizing FIFOs"); |
457e84b6 FB |
982 | dwc3_gadget_resize_tx_fifos(dwc); |
983 | dwc->resize_fifos = 0; | |
984 | } | |
985 | ||
f0f2b2a2 | 986 | WARN_ON(dwc3_ep0_start_control_status(dep)); |
c7fcdeb2 FB |
987 | } |
988 | ||
788a23f4 FB |
989 | static void dwc3_ep0_do_control_status(struct dwc3 *dwc, |
990 | const struct dwc3_event_depevt *event) | |
991 | { | |
992 | struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; | |
993 | ||
994 | __dwc3_ep0_do_control_status(dwc, dep); | |
995 | } | |
996 | ||
2e3db064 FB |
997 | static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) |
998 | { | |
999 | struct dwc3_gadget_ep_cmd_params params; | |
1000 | u32 cmd; | |
1001 | int ret; | |
1002 | ||
1003 | if (!dep->resource_index) | |
1004 | return; | |
1005 | ||
1006 | cmd = DWC3_DEPCMD_ENDTRANSFER; | |
1007 | cmd |= DWC3_DEPCMD_CMDIOC; | |
1008 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); | |
1009 | memset(¶ms, 0, sizeof(params)); | |
1010 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
1011 | WARN_ON_ONCE(ret); | |
1012 | dep->resource_index = 0; | |
1013 | } | |
1014 | ||
c7fcdeb2 FB |
1015 | static void dwc3_ep0_xfernotready(struct dwc3 *dwc, |
1016 | const struct dwc3_event_depevt *event) | |
1017 | { | |
df62df56 FB |
1018 | dwc->setup_packet_pending = true; |
1019 | ||
c7fcdeb2 | 1020 | switch (event->status) { |
c7fcdeb2 | 1021 | case DEPEVT_STATUS_CONTROL_DATA: |
2c4cbe6e | 1022 | dwc3_trace(trace_dwc3_ep0, "Control Data"); |
1ddcb218 | 1023 | |
55f3fba6 | 1024 | /* |
2e3db064 FB |
1025 | * We already have a DATA transfer in the controller's cache, |
1026 | * if we receive a XferNotReady(DATA) we will ignore it, unless | |
1027 | * it's for the wrong direction. | |
55f3fba6 | 1028 | * |
2e3db064 FB |
1029 | * In that case, we must issue END_TRANSFER command to the Data |
1030 | * Phase we already have started and issue SetStall on the | |
1031 | * control endpoint. | |
55f3fba6 FB |
1032 | */ |
1033 | if (dwc->ep0_expect_in != event->endpoint_number) { | |
2e3db064 FB |
1034 | struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; |
1035 | ||
2c4cbe6e FB |
1036 | dwc3_trace(trace_dwc3_ep0, |
1037 | "Wrong direction for Data phase"); | |
2e3db064 | 1038 | dwc3_ep0_end_control_data(dwc, dep); |
55f3fba6 FB |
1039 | dwc3_ep0_stall_and_restart(dwc); |
1040 | return; | |
1041 | } | |
1042 | ||
c7fcdeb2 | 1043 | break; |
1ddcb218 | 1044 | |
c7fcdeb2 | 1045 | case DEPEVT_STATUS_CONTROL_STATUS: |
77fa6df8 FB |
1046 | if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) |
1047 | return; | |
1048 | ||
2c4cbe6e | 1049 | dwc3_trace(trace_dwc3_ep0, "Control Status"); |
1ddcb218 | 1050 | |
f0f2b2a2 SAS |
1051 | dwc->ep0state = EP0_STATUS_PHASE; |
1052 | ||
5bdb1dcc SAS |
1053 | if (dwc->delayed_status) { |
1054 | WARN_ON_ONCE(event->endpoint_number != 1); | |
2c4cbe6e | 1055 | dwc3_trace(trace_dwc3_ep0, "Delayed Status"); |
5bdb1dcc SAS |
1056 | return; |
1057 | } | |
1058 | ||
788a23f4 | 1059 | dwc3_ep0_do_control_status(dwc, event); |
72246da4 FB |
1060 | } |
1061 | } | |
1062 | ||
1063 | void dwc3_ep0_interrupt(struct dwc3 *dwc, | |
8becf270 | 1064 | const struct dwc3_event_depevt *event) |
72246da4 FB |
1065 | { |
1066 | u8 epnum = event->endpoint_number; | |
1067 | ||
2c4cbe6e | 1068 | dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'", |
72246da4 | 1069 | dwc3_ep_event_string(event->endpoint_event), |
b147f357 | 1070 | epnum >> 1, (epnum & 1) ? "in" : "out", |
72246da4 FB |
1071 | dwc3_ep0_state_string(dwc->ep0state)); |
1072 | ||
1073 | switch (event->endpoint_event) { | |
1074 | case DWC3_DEPEVT_XFERCOMPLETE: | |
1075 | dwc3_ep0_xfer_complete(dwc, event); | |
1076 | break; | |
1077 | ||
1078 | case DWC3_DEPEVT_XFERNOTREADY: | |
1079 | dwc3_ep0_xfernotready(dwc, event); | |
1080 | break; | |
1081 | ||
1082 | case DWC3_DEPEVT_XFERINPROGRESS: | |
1083 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
1084 | case DWC3_DEPEVT_STREAMEVT: | |
1085 | case DWC3_DEPEVT_EPCMDCMPLT: | |
1086 | break; | |
1087 | } | |
1088 | } |