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72246da4 FB |
1 | /** |
2 | * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
9 | * Redistribution and use in source and binary forms, with or without | |
10 | * modification, are permitted provided that the following conditions | |
11 | * are met: | |
12 | * 1. Redistributions of source code must retain the above copyright | |
13 | * notice, this list of conditions, and the following disclaimer, | |
14 | * without modification. | |
15 | * 2. Redistributions in binary form must reproduce the above copyright | |
16 | * notice, this list of conditions and the following disclaimer in the | |
17 | * documentation and/or other materials provided with the distribution. | |
18 | * 3. The names of the above-listed copyright holders may not be used | |
19 | * to endorse or promote products derived from this software without | |
20 | * specific prior written permission. | |
21 | * | |
22 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
23 | * GNU General Public License ("GPL") version 2, as published by the Free | |
24 | * Software Foundation. | |
25 | * | |
26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
27 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
28 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
29 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
30 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
31 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
32 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
33 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
34 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
35 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
36 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
37 | */ | |
38 | ||
39 | #include <linux/kernel.h> | |
40 | #include <linux/slab.h> | |
41 | #include <linux/spinlock.h> | |
42 | #include <linux/platform_device.h> | |
43 | #include <linux/pm_runtime.h> | |
44 | #include <linux/interrupt.h> | |
45 | #include <linux/io.h> | |
46 | #include <linux/list.h> | |
47 | #include <linux/dma-mapping.h> | |
48 | ||
49 | #include <linux/usb/ch9.h> | |
50 | #include <linux/usb/gadget.h> | |
5bdb1dcc | 51 | #include <linux/usb/composite.h> |
72246da4 FB |
52 | |
53 | #include "core.h" | |
54 | #include "gadget.h" | |
55 | #include "io.h" | |
56 | ||
788a23f4 | 57 | static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); |
a0807881 FB |
58 | static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, |
59 | struct dwc3_ep *dep, struct dwc3_request *req); | |
5bdb1dcc | 60 | |
72246da4 FB |
61 | static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) |
62 | { | |
63 | switch (state) { | |
64 | case EP0_UNCONNECTED: | |
65 | return "Unconnected"; | |
c7fcdeb2 FB |
66 | case EP0_SETUP_PHASE: |
67 | return "Setup Phase"; | |
68 | case EP0_DATA_PHASE: | |
69 | return "Data Phase"; | |
70 | case EP0_STATUS_PHASE: | |
71 | return "Status Phase"; | |
72246da4 FB |
72 | default: |
73 | return "UNKNOWN"; | |
74 | } | |
75 | } | |
76 | ||
77 | static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, | |
c7fcdeb2 | 78 | u32 len, u32 type) |
72246da4 FB |
79 | { |
80 | struct dwc3_gadget_ep_cmd_params params; | |
f6bafc6a | 81 | struct dwc3_trb *trb; |
72246da4 FB |
82 | struct dwc3_ep *dep; |
83 | ||
84 | int ret; | |
85 | ||
86 | dep = dwc->eps[epnum]; | |
c7fcdeb2 FB |
87 | if (dep->flags & DWC3_EP_BUSY) { |
88 | dev_vdbg(dwc->dev, "%s: still busy\n", dep->name); | |
89 | return 0; | |
90 | } | |
72246da4 | 91 | |
f6bafc6a | 92 | trb = dwc->ep0_trb; |
72246da4 | 93 | |
f6bafc6a FB |
94 | trb->bpl = lower_32_bits(buf_dma); |
95 | trb->bph = upper_32_bits(buf_dma); | |
96 | trb->size = len; | |
97 | trb->ctrl = type; | |
72246da4 | 98 | |
f6bafc6a FB |
99 | trb->ctrl |= (DWC3_TRB_CTRL_HWO |
100 | | DWC3_TRB_CTRL_LST | |
101 | | DWC3_TRB_CTRL_IOC | |
102 | | DWC3_TRB_CTRL_ISP_IMI); | |
72246da4 FB |
103 | |
104 | memset(¶ms, 0, sizeof(params)); | |
dc1c70a7 FB |
105 | params.param0 = upper_32_bits(dwc->ep0_trb_addr); |
106 | params.param1 = lower_32_bits(dwc->ep0_trb_addr); | |
72246da4 FB |
107 | |
108 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
109 | DWC3_DEPCMD_STARTTRANSFER, ¶ms); | |
110 | if (ret < 0) { | |
111 | dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); | |
112 | return ret; | |
113 | } | |
114 | ||
c7fcdeb2 | 115 | dep->flags |= DWC3_EP_BUSY; |
b4996a86 | 116 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, |
72246da4 FB |
117 | dep->number); |
118 | ||
1ddcb218 FB |
119 | dwc->ep0_next_event = DWC3_EP0_COMPLETE; |
120 | ||
72246da4 FB |
121 | return 0; |
122 | } | |
123 | ||
124 | static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, | |
125 | struct dwc3_request *req) | |
126 | { | |
5bdb1dcc | 127 | struct dwc3 *dwc = dep->dwc; |
72246da4 FB |
128 | |
129 | req->request.actual = 0; | |
130 | req->request.status = -EINPROGRESS; | |
72246da4 FB |
131 | req->epnum = dep->number; |
132 | ||
133 | list_add_tail(&req->list, &dep->request_list); | |
a6829706 | 134 | |
c7fcdeb2 FB |
135 | /* |
136 | * Gadget driver might not be quick enough to queue a request | |
137 | * before we get a Transfer Not Ready event on this endpoint. | |
138 | * | |
139 | * In that case, we will set DWC3_EP_PENDING_REQUEST. When that | |
140 | * flag is set, it's telling us that as soon as Gadget queues the | |
141 | * required request, we should kick the transfer here because the | |
142 | * IRQ we were waiting for is long gone. | |
143 | */ | |
144 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
c7fcdeb2 | 145 | unsigned direction; |
c7fcdeb2 FB |
146 | |
147 | direction = !!(dep->flags & DWC3_EP0_DIR_IN); | |
148 | ||
68d8a781 FB |
149 | if (dwc->ep0state != EP0_DATA_PHASE) { |
150 | dev_WARN(dwc->dev, "Unexpected pending request\n"); | |
c7fcdeb2 FB |
151 | return 0; |
152 | } | |
72246da4 | 153 | |
a0807881 FB |
154 | __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); |
155 | ||
c7fcdeb2 FB |
156 | dep->flags &= ~(DWC3_EP_PENDING_REQUEST | |
157 | DWC3_EP0_DIR_IN); | |
d9b33c60 FB |
158 | |
159 | return 0; | |
160 | } | |
161 | ||
162 | /* | |
163 | * In case gadget driver asked us to delay the STATUS phase, | |
164 | * handle it here. | |
165 | */ | |
166 | if (dwc->delayed_status) { | |
7125d584 FB |
167 | unsigned direction; |
168 | ||
169 | direction = !dwc->ep0_expect_in; | |
5bdb1dcc | 170 | dwc->delayed_status = false; |
68d3e668 FB |
171 | |
172 | if (dwc->ep0state == EP0_STATUS_PHASE) | |
7125d584 | 173 | __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); |
68d3e668 FB |
174 | else |
175 | dev_dbg(dwc->dev, "too early for delayed status\n"); | |
d9b33c60 FB |
176 | |
177 | return 0; | |
72246da4 FB |
178 | } |
179 | ||
fca8892a FB |
180 | /* |
181 | * Unfortunately we have uncovered a limitation wrt the Data Phase. | |
182 | * | |
183 | * Section 9.4 says we can wait for the XferNotReady(DATA) event to | |
184 | * come before issueing Start Transfer command, but if we do, we will | |
185 | * miss situations where the host starts another SETUP phase instead of | |
186 | * the DATA phase. Such cases happen at least on TD.7.6 of the Link | |
187 | * Layer Compliance Suite. | |
188 | * | |
189 | * The problem surfaces due to the fact that in case of back-to-back | |
190 | * SETUP packets there will be no XferNotReady(DATA) generated and we | |
191 | * will be stuck waiting for XferNotReady(DATA) forever. | |
192 | * | |
193 | * By looking at tables 9-13 and 9-14 of the Databook, we can see that | |
194 | * it tells us to start Data Phase right away. It also mentions that if | |
195 | * we receive a SETUP phase instead of the DATA phase, core will issue | |
196 | * XferComplete for the DATA phase, before actually initiating it in | |
197 | * the wire, with the TRB's status set to "SETUP_PENDING". Such status | |
198 | * can only be used to print some debugging logs, as the core expects | |
199 | * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, | |
200 | * just so it completes right away, without transferring anything and, | |
201 | * only then, we can go back to the SETUP phase. | |
202 | * | |
203 | * Because of this scenario, SNPS decided to change the programming | |
204 | * model of control transfers and support on-demand transfers only for | |
205 | * the STATUS phase. To fix the issue we have now, we will always wait | |
206 | * for gadget driver to queue the DATA phase's struct usb_request, then | |
207 | * start it right away. | |
208 | * | |
209 | * If we're actually in a 2-stage transfer, we will wait for | |
210 | * XferNotReady(STATUS). | |
211 | */ | |
212 | if (dwc->three_stage_setup) { | |
213 | unsigned direction; | |
214 | ||
215 | direction = dwc->ep0_expect_in; | |
216 | dwc->ep0state = EP0_DATA_PHASE; | |
217 | ||
218 | __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); | |
219 | ||
220 | dep->flags &= ~DWC3_EP0_DIR_IN; | |
221 | } | |
222 | ||
35f75696 | 223 | return 0; |
72246da4 FB |
224 | } |
225 | ||
226 | int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, | |
227 | gfp_t gfp_flags) | |
228 | { | |
229 | struct dwc3_request *req = to_dwc3_request(request); | |
230 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
231 | struct dwc3 *dwc = dep->dwc; | |
232 | ||
233 | unsigned long flags; | |
234 | ||
235 | int ret; | |
236 | ||
72246da4 | 237 | spin_lock_irqsave(&dwc->lock, flags); |
16e78db7 | 238 | if (!dep->endpoint.desc) { |
72246da4 FB |
239 | dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", |
240 | request, dep->name); | |
241 | ret = -ESHUTDOWN; | |
242 | goto out; | |
243 | } | |
244 | ||
245 | /* we share one TRB for ep0/1 */ | |
c2da2ff0 | 246 | if (!list_empty(&dep->request_list)) { |
72246da4 FB |
247 | ret = -EBUSY; |
248 | goto out; | |
249 | } | |
250 | ||
251 | dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n", | |
252 | request, dep->name, request->length, | |
253 | dwc3_ep0_state_string(dwc->ep0state)); | |
254 | ||
255 | ret = __dwc3_gadget_ep0_queue(dep, req); | |
256 | ||
257 | out: | |
258 | spin_unlock_irqrestore(&dwc->lock, flags); | |
259 | ||
260 | return ret; | |
261 | } | |
262 | ||
263 | static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) | |
264 | { | |
2dfe37d4 FB |
265 | struct dwc3_ep *dep; |
266 | ||
267 | /* reinitialize physical ep1 */ | |
268 | dep = dwc->eps[1]; | |
269 | dep->flags = DWC3_EP_ENABLED; | |
d742220b | 270 | |
72246da4 | 271 | /* stall is always issued on EP0 */ |
2dfe37d4 | 272 | dep = dwc->eps[0]; |
c2da2ff0 SAS |
273 | __dwc3_gadget_ep_set_halt(dep, 1); |
274 | dep->flags = DWC3_EP_ENABLED; | |
5bdb1dcc | 275 | dwc->delayed_status = false; |
d742220b FB |
276 | |
277 | if (!list_empty(&dep->request_list)) { | |
278 | struct dwc3_request *req; | |
279 | ||
280 | req = next_request(&dep->request_list); | |
281 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
282 | } | |
283 | ||
c7fcdeb2 | 284 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
285 | dwc3_ep0_out_start(dwc); |
286 | } | |
287 | ||
08f0d966 PA |
288 | int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) |
289 | { | |
290 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
291 | struct dwc3 *dwc = dep->dwc; | |
292 | ||
293 | dwc3_ep0_stall_and_restart(dwc); | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
72246da4 FB |
298 | void dwc3_ep0_out_start(struct dwc3 *dwc) |
299 | { | |
72246da4 FB |
300 | int ret; |
301 | ||
c7fcdeb2 FB |
302 | ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, |
303 | DWC3_TRBCTL_CONTROL_SETUP); | |
72246da4 FB |
304 | WARN_ON(ret < 0); |
305 | } | |
306 | ||
72246da4 FB |
307 | static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) |
308 | { | |
309 | struct dwc3_ep *dep; | |
310 | u32 windex = le16_to_cpu(wIndex_le); | |
311 | u32 epnum; | |
312 | ||
313 | epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; | |
314 | if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) | |
315 | epnum |= 1; | |
316 | ||
317 | dep = dwc->eps[epnum]; | |
318 | if (dep->flags & DWC3_EP_ENABLED) | |
319 | return dep; | |
320 | ||
321 | return NULL; | |
322 | } | |
323 | ||
8ee6270c | 324 | static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) |
72246da4 | 325 | { |
72246da4 | 326 | } |
72246da4 FB |
327 | /* |
328 | * ch 9.4.5 | |
329 | */ | |
25b8ff68 FB |
330 | static int dwc3_ep0_handle_status(struct dwc3 *dwc, |
331 | struct usb_ctrlrequest *ctrl) | |
72246da4 FB |
332 | { |
333 | struct dwc3_ep *dep; | |
334 | u32 recip; | |
e6a3b5e2 | 335 | u32 reg; |
72246da4 FB |
336 | u16 usb_status = 0; |
337 | __le16 *response_pkt; | |
338 | ||
339 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
340 | switch (recip) { | |
341 | case USB_RECIP_DEVICE: | |
342 | /* | |
e6a3b5e2 | 343 | * LTM will be set once we know how to set this in HW. |
72246da4 FB |
344 | */ |
345 | usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED; | |
e6a3b5e2 SAS |
346 | |
347 | if (dwc->speed == DWC3_DSTS_SUPERSPEED) { | |
348 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
349 | if (reg & DWC3_DCTL_INITU1ENA) | |
350 | usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; | |
351 | if (reg & DWC3_DCTL_INITU2ENA) | |
352 | usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; | |
353 | } | |
354 | ||
72246da4 FB |
355 | break; |
356 | ||
357 | case USB_RECIP_INTERFACE: | |
358 | /* | |
359 | * Function Remote Wake Capable D0 | |
360 | * Function Remote Wakeup D1 | |
361 | */ | |
362 | break; | |
363 | ||
364 | case USB_RECIP_ENDPOINT: | |
365 | dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); | |
366 | if (!dep) | |
25b8ff68 | 367 | return -EINVAL; |
72246da4 FB |
368 | |
369 | if (dep->flags & DWC3_EP_STALL) | |
370 | usb_status = 1 << USB_ENDPOINT_HALT; | |
371 | break; | |
372 | default: | |
373 | return -EINVAL; | |
374 | }; | |
375 | ||
376 | response_pkt = (__le16 *) dwc->setup_buf; | |
377 | *response_pkt = cpu_to_le16(usb_status); | |
e2617796 FB |
378 | |
379 | dep = dwc->eps[0]; | |
380 | dwc->ep0_usb_req.dep = dep; | |
e0ce0b0a | 381 | dwc->ep0_usb_req.request.length = sizeof(*response_pkt); |
0fc9a1be | 382 | dwc->ep0_usb_req.request.buf = dwc->setup_buf; |
e0ce0b0a | 383 | dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; |
e2617796 FB |
384 | |
385 | return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); | |
72246da4 FB |
386 | } |
387 | ||
388 | static int dwc3_ep0_handle_feature(struct dwc3 *dwc, | |
389 | struct usb_ctrlrequest *ctrl, int set) | |
390 | { | |
391 | struct dwc3_ep *dep; | |
392 | u32 recip; | |
393 | u32 wValue; | |
394 | u32 wIndex; | |
e6a3b5e2 | 395 | u32 reg; |
72246da4 | 396 | int ret; |
72246da4 FB |
397 | |
398 | wValue = le16_to_cpu(ctrl->wValue); | |
399 | wIndex = le16_to_cpu(ctrl->wIndex); | |
400 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
401 | switch (recip) { | |
402 | case USB_RECIP_DEVICE: | |
403 | ||
e6a3b5e2 SAS |
404 | switch (wValue) { |
405 | case USB_DEVICE_REMOTE_WAKEUP: | |
406 | break; | |
72246da4 FB |
407 | /* |
408 | * 9.4.1 says only only for SS, in AddressState only for | |
409 | * default control pipe | |
410 | */ | |
72246da4 | 411 | case USB_DEVICE_U1_ENABLE: |
72246da4 FB |
412 | if (dwc->dev_state != DWC3_CONFIGURED_STATE) |
413 | return -EINVAL; | |
414 | if (dwc->speed != DWC3_DSTS_SUPERSPEED) | |
415 | return -EINVAL; | |
72246da4 | 416 | |
e6a3b5e2 SAS |
417 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
418 | if (set) | |
419 | reg |= DWC3_DCTL_INITU1ENA; | |
420 | else | |
421 | reg &= ~DWC3_DCTL_INITU1ENA; | |
422 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 423 | break; |
e6a3b5e2 | 424 | |
72246da4 | 425 | case USB_DEVICE_U2_ENABLE: |
e6a3b5e2 SAS |
426 | if (dwc->dev_state != DWC3_CONFIGURED_STATE) |
427 | return -EINVAL; | |
428 | if (dwc->speed != DWC3_DSTS_SUPERSPEED) | |
429 | return -EINVAL; | |
430 | ||
431 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
432 | if (set) | |
433 | reg |= DWC3_DCTL_INITU2ENA; | |
434 | else | |
435 | reg &= ~DWC3_DCTL_INITU2ENA; | |
436 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 437 | break; |
e6a3b5e2 | 438 | |
72246da4 | 439 | case USB_DEVICE_LTM_ENABLE: |
e6a3b5e2 | 440 | return -EINVAL; |
72246da4 FB |
441 | break; |
442 | ||
443 | case USB_DEVICE_TEST_MODE: | |
444 | if ((wIndex & 0xff) != 0) | |
445 | return -EINVAL; | |
446 | if (!set) | |
447 | return -EINVAL; | |
448 | ||
3b637367 GC |
449 | dwc->test_mode_nr = wIndex >> 8; |
450 | dwc->test_mode = true; | |
ecb07797 GC |
451 | break; |
452 | default: | |
453 | return -EINVAL; | |
72246da4 FB |
454 | } |
455 | break; | |
456 | ||
457 | case USB_RECIP_INTERFACE: | |
458 | switch (wValue) { | |
459 | case USB_INTRF_FUNC_SUSPEND: | |
460 | if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) | |
461 | /* XXX enable Low power suspend */ | |
462 | ; | |
463 | if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) | |
464 | /* XXX enable remote wakeup */ | |
465 | ; | |
466 | break; | |
467 | default: | |
468 | return -EINVAL; | |
469 | } | |
470 | break; | |
471 | ||
472 | case USB_RECIP_ENDPOINT: | |
473 | switch (wValue) { | |
474 | case USB_ENDPOINT_HALT: | |
1d046793 | 475 | dep = dwc3_wIndex_to_dep(dwc, wIndex); |
72246da4 FB |
476 | if (!dep) |
477 | return -EINVAL; | |
478 | ret = __dwc3_gadget_ep_set_halt(dep, set); | |
479 | if (ret) | |
480 | return -EINVAL; | |
481 | break; | |
482 | default: | |
483 | return -EINVAL; | |
484 | } | |
485 | break; | |
486 | ||
487 | default: | |
488 | return -EINVAL; | |
489 | }; | |
490 | ||
72246da4 FB |
491 | return 0; |
492 | } | |
493 | ||
494 | static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
495 | { | |
72246da4 FB |
496 | u32 addr; |
497 | u32 reg; | |
498 | ||
499 | addr = le16_to_cpu(ctrl->wValue); | |
f96a6ec1 FB |
500 | if (addr > 127) { |
501 | dev_dbg(dwc->dev, "invalid device address %d\n", addr); | |
72246da4 | 502 | return -EINVAL; |
f96a6ec1 FB |
503 | } |
504 | ||
505 | if (dwc->dev_state == DWC3_CONFIGURED_STATE) { | |
506 | dev_dbg(dwc->dev, "trying to set address when configured\n"); | |
507 | return -EINVAL; | |
508 | } | |
72246da4 | 509 | |
2646021e FB |
510 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
511 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
512 | reg |= DWC3_DCFG_DEVADDR(addr); | |
513 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 | 514 | |
14cd592f | 515 | if (addr) { |
2646021e | 516 | dwc->dev_state = DWC3_ADDRESS_STATE; |
14cd592f FB |
517 | usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS); |
518 | } else { | |
2646021e | 519 | dwc->dev_state = DWC3_DEFAULT_STATE; |
14cd592f FB |
520 | usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); |
521 | } | |
c7fcdeb2 | 522 | |
2646021e | 523 | return 0; |
72246da4 FB |
524 | } |
525 | ||
526 | static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
527 | { | |
528 | int ret; | |
529 | ||
530 | spin_unlock(&dwc->lock); | |
531 | ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); | |
532 | spin_lock(&dwc->lock); | |
533 | return ret; | |
534 | } | |
535 | ||
536 | static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
537 | { | |
538 | u32 cfg; | |
539 | int ret; | |
e274a31e | 540 | u32 reg; |
72246da4 | 541 | |
b23c8439 | 542 | dwc->start_config_issued = false; |
72246da4 FB |
543 | cfg = le16_to_cpu(ctrl->wValue); |
544 | ||
545 | switch (dwc->dev_state) { | |
546 | case DWC3_DEFAULT_STATE: | |
547 | return -EINVAL; | |
548 | break; | |
549 | ||
550 | case DWC3_ADDRESS_STATE: | |
551 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
552 | /* if the cfg matches and the cfg is non zero */ | |
457e84b6 | 553 | if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { |
72246da4 | 554 | dwc->dev_state = DWC3_CONFIGURED_STATE; |
14cd592f FB |
555 | usb_gadget_set_state(&dwc->gadget, |
556 | USB_STATE_CONFIGURED); | |
557 | ||
e274a31e PA |
558 | /* |
559 | * Enable transition to U1/U2 state when | |
560 | * nothing is pending from application. | |
561 | */ | |
562 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
563 | reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); | |
564 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
565 | ||
457e84b6 FB |
566 | dwc->resize_fifos = true; |
567 | dev_dbg(dwc->dev, "resize fifos flag SET\n"); | |
568 | } | |
72246da4 FB |
569 | break; |
570 | ||
571 | case DWC3_CONFIGURED_STATE: | |
572 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
14cd592f | 573 | if (!cfg) { |
72246da4 | 574 | dwc->dev_state = DWC3_ADDRESS_STATE; |
14cd592f FB |
575 | usb_gadget_set_state(&dwc->gadget, |
576 | USB_STATE_ADDRESS); | |
577 | } | |
72246da4 | 578 | break; |
5bdb1dcc SAS |
579 | default: |
580 | ret = -EINVAL; | |
72246da4 | 581 | } |
5bdb1dcc | 582 | return ret; |
72246da4 FB |
583 | } |
584 | ||
865e09e7 FB |
585 | static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) |
586 | { | |
587 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
588 | struct dwc3 *dwc = dep->dwc; | |
589 | ||
590 | u32 param = 0; | |
591 | u32 reg; | |
592 | ||
593 | struct timing { | |
594 | u8 u1sel; | |
595 | u8 u1pel; | |
596 | u16 u2sel; | |
597 | u16 u2pel; | |
598 | } __packed timing; | |
599 | ||
600 | int ret; | |
601 | ||
602 | memcpy(&timing, req->buf, sizeof(timing)); | |
603 | ||
604 | dwc->u1sel = timing.u1sel; | |
605 | dwc->u1pel = timing.u1pel; | |
c8cf7af4 FB |
606 | dwc->u2sel = le16_to_cpu(timing.u2sel); |
607 | dwc->u2pel = le16_to_cpu(timing.u2pel); | |
865e09e7 FB |
608 | |
609 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
610 | if (reg & DWC3_DCTL_INITU2ENA) | |
611 | param = dwc->u2pel; | |
612 | if (reg & DWC3_DCTL_INITU1ENA) | |
613 | param = dwc->u1pel; | |
614 | ||
615 | /* | |
616 | * According to Synopsys Databook, if parameter is | |
617 | * greater than 125, a value of zero should be | |
618 | * programmed in the register. | |
619 | */ | |
620 | if (param > 125) | |
621 | param = 0; | |
622 | ||
623 | /* now that we have the time, issue DGCMD Set Sel */ | |
624 | ret = dwc3_send_gadget_generic_command(dwc, | |
625 | DWC3_DGCMD_SET_PERIODIC_PAR, param); | |
626 | WARN_ON(ret < 0); | |
627 | } | |
628 | ||
629 | static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
630 | { | |
631 | struct dwc3_ep *dep; | |
632 | u16 wLength; | |
633 | u16 wValue; | |
634 | ||
635 | if (dwc->dev_state == DWC3_DEFAULT_STATE) | |
636 | return -EINVAL; | |
637 | ||
638 | wValue = le16_to_cpu(ctrl->wValue); | |
639 | wLength = le16_to_cpu(ctrl->wLength); | |
640 | ||
641 | if (wLength != 6) { | |
642 | dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", | |
643 | wLength); | |
644 | return -EINVAL; | |
645 | } | |
646 | ||
647 | /* | |
648 | * To handle Set SEL we need to receive 6 bytes from Host. So let's | |
649 | * queue a usb_request for 6 bytes. | |
650 | * | |
651 | * Remember, though, this controller can't handle non-wMaxPacketSize | |
652 | * aligned transfers on the OUT direction, so we queue a request for | |
653 | * wMaxPacketSize instead. | |
654 | */ | |
655 | dep = dwc->eps[0]; | |
656 | dwc->ep0_usb_req.dep = dep; | |
657 | dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; | |
658 | dwc->ep0_usb_req.request.buf = dwc->setup_buf; | |
659 | dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; | |
660 | ||
661 | return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); | |
662 | } | |
663 | ||
c12a0d86 FB |
664 | static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) |
665 | { | |
666 | u16 wLength; | |
667 | u16 wValue; | |
668 | u16 wIndex; | |
669 | ||
670 | wValue = le16_to_cpu(ctrl->wValue); | |
671 | wLength = le16_to_cpu(ctrl->wLength); | |
672 | wIndex = le16_to_cpu(ctrl->wIndex); | |
673 | ||
674 | if (wIndex || wLength) | |
675 | return -EINVAL; | |
676 | ||
677 | /* | |
678 | * REVISIT It's unclear from Databook what to do with this | |
679 | * value. For now, just cache it. | |
680 | */ | |
681 | dwc->isoch_delay = wValue; | |
682 | ||
683 | return 0; | |
684 | } | |
685 | ||
72246da4 FB |
686 | static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) |
687 | { | |
688 | int ret; | |
689 | ||
690 | switch (ctrl->bRequest) { | |
691 | case USB_REQ_GET_STATUS: | |
692 | dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n"); | |
693 | ret = dwc3_ep0_handle_status(dwc, ctrl); | |
694 | break; | |
695 | case USB_REQ_CLEAR_FEATURE: | |
696 | dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n"); | |
697 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); | |
698 | break; | |
699 | case USB_REQ_SET_FEATURE: | |
700 | dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n"); | |
701 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); | |
702 | break; | |
703 | case USB_REQ_SET_ADDRESS: | |
704 | dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n"); | |
705 | ret = dwc3_ep0_set_address(dwc, ctrl); | |
706 | break; | |
707 | case USB_REQ_SET_CONFIGURATION: | |
708 | dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n"); | |
709 | ret = dwc3_ep0_set_config(dwc, ctrl); | |
710 | break; | |
865e09e7 FB |
711 | case USB_REQ_SET_SEL: |
712 | dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n"); | |
713 | ret = dwc3_ep0_set_sel(dwc, ctrl); | |
714 | break; | |
c12a0d86 FB |
715 | case USB_REQ_SET_ISOCH_DELAY: |
716 | dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n"); | |
717 | ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); | |
718 | break; | |
72246da4 FB |
719 | default: |
720 | dev_vdbg(dwc->dev, "Forwarding to gadget driver\n"); | |
721 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
722 | break; | |
723 | }; | |
724 | ||
725 | return ret; | |
726 | } | |
727 | ||
728 | static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, | |
729 | const struct dwc3_event_depevt *event) | |
730 | { | |
731 | struct usb_ctrlrequest *ctrl = dwc->ctrl_req; | |
ef21ede6 | 732 | int ret = -EINVAL; |
72246da4 FB |
733 | u32 len; |
734 | ||
735 | if (!dwc->gadget_driver) | |
ef21ede6 | 736 | goto out; |
72246da4 FB |
737 | |
738 | len = le16_to_cpu(ctrl->wLength); | |
1ddcb218 | 739 | if (!len) { |
d95b09b9 FB |
740 | dwc->three_stage_setup = false; |
741 | dwc->ep0_expect_in = false; | |
1ddcb218 FB |
742 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
743 | } else { | |
d95b09b9 FB |
744 | dwc->three_stage_setup = true; |
745 | dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); | |
1ddcb218 FB |
746 | dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; |
747 | } | |
72246da4 FB |
748 | |
749 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) | |
750 | ret = dwc3_ep0_std_request(dwc, ctrl); | |
751 | else | |
752 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
753 | ||
5bdb1dcc SAS |
754 | if (ret == USB_GADGET_DELAYED_STATUS) |
755 | dwc->delayed_status = true; | |
756 | ||
ef21ede6 FB |
757 | out: |
758 | if (ret < 0) | |
759 | dwc3_ep0_stall_and_restart(dwc); | |
72246da4 FB |
760 | } |
761 | ||
762 | static void dwc3_ep0_complete_data(struct dwc3 *dwc, | |
763 | const struct dwc3_event_depevt *event) | |
764 | { | |
765 | struct dwc3_request *r = NULL; | |
766 | struct usb_request *ur; | |
f6bafc6a | 767 | struct dwc3_trb *trb; |
c2da2ff0 | 768 | struct dwc3_ep *ep0; |
c611ccb4 | 769 | u32 transferred; |
fca8892a | 770 | u32 status; |
f6bafc6a | 771 | u32 length; |
72246da4 FB |
772 | u8 epnum; |
773 | ||
774 | epnum = event->endpoint_number; | |
c2da2ff0 | 775 | ep0 = dwc->eps[0]; |
72246da4 | 776 | |
1ddcb218 FB |
777 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
778 | ||
c2da2ff0 | 779 | r = next_request(&ep0->request_list); |
8ee6270c | 780 | ur = &r->request; |
72246da4 | 781 | |
f6bafc6a | 782 | trb = dwc->ep0_trb; |
fca8892a FB |
783 | |
784 | status = DWC3_TRB_SIZE_TRBSTS(trb->size); | |
785 | if (status == DWC3_TRBSTS_SETUP_PENDING) { | |
786 | dev_dbg(dwc->dev, "Setup Pending received\n"); | |
787 | ||
788 | if (r) | |
789 | dwc3_gadget_giveback(ep0, r, -ECONNRESET); | |
790 | ||
791 | return; | |
792 | } | |
793 | ||
f6bafc6a | 794 | length = trb->size & DWC3_TRB_SIZE_MASK; |
72246da4 | 795 | |
a6829706 | 796 | if (dwc->ep0_bounced) { |
566ccdda MS |
797 | unsigned transfer_size = ur->length; |
798 | unsigned maxp = ep0->endpoint.maxpacket; | |
799 | ||
800 | transfer_size += (maxp - (transfer_size % maxp)); | |
c7fcdeb2 | 801 | transferred = min_t(u32, ur->length, |
566ccdda | 802 | transfer_size - length); |
a6829706 | 803 | memcpy(ur->buf, dwc->ep0_bounce, transferred); |
a6829706 | 804 | } else { |
f6bafc6a | 805 | transferred = ur->length - length; |
a6829706 | 806 | } |
72246da4 | 807 | |
cd423dd3 FB |
808 | ur->actual += transferred; |
809 | ||
72246da4 FB |
810 | if ((epnum & 1) && ur->actual < ur->length) { |
811 | /* for some reason we did not get everything out */ | |
812 | ||
813 | dwc3_ep0_stall_and_restart(dwc); | |
72246da4 FB |
814 | } else { |
815 | /* | |
816 | * handle the case where we have to send a zero packet. This | |
817 | * seems to be case when req.length > maxpacket. Could it be? | |
818 | */ | |
72246da4 | 819 | if (r) |
c2da2ff0 | 820 | dwc3_gadget_giveback(ep0, r, 0); |
72246da4 FB |
821 | } |
822 | } | |
823 | ||
85a78101 | 824 | static void dwc3_ep0_complete_status(struct dwc3 *dwc, |
72246da4 FB |
825 | const struct dwc3_event_depevt *event) |
826 | { | |
827 | struct dwc3_request *r; | |
828 | struct dwc3_ep *dep; | |
fca8892a FB |
829 | struct dwc3_trb *trb; |
830 | u32 status; | |
72246da4 | 831 | |
c7fcdeb2 | 832 | dep = dwc->eps[0]; |
fca8892a | 833 | trb = dwc->ep0_trb; |
72246da4 FB |
834 | |
835 | if (!list_empty(&dep->request_list)) { | |
836 | r = next_request(&dep->request_list); | |
837 | ||
838 | dwc3_gadget_giveback(dep, r, 0); | |
839 | } | |
840 | ||
3b637367 GC |
841 | if (dwc->test_mode) { |
842 | int ret; | |
843 | ||
844 | ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); | |
845 | if (ret < 0) { | |
846 | dev_dbg(dwc->dev, "Invalid Test #%d\n", | |
847 | dwc->test_mode_nr); | |
848 | dwc3_ep0_stall_and_restart(dwc); | |
5c81abab | 849 | return; |
3b637367 GC |
850 | } |
851 | } | |
852 | ||
fca8892a FB |
853 | status = DWC3_TRB_SIZE_TRBSTS(trb->size); |
854 | if (status == DWC3_TRBSTS_SETUP_PENDING) | |
855 | dev_dbg(dwc->dev, "Setup Pending received\n"); | |
856 | ||
c7fcdeb2 | 857 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
858 | dwc3_ep0_out_start(dwc); |
859 | } | |
860 | ||
861 | static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, | |
862 | const struct dwc3_event_depevt *event) | |
863 | { | |
c7fcdeb2 FB |
864 | struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; |
865 | ||
866 | dep->flags &= ~DWC3_EP_BUSY; | |
b4996a86 | 867 | dep->resource_index = 0; |
df62df56 | 868 | dwc->setup_packet_pending = false; |
c7fcdeb2 | 869 | |
72246da4 | 870 | switch (dwc->ep0state) { |
c7fcdeb2 FB |
871 | case EP0_SETUP_PHASE: |
872 | dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n"); | |
72246da4 FB |
873 | dwc3_ep0_inspect_setup(dwc, event); |
874 | break; | |
875 | ||
c7fcdeb2 FB |
876 | case EP0_DATA_PHASE: |
877 | dev_vdbg(dwc->dev, "Data Phase\n"); | |
72246da4 FB |
878 | dwc3_ep0_complete_data(dwc, event); |
879 | break; | |
880 | ||
c7fcdeb2 FB |
881 | case EP0_STATUS_PHASE: |
882 | dev_vdbg(dwc->dev, "Status Phase\n"); | |
85a78101 | 883 | dwc3_ep0_complete_status(dwc, event); |
72246da4 | 884 | break; |
c7fcdeb2 FB |
885 | default: |
886 | WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); | |
887 | } | |
888 | } | |
72246da4 | 889 | |
a0807881 FB |
890 | static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, |
891 | struct dwc3_ep *dep, struct dwc3_request *req) | |
c7fcdeb2 | 892 | { |
c7fcdeb2 FB |
893 | int ret; |
894 | ||
a0807881 | 895 | req->direction = !!dep->number; |
c7fcdeb2 | 896 | |
c7fcdeb2 | 897 | if (req->request.length == 0) { |
a0807881 | 898 | ret = dwc3_ep0_start_trans(dwc, dep->number, |
c7fcdeb2 FB |
899 | dwc->ctrl_req_addr, 0, |
900 | DWC3_TRBCTL_CONTROL_DATA); | |
c74c6d4a | 901 | } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) |
a0807881 | 902 | && (dep->number == 0)) { |
c390b036 AM |
903 | u32 transfer_size; |
904 | u32 maxpacket; | |
a0807881 | 905 | |
0fc9a1be | 906 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
a0807881 | 907 | dep->number); |
0fc9a1be FB |
908 | if (ret) { |
909 | dev_dbg(dwc->dev, "failed to map request\n"); | |
910 | return; | |
911 | } | |
c7fcdeb2 | 912 | |
4552a0ca | 913 | WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE); |
c7fcdeb2 | 914 | |
c390b036 AM |
915 | maxpacket = dep->endpoint.maxpacket; |
916 | transfer_size = roundup(req->request.length, maxpacket); | |
a0807881 | 917 | |
c7fcdeb2 FB |
918 | dwc->ep0_bounced = true; |
919 | ||
920 | /* | |
4552a0ca FB |
921 | * REVISIT in case request length is bigger than |
922 | * DWC3_EP0_BOUNCE_SIZE we will need two chained | |
923 | * TRBs to handle the transfer. | |
c7fcdeb2 | 924 | */ |
a0807881 FB |
925 | ret = dwc3_ep0_start_trans(dwc, dep->number, |
926 | dwc->ep0_bounce_addr, transfer_size, | |
c7fcdeb2 FB |
927 | DWC3_TRBCTL_CONTROL_DATA); |
928 | } else { | |
0fc9a1be | 929 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
a0807881 | 930 | dep->number); |
0fc9a1be FB |
931 | if (ret) { |
932 | dev_dbg(dwc->dev, "failed to map request\n"); | |
933 | return; | |
934 | } | |
c7fcdeb2 | 935 | |
a0807881 FB |
936 | ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma, |
937 | req->request.length, DWC3_TRBCTL_CONTROL_DATA); | |
c7fcdeb2 FB |
938 | } |
939 | ||
940 | WARN_ON(ret < 0); | |
72246da4 FB |
941 | } |
942 | ||
f0f2b2a2 | 943 | static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) |
72246da4 | 944 | { |
f0f2b2a2 | 945 | struct dwc3 *dwc = dep->dwc; |
c7fcdeb2 | 946 | u32 type; |
72246da4 | 947 | |
c7fcdeb2 FB |
948 | type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 |
949 | : DWC3_TRBCTL_CONTROL_STATUS2; | |
950 | ||
f0f2b2a2 | 951 | return dwc3_ep0_start_trans(dwc, dep->number, |
c7fcdeb2 | 952 | dwc->ctrl_req_addr, 0, type); |
f0f2b2a2 | 953 | } |
c7fcdeb2 | 954 | |
788a23f4 | 955 | static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) |
f0f2b2a2 | 956 | { |
457e84b6 FB |
957 | if (dwc->resize_fifos) { |
958 | dev_dbg(dwc->dev, "starting to resize fifos\n"); | |
959 | dwc3_gadget_resize_tx_fifos(dwc); | |
960 | dwc->resize_fifos = 0; | |
961 | } | |
962 | ||
f0f2b2a2 | 963 | WARN_ON(dwc3_ep0_start_control_status(dep)); |
c7fcdeb2 FB |
964 | } |
965 | ||
788a23f4 FB |
966 | static void dwc3_ep0_do_control_status(struct dwc3 *dwc, |
967 | const struct dwc3_event_depevt *event) | |
968 | { | |
969 | struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; | |
970 | ||
971 | __dwc3_ep0_do_control_status(dwc, dep); | |
972 | } | |
973 | ||
2e3db064 FB |
974 | static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) |
975 | { | |
976 | struct dwc3_gadget_ep_cmd_params params; | |
977 | u32 cmd; | |
978 | int ret; | |
979 | ||
980 | if (!dep->resource_index) | |
981 | return; | |
982 | ||
983 | cmd = DWC3_DEPCMD_ENDTRANSFER; | |
984 | cmd |= DWC3_DEPCMD_CMDIOC; | |
985 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); | |
986 | memset(¶ms, 0, sizeof(params)); | |
987 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
988 | WARN_ON_ONCE(ret); | |
989 | dep->resource_index = 0; | |
990 | } | |
991 | ||
c7fcdeb2 FB |
992 | static void dwc3_ep0_xfernotready(struct dwc3 *dwc, |
993 | const struct dwc3_event_depevt *event) | |
994 | { | |
df62df56 FB |
995 | dwc->setup_packet_pending = true; |
996 | ||
c7fcdeb2 | 997 | switch (event->status) { |
c7fcdeb2 FB |
998 | case DEPEVT_STATUS_CONTROL_DATA: |
999 | dev_vdbg(dwc->dev, "Control Data\n"); | |
1ddcb218 | 1000 | |
55f3fba6 | 1001 | /* |
2e3db064 FB |
1002 | * We already have a DATA transfer in the controller's cache, |
1003 | * if we receive a XferNotReady(DATA) we will ignore it, unless | |
1004 | * it's for the wrong direction. | |
55f3fba6 | 1005 | * |
2e3db064 FB |
1006 | * In that case, we must issue END_TRANSFER command to the Data |
1007 | * Phase we already have started and issue SetStall on the | |
1008 | * control endpoint. | |
55f3fba6 FB |
1009 | */ |
1010 | if (dwc->ep0_expect_in != event->endpoint_number) { | |
2e3db064 FB |
1011 | struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; |
1012 | ||
55f3fba6 | 1013 | dev_vdbg(dwc->dev, "Wrong direction for Data phase\n"); |
2e3db064 | 1014 | dwc3_ep0_end_control_data(dwc, dep); |
55f3fba6 FB |
1015 | dwc3_ep0_stall_and_restart(dwc); |
1016 | return; | |
1017 | } | |
1018 | ||
c7fcdeb2 | 1019 | break; |
1ddcb218 | 1020 | |
c7fcdeb2 | 1021 | case DEPEVT_STATUS_CONTROL_STATUS: |
77fa6df8 FB |
1022 | if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) |
1023 | return; | |
1024 | ||
c7fcdeb2 | 1025 | dev_vdbg(dwc->dev, "Control Status\n"); |
1ddcb218 | 1026 | |
f0f2b2a2 SAS |
1027 | dwc->ep0state = EP0_STATUS_PHASE; |
1028 | ||
5bdb1dcc SAS |
1029 | if (dwc->delayed_status) { |
1030 | WARN_ON_ONCE(event->endpoint_number != 1); | |
1031 | dev_vdbg(dwc->dev, "Mass Storage delayed status\n"); | |
1032 | return; | |
1033 | } | |
1034 | ||
788a23f4 | 1035 | dwc3_ep0_do_control_status(dwc, event); |
72246da4 FB |
1036 | } |
1037 | } | |
1038 | ||
1039 | void dwc3_ep0_interrupt(struct dwc3 *dwc, | |
8becf270 | 1040 | const struct dwc3_event_depevt *event) |
72246da4 FB |
1041 | { |
1042 | u8 epnum = event->endpoint_number; | |
1043 | ||
1044 | dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n", | |
1045 | dwc3_ep_event_string(event->endpoint_event), | |
b147f357 | 1046 | epnum >> 1, (epnum & 1) ? "in" : "out", |
72246da4 FB |
1047 | dwc3_ep0_state_string(dwc->ep0state)); |
1048 | ||
1049 | switch (event->endpoint_event) { | |
1050 | case DWC3_DEPEVT_XFERCOMPLETE: | |
1051 | dwc3_ep0_xfer_complete(dwc, event); | |
1052 | break; | |
1053 | ||
1054 | case DWC3_DEPEVT_XFERNOTREADY: | |
1055 | dwc3_ep0_xfernotready(dwc, event); | |
1056 | break; | |
1057 | ||
1058 | case DWC3_DEPEVT_XFERINPROGRESS: | |
1059 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
1060 | case DWC3_DEPEVT_STREAMEVT: | |
1061 | case DWC3_DEPEVT_EPCMDCMPLT: | |
1062 | break; | |
1063 | } | |
1064 | } |