Commit | Line | Data |
---|---|---|
72246da4 FB |
1 | /** |
2 | * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/pm_runtime.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/list.h> | |
27 | #include <linux/dma-mapping.h> | |
28 | ||
29 | #include <linux/usb/ch9.h> | |
30 | #include <linux/usb/gadget.h> | |
5bdb1dcc | 31 | #include <linux/usb/composite.h> |
72246da4 FB |
32 | |
33 | #include "core.h" | |
80977dc9 | 34 | #include "debug.h" |
72246da4 FB |
35 | #include "gadget.h" |
36 | #include "io.h" | |
37 | ||
788a23f4 | 38 | static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); |
a0807881 FB |
39 | static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, |
40 | struct dwc3_ep *dep, struct dwc3_request *req); | |
5bdb1dcc | 41 | |
7931ec86 FB |
42 | static void dwc3_ep0_prepare_one_trb(struct dwc3 *dwc, u8 epnum, |
43 | dma_addr_t buf_dma, u32 len, u32 type, bool chain) | |
72246da4 | 44 | { |
f6bafc6a | 45 | struct dwc3_trb *trb; |
72246da4 FB |
46 | struct dwc3_ep *dep; |
47 | ||
72246da4 FB |
48 | dep = dwc->eps[epnum]; |
49 | ||
53fd8818 | 50 | trb = &dwc->ep0_trb[dep->trb_enqueue]; |
2abd9d5f KVA |
51 | |
52 | if (chain) | |
53fd8818 | 53 | dep->trb_enqueue++; |
72246da4 | 54 | |
f6bafc6a FB |
55 | trb->bpl = lower_32_bits(buf_dma); |
56 | trb->bph = upper_32_bits(buf_dma); | |
57 | trb->size = len; | |
58 | trb->ctrl = type; | |
72246da4 | 59 | |
f6bafc6a | 60 | trb->ctrl |= (DWC3_TRB_CTRL_HWO |
f6bafc6a | 61 | | DWC3_TRB_CTRL_ISP_IMI); |
72246da4 | 62 | |
2abd9d5f KVA |
63 | if (chain) |
64 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
65 | else | |
66 | trb->ctrl |= (DWC3_TRB_CTRL_IOC | |
67 | | DWC3_TRB_CTRL_LST); | |
68 | ||
7931ec86 FB |
69 | trace_dwc3_prepare_trb(dep, trb); |
70 | } | |
71 | ||
19ec3123 | 72 | static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum) |
7931ec86 FB |
73 | { |
74 | struct dwc3_gadget_ep_cmd_params params; | |
75 | struct dwc3_ep *dep; | |
76 | int ret; | |
77 | ||
78 | dep = dwc->eps[epnum]; | |
79 | if (dep->flags & DWC3_EP_BUSY) | |
2abd9d5f KVA |
80 | return 0; |
81 | ||
72246da4 | 82 | memset(¶ms, 0, sizeof(params)); |
dc1c70a7 FB |
83 | params.param0 = upper_32_bits(dwc->ep0_trb_addr); |
84 | params.param1 = lower_32_bits(dwc->ep0_trb_addr); | |
72246da4 | 85 | |
2cd4718d | 86 | ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms); |
8566cd1a | 87 | if (ret < 0) |
72246da4 | 88 | return ret; |
72246da4 | 89 | |
c7fcdeb2 | 90 | dep->flags |= DWC3_EP_BUSY; |
2eb88016 | 91 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep); |
1ddcb218 FB |
92 | dwc->ep0_next_event = DWC3_EP0_COMPLETE; |
93 | ||
72246da4 FB |
94 | return 0; |
95 | } | |
96 | ||
97 | static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, | |
98 | struct dwc3_request *req) | |
99 | { | |
5bdb1dcc | 100 | struct dwc3 *dwc = dep->dwc; |
72246da4 FB |
101 | |
102 | req->request.actual = 0; | |
103 | req->request.status = -EINPROGRESS; | |
72246da4 FB |
104 | req->epnum = dep->number; |
105 | ||
aa3342c8 | 106 | list_add_tail(&req->list, &dep->pending_list); |
a6829706 | 107 | |
c7fcdeb2 FB |
108 | /* |
109 | * Gadget driver might not be quick enough to queue a request | |
110 | * before we get a Transfer Not Ready event on this endpoint. | |
111 | * | |
112 | * In that case, we will set DWC3_EP_PENDING_REQUEST. When that | |
113 | * flag is set, it's telling us that as soon as Gadget queues the | |
114 | * required request, we should kick the transfer here because the | |
115 | * IRQ we were waiting for is long gone. | |
116 | */ | |
117 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
c7fcdeb2 | 118 | unsigned direction; |
c7fcdeb2 FB |
119 | |
120 | direction = !!(dep->flags & DWC3_EP0_DIR_IN); | |
121 | ||
68d8a781 FB |
122 | if (dwc->ep0state != EP0_DATA_PHASE) { |
123 | dev_WARN(dwc->dev, "Unexpected pending request\n"); | |
c7fcdeb2 FB |
124 | return 0; |
125 | } | |
72246da4 | 126 | |
a0807881 FB |
127 | __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); |
128 | ||
c7fcdeb2 FB |
129 | dep->flags &= ~(DWC3_EP_PENDING_REQUEST | |
130 | DWC3_EP0_DIR_IN); | |
d9b33c60 FB |
131 | |
132 | return 0; | |
133 | } | |
134 | ||
135 | /* | |
136 | * In case gadget driver asked us to delay the STATUS phase, | |
137 | * handle it here. | |
138 | */ | |
139 | if (dwc->delayed_status) { | |
7125d584 FB |
140 | unsigned direction; |
141 | ||
142 | direction = !dwc->ep0_expect_in; | |
5bdb1dcc | 143 | dwc->delayed_status = false; |
7c81290e | 144 | usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED); |
68d3e668 FB |
145 | |
146 | if (dwc->ep0state == EP0_STATUS_PHASE) | |
7125d584 | 147 | __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); |
d9b33c60 FB |
148 | |
149 | return 0; | |
72246da4 FB |
150 | } |
151 | ||
fca8892a FB |
152 | /* |
153 | * Unfortunately we have uncovered a limitation wrt the Data Phase. | |
154 | * | |
155 | * Section 9.4 says we can wait for the XferNotReady(DATA) event to | |
156 | * come before issueing Start Transfer command, but if we do, we will | |
157 | * miss situations where the host starts another SETUP phase instead of | |
158 | * the DATA phase. Such cases happen at least on TD.7.6 of the Link | |
159 | * Layer Compliance Suite. | |
160 | * | |
161 | * The problem surfaces due to the fact that in case of back-to-back | |
162 | * SETUP packets there will be no XferNotReady(DATA) generated and we | |
163 | * will be stuck waiting for XferNotReady(DATA) forever. | |
164 | * | |
165 | * By looking at tables 9-13 and 9-14 of the Databook, we can see that | |
166 | * it tells us to start Data Phase right away. It also mentions that if | |
167 | * we receive a SETUP phase instead of the DATA phase, core will issue | |
168 | * XferComplete for the DATA phase, before actually initiating it in | |
169 | * the wire, with the TRB's status set to "SETUP_PENDING". Such status | |
170 | * can only be used to print some debugging logs, as the core expects | |
171 | * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, | |
172 | * just so it completes right away, without transferring anything and, | |
173 | * only then, we can go back to the SETUP phase. | |
174 | * | |
175 | * Because of this scenario, SNPS decided to change the programming | |
176 | * model of control transfers and support on-demand transfers only for | |
177 | * the STATUS phase. To fix the issue we have now, we will always wait | |
178 | * for gadget driver to queue the DATA phase's struct usb_request, then | |
179 | * start it right away. | |
180 | * | |
181 | * If we're actually in a 2-stage transfer, we will wait for | |
182 | * XferNotReady(STATUS). | |
183 | */ | |
184 | if (dwc->three_stage_setup) { | |
185 | unsigned direction; | |
186 | ||
187 | direction = dwc->ep0_expect_in; | |
188 | dwc->ep0state = EP0_DATA_PHASE; | |
189 | ||
190 | __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); | |
191 | ||
192 | dep->flags &= ~DWC3_EP0_DIR_IN; | |
193 | } | |
194 | ||
35f75696 | 195 | return 0; |
72246da4 FB |
196 | } |
197 | ||
198 | int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, | |
199 | gfp_t gfp_flags) | |
200 | { | |
201 | struct dwc3_request *req = to_dwc3_request(request); | |
202 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
203 | struct dwc3 *dwc = dep->dwc; | |
204 | ||
205 | unsigned long flags; | |
206 | ||
207 | int ret; | |
208 | ||
72246da4 | 209 | spin_lock_irqsave(&dwc->lock, flags); |
16e78db7 | 210 | if (!dep->endpoint.desc) { |
5eb30ced FB |
211 | dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", |
212 | dep->name); | |
72246da4 FB |
213 | ret = -ESHUTDOWN; |
214 | goto out; | |
215 | } | |
216 | ||
217 | /* we share one TRB for ep0/1 */ | |
aa3342c8 | 218 | if (!list_empty(&dep->pending_list)) { |
72246da4 FB |
219 | ret = -EBUSY; |
220 | goto out; | |
221 | } | |
222 | ||
72246da4 FB |
223 | ret = __dwc3_gadget_ep0_queue(dep, req); |
224 | ||
225 | out: | |
226 | spin_unlock_irqrestore(&dwc->lock, flags); | |
227 | ||
228 | return ret; | |
229 | } | |
230 | ||
231 | static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) | |
232 | { | |
2dfe37d4 FB |
233 | struct dwc3_ep *dep; |
234 | ||
235 | /* reinitialize physical ep1 */ | |
236 | dep = dwc->eps[1]; | |
237 | dep->flags = DWC3_EP_ENABLED; | |
d742220b | 238 | |
72246da4 | 239 | /* stall is always issued on EP0 */ |
2dfe37d4 | 240 | dep = dwc->eps[0]; |
7a608559 | 241 | __dwc3_gadget_ep_set_halt(dep, 1, false); |
c2da2ff0 | 242 | dep->flags = DWC3_EP_ENABLED; |
5bdb1dcc | 243 | dwc->delayed_status = false; |
d742220b | 244 | |
aa3342c8 | 245 | if (!list_empty(&dep->pending_list)) { |
d742220b FB |
246 | struct dwc3_request *req; |
247 | ||
aa3342c8 | 248 | req = next_request(&dep->pending_list); |
d742220b FB |
249 | dwc3_gadget_giveback(dep, req, -ECONNRESET); |
250 | } | |
251 | ||
c7fcdeb2 | 252 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
253 | dwc3_ep0_out_start(dwc); |
254 | } | |
255 | ||
33fb691b | 256 | int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) |
08f0d966 PA |
257 | { |
258 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
259 | struct dwc3 *dwc = dep->dwc; | |
260 | ||
261 | dwc3_ep0_stall_and_restart(dwc); | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
33fb691b FB |
266 | int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) |
267 | { | |
268 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
269 | struct dwc3 *dwc = dep->dwc; | |
270 | unsigned long flags; | |
271 | int ret; | |
272 | ||
273 | spin_lock_irqsave(&dwc->lock, flags); | |
274 | ret = __dwc3_gadget_ep0_set_halt(ep, value); | |
275 | spin_unlock_irqrestore(&dwc->lock, flags); | |
276 | ||
277 | return ret; | |
278 | } | |
279 | ||
72246da4 FB |
280 | void dwc3_ep0_out_start(struct dwc3 *dwc) |
281 | { | |
72246da4 FB |
282 | int ret; |
283 | ||
bb014736 BW |
284 | complete(&dwc->ep0_in_setup); |
285 | ||
19ec3123 | 286 | dwc3_ep0_prepare_one_trb(dwc, 0, dwc->ctrl_req_addr, 8, |
368ca113 | 287 | DWC3_TRBCTL_CONTROL_SETUP, false); |
19ec3123 | 288 | ret = dwc3_ep0_start_trans(dwc, 0); |
72246da4 FB |
289 | WARN_ON(ret < 0); |
290 | } | |
291 | ||
72246da4 FB |
292 | static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) |
293 | { | |
294 | struct dwc3_ep *dep; | |
295 | u32 windex = le16_to_cpu(wIndex_le); | |
296 | u32 epnum; | |
297 | ||
298 | epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; | |
299 | if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) | |
300 | epnum |= 1; | |
301 | ||
302 | dep = dwc->eps[epnum]; | |
303 | if (dep->flags & DWC3_EP_ENABLED) | |
304 | return dep; | |
305 | ||
306 | return NULL; | |
307 | } | |
308 | ||
8ee6270c | 309 | static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) |
72246da4 | 310 | { |
72246da4 | 311 | } |
72246da4 FB |
312 | /* |
313 | * ch 9.4.5 | |
314 | */ | |
25b8ff68 FB |
315 | static int dwc3_ep0_handle_status(struct dwc3 *dwc, |
316 | struct usb_ctrlrequest *ctrl) | |
72246da4 FB |
317 | { |
318 | struct dwc3_ep *dep; | |
319 | u32 recip; | |
e6a3b5e2 | 320 | u32 reg; |
72246da4 FB |
321 | u16 usb_status = 0; |
322 | __le16 *response_pkt; | |
323 | ||
324 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
325 | switch (recip) { | |
326 | case USB_RECIP_DEVICE: | |
327 | /* | |
e6a3b5e2 | 328 | * LTM will be set once we know how to set this in HW. |
72246da4 | 329 | */ |
bcdea503 | 330 | usb_status |= dwc->gadget.is_selfpowered; |
e6a3b5e2 | 331 | |
ee5cd41c JY |
332 | if ((dwc->speed == DWC3_DSTS_SUPERSPEED) || |
333 | (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) { | |
e6a3b5e2 SAS |
334 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
335 | if (reg & DWC3_DCTL_INITU1ENA) | |
336 | usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; | |
337 | if (reg & DWC3_DCTL_INITU2ENA) | |
338 | usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; | |
339 | } | |
340 | ||
72246da4 FB |
341 | break; |
342 | ||
343 | case USB_RECIP_INTERFACE: | |
344 | /* | |
345 | * Function Remote Wake Capable D0 | |
346 | * Function Remote Wakeup D1 | |
347 | */ | |
348 | break; | |
349 | ||
350 | case USB_RECIP_ENDPOINT: | |
351 | dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); | |
352 | if (!dep) | |
25b8ff68 | 353 | return -EINVAL; |
72246da4 FB |
354 | |
355 | if (dep->flags & DWC3_EP_STALL) | |
356 | usb_status = 1 << USB_ENDPOINT_HALT; | |
357 | break; | |
358 | default: | |
359 | return -EINVAL; | |
2b84f92b | 360 | } |
72246da4 FB |
361 | |
362 | response_pkt = (__le16 *) dwc->setup_buf; | |
363 | *response_pkt = cpu_to_le16(usb_status); | |
e2617796 FB |
364 | |
365 | dep = dwc->eps[0]; | |
366 | dwc->ep0_usb_req.dep = dep; | |
e0ce0b0a | 367 | dwc->ep0_usb_req.request.length = sizeof(*response_pkt); |
0fc9a1be | 368 | dwc->ep0_usb_req.request.buf = dwc->setup_buf; |
e0ce0b0a | 369 | dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; |
e2617796 FB |
370 | |
371 | return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); | |
72246da4 FB |
372 | } |
373 | ||
39e07ffb FB |
374 | static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state, |
375 | int set) | |
376 | { | |
377 | u32 reg; | |
378 | ||
379 | if (state != USB_STATE_CONFIGURED) | |
380 | return -EINVAL; | |
381 | if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && | |
382 | (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) | |
383 | return -EINVAL; | |
384 | ||
385 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
386 | if (set) | |
387 | reg |= DWC3_DCTL_INITU1ENA; | |
388 | else | |
389 | reg &= ~DWC3_DCTL_INITU1ENA; | |
390 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
395 | static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state, | |
396 | int set) | |
397 | { | |
398 | u32 reg; | |
399 | ||
400 | ||
401 | if (state != USB_STATE_CONFIGURED) | |
402 | return -EINVAL; | |
403 | if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && | |
404 | (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) | |
405 | return -EINVAL; | |
406 | ||
407 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
408 | if (set) | |
409 | reg |= DWC3_DCTL_INITU2ENA; | |
410 | else | |
411 | reg &= ~DWC3_DCTL_INITU2ENA; | |
412 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
417 | static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state, | |
418 | u32 wIndex, int set) | |
419 | { | |
420 | if ((wIndex & 0xff) != 0) | |
421 | return -EINVAL; | |
422 | if (!set) | |
423 | return -EINVAL; | |
424 | ||
425 | switch (wIndex >> 8) { | |
426 | case TEST_J: | |
427 | case TEST_K: | |
428 | case TEST_SE0_NAK: | |
429 | case TEST_PACKET: | |
430 | case TEST_FORCE_EN: | |
431 | dwc->test_mode_nr = wIndex >> 8; | |
432 | dwc->test_mode = true; | |
433 | break; | |
434 | default: | |
435 | return -EINVAL; | |
436 | } | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
441 | static int dwc3_ep0_handle_device(struct dwc3 *dwc, | |
72246da4 FB |
442 | struct usb_ctrlrequest *ctrl, int set) |
443 | { | |
39e07ffb | 444 | enum usb_device_state state; |
72246da4 FB |
445 | u32 wValue; |
446 | u32 wIndex; | |
39e07ffb | 447 | int ret = 0; |
72246da4 FB |
448 | |
449 | wValue = le16_to_cpu(ctrl->wValue); | |
450 | wIndex = le16_to_cpu(ctrl->wIndex); | |
fdba5aa5 FB |
451 | state = dwc->gadget.state; |
452 | ||
39e07ffb FB |
453 | switch (wValue) { |
454 | case USB_DEVICE_REMOTE_WAKEUP: | |
455 | break; | |
456 | /* | |
457 | * 9.4.1 says only only for SS, in AddressState only for | |
458 | * default control pipe | |
459 | */ | |
460 | case USB_DEVICE_U1_ENABLE: | |
461 | ret = dwc3_ep0_handle_u1(dwc, state, set); | |
462 | break; | |
463 | case USB_DEVICE_U2_ENABLE: | |
464 | ret = dwc3_ep0_handle_u2(dwc, state, set); | |
465 | break; | |
466 | case USB_DEVICE_LTM_ENABLE: | |
467 | ret = -EINVAL; | |
468 | break; | |
469 | case USB_DEVICE_TEST_MODE: | |
470 | ret = dwc3_ep0_handle_test(dwc, state, wIndex, set); | |
471 | break; | |
472 | default: | |
473 | ret = -EINVAL; | |
474 | } | |
72246da4 | 475 | |
39e07ffb FB |
476 | return ret; |
477 | } | |
72246da4 | 478 | |
39e07ffb FB |
479 | static int dwc3_ep0_handle_intf(struct dwc3 *dwc, |
480 | struct usb_ctrlrequest *ctrl, int set) | |
481 | { | |
482 | enum usb_device_state state; | |
483 | u32 wValue; | |
484 | u32 wIndex; | |
485 | int ret = 0; | |
e6a3b5e2 | 486 | |
39e07ffb FB |
487 | wValue = le16_to_cpu(ctrl->wValue); |
488 | wIndex = le16_to_cpu(ctrl->wIndex); | |
489 | state = dwc->gadget.state; | |
e6a3b5e2 | 490 | |
39e07ffb FB |
491 | switch (wValue) { |
492 | case USB_INTRF_FUNC_SUSPEND: | |
1c404b51 AB |
493 | /* |
494 | * REVISIT: Ideally we would enable some low power mode here, | |
495 | * however it's unclear what we should be doing here. | |
496 | * | |
497 | * For now, we're not doing anything, just making sure we return | |
498 | * 0 so USB Command Verifier tests pass without any errors. | |
499 | */ | |
39e07ffb FB |
500 | break; |
501 | default: | |
502 | ret = -EINVAL; | |
503 | } | |
e6a3b5e2 | 504 | |
39e07ffb FB |
505 | return ret; |
506 | } | |
507 | ||
508 | static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc, | |
509 | struct usb_ctrlrequest *ctrl, int set) | |
510 | { | |
511 | struct dwc3_ep *dep; | |
512 | enum usb_device_state state; | |
513 | u32 wValue; | |
514 | u32 wIndex; | |
515 | int ret; | |
516 | ||
517 | wValue = le16_to_cpu(ctrl->wValue); | |
518 | wIndex = le16_to_cpu(ctrl->wIndex); | |
519 | state = dwc->gadget.state; | |
520 | ||
521 | switch (wValue) { | |
522 | case USB_ENDPOINT_HALT: | |
523 | dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); | |
524 | if (!dep) | |
e6a3b5e2 | 525 | return -EINVAL; |
72246da4 | 526 | |
39e07ffb | 527 | if (set == 0 && (dep->flags & DWC3_EP_WEDGE)) |
ecb07797 | 528 | break; |
39e07ffb FB |
529 | |
530 | ret = __dwc3_gadget_ep_set_halt(dep, set, true); | |
531 | if (ret) | |
ecb07797 | 532 | return -EINVAL; |
72246da4 | 533 | break; |
39e07ffb FB |
534 | default: |
535 | return -EINVAL; | |
536 | } | |
537 | ||
538 | return 0; | |
539 | } | |
540 | ||
541 | static int dwc3_ep0_handle_feature(struct dwc3 *dwc, | |
542 | struct usb_ctrlrequest *ctrl, int set) | |
543 | { | |
544 | u32 recip; | |
545 | int ret; | |
546 | enum usb_device_state state; | |
547 | ||
548 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
549 | state = dwc->gadget.state; | |
72246da4 | 550 | |
39e07ffb FB |
551 | switch (recip) { |
552 | case USB_RECIP_DEVICE: | |
553 | ret = dwc3_ep0_handle_device(dwc, ctrl, set); | |
554 | break; | |
72246da4 | 555 | case USB_RECIP_INTERFACE: |
39e07ffb | 556 | ret = dwc3_ep0_handle_intf(dwc, ctrl, set); |
72246da4 | 557 | break; |
72246da4 | 558 | case USB_RECIP_ENDPOINT: |
39e07ffb | 559 | ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set); |
72246da4 | 560 | break; |
72246da4 | 561 | default: |
39e07ffb | 562 | ret = -EINVAL; |
2b84f92b | 563 | } |
72246da4 | 564 | |
39e07ffb | 565 | return ret; |
72246da4 FB |
566 | } |
567 | ||
568 | static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
569 | { | |
fdba5aa5 | 570 | enum usb_device_state state = dwc->gadget.state; |
72246da4 FB |
571 | u32 addr; |
572 | u32 reg; | |
573 | ||
574 | addr = le16_to_cpu(ctrl->wValue); | |
f96a6ec1 | 575 | if (addr > 127) { |
5eb30ced | 576 | dev_err(dwc->dev, "invalid device address %d\n", addr); |
72246da4 | 577 | return -EINVAL; |
f96a6ec1 FB |
578 | } |
579 | ||
fdba5aa5 | 580 | if (state == USB_STATE_CONFIGURED) { |
5eb30ced | 581 | dev_err(dwc->dev, "can't SetAddress() from Configured State\n"); |
f96a6ec1 FB |
582 | return -EINVAL; |
583 | } | |
72246da4 | 584 | |
2646021e FB |
585 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
586 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
587 | reg |= DWC3_DCFG_DEVADDR(addr); | |
588 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 | 589 | |
fdba5aa5 | 590 | if (addr) |
14cd592f | 591 | usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS); |
fdba5aa5 | 592 | else |
14cd592f | 593 | usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); |
c7fcdeb2 | 594 | |
2646021e | 595 | return 0; |
72246da4 FB |
596 | } |
597 | ||
598 | static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
599 | { | |
600 | int ret; | |
601 | ||
602 | spin_unlock(&dwc->lock); | |
603 | ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); | |
604 | spin_lock(&dwc->lock); | |
605 | return ret; | |
606 | } | |
607 | ||
608 | static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
609 | { | |
fdba5aa5 | 610 | enum usb_device_state state = dwc->gadget.state; |
72246da4 FB |
611 | u32 cfg; |
612 | int ret; | |
e274a31e | 613 | u32 reg; |
72246da4 FB |
614 | |
615 | cfg = le16_to_cpu(ctrl->wValue); | |
616 | ||
fdba5aa5 FB |
617 | switch (state) { |
618 | case USB_STATE_DEFAULT: | |
72246da4 | 619 | return -EINVAL; |
72246da4 | 620 | |
fdba5aa5 | 621 | case USB_STATE_ADDRESS: |
72246da4 FB |
622 | ret = dwc3_ep0_delegate_req(dwc, ctrl); |
623 | /* if the cfg matches and the cfg is non zero */ | |
457e84b6 | 624 | if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { |
7c81290e FB |
625 | |
626 | /* | |
627 | * only change state if set_config has already | |
628 | * been processed. If gadget driver returns | |
629 | * USB_GADGET_DELAYED_STATUS, we will wait | |
630 | * to change the state on the next usb_ep_queue() | |
631 | */ | |
632 | if (ret == 0) | |
633 | usb_gadget_set_state(&dwc->gadget, | |
634 | USB_STATE_CONFIGURED); | |
14cd592f | 635 | |
e274a31e PA |
636 | /* |
637 | * Enable transition to U1/U2 state when | |
638 | * nothing is pending from application. | |
639 | */ | |
640 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
641 | reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); | |
642 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
457e84b6 | 643 | } |
72246da4 FB |
644 | break; |
645 | ||
fdba5aa5 | 646 | case USB_STATE_CONFIGURED: |
72246da4 | 647 | ret = dwc3_ep0_delegate_req(dwc, ctrl); |
7a42d835 | 648 | if (!cfg && !ret) |
14cd592f FB |
649 | usb_gadget_set_state(&dwc->gadget, |
650 | USB_STATE_ADDRESS); | |
72246da4 | 651 | break; |
5bdb1dcc SAS |
652 | default: |
653 | ret = -EINVAL; | |
72246da4 | 654 | } |
5bdb1dcc | 655 | return ret; |
72246da4 FB |
656 | } |
657 | ||
865e09e7 FB |
658 | static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) |
659 | { | |
660 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
661 | struct dwc3 *dwc = dep->dwc; | |
662 | ||
663 | u32 param = 0; | |
664 | u32 reg; | |
665 | ||
666 | struct timing { | |
667 | u8 u1sel; | |
668 | u8 u1pel; | |
501058ed JY |
669 | __le16 u2sel; |
670 | __le16 u2pel; | |
865e09e7 FB |
671 | } __packed timing; |
672 | ||
673 | int ret; | |
674 | ||
675 | memcpy(&timing, req->buf, sizeof(timing)); | |
676 | ||
677 | dwc->u1sel = timing.u1sel; | |
678 | dwc->u1pel = timing.u1pel; | |
c8cf7af4 FB |
679 | dwc->u2sel = le16_to_cpu(timing.u2sel); |
680 | dwc->u2pel = le16_to_cpu(timing.u2pel); | |
865e09e7 FB |
681 | |
682 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
683 | if (reg & DWC3_DCTL_INITU2ENA) | |
684 | param = dwc->u2pel; | |
685 | if (reg & DWC3_DCTL_INITU1ENA) | |
686 | param = dwc->u1pel; | |
687 | ||
688 | /* | |
689 | * According to Synopsys Databook, if parameter is | |
690 | * greater than 125, a value of zero should be | |
691 | * programmed in the register. | |
692 | */ | |
693 | if (param > 125) | |
694 | param = 0; | |
695 | ||
696 | /* now that we have the time, issue DGCMD Set Sel */ | |
697 | ret = dwc3_send_gadget_generic_command(dwc, | |
698 | DWC3_DGCMD_SET_PERIODIC_PAR, param); | |
699 | WARN_ON(ret < 0); | |
700 | } | |
701 | ||
702 | static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
703 | { | |
704 | struct dwc3_ep *dep; | |
fdba5aa5 | 705 | enum usb_device_state state = dwc->gadget.state; |
865e09e7 FB |
706 | u16 wLength; |
707 | u16 wValue; | |
708 | ||
fdba5aa5 | 709 | if (state == USB_STATE_DEFAULT) |
865e09e7 FB |
710 | return -EINVAL; |
711 | ||
712 | wValue = le16_to_cpu(ctrl->wValue); | |
713 | wLength = le16_to_cpu(ctrl->wLength); | |
714 | ||
715 | if (wLength != 6) { | |
716 | dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", | |
717 | wLength); | |
718 | return -EINVAL; | |
719 | } | |
720 | ||
721 | /* | |
722 | * To handle Set SEL we need to receive 6 bytes from Host. So let's | |
723 | * queue a usb_request for 6 bytes. | |
724 | * | |
725 | * Remember, though, this controller can't handle non-wMaxPacketSize | |
726 | * aligned transfers on the OUT direction, so we queue a request for | |
727 | * wMaxPacketSize instead. | |
728 | */ | |
729 | dep = dwc->eps[0]; | |
730 | dwc->ep0_usb_req.dep = dep; | |
731 | dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; | |
732 | dwc->ep0_usb_req.request.buf = dwc->setup_buf; | |
733 | dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; | |
734 | ||
735 | return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); | |
736 | } | |
737 | ||
c12a0d86 FB |
738 | static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) |
739 | { | |
740 | u16 wLength; | |
741 | u16 wValue; | |
742 | u16 wIndex; | |
743 | ||
744 | wValue = le16_to_cpu(ctrl->wValue); | |
745 | wLength = le16_to_cpu(ctrl->wLength); | |
746 | wIndex = le16_to_cpu(ctrl->wIndex); | |
747 | ||
748 | if (wIndex || wLength) | |
749 | return -EINVAL; | |
750 | ||
751 | /* | |
752 | * REVISIT It's unclear from Databook what to do with this | |
753 | * value. For now, just cache it. | |
754 | */ | |
755 | dwc->isoch_delay = wValue; | |
756 | ||
757 | return 0; | |
758 | } | |
759 | ||
72246da4 FB |
760 | static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) |
761 | { | |
762 | int ret; | |
763 | ||
764 | switch (ctrl->bRequest) { | |
765 | case USB_REQ_GET_STATUS: | |
72246da4 FB |
766 | ret = dwc3_ep0_handle_status(dwc, ctrl); |
767 | break; | |
768 | case USB_REQ_CLEAR_FEATURE: | |
72246da4 FB |
769 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); |
770 | break; | |
771 | case USB_REQ_SET_FEATURE: | |
72246da4 FB |
772 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); |
773 | break; | |
774 | case USB_REQ_SET_ADDRESS: | |
72246da4 FB |
775 | ret = dwc3_ep0_set_address(dwc, ctrl); |
776 | break; | |
777 | case USB_REQ_SET_CONFIGURATION: | |
72246da4 FB |
778 | ret = dwc3_ep0_set_config(dwc, ctrl); |
779 | break; | |
865e09e7 | 780 | case USB_REQ_SET_SEL: |
865e09e7 FB |
781 | ret = dwc3_ep0_set_sel(dwc, ctrl); |
782 | break; | |
c12a0d86 | 783 | case USB_REQ_SET_ISOCH_DELAY: |
c12a0d86 FB |
784 | ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); |
785 | break; | |
72246da4 | 786 | default: |
72246da4 FB |
787 | ret = dwc3_ep0_delegate_req(dwc, ctrl); |
788 | break; | |
2b84f92b | 789 | } |
72246da4 FB |
790 | |
791 | return ret; | |
792 | } | |
793 | ||
794 | static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, | |
795 | const struct dwc3_event_depevt *event) | |
796 | { | |
797 | struct usb_ctrlrequest *ctrl = dwc->ctrl_req; | |
ef21ede6 | 798 | int ret = -EINVAL; |
72246da4 FB |
799 | u32 len; |
800 | ||
801 | if (!dwc->gadget_driver) | |
ef21ede6 | 802 | goto out; |
72246da4 | 803 | |
2c4cbe6e FB |
804 | trace_dwc3_ctrl_req(ctrl); |
805 | ||
72246da4 | 806 | len = le16_to_cpu(ctrl->wLength); |
1ddcb218 | 807 | if (!len) { |
d95b09b9 FB |
808 | dwc->three_stage_setup = false; |
809 | dwc->ep0_expect_in = false; | |
1ddcb218 FB |
810 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
811 | } else { | |
d95b09b9 FB |
812 | dwc->three_stage_setup = true; |
813 | dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); | |
1ddcb218 FB |
814 | dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; |
815 | } | |
72246da4 FB |
816 | |
817 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) | |
818 | ret = dwc3_ep0_std_request(dwc, ctrl); | |
819 | else | |
820 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
821 | ||
5bdb1dcc SAS |
822 | if (ret == USB_GADGET_DELAYED_STATUS) |
823 | dwc->delayed_status = true; | |
824 | ||
ef21ede6 FB |
825 | out: |
826 | if (ret < 0) | |
827 | dwc3_ep0_stall_and_restart(dwc); | |
72246da4 FB |
828 | } |
829 | ||
830 | static void dwc3_ep0_complete_data(struct dwc3 *dwc, | |
831 | const struct dwc3_event_depevt *event) | |
832 | { | |
833 | struct dwc3_request *r = NULL; | |
834 | struct usb_request *ur; | |
f6bafc6a | 835 | struct dwc3_trb *trb; |
c2da2ff0 | 836 | struct dwc3_ep *ep0; |
8a344220 KVA |
837 | unsigned transfer_size = 0; |
838 | unsigned maxp; | |
839 | unsigned remaining_ur_length; | |
840 | void *buf; | |
841 | u32 transferred = 0; | |
fca8892a | 842 | u32 status; |
f6bafc6a | 843 | u32 length; |
72246da4 FB |
844 | u8 epnum; |
845 | ||
846 | epnum = event->endpoint_number; | |
c2da2ff0 | 847 | ep0 = dwc->eps[0]; |
72246da4 | 848 | |
1ddcb218 FB |
849 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
850 | ||
f6bafc6a | 851 | trb = dwc->ep0_trb; |
fca8892a | 852 | |
ccb072de FB |
853 | trace_dwc3_complete_trb(ep0, trb); |
854 | ||
aa3342c8 | 855 | r = next_request(&ep0->pending_list); |
520fe763 FB |
856 | if (!r) |
857 | return; | |
858 | ||
fca8892a FB |
859 | status = DWC3_TRB_SIZE_TRBSTS(trb->size); |
860 | if (status == DWC3_TRBSTS_SETUP_PENDING) { | |
b5d335e5 | 861 | dwc->setup_packet_pending = true; |
fca8892a FB |
862 | if (r) |
863 | dwc3_gadget_giveback(ep0, r, -ECONNRESET); | |
864 | ||
865 | return; | |
866 | } | |
867 | ||
6856d30c | 868 | ur = &r->request; |
8a344220 KVA |
869 | buf = ur->buf; |
870 | remaining_ur_length = ur->length; | |
6856d30c | 871 | |
f6bafc6a | 872 | length = trb->size & DWC3_TRB_SIZE_MASK; |
72246da4 | 873 | |
8a344220 KVA |
874 | maxp = ep0->endpoint.maxpacket; |
875 | ||
a6829706 | 876 | if (dwc->ep0_bounced) { |
c0bd5456 KVA |
877 | /* |
878 | * Handle the first TRB before handling the bounce buffer if | |
879 | * the request length is greater than the bounce buffer size | |
880 | */ | |
881 | if (ur->length > DWC3_EP0_BOUNCE_SIZE) { | |
882 | transfer_size = ALIGN(ur->length - maxp, maxp); | |
883 | transferred = transfer_size - length; | |
884 | buf = (u8 *)buf + transferred; | |
885 | ur->actual += transferred; | |
886 | remaining_ur_length -= transferred; | |
887 | ||
888 | trb++; | |
889 | length = trb->size & DWC3_TRB_SIZE_MASK; | |
890 | ||
53fd8818 | 891 | ep0->trb_enqueue = 0; |
c0bd5456 KVA |
892 | } |
893 | ||
8a344220 KVA |
894 | transfer_size = roundup((ur->length - transfer_size), |
895 | maxp); | |
b2fb5b1a | 896 | |
8a344220 KVA |
897 | transferred = min_t(u32, remaining_ur_length, |
898 | transfer_size - length); | |
899 | memcpy(buf, dwc->ep0_bounce, transferred); | |
a6829706 | 900 | } else { |
f6bafc6a | 901 | transferred = ur->length - length; |
a6829706 | 902 | } |
72246da4 | 903 | |
cd423dd3 FB |
904 | ur->actual += transferred; |
905 | ||
72246da4 FB |
906 | if ((epnum & 1) && ur->actual < ur->length) { |
907 | /* for some reason we did not get everything out */ | |
908 | ||
909 | dwc3_ep0_stall_and_restart(dwc); | |
72246da4 | 910 | } else { |
36f84ffb FB |
911 | dwc3_gadget_giveback(ep0, r, 0); |
912 | ||
913 | if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) && | |
914 | ur->length && ur->zero) { | |
915 | int ret; | |
916 | ||
917 | dwc->ep0_next_event = DWC3_EP0_COMPLETE; | |
918 | ||
19ec3123 FB |
919 | dwc3_ep0_prepare_one_trb(dwc, epnum, dwc->ctrl_req_addr, |
920 | 0, DWC3_TRBCTL_CONTROL_DATA, false); | |
921 | ret = dwc3_ep0_start_trans(dwc, epnum); | |
36f84ffb FB |
922 | WARN_ON(ret < 0); |
923 | } | |
72246da4 FB |
924 | } |
925 | } | |
926 | ||
85a78101 | 927 | static void dwc3_ep0_complete_status(struct dwc3 *dwc, |
72246da4 FB |
928 | const struct dwc3_event_depevt *event) |
929 | { | |
930 | struct dwc3_request *r; | |
931 | struct dwc3_ep *dep; | |
fca8892a FB |
932 | struct dwc3_trb *trb; |
933 | u32 status; | |
72246da4 | 934 | |
c7fcdeb2 | 935 | dep = dwc->eps[0]; |
fca8892a | 936 | trb = dwc->ep0_trb; |
72246da4 | 937 | |
ccb072de FB |
938 | trace_dwc3_complete_trb(dep, trb); |
939 | ||
aa3342c8 FB |
940 | if (!list_empty(&dep->pending_list)) { |
941 | r = next_request(&dep->pending_list); | |
72246da4 FB |
942 | |
943 | dwc3_gadget_giveback(dep, r, 0); | |
944 | } | |
945 | ||
3b637367 GC |
946 | if (dwc->test_mode) { |
947 | int ret; | |
948 | ||
949 | ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); | |
950 | if (ret < 0) { | |
5eb30ced | 951 | dev_err(dwc->dev, "invalid test #%d\n", |
3b637367 GC |
952 | dwc->test_mode_nr); |
953 | dwc3_ep0_stall_and_restart(dwc); | |
5c81abab | 954 | return; |
3b637367 GC |
955 | } |
956 | } | |
957 | ||
fca8892a | 958 | status = DWC3_TRB_SIZE_TRBSTS(trb->size); |
5eb30ced | 959 | if (status == DWC3_TRBSTS_SETUP_PENDING) |
b5d335e5 | 960 | dwc->setup_packet_pending = true; |
fca8892a | 961 | |
c7fcdeb2 | 962 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
963 | dwc3_ep0_out_start(dwc); |
964 | } | |
965 | ||
966 | static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, | |
967 | const struct dwc3_event_depevt *event) | |
968 | { | |
c7fcdeb2 FB |
969 | struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; |
970 | ||
971 | dep->flags &= ~DWC3_EP_BUSY; | |
b4996a86 | 972 | dep->resource_index = 0; |
df62df56 | 973 | dwc->setup_packet_pending = false; |
c7fcdeb2 | 974 | |
72246da4 | 975 | switch (dwc->ep0state) { |
c7fcdeb2 | 976 | case EP0_SETUP_PHASE: |
72246da4 FB |
977 | dwc3_ep0_inspect_setup(dwc, event); |
978 | break; | |
979 | ||
c7fcdeb2 | 980 | case EP0_DATA_PHASE: |
72246da4 FB |
981 | dwc3_ep0_complete_data(dwc, event); |
982 | break; | |
983 | ||
c7fcdeb2 | 984 | case EP0_STATUS_PHASE: |
85a78101 | 985 | dwc3_ep0_complete_status(dwc, event); |
72246da4 | 986 | break; |
c7fcdeb2 FB |
987 | default: |
988 | WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); | |
989 | } | |
990 | } | |
72246da4 | 991 | |
a0807881 FB |
992 | static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, |
993 | struct dwc3_ep *dep, struct dwc3_request *req) | |
c7fcdeb2 | 994 | { |
c7fcdeb2 FB |
995 | int ret; |
996 | ||
a0807881 | 997 | req->direction = !!dep->number; |
c7fcdeb2 | 998 | |
c7fcdeb2 | 999 | if (req->request.length == 0) { |
19ec3123 | 1000 | dwc3_ep0_prepare_one_trb(dwc, dep->number, |
c7fcdeb2 | 1001 | dwc->ctrl_req_addr, 0, |
368ca113 | 1002 | DWC3_TRBCTL_CONTROL_DATA, false); |
19ec3123 | 1003 | ret = dwc3_ep0_start_trans(dwc, dep->number); |
c74c6d4a | 1004 | } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) |
a0807881 | 1005 | && (dep->number == 0)) { |
8a344220 | 1006 | u32 transfer_size = 0; |
c390b036 | 1007 | u32 maxpacket; |
a0807881 | 1008 | |
d64ff406 AB |
1009 | ret = usb_gadget_map_request_by_dev(dwc->sysdev, |
1010 | &req->request, dep->number); | |
5eb30ced | 1011 | if (ret) |
0fc9a1be | 1012 | return; |
c7fcdeb2 | 1013 | |
c390b036 | 1014 | maxpacket = dep->endpoint.maxpacket; |
a0807881 | 1015 | |
c0bd5456 KVA |
1016 | if (req->request.length > DWC3_EP0_BOUNCE_SIZE) { |
1017 | transfer_size = ALIGN(req->request.length - maxpacket, | |
1018 | maxpacket); | |
19ec3123 | 1019 | dwc3_ep0_prepare_one_trb(dwc, dep->number, |
c0bd5456 KVA |
1020 | req->request.dma, |
1021 | transfer_size, | |
1022 | DWC3_TRBCTL_CONTROL_DATA, | |
1023 | true); | |
b2fb5b1a KVA |
1024 | } |
1025 | ||
c0bd5456 KVA |
1026 | transfer_size = roundup((req->request.length - transfer_size), |
1027 | maxpacket); | |
1028 | ||
c7fcdeb2 FB |
1029 | dwc->ep0_bounced = true; |
1030 | ||
19ec3123 | 1031 | dwc3_ep0_prepare_one_trb(dwc, dep->number, |
a0807881 | 1032 | dwc->ep0_bounce_addr, transfer_size, |
368ca113 | 1033 | DWC3_TRBCTL_CONTROL_DATA, false); |
19ec3123 | 1034 | ret = dwc3_ep0_start_trans(dwc, dep->number); |
c7fcdeb2 | 1035 | } else { |
d64ff406 AB |
1036 | ret = usb_gadget_map_request_by_dev(dwc->sysdev, |
1037 | &req->request, dep->number); | |
5eb30ced | 1038 | if (ret) |
0fc9a1be | 1039 | return; |
c7fcdeb2 | 1040 | |
19ec3123 | 1041 | dwc3_ep0_prepare_one_trb(dwc, dep->number, req->request.dma, |
368ca113 KVA |
1042 | req->request.length, DWC3_TRBCTL_CONTROL_DATA, |
1043 | false); | |
19ec3123 | 1044 | ret = dwc3_ep0_start_trans(dwc, dep->number); |
c7fcdeb2 FB |
1045 | } |
1046 | ||
1047 | WARN_ON(ret < 0); | |
72246da4 FB |
1048 | } |
1049 | ||
f0f2b2a2 | 1050 | static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) |
72246da4 | 1051 | { |
f0f2b2a2 | 1052 | struct dwc3 *dwc = dep->dwc; |
c7fcdeb2 | 1053 | u32 type; |
72246da4 | 1054 | |
c7fcdeb2 FB |
1055 | type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 |
1056 | : DWC3_TRBCTL_CONTROL_STATUS2; | |
1057 | ||
19ec3123 | 1058 | dwc3_ep0_prepare_one_trb(dwc, dep->number, |
368ca113 | 1059 | dwc->ctrl_req_addr, 0, type, false); |
19ec3123 | 1060 | return dwc3_ep0_start_trans(dwc, dep->number); |
f0f2b2a2 | 1061 | } |
c7fcdeb2 | 1062 | |
788a23f4 | 1063 | static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) |
f0f2b2a2 | 1064 | { |
f0f2b2a2 | 1065 | WARN_ON(dwc3_ep0_start_control_status(dep)); |
c7fcdeb2 FB |
1066 | } |
1067 | ||
788a23f4 FB |
1068 | static void dwc3_ep0_do_control_status(struct dwc3 *dwc, |
1069 | const struct dwc3_event_depevt *event) | |
1070 | { | |
1071 | struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; | |
1072 | ||
1073 | __dwc3_ep0_do_control_status(dwc, dep); | |
1074 | } | |
1075 | ||
2e3db064 FB |
1076 | static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) |
1077 | { | |
1078 | struct dwc3_gadget_ep_cmd_params params; | |
1079 | u32 cmd; | |
1080 | int ret; | |
1081 | ||
1082 | if (!dep->resource_index) | |
1083 | return; | |
1084 | ||
1085 | cmd = DWC3_DEPCMD_ENDTRANSFER; | |
1086 | cmd |= DWC3_DEPCMD_CMDIOC; | |
1087 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); | |
1088 | memset(¶ms, 0, sizeof(params)); | |
2cd4718d | 1089 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
2e3db064 FB |
1090 | WARN_ON_ONCE(ret); |
1091 | dep->resource_index = 0; | |
1092 | } | |
1093 | ||
c7fcdeb2 FB |
1094 | static void dwc3_ep0_xfernotready(struct dwc3 *dwc, |
1095 | const struct dwc3_event_depevt *event) | |
1096 | { | |
1097 | switch (event->status) { | |
c7fcdeb2 | 1098 | case DEPEVT_STATUS_CONTROL_DATA: |
55f3fba6 | 1099 | /* |
2e3db064 FB |
1100 | * We already have a DATA transfer in the controller's cache, |
1101 | * if we receive a XferNotReady(DATA) we will ignore it, unless | |
1102 | * it's for the wrong direction. | |
55f3fba6 | 1103 | * |
2e3db064 FB |
1104 | * In that case, we must issue END_TRANSFER command to the Data |
1105 | * Phase we already have started and issue SetStall on the | |
1106 | * control endpoint. | |
55f3fba6 FB |
1107 | */ |
1108 | if (dwc->ep0_expect_in != event->endpoint_number) { | |
2e3db064 FB |
1109 | struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; |
1110 | ||
5eb30ced | 1111 | dev_err(dwc->dev, "unexpected direction for Data Phase\n"); |
2e3db064 | 1112 | dwc3_ep0_end_control_data(dwc, dep); |
55f3fba6 FB |
1113 | dwc3_ep0_stall_and_restart(dwc); |
1114 | return; | |
1115 | } | |
1116 | ||
c7fcdeb2 | 1117 | break; |
1ddcb218 | 1118 | |
c7fcdeb2 | 1119 | case DEPEVT_STATUS_CONTROL_STATUS: |
77fa6df8 FB |
1120 | if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) |
1121 | return; | |
1122 | ||
f0f2b2a2 SAS |
1123 | dwc->ep0state = EP0_STATUS_PHASE; |
1124 | ||
5bdb1dcc SAS |
1125 | if (dwc->delayed_status) { |
1126 | WARN_ON_ONCE(event->endpoint_number != 1); | |
5bdb1dcc SAS |
1127 | return; |
1128 | } | |
1129 | ||
788a23f4 | 1130 | dwc3_ep0_do_control_status(dwc, event); |
72246da4 FB |
1131 | } |
1132 | } | |
1133 | ||
1134 | void dwc3_ep0_interrupt(struct dwc3 *dwc, | |
8becf270 | 1135 | const struct dwc3_event_depevt *event) |
72246da4 | 1136 | { |
72246da4 FB |
1137 | switch (event->endpoint_event) { |
1138 | case DWC3_DEPEVT_XFERCOMPLETE: | |
1139 | dwc3_ep0_xfer_complete(dwc, event); | |
1140 | break; | |
1141 | ||
1142 | case DWC3_DEPEVT_XFERNOTREADY: | |
1143 | dwc3_ep0_xfernotready(dwc, event); | |
1144 | break; | |
1145 | ||
1146 | case DWC3_DEPEVT_XFERINPROGRESS: | |
1147 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
1148 | case DWC3_DEPEVT_STREAMEVT: | |
1149 | case DWC3_DEPEVT_EPCMDCMPLT: | |
1150 | break; | |
1151 | } | |
1152 | } |