[linux-block.git] / drivers / usb / dwc3 / dwc3-xilinx.c

// SPDX-License-Identifier: GPL-2.0
/*
 * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver
 *
 * Authors: Manish Narani <manish.narani@xilinx.com>
 *          Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio/consumer.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/of_address.h>
#include <linux/delay.h>
#include <linux/firmware/xlnx-zynqmp.h>
#include <linux/io.h>

#include <linux/phy/phy.h>

/* USB phy reset mask register */
#define XLNX_USB_PHY_RST_EN			0x001C
#define XLNX_PHY_RST_MASK			0x1

/* Xilinx USB 3.0 IP Register */
#define XLNX_USB_TRAFFIC_ROUTE_CONFIG		0x005C
#define XLNX_USB_TRAFFIC_ROUTE_FPD		0x1

/* Versal USB Reset ID */
#define VERSAL_USB_RESET_ID			0xC104036

#define XLNX_USB_FPD_PIPE_CLK			0x7c
#define PIPE_CLK_DESELECT			1
#define PIPE_CLK_SELECT				0
#define XLNX_USB_FPD_POWER_PRSNT		0x80
#define FPD_POWER_PRSNT_OPTION			BIT(0)

struct dwc3_xlnx {
	int				num_clocks;
	struct clk_bulk_data		*clks;
	struct device			*dev;
	void __iomem			*regs;
	int				(*pltfm_init)(struct dwc3_xlnx *data);
	struct phy			*usb3_phy;
};

static void dwc3_xlnx_mask_phy_rst(struct dwc3_xlnx *priv_data, bool mask)
{
	u32 reg;

	/*
	 * Enable or disable ULPI PHY reset from USB Controller.
	 * This does not actually reset the phy, but just controls
	 * whether USB controller can or cannot reset ULPI PHY.
	 */
	reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN);

	if (mask)
		reg &= ~XLNX_PHY_RST_MASK;
	else
		reg |= XLNX_PHY_RST_MASK;

	writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN);
}

static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data)
{
	struct device		*dev = priv_data->dev;
	int			ret;

	dwc3_xlnx_mask_phy_rst(priv_data, false);

	/* Assert and De-assert reset */
	ret = zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID,
				     PM_RESET_ACTION_ASSERT);
	if (ret < 0) {
		dev_err_probe(dev, ret, "failed to assert Reset\n");
		return ret;
	}

	ret = zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID,
				     PM_RESET_ACTION_RELEASE);
	if (ret < 0) {
		dev_err_probe(dev, ret, "failed to De-assert Reset\n");
		return ret;
	}

	dwc3_xlnx_mask_phy_rst(priv_data, true);

	return 0;
}

static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
{
	struct device		*dev = priv_data->dev;
	struct reset_control	*crst, *hibrst, *apbrst;
	struct gpio_desc	*reset_gpio;
	int			ret = 0;
	u32			reg;

	priv_data->usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
	if (IS_ERR(priv_data->usb3_phy)) {
		ret = PTR_ERR(priv_data->usb3_phy);
		dev_err_probe(dev, ret,
			      "failed to get USB3 PHY\n");
		goto err;
	}

	/*
	 * The following core resets are not required unless a USB3 PHY
	 * is used, and the subsequent register settings are not required
	 * unless a core reset is performed (they should be set properly
	 * by the first-stage boot loader, but may be reverted by a core
	 * reset). They may also break the configuration if USB3 is actually
	 * in use but the usb3-phy entry is missing from the device tree.
	 * Therefore, skip these operations in this case.
	 */
	if (!priv_data->usb3_phy)
		goto skip_usb3_phy;

	crst = devm_reset_control_get_exclusive(dev, "usb_crst");
	if (IS_ERR(crst)) {
		ret = PTR_ERR(crst);
		dev_err_probe(dev, ret,
			      "failed to get core reset signal\n");
		goto err;
	}

	hibrst = devm_reset_control_get_exclusive(dev, "usb_hibrst");
	if (IS_ERR(hibrst)) {
		ret = PTR_ERR(hibrst);
		dev_err_probe(dev, ret,
			      "failed to get hibernation reset signal\n");
		goto err;
	}

	apbrst = devm_reset_control_get_exclusive(dev, "usb_apbrst");
	if (IS_ERR(apbrst)) {
		ret = PTR_ERR(apbrst);
		dev_err_probe(dev, ret,
			      "failed to get APB reset signal\n");
		goto err;
	}

	ret = reset_control_assert(crst);
	if (ret < 0) {
		dev_err(dev, "Failed to assert core reset\n");
		goto err;
	}

	ret = reset_control_assert(hibrst);
	if (ret < 0) {
		dev_err(dev, "Failed to assert hibernation reset\n");
		goto err;
	}

	ret = reset_control_assert(apbrst);
	if (ret < 0) {
		dev_err(dev, "Failed to assert APB reset\n");
		goto err;
	}

	ret = phy_init(priv_data->usb3_phy);
	if (ret < 0) {
		phy_exit(priv_data->usb3_phy);
		goto err;
	}

	ret = reset_control_deassert(apbrst);
	if (ret < 0) {
		dev_err(dev, "Failed to release APB reset\n");
		goto err;
	}

	/* Set PIPE Power Present signal in FPD Power Present Register*/
	writel(FPD_POWER_PRSNT_OPTION, priv_data->regs + XLNX_USB_FPD_POWER_PRSNT);

	/* Set the PIPE Clock Select bit in FPD PIPE Clock register */
	writel(PIPE_CLK_SELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK);

	ret = reset_control_deassert(crst);
	if (ret < 0) {
		dev_err(dev, "Failed to release core reset\n");
		goto err;
	}

	ret = reset_control_deassert(hibrst);
	if (ret < 0) {
		dev_err(dev, "Failed to release hibernation reset\n");
		goto err;
	}

	ret = phy_power_on(priv_data->usb3_phy);
	if (ret < 0) {
		phy_exit(priv_data->usb3_phy);
		goto err;
	}

skip_usb3_phy:
	/* ulpi reset via gpio-modepin or gpio-framework driver */
	reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
	if (IS_ERR(reset_gpio)) {
		return dev_err_probe(dev, PTR_ERR(reset_gpio),
				     "Failed to request reset GPIO\n");
	}

	if (reset_gpio) {
		/* Toggle ulpi to reset the phy. */
		gpiod_set_value_cansleep(reset_gpio, 1);
		usleep_range(5000, 10000);
		gpiod_set_value_cansleep(reset_gpio, 0);
		usleep_range(5000, 10000);
	}

	/*
	 * This routes the USB DMA traffic to go through FPD path instead
	 * of reaching DDR directly. This traffic routing is needed to
	 * make SMMU and CCI work with USB DMA.
	 */
	if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) {
		reg = readl(priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG);
		reg |= XLNX_USB_TRAFFIC_ROUTE_FPD;
		writel(reg, priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG);
	}

err:
	return ret;
}

static const struct of_device_id dwc3_xlnx_of_match[] = {
	{
		.compatible = "xlnx,zynqmp-dwc3",
		.data = &dwc3_xlnx_init_zynqmp,
	},
	{
		.compatible = "xlnx,versal-dwc3",
		.data = &dwc3_xlnx_init_versal,
	},
	{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dwc3_xlnx_of_match);

static int dwc3_xlnx_probe(struct platform_device *pdev)
{
	struct dwc3_xlnx		*priv_data;
	struct device			*dev = &pdev->dev;
	struct device_node		*np = dev->of_node;
	const struct of_device_id	*match;
	void __iomem			*regs;
	int				ret;

	priv_data = devm_kzalloc(dev, sizeof(*priv_data), GFP_KERNEL);
	if (!priv_data)
		return -ENOMEM;

	regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(regs)) {
		ret = PTR_ERR(regs);
		dev_err_probe(dev, ret, "failed to map registers\n");
		return ret;
	}

	match = of_match_node(dwc3_xlnx_of_match, pdev->dev.of_node);

	priv_data->pltfm_init = match->data;
	priv_data->regs = regs;
	priv_data->dev = dev;

	platform_set_drvdata(pdev, priv_data);

	ret = devm_clk_bulk_get_all(priv_data->dev, &priv_data->clks);
	if (ret < 0)
		return ret;

	priv_data->num_clocks = ret;

	ret = clk_bulk_prepare_enable(priv_data->num_clocks, priv_data->clks);
	if (ret)
		return ret;

	ret = priv_data->pltfm_init(priv_data);
	if (ret)
		goto err_clk_put;

	ret = of_platform_populate(np, NULL, NULL, dev);
	if (ret)
		goto err_clk_put;

	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);
	pm_suspend_ignore_children(dev, false);
	pm_runtime_get_sync(dev);

	return 0;

err_clk_put:
	clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks);

	return ret;
}

static int dwc3_xlnx_remove(struct platform_device *pdev)
{
	struct dwc3_xlnx	*priv_data = platform_get_drvdata(pdev);
	struct device		*dev = &pdev->dev;

	of_platform_depopulate(dev);

	clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks);
	priv_data->num_clocks = 0;

	pm_runtime_disable(dev);
	pm_runtime_put_noidle(dev);
	pm_runtime_set_suspended(dev);

	return 0;
}

static int __maybe_unused dwc3_xlnx_runtime_suspend(struct device *dev)
{
	struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);

	clk_bulk_disable(priv_data->num_clocks, priv_data->clks);

	return 0;
}

static int __maybe_unused dwc3_xlnx_runtime_resume(struct device *dev)
{
	struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);

	return clk_bulk_enable(priv_data->num_clocks, priv_data->clks);
}

static int __maybe_unused dwc3_xlnx_runtime_idle(struct device *dev)
{
	pm_runtime_mark_last_busy(dev);
	pm_runtime_autosuspend(dev);

	return 0;
}

static int __maybe_unused dwc3_xlnx_suspend(struct device *dev)
{
	struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);

	phy_exit(priv_data->usb3_phy);

	/* Disable the clocks */
	clk_bulk_disable(priv_data->num_clocks, priv_data->clks);

	return 0;
}

static int __maybe_unused dwc3_xlnx_resume(struct device *dev)
{
	struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
	int ret;

	ret = clk_bulk_enable(priv_data->num_clocks, priv_data->clks);
	if (ret)
		return ret;

	ret = phy_init(priv_data->usb3_phy);
	if (ret < 0)
		return ret;

	ret = phy_power_on(priv_data->usb3_phy);
	if (ret < 0) {
		phy_exit(priv_data->usb3_phy);
		return ret;
	}

	return 0;
}

static const struct dev_pm_ops dwc3_xlnx_dev_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(dwc3_xlnx_suspend, dwc3_xlnx_resume)
	SET_RUNTIME_PM_OPS(dwc3_xlnx_runtime_suspend,
			   dwc3_xlnx_runtime_resume, dwc3_xlnx_runtime_idle)
};

static struct platform_driver dwc3_xlnx_driver = {
	.probe		= dwc3_xlnx_probe,
	.remove		= dwc3_xlnx_remove,
	.driver		= {
		.name		= "dwc3-xilinx",
		.of_match_table	= dwc3_xlnx_of_match,
		.pm		= &dwc3_xlnx_dev_pm_ops,
	},
};

module_platform_driver(dwc3_xlnx_driver);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Xilinx DWC3 controller specific glue driver");
MODULE_AUTHOR("Manish Narani <manish.narani@xilinx.com>");
MODULE_AUTHOR("Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>");
Commit	Line	Data
84770f02	1	// SPDX-License-Identifier: GPL-2.0
3a2a68ec	2	/*
84770f02 MN	3	* dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver
	4	*
	5	* Authors: Manish Narani <manish.narani@xilinx.com>
	6	* Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
	7	*/
	8
	9	#include <linux/module.h>
	10	#include <linux/kernel.h>
	11	#include <linux/slab.h>
	12	#include <linux/clk.h>
	13	#include <linux/of.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/dma-mapping.h>
e498a044	16	#include <linux/gpio/consumer.h>
84770f02 MN	17	#include <linux/of_platform.h>
	18	#include <linux/pm_runtime.h>
	19	#include <linux/reset.h>
	20	#include <linux/of_address.h>
	21	#include <linux/delay.h>
	22	#include <linux/firmware/xlnx-zynqmp.h>
	23	#include <linux/io.h>
	24
	25	#include <linux/phy/phy.h>
	26
	27	/* USB phy reset mask register */
	28	#define XLNX_USB_PHY_RST_EN 0x001C
	29	#define XLNX_PHY_RST_MASK 0x1
	30
	31	/* Xilinx USB 3.0 IP Register */
	32	#define XLNX_USB_TRAFFIC_ROUTE_CONFIG 0x005C
	33	#define XLNX_USB_TRAFFIC_ROUTE_FPD 0x1
	34
	35	/* Versal USB Reset ID */
	36	#define VERSAL_USB_RESET_ID 0xC104036
	37
	38	#define XLNX_USB_FPD_PIPE_CLK 0x7c
	39	#define PIPE_CLK_DESELECT 1
	40	#define PIPE_CLK_SELECT 0
	41	#define XLNX_USB_FPD_POWER_PRSNT 0x80
	42	#define FPD_POWER_PRSNT_OPTION BIT(0)
	43
	44	struct dwc3_xlnx {
	45	int num_clocks;
	46	struct clk_bulk_data *clks;
	47	struct device *dev;
	48	void __iomem *regs;
	49	int (pltfm_init)(struct dwc3_xlnx data);
d6edcdc1	50	struct phy *usb3_phy;
84770f02 MN	51	};
	52
	53	static void dwc3_xlnx_mask_phy_rst(struct dwc3_xlnx *priv_data, bool mask)
	54	{
	55	u32 reg;
	56
	57	/*
	58	* Enable or disable ULPI PHY reset from USB Controller.
	59	* This does not actually reset the phy, but just controls
	60	* whether USB controller can or cannot reset ULPI PHY.
	61	*/
	62	reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN);
	63
	64	if (mask)
	65	reg &= ~XLNX_PHY_RST_MASK;
	66	else
	67	reg \|= XLNX_PHY_RST_MASK;
	68
	69	writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN);
	70	}
	71
	72	static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data)
	73	{
	74	struct device *dev = priv_data->dev;
	75	int ret;
	76
	77	dwc3_xlnx_mask_phy_rst(priv_data, false);
	78
	79	/* Assert and De-assert reset */
	80	ret = zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID,
	81	PM_RESET_ACTION_ASSERT);
	82	if (ret < 0) {
	83	dev_err_probe(dev, ret, "failed to assert Reset\n");
	84	return ret;
	85	}
	86
	87	ret = zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID,
	88	PM_RESET_ACTION_RELEASE);
	89	if (ret < 0) {
	90	dev_err_probe(dev, ret, "failed to De-assert Reset\n");
	91	return ret;
	92	}
	93
	94	dwc3_xlnx_mask_phy_rst(priv_data, true);
	95
	96	return 0;
	97	}
	98
	99	static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
	100	{
	101	struct device *dev = priv_data->dev;
	102	struct reset_control crst, hibrst, *apbrst;
ca05b382	103	struct gpio_desc *reset_gpio;
b470947c	104	int ret = 0;
84770f02 MN	105	u32 reg;
84770f02 MN	106
d6edcdc1 PM	107	priv_data->usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
	108	if (IS_ERR(priv_data->usb3_phy)) {
	109	ret = PTR_ERR(priv_data->usb3_phy);
2cc9b1c9 RH	110	dev_err_probe(dev, ret,
2cc9b1c9 RH	111	"failed to get USB3 PHY\n");
84770f02	112	goto err;
84770f02 MN	113	}
84770f02 MN	114
9678f336 RH	115	/*
	116	* The following core resets are not required unless a USB3 PHY
	117	* is used, and the subsequent register settings are not required
	118	* unless a core reset is performed (they should be set properly
	119	* by the first-stage boot loader, but may be reverted by a core
	120	* reset). They may also break the configuration if USB3 is actually
	121	* in use but the usb3-phy entry is missing from the device tree.
	122	* Therefore, skip these operations in this case.
	123	*/
d6edcdc1	124	if (!priv_data->usb3_phy)
9678f336 RH	125	goto skip_usb3_phy;
9678f336 RH	126
84770f02 MN	127	crst = devm_reset_control_get_exclusive(dev, "usb_crst");
	128	if (IS_ERR(crst)) {
	129	ret = PTR_ERR(crst);
	130	dev_err_probe(dev, ret,
	131	"failed to get core reset signal\n");
	132	goto err;
	133	}
	134
	135	hibrst = devm_reset_control_get_exclusive(dev, "usb_hibrst");
	136	if (IS_ERR(hibrst)) {
	137	ret = PTR_ERR(hibrst);
	138	dev_err_probe(dev, ret,
	139	"failed to get hibernation reset signal\n");
	140	goto err;
	141	}
	142
	143	apbrst = devm_reset_control_get_exclusive(dev, "usb_apbrst");
	144	if (IS_ERR(apbrst)) {
	145	ret = PTR_ERR(apbrst);
	146	dev_err_probe(dev, ret,
	147	"failed to get APB reset signal\n");
	148	goto err;
	149	}
	150
	151	ret = reset_control_assert(crst);
	152	if (ret < 0) {
	153	dev_err(dev, "Failed to assert core reset\n");
	154	goto err;
	155	}
	156
	157	ret = reset_control_assert(hibrst);
	158	if (ret < 0) {
	159	dev_err(dev, "Failed to assert hibernation reset\n");
	160	goto err;
	161	}
	162
	163	ret = reset_control_assert(apbrst);
	164	if (ret < 0) {
	165	dev_err(dev, "Failed to assert APB reset\n");
	166	goto err;
	167	}
	168
d6edcdc1	169	ret = phy_init(priv_data->usb3_phy);
84770f02	170	if (ret < 0) {
d6edcdc1	171	phy_exit(priv_data->usb3_phy);
84770f02 MN	172	goto err;
	173	}
	174
	175	ret = reset_control_deassert(apbrst);
	176	if (ret < 0) {
	177	dev_err(dev, "Failed to release APB reset\n");
	178	goto err;
	179	}
	180
	181	/* Set PIPE Power Present signal in FPD Power Present Register*/
	182	writel(FPD_POWER_PRSNT_OPTION, priv_data->regs + XLNX_USB_FPD_POWER_PRSNT);
	183
	184	/* Set the PIPE Clock Select bit in FPD PIPE Clock register */
	185	writel(PIPE_CLK_SELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK);
	186
	187	ret = reset_control_deassert(crst);
	188	if (ret < 0) {
	189	dev_err(dev, "Failed to release core reset\n");
	190	goto err;
	191	}
	192
	193	ret = reset_control_deassert(hibrst);
	194	if (ret < 0) {
	195	dev_err(dev, "Failed to release hibernation reset\n");
	196	goto err;
	197	}
	198
d6edcdc1	199	ret = phy_power_on(priv_data->usb3_phy);
84770f02	200	if (ret < 0) {
d6edcdc1	201	phy_exit(priv_data->usb3_phy);
84770f02 MN	202	goto err;
	203	}
	204
9678f336	205	skip_usb3_phy:
ca05b382 PM	206	/* ulpi reset via gpio-modepin or gpio-framework driver */
	207	reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
	208	if (IS_ERR(reset_gpio)) {
	209	return dev_err_probe(dev, PTR_ERR(reset_gpio),
	210	"Failed to request reset GPIO\n");
	211	}
	212
	213	if (reset_gpio) {
	214	/* Toggle ulpi to reset the phy. */
	215	gpiod_set_value_cansleep(reset_gpio, 1);
	216	usleep_range(5000, 10000);
	217	gpiod_set_value_cansleep(reset_gpio, 0);
	218	usleep_range(5000, 10000);
	219	}
	220
84770f02 MN	221	/*
	222	* This routes the USB DMA traffic to go through FPD path instead
	223	* of reaching DDR directly. This traffic routing is needed to
	224	* make SMMU and CCI work with USB DMA.
	225	*/
	226	if (of_dma_is_coherent(dev->of_node) \|\| device_iommu_mapped(dev)) {
	227	reg = readl(priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG);
	228	reg \|= XLNX_USB_TRAFFIC_ROUTE_FPD;
	229	writel(reg, priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG);
	230	}
	231
	232	err:
	233	return ret;
	234	}
	235
	236	static const struct of_device_id dwc3_xlnx_of_match[] = {
	237	{
	238	.compatible = "xlnx,zynqmp-dwc3",
	239	.data = &dwc3_xlnx_init_zynqmp,
	240	},
	241	{
	242	.compatible = "xlnx,versal-dwc3",
	243	.data = &dwc3_xlnx_init_versal,
	244	},
	245	{ /* Sentinel */ }
	246	};
	247	MODULE_DEVICE_TABLE(of, dwc3_xlnx_of_match);
	248
	249	static int dwc3_xlnx_probe(struct platform_device *pdev)
	250	{
	251	struct dwc3_xlnx *priv_data;
	252	struct device *dev = &pdev->dev;
	253	struct device_node *np = dev->of_node;
	254	const struct of_device_id *match;
	255	void __iomem *regs;
	256	int ret;
	257
	258	priv_data = devm_kzalloc(dev, sizeof(*priv_data), GFP_KERNEL);
	259	if (!priv_data)
	260	return -ENOMEM;
	261
	262	regs = devm_platform_ioremap_resource(pdev, 0);
	263	if (IS_ERR(regs)) {
	264	ret = PTR_ERR(regs);
	265	dev_err_probe(dev, ret, "failed to map registers\n");
	266	return ret;
	267	}
	268
	269	match = of_match_node(dwc3_xlnx_of_match, pdev->dev.of_node);
	270
	271	priv_data->pltfm_init = match->data;
	272	priv_data->regs = regs;
	273	priv_data->dev = dev;
	274
	275	platform_set_drvdata(pdev, priv_data);
	276
	277	ret = devm_clk_bulk_get_all(priv_data->dev, &priv_data->clks);
	278	if (ret < 0)
	279	return ret;
	280
	281	priv_data->num_clocks = ret;
	282
	283	ret = clk_bulk_prepare_enable(priv_data->num_clocks, priv_data->clks);
	284	if (ret)
285	return ret;
286
287	ret = priv_data->pltfm_init(priv_data);
288	if (ret)
289	goto err_clk_put;
290
291	ret = of_platform_populate(np, NULL, NULL, dev);
292	if (ret)
293	goto err_clk_put;
294
295	pm_runtime_set_active(dev);
296	pm_runtime_enable(dev);
297	pm_suspend_ignore_children(dev, false);
298	pm_runtime_get_sync(dev);
299
300	return 0;
301
302	err_clk_put:
303	clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks);
84770f02 MN	304
	305	return ret;
	306	}
	307
	308	static int dwc3_xlnx_remove(struct platform_device *pdev)
	309	{
	310	struct dwc3_xlnx *priv_data = platform_get_drvdata(pdev);
	311	struct device *dev = &pdev->dev;
	312
	313	of_platform_depopulate(dev);
	314
	315	clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks);
84770f02 MN	316	priv_data->num_clocks = 0;
	317
	318	pm_runtime_disable(dev);
	319	pm_runtime_put_noidle(dev);
	320	pm_runtime_set_suspended(dev);
	321
	322	return 0;
	323	}
	324
ec50e114	325	static int __maybe_unused dwc3_xlnx_runtime_suspend(struct device *dev)
84770f02 MN	326	{
	327	struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
	328
	329	clk_bulk_disable(priv_data->num_clocks, priv_data->clks);
	330
	331	return 0;
	332	}
	333
ec50e114	334	static int __maybe_unused dwc3_xlnx_runtime_resume(struct device *dev)
84770f02 MN	335	{
	336	struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
	337
	338	return clk_bulk_enable(priv_data->num_clocks, priv_data->clks);
	339	}
	340
	341	static int __maybe_unused dwc3_xlnx_runtime_idle(struct device *dev)
	342	{
	343	pm_runtime_mark_last_busy(dev);
	344	pm_runtime_autosuspend(dev);
	345
	346	return 0;
	347	}
	348
ec50e114 PM	349	static int __maybe_unused dwc3_xlnx_suspend(struct device *dev)
	350	{
	351	struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
	352
d6edcdc1 PM	353	phy_exit(priv_data->usb3_phy);
d6edcdc1 PM	354
ec50e114 PM	355	/* Disable the clocks */
	356	clk_bulk_disable(priv_data->num_clocks, priv_data->clks);
	357
	358	return 0;
	359	}
	360
	361	static int __maybe_unused dwc3_xlnx_resume(struct device *dev)
	362	{
	363	struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
	364	int ret;
	365
	366	ret = clk_bulk_enable(priv_data->num_clocks, priv_data->clks);
	367	if (ret)
	368	return ret;
	369
d6edcdc1 PM	370	ret = phy_init(priv_data->usb3_phy);
	371	if (ret < 0)
	372	return ret;
	373
	374	ret = phy_power_on(priv_data->usb3_phy);
	375	if (ret < 0) {
	376	phy_exit(priv_data->usb3_phy);
	377	return ret;
	378	}
	379
ec50e114 PM	380	return 0;
	381	}
	382
	383	static const struct dev_pm_ops dwc3_xlnx_dev_pm_ops = {
	384	SET_SYSTEM_SLEEP_PM_OPS(dwc3_xlnx_suspend, dwc3_xlnx_resume)
	385	SET_RUNTIME_PM_OPS(dwc3_xlnx_runtime_suspend,
	386	dwc3_xlnx_runtime_resume, dwc3_xlnx_runtime_idle)
	387	};
84770f02 MN	388
	389	static struct platform_driver dwc3_xlnx_driver = {
	390	.probe = dwc3_xlnx_probe,
	391	.remove = dwc3_xlnx_remove,
	392	.driver = {
	393	.name = "dwc3-xilinx",
	394	.of_match_table = dwc3_xlnx_of_match,
	395	.pm = &dwc3_xlnx_dev_pm_ops,
	396	},
	397	};
	398
	399	module_platform_driver(dwc3_xlnx_driver);
	400
	401	MODULE_LICENSE("GPL v2");
	402	MODULE_DESCRIPTION("Xilinx DWC3 controller specific glue driver");
	403	MODULE_AUTHOR("Manish Narani <manish.narani@xilinx.com>");
	404	MODULE_AUTHOR("Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>");