[linux-block.git] / drivers / usb / dwc3 / dwc3-pci.c

// SPDX-License-Identifier: GPL-2.0
/**
 * dwc3-pci.c - PCI Specific glue layer
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Felipe Balbi <balbi@ti.com>,
 *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/workqueue.h>
#include <linux/pm_runtime.h>
#include <linux/platform_device.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/machine.h>
#include <linux/acpi.h>
#include <linux/delay.h>

#define PCI_DEVICE_ID_INTEL_BYT			0x0f37
#define PCI_DEVICE_ID_INTEL_MRFLD		0x119e
#define PCI_DEVICE_ID_INTEL_BSW			0x22b7
#define PCI_DEVICE_ID_INTEL_SPTLP		0x9d30
#define PCI_DEVICE_ID_INTEL_SPTH		0xa130
#define PCI_DEVICE_ID_INTEL_BXT			0x0aaa
#define PCI_DEVICE_ID_INTEL_BXT_M		0x1aaa
#define PCI_DEVICE_ID_INTEL_APL			0x5aaa
#define PCI_DEVICE_ID_INTEL_KBP			0xa2b0
#define PCI_DEVICE_ID_INTEL_CMLLP		0x02ee
#define PCI_DEVICE_ID_INTEL_CMLH		0x06ee
#define PCI_DEVICE_ID_INTEL_GLK			0x31aa
#define PCI_DEVICE_ID_INTEL_CNPLP		0x9dee
#define PCI_DEVICE_ID_INTEL_CNPH		0xa36e
#define PCI_DEVICE_ID_INTEL_ICLLP		0x34ee
#define PCI_DEVICE_ID_INTEL_EHLLP		0x4b7e
#define PCI_DEVICE_ID_INTEL_TGPLP		0xa0ee

#define PCI_INTEL_BXT_DSM_GUID		"732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
#define PCI_INTEL_BXT_FUNC_PMU_PWR	4
#define PCI_INTEL_BXT_STATE_D0		0
#define PCI_INTEL_BXT_STATE_D3		3

#define GP_RWBAR			1
#define GP_RWREG1			0xa0
#define GP_RWREG1_ULPI_REFCLK_DISABLE	(1 << 17)

/**
 * struct dwc3_pci - Driver private structure
 * @dwc3: child dwc3 platform_device
 * @pci: our link to PCI bus
 * @guid: _DSM GUID
 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
 * @wakeup_work: work for asynchronous resume
 */
struct dwc3_pci {
	struct platform_device *dwc3;
	struct pci_dev *pci;

	guid_t guid;

	unsigned int has_dsm_for_pm:1;
	struct work_struct wakeup_work;
};

static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
static const struct acpi_gpio_params cs_gpios = { 1, 0, false };

static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
	{ "reset-gpios", &reset_gpios, 1 },
	{ "cs-gpios", &cs_gpios, 1 },
	{ },
};

static struct gpiod_lookup_table platform_bytcr_gpios = {
	.dev_id		= "0000:00:16.0",
	.table		= {
		GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH),
		GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH),
		{}
	},
};

static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
{
	void __iomem	*reg;
	u32		value;

	reg = pcim_iomap(pci, GP_RWBAR, 0);
	if (!reg)
		return -ENOMEM;

	value = readl(reg + GP_RWREG1);
	if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
		goto unmap; /* ULPI refclk already enabled */

	value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
	writel(value, reg + GP_RWREG1);
	/* This comes from the Intel Android x86 tree w/o any explanation */
	msleep(100);
unmap:
	pcim_iounmap(pci, reg);
	return 0;
}

static const struct property_entry dwc3_pci_intel_properties[] = {
	PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
	PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
	{}
};

static const struct property_entry dwc3_pci_mrfld_properties[] = {
	PROPERTY_ENTRY_STRING("dr_mode", "otg"),
	PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
	{}
};

static const struct property_entry dwc3_pci_amd_properties[] = {
	PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
	PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
	PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
	PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
	PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
	PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
	PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
	PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
	PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
	PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
	PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
	/* FIXME these quirks should be removed when AMD NL tapes out */
	PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
	PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
	PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
	PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
	{}
};

static int dwc3_pci_quirks(struct dwc3_pci *dwc)
{
	struct pci_dev			*pdev = dwc->pci;

	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
		if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
				pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) {
			guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
			dwc->has_dsm_for_pm = true;
		}

		if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
			struct gpio_desc *gpio;
			int ret;

			/* On BYT the FW does not always enable the refclock */
			ret = dwc3_byt_enable_ulpi_refclock(pdev);
			if (ret)
				return ret;

			ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
					acpi_dwc3_byt_gpios);
			if (ret)
				dev_dbg(&pdev->dev, "failed to add mapping table\n");

			/*
			 * A lot of BYT devices lack ACPI resource entries for
			 * the GPIOs, add a fallback mapping to the reference
			 * design GPIOs which all boards seem to use.
			 */
			gpiod_add_lookup_table(&platform_bytcr_gpios);

			/*
			 * These GPIOs will turn on the USB2 PHY. Note that we have to
			 * put the gpio descriptors again here because the phy driver
			 * might want to grab them, too.
			 */
			gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
			if (IS_ERR(gpio))
				return PTR_ERR(gpio);

			gpiod_set_value_cansleep(gpio, 1);
			gpiod_put(gpio);

			gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
			if (IS_ERR(gpio))
				return PTR_ERR(gpio);

			if (gpio) {
				gpiod_set_value_cansleep(gpio, 1);
				gpiod_put(gpio);
				usleep_range(10000, 11000);
			}
		}
	}

	return 0;
}

#ifdef CONFIG_PM
static void dwc3_pci_resume_work(struct work_struct *work)
{
	struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
	struct platform_device *dwc3 = dwc->dwc3;
	int ret;

	ret = pm_runtime_get_sync(&dwc3->dev);
	if (ret)
		return;

	pm_runtime_mark_last_busy(&dwc3->dev);
	pm_runtime_put_sync_autosuspend(&dwc3->dev);
}
#endif

static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
{
	struct property_entry *p = (struct property_entry *)id->driver_data;
	struct dwc3_pci		*dwc;
	struct resource		res[2];
	int			ret;
	struct device		*dev = &pci->dev;

	ret = pcim_enable_device(pci);
	if (ret) {
		dev_err(dev, "failed to enable pci device\n");
		return -ENODEV;
	}

	pci_set_master(pci);

	dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
	if (!dwc)
		return -ENOMEM;

	dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
	if (!dwc->dwc3)
		return -ENOMEM;

	memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));

	res[0].start	= pci_resource_start(pci, 0);
	res[0].end	= pci_resource_end(pci, 0);
	res[0].name	= "dwc_usb3";
	res[0].flags	= IORESOURCE_MEM;

	res[1].start	= pci->irq;
	res[1].name	= "dwc_usb3";
	res[1].flags	= IORESOURCE_IRQ;

	ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
	if (ret) {
		dev_err(dev, "couldn't add resources to dwc3 device\n");
		goto err;
	}

	dwc->pci = pci;
	dwc->dwc3->dev.parent = dev;
	ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));

	ret = platform_device_add_properties(dwc->dwc3, p);
	if (ret < 0)
		goto err;

	ret = dwc3_pci_quirks(dwc);
	if (ret)
		goto err;

	ret = platform_device_add(dwc->dwc3);
	if (ret) {
		dev_err(dev, "failed to register dwc3 device\n");
		goto err;
	}

	device_init_wakeup(dev, true);
	pci_set_drvdata(pci, dwc);
	pm_runtime_put(dev);
#ifdef CONFIG_PM
	INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
#endif

	return 0;
err:
	platform_device_put(dwc->dwc3);
	return ret;
}

static void dwc3_pci_remove(struct pci_dev *pci)
{
	struct dwc3_pci		*dwc = pci_get_drvdata(pci);
	struct pci_dev		*pdev = dwc->pci;

	if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
		gpiod_remove_lookup_table(&platform_bytcr_gpios);
#ifdef CONFIG_PM
	cancel_work_sync(&dwc->wakeup_work);
#endif
	device_init_wakeup(&pci->dev, false);
	pm_runtime_get(&pci->dev);
	platform_device_unregister(dwc->dwc3);
}

static const struct pci_device_id dwc3_pci_id_table[] = {
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
	  (kernel_ulong_t) &dwc3_pci_intel_properties },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
	  (kernel_ulong_t) &dwc3_pci_mrfld_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHLLP),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
	  (kernel_ulong_t) &dwc3_pci_amd_properties, },
	{  }	/* Terminating Entry */
};
MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);

#if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
{
	union acpi_object *obj;
	union acpi_object tmp;
	union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);

	if (!dwc->has_dsm_for_pm)
		return 0;

	tmp.type = ACPI_TYPE_INTEGER;
	tmp.integer.value = param;

	obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
			1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
	if (!obj) {
		dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
		return -EIO;
	}

	ACPI_FREE(obj);

	return 0;
}
#endif /* CONFIG_PM || CONFIG_PM_SLEEP */

#ifdef CONFIG_PM
static int dwc3_pci_runtime_suspend(struct device *dev)
{
	struct dwc3_pci		*dwc = dev_get_drvdata(dev);

	if (device_can_wakeup(dev))
		return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);

	return -EBUSY;
}

static int dwc3_pci_runtime_resume(struct device *dev)
{
	struct dwc3_pci		*dwc = dev_get_drvdata(dev);
	int			ret;

	ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
	if (ret)
		return ret;

	queue_work(pm_wq, &dwc->wakeup_work);

	return 0;
}
#endif /* CONFIG_PM */

#ifdef CONFIG_PM_SLEEP
static int dwc3_pci_suspend(struct device *dev)
{
	struct dwc3_pci		*dwc = dev_get_drvdata(dev);

	return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
}

static int dwc3_pci_resume(struct device *dev)
{
	struct dwc3_pci		*dwc = dev_get_drvdata(dev);

	return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
}
#endif /* CONFIG_PM_SLEEP */

static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
	SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
		NULL)
};

static struct pci_driver dwc3_pci_driver = {
	.name		= "dwc3-pci",
	.id_table	= dwc3_pci_id_table,
	.probe		= dwc3_pci_probe,
	.remove		= dwc3_pci_remove,
	.driver		= {
		.pm	= &dwc3_pci_dev_pm_ops,
	}
};

MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");

module_pci_driver(dwc3_pci_driver);
Commit	Line	Data
5fd54ace	1	// SPDX-License-Identifier: GPL-2.0
72246da4 FB	2	/**
	3	* dwc3-pci.c - PCI Specific glue layer
	4	*
	5	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4 FB	6	*
	7	* Authors: Felipe Balbi <balbi@ti.com>,
	8	* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
72246da4 FB	9	*/
	10
	11	#include <linux/kernel.h>
46a57283	12	#include <linux/module.h>
72246da4 FB	13	#include <linux/slab.h>
72246da4 FB	14	#include <linux/pci.h>
8eed00b2	15	#include <linux/workqueue.h>
e9af9229	16	#include <linux/pm_runtime.h>
72246da4	17	#include <linux/platform_device.h>
a89d977c	18	#include <linux/gpio/consumer.h>
5741022c	19	#include <linux/gpio/machine.h>
a89d977c	20	#include <linux/acpi.h>
cf48305d	21	#include <linux/delay.h>
8f317b47	22
9a5a0783 JY	23	#define PCI_DEVICE_ID_INTEL_BYT 0x0f37
	24	#define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
	25	#define PCI_DEVICE_ID_INTEL_BSW 0x22b7
	26	#define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
	27	#define PCI_DEVICE_ID_INTEL_SPTH 0xa130
b4c580a4	28	#define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
1ffb4d5c	29	#define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
b4c580a4	30	#define PCI_DEVICE_ID_INTEL_APL 0x5aaa
4491ed50	31	#define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
3c3caae4 HK	32	#define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee
3c3caae4 HK	33	#define PCI_DEVICE_ID_INTEL_CMLH 0x06ee
8f8983a5	34	#define PCI_DEVICE_ID_INTEL_GLK 0x31aa
68217959 HK	35	#define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
68217959 HK	36	#define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
00908693	37	#define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee
dbb0569d	38	#define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e
b3649dee	39	#define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee
72246da4	40
94116f81	41	#define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
9cecca75 FB	42	#define PCI_INTEL_BXT_FUNC_PMU_PWR 4
	43	#define PCI_INTEL_BXT_STATE_D0 0
	44	#define PCI_INTEL_BXT_STATE_D3 3
	45
7740d04d HG	46	#define GP_RWBAR 1
	47	#define GP_RWREG1 0xa0
	48	#define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
	49
0f817ae6 FB	50	/**
	51	* struct dwc3_pci - Driver private structure
	52	* @dwc3: child dwc3 platform_device
	53	* @pci: our link to PCI bus
94116f81	54	* @guid: _DSM GUID
9cecca75	55	* @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
87d852de	56	* @wakeup_work: work for asynchronous resume
0f817ae6 FB	57	*/
	58	struct dwc3_pci {
	59	struct platform_device *dwc3;
	60	struct pci_dev *pci;
9cecca75	61
94116f81	62	guid_t guid;
9cecca75 FB	63
9cecca75 FB	64	unsigned int has_dsm_for_pm:1;
8eed00b2	65	struct work_struct wakeup_work;
0f817ae6 FB	66	};
0f817ae6 FB	67
a89d977c HK	68	static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
	69	static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
	70
	71	static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
	72	{ "reset-gpios", &reset_gpios, 1 },
	73	{ "cs-gpios", &cs_gpios, 1 },
	74	{ },
	75	};
	76
5741022c HG	77	static struct gpiod_lookup_table platform_bytcr_gpios = {
	78	.dev_id = "0000:00:16.0",
	79	.table = {
	80	GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH),
	81	GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH),
	82	{}
	83	},
	84	};
	85
7740d04d HG	86	static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
	87	{
	88	void __iomem *reg;
	89	u32 value;
	90
	91	reg = pcim_iomap(pci, GP_RWBAR, 0);
b497fff6 WY	92	if (!reg)
b497fff6 WY	93	return -ENOMEM;
7740d04d HG	94
	95	value = readl(reg + GP_RWREG1);
	96	if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
	97	goto unmap; /* ULPI refclk already enabled */
	98
	99	value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
	100	writel(value, reg + GP_RWREG1);
	101	/* This comes from the Intel Android x86 tree w/o any explanation */
	102	msleep(100);
	103	unmap:
	104	pcim_iounmap(pci, reg);
	105	return 0;
	106	}
	107
1a7b12f6 AS	108	static const struct property_entry dwc3_pci_intel_properties[] = {
	109	PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
	110	PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
	111	{}
	112	};
	113
c31d983b AS	114	static const struct property_entry dwc3_pci_mrfld_properties[] = {
	115	PROPERTY_ENTRY_STRING("dr_mode", "otg"),
	116	PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
	117	{}
	118	};
	119
1a7b12f6 AS	120	static const struct property_entry dwc3_pci_amd_properties[] = {
	121	PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
	122	PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
	123	PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
	124	PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
	125	PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
	126	PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
	127	PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
	128	PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
	129	PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
	130	PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
	131	PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
	132	/* FIXME these quirks should be removed when AMD NL tapes out */
	133	PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
	134	PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
	135	PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
	136	PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
	137	{}
	138	};
	139
0f817ae6	140	static int dwc3_pci_quirks(struct dwc3_pci *dwc)
2cd9ddf7	141	{
0f817ae6 FB	142	struct pci_dev *pdev = dwc->pci;
0f817ae6 FB	143
e6fe66fe	144	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
9cecca75 FB	145	if (pdev->device == PCI_DEVICE_ID_INTEL_BXT \|\|
9cecca75 FB	146	pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) {
94116f81	147	guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
9cecca75 FB	148	dwc->has_dsm_for_pm = true;
	149	}
	150
e6fe66fe FB	151	if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
e6fe66fe FB	152	struct gpio_desc *gpio;
1a7b12f6	153	int ret;
e6fe66fe	154
7740d04d HG	155	/* On BYT the FW does not always enable the refclock */
	156	ret = dwc3_byt_enable_ulpi_refclock(pdev);
	157	if (ret)
	158	return ret;
	159
4a56e413	160	ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
e6fe66fe	161	acpi_dwc3_byt_gpios);
4a56e413 AS	162	if (ret)
4a56e413 AS	163	dev_dbg(&pdev->dev, "failed to add mapping table\n");
e6fe66fe	164
5741022c HG	165	/*
	166	* A lot of BYT devices lack ACPI resource entries for
	167	* the GPIOs, add a fallback mapping to the reference
	168	* design GPIOs which all boards seem to use.
	169	*/
	170	gpiod_add_lookup_table(&platform_bytcr_gpios);
	171
e6fe66fe FB	172	/*
	173	* These GPIOs will turn on the USB2 PHY. Note that we have to
	174	* put the gpio descriptors again here because the phy driver
	175	* might want to grab them, too.
	176	*/
3004cfd6	177	gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
e6fe66fe FB	178	if (IS_ERR(gpio))
	179	return PTR_ERR(gpio);
	180
a89d977c	181	gpiod_set_value_cansleep(gpio, 1);
3004cfd6	182	gpiod_put(gpio);
e6fe66fe	183
3004cfd6	184	gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
e6fe66fe FB	185	if (IS_ERR(gpio))
	186	return PTR_ERR(gpio);
	187
	188	if (gpio) {
	189	gpiod_set_value_cansleep(gpio, 1);
3004cfd6	190	gpiod_put(gpio);
e6fe66fe FB	191	usleep_range(10000, 11000);
e6fe66fe FB	192	}
a89d977c HK	193	}
	194	}
	195
2cd9ddf7 HK	196	return 0;
2cd9ddf7 HK	197	}
72246da4	198
8eed00b2 MG	199	#ifdef CONFIG_PM
	200	static void dwc3_pci_resume_work(struct work_struct *work)
	201	{
	202	struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
	203	struct platform_device *dwc3 = dwc->dwc3;
	204	int ret;
	205
	206	ret = pm_runtime_get_sync(&dwc3->dev);
	207	if (ret)
	208	return;
	209
	210	pm_runtime_mark_last_busy(&dwc3->dev);
	211	pm_runtime_put_sync_autosuspend(&dwc3->dev);
	212	}
	213	#endif
	214
1a7b12f6	215	static int dwc3_pci_probe(struct pci_dev pci, const struct pci_device_id id)
72246da4	216	{
1a7b12f6	217	struct property_entry p = (struct property_entry )id->driver_data;
0f817ae6	218	struct dwc3_pci *dwc;
72246da4	219	struct resource res[2];
b09e99ee	220	int ret;
802ca850	221	struct device *dev = &pci->dev;
72246da4	222
f1c7e710	223	ret = pcim_enable_device(pci);
72246da4	224	if (ret) {
802ca850 CP	225	dev_err(dev, "failed to enable pci device\n");
802ca850 CP	226	return -ENODEV;
72246da4 FB	227	}
72246da4 FB	228
72246da4 FB	229	pci_set_master(pci);
72246da4 FB	230
0f817ae6 FB	231	dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
	232	if (!dwc)
	233	return -ENOMEM;
	234
	235	dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
	236	if (!dwc->dwc3)
f1c7e710	237	return -ENOMEM;
72246da4 FB	238
	239	memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
	240
	241	res[0].start = pci_resource_start(pci, 0);
	242	res[0].end = pci_resource_end(pci, 0);
	243	res[0].name = "dwc_usb3";
	244	res[0].flags = IORESOURCE_MEM;
	245
	246	res[1].start = pci->irq;
	247	res[1].name = "dwc_usb3";
	248	res[1].flags = IORESOURCE_IRQ;
	249
0f817ae6	250	ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
72246da4	251	if (ret) {
802ca850	252	dev_err(dev, "couldn't add resources to dwc3 device\n");
cabdf83d	253	goto err;
72246da4 FB	254	}
72246da4 FB	255
0f817ae6 FB	256	dwc->pci = pci;
	257	dwc->dwc3->dev.parent = dev;
	258	ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
72246da4	259
1a7b12f6 AS	260	ret = platform_device_add_properties(dwc->dwc3, p);
1a7b12f6 AS	261	if (ret < 0)
9bbfceea	262	goto err;
1a7b12f6	263
0f817ae6	264	ret = dwc3_pci_quirks(dwc);
474799f0 HK	265	if (ret)
	266	goto err;
	267
0f817ae6	268	ret = platform_device_add(dwc->dwc3);
72246da4	269	if (ret) {
802ca850	270	dev_err(dev, "failed to register dwc3 device\n");
2cd9ddf7	271	goto err;
72246da4 FB	272	}
72246da4 FB	273
e9af9229	274	device_init_wakeup(dev, true);
0f817ae6	275	pci_set_drvdata(pci, dwc);
e9af9229	276	pm_runtime_put(dev);
8eed00b2 MG	277	#ifdef CONFIG_PM
	278	INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
	279	#endif
e9af9229	280
72246da4	281	return 0;
2cd9ddf7	282	err:
0f817ae6	283	platform_device_put(dwc->dwc3);
72246da4 FB	284	return ret;
	285	}
	286
fb4e98ab	287	static void dwc3_pci_remove(struct pci_dev *pci)
72246da4	288	{
0f817ae6	289	struct dwc3_pci *dwc = pci_get_drvdata(pci);
7b412b04	290	struct pci_dev *pdev = dwc->pci;
0f817ae6	291
7b412b04 KS	292	if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
7b412b04 KS	293	gpiod_remove_lookup_table(&platform_bytcr_gpios);
8eed00b2 MG	294	#ifdef CONFIG_PM
	295	cancel_work_sync(&dwc->wakeup_work);
	296	#endif
e9af9229 FB	297	device_init_wakeup(&pci->dev, false);
e9af9229 FB	298	pm_runtime_get(&pci->dev);
0f817ae6	299	platform_device_unregister(dwc->dwc3);
72246da4 FB	300	}
72246da4 FB	301
782df20c	302	static const struct pci_device_id dwc3_pci_id_table[] = {
1a7b12f6 AS	303	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
	304	(kernel_ulong_t) &dwc3_pci_intel_properties },
	305
	306	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
	307	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	308
	309	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
c31d983b	310	(kernel_ulong_t) &dwc3_pci_mrfld_properties, },
1a7b12f6	311
3c3caae4 HK	312	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP),
	313	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	314
7ae622c9 FB	315	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH),
	316	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	317
1a7b12f6 AS	318	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
	319	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	320
	321	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
	322	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	323
	324	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
	325	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	326
	327	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
	328	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	329
	330	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
	331	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	332
	333	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
	334	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	335
	336	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
	337	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	338
	339	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
	340	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	341
	342	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
	343	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	344
	345	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
	346	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	347
dbb0569d FB	348	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHLLP),
	349	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	350
b3649dee FB	351	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP),
	352	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	353
1a7b12f6 AS	354	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
1a7b12f6 AS	355	(kernel_ulong_t) &dwc3_pci_amd_properties, },
72246da4 FB	356	{ } /* Terminating Entry */
	357	};
	358	MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
	359
36daf3aa FB	360	#if defined(CONFIG_PM) \|\| defined(CONFIG_PM_SLEEP)
	361	static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
	362	{
	363	union acpi_object *obj;
	364	union acpi_object tmp;
	365	union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
	366
	367	if (!dwc->has_dsm_for_pm)
	368	return 0;
	369
	370	tmp.type = ACPI_TYPE_INTEGER;
	371	tmp.integer.value = param;
	372
94116f81	373	obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
36daf3aa FB	374	1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
	375	if (!obj) {
	376	dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
	377	return -EIO;
	378	}
	379
	380	ACPI_FREE(obj);
	381
	382	return 0;
	383	}
	384	#endif /* CONFIG_PM \|\| CONFIG_PM_SLEEP */
	385
e9af9229 FB	386	#ifdef CONFIG_PM
	387	static int dwc3_pci_runtime_suspend(struct device *dev)
	388	{
9cecca75 FB	389	struct dwc3_pci *dwc = dev_get_drvdata(dev);
9cecca75 FB	390
de3ef1eb	391	if (device_can_wakeup(dev))
9cecca75	392	return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
e9af9229 FB	393
	394	return -EBUSY;
	395	}
	396
f6c274e1 FB	397	static int dwc3_pci_runtime_resume(struct device *dev)
f6c274e1 FB	398	{
0f817ae6	399	struct dwc3_pci *dwc = dev_get_drvdata(dev);
9cecca75 FB	400	int ret;
	401
	402	ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
	403	if (ret)
	404	return ret;
f6c274e1	405
8eed00b2 MG	406	queue_work(pm_wq, &dwc->wakeup_work);
	407
	408	return 0;
f6c274e1	409	}
696118c0	410	#endif /* CONFIG_PM */
f6c274e1	411
696118c0	412	#ifdef CONFIG_PM_SLEEP
9cecca75	413	static int dwc3_pci_suspend(struct device *dev)
e9af9229	414	{
9cecca75 FB	415	struct dwc3_pci *dwc = dev_get_drvdata(dev);
	416
	417	return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
	418	}
	419
	420	static int dwc3_pci_resume(struct device *dev)
	421	{
	422	struct dwc3_pci *dwc = dev_get_drvdata(dev);
	423
	424	return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
e9af9229	425	}
696118c0	426	#endif /* CONFIG_PM_SLEEP */
e9af9229	427
95aa932c	428	static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
9cecca75	429	SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
f6c274e1	430	SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
e9af9229 FB	431	NULL)
	432	};
	433
72246da4	434	static struct pci_driver dwc3_pci_driver = {
0949e99b	435	.name = "dwc3-pci",
72246da4 FB	436	.id_table = dwc3_pci_id_table,
72246da4 FB	437	.probe = dwc3_pci_probe,
7690417d	438	.remove = dwc3_pci_remove,
e9af9229 FB	439	.driver = {
	440	.pm = &dwc3_pci_dev_pm_ops,
	441	}
72246da4 FB	442	};
	443
	444	MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
5945f789	445	MODULE_LICENSE("GPL v2");
72246da4 FB	446	MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
72246da4 FB	447
95656336	448	module_pci_driver(dwc3_pci_driver);