Commit | Line | Data |
---|---|---|
5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
3c373454 | 2 | /* |
72246da4 FB |
3 | * dwc3-omap.c - OMAP Specific Glue layer |
4 | * | |
10623b87 | 5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com |
72246da4 FB |
6 | * |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
72246da4 FB |
9 | */ |
10 | ||
a72e658b | 11 | #include <linux/module.h> |
72246da4 FB |
12 | #include <linux/kernel.h> |
13 | #include <linux/slab.h> | |
12a7f17f | 14 | #include <linux/irq.h> |
72246da4 | 15 | #include <linux/interrupt.h> |
72246da4 | 16 | #include <linux/platform_device.h> |
af310e96 | 17 | #include <linux/pm_runtime.h> |
72246da4 FB |
18 | #include <linux/dma-mapping.h> |
19 | #include <linux/ioport.h> | |
20 | #include <linux/io.h> | |
45b3cd4a | 21 | #include <linux/of.h> |
b4bfe6aa | 22 | #include <linux/of_platform.h> |
8061ad72 | 23 | #include <linux/extcon.h> |
8061ad72 | 24 | #include <linux/regulator/consumer.h> |
72246da4 | 25 | |
a418cc4e | 26 | #include <linux/usb/otg.h> |
a418cc4e | 27 | |
72246da4 FB |
28 | /* |
29 | * All these registers belong to OMAP's Wrapper around the | |
30 | * DesignWare USB3 Core. | |
31 | */ | |
32 | ||
33 | #define USBOTGSS_REVISION 0x0000 | |
34 | #define USBOTGSS_SYSCONFIG 0x0010 | |
35 | #define USBOTGSS_IRQ_EOI 0x0020 | |
ff7307b5 | 36 | #define USBOTGSS_EOI_OFFSET 0x0008 |
72246da4 FB |
37 | #define USBOTGSS_IRQSTATUS_RAW_0 0x0024 |
38 | #define USBOTGSS_IRQSTATUS_0 0x0028 | |
39 | #define USBOTGSS_IRQENABLE_SET_0 0x002c | |
40 | #define USBOTGSS_IRQENABLE_CLR_0 0x0030 | |
ff7307b5 | 41 | #define USBOTGSS_IRQ0_OFFSET 0x0004 |
b1fd6cb5 GC |
42 | #define USBOTGSS_IRQSTATUS_RAW_1 0x0030 |
43 | #define USBOTGSS_IRQSTATUS_1 0x0034 | |
44 | #define USBOTGSS_IRQENABLE_SET_1 0x0038 | |
45 | #define USBOTGSS_IRQENABLE_CLR_1 0x003c | |
46 | #define USBOTGSS_IRQSTATUS_RAW_2 0x0040 | |
47 | #define USBOTGSS_IRQSTATUS_2 0x0044 | |
48 | #define USBOTGSS_IRQENABLE_SET_2 0x0048 | |
49 | #define USBOTGSS_IRQENABLE_CLR_2 0x004c | |
50 | #define USBOTGSS_IRQSTATUS_RAW_3 0x0050 | |
51 | #define USBOTGSS_IRQSTATUS_3 0x0054 | |
52 | #define USBOTGSS_IRQENABLE_SET_3 0x0058 | |
53 | #define USBOTGSS_IRQENABLE_CLR_3 0x005c | |
ff7307b5 GC |
54 | #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030 |
55 | #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034 | |
56 | #define USBOTGSS_IRQSTATUS_MISC 0x0038 | |
57 | #define USBOTGSS_IRQENABLE_SET_MISC 0x003c | |
58 | #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040 | |
59 | #define USBOTGSS_IRQMISC_OFFSET 0x03fc | |
22832190 BL |
60 | #define USBOTGSS_UTMI_OTG_STATUS 0x0080 |
61 | #define USBOTGSS_UTMI_OTG_CTRL 0x0084 | |
ff7307b5 GC |
62 | #define USBOTGSS_UTMI_OTG_OFFSET 0x0480 |
63 | #define USBOTGSS_TXFIFO_DEPTH 0x0508 | |
64 | #define USBOTGSS_RXFIFO_DEPTH 0x050c | |
72246da4 FB |
65 | #define USBOTGSS_MMRAM_OFFSET 0x0100 |
66 | #define USBOTGSS_FLADJ 0x0104 | |
67 | #define USBOTGSS_DEBUG_CFG 0x0108 | |
68 | #define USBOTGSS_DEBUG_DATA 0x010c | |
ff7307b5 GC |
69 | #define USBOTGSS_DEV_EBC_EN 0x0110 |
70 | #define USBOTGSS_DEBUG_OFFSET 0x0600 | |
72246da4 FB |
71 | |
72 | /* SYSCONFIG REGISTER */ | |
ff3f0789 | 73 | #define USBOTGSS_SYSCONFIG_DMADISABLE BIT(16) |
4b5faa7a | 74 | |
72246da4 | 75 | /* IRQ_EOI REGISTER */ |
ff3f0789 | 76 | #define USBOTGSS_IRQ_EOI_LINE_NUMBER BIT(0) |
72246da4 FB |
77 | |
78 | /* IRQS0 BITS */ | |
ff3f0789 | 79 | #define USBOTGSS_IRQO_COREIRQ_ST BIT(0) |
72246da4 | 80 | |
b1fd6cb5 | 81 | /* IRQMISC BITS */ |
ff3f0789 RQ |
82 | #define USBOTGSS_IRQMISC_DMADISABLECLR BIT(17) |
83 | #define USBOTGSS_IRQMISC_OEVT BIT(16) | |
84 | #define USBOTGSS_IRQMISC_DRVVBUS_RISE BIT(13) | |
85 | #define USBOTGSS_IRQMISC_CHRGVBUS_RISE BIT(12) | |
86 | #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE BIT(11) | |
87 | #define USBOTGSS_IRQMISC_IDPULLUP_RISE BIT(8) | |
88 | #define USBOTGSS_IRQMISC_DRVVBUS_FALL BIT(5) | |
89 | #define USBOTGSS_IRQMISC_CHRGVBUS_FALL BIT(4) | |
90 | #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL BIT(3) | |
91 | #define USBOTGSS_IRQMISC_IDPULLUP_FALL BIT(0) | |
72246da4 | 92 | |
72246da4 | 93 | /* UTMI_OTG_STATUS REGISTER */ |
ff3f0789 RQ |
94 | #define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS BIT(5) |
95 | #define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS BIT(4) | |
96 | #define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS BIT(3) | |
97 | #define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP BIT(0) | |
22832190 BL |
98 | |
99 | /* UTMI_OTG_CTRL REGISTER */ | |
ff3f0789 RQ |
100 | #define USBOTGSS_UTMI_OTG_CTRL_SW_MODE BIT(31) |
101 | #define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT BIT(9) | |
102 | #define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE BIT(8) | |
103 | #define USBOTGSS_UTMI_OTG_CTRL_IDDIG BIT(4) | |
104 | #define USBOTGSS_UTMI_OTG_CTRL_SESSEND BIT(3) | |
105 | #define USBOTGSS_UTMI_OTG_CTRL_SESSVALID BIT(2) | |
106 | #define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID BIT(1) | |
72246da4 | 107 | |
b2a39742 MY |
108 | enum dwc3_omap_utmi_mode { |
109 | DWC3_OMAP_UTMI_MODE_UNKNOWN = 0, | |
110 | DWC3_OMAP_UTMI_MODE_HW, | |
111 | DWC3_OMAP_UTMI_MODE_SW, | |
112 | }; | |
113 | ||
72246da4 | 114 | struct dwc3_omap { |
72246da4 FB |
115 | struct device *dev; |
116 | ||
117 | int irq; | |
118 | void __iomem *base; | |
119 | ||
22832190 | 120 | u32 utmi_otg_ctrl; |
1e2a064c GC |
121 | u32 utmi_otg_offset; |
122 | u32 irqmisc_offset; | |
123 | u32 irq_eoi_offset; | |
124 | u32 debug_offset; | |
125 | u32 irq0_offset; | |
f3e117f4 | 126 | |
5960387a | 127 | struct extcon_dev *edev; |
8061ad72 KVA |
128 | struct notifier_block vbus_nb; |
129 | struct notifier_block id_nb; | |
130 | ||
131 | struct regulator *vbus_reg; | |
72246da4 FB |
132 | }; |
133 | ||
8061ad72 KVA |
134 | enum omap_dwc3_vbus_id_status { |
135 | OMAP_DWC3_ID_FLOAT, | |
136 | OMAP_DWC3_ID_GROUND, | |
137 | OMAP_DWC3_VBUS_OFF, | |
138 | OMAP_DWC3_VBUS_VALID, | |
139 | }; | |
7e41bba9 | 140 | |
ab5e59db IS |
141 | static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset) |
142 | { | |
143 | return readl(base + offset); | |
144 | } | |
145 | ||
146 | static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value) | |
147 | { | |
148 | writel(value, base + offset); | |
149 | } | |
150 | ||
22832190 | 151 | static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap) |
b1fd6cb5 | 152 | { |
22832190 | 153 | return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL + |
b1fd6cb5 GC |
154 | omap->utmi_otg_offset); |
155 | } | |
156 | ||
22832190 | 157 | static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value) |
b1fd6cb5 | 158 | { |
22832190 | 159 | dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL + |
b1fd6cb5 GC |
160 | omap->utmi_otg_offset, value); |
161 | ||
162 | } | |
163 | ||
164 | static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap) | |
165 | { | |
3f586c92 | 166 | return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_0 - |
b1fd6cb5 GC |
167 | omap->irq0_offset); |
168 | } | |
169 | ||
170 | static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value) | |
171 | { | |
172 | dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 - | |
173 | omap->irq0_offset, value); | |
174 | ||
175 | } | |
176 | ||
177 | static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap) | |
178 | { | |
3f586c92 | 179 | return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_MISC + |
b1fd6cb5 GC |
180 | omap->irqmisc_offset); |
181 | } | |
182 | ||
183 | static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value) | |
184 | { | |
185 | dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC + | |
186 | omap->irqmisc_offset, value); | |
187 | ||
188 | } | |
189 | ||
190 | static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value) | |
191 | { | |
192 | dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC + | |
193 | omap->irqmisc_offset, value); | |
194 | ||
195 | } | |
196 | ||
197 | static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value) | |
198 | { | |
199 | dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 - | |
200 | omap->irq0_offset, value); | |
201 | } | |
202 | ||
96e5d312 GC |
203 | static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value) |
204 | { | |
205 | dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC + | |
206 | omap->irqmisc_offset, value); | |
207 | } | |
208 | ||
209 | static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value) | |
210 | { | |
211 | dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 - | |
212 | omap->irq0_offset, value); | |
213 | } | |
214 | ||
8061ad72 KVA |
215 | static void dwc3_omap_set_mailbox(struct dwc3_omap *omap, |
216 | enum omap_dwc3_vbus_id_status status) | |
7e41bba9 | 217 | { |
8061ad72 KVA |
218 | int ret; |
219 | u32 val; | |
2ba7943a | 220 | |
7e41bba9 KVA |
221 | switch (status) { |
222 | case OMAP_DWC3_ID_GROUND: | |
8061ad72 KVA |
223 | if (omap->vbus_reg) { |
224 | ret = regulator_enable(omap->vbus_reg); | |
225 | if (ret) { | |
e4f75667 | 226 | dev_err(omap->dev, "regulator enable failed\n"); |
8061ad72 KVA |
227 | return; |
228 | } | |
229 | } | |
230 | ||
22832190 | 231 | val = dwc3_omap_read_utmi_ctrl(omap); |
d2728fb3 | 232 | val &= ~USBOTGSS_UTMI_OTG_CTRL_IDDIG; |
22832190 | 233 | dwc3_omap_write_utmi_ctrl(omap, val); |
7e41bba9 KVA |
234 | break; |
235 | ||
236 | case OMAP_DWC3_VBUS_VALID: | |
22832190 BL |
237 | val = dwc3_omap_read_utmi_ctrl(omap); |
238 | val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND; | |
d2728fb3 | 239 | val |= USBOTGSS_UTMI_OTG_CTRL_VBUSVALID |
9ab330bf | 240 | | USBOTGSS_UTMI_OTG_CTRL_SESSVALID; |
22832190 | 241 | dwc3_omap_write_utmi_ctrl(omap, val); |
7e41bba9 KVA |
242 | break; |
243 | ||
244 | case OMAP_DWC3_ID_FLOAT: | |
ac01df34 | 245 | if (omap->vbus_reg && regulator_is_enabled(omap->vbus_reg)) |
8061ad72 | 246 | regulator_disable(omap->vbus_reg); |
d2728fb3 RQ |
247 | val = dwc3_omap_read_utmi_ctrl(omap); |
248 | val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG; | |
249 | dwc3_omap_write_utmi_ctrl(omap, val); | |
0913750f | 250 | break; |
8061ad72 | 251 | |
7e41bba9 | 252 | case OMAP_DWC3_VBUS_OFF: |
22832190 BL |
253 | val = dwc3_omap_read_utmi_ctrl(omap); |
254 | val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID | |
9ab330bf | 255 | | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID); |
d2728fb3 | 256 | val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND; |
22832190 | 257 | dwc3_omap_write_utmi_ctrl(omap, val); |
7e41bba9 KVA |
258 | break; |
259 | ||
260 | default: | |
e4f75667 | 261 | dev_WARN(omap->dev, "invalid state\n"); |
7e41bba9 | 262 | } |
7e41bba9 | 263 | } |
7e41bba9 | 264 | |
3f586c92 RQ |
265 | static void dwc3_omap_enable_irqs(struct dwc3_omap *omap); |
266 | static void dwc3_omap_disable_irqs(struct dwc3_omap *omap); | |
267 | ||
72246da4 | 268 | static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) |
3f586c92 RQ |
269 | { |
270 | struct dwc3_omap *omap = _omap; | |
271 | ||
272 | if (dwc3_omap_read_irqmisc_status(omap) || | |
273 | dwc3_omap_read_irq0_status(omap)) { | |
274 | /* mask irqs */ | |
275 | dwc3_omap_disable_irqs(omap); | |
276 | return IRQ_WAKE_THREAD; | |
277 | } | |
278 | ||
279 | return IRQ_NONE; | |
280 | } | |
281 | ||
282 | static irqreturn_t dwc3_omap_interrupt_thread(int irq, void *_omap) | |
72246da4 FB |
283 | { |
284 | struct dwc3_omap *omap = _omap; | |
285 | u32 reg; | |
72246da4 | 286 | |
3f586c92 | 287 | /* clear irq status flags */ |
b1fd6cb5 | 288 | reg = dwc3_omap_read_irqmisc_status(omap); |
b1fd6cb5 GC |
289 | dwc3_omap_write_irqmisc_status(omap, reg); |
290 | ||
291 | reg = dwc3_omap_read_irq0_status(omap); | |
b1fd6cb5 | 292 | dwc3_omap_write_irq0_status(omap, reg); |
72246da4 | 293 | |
3f586c92 RQ |
294 | /* unmask irqs */ |
295 | dwc3_omap_enable_irqs(omap); | |
296 | ||
72246da4 FB |
297 | return IRQ_HANDLED; |
298 | } | |
299 | ||
9a4b5dab FB |
300 | static void dwc3_omap_enable_irqs(struct dwc3_omap *omap) |
301 | { | |
302 | u32 reg; | |
303 | ||
304 | /* enable all IRQs */ | |
305 | reg = USBOTGSS_IRQO_COREIRQ_ST; | |
b1fd6cb5 GC |
306 | dwc3_omap_write_irq0_set(omap, reg); |
307 | ||
308 | reg = (USBOTGSS_IRQMISC_OEVT | | |
309 | USBOTGSS_IRQMISC_DRVVBUS_RISE | | |
310 | USBOTGSS_IRQMISC_CHRGVBUS_RISE | | |
311 | USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | | |
312 | USBOTGSS_IRQMISC_IDPULLUP_RISE | | |
313 | USBOTGSS_IRQMISC_DRVVBUS_FALL | | |
314 | USBOTGSS_IRQMISC_CHRGVBUS_FALL | | |
315 | USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | | |
316 | USBOTGSS_IRQMISC_IDPULLUP_FALL); | |
317 | ||
318 | dwc3_omap_write_irqmisc_set(omap, reg); | |
9a4b5dab FB |
319 | } |
320 | ||
321 | static void dwc3_omap_disable_irqs(struct dwc3_omap *omap) | |
322 | { | |
96e5d312 GC |
323 | u32 reg; |
324 | ||
9a4b5dab | 325 | /* disable all IRQs */ |
96e5d312 GC |
326 | reg = USBOTGSS_IRQO_COREIRQ_ST; |
327 | dwc3_omap_write_irq0_clr(omap, reg); | |
328 | ||
329 | reg = (USBOTGSS_IRQMISC_OEVT | | |
330 | USBOTGSS_IRQMISC_DRVVBUS_RISE | | |
331 | USBOTGSS_IRQMISC_CHRGVBUS_RISE | | |
332 | USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | | |
333 | USBOTGSS_IRQMISC_IDPULLUP_RISE | | |
334 | USBOTGSS_IRQMISC_DRVVBUS_FALL | | |
335 | USBOTGSS_IRQMISC_CHRGVBUS_FALL | | |
336 | USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | | |
337 | USBOTGSS_IRQMISC_IDPULLUP_FALL); | |
338 | ||
339 | dwc3_omap_write_irqmisc_clr(omap, reg); | |
9a4b5dab FB |
340 | } |
341 | ||
8061ad72 KVA |
342 | static int dwc3_omap_id_notifier(struct notifier_block *nb, |
343 | unsigned long event, void *ptr) | |
344 | { | |
345 | struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb); | |
346 | ||
347 | if (event) | |
348 | dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); | |
349 | else | |
350 | dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT); | |
351 | ||
352 | return NOTIFY_DONE; | |
353 | } | |
354 | ||
355 | static int dwc3_omap_vbus_notifier(struct notifier_block *nb, | |
356 | unsigned long event, void *ptr) | |
357 | { | |
358 | struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb); | |
359 | ||
360 | if (event) | |
361 | dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); | |
362 | else | |
363 | dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF); | |
364 | ||
365 | return NOTIFY_DONE; | |
366 | } | |
367 | ||
30fef1a9 GC |
368 | static void dwc3_omap_map_offset(struct dwc3_omap *omap) |
369 | { | |
370 | struct device_node *node = omap->dev->of_node; | |
371 | ||
372 | /* | |
373 | * Differentiate between OMAP5 and AM437x. | |
374 | * | |
375 | * For OMAP5(ES2.0) and AM437x wrapper revision is same, even | |
376 | * though there are changes in wrapper register offsets. | |
377 | * | |
378 | * Using dt compatible to differentiate AM437x. | |
379 | */ | |
380 | if (of_device_is_compatible(node, "ti,am437x-dwc3")) { | |
381 | omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET; | |
382 | omap->irq0_offset = USBOTGSS_IRQ0_OFFSET; | |
383 | omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET; | |
384 | omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET; | |
385 | omap->debug_offset = USBOTGSS_DEBUG_OFFSET; | |
386 | } | |
387 | } | |
388 | ||
d2f0cf89 GC |
389 | static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap) |
390 | { | |
391 | u32 reg; | |
392 | struct device_node *node = omap->dev->of_node; | |
73561128 | 393 | u32 utmi_mode = 0; |
d2f0cf89 | 394 | |
22832190 | 395 | reg = dwc3_omap_read_utmi_ctrl(omap); |
d2f0cf89 GC |
396 | |
397 | of_property_read_u32(node, "utmi-mode", &utmi_mode); | |
398 | ||
399 | switch (utmi_mode) { | |
400 | case DWC3_OMAP_UTMI_MODE_SW: | |
22832190 | 401 | reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE; |
d2f0cf89 GC |
402 | break; |
403 | case DWC3_OMAP_UTMI_MODE_HW: | |
22832190 | 404 | reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE; |
d2f0cf89 GC |
405 | break; |
406 | default: | |
e4f75667 | 407 | dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode); |
d2f0cf89 GC |
408 | } |
409 | ||
22832190 | 410 | dwc3_omap_write_utmi_ctrl(omap, reg); |
d2f0cf89 GC |
411 | } |
412 | ||
025b431b GC |
413 | static int dwc3_omap_extcon_register(struct dwc3_omap *omap) |
414 | { | |
788b0bc4 | 415 | int ret; |
025b431b GC |
416 | struct device_node *node = omap->dev->of_node; |
417 | struct extcon_dev *edev; | |
418 | ||
419 | if (of_property_read_bool(node, "extcon")) { | |
420 | edev = extcon_get_edev_by_phandle(omap->dev, 0); | |
421 | if (IS_ERR(edev)) { | |
422 | dev_vdbg(omap->dev, "couldn't get extcon device\n"); | |
423 | return -EPROBE_DEFER; | |
424 | } | |
425 | ||
426 | omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier; | |
c773bb0b CC |
427 | ret = devm_extcon_register_notifier(omap->dev, edev, |
428 | EXTCON_USB, &omap->vbus_nb); | |
025b431b GC |
429 | if (ret < 0) |
430 | dev_vdbg(omap->dev, "failed to register notifier for USB\n"); | |
431 | ||
432 | omap->id_nb.notifier_call = dwc3_omap_id_notifier; | |
c773bb0b CC |
433 | ret = devm_extcon_register_notifier(omap->dev, edev, |
434 | EXTCON_USB_HOST, &omap->id_nb); | |
025b431b GC |
435 | if (ret < 0) |
436 | dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n"); | |
437 | ||
c773bb0b | 438 | if (extcon_get_state(edev, EXTCON_USB) == true) |
025b431b | 439 | dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); |
e17b02d4 MH |
440 | else |
441 | dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF); | |
442 | ||
c773bb0b | 443 | if (extcon_get_state(edev, EXTCON_USB_HOST) == true) |
025b431b | 444 | dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); |
e17b02d4 MH |
445 | else |
446 | dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT); | |
5960387a CC |
447 | |
448 | omap->edev = edev; | |
025b431b GC |
449 | } |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
41ac7b3a | 454 | static int dwc3_omap_probe(struct platform_device *pdev) |
72246da4 | 455 | { |
45b3cd4a FB |
456 | struct device_node *node = pdev->dev.of_node; |
457 | ||
72246da4 | 458 | struct dwc3_omap *omap; |
802ca850 | 459 | struct device *dev = &pdev->dev; |
8061ad72 | 460 | struct regulator *vbus_reg = NULL; |
72246da4 | 461 | |
b09e99ee | 462 | int ret; |
72246da4 FB |
463 | int irq; |
464 | ||
72246da4 | 465 | void __iomem *base; |
72246da4 | 466 | |
4495afcf KVA |
467 | if (!node) { |
468 | dev_err(dev, "device node not found\n"); | |
469 | return -EINVAL; | |
470 | } | |
471 | ||
802ca850 | 472 | omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); |
734d5a53 | 473 | if (!omap) |
802ca850 | 474 | return -ENOMEM; |
72246da4 FB |
475 | |
476 | platform_set_drvdata(pdev, omap); | |
477 | ||
e36a0c87 | 478 | irq = platform_get_irq(pdev, 0); |
b33f3706 | 479 | if (irq < 0) |
0ae99ecb | 480 | return irq; |
72246da4 | 481 | |
58dd0bad | 482 | base = devm_platform_ioremap_resource(pdev, 0); |
8bbcd17d FB |
483 | if (IS_ERR(base)) |
484 | return PTR_ERR(base); | |
72246da4 | 485 | |
8061ad72 KVA |
486 | if (of_property_read_bool(node, "vbus-supply")) { |
487 | vbus_reg = devm_regulator_get(dev, "vbus"); | |
488 | if (IS_ERR(vbus_reg)) { | |
489 | dev_err(dev, "vbus init failed\n"); | |
490 | return PTR_ERR(vbus_reg); | |
491 | } | |
492 | } | |
493 | ||
802ca850 | 494 | omap->dev = dev; |
72246da4 FB |
495 | omap->irq = irq; |
496 | omap->base = base; | |
8061ad72 | 497 | omap->vbus_reg = vbus_reg; |
72246da4 | 498 | |
af310e96 KVA |
499 | pm_runtime_enable(dev); |
500 | ret = pm_runtime_get_sync(dev); | |
501 | if (ret < 0) { | |
502 | dev_err(dev, "get_sync failed with err %d\n", ret); | |
45d49cb7 | 503 | goto err1; |
af310e96 KVA |
504 | } |
505 | ||
30fef1a9 | 506 | dwc3_omap_map_offset(omap); |
d2f0cf89 | 507 | dwc3_omap_set_utmi_mode(omap); |
9962444f | 508 | |
025b431b GC |
509 | ret = dwc3_omap_extcon_register(omap); |
510 | if (ret < 0) | |
45d49cb7 | 511 | goto err1; |
8061ad72 | 512 | |
4495afcf KVA |
513 | ret = of_platform_populate(node, NULL, NULL, dev); |
514 | if (ret) { | |
515 | dev_err(&pdev->dev, "failed to create dwc3 core\n"); | |
c773bb0b | 516 | goto err1; |
72246da4 FB |
517 | } |
518 | ||
ee249b45 V |
519 | ret = devm_request_threaded_irq(dev, omap->irq, dwc3_omap_interrupt, |
520 | dwc3_omap_interrupt_thread, IRQF_SHARED, | |
521 | "dwc3-omap", omap); | |
522 | if (ret) { | |
523 | dev_err(dev, "failed to request IRQ #%d --> %d\n", | |
524 | omap->irq, ret); | |
2aa765a4 | 525 | goto err2; |
ee249b45 | 526 | } |
e2ae0692 | 527 | dwc3_omap_enable_irqs(omap); |
72246da4 | 528 | return 0; |
594daba1 | 529 | |
2aa765a4 KK |
530 | err2: |
531 | of_platform_depopulate(dev); | |
594daba1 KVA |
532 | err1: |
533 | pm_runtime_put_sync(dev); | |
594daba1 KVA |
534 | pm_runtime_disable(dev); |
535 | ||
536 | return ret; | |
72246da4 FB |
537 | } |
538 | ||
abe04efc | 539 | static void dwc3_omap_remove(struct platform_device *pdev) |
72246da4 | 540 | { |
9a4b5dab FB |
541 | struct dwc3_omap *omap = platform_get_drvdata(pdev); |
542 | ||
543 | dwc3_omap_disable_irqs(omap); | |
12a7f17f | 544 | disable_irq(omap->irq); |
3d0184d0 | 545 | of_platform_depopulate(omap->dev); |
af310e96 KVA |
546 | pm_runtime_put_sync(&pdev->dev); |
547 | pm_runtime_disable(&pdev->dev); | |
72246da4 FB |
548 | } |
549 | ||
2c2dc89c | 550 | static const struct of_device_id of_dwc3_match[] = { |
72246da4 | 551 | { |
e36a0c87 | 552 | .compatible = "ti,dwc3" |
72246da4 | 553 | }, |
ff7307b5 GC |
554 | { |
555 | .compatible = "ti,am437x-dwc3" | |
556 | }, | |
72246da4 FB |
557 | { }, |
558 | }; | |
2c2dc89c | 559 | MODULE_DEVICE_TABLE(of, of_dwc3_match); |
72246da4 | 560 | |
19fda7cd | 561 | #ifdef CONFIG_PM_SLEEP |
f3e117f4 FB |
562 | static int dwc3_omap_suspend(struct device *dev) |
563 | { | |
564 | struct dwc3_omap *omap = dev_get_drvdata(dev); | |
565 | ||
22832190 | 566 | omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap); |
7ee2566f | 567 | dwc3_omap_disable_irqs(omap); |
f3e117f4 FB |
568 | |
569 | return 0; | |
570 | } | |
571 | ||
572 | static int dwc3_omap_resume(struct device *dev) | |
573 | { | |
574 | struct dwc3_omap *omap = dev_get_drvdata(dev); | |
575 | ||
22832190 | 576 | dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl); |
7ee2566f | 577 | dwc3_omap_enable_irqs(omap); |
f3e117f4 FB |
578 | |
579 | pm_runtime_disable(dev); | |
580 | pm_runtime_set_active(dev); | |
581 | pm_runtime_enable(dev); | |
582 | ||
583 | return 0; | |
584 | } | |
585 | ||
c49f6305 RQ |
586 | static void dwc3_omap_complete(struct device *dev) |
587 | { | |
588 | struct dwc3_omap *omap = dev_get_drvdata(dev); | |
589 | ||
590 | if (extcon_get_state(omap->edev, EXTCON_USB)) | |
591 | dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); | |
592 | else | |
593 | dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF); | |
594 | ||
595 | if (extcon_get_state(omap->edev, EXTCON_USB_HOST)) | |
596 | dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); | |
597 | else | |
598 | dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT); | |
599 | } | |
600 | ||
f3e117f4 | 601 | static const struct dev_pm_ops dwc3_omap_dev_pm_ops = { |
f3e117f4 FB |
602 | |
603 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume) | |
c49f6305 | 604 | .complete = dwc3_omap_complete, |
f3e117f4 FB |
605 | }; |
606 | ||
607 | #define DEV_PM_OPS (&dwc3_omap_dev_pm_ops) | |
608 | #else | |
609 | #define DEV_PM_OPS NULL | |
19fda7cd | 610 | #endif /* CONFIG_PM_SLEEP */ |
f3e117f4 | 611 | |
72246da4 FB |
612 | static struct platform_driver dwc3_omap_driver = { |
613 | .probe = dwc3_omap_probe, | |
abe04efc | 614 | .remove_new = dwc3_omap_remove, |
72246da4 FB |
615 | .driver = { |
616 | .name = "omap-dwc3", | |
2c2dc89c | 617 | .of_match_table = of_dwc3_match, |
f3e117f4 | 618 | .pm = DEV_PM_OPS, |
72246da4 FB |
619 | }, |
620 | }; | |
621 | ||
cc27c96c AL |
622 | module_platform_driver(dwc3_omap_driver); |
623 | ||
7ae4fc4d | 624 | MODULE_ALIAS("platform:omap-dwc3"); |
72246da4 | 625 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); |
5945f789 | 626 | MODULE_LICENSE("GPL v2"); |
72246da4 | 627 | MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer"); |