[linux-2.6-block.git] / drivers / usb / dwc3 / dwc3-omap.c

/**
 * dwc3-omap.c - OMAP Specific Glue layer
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Felipe Balbi <balbi@ti.com>,
 *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2  of
 * the License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/platform_data/dwc3-omap.h>
#include <linux/pm_runtime.h>
#include <linux/dma-mapping.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/extcon.h>
#include <linux/regulator/consumer.h>

#include <linux/usb/otg.h>

/*
 * All these registers belong to OMAP's Wrapper around the
 * DesignWare USB3 Core.
 */

#define USBOTGSS_REVISION			0x0000
#define USBOTGSS_SYSCONFIG			0x0010
#define USBOTGSS_IRQ_EOI			0x0020
#define USBOTGSS_EOI_OFFSET			0x0008
#define USBOTGSS_IRQSTATUS_RAW_0		0x0024
#define USBOTGSS_IRQSTATUS_0			0x0028
#define USBOTGSS_IRQENABLE_SET_0		0x002c
#define USBOTGSS_IRQENABLE_CLR_0		0x0030
#define USBOTGSS_IRQ0_OFFSET			0x0004
#define USBOTGSS_IRQSTATUS_RAW_1		0x0030
#define USBOTGSS_IRQSTATUS_1			0x0034
#define USBOTGSS_IRQENABLE_SET_1		0x0038
#define USBOTGSS_IRQENABLE_CLR_1		0x003c
#define USBOTGSS_IRQSTATUS_RAW_2		0x0040
#define USBOTGSS_IRQSTATUS_2			0x0044
#define USBOTGSS_IRQENABLE_SET_2		0x0048
#define USBOTGSS_IRQENABLE_CLR_2		0x004c
#define USBOTGSS_IRQSTATUS_RAW_3		0x0050
#define USBOTGSS_IRQSTATUS_3			0x0054
#define USBOTGSS_IRQENABLE_SET_3		0x0058
#define USBOTGSS_IRQENABLE_CLR_3		0x005c
#define USBOTGSS_IRQSTATUS_EOI_MISC		0x0030
#define USBOTGSS_IRQSTATUS_RAW_MISC		0x0034
#define USBOTGSS_IRQSTATUS_MISC			0x0038
#define USBOTGSS_IRQENABLE_SET_MISC		0x003c
#define USBOTGSS_IRQENABLE_CLR_MISC		0x0040
#define USBOTGSS_IRQMISC_OFFSET			0x03fc
#define USBOTGSS_UTMI_OTG_STATUS		0x0080
#define USBOTGSS_UTMI_OTG_CTRL			0x0084
#define USBOTGSS_UTMI_OTG_OFFSET		0x0480
#define USBOTGSS_TXFIFO_DEPTH			0x0508
#define USBOTGSS_RXFIFO_DEPTH			0x050c
#define USBOTGSS_MMRAM_OFFSET			0x0100
#define USBOTGSS_FLADJ				0x0104
#define USBOTGSS_DEBUG_CFG			0x0108
#define USBOTGSS_DEBUG_DATA			0x010c
#define USBOTGSS_DEV_EBC_EN			0x0110
#define USBOTGSS_DEBUG_OFFSET			0x0600

/* SYSCONFIG REGISTER */
#define USBOTGSS_SYSCONFIG_DMADISABLE		(1 << 16)

/* IRQ_EOI REGISTER */
#define USBOTGSS_IRQ_EOI_LINE_NUMBER		(1 << 0)

/* IRQS0 BITS */
#define USBOTGSS_IRQO_COREIRQ_ST		(1 << 0)

/* IRQMISC BITS */
#define USBOTGSS_IRQMISC_DMADISABLECLR		(1 << 17)
#define USBOTGSS_IRQMISC_OEVT			(1 << 16)
#define USBOTGSS_IRQMISC_DRVVBUS_RISE		(1 << 13)
#define USBOTGSS_IRQMISC_CHRGVBUS_RISE		(1 << 12)
#define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE	(1 << 11)
#define USBOTGSS_IRQMISC_IDPULLUP_RISE		(1 << 8)
#define USBOTGSS_IRQMISC_DRVVBUS_FALL		(1 << 5)
#define USBOTGSS_IRQMISC_CHRGVBUS_FALL		(1 << 4)
#define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL		(1 << 3)
#define USBOTGSS_IRQMISC_IDPULLUP_FALL		(1 << 0)

/* UTMI_OTG_STATUS REGISTER */
#define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS	(1 << 5)
#define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS	(1 << 4)
#define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS	(1 << 3)
#define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP	(1 << 0)

/* UTMI_OTG_CTRL REGISTER */
#define USBOTGSS_UTMI_OTG_CTRL_SW_MODE		(1 << 31)
#define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT	(1 << 9)
#define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE (1 << 8)
#define USBOTGSS_UTMI_OTG_CTRL_IDDIG		(1 << 4)
#define USBOTGSS_UTMI_OTG_CTRL_SESSEND		(1 << 3)
#define USBOTGSS_UTMI_OTG_CTRL_SESSVALID	(1 << 2)
#define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID	(1 << 1)

struct dwc3_omap {
	struct device		*dev;

	int			irq;
	void __iomem		*base;

	u32			utmi_otg_ctrl;
	u32			utmi_otg_offset;
	u32			irqmisc_offset;
	u32			irq_eoi_offset;
	u32			debug_offset;
	u32			irq0_offset;

	u32			dma_status:1;

	struct extcon_dev	*edev;
	struct notifier_block	vbus_nb;
	struct notifier_block	id_nb;

	struct regulator	*vbus_reg;
};

enum omap_dwc3_vbus_id_status {
	OMAP_DWC3_ID_FLOAT,
	OMAP_DWC3_ID_GROUND,
	OMAP_DWC3_VBUS_OFF,
	OMAP_DWC3_VBUS_VALID,
};

static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
{
	return readl(base + offset);
}

static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
{
	writel(value, base + offset);
}

static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap)
{
	return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL +
							omap->utmi_otg_offset);
}

static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL +
					omap->utmi_otg_offset, value);

}

static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
{
	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
						omap->irq0_offset);
}

static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
						omap->irq0_offset, value);

}

static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
{
	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
						omap->irqmisc_offset);
}

static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
					omap->irqmisc_offset, value);

}

static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
						omap->irqmisc_offset, value);

}

static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
						omap->irq0_offset, value);
}

static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
						omap->irqmisc_offset, value);
}

static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
						omap->irq0_offset, value);
}

static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
	enum omap_dwc3_vbus_id_status status)
{
	int	ret;
	u32	val;

	switch (status) {
	case OMAP_DWC3_ID_GROUND:
		if (omap->vbus_reg) {
			ret = regulator_enable(omap->vbus_reg);
			if (ret) {
				dev_err(omap->dev, "regulator enable failed\n");
				return;
			}
		}

		val = dwc3_omap_read_utmi_ctrl(omap);
		val &= ~(USBOTGSS_UTMI_OTG_CTRL_IDDIG
				| USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
				| USBOTGSS_UTMI_OTG_CTRL_SESSEND);
		val |= USBOTGSS_UTMI_OTG_CTRL_SESSVALID
				| USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT;
		dwc3_omap_write_utmi_ctrl(omap, val);
		break;

	case OMAP_DWC3_VBUS_VALID:
		val = dwc3_omap_read_utmi_ctrl(omap);
		val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND;
		val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG
				| USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
				| USBOTGSS_UTMI_OTG_CTRL_SESSVALID
				| USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT;
		dwc3_omap_write_utmi_ctrl(omap, val);
		break;

	case OMAP_DWC3_ID_FLOAT:
		if (omap->vbus_reg)
			regulator_disable(omap->vbus_reg);

	case OMAP_DWC3_VBUS_OFF:
		val = dwc3_omap_read_utmi_ctrl(omap);
		val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID
				| USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
				| USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT);
		val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND
				| USBOTGSS_UTMI_OTG_CTRL_IDDIG;
		dwc3_omap_write_utmi_ctrl(omap, val);
		break;

	default:
		dev_WARN(omap->dev, "invalid state\n");
	}
}

static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
{
	struct dwc3_omap	*omap = _omap;
	u32			reg;

	reg = dwc3_omap_read_irqmisc_status(omap);

	if (reg & USBOTGSS_IRQMISC_DMADISABLECLR)
		omap->dma_status = false;

	dwc3_omap_write_irqmisc_status(omap, reg);

	reg = dwc3_omap_read_irq0_status(omap);

	dwc3_omap_write_irq0_status(omap, reg);

	return IRQ_HANDLED;
}

static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
{
	u32			reg;

	/* enable all IRQs */
	reg = USBOTGSS_IRQO_COREIRQ_ST;
	dwc3_omap_write_irq0_set(omap, reg);

	reg = (USBOTGSS_IRQMISC_OEVT |
			USBOTGSS_IRQMISC_DRVVBUS_RISE |
			USBOTGSS_IRQMISC_CHRGVBUS_RISE |
			USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
			USBOTGSS_IRQMISC_IDPULLUP_RISE |
			USBOTGSS_IRQMISC_DRVVBUS_FALL |
			USBOTGSS_IRQMISC_CHRGVBUS_FALL |
			USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
			USBOTGSS_IRQMISC_IDPULLUP_FALL);

	dwc3_omap_write_irqmisc_set(omap, reg);
}

static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
{
	u32			reg;

	/* disable all IRQs */
	reg = USBOTGSS_IRQO_COREIRQ_ST;
	dwc3_omap_write_irq0_clr(omap, reg);

	reg = (USBOTGSS_IRQMISC_OEVT |
			USBOTGSS_IRQMISC_DRVVBUS_RISE |
			USBOTGSS_IRQMISC_CHRGVBUS_RISE |
			USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
			USBOTGSS_IRQMISC_IDPULLUP_RISE |
			USBOTGSS_IRQMISC_DRVVBUS_FALL |
			USBOTGSS_IRQMISC_CHRGVBUS_FALL |
			USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
			USBOTGSS_IRQMISC_IDPULLUP_FALL);

	dwc3_omap_write_irqmisc_clr(omap, reg);
}

static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);

static int dwc3_omap_id_notifier(struct notifier_block *nb,
	unsigned long event, void *ptr)
{
	struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);

	if (event)
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
	else
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);

	return NOTIFY_DONE;
}

static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
	unsigned long event, void *ptr)
{
	struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);

	if (event)
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
	else
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);

	return NOTIFY_DONE;
}

static void dwc3_omap_map_offset(struct dwc3_omap *omap)
{
	struct device_node	*node = omap->dev->of_node;

	/*
	 * Differentiate between OMAP5 and AM437x.
	 *
	 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even
	 * though there are changes in wrapper register offsets.
	 *
	 * Using dt compatible to differentiate AM437x.
	 */
	if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
		omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
		omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
		omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
		omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
		omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
	}
}

static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
{
	u32			reg;
	struct device_node	*node = omap->dev->of_node;
	int			utmi_mode = 0;

	reg = dwc3_omap_read_utmi_ctrl(omap);

	of_property_read_u32(node, "utmi-mode", &utmi_mode);

	switch (utmi_mode) {
	case DWC3_OMAP_UTMI_MODE_SW:
		reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
		break;
	case DWC3_OMAP_UTMI_MODE_HW:
		reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
		break;
	default:
		dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
	}

	dwc3_omap_write_utmi_ctrl(omap, reg);
}

static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
{
	int			ret;
	struct device_node	*node = omap->dev->of_node;
	struct extcon_dev	*edev;

	if (of_property_read_bool(node, "extcon")) {
		edev = extcon_get_edev_by_phandle(omap->dev, 0);
		if (IS_ERR(edev)) {
			dev_vdbg(omap->dev, "couldn't get extcon device\n");
			return -EPROBE_DEFER;
		}

		omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
		ret = extcon_register_notifier(edev, EXTCON_USB,
						&omap->vbus_nb);
		if (ret < 0)
			dev_vdbg(omap->dev, "failed to register notifier for USB\n");

		omap->id_nb.notifier_call = dwc3_omap_id_notifier;
		ret = extcon_register_notifier(edev, EXTCON_USB_HOST,
						&omap->id_nb);
		if (ret < 0)
			dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n");

		if (extcon_get_cable_state_(edev, EXTCON_USB) == true)
			dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
		if (extcon_get_cable_state_(edev, EXTCON_USB_HOST) == true)
			dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);

		omap->edev = edev;
	}

	return 0;
}

static int dwc3_omap_probe(struct platform_device *pdev)
{
	struct device_node	*node = pdev->dev.of_node;

	struct dwc3_omap	*omap;
	struct resource		*res;
	struct device		*dev = &pdev->dev;
	struct regulator	*vbus_reg = NULL;

	int			ret;
	int			irq;

	u32			reg;

	void __iomem		*base;

	if (!node) {
		dev_err(dev, "device node not found\n");
		return -EINVAL;
	}

	omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
	if (!omap)
		return -ENOMEM;

	platform_set_drvdata(pdev, omap);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "missing IRQ resource\n");
		return -EINVAL;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	if (of_property_read_bool(node, "vbus-supply")) {
		vbus_reg = devm_regulator_get(dev, "vbus");
		if (IS_ERR(vbus_reg)) {
			dev_err(dev, "vbus init failed\n");
			return PTR_ERR(vbus_reg);
		}
	}

	omap->dev	= dev;
	omap->irq	= irq;
	omap->base	= base;
	omap->vbus_reg	= vbus_reg;
	dev->dma_mask	= &dwc3_omap_dma_mask;

	pm_runtime_enable(dev);
	ret = pm_runtime_get_sync(dev);
	if (ret < 0) {
		dev_err(dev, "get_sync failed with err %d\n", ret);
		goto err1;
	}

	dwc3_omap_map_offset(omap);
	dwc3_omap_set_utmi_mode(omap);

	/* check the DMA Status */
	reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
	omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);

	ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
			"dwc3-omap", omap);
	if (ret) {
		dev_err(dev, "failed to request IRQ #%d --> %d\n",
				omap->irq, ret);
		goto err1;
	}

	ret = dwc3_omap_extcon_register(omap);
	if (ret < 0)
		goto err1;

	ret = of_platform_populate(node, NULL, NULL, dev);
	if (ret) {
		dev_err(&pdev->dev, "failed to create dwc3 core\n");
		goto err2;
	}

	dwc3_omap_enable_irqs(omap);

	return 0;

err2:
	extcon_unregister_notifier(omap->edev, EXTCON_USB, &omap->vbus_nb);
	extcon_unregister_notifier(omap->edev, EXTCON_USB_HOST, &omap->id_nb);

err1:
	pm_runtime_put_sync(dev);
	pm_runtime_disable(dev);

	return ret;
}

static int dwc3_omap_remove(struct platform_device *pdev)
{
	struct dwc3_omap	*omap = platform_get_drvdata(pdev);

	extcon_unregister_notifier(omap->edev, EXTCON_USB, &omap->vbus_nb);
	extcon_unregister_notifier(omap->edev, EXTCON_USB_HOST, &omap->id_nb);
	dwc3_omap_disable_irqs(omap);
	of_platform_depopulate(omap->dev);
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

static const struct of_device_id of_dwc3_match[] = {
	{
		.compatible =	"ti,dwc3"
	},
	{
		.compatible =	"ti,am437x-dwc3"
	},
	{ },
};
MODULE_DEVICE_TABLE(of, of_dwc3_match);

#ifdef CONFIG_PM_SLEEP
static int dwc3_omap_suspend(struct device *dev)
{
	struct dwc3_omap	*omap = dev_get_drvdata(dev);

	omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap);
	dwc3_omap_disable_irqs(omap);

	return 0;
}

static int dwc3_omap_resume(struct device *dev)
{
	struct dwc3_omap	*omap = dev_get_drvdata(dev);

	dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl);
	dwc3_omap_enable_irqs(omap);

	pm_runtime_disable(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	return 0;
}

static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {

	SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
};

#define DEV_PM_OPS	(&dwc3_omap_dev_pm_ops)
#else
#define DEV_PM_OPS	NULL
#endif /* CONFIG_PM_SLEEP */

static struct platform_driver dwc3_omap_driver = {
	.probe		= dwc3_omap_probe,
	.remove		= dwc3_omap_remove,
	.driver		= {
		.name	= "omap-dwc3",
		.of_match_table	= of_dwc3_match,
		.pm	= DEV_PM_OPS,
	},
};

module_platform_driver(dwc3_omap_driver);

MODULE_ALIAS("platform:omap-dwc3");
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
Commit	Line	Data
72246da4 FB	1	/**
	2	* dwc3-omap.c - OMAP Specific Glue layer
	3	*
	4	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4 FB	5	*
	6	* Authors: Felipe Balbi <balbi@ti.com>,
	7	* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
	8	*
5945f789 FB	9	* This program is free software: you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 of
	11	* the License as published by the Free Software Foundation.
72246da4	12	*
5945f789 FB	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
72246da4 FB	17	*/
72246da4 FB	18
a72e658b	19	#include <linux/module.h>
72246da4 FB	20	#include <linux/kernel.h>
	21	#include <linux/slab.h>
	22	#include <linux/interrupt.h>
72246da4	23	#include <linux/platform_device.h>
9962444f	24	#include <linux/platform_data/dwc3-omap.h>
af310e96	25	#include <linux/pm_runtime.h>
72246da4 FB	26	#include <linux/dma-mapping.h>
	27	#include <linux/ioport.h>
	28	#include <linux/io.h>
45b3cd4a	29	#include <linux/of.h>
b4bfe6aa	30	#include <linux/of_platform.h>
8061ad72	31	#include <linux/extcon.h>
8061ad72	32	#include <linux/regulator/consumer.h>
72246da4	33
a418cc4e	34	#include <linux/usb/otg.h>
a418cc4e	35
72246da4 FB	36	/*
	37	* All these registers belong to OMAP's Wrapper around the
	38	* DesignWare USB3 Core.
	39	*/
	40
	41	#define USBOTGSS_REVISION 0x0000
	42	#define USBOTGSS_SYSCONFIG 0x0010
	43	#define USBOTGSS_IRQ_EOI 0x0020
ff7307b5	44	#define USBOTGSS_EOI_OFFSET 0x0008
72246da4 FB	45	#define USBOTGSS_IRQSTATUS_RAW_0 0x0024
	46	#define USBOTGSS_IRQSTATUS_0 0x0028
	47	#define USBOTGSS_IRQENABLE_SET_0 0x002c
	48	#define USBOTGSS_IRQENABLE_CLR_0 0x0030
ff7307b5	49	#define USBOTGSS_IRQ0_OFFSET 0x0004
b1fd6cb5 GC	50	#define USBOTGSS_IRQSTATUS_RAW_1 0x0030
	51	#define USBOTGSS_IRQSTATUS_1 0x0034
	52	#define USBOTGSS_IRQENABLE_SET_1 0x0038
	53	#define USBOTGSS_IRQENABLE_CLR_1 0x003c
	54	#define USBOTGSS_IRQSTATUS_RAW_2 0x0040
	55	#define USBOTGSS_IRQSTATUS_2 0x0044
	56	#define USBOTGSS_IRQENABLE_SET_2 0x0048
	57	#define USBOTGSS_IRQENABLE_CLR_2 0x004c
	58	#define USBOTGSS_IRQSTATUS_RAW_3 0x0050
	59	#define USBOTGSS_IRQSTATUS_3 0x0054
	60	#define USBOTGSS_IRQENABLE_SET_3 0x0058
	61	#define USBOTGSS_IRQENABLE_CLR_3 0x005c
ff7307b5 GC	62	#define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030
	63	#define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034
	64	#define USBOTGSS_IRQSTATUS_MISC 0x0038
	65	#define USBOTGSS_IRQENABLE_SET_MISC 0x003c
	66	#define USBOTGSS_IRQENABLE_CLR_MISC 0x0040
	67	#define USBOTGSS_IRQMISC_OFFSET 0x03fc
22832190 BL	68	#define USBOTGSS_UTMI_OTG_STATUS 0x0080
22832190 BL	69	#define USBOTGSS_UTMI_OTG_CTRL 0x0084
ff7307b5 GC	70	#define USBOTGSS_UTMI_OTG_OFFSET 0x0480
	71	#define USBOTGSS_TXFIFO_DEPTH 0x0508
	72	#define USBOTGSS_RXFIFO_DEPTH 0x050c
72246da4 FB	73	#define USBOTGSS_MMRAM_OFFSET 0x0100
	74	#define USBOTGSS_FLADJ 0x0104
	75	#define USBOTGSS_DEBUG_CFG 0x0108
	76	#define USBOTGSS_DEBUG_DATA 0x010c
ff7307b5 GC	77	#define USBOTGSS_DEV_EBC_EN 0x0110
ff7307b5 GC	78	#define USBOTGSS_DEBUG_OFFSET 0x0600
72246da4 FB	79
	80	/* SYSCONFIG REGISTER */
	81	#define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
4b5faa7a	82
72246da4 FB	83	/* IRQ_EOI REGISTER */
	84	#define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
	85
	86	/* IRQS0 BITS */
	87	#define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
	88
b1fd6cb5 GC	89	/* IRQMISC BITS */
	90	#define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17)
	91	#define USBOTGSS_IRQMISC_OEVT (1 << 16)
	92	#define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13)
	93	#define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12)
	94	#define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11)
	95	#define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8)
	96	#define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5)
	97	#define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4)
	98	#define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3)
	99	#define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0)
72246da4	100
72246da4	101	/* UTMI_OTG_STATUS REGISTER */
22832190 BL	102	#define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS (1 << 5)
	103	#define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS (1 << 4)
	104	#define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS (1 << 3)
	105	#define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP (1 << 0)
	106
	107	/* UTMI_OTG_CTRL REGISTER */
	108	#define USBOTGSS_UTMI_OTG_CTRL_SW_MODE (1 << 31)
	109	#define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT (1 << 9)
	110	#define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE (1 << 8)
	111	#define USBOTGSS_UTMI_OTG_CTRL_IDDIG (1 << 4)
	112	#define USBOTGSS_UTMI_OTG_CTRL_SESSEND (1 << 3)
	113	#define USBOTGSS_UTMI_OTG_CTRL_SESSVALID (1 << 2)
	114	#define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID (1 << 1)
72246da4 FB	115
72246da4 FB	116	struct dwc3_omap {
72246da4 FB	117	struct device *dev;
	118
	119	int irq;
	120	void __iomem *base;
	121
22832190	122	u32 utmi_otg_ctrl;
1e2a064c GC	123	u32 utmi_otg_offset;
	124	u32 irqmisc_offset;
	125	u32 irq_eoi_offset;
	126	u32 debug_offset;
	127	u32 irq0_offset;
f3e117f4	128
72246da4	129	u32 dma_status:1;
8061ad72	130
5960387a	131	struct extcon_dev *edev;
8061ad72 KVA	132	struct notifier_block vbus_nb;
	133	struct notifier_block id_nb;
	134
	135	struct regulator *vbus_reg;
72246da4 FB	136	};
72246da4 FB	137
8061ad72 KVA	138	enum omap_dwc3_vbus_id_status {
	139	OMAP_DWC3_ID_FLOAT,
	140	OMAP_DWC3_ID_GROUND,
	141	OMAP_DWC3_VBUS_OFF,
	142	OMAP_DWC3_VBUS_VALID,
	143	};
7e41bba9	144
ab5e59db IS	145	static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
	146	{
	147	return readl(base + offset);
	148	}
	149
	150	static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
	151	{
	152	writel(value, base + offset);
	153	}
	154
22832190	155	static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap)
b1fd6cb5	156	{
22832190	157	return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL +
b1fd6cb5 GC	158	omap->utmi_otg_offset);
	159	}
	160
22832190	161	static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value)
b1fd6cb5	162	{
22832190	163	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL +
b1fd6cb5 GC	164	omap->utmi_otg_offset, value);
	165
	166	}
	167
	168	static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
	169	{
	170	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
	171	omap->irq0_offset);
	172	}
	173
	174	static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
	175	{
	176	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
	177	omap->irq0_offset, value);
	178
	179	}
	180
	181	static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
	182	{
	183	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
	184	omap->irqmisc_offset);
	185	}
	186
	187	static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
	188	{
	189	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
	190	omap->irqmisc_offset, value);
	191
	192	}
	193
	194	static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
	195	{
	196	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
	197	omap->irqmisc_offset, value);
	198
	199	}
	200
	201	static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
	202	{
	203	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
	204	omap->irq0_offset, value);
	205	}
	206
96e5d312 GC	207	static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
	208	{
	209	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
	210	omap->irqmisc_offset, value);
	211	}
	212
	213	static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
	214	{
	215	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
	216	omap->irq0_offset, value);
	217	}
	218
8061ad72 KVA	219	static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
8061ad72 KVA	220	enum omap_dwc3_vbus_id_status status)
7e41bba9	221	{
8061ad72 KVA	222	int ret;
8061ad72 KVA	223	u32 val;
2ba7943a	224
7e41bba9 KVA	225	switch (status) {
7e41bba9 KVA	226	case OMAP_DWC3_ID_GROUND:
8061ad72 KVA	227	if (omap->vbus_reg) {
	228	ret = regulator_enable(omap->vbus_reg);
	229	if (ret) {
e4f75667	230	dev_err(omap->dev, "regulator enable failed\n");
8061ad72 KVA	231	return;
	232	}
	233	}
	234
22832190 BL	235	val = dwc3_omap_read_utmi_ctrl(omap);
	236	val &= ~(USBOTGSS_UTMI_OTG_CTRL_IDDIG
	237	\| USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
	238	\| USBOTGSS_UTMI_OTG_CTRL_SESSEND);
	239	val \|= USBOTGSS_UTMI_OTG_CTRL_SESSVALID
	240	\| USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT;
	241	dwc3_omap_write_utmi_ctrl(omap, val);
7e41bba9 KVA	242	break;
	243
	244	case OMAP_DWC3_VBUS_VALID:
22832190 BL	245	val = dwc3_omap_read_utmi_ctrl(omap);
	246	val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND;
	247	val \|= USBOTGSS_UTMI_OTG_CTRL_IDDIG
	248	\| USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
	249	\| USBOTGSS_UTMI_OTG_CTRL_SESSVALID
	250	\| USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT;
	251	dwc3_omap_write_utmi_ctrl(omap, val);
7e41bba9 KVA	252	break;
	253
	254	case OMAP_DWC3_ID_FLOAT:
8061ad72 KVA	255	if (omap->vbus_reg)
	256	regulator_disable(omap->vbus_reg);
	257
7e41bba9	258	case OMAP_DWC3_VBUS_OFF:
22832190 BL	259	val = dwc3_omap_read_utmi_ctrl(omap);
	260	val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID
	261	\| USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
	262	\| USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT);
	263	val \|= USBOTGSS_UTMI_OTG_CTRL_SESSEND
	264	\| USBOTGSS_UTMI_OTG_CTRL_IDDIG;
	265	dwc3_omap_write_utmi_ctrl(omap, val);
7e41bba9 KVA	266	break;
	267
	268	default:
e4f75667	269	dev_WARN(omap->dev, "invalid state\n");
7e41bba9	270	}
7e41bba9	271	}
7e41bba9	272
72246da4 FB	273	static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
	274	{
	275	struct dwc3_omap *omap = _omap;
	276	u32 reg;
72246da4	277
b1fd6cb5	278	reg = dwc3_omap_read_irqmisc_status(omap);
72246da4	279
e4f75667	280	if (reg & USBOTGSS_IRQMISC_DMADISABLECLR)
72246da4	281	omap->dma_status = false;
72246da4	282
b1fd6cb5 GC	283	dwc3_omap_write_irqmisc_status(omap, reg);
	284
	285	reg = dwc3_omap_read_irq0_status(omap);
42077b0a	286
b1fd6cb5	287	dwc3_omap_write_irq0_status(omap, reg);
72246da4	288
72246da4 FB	289	return IRQ_HANDLED;
	290	}
	291
9a4b5dab FB	292	static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
	293	{
	294	u32 reg;
	295
	296	/* enable all IRQs */
	297	reg = USBOTGSS_IRQO_COREIRQ_ST;
b1fd6cb5 GC	298	dwc3_omap_write_irq0_set(omap, reg);
	299
	300	reg = (USBOTGSS_IRQMISC_OEVT \|
	301	USBOTGSS_IRQMISC_DRVVBUS_RISE \|
	302	USBOTGSS_IRQMISC_CHRGVBUS_RISE \|
	303	USBOTGSS_IRQMISC_DISCHRGVBUS_RISE \|
	304	USBOTGSS_IRQMISC_IDPULLUP_RISE \|
	305	USBOTGSS_IRQMISC_DRVVBUS_FALL \|
	306	USBOTGSS_IRQMISC_CHRGVBUS_FALL \|
	307	USBOTGSS_IRQMISC_DISCHRGVBUS_FALL \|
	308	USBOTGSS_IRQMISC_IDPULLUP_FALL);
	309
	310	dwc3_omap_write_irqmisc_set(omap, reg);
9a4b5dab FB	311	}
	312
	313	static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
	314	{
96e5d312 GC	315	u32 reg;
96e5d312 GC	316
9a4b5dab	317	/* disable all IRQs */
96e5d312 GC	318	reg = USBOTGSS_IRQO_COREIRQ_ST;
	319	dwc3_omap_write_irq0_clr(omap, reg);
	320
	321	reg = (USBOTGSS_IRQMISC_OEVT \|
	322	USBOTGSS_IRQMISC_DRVVBUS_RISE \|
	323	USBOTGSS_IRQMISC_CHRGVBUS_RISE \|
	324	USBOTGSS_IRQMISC_DISCHRGVBUS_RISE \|
	325	USBOTGSS_IRQMISC_IDPULLUP_RISE \|
	326	USBOTGSS_IRQMISC_DRVVBUS_FALL \|
	327	USBOTGSS_IRQMISC_CHRGVBUS_FALL \|
	328	USBOTGSS_IRQMISC_DISCHRGVBUS_FALL \|
	329	USBOTGSS_IRQMISC_IDPULLUP_FALL);
	330
	331	dwc3_omap_write_irqmisc_clr(omap, reg);
9a4b5dab FB	332	}
9a4b5dab FB	333
ddff14f1 KVA	334	static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);
ddff14f1 KVA	335
8061ad72 KVA	336	static int dwc3_omap_id_notifier(struct notifier_block *nb,
	337	unsigned long event, void *ptr)
	338	{
	339	struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);
	340
	341	if (event)
	342	dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
	343	else
	344	dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
	345
	346	return NOTIFY_DONE;
	347	}
	348
	349	static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
	350	unsigned long event, void *ptr)
	351	{
	352	struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);
	353
	354	if (event)
	355	dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
	356	else
	357	dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
	358
	359	return NOTIFY_DONE;
	360	}
	361
30fef1a9 GC	362	static void dwc3_omap_map_offset(struct dwc3_omap *omap)
	363	{
	364	struct device_node *node = omap->dev->of_node;
	365
	366	/*
	367	* Differentiate between OMAP5 and AM437x.
	368	*
	369	* For OMAP5(ES2.0) and AM437x wrapper revision is same, even
	370	* though there are changes in wrapper register offsets.
	371	*
	372	* Using dt compatible to differentiate AM437x.
	373	*/
	374	if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
	375	omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
	376	omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
	377	omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
	378	omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
	379	omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
	380	}
	381	}
	382
d2f0cf89 GC	383	static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
	384	{
	385	u32 reg;
	386	struct device_node *node = omap->dev->of_node;
	387	int utmi_mode = 0;
	388
22832190	389	reg = dwc3_omap_read_utmi_ctrl(omap);
d2f0cf89 GC	390
	391	of_property_read_u32(node, "utmi-mode", &utmi_mode);
	392
	393	switch (utmi_mode) {
	394	case DWC3_OMAP_UTMI_MODE_SW:
22832190	395	reg \|= USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
d2f0cf89 GC	396	break;
d2f0cf89 GC	397	case DWC3_OMAP_UTMI_MODE_HW:
22832190	398	reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
d2f0cf89 GC	399	break;
d2f0cf89 GC	400	default:
e4f75667	401	dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
d2f0cf89 GC	402	}
d2f0cf89 GC	403
22832190	404	dwc3_omap_write_utmi_ctrl(omap, reg);
d2f0cf89 GC	405	}
d2f0cf89 GC	406
025b431b GC	407	static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
025b431b GC	408	{
788b0bc4	409	int ret;
025b431b GC	410	struct device_node *node = omap->dev->of_node;
	411	struct extcon_dev *edev;
	412
	413	if (of_property_read_bool(node, "extcon")) {
	414	edev = extcon_get_edev_by_phandle(omap->dev, 0);
	415	if (IS_ERR(edev)) {
	416	dev_vdbg(omap->dev, "couldn't get extcon device\n");
	417	return -EPROBE_DEFER;
	418	}
	419
	420	omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
5960387a CC	421	ret = extcon_register_notifier(edev, EXTCON_USB,
5960387a CC	422	&omap->vbus_nb);
025b431b GC	423	if (ret < 0)
	424	dev_vdbg(omap->dev, "failed to register notifier for USB\n");
	425
	426	omap->id_nb.notifier_call = dwc3_omap_id_notifier;
5960387a CC	427	ret = extcon_register_notifier(edev, EXTCON_USB_HOST,
5960387a CC	428	&omap->id_nb);
025b431b GC	429	if (ret < 0)
	430	dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n");
	431
5960387a	432	if (extcon_get_cable_state_(edev, EXTCON_USB) == true)
025b431b	433	dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
5960387a	434	if (extcon_get_cable_state_(edev, EXTCON_USB_HOST) == true)
025b431b	435	dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
5960387a CC	436
5960387a CC	437	omap->edev = edev;
025b431b GC	438	}
	439
	440	return 0;
	441	}
	442
41ac7b3a	443	static int dwc3_omap_probe(struct platform_device *pdev)
72246da4	444	{
45b3cd4a FB	445	struct device_node *node = pdev->dev.of_node;
45b3cd4a FB	446
72246da4 FB	447	struct dwc3_omap *omap;
72246da4 FB	448	struct resource *res;
802ca850	449	struct device *dev = &pdev->dev;
8061ad72	450	struct regulator *vbus_reg = NULL;
72246da4	451
b09e99ee	452	int ret;
72246da4 FB	453	int irq;
	454
	455	u32 reg;
	456
	457	void __iomem *base;
72246da4	458
4495afcf KVA	459	if (!node) {
	460	dev_err(dev, "device node not found\n");
	461	return -EINVAL;
	462	}
	463
802ca850	464	omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
734d5a53	465	if (!omap)
802ca850	466	return -ENOMEM;
72246da4 FB	467
	468	platform_set_drvdata(pdev, omap);
	469
e36a0c87	470	irq = platform_get_irq(pdev, 0);
72246da4	471	if (irq < 0) {
802ca850 CP	472	dev_err(dev, "missing IRQ resource\n");
802ca850 CP	473	return -EINVAL;
72246da4 FB	474	}
72246da4 FB	475
e36a0c87	476	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8bbcd17d FB	477	base = devm_ioremap_resource(dev, res);
	478	if (IS_ERR(base))
	479	return PTR_ERR(base);
72246da4	480
8061ad72 KVA	481	if (of_property_read_bool(node, "vbus-supply")) {
	482	vbus_reg = devm_regulator_get(dev, "vbus");
	483	if (IS_ERR(vbus_reg)) {
	484	dev_err(dev, "vbus init failed\n");
	485	return PTR_ERR(vbus_reg);
	486	}
	487	}
	488
802ca850	489	omap->dev = dev;
72246da4 FB	490	omap->irq = irq;
72246da4 FB	491	omap->base = base;
8061ad72	492	omap->vbus_reg = vbus_reg;
ddff14f1	493	dev->dma_mask = &dwc3_omap_dma_mask;
72246da4	494
af310e96 KVA	495	pm_runtime_enable(dev);
	496	ret = pm_runtime_get_sync(dev);
	497	if (ret < 0) {
	498	dev_err(dev, "get_sync failed with err %d\n", ret);
45d49cb7	499	goto err1;
af310e96 KVA	500	}
af310e96 KVA	501
30fef1a9	502	dwc3_omap_map_offset(omap);
d2f0cf89	503	dwc3_omap_set_utmi_mode(omap);
9962444f	504
72246da4	505	/* check the DMA Status */
ab5e59db	506	reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
72246da4 FB	507	omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
72246da4 FB	508
802ca850	509	ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
dd17a6b2	510	"dwc3-omap", omap);
72246da4	511	if (ret) {
802ca850	512	dev_err(dev, "failed to request IRQ #%d --> %d\n",
72246da4	513	omap->irq, ret);
594daba1	514	goto err1;
72246da4 FB	515	}
72246da4 FB	516
025b431b GC	517	ret = dwc3_omap_extcon_register(omap);
025b431b GC	518	if (ret < 0)
45d49cb7	519	goto err1;
8061ad72	520
4495afcf KVA	521	ret = of_platform_populate(node, NULL, NULL, dev);
	522	if (ret) {
	523	dev_err(&pdev->dev, "failed to create dwc3 core\n");
45d49cb7	524	goto err2;
72246da4 FB	525	}
72246da4 FB	526
e2ae0692 FB	527	dwc3_omap_enable_irqs(omap);
e2ae0692 FB	528
72246da4	529	return 0;
594daba1	530
45d49cb7	531	err2:
5960387a CC	532	extcon_unregister_notifier(omap->edev, EXTCON_USB, &omap->vbus_nb);
5960387a CC	533	extcon_unregister_notifier(omap->edev, EXTCON_USB_HOST, &omap->id_nb);
594daba1 KVA	534
	535	err1:
	536	pm_runtime_put_sync(dev);
594daba1 KVA	537	pm_runtime_disable(dev);
	538
	539	return ret;
72246da4 FB	540	}
72246da4 FB	541
fb4e98ab	542	static int dwc3_omap_remove(struct platform_device *pdev)
72246da4	543	{
9a4b5dab FB	544	struct dwc3_omap *omap = platform_get_drvdata(pdev);
9a4b5dab FB	545
5960387a CC	546	extcon_unregister_notifier(omap->edev, EXTCON_USB, &omap->vbus_nb);
5960387a CC	547	extcon_unregister_notifier(omap->edev, EXTCON_USB_HOST, &omap->id_nb);
9a4b5dab	548	dwc3_omap_disable_irqs(omap);
3d0184d0	549	of_platform_depopulate(omap->dev);
af310e96 KVA	550	pm_runtime_put_sync(&pdev->dev);
af310e96 KVA	551	pm_runtime_disable(&pdev->dev);
94c6a436	552
72246da4 FB	553	return 0;
	554	}
	555
2c2dc89c	556	static const struct of_device_id of_dwc3_match[] = {
72246da4	557	{
e36a0c87	558	.compatible = "ti,dwc3"
72246da4	559	},
ff7307b5 GC	560	{
	561	.compatible = "ti,am437x-dwc3"
	562	},
72246da4 FB	563	{ },
72246da4 FB	564	};
2c2dc89c	565	MODULE_DEVICE_TABLE(of, of_dwc3_match);
72246da4	566
19fda7cd	567	#ifdef CONFIG_PM_SLEEP
f3e117f4 FB	568	static int dwc3_omap_suspend(struct device *dev)
	569	{
	570	struct dwc3_omap *omap = dev_get_drvdata(dev);
	571
22832190	572	omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap);
7ee2566f	573	dwc3_omap_disable_irqs(omap);
f3e117f4 FB	574
	575	return 0;
	576	}
	577
	578	static int dwc3_omap_resume(struct device *dev)
	579	{
	580	struct dwc3_omap *omap = dev_get_drvdata(dev);
	581
22832190	582	dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl);
7ee2566f	583	dwc3_omap_enable_irqs(omap);
f3e117f4 FB	584
	585	pm_runtime_disable(dev);
	586	pm_runtime_set_active(dev);
	587	pm_runtime_enable(dev);
	588
	589	return 0;
	590	}
	591
	592	static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
f3e117f4 FB	593
	594	SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
	595	};
	596
	597	#define DEV_PM_OPS (&dwc3_omap_dev_pm_ops)
	598	#else
	599	#define DEV_PM_OPS NULL
19fda7cd	600	#endif /* CONFIG_PM_SLEEP */
f3e117f4	601
72246da4 FB	602	static struct platform_driver dwc3_omap_driver = {
72246da4 FB	603	.probe = dwc3_omap_probe,
7690417d	604	.remove = dwc3_omap_remove,
72246da4 FB	605	.driver = {
72246da4 FB	606	.name = "omap-dwc3",
2c2dc89c	607	.of_match_table = of_dwc3_match,
f3e117f4	608	.pm = DEV_PM_OPS,
72246da4 FB	609	},
	610	};
	611
cc27c96c AL	612	module_platform_driver(dwc3_omap_driver);
cc27c96c AL	613
7ae4fc4d	614	MODULE_ALIAS("platform:omap-dwc3");
72246da4	615	MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
5945f789	616	MODULE_LICENSE("GPL v2");
72246da4	617	MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");