Commit | Line | Data |
---|---|---|
b33f69f5 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
bfad65ee | 2 | /* |
72246da4 FB |
3 | * core.h - DesignWare USB3 DRD Core Header |
4 | * | |
10623b87 | 5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com |
72246da4 FB |
6 | * |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
72246da4 FB |
9 | */ |
10 | ||
11 | #ifndef __DRIVERS_USB_DWC3_CORE_H | |
12 | #define __DRIVERS_USB_DWC3_CORE_H | |
13 | ||
14 | #include <linux/device.h> | |
15 | #include <linux/spinlock.h> | |
f88359e1 | 16 | #include <linux/mutex.h> |
d07e8819 | 17 | #include <linux/ioport.h> |
72246da4 | 18 | #include <linux/list.h> |
ff3f0789 | 19 | #include <linux/bitops.h> |
72246da4 FB |
20 | #include <linux/dma-mapping.h> |
21 | #include <linux/mm.h> | |
22 | #include <linux/debugfs.h> | |
76a638f8 | 23 | #include <linux/wait.h> |
41ce1456 | 24 | #include <linux/workqueue.h> |
72246da4 FB |
25 | |
26 | #include <linux/usb/ch9.h> | |
27 | #include <linux/usb/gadget.h> | |
a45c82b8 | 28 | #include <linux/usb/otg.h> |
8a0a1379 | 29 | #include <linux/usb/role.h> |
88bc9d19 | 30 | #include <linux/ulpi/interface.h> |
72246da4 | 31 | |
57303488 KVA |
32 | #include <linux/phy/phy.h> |
33 | ||
6f0764b5 RC |
34 | #include <linux/power_supply.h> |
35 | ||
2c4cbe6e FB |
36 | #define DWC3_MSG_MAX 500 |
37 | ||
72246da4 | 38 | /* Global constants */ |
bb014736 | 39 | #define DWC3_PULL_UP_TIMEOUT 500 /* ms */ |
905dc04e | 40 | #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */ |
4199c5f8 | 41 | #define DWC3_EP0_SETUP_SIZE 512 |
72246da4 | 42 | #define DWC3_ENDPOINTS_NUM 32 |
51249dca | 43 | #define DWC3_XHCI_RESOURCES_NUM 2 |
d5370106 | 44 | #define DWC3_ISOC_MAX_RETRIES 5 |
72246da4 | 45 | |
0ffcaf37 | 46 | #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ |
e71d363d | 47 | #define DWC3_EVENT_BUFFERS_SIZE 4096 |
72246da4 FB |
48 | #define DWC3_EVENT_TYPE_MASK 0xfe |
49 | ||
50 | #define DWC3_EVENT_TYPE_DEV 0 | |
51 | #define DWC3_EVENT_TYPE_CARKIT 3 | |
52 | #define DWC3_EVENT_TYPE_I2C 4 | |
53 | ||
54 | #define DWC3_DEVICE_EVENT_DISCONNECT 0 | |
55 | #define DWC3_DEVICE_EVENT_RESET 1 | |
56 | #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 | |
57 | #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 | |
58 | #define DWC3_DEVICE_EVENT_WAKEUP 4 | |
2c61a8ef | 59 | #define DWC3_DEVICE_EVENT_HIBER_REQ 5 |
6f26ebb7 | 60 | #define DWC3_DEVICE_EVENT_SUSPEND 6 |
72246da4 FB |
61 | #define DWC3_DEVICE_EVENT_SOF 7 |
62 | #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 | |
63 | #define DWC3_DEVICE_EVENT_CMD_CMPL 10 | |
64 | #define DWC3_DEVICE_EVENT_OVERFLOW 11 | |
65 | ||
f09cc79b RQ |
66 | /* Controller's role while using the OTG block */ |
67 | #define DWC3_OTG_ROLE_IDLE 0 | |
68 | #define DWC3_OTG_ROLE_HOST 1 | |
69 | #define DWC3_OTG_ROLE_DEVICE 2 | |
70 | ||
72246da4 | 71 | #define DWC3_GEVNTCOUNT_MASK 0xfffc |
ff3f0789 | 72 | #define DWC3_GEVNTCOUNT_EHB BIT(31) |
72246da4 FB |
73 | #define DWC3_GSNPSID_MASK 0xffff0000 |
74 | #define DWC3_GSNPSREV_MASK 0xffff | |
9af21dd6 | 75 | #define DWC3_GSNPS_ID(p) (((p) & DWC3_GSNPSID_MASK) >> 16) |
72246da4 | 76 | |
51249dca IS |
77 | /* DWC3 registers memory space boundries */ |
78 | #define DWC3_XHCI_REGS_START 0x0 | |
79 | #define DWC3_XHCI_REGS_END 0x7fff | |
80 | #define DWC3_GLOBALS_REGS_START 0xc100 | |
81 | #define DWC3_GLOBALS_REGS_END 0xc6ff | |
82 | #define DWC3_DEVICE_REGS_START 0xc700 | |
83 | #define DWC3_DEVICE_REGS_END 0xcbff | |
84 | #define DWC3_OTG_REGS_START 0xcc00 | |
85 | #define DWC3_OTG_REGS_END 0xccff | |
86 | ||
ec5eb438 SC |
87 | #define DWC3_RTK_RTD_GLOBALS_REGS_START 0x8100 |
88 | ||
72246da4 FB |
89 | /* Global Registers */ |
90 | #define DWC3_GSBUSCFG0 0xc100 | |
91 | #define DWC3_GSBUSCFG1 0xc104 | |
92 | #define DWC3_GTXTHRCFG 0xc108 | |
93 | #define DWC3_GRXTHRCFG 0xc10c | |
94 | #define DWC3_GCTL 0xc110 | |
95 | #define DWC3_GEVTEN 0xc114 | |
96 | #define DWC3_GSTS 0xc118 | |
475c8beb | 97 | #define DWC3_GUCTL1 0xc11c |
72246da4 FB |
98 | #define DWC3_GSNPSID 0xc120 |
99 | #define DWC3_GGPIO 0xc124 | |
100 | #define DWC3_GUID 0xc128 | |
101 | #define DWC3_GUCTL 0xc12c | |
102 | #define DWC3_GBUSERRADDR0 0xc130 | |
103 | #define DWC3_GBUSERRADDR1 0xc134 | |
104 | #define DWC3_GPRTBIMAP0 0xc138 | |
105 | #define DWC3_GPRTBIMAP1 0xc13c | |
106 | #define DWC3_GHWPARAMS0 0xc140 | |
107 | #define DWC3_GHWPARAMS1 0xc144 | |
108 | #define DWC3_GHWPARAMS2 0xc148 | |
109 | #define DWC3_GHWPARAMS3 0xc14c | |
110 | #define DWC3_GHWPARAMS4 0xc150 | |
111 | #define DWC3_GHWPARAMS5 0xc154 | |
112 | #define DWC3_GHWPARAMS6 0xc158 | |
113 | #define DWC3_GHWPARAMS7 0xc15c | |
114 | #define DWC3_GDBGFIFOSPACE 0xc160 | |
115 | #define DWC3_GDBGLTSSM 0xc164 | |
80b77634 TN |
116 | #define DWC3_GDBGBMU 0xc16c |
117 | #define DWC3_GDBGLSPMUX 0xc170 | |
118 | #define DWC3_GDBGLSP 0xc174 | |
119 | #define DWC3_GDBGEPINFO0 0xc178 | |
120 | #define DWC3_GDBGEPINFO1 0xc17c | |
72246da4 FB |
121 | #define DWC3_GPRTBIMAP_HS0 0xc180 |
122 | #define DWC3_GPRTBIMAP_HS1 0xc184 | |
123 | #define DWC3_GPRTBIMAP_FS0 0xc188 | |
124 | #define DWC3_GPRTBIMAP_FS1 0xc18c | |
06281d46 | 125 | #define DWC3_GUCTL2 0xc19c |
72246da4 | 126 | |
690fb371 JY |
127 | #define DWC3_VER_NUMBER 0xc1a0 |
128 | #define DWC3_VER_TYPE 0xc1a4 | |
129 | ||
8261bd4e RQ |
130 | #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04)) |
131 | #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04)) | |
72246da4 | 132 | |
8261bd4e | 133 | #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04)) |
72246da4 | 134 | |
8261bd4e | 135 | #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04)) |
72246da4 | 136 | |
8261bd4e RQ |
137 | #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04)) |
138 | #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04)) | |
72246da4 | 139 | |
8261bd4e RQ |
140 | #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10)) |
141 | #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10)) | |
142 | #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10)) | |
143 | #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) | |
72246da4 FB |
144 | |
145 | #define DWC3_GHWPARAMS8 0xc600 | |
f580170f | 146 | #define DWC3_GUCTL3 0xc60c |
db2be4e9 | 147 | #define DWC3_GFLADJ 0xc630 |
250fdabe | 148 | #define DWC3_GHWPARAMS9 0xc6e0 |
72246da4 FB |
149 | |
150 | /* Device Registers */ | |
151 | #define DWC3_DCFG 0xc700 | |
152 | #define DWC3_DCTL 0xc704 | |
153 | #define DWC3_DEVTEN 0xc708 | |
154 | #define DWC3_DSTS 0xc70c | |
155 | #define DWC3_DGCMDPAR 0xc710 | |
156 | #define DWC3_DGCMD 0xc714 | |
157 | #define DWC3_DALEPENA 0xc720 | |
666f3de7 | 158 | #define DWC3_DCFG1 0xc740 /* DWC_usb32 only */ |
2eb88016 | 159 | |
8261bd4e | 160 | #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10)) |
2eb88016 FB |
161 | #define DWC3_DEPCMDPAR2 0x00 |
162 | #define DWC3_DEPCMDPAR1 0x04 | |
163 | #define DWC3_DEPCMDPAR0 0x08 | |
164 | #define DWC3_DEPCMD 0x0c | |
72246da4 | 165 | |
8261bd4e | 166 | #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4)) |
cf40b86b | 167 | |
72246da4 FB |
168 | /* OTG Registers */ |
169 | #define DWC3_OCFG 0xcc00 | |
170 | #define DWC3_OCTL 0xcc04 | |
d4436c3a GC |
171 | #define DWC3_OEVT 0xcc08 |
172 | #define DWC3_OEVTEN 0xcc0C | |
173 | #define DWC3_OSTS 0xcc10 | |
72246da4 FB |
174 | |
175 | /* Bit fields */ | |
176 | ||
d635db55 PM |
177 | /* Global SoC Bus Configuration INCRx Register 0 */ |
178 | #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */ | |
179 | #define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */ | |
180 | #define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */ | |
181 | #define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */ | |
182 | #define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */ | |
183 | #define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */ | |
184 | #define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */ | |
185 | #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */ | |
186 | #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff | |
187 | ||
62ba09d6 TN |
188 | /* Global Debug LSP MUX Select */ |
189 | #define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */ | |
190 | #define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff) | |
191 | #define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4) | |
192 | #define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf) | |
193 | ||
cf6d867d FB |
194 | /* Global Debug Queue/FIFO Space Available Register */ |
195 | #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) | |
196 | #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) | |
197 | #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff) | |
198 | ||
2c85a181 TN |
199 | #define DWC3_TXFIFO 0 |
200 | #define DWC3_RXFIFO 1 | |
b16ea8b9 TN |
201 | #define DWC3_TXREQQ 2 |
202 | #define DWC3_RXREQQ 3 | |
203 | #define DWC3_RXINFOQ 4 | |
204 | #define DWC3_PSTATQ 5 | |
205 | #define DWC3_DESCFETCHQ 6 | |
206 | #define DWC3_EVENTQ 7 | |
207 | #define DWC3_AUXEVENTQ 8 | |
cf6d867d | 208 | |
2a58f9c1 FB |
209 | /* Global RX Threshold Configuration Register */ |
210 | #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19) | |
211 | #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24) | |
ff3f0789 | 212 | #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29) |
2a58f9c1 | 213 | |
2fbc5bdc TN |
214 | /* Global RX Threshold Configuration Register for DWC_usb31 only */ |
215 | #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16) | |
216 | #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21) | |
217 | #define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26) | |
218 | #define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15) | |
219 | #define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) | |
220 | #define DWC31_RXTHRNUMPKTSEL_PRD BIT(10) | |
221 | #define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) | |
222 | #define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f) | |
223 | ||
6743e817 TN |
224 | /* Global TX Threshold Configuration Register for DWC_usb31 only */ |
225 | #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16) | |
226 | #define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21) | |
227 | #define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26) | |
228 | #define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15) | |
229 | #define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) | |
230 | #define DWC31_TXTHRNUMPKTSEL_PRD BIT(10) | |
231 | #define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) | |
232 | #define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f) | |
233 | ||
72246da4 | 234 | /* Global Configuration Register */ |
1d046793 | 235 | #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) |
3497b9a5 | 236 | #define DWC3_GCTL_PWRDNSCALE_MASK GENMASK(31, 19) |
ff3f0789 | 237 | #define DWC3_GCTL_U2RSTECN BIT(16) |
1d046793 | 238 | #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) |
72246da4 FB |
239 | #define DWC3_GCTL_CLK_BUS (0) |
240 | #define DWC3_GCTL_CLK_PIPE (1) | |
241 | #define DWC3_GCTL_CLK_PIPEHALF (2) | |
242 | #define DWC3_GCTL_CLK_MASK (3) | |
243 | ||
0b9fe32d | 244 | #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) |
1d046793 | 245 | #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) |
72246da4 FB |
246 | #define DWC3_GCTL_PRTCAP_HOST 1 |
247 | #define DWC3_GCTL_PRTCAP_DEVICE 2 | |
248 | #define DWC3_GCTL_PRTCAP_OTG 3 | |
249 | ||
ff3f0789 RQ |
250 | #define DWC3_GCTL_CORESOFTRESET BIT(11) |
251 | #define DWC3_GCTL_SOFITPSYNC BIT(10) | |
2c61a8ef PZ |
252 | #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) |
253 | #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) | |
ff3f0789 RQ |
254 | #define DWC3_GCTL_DISSCRAMBLE BIT(3) |
255 | #define DWC3_GCTL_U2EXIT_LFPS BIT(2) | |
256 | #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1) | |
257 | #define DWC3_GCTL_DSBLCLKGTNG BIT(0) | |
72246da4 | 258 | |
0bb39ca1 | 259 | /* Global User Control 1 Register */ |
843714bb | 260 | #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31) |
65db7a0c | 261 | #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) |
62b20e6e | 262 | #define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26) |
843714bb JP |
263 | #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) |
264 | #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) | |
d21a797a | 265 | #define DWC3_GUCTL1_PARKMODE_DISABLE_HS BIT(16) |
63d7f981 | 266 | #define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT(10) |
0bb39ca1 | 267 | |
4cff75c7 RQ |
268 | /* Global Status Register */ |
269 | #define DWC3_GSTS_OTG_IP BIT(10) | |
270 | #define DWC3_GSTS_BC_IP BIT(9) | |
271 | #define DWC3_GSTS_ADP_IP BIT(8) | |
272 | #define DWC3_GSTS_HOST_IP BIT(7) | |
273 | #define DWC3_GSTS_DEVICE_IP BIT(6) | |
274 | #define DWC3_GSTS_CSR_TIMEOUT BIT(5) | |
275 | #define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4) | |
62ba09d6 TN |
276 | #define DWC3_GSTS_CURMOD(n) ((n) & 0x3) |
277 | #define DWC3_GSTS_CURMOD_DEVICE 0 | |
278 | #define DWC3_GSTS_CURMOD_HOST 1 | |
4cff75c7 | 279 | |
72246da4 | 280 | /* Global USB2 PHY Configuration Register */ |
ff3f0789 RQ |
281 | #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31) |
282 | #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30) | |
b84ba26c | 283 | #define DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV BIT(17) |
ff3f0789 RQ |
284 | #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6) |
285 | #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4) | |
286 | #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8) | |
32f2ed86 WW |
287 | #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3) |
288 | #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) | |
289 | #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10) | |
290 | #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) | |
291 | #define USBTRDTIM_UTMI_8_BIT 9 | |
292 | #define USBTRDTIM_UTMI_16_BIT 5 | |
293 | #define UTMI_PHYIF_16_BIT 1 | |
294 | #define UTMI_PHYIF_8_BIT 0 | |
72246da4 | 295 | |
b5699eee | 296 | /* Global USB2 PHY Vendor Control Register */ |
ff3f0789 | 297 | #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25) |
ce722da6 | 298 | #define DWC3_GUSB2PHYACC_DONE BIT(24) |
ff3f0789 RQ |
299 | #define DWC3_GUSB2PHYACC_BUSY BIT(23) |
300 | #define DWC3_GUSB2PHYACC_WRITE BIT(22) | |
b5699eee HK |
301 | #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) |
302 | #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) | |
303 | #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) | |
304 | ||
72246da4 | 305 | /* Global USB3 PIPE Control Register */ |
ff3f0789 RQ |
306 | #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31) |
307 | #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29) | |
308 | #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28) | |
309 | #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27) | |
310 | #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24) | |
a2a1d0f5 HR |
311 | #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) |
312 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) | |
313 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) | |
ff3f0789 RQ |
314 | #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18) |
315 | #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17) | |
316 | #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9) | |
317 | #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8) | |
6b6a0c9a HR |
318 | #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) |
319 | #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) | |
72246da4 | 320 | |
457e84b6 | 321 | /* Global TX Fifo Size Register */ |
0cab8d26 | 322 | #define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */ |
586f4335 TN |
323 | #define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */ |
324 | #define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff) | |
2c61a8ef | 325 | #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) |
457e84b6 | 326 | |
d94ea531 TN |
327 | /* Global RX Fifo Size Register */ |
328 | #define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */ | |
329 | #define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff) | |
330 | ||
68d6a01b | 331 | /* Global Event Size Registers */ |
ff3f0789 | 332 | #define DWC3_GEVNTSIZ_INTMASK BIT(31) |
68d6a01b FB |
333 | #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) |
334 | ||
4e99472b | 335 | /* Global HWPARAMS0 Register */ |
9d6173e1 TN |
336 | #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3) |
337 | #define DWC3_GHWPARAMS0_MODE_GADGET 0 | |
338 | #define DWC3_GHWPARAMS0_MODE_HOST 1 | |
339 | #define DWC3_GHWPARAMS0_MODE_DRD 2 | |
4e99472b FB |
340 | #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7) |
341 | #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3) | |
342 | #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff) | |
343 | #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff) | |
344 | #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff) | |
345 | ||
aabb7075 | 346 | /* Global HWPARAMS1 Register */ |
1d046793 | 347 | #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) |
aabb7075 FB |
348 | #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 |
349 | #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 | |
2c61a8ef PZ |
350 | #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 |
351 | #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) | |
352 | #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) | |
62ba09d6 | 353 | #define DWC3_GHWPARAMS1_ENDBC BIT(31) |
2c61a8ef | 354 | |
0e1e5c47 PZ |
355 | /* Global HWPARAMS3 Register */ |
356 | #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) | |
357 | #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 | |
1f38f88a JY |
358 | #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1 |
359 | #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */ | |
0e1e5c47 PZ |
360 | #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) |
361 | #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 | |
362 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 | |
363 | #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 | |
364 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 | |
365 | #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) | |
366 | #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 | |
367 | #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 | |
368 | ||
2c61a8ef PZ |
369 | /* Global HWPARAMS4 Register */ |
370 | #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) | |
371 | #define DWC3_MAX_HIBER_SCRATCHBUFS 15 | |
aabb7075 | 372 | |
946bd579 | 373 | /* Global HWPARAMS6 Register */ |
4cff75c7 RQ |
374 | #define DWC3_GHWPARAMS6_BCSUPPORT BIT(14) |
375 | #define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13) | |
376 | #define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12) | |
377 | #define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11) | |
378 | #define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10) | |
ff3f0789 | 379 | #define DWC3_GHWPARAMS6_EN_FPGA BIT(7) |
946bd579 | 380 | |
4244ba02 TN |
381 | /* DWC_usb32 only */ |
382 | #define DWC3_GHWPARAMS6_MDWIDTH(n) ((n) & (0x3 << 8)) | |
383 | ||
4e99472b FB |
384 | /* Global HWPARAMS7 Register */ |
385 | #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff) | |
386 | #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff) | |
387 | ||
ddae7979 TN |
388 | /* Global HWPARAMS9 Register */ |
389 | #define DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS BIT(0) | |
666f3de7 | 390 | #define DWC3_GHWPARAMS9_DEV_MST BIT(1) |
ddae7979 | 391 | |
db2be4e9 | 392 | /* Global Frame Length Adjustment Register */ |
ff3f0789 | 393 | #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7) |
db2be4e9 | 394 | #define DWC3_GFLADJ_30MHZ_MASK 0x3f |
596c8785 | 395 | #define DWC3_GFLADJ_REFCLK_FLADJ_MASK GENMASK(21, 8) |
a6fc2f1b | 396 | #define DWC3_GFLADJ_REFCLK_LPM_SEL BIT(23) |
596c8785 SA |
397 | #define DWC3_GFLADJ_240MHZDECR GENMASK(30, 24) |
398 | #define DWC3_GFLADJ_240MHZDECR_PLS1 BIT(31) | |
db2be4e9 | 399 | |
7bee3188 BP |
400 | /* Global User Control Register*/ |
401 | #define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000 | |
402 | #define DWC3_GUCTL_REFCLKPER_SEL 22 | |
403 | ||
06281d46 | 404 | /* Global User Control Register 2 */ |
ff3f0789 | 405 | #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) |
06281d46 | 406 | |
f580170f YC |
407 | /* Global User Control Register 3 */ |
408 | #define DWC3_GUCTL3_SPLITDISABLE BIT(14) | |
409 | ||
72246da4 | 410 | /* Device Configuration Register */ |
072cab8a TN |
411 | #define DWC3_DCFG_NUMLANES(n) (((n) & 0x3) << 30) /* DWC_usb32 only */ |
412 | ||
72246da4 FB |
413 | #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) |
414 | #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) | |
415 | ||
416 | #define DWC3_DCFG_SPEED_MASK (7 << 0) | |
1f38f88a | 417 | #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ |
72246da4 FB |
418 | #define DWC3_DCFG_SUPERSPEED (4 << 0) |
419 | #define DWC3_DCFG_HIGHSPEED (0 << 0) | |
ff3f0789 | 420 | #define DWC3_DCFG_FULLSPEED BIT(0) |
72246da4 | 421 | |
676e3497 | 422 | #define DWC3_DCFG_NUMP_SHIFT 17 |
97398612 | 423 | #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f) |
676e3497 | 424 | #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT) |
ff3f0789 | 425 | #define DWC3_DCFG_LPM_CAP BIT(22) |
e66bbfb0 | 426 | #define DWC3_DCFG_IGNSTRMPP BIT(23) |
2c61a8ef | 427 | |
72246da4 | 428 | /* Device Control Register */ |
ff3f0789 RQ |
429 | #define DWC3_DCTL_RUN_STOP BIT(31) |
430 | #define DWC3_DCTL_CSFTRST BIT(30) | |
431 | #define DWC3_DCTL_LSFTRST BIT(29) | |
72246da4 FB |
432 | |
433 | #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) | |
7e39b817 | 434 | #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) |
72246da4 | 435 | |
ff3f0789 | 436 | #define DWC3_DCTL_APPL1RES BIT(23) |
72246da4 | 437 | |
2c61a8ef PZ |
438 | /* These apply for core versions 1.87a and earlier */ |
439 | #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) | |
440 | #define DWC3_DCTL_TRGTULST(n) ((n) << 17) | |
441 | #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) | |
442 | #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) | |
443 | #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) | |
444 | #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) | |
445 | #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) | |
446 | ||
447 | /* These apply for core versions 1.94a and later */ | |
2e487d28 | 448 | #define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20) |
8db7ed15 | 449 | |
ff3f0789 RQ |
450 | #define DWC3_DCTL_KEEP_CONNECT BIT(19) |
451 | #define DWC3_DCTL_L1_HIBER_EN BIT(18) | |
452 | #define DWC3_DCTL_CRS BIT(17) | |
453 | #define DWC3_DCTL_CSS BIT(16) | |
80caf7d2 | 454 | |
ff3f0789 RQ |
455 | #define DWC3_DCTL_INITU2ENA BIT(12) |
456 | #define DWC3_DCTL_ACCEPTU2ENA BIT(11) | |
457 | #define DWC3_DCTL_INITU1ENA BIT(10) | |
458 | #define DWC3_DCTL_ACCEPTU1ENA BIT(9) | |
80caf7d2 | 459 | #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) |
72246da4 FB |
460 | |
461 | #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) | |
462 | #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) | |
463 | ||
464 | #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) | |
465 | #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) | |
466 | #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) | |
467 | #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) | |
468 | #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) | |
469 | #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) | |
470 | #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) | |
471 | ||
472 | /* Device Event Enable Register */ | |
ff3f0789 RQ |
473 | #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12) |
474 | #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11) | |
475 | #define DWC3_DEVTEN_CMDCMPLTEN BIT(10) | |
476 | #define DWC3_DEVTEN_ERRTICERREN BIT(9) | |
477 | #define DWC3_DEVTEN_SOFEN BIT(7) | |
6f26ebb7 | 478 | #define DWC3_DEVTEN_U3L2L1SUSPEN BIT(6) |
ff3f0789 RQ |
479 | #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5) |
480 | #define DWC3_DEVTEN_WKUPEVTEN BIT(4) | |
481 | #define DWC3_DEVTEN_ULSTCNGEN BIT(3) | |
482 | #define DWC3_DEVTEN_CONNECTDONEEN BIT(2) | |
483 | #define DWC3_DEVTEN_USBRSTEN BIT(1) | |
484 | #define DWC3_DEVTEN_DISCONNEVTEN BIT(0) | |
72246da4 | 485 | |
f551037c TN |
486 | #define DWC3_DSTS_CONNLANES(n) (((n) >> 30) & 0x3) /* DWC_usb32 only */ |
487 | ||
72246da4 | 488 | /* Device Status Register */ |
ff3f0789 | 489 | #define DWC3_DSTS_DCNRD BIT(29) |
2c61a8ef PZ |
490 | |
491 | /* This applies for core versions 1.87a and earlier */ | |
ff3f0789 | 492 | #define DWC3_DSTS_PWRUPREQ BIT(24) |
2c61a8ef PZ |
493 | |
494 | /* These apply for core versions 1.94a and later */ | |
ff3f0789 RQ |
495 | #define DWC3_DSTS_RSS BIT(25) |
496 | #define DWC3_DSTS_SSS BIT(24) | |
2c61a8ef | 497 | |
ff3f0789 RQ |
498 | #define DWC3_DSTS_COREIDLE BIT(23) |
499 | #define DWC3_DSTS_DEVCTRLHLT BIT(22) | |
72246da4 FB |
500 | |
501 | #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) | |
502 | #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) | |
503 | ||
ff3f0789 | 504 | #define DWC3_DSTS_RXFIFOEMPTY BIT(17) |
72246da4 | 505 | |
d05b8182 | 506 | #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) |
72246da4 FB |
507 | #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) |
508 | ||
509 | #define DWC3_DSTS_CONNECTSPD (7 << 0) | |
510 | ||
1f38f88a | 511 | #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ |
72246da4 FB |
512 | #define DWC3_DSTS_SUPERSPEED (4 << 0) |
513 | #define DWC3_DSTS_HIGHSPEED (0 << 0) | |
ff3f0789 | 514 | #define DWC3_DSTS_FULLSPEED BIT(0) |
72246da4 FB |
515 | |
516 | /* Device Generic Command Register */ | |
517 | #define DWC3_DGCMD_SET_LMP 0x01 | |
518 | #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 | |
519 | #define DWC3_DGCMD_XMIT_FUNCTION 0x03 | |
2c61a8ef PZ |
520 | |
521 | /* These apply for core versions 1.94a and later */ | |
522 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 | |
523 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 | |
524 | ||
72246da4 FB |
525 | #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 |
526 | #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a | |
527 | #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c | |
140ca4cf | 528 | #define DWC3_DGCMD_SET_ENDPOINT_PRIME 0x0d |
72246da4 | 529 | #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 |
92c08a84 | 530 | #define DWC3_DGCMD_DEV_NOTIFICATION 0x07 |
72246da4 | 531 | |
459e210c | 532 | #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) |
ff3f0789 RQ |
533 | #define DWC3_DGCMD_CMDACT BIT(10) |
534 | #define DWC3_DGCMD_CMDIOC BIT(8) | |
2c61a8ef PZ |
535 | |
536 | /* Device Generic Command Parameter Register */ | |
ff3f0789 | 537 | #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0) |
2c61a8ef PZ |
538 | #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) |
539 | #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) | |
ff3f0789 | 540 | #define DWC3_DGCMDPAR_TX_FIFO BIT(5) |
2c61a8ef | 541 | #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) |
ff3f0789 | 542 | #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0) |
92c08a84 ERS |
543 | #define DWC3_DGCMDPAR_DN_FUNC_WAKE BIT(0) |
544 | #define DWC3_DGCMDPAR_INTF_SEL(n) ((n) << 4) | |
b09bb642 | 545 | |
72246da4 FB |
546 | /* Device Endpoint Command Register */ |
547 | #define DWC3_DEPCMD_PARAM_SHIFT 16 | |
1d046793 | 548 | #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) |
835fadb4 | 549 | #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) |
459e210c | 550 | #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) |
ff3f0789 RQ |
551 | #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11) |
552 | #define DWC3_DEPCMD_CLEARPENDIN BIT(11) | |
553 | #define DWC3_DEPCMD_CMDACT BIT(10) | |
554 | #define DWC3_DEPCMD_CMDIOC BIT(8) | |
72246da4 FB |
555 | |
556 | #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) | |
557 | #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) | |
558 | #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) | |
559 | #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) | |
560 | #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) | |
561 | #define DWC3_DEPCMD_SETSTALL (0x04 << 0) | |
2c61a8ef | 562 | /* This applies for core versions 1.90a and earlier */ |
72246da4 | 563 | #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) |
2c61a8ef PZ |
564 | /* This applies for core versions 1.94a and later */ |
565 | #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) | |
72246da4 FB |
566 | #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) |
567 | #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) | |
568 | ||
5999914f FB |
569 | #define DWC3_DEPCMD_CMD(x) ((x) & 0xf) |
570 | ||
72246da4 | 571 | /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ |
ff3f0789 | 572 | #define DWC3_DALEPENA_EP(n) BIT(n) |
72246da4 | 573 | |
666f3de7 TN |
574 | /* DWC_usb32 DCFG1 config */ |
575 | #define DWC3_DCFG1_DIS_MST_ENH BIT(1) | |
576 | ||
72246da4 FB |
577 | #define DWC3_DEPCMD_TYPE_CONTROL 0 |
578 | #define DWC3_DEPCMD_TYPE_ISOC 1 | |
579 | #define DWC3_DEPCMD_TYPE_BULK 2 | |
580 | #define DWC3_DEPCMD_TYPE_INTR 3 | |
581 | ||
cf40b86b JY |
582 | #define DWC3_DEV_IMOD_COUNT_SHIFT 16 |
583 | #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16) | |
584 | #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0 | |
585 | #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0) | |
586 | ||
4cff75c7 RQ |
587 | /* OTG Configuration Register */ |
588 | #define DWC3_OCFG_DISPWRCUTTOFF BIT(5) | |
589 | #define DWC3_OCFG_HIBDISMASK BIT(4) | |
590 | #define DWC3_OCFG_SFTRSTMASK BIT(3) | |
591 | #define DWC3_OCFG_OTGVERSION BIT(2) | |
592 | #define DWC3_OCFG_HNPCAP BIT(1) | |
593 | #define DWC3_OCFG_SRPCAP BIT(0) | |
594 | ||
595 | /* OTG CTL Register */ | |
596 | #define DWC3_OCTL_OTG3GOERR BIT(7) | |
597 | #define DWC3_OCTL_PERIMODE BIT(6) | |
598 | #define DWC3_OCTL_PRTPWRCTL BIT(5) | |
599 | #define DWC3_OCTL_HNPREQ BIT(4) | |
600 | #define DWC3_OCTL_SESREQ BIT(3) | |
601 | #define DWC3_OCTL_TERMSELIDPULSE BIT(2) | |
602 | #define DWC3_OCTL_DEVSETHNPEN BIT(1) | |
603 | #define DWC3_OCTL_HSTSETHNPEN BIT(0) | |
604 | ||
605 | /* OTG Event Register */ | |
606 | #define DWC3_OEVT_DEVICEMODE BIT(31) | |
607 | #define DWC3_OEVT_XHCIRUNSTPSET BIT(27) | |
608 | #define DWC3_OEVT_DEVRUNSTPSET BIT(26) | |
609 | #define DWC3_OEVT_HIBENTRY BIT(25) | |
610 | #define DWC3_OEVT_CONIDSTSCHNG BIT(24) | |
611 | #define DWC3_OEVT_HRRCONFNOTIF BIT(23) | |
612 | #define DWC3_OEVT_HRRINITNOTIF BIT(22) | |
613 | #define DWC3_OEVT_ADEVIDLE BIT(21) | |
614 | #define DWC3_OEVT_ADEVBHOSTEND BIT(20) | |
615 | #define DWC3_OEVT_ADEVHOST BIT(19) | |
616 | #define DWC3_OEVT_ADEVHNPCHNG BIT(18) | |
617 | #define DWC3_OEVT_ADEVSRPDET BIT(17) | |
618 | #define DWC3_OEVT_ADEVSESSENDDET BIT(16) | |
619 | #define DWC3_OEVT_BDEVBHOSTEND BIT(11) | |
620 | #define DWC3_OEVT_BDEVHNPCHNG BIT(10) | |
621 | #define DWC3_OEVT_BDEVSESSVLDDET BIT(9) | |
622 | #define DWC3_OEVT_BDEVVBUSCHNG BIT(8) | |
623 | #define DWC3_OEVT_BSESSVLD BIT(3) | |
624 | #define DWC3_OEVT_HSTNEGSTS BIT(2) | |
625 | #define DWC3_OEVT_SESREQSTS BIT(1) | |
626 | #define DWC3_OEVT_ERROR BIT(0) | |
627 | ||
628 | /* OTG Event Enable Register */ | |
629 | #define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27) | |
630 | #define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26) | |
631 | #define DWC3_OEVTEN_HIBENTRYEN BIT(25) | |
632 | #define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24) | |
633 | #define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23) | |
634 | #define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22) | |
635 | #define DWC3_OEVTEN_ADEVIDLEEN BIT(21) | |
636 | #define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20) | |
637 | #define DWC3_OEVTEN_ADEVHOSTEN BIT(19) | |
638 | #define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18) | |
639 | #define DWC3_OEVTEN_ADEVSRPDETEN BIT(17) | |
640 | #define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16) | |
641 | #define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11) | |
642 | #define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10) | |
643 | #define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9) | |
644 | #define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8) | |
645 | ||
646 | /* OTG Status Register */ | |
647 | #define DWC3_OSTS_DEVRUNSTP BIT(13) | |
648 | #define DWC3_OSTS_XHCIRUNSTP BIT(12) | |
649 | #define DWC3_OSTS_PERIPHERALSTATE BIT(4) | |
650 | #define DWC3_OSTS_XHCIPRTPOWER BIT(3) | |
651 | #define DWC3_OSTS_BSESVLD BIT(2) | |
652 | #define DWC3_OSTS_VBUSVLD BIT(1) | |
653 | #define DWC3_OSTS_CONIDSTS BIT(0) | |
654 | ||
72246da4 FB |
655 | /* Structures */ |
656 | ||
f6bafc6a | 657 | struct dwc3_trb; |
72246da4 FB |
658 | |
659 | /** | |
660 | * struct dwc3_event_buffer - Software event buffer representation | |
72246da4 | 661 | * @buf: _THE_ buffer |
d9fa4c63 | 662 | * @cache: The buffer cache used in the threaded interrupt |
72246da4 | 663 | * @length: size of this buffer |
abed4118 | 664 | * @lpos: event offset |
60d04bbe | 665 | * @count: cache of last read event count register |
abed4118 | 666 | * @flags: flags related to this event buffer |
72246da4 FB |
667 | * @dma: dma_addr_t |
668 | * @dwc: pointer to DWC controller | |
669 | */ | |
670 | struct dwc3_event_buffer { | |
671 | void *buf; | |
d9fa4c63 | 672 | void *cache; |
87b923a2 | 673 | unsigned int length; |
72246da4 | 674 | unsigned int lpos; |
60d04bbe | 675 | unsigned int count; |
abed4118 FB |
676 | unsigned int flags; |
677 | ||
678 | #define DWC3_EVENT_PENDING BIT(0) | |
72246da4 FB |
679 | |
680 | dma_addr_t dma; | |
681 | ||
682 | struct dwc3 *dwc; | |
683 | }; | |
684 | ||
ff3f0789 RQ |
685 | #define DWC3_EP_FLAG_STALLED BIT(0) |
686 | #define DWC3_EP_FLAG_WEDGED BIT(1) | |
72246da4 FB |
687 | |
688 | #define DWC3_EP_DIRECTION_TX true | |
689 | #define DWC3_EP_DIRECTION_RX false | |
690 | ||
8495036e | 691 | #define DWC3_TRB_NUM 256 |
72246da4 FB |
692 | |
693 | /** | |
694 | * struct dwc3_ep - device side endpoint representation | |
695 | * @endpoint: usb endpoint | |
d5443bbf | 696 | * @cancelled_list: list of cancelled requests for this endpoint |
aa3342c8 FB |
697 | * @pending_list: list of pending requests for this endpoint |
698 | * @started_list: list of started requests on this endpoint | |
2eb88016 | 699 | * @regs: pointer to first endpoint register |
72246da4 FB |
700 | * @trb_pool: array of transaction buffers |
701 | * @trb_pool_dma: dma address of @trb_pool | |
53fd8818 FB |
702 | * @trb_enqueue: enqueue 'pointer' into TRB array |
703 | * @trb_dequeue: dequeue 'pointer' into TRB array | |
72246da4 | 704 | * @dwc: pointer to DWC controller |
4cfcf876 | 705 | * @saved_state: ep state saved during hibernation |
72246da4 | 706 | * @flags: endpoint flags (wedged, stalled, ...) |
72246da4 FB |
707 | * @number: endpoint number (1 - 15) |
708 | * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK | |
b4996a86 | 709 | * @resource_index: Resource transfer index |
502a37b9 | 710 | * @frame_number: set to the frame number we want this transfer to start (ISOC) |
c75f52fb | 711 | * @interval: the interval on which the ISOC transfer is started |
72246da4 FB |
712 | * @name: a human readable name e.g. ep1out-bulk |
713 | * @direction: true for TX, false for RX | |
879631aa | 714 | * @stream_capable: true when streams are enabled |
d92021f6 TN |
715 | * @combo_num: the test combination BIT[15:14] of the frame number to test |
716 | * isochronous START TRANSFER command failure workaround | |
717 | * @start_cmd_status: the status of testing START TRANSFER command with | |
718 | * combo_num = 'b00 | |
72246da4 FB |
719 | */ |
720 | struct dwc3_ep { | |
721 | struct usb_ep endpoint; | |
d5443bbf | 722 | struct list_head cancelled_list; |
aa3342c8 FB |
723 | struct list_head pending_list; |
724 | struct list_head started_list; | |
72246da4 | 725 | |
2eb88016 FB |
726 | void __iomem *regs; |
727 | ||
f6bafc6a | 728 | struct dwc3_trb *trb_pool; |
72246da4 | 729 | dma_addr_t trb_pool_dma; |
72246da4 FB |
730 | struct dwc3 *dwc; |
731 | ||
4cfcf876 | 732 | u32 saved_state; |
87b923a2 | 733 | unsigned int flags; |
d1a46837 JP |
734 | #define DWC3_EP_ENABLED BIT(0) |
735 | #define DWC3_EP_STALL BIT(1) | |
736 | #define DWC3_EP_WEDGE BIT(2) | |
737 | #define DWC3_EP_TRANSFER_STARTED BIT(3) | |
738 | #define DWC3_EP_END_TRANSFER_PENDING BIT(4) | |
739 | #define DWC3_EP_PENDING_REQUEST BIT(5) | |
740 | #define DWC3_EP_DELAY_START BIT(6) | |
e0d19563 | 741 | #define DWC3_EP_WAIT_TRANSFER_COMPLETE BIT(7) |
140ca4cf TN |
742 | #define DWC3_EP_IGNORE_NEXT_NOSTREAM BIT(8) |
743 | #define DWC3_EP_FORCE_RESTART_STREAM BIT(9) | |
744 | #define DWC3_EP_FIRST_STREAM_PRIMED BIT(10) | |
d97c78a1 | 745 | #define DWC3_EP_PENDING_CLEAR_STALL BIT(11) |
876a75cb | 746 | #define DWC3_EP_TXFIFO_RESIZED BIT(12) |
e4cf6580 | 747 | #define DWC3_EP_DELAY_STOP BIT(13) |
72246da4 | 748 | |
984f66a6 | 749 | /* This last one is specific to EP0 */ |
d1a46837 | 750 | #define DWC3_EP0_DIR_IN BIT(31) |
984f66a6 | 751 | |
c28f8259 FB |
752 | /* |
753 | * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will | |
754 | * use a u8 type here. If anybody decides to increase number of TRBs to | |
755 | * anything larger than 256 - I can't see why people would want to do | |
756 | * this though - then this type needs to be changed. | |
757 | * | |
758 | * By using u8 types we ensure that our % operator when incrementing | |
759 | * enqueue and dequeue get optimized away by the compiler. | |
760 | */ | |
761 | u8 trb_enqueue; | |
762 | u8 trb_dequeue; | |
763 | ||
72246da4 FB |
764 | u8 number; |
765 | u8 type; | |
b4996a86 | 766 | u8 resource_index; |
502a37b9 | 767 | u32 frame_number; |
72246da4 FB |
768 | u32 interval; |
769 | ||
770 | char name[20]; | |
771 | ||
772 | unsigned direction:1; | |
879631aa | 773 | unsigned stream_capable:1; |
d92021f6 TN |
774 | |
775 | /* For isochronous START TRANSFER workaround only */ | |
776 | u8 combo_num; | |
777 | int start_cmd_status; | |
72246da4 FB |
778 | }; |
779 | ||
780 | enum dwc3_phy { | |
781 | DWC3_PHY_UNKNOWN = 0, | |
782 | DWC3_PHY_USB3, | |
783 | DWC3_PHY_USB2, | |
784 | }; | |
785 | ||
b53c772d FB |
786 | enum dwc3_ep0_next { |
787 | DWC3_EP0_UNKNOWN = 0, | |
788 | DWC3_EP0_COMPLETE, | |
b53c772d FB |
789 | DWC3_EP0_NRDY_DATA, |
790 | DWC3_EP0_NRDY_STATUS, | |
791 | }; | |
792 | ||
72246da4 FB |
793 | enum dwc3_ep0_state { |
794 | EP0_UNCONNECTED = 0, | |
c7fcdeb2 FB |
795 | EP0_SETUP_PHASE, |
796 | EP0_DATA_PHASE, | |
797 | EP0_STATUS_PHASE, | |
72246da4 FB |
798 | }; |
799 | ||
800 | enum dwc3_link_state { | |
801 | /* In SuperSpeed */ | |
802 | DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ | |
803 | DWC3_LINK_STATE_U1 = 0x01, | |
804 | DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ | |
805 | DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ | |
806 | DWC3_LINK_STATE_SS_DIS = 0x04, | |
807 | DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ | |
808 | DWC3_LINK_STATE_SS_INACT = 0x06, | |
809 | DWC3_LINK_STATE_POLL = 0x07, | |
810 | DWC3_LINK_STATE_RECOV = 0x08, | |
811 | DWC3_LINK_STATE_HRESET = 0x09, | |
812 | DWC3_LINK_STATE_CMPLY = 0x0a, | |
813 | DWC3_LINK_STATE_LPBK = 0x0b, | |
2c61a8ef PZ |
814 | DWC3_LINK_STATE_RESET = 0x0e, |
815 | DWC3_LINK_STATE_RESUME = 0x0f, | |
72246da4 FB |
816 | DWC3_LINK_STATE_MASK = 0x0f, |
817 | }; | |
818 | ||
f6bafc6a FB |
819 | /* TRB Length, PCM and Status */ |
820 | #define DWC3_TRB_SIZE_MASK (0x00ffffff) | |
821 | #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) | |
822 | #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) | |
389f2828 | 823 | #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) |
f6bafc6a FB |
824 | |
825 | #define DWC3_TRBSTS_OK 0 | |
826 | #define DWC3_TRBSTS_MISSED_ISOC 1 | |
827 | #define DWC3_TRBSTS_SETUP_PENDING 2 | |
2c61a8ef | 828 | #define DWC3_TRB_STS_XFER_IN_PROG 4 |
f6bafc6a FB |
829 | |
830 | /* TRB Control */ | |
ff3f0789 RQ |
831 | #define DWC3_TRB_CTRL_HWO BIT(0) |
832 | #define DWC3_TRB_CTRL_LST BIT(1) | |
833 | #define DWC3_TRB_CTRL_CHN BIT(2) | |
834 | #define DWC3_TRB_CTRL_CSP BIT(3) | |
f6bafc6a | 835 | #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) |
ff3f0789 RQ |
836 | #define DWC3_TRB_CTRL_ISP_IMI BIT(10) |
837 | #define DWC3_TRB_CTRL_IOC BIT(11) | |
f6bafc6a | 838 | #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) |
6abfa0f5 | 839 | #define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14) |
f6bafc6a | 840 | |
b058f3e8 | 841 | #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4)) |
f6bafc6a FB |
842 | #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) |
843 | #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) | |
844 | #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) | |
845 | #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) | |
846 | #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) | |
847 | #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) | |
848 | #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) | |
849 | #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) | |
72246da4 FB |
850 | |
851 | /** | |
f6bafc6a | 852 | * struct dwc3_trb - transfer request block (hw format) |
72246da4 FB |
853 | * @bpl: DW0-3 |
854 | * @bph: DW4-7 | |
855 | * @size: DW8-B | |
bfad65ee | 856 | * @ctrl: DWC-F |
72246da4 | 857 | */ |
f6bafc6a FB |
858 | struct dwc3_trb { |
859 | u32 bpl; | |
860 | u32 bph; | |
861 | u32 size; | |
862 | u32 ctrl; | |
72246da4 FB |
863 | } __packed; |
864 | ||
a3299499 | 865 | /** |
bfad65ee FB |
866 | * struct dwc3_hwparams - copy of HWPARAMS registers |
867 | * @hwparams0: GHWPARAMS0 | |
868 | * @hwparams1: GHWPARAMS1 | |
869 | * @hwparams2: GHWPARAMS2 | |
870 | * @hwparams3: GHWPARAMS3 | |
871 | * @hwparams4: GHWPARAMS4 | |
872 | * @hwparams5: GHWPARAMS5 | |
873 | * @hwparams6: GHWPARAMS6 | |
874 | * @hwparams7: GHWPARAMS7 | |
875 | * @hwparams8: GHWPARAMS8 | |
9cbc7eb1 | 876 | * @hwparams9: GHWPARAMS9 |
a3299499 FB |
877 | */ |
878 | struct dwc3_hwparams { | |
879 | u32 hwparams0; | |
880 | u32 hwparams1; | |
881 | u32 hwparams2; | |
882 | u32 hwparams3; | |
883 | u32 hwparams4; | |
884 | u32 hwparams5; | |
885 | u32 hwparams6; | |
886 | u32 hwparams7; | |
887 | u32 hwparams8; | |
16710380 | 888 | u32 hwparams9; |
a3299499 FB |
889 | }; |
890 | ||
0949e99b FB |
891 | /* HWPARAMS0 */ |
892 | #define DWC3_MODE(n) ((n) & 0x7) | |
893 | ||
0949e99b | 894 | /* HWPARAMS1 */ |
457e84b6 FB |
895 | #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) |
896 | ||
789451f6 FB |
897 | /* HWPARAMS3 */ |
898 | #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) | |
899 | #define DWC3_NUM_EPS_MASK (0x3f << 12) | |
900 | #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ | |
901 | (DWC3_NUM_EPS_MASK)) >> 12) | |
902 | #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ | |
903 | (DWC3_NUM_IN_EPS_MASK)) >> 18) | |
904 | ||
457e84b6 FB |
905 | /* HWPARAMS7 */ |
906 | #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) | |
9f622b2a | 907 | |
666f3de7 TN |
908 | /* HWPARAMS9 */ |
909 | #define DWC3_MST_CAPABLE(p) (!!((p)->hwparams9 & \ | |
910 | DWC3_GHWPARAMS9_DEV_MST)) | |
911 | ||
5ef68c56 FB |
912 | /** |
913 | * struct dwc3_request - representation of a transfer request | |
914 | * @request: struct usb_request to be transferred | |
915 | * @list: a list_head used for request queueing | |
916 | * @dep: struct dwc3_ep owning this request | |
0b3e4af3 | 917 | * @sg: pointer to first incomplete sg |
a31e63b6 | 918 | * @start_sg: pointer to the sg which should be queued next |
0b3e4af3 | 919 | * @num_pending_sgs: counter to pending sgs |
c96e6725 | 920 | * @num_queued_sgs: counter to the number of sgs which already got queued |
e62c5bc5 | 921 | * @remaining: amount of data remaining |
a3af5e3a | 922 | * @status: internal dwc3 request status tracking |
5ef68c56 FB |
923 | * @epnum: endpoint number to which this request refers |
924 | * @trb: pointer to struct dwc3_trb | |
925 | * @trb_dma: DMA address of @trb | |
09fe1f8d | 926 | * @num_trbs: number of TRBs used by this request |
1a22ec64 FB |
927 | * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP |
928 | * or unaligned OUT) | |
5ef68c56 FB |
929 | * @direction: IN or OUT direction flag |
930 | * @mapped: true when request has been dma-mapped | |
5ef68c56 | 931 | */ |
e0ce0b0a SAS |
932 | struct dwc3_request { |
933 | struct usb_request request; | |
934 | struct list_head list; | |
935 | struct dwc3_ep *dep; | |
0b3e4af3 | 936 | struct scatterlist *sg; |
a31e63b6 | 937 | struct scatterlist *start_sg; |
e0ce0b0a | 938 | |
87b923a2 | 939 | unsigned int num_pending_sgs; |
c96e6725 | 940 | unsigned int num_queued_sgs; |
87b923a2 | 941 | unsigned int remaining; |
a3af5e3a FB |
942 | |
943 | unsigned int status; | |
04dd6e76 RC |
944 | #define DWC3_REQUEST_STATUS_QUEUED 0 |
945 | #define DWC3_REQUEST_STATUS_STARTED 1 | |
946 | #define DWC3_REQUEST_STATUS_DISCONNECTED 2 | |
947 | #define DWC3_REQUEST_STATUS_DEQUEUED 3 | |
948 | #define DWC3_REQUEST_STATUS_STALLED 4 | |
949 | #define DWC3_REQUEST_STATUS_COMPLETED 5 | |
950 | #define DWC3_REQUEST_STATUS_UNKNOWN -1 | |
a3af5e3a | 951 | |
e0ce0b0a | 952 | u8 epnum; |
f6bafc6a | 953 | struct dwc3_trb *trb; |
e0ce0b0a SAS |
954 | dma_addr_t trb_dma; |
955 | ||
87b923a2 | 956 | unsigned int num_trbs; |
09fe1f8d | 957 | |
87b923a2 FB |
958 | unsigned int needs_extra_trb:1; |
959 | unsigned int direction:1; | |
960 | unsigned int mapped:1; | |
e0ce0b0a SAS |
961 | }; |
962 | ||
2c61a8ef PZ |
963 | /* |
964 | * struct dwc3_scratchpad_array - hibernation scratchpad array | |
965 | * (format defined by hw) | |
966 | */ | |
967 | struct dwc3_scratchpad_array { | |
968 | __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; | |
969 | }; | |
970 | ||
72246da4 FB |
971 | /** |
972 | * struct dwc3 - representation of our controller | |
bfad65ee | 973 | * @drd_work: workqueue used for role swapping |
91db07dc | 974 | * @ep0_trb: trb which is used for the ctrl_req |
bfad65ee | 975 | * @bounce: address of bounce buffer |
91db07dc | 976 | * @setup_buf: used while precessing STD USB requests |
bfad65ee FB |
977 | * @ep0_trb_addr: dma address of @ep0_trb |
978 | * @bounce_addr: dma address of @bounce | |
91db07dc | 979 | * @ep0_usb_req: dummy req used while handling STD USB requests |
bb014736 | 980 | * @ep0_in_setup: one control transfer is completed and enter setup phase |
72246da4 | 981 | * @lock: for synchronizing |
f88359e1 | 982 | * @mutex: for mode switching |
72246da4 | 983 | * @dev: pointer to our struct device |
bfad65ee | 984 | * @sysdev: pointer to the DMA-capable device |
d07e8819 | 985 | * @xhci: pointer to our xHCI child |
bfad65ee FB |
986 | * @xhci_resources: struct resources for our @xhci child |
987 | * @ev_buf: struct dwc3_event_buffer pointer | |
988 | * @eps: endpoint array | |
72246da4 FB |
989 | * @gadget: device side representation of the peripheral controller |
990 | * @gadget_driver: pointer to the gadget driver | |
33fb697e SA |
991 | * @bus_clk: clock for accessing the registers |
992 | * @ref_clk: reference clock | |
993 | * @susp_clk: clock used when the SS phy is in low power (S3) state | |
fe8abf33 | 994 | * @reset: reset control |
72246da4 FB |
995 | * @regs: base address for our registers |
996 | * @regs_size: address space size | |
bcdb3272 | 997 | * @fladj: frame length adjustment |
7bee3188 | 998 | * @ref_clk_per: reference clock period configuration |
3f308d17 | 999 | * @irq_gadget: peripheral controller's IRQ number |
f09cc79b RQ |
1000 | * @otg_irq: IRQ number for OTG IRQs |
1001 | * @current_otg_role: current role of operation while using the OTG block | |
1002 | * @desired_otg_role: desired role of operation while using the OTG block | |
1003 | * @otg_restart_host: flag that OTG controller needs to restart host | |
fae2b904 | 1004 | * @u1u2: only used on revisions <1.83a for workaround |
6c167fc9 | 1005 | * @maximum_speed: maximum speed requested (mainly for testing purposes) |
67848146 | 1006 | * @max_ssp_rate: SuperSpeed Plus maximum signaling rate and lane count |
5dc71f1e | 1007 | * @gadget_max_speed: maximum gadget speed requested |
072cab8a TN |
1008 | * @gadget_ssp_rate: Gadget driver's maximum supported SuperSpeed Plus signaling |
1009 | * rate and lane count. | |
9af21dd6 TN |
1010 | * @ip: controller's ID |
1011 | * @revision: controller's version of an IP | |
475d8e01 | 1012 | * @version_type: VERSIONTYPE register contents, a sub release of a revision |
a45c82b8 | 1013 | * @dr_mode: requested mode of operation |
6b3261a2 | 1014 | * @current_dr_role: current role of operation when in dual-role mode |
41ce1456 | 1015 | * @desired_dr_role: desired role of operation when in dual-role mode |
9840354f RQ |
1016 | * @edev: extcon handle |
1017 | * @edev_nb: extcon notifier | |
32f2ed86 WW |
1018 | * @hsphy_mode: UTMI phy mode, one of following: |
1019 | * - USBPHY_INTERFACE_MODE_UTMI | |
1020 | * - USBPHY_INTERFACE_MODE_UTMIW | |
8a0a1379 | 1021 | * @role_sw: usb_role_switch handle |
98ed256a JS |
1022 | * @role_switch_default_mode: default operation mode of controller while |
1023 | * usb role is USB_ROLE_NONE. | |
0f3edf99 | 1024 | * @usb_psy: pointer to power supply interface. |
51e1e7bc FB |
1025 | * @usb2_phy: pointer to USB2 PHY |
1026 | * @usb3_phy: pointer to USB3 PHY | |
57303488 KVA |
1027 | * @usb2_generic_phy: pointer to USB2 PHY |
1028 | * @usb3_generic_phy: pointer to USB3 PHY | |
98112041 | 1029 | * @phys_ready: flag to indicate that PHYs are ready |
88bc9d19 | 1030 | * @ulpi: pointer to ulpi interface |
98112041 | 1031 | * @ulpi_ready: flag to indicate that ULPI is initialized |
865e09e7 FB |
1032 | * @u2sel: parameter from Set SEL request. |
1033 | * @u2pel: parameter from Set SEL request. | |
1034 | * @u1sel: parameter from Set SEL request. | |
1035 | * @u1pel: parameter from Set SEL request. | |
47d3946e | 1036 | * @num_eps: number of endpoints |
b53c772d | 1037 | * @ep0_next_event: hold the next expected event |
72246da4 FB |
1038 | * @ep0state: state of endpoint zero |
1039 | * @link_state: link state | |
1040 | * @speed: device speed (super, high, full, low) | |
a3299499 | 1041 | * @hwparams: copy of hwparams registers |
f2b685d5 | 1042 | * @regset: debugfs pointer to regdump file |
62ba09d6 | 1043 | * @dbg_lsp_select: current debug lsp mux register selection |
f2b685d5 FB |
1044 | * @test_mode: true when we're entering a USB test mode |
1045 | * @test_mode_nr: test feature selector | |
80caf7d2 | 1046 | * @lpm_nyet_threshold: LPM NYET response threshold |
460d098c | 1047 | * @hird_threshold: HIRD threshold |
938a5ad1 TN |
1048 | * @rx_thr_num_pkt_prd: periodic ESS receive packet count |
1049 | * @rx_max_burst_prd: max periodic ESS receive burst size | |
1050 | * @tx_thr_num_pkt_prd: periodic ESS transmit packet count | |
1051 | * @tx_max_burst_prd: max periodic ESS transmit burst size | |
9f607a30 | 1052 | * @tx_fifo_resize_max_num: max number of fifos allocated during txfifo resize |
2840d6df | 1053 | * @clear_stall_protocol: endpoint number that requires a delayed status phase |
3e10a2ce | 1054 | * @hsphy_interface: "utmi" or "ulpi" |
fc8bb91b | 1055 | * @connected: true when we're connected to a host, false otherwise |
8217f07a | 1056 | * @softconnect: true when gadget connect is called, false when disconnect runs |
f2b685d5 FB |
1057 | * @delayed_status: true when gadget driver asks for delayed status |
1058 | * @ep0_bounced: true when we used bounce buffer | |
1059 | * @ep0_expect_in: true when we expect a DATA IN transfer | |
d64ff406 | 1060 | * @sysdev_is_parent: true when dwc3 device has a parent driver |
80caf7d2 HR |
1061 | * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that |
1062 | * there's now way for software to detect this in runtime. | |
460d098c | 1063 | * @is_utmi_l1_suspend: the core asserts output signal |
87b923a2 FB |
1064 | * 0 - utmi_sleep_n |
1065 | * 1 - utmi_l1_suspend_n | |
946bd579 | 1066 | * @is_fpga: true when we are using the FPGA board |
fc8bb91b | 1067 | * @pending_events: true when we have pending IRQs to be handled |
9f607a30 | 1068 | * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints |
f2b685d5 | 1069 | * @pullups_connected: true when Run/Stop bit is set |
f2b685d5 | 1070 | * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround |
f2b685d5 | 1071 | * @three_stage_setup: set if we perform a three phase setup |
d92021f6 TN |
1072 | * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is |
1073 | * not needed for DWC_usb31 version 1.70a-ea06 and below | |
eac68e8f | 1074 | * @usb3_lpm_capable: set if hadrware supports Link Power Management |
475e8be5 TN |
1075 | * @usb2_lpm_disable: set to disable usb2 lpm for host |
1076 | * @usb2_gadget_lpm_disable: set to disable usb2 lpm for gadget | |
3b81221a | 1077 | * @disable_scramble_quirk: set if we enable the disable scramble quirk |
9a5b2f31 | 1078 | * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk |
b5a65c40 | 1079 | * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk |
df31f5b3 | 1080 | * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk |
a2a1d0f5 | 1081 | * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk |
41c06ffd | 1082 | * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk |
fb67afca | 1083 | * @lfps_filter_quirk: set if we enable LFPS filter quirk |
14f4ac53 | 1084 | * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk |
59acfa20 | 1085 | * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy |
0effe0a3 | 1086 | * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy |
ec791d14 JY |
1087 | * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, |
1088 | * disabling the suspend signal to the PHY. | |
729dcffd AKV |
1089 | * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled. |
1090 | * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled. | |
bfad65ee | 1091 | * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3 |
ad44cf40 MCC |
1092 | * @async_callbacks: if set, indicate that async callbacks will be used. |
1093 | * | |
16199f33 WW |
1094 | * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists |
1095 | * in GUSB2PHYCFG, specify that USB2 PHY doesn't | |
1096 | * provide a free-running PHY clock. | |
00fe081d WW |
1097 | * @dis_del_phy_power_chg_quirk: set if we disable delay phy power |
1098 | * change quirk. | |
65db7a0c WW |
1099 | * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate |
1100 | * check during HS transmit. | |
02c18203 | 1101 | * @resume_hs_terminations: Set if we enable quirk for fixing improper crc |
63d7f981 | 1102 | * generation after resume from suspend. |
b84ba26c PM |
1103 | * @ulpi_ext_vbus_drv: Set to confiure the upli chip to drives CPEN pin |
1104 | * VBUS with an external supply. | |
7ba6b09f NA |
1105 | * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed |
1106 | * instances in park mode. | |
d21a797a SC |
1107 | * @parkmode_disable_hs_quirk: set if we need to disable all HishSpeed |
1108 | * instances in park mode. | |
6b6a0c9a HR |
1109 | * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk |
1110 | * @tx_de_emphasis: Tx de-emphasis value | |
87b923a2 FB |
1111 | * 0 - -6dB de-emphasis |
1112 | * 1 - -3.5dB de-emphasis | |
1113 | * 2 - No de-emphasis | |
1114 | * 3 - Reserved | |
42bf02ec | 1115 | * @dis_metastability_quirk: set to disable metastability quirk. |
f580170f | 1116 | * @dis_split_quirk: set to disable split boundary. |
04716168 | 1117 | * @wakeup_configured: set if the device is configured for remote wakeup. |
4e8ef34e | 1118 | * @suspended: set to track suspend event due to U3/L2. |
cf40b86b | 1119 | * @imod_interval: set the interrupt moderation interval in 250ns |
87b923a2 | 1120 | * increments or 0 to disable. |
9f607a30 WC |
1121 | * @max_cfg_eps: current max number of IN eps used across all USB configs. |
1122 | * @last_fifo_depth: last fifo depth used to determine next fifo ram start | |
1123 | * address. | |
1124 | * @num_ep_resized: carries the current number endpoints which have had its tx | |
1125 | * fifo resized. | |
be308d68 | 1126 | * @debug_root: root debugfs directory for this device to put its files in. |
72246da4 FB |
1127 | */ |
1128 | struct dwc3 { | |
41ce1456 | 1129 | struct work_struct drd_work; |
f6bafc6a | 1130 | struct dwc3_trb *ep0_trb; |
905dc04e | 1131 | void *bounce; |
72246da4 | 1132 | u8 *setup_buf; |
72246da4 | 1133 | dma_addr_t ep0_trb_addr; |
905dc04e | 1134 | dma_addr_t bounce_addr; |
e0ce0b0a | 1135 | struct dwc3_request ep0_usb_req; |
bb014736 | 1136 | struct completion ep0_in_setup; |
789451f6 | 1137 | |
72246da4 FB |
1138 | /* device lock */ |
1139 | spinlock_t lock; | |
789451f6 | 1140 | |
f88359e1 YC |
1141 | /* mode switching lock */ |
1142 | struct mutex mutex; | |
1143 | ||
72246da4 | 1144 | struct device *dev; |
d64ff406 | 1145 | struct device *sysdev; |
72246da4 | 1146 | |
d07e8819 | 1147 | struct platform_device *xhci; |
51249dca | 1148 | struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; |
d07e8819 | 1149 | |
696c8b12 | 1150 | struct dwc3_event_buffer *ev_buf; |
72246da4 FB |
1151 | struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; |
1152 | ||
e81a7018 | 1153 | struct usb_gadget *gadget; |
72246da4 FB |
1154 | struct usb_gadget_driver *gadget_driver; |
1155 | ||
33fb697e SA |
1156 | struct clk *bus_clk; |
1157 | struct clk *ref_clk; | |
1158 | struct clk *susp_clk; | |
fe8abf33 MY |
1159 | |
1160 | struct reset_control *reset; | |
1161 | ||
51e1e7bc FB |
1162 | struct usb_phy *usb2_phy; |
1163 | struct usb_phy *usb3_phy; | |
1164 | ||
57303488 KVA |
1165 | struct phy *usb2_generic_phy; |
1166 | struct phy *usb3_generic_phy; | |
1167 | ||
98112041 RQ |
1168 | bool phys_ready; |
1169 | ||
88bc9d19 | 1170 | struct ulpi *ulpi; |
98112041 | 1171 | bool ulpi_ready; |
88bc9d19 | 1172 | |
72246da4 FB |
1173 | void __iomem *regs; |
1174 | size_t regs_size; | |
1175 | ||
a45c82b8 | 1176 | enum usb_dr_mode dr_mode; |
6b3261a2 | 1177 | u32 current_dr_role; |
41ce1456 | 1178 | u32 desired_dr_role; |
9840354f RQ |
1179 | struct extcon_dev *edev; |
1180 | struct notifier_block edev_nb; | |
32f2ed86 | 1181 | enum usb_phy_interface hsphy_mode; |
8a0a1379 | 1182 | struct usb_role_switch *role_sw; |
98ed256a | 1183 | enum usb_dr_mode role_switch_default_mode; |
a45c82b8 | 1184 | |
6f0764b5 RC |
1185 | struct power_supply *usb_psy; |
1186 | ||
bcdb3272 | 1187 | u32 fladj; |
7bee3188 | 1188 | u32 ref_clk_per; |
3f308d17 | 1189 | u32 irq_gadget; |
f09cc79b RQ |
1190 | u32 otg_irq; |
1191 | u32 current_otg_role; | |
1192 | u32 desired_otg_role; | |
1193 | bool otg_restart_host; | |
fae2b904 | 1194 | u32 u1u2; |
6c167fc9 | 1195 | u32 maximum_speed; |
7c9a2598 | 1196 | u32 gadget_max_speed; |
67848146 | 1197 | enum usb_ssp_rate max_ssp_rate; |
072cab8a | 1198 | enum usb_ssp_rate gadget_ssp_rate; |
690fb371 | 1199 | |
9af21dd6 TN |
1200 | u32 ip; |
1201 | ||
1202 | #define DWC3_IP 0x5533 | |
1203 | #define DWC31_IP 0x3331 | |
1204 | #define DWC32_IP 0x3332 | |
1205 | ||
72246da4 FB |
1206 | u32 revision; |
1207 | ||
9af21dd6 | 1208 | #define DWC3_REVISION_ANY 0x0 |
72246da4 FB |
1209 | #define DWC3_REVISION_173A 0x5533173a |
1210 | #define DWC3_REVISION_175A 0x5533175a | |
1211 | #define DWC3_REVISION_180A 0x5533180a | |
1212 | #define DWC3_REVISION_183A 0x5533183a | |
1213 | #define DWC3_REVISION_185A 0x5533185a | |
2c61a8ef | 1214 | #define DWC3_REVISION_187A 0x5533187a |
72246da4 FB |
1215 | #define DWC3_REVISION_188A 0x5533188a |
1216 | #define DWC3_REVISION_190A 0x5533190a | |
2c61a8ef | 1217 | #define DWC3_REVISION_194A 0x5533194a |
1522d703 FB |
1218 | #define DWC3_REVISION_200A 0x5533200a |
1219 | #define DWC3_REVISION_202A 0x5533202a | |
1220 | #define DWC3_REVISION_210A 0x5533210a | |
1221 | #define DWC3_REVISION_220A 0x5533220a | |
7ac6a593 FB |
1222 | #define DWC3_REVISION_230A 0x5533230a |
1223 | #define DWC3_REVISION_240A 0x5533240a | |
1224 | #define DWC3_REVISION_250A 0x5533250a | |
dbf5aaf7 FB |
1225 | #define DWC3_REVISION_260A 0x5533260a |
1226 | #define DWC3_REVISION_270A 0x5533270a | |
1227 | #define DWC3_REVISION_280A 0x5533280a | |
0bb39ca1 | 1228 | #define DWC3_REVISION_290A 0x5533290a |
512e4757 JY |
1229 | #define DWC3_REVISION_300A 0x5533300a |
1230 | #define DWC3_REVISION_310A 0x5533310a | |
89a9cc47 | 1231 | #define DWC3_REVISION_330A 0x5533330a |
72246da4 | 1232 | |
9af21dd6 TN |
1233 | #define DWC31_REVISION_ANY 0x0 |
1234 | #define DWC31_REVISION_110A 0x3131302a | |
1235 | #define DWC31_REVISION_120A 0x3132302a | |
1236 | #define DWC31_REVISION_160A 0x3136302a | |
1237 | #define DWC31_REVISION_170A 0x3137302a | |
1238 | #define DWC31_REVISION_180A 0x3138302a | |
1239 | #define DWC31_REVISION_190A 0x3139302a | |
690fb371 | 1240 | |
b10e1c25 TN |
1241 | #define DWC32_REVISION_ANY 0x0 |
1242 | #define DWC32_REVISION_100A 0x3130302a | |
1243 | ||
475d8e01 TN |
1244 | u32 version_type; |
1245 | ||
9af21dd6 | 1246 | #define DWC31_VERSIONTYPE_ANY 0x0 |
475d8e01 TN |
1247 | #define DWC31_VERSIONTYPE_EA01 0x65613031 |
1248 | #define DWC31_VERSIONTYPE_EA02 0x65613032 | |
1249 | #define DWC31_VERSIONTYPE_EA03 0x65613033 | |
1250 | #define DWC31_VERSIONTYPE_EA04 0x65613034 | |
1251 | #define DWC31_VERSIONTYPE_EA05 0x65613035 | |
1252 | #define DWC31_VERSIONTYPE_EA06 0x65613036 | |
1253 | ||
b53c772d | 1254 | enum dwc3_ep0_next ep0_next_event; |
72246da4 FB |
1255 | enum dwc3_ep0_state ep0state; |
1256 | enum dwc3_link_state link_state; | |
72246da4 | 1257 | |
865e09e7 FB |
1258 | u16 u2sel; |
1259 | u16 u2pel; | |
1260 | u8 u1sel; | |
1261 | u8 u1pel; | |
1262 | ||
72246da4 | 1263 | u8 speed; |
865e09e7 | 1264 | |
47d3946e | 1265 | u8 num_eps; |
789451f6 | 1266 | |
a3299499 | 1267 | struct dwc3_hwparams hwparams; |
d7668024 | 1268 | struct debugfs_regset32 *regset; |
3b637367 | 1269 | |
62ba09d6 TN |
1270 | u32 dbg_lsp_select; |
1271 | ||
3b637367 GC |
1272 | u8 test_mode; |
1273 | u8 test_mode_nr; | |
80caf7d2 | 1274 | u8 lpm_nyet_threshold; |
460d098c | 1275 | u8 hird_threshold; |
938a5ad1 TN |
1276 | u8 rx_thr_num_pkt_prd; |
1277 | u8 rx_max_burst_prd; | |
1278 | u8 tx_thr_num_pkt_prd; | |
1279 | u8 tx_max_burst_prd; | |
9f607a30 | 1280 | u8 tx_fifo_resize_max_num; |
2840d6df | 1281 | u8 clear_stall_protocol; |
f2b685d5 | 1282 | |
3e10a2ce HK |
1283 | const char *hsphy_interface; |
1284 | ||
fc8bb91b | 1285 | unsigned connected:1; |
8217f07a | 1286 | unsigned softconnect:1; |
f2b685d5 FB |
1287 | unsigned delayed_status:1; |
1288 | unsigned ep0_bounced:1; | |
1289 | unsigned ep0_expect_in:1; | |
d64ff406 | 1290 | unsigned sysdev_is_parent:1; |
80caf7d2 | 1291 | unsigned has_lpm_erratum:1; |
460d098c | 1292 | unsigned is_utmi_l1_suspend:1; |
946bd579 | 1293 | unsigned is_fpga:1; |
fc8bb91b | 1294 | unsigned pending_events:1; |
9f607a30 | 1295 | unsigned do_fifo_resize:1; |
f2b685d5 | 1296 | unsigned pullups_connected:1; |
f2b685d5 | 1297 | unsigned setup_packet_pending:1; |
f2b685d5 | 1298 | unsigned three_stage_setup:1; |
d92021f6 | 1299 | unsigned dis_start_transfer_quirk:1; |
eac68e8f | 1300 | unsigned usb3_lpm_capable:1; |
022a0208 | 1301 | unsigned usb2_lpm_disable:1; |
475e8be5 | 1302 | unsigned usb2_gadget_lpm_disable:1; |
3b81221a HR |
1303 | |
1304 | unsigned disable_scramble_quirk:1; | |
9a5b2f31 | 1305 | unsigned u2exit_lfps_quirk:1; |
b5a65c40 | 1306 | unsigned u2ss_inp3_quirk:1; |
df31f5b3 | 1307 | unsigned req_p1p2p3_quirk:1; |
a2a1d0f5 | 1308 | unsigned del_p1p2p3_quirk:1; |
41c06ffd | 1309 | unsigned del_phy_power_chg_quirk:1; |
fb67afca | 1310 | unsigned lfps_filter_quirk:1; |
14f4ac53 | 1311 | unsigned rx_detect_poll_quirk:1; |
59acfa20 | 1312 | unsigned dis_u3_susphy_quirk:1; |
0effe0a3 | 1313 | unsigned dis_u2_susphy_quirk:1; |
ec791d14 | 1314 | unsigned dis_enblslpm_quirk:1; |
729dcffd AKV |
1315 | unsigned dis_u1_entry_quirk:1; |
1316 | unsigned dis_u2_entry_quirk:1; | |
e58dd357 | 1317 | unsigned dis_rxdet_inp3_quirk:1; |
16199f33 | 1318 | unsigned dis_u2_freeclk_exists_quirk:1; |
00fe081d | 1319 | unsigned dis_del_phy_power_chg_quirk:1; |
65db7a0c | 1320 | unsigned dis_tx_ipgap_linecheck_quirk:1; |
63d7f981 | 1321 | unsigned resume_hs_terminations:1; |
b84ba26c | 1322 | unsigned ulpi_ext_vbus_drv:1; |
7ba6b09f | 1323 | unsigned parkmode_disable_ss_quirk:1; |
d21a797a | 1324 | unsigned parkmode_disable_hs_quirk:1; |
a6fc2f1b | 1325 | unsigned gfladj_refclk_lpm_sel:1; |
6b6a0c9a HR |
1326 | |
1327 | unsigned tx_de_emphasis_quirk:1; | |
1328 | unsigned tx_de_emphasis:2; | |
cf40b86b | 1329 | |
42bf02ec RQ |
1330 | unsigned dis_metastability_quirk:1; |
1331 | ||
f580170f | 1332 | unsigned dis_split_quirk:1; |
40edb522 | 1333 | unsigned async_callbacks:1; |
04716168 | 1334 | unsigned wakeup_configured:1; |
4e8ef34e | 1335 | unsigned suspended:1; |
f580170f | 1336 | |
cf40b86b | 1337 | u16 imod_interval; |
9f607a30 WC |
1338 | |
1339 | int max_cfg_eps; | |
1340 | int last_fifo_depth; | |
1341 | int num_ep_resized; | |
be308d68 | 1342 | struct dentry *debug_root; |
72246da4 FB |
1343 | }; |
1344 | ||
d9612c2f PM |
1345 | #define INCRX_BURST_MODE 0 |
1346 | #define INCRX_UNDEF_LENGTH_BURST_MODE 1 | |
1347 | ||
41ce1456 | 1348 | #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work)) |
72246da4 | 1349 | |
72246da4 FB |
1350 | /* -------------------------------------------------------------------------- */ |
1351 | ||
1352 | struct dwc3_event_type { | |
1353 | u32 is_devspec:1; | |
1974d494 HR |
1354 | u32 type:7; |
1355 | u32 reserved8_31:24; | |
72246da4 FB |
1356 | } __packed; |
1357 | ||
1358 | #define DWC3_DEPEVT_XFERCOMPLETE 0x01 | |
1359 | #define DWC3_DEPEVT_XFERINPROGRESS 0x02 | |
1360 | #define DWC3_DEPEVT_XFERNOTREADY 0x03 | |
1361 | #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 | |
1362 | #define DWC3_DEPEVT_STREAMEVT 0x06 | |
1363 | #define DWC3_DEPEVT_EPCMDCMPLT 0x07 | |
1364 | ||
1365 | /** | |
cbdc0f54 | 1366 | * struct dwc3_event_depevt - Device Endpoint Events |
72246da4 FB |
1367 | * @one_bit: indicates this is an endpoint event (not used) |
1368 | * @endpoint_number: number of the endpoint | |
1369 | * @endpoint_event: The event we have: | |
1370 | * 0x00 - Reserved | |
1371 | * 0x01 - XferComplete | |
1372 | * 0x02 - XferInProgress | |
1373 | * 0x03 - XferNotReady | |
1374 | * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) | |
1375 | * 0x05 - Reserved | |
1376 | * 0x06 - StreamEvt | |
1377 | * 0x07 - EPCmdCmplt | |
1378 | * @reserved11_10: Reserved, don't use. | |
1379 | * @status: Indicates the status of the event. Refer to databook for | |
1380 | * more information. | |
1381 | * @parameters: Parameters of the current event. Refer to databook for | |
1382 | * more information. | |
1383 | */ | |
1384 | struct dwc3_event_depevt { | |
1385 | u32 one_bit:1; | |
1386 | u32 endpoint_number:5; | |
1387 | u32 endpoint_event:4; | |
1388 | u32 reserved11_10:2; | |
1389 | u32 status:4; | |
40aa41fb FB |
1390 | |
1391 | /* Within XferNotReady */ | |
ff3f0789 | 1392 | #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3) |
40aa41fb | 1393 | |
6d8a0196 | 1394 | /* Within XferComplete or XferInProgress */ |
ff3f0789 RQ |
1395 | #define DEPEVT_STATUS_BUSERR BIT(0) |
1396 | #define DEPEVT_STATUS_SHORT BIT(1) | |
1397 | #define DEPEVT_STATUS_IOC BIT(2) | |
6d8a0196 FB |
1398 | #define DEPEVT_STATUS_LST BIT(3) /* XferComplete */ |
1399 | #define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */ | |
dc137f01 | 1400 | |
879631aa FB |
1401 | /* Stream event only */ |
1402 | #define DEPEVT_STREAMEVT_FOUND 1 | |
1403 | #define DEPEVT_STREAMEVT_NOTFOUND 2 | |
1404 | ||
140ca4cf TN |
1405 | /* Stream event parameter */ |
1406 | #define DEPEVT_STREAM_PRIME 0xfffe | |
1407 | #define DEPEVT_STREAM_NOSTREAM 0x0 | |
1408 | ||
dc137f01 | 1409 | /* Control-only Status */ |
dc137f01 FB |
1410 | #define DEPEVT_STATUS_CONTROL_DATA 1 |
1411 | #define DEPEVT_STATUS_CONTROL_STATUS 2 | |
45a2af2f | 1412 | #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3) |
dc137f01 | 1413 | |
7b9cc7a2 KL |
1414 | /* In response to Start Transfer */ |
1415 | #define DEPEVT_TRANSFER_NO_RESOURCE 1 | |
1416 | #define DEPEVT_TRANSFER_BUS_EXPIRY 2 | |
1417 | ||
72246da4 | 1418 | u32 parameters:16; |
76a638f8 BW |
1419 | |
1420 | /* For Command Complete Events */ | |
1421 | #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8) | |
72246da4 FB |
1422 | } __packed; |
1423 | ||
1424 | /** | |
1425 | * struct dwc3_event_devt - Device Events | |
1426 | * @one_bit: indicates this is a non-endpoint event (not used) | |
1427 | * @device_event: indicates it's a device event. Should read as 0x00 | |
1428 | * @type: indicates the type of device event. | |
1429 | * 0 - DisconnEvt | |
1430 | * 1 - USBRst | |
1431 | * 2 - ConnectDone | |
1432 | * 3 - ULStChng | |
1433 | * 4 - WkUpEvt | |
1434 | * 5 - Reserved | |
6f26ebb7 | 1435 | * 6 - Suspend (EOPF on revisions 2.10a and prior) |
72246da4 FB |
1436 | * 7 - SOF |
1437 | * 8 - Reserved | |
1438 | * 9 - ErrticErr | |
1439 | * 10 - CmdCmplt | |
1440 | * 11 - EvntOverflow | |
1441 | * 12 - VndrDevTstRcved | |
1442 | * @reserved15_12: Reserved, not used | |
1443 | * @event_info: Information about this event | |
06f9b6e5 | 1444 | * @reserved31_25: Reserved, not used |
72246da4 FB |
1445 | */ |
1446 | struct dwc3_event_devt { | |
1447 | u32 one_bit:1; | |
1448 | u32 device_event:7; | |
1449 | u32 type:4; | |
1450 | u32 reserved15_12:4; | |
06f9b6e5 HR |
1451 | u32 event_info:9; |
1452 | u32 reserved31_25:7; | |
72246da4 FB |
1453 | } __packed; |
1454 | ||
1455 | /** | |
1456 | * struct dwc3_event_gevt - Other Core Events | |
1457 | * @one_bit: indicates this is a non-endpoint event (not used) | |
1458 | * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. | |
1459 | * @phy_port_number: self-explanatory | |
1460 | * @reserved31_12: Reserved, not used. | |
1461 | */ | |
1462 | struct dwc3_event_gevt { | |
1463 | u32 one_bit:1; | |
1464 | u32 device_event:7; | |
1465 | u32 phy_port_number:4; | |
1466 | u32 reserved31_12:20; | |
1467 | } __packed; | |
1468 | ||
1469 | /** | |
1470 | * union dwc3_event - representation of Event Buffer contents | |
1471 | * @raw: raw 32-bit event | |
1472 | * @type: the type of the event | |
1473 | * @depevt: Device Endpoint Event | |
1474 | * @devt: Device Event | |
1475 | * @gevt: Global Event | |
1476 | */ | |
1477 | union dwc3_event { | |
1478 | u32 raw; | |
1479 | struct dwc3_event_type type; | |
1480 | struct dwc3_event_depevt depevt; | |
1481 | struct dwc3_event_devt devt; | |
1482 | struct dwc3_event_gevt gevt; | |
1483 | }; | |
1484 | ||
61018305 FB |
1485 | /** |
1486 | * struct dwc3_gadget_ep_cmd_params - representation of endpoint command | |
1487 | * parameters | |
1488 | * @param2: third parameter | |
1489 | * @param1: second parameter | |
1490 | * @param0: first parameter | |
1491 | */ | |
1492 | struct dwc3_gadget_ep_cmd_params { | |
1493 | u32 param2; | |
1494 | u32 param1; | |
1495 | u32 param0; | |
1496 | }; | |
1497 | ||
72246da4 FB |
1498 | /* |
1499 | * DWC3 Features to be used as Driver Data | |
1500 | */ | |
1501 | ||
1502 | #define DWC3_HAS_PERIPHERAL BIT(0) | |
1503 | #define DWC3_HAS_XHCI BIT(1) | |
1504 | #define DWC3_HAS_OTG BIT(3) | |
1505 | ||
d07e8819 | 1506 | /* prototypes */ |
f09cc79b | 1507 | void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode); |
3140e8cb | 1508 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode); |
cf6d867d | 1509 | u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type); |
3140e8cb | 1510 | |
9af21dd6 TN |
1511 | #define DWC3_IP_IS(_ip) \ |
1512 | (dwc->ip == _ip##_IP) | |
1513 | ||
1514 | #define DWC3_VER_IS(_ip, _ver) \ | |
1515 | (DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver) | |
1516 | ||
1517 | #define DWC3_VER_IS_PRIOR(_ip, _ver) \ | |
1518 | (DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver) | |
1519 | ||
1520 | #define DWC3_VER_IS_WITHIN(_ip, _from, _to) \ | |
1521 | (DWC3_IP_IS(_ip) && \ | |
1522 | dwc->revision >= _ip##_REVISION_##_from && \ | |
1523 | (!(_ip##_REVISION_##_to) || \ | |
1524 | dwc->revision <= _ip##_REVISION_##_to)) | |
1525 | ||
1526 | #define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to) \ | |
1527 | (DWC3_VER_IS(_ip, _ver) && \ | |
1528 | dwc->version_type >= _ip##_VERSIONTYPE_##_from && \ | |
1529 | (!(_ip##_VERSIONTYPE_##_to) || \ | |
1530 | dwc->version_type <= _ip##_VERSIONTYPE_##_to)) | |
c4137a9c | 1531 | |
d00be779 TN |
1532 | /** |
1533 | * dwc3_mdwidth - get MDWIDTH value in bits | |
1534 | * @dwc: pointer to our context structure | |
1535 | * | |
1536 | * Return MDWIDTH configuration value in bits. | |
1537 | */ | |
1538 | static inline u32 dwc3_mdwidth(struct dwc3 *dwc) | |
1539 | { | |
1540 | u32 mdwidth; | |
1541 | ||
1542 | mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0); | |
1543 | if (DWC3_IP_IS(DWC32)) | |
1544 | mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6); | |
1545 | ||
1546 | return mdwidth; | |
1547 | } | |
1548 | ||
cf40b86b JY |
1549 | bool dwc3_has_imod(struct dwc3 *dwc); |
1550 | ||
f09cc79b RQ |
1551 | int dwc3_event_buffers_setup(struct dwc3 *dwc); |
1552 | void dwc3_event_buffers_cleanup(struct dwc3 *dwc); | |
0066472d WC |
1553 | |
1554 | int dwc3_core_soft_reset(struct dwc3 *dwc); | |
f09cc79b | 1555 | |
388e5c51 | 1556 | #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
d07e8819 FB |
1557 | int dwc3_host_init(struct dwc3 *dwc); |
1558 | void dwc3_host_exit(struct dwc3 *dwc); | |
388e5c51 VG |
1559 | #else |
1560 | static inline int dwc3_host_init(struct dwc3 *dwc) | |
1561 | { return 0; } | |
1562 | static inline void dwc3_host_exit(struct dwc3 *dwc) | |
1563 | { } | |
1564 | #endif | |
1565 | ||
1566 | #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) | |
f80b45e7 FB |
1567 | int dwc3_gadget_init(struct dwc3 *dwc); |
1568 | void dwc3_gadget_exit(struct dwc3 *dwc); | |
61018305 FB |
1569 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); |
1570 | int dwc3_gadget_get_link_state(struct dwc3 *dwc); | |
1571 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); | |
87b923a2 | 1572 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, |
2cd4718d | 1573 | struct dwc3_gadget_ep_cmd_params *params); |
87b923a2 FB |
1574 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, |
1575 | u32 param); | |
9f607a30 | 1576 | void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc); |
2b2da657 | 1577 | void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status); |
388e5c51 VG |
1578 | #else |
1579 | static inline int dwc3_gadget_init(struct dwc3 *dwc) | |
1580 | { return 0; } | |
1581 | static inline void dwc3_gadget_exit(struct dwc3 *dwc) | |
1582 | { } | |
61018305 FB |
1583 | static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) |
1584 | { return 0; } | |
1585 | static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
1586 | { return 0; } | |
1587 | static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, | |
1588 | enum dwc3_link_state state) | |
1589 | { return 0; } | |
1590 | ||
87b923a2 | 1591 | static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, |
2cd4718d | 1592 | struct dwc3_gadget_ep_cmd_params *params) |
61018305 FB |
1593 | { return 0; } |
1594 | static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, | |
1595 | int cmd, u32 param) | |
1596 | { return 0; } | |
9f607a30 WC |
1597 | static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc) |
1598 | { } | |
388e5c51 | 1599 | #endif |
f80b45e7 | 1600 | |
9840354f RQ |
1601 | #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
1602 | int dwc3_drd_init(struct dwc3 *dwc); | |
1603 | void dwc3_drd_exit(struct dwc3 *dwc); | |
f09cc79b RQ |
1604 | void dwc3_otg_init(struct dwc3 *dwc); |
1605 | void dwc3_otg_exit(struct dwc3 *dwc); | |
1606 | void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus); | |
1607 | void dwc3_otg_host_init(struct dwc3 *dwc); | |
9840354f RQ |
1608 | #else |
1609 | static inline int dwc3_drd_init(struct dwc3 *dwc) | |
1610 | { return 0; } | |
1611 | static inline void dwc3_drd_exit(struct dwc3 *dwc) | |
1612 | { } | |
f09cc79b RQ |
1613 | static inline void dwc3_otg_init(struct dwc3 *dwc) |
1614 | { } | |
1615 | static inline void dwc3_otg_exit(struct dwc3 *dwc) | |
1616 | { } | |
1617 | static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) | |
1618 | { } | |
1619 | static inline void dwc3_otg_host_init(struct dwc3 *dwc) | |
1620 | { } | |
9840354f RQ |
1621 | #endif |
1622 | ||
7415f17c FB |
1623 | /* power management interface */ |
1624 | #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) | |
7415f17c FB |
1625 | int dwc3_gadget_suspend(struct dwc3 *dwc); |
1626 | int dwc3_gadget_resume(struct dwc3 *dwc); | |
fc8bb91b | 1627 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc); |
7415f17c | 1628 | #else |
7415f17c FB |
1629 | static inline int dwc3_gadget_suspend(struct dwc3 *dwc) |
1630 | { | |
1631 | return 0; | |
1632 | } | |
1633 | ||
1634 | static inline int dwc3_gadget_resume(struct dwc3 *dwc) | |
1635 | { | |
1636 | return 0; | |
1637 | } | |
fc8bb91b FB |
1638 | |
1639 | static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc) | |
1640 | { | |
1641 | } | |
7415f17c FB |
1642 | #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ |
1643 | ||
88bc9d19 HK |
1644 | #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) |
1645 | int dwc3_ulpi_init(struct dwc3 *dwc); | |
1646 | void dwc3_ulpi_exit(struct dwc3 *dwc); | |
1647 | #else | |
1648 | static inline int dwc3_ulpi_init(struct dwc3 *dwc) | |
1649 | { return 0; } | |
1650 | static inline void dwc3_ulpi_exit(struct dwc3 *dwc) | |
1651 | { } | |
1652 | #endif | |
1653 | ||
72246da4 | 1654 | #endif /* __DRIVERS_USB_DWC3_CORE_H */ |