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72246da4 FB |
1 | /** |
2 | * core.h - DesignWare USB3 DRD Core Header | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #ifndef __DRIVERS_USB_DWC3_CORE_H | |
20 | #define __DRIVERS_USB_DWC3_CORE_H | |
21 | ||
22 | #include <linux/device.h> | |
23 | #include <linux/spinlock.h> | |
d07e8819 | 24 | #include <linux/ioport.h> |
72246da4 FB |
25 | #include <linux/list.h> |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/mm.h> | |
28 | #include <linux/debugfs.h> | |
29 | ||
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
a45c82b8 | 32 | #include <linux/usb/otg.h> |
72246da4 | 33 | |
57303488 KVA |
34 | #include <linux/phy/phy.h> |
35 | ||
2c4cbe6e FB |
36 | #define DWC3_MSG_MAX 500 |
37 | ||
72246da4 | 38 | /* Global constants */ |
3ef35faf | 39 | #define DWC3_EP0_BOUNCE_SIZE 512 |
72246da4 | 40 | #define DWC3_ENDPOINTS_NUM 32 |
51249dca | 41 | #define DWC3_XHCI_RESOURCES_NUM 2 |
72246da4 | 42 | |
0ffcaf37 | 43 | #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ |
5da93478 FB |
44 | #define DWC3_EVENT_SIZE 4 /* bytes */ |
45 | #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ | |
46 | #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) | |
72246da4 FB |
47 | #define DWC3_EVENT_TYPE_MASK 0xfe |
48 | ||
49 | #define DWC3_EVENT_TYPE_DEV 0 | |
50 | #define DWC3_EVENT_TYPE_CARKIT 3 | |
51 | #define DWC3_EVENT_TYPE_I2C 4 | |
52 | ||
53 | #define DWC3_DEVICE_EVENT_DISCONNECT 0 | |
54 | #define DWC3_DEVICE_EVENT_RESET 1 | |
55 | #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 | |
56 | #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 | |
57 | #define DWC3_DEVICE_EVENT_WAKEUP 4 | |
2c61a8ef | 58 | #define DWC3_DEVICE_EVENT_HIBER_REQ 5 |
72246da4 FB |
59 | #define DWC3_DEVICE_EVENT_EOPF 6 |
60 | #define DWC3_DEVICE_EVENT_SOF 7 | |
61 | #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 | |
62 | #define DWC3_DEVICE_EVENT_CMD_CMPL 10 | |
63 | #define DWC3_DEVICE_EVENT_OVERFLOW 11 | |
64 | ||
65 | #define DWC3_GEVNTCOUNT_MASK 0xfffc | |
66 | #define DWC3_GSNPSID_MASK 0xffff0000 | |
67 | #define DWC3_GSNPSREV_MASK 0xffff | |
68 | ||
51249dca IS |
69 | /* DWC3 registers memory space boundries */ |
70 | #define DWC3_XHCI_REGS_START 0x0 | |
71 | #define DWC3_XHCI_REGS_END 0x7fff | |
72 | #define DWC3_GLOBALS_REGS_START 0xc100 | |
73 | #define DWC3_GLOBALS_REGS_END 0xc6ff | |
74 | #define DWC3_DEVICE_REGS_START 0xc700 | |
75 | #define DWC3_DEVICE_REGS_END 0xcbff | |
76 | #define DWC3_OTG_REGS_START 0xcc00 | |
77 | #define DWC3_OTG_REGS_END 0xccff | |
78 | ||
72246da4 FB |
79 | /* Global Registers */ |
80 | #define DWC3_GSBUSCFG0 0xc100 | |
81 | #define DWC3_GSBUSCFG1 0xc104 | |
82 | #define DWC3_GTXTHRCFG 0xc108 | |
83 | #define DWC3_GRXTHRCFG 0xc10c | |
84 | #define DWC3_GCTL 0xc110 | |
85 | #define DWC3_GEVTEN 0xc114 | |
86 | #define DWC3_GSTS 0xc118 | |
87 | #define DWC3_GSNPSID 0xc120 | |
88 | #define DWC3_GGPIO 0xc124 | |
89 | #define DWC3_GUID 0xc128 | |
90 | #define DWC3_GUCTL 0xc12c | |
91 | #define DWC3_GBUSERRADDR0 0xc130 | |
92 | #define DWC3_GBUSERRADDR1 0xc134 | |
93 | #define DWC3_GPRTBIMAP0 0xc138 | |
94 | #define DWC3_GPRTBIMAP1 0xc13c | |
95 | #define DWC3_GHWPARAMS0 0xc140 | |
96 | #define DWC3_GHWPARAMS1 0xc144 | |
97 | #define DWC3_GHWPARAMS2 0xc148 | |
98 | #define DWC3_GHWPARAMS3 0xc14c | |
99 | #define DWC3_GHWPARAMS4 0xc150 | |
100 | #define DWC3_GHWPARAMS5 0xc154 | |
101 | #define DWC3_GHWPARAMS6 0xc158 | |
102 | #define DWC3_GHWPARAMS7 0xc15c | |
103 | #define DWC3_GDBGFIFOSPACE 0xc160 | |
104 | #define DWC3_GDBGLTSSM 0xc164 | |
105 | #define DWC3_GPRTBIMAP_HS0 0xc180 | |
106 | #define DWC3_GPRTBIMAP_HS1 0xc184 | |
107 | #define DWC3_GPRTBIMAP_FS0 0xc188 | |
108 | #define DWC3_GPRTBIMAP_FS1 0xc18c | |
109 | ||
110 | #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) | |
111 | #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) | |
112 | ||
113 | #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) | |
114 | ||
115 | #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) | |
116 | ||
117 | #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) | |
118 | #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) | |
119 | ||
120 | #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) | |
121 | #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) | |
122 | #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) | |
123 | #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) | |
124 | ||
125 | #define DWC3_GHWPARAMS8 0xc600 | |
126 | ||
127 | /* Device Registers */ | |
128 | #define DWC3_DCFG 0xc700 | |
129 | #define DWC3_DCTL 0xc704 | |
130 | #define DWC3_DEVTEN 0xc708 | |
131 | #define DWC3_DSTS 0xc70c | |
132 | #define DWC3_DGCMDPAR 0xc710 | |
133 | #define DWC3_DGCMD 0xc714 | |
134 | #define DWC3_DALEPENA 0xc720 | |
135 | #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) | |
136 | #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) | |
137 | #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) | |
138 | #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) | |
139 | ||
140 | /* OTG Registers */ | |
141 | #define DWC3_OCFG 0xcc00 | |
142 | #define DWC3_OCTL 0xcc04 | |
d4436c3a GC |
143 | #define DWC3_OEVT 0xcc08 |
144 | #define DWC3_OEVTEN 0xcc0C | |
145 | #define DWC3_OSTS 0xcc10 | |
72246da4 FB |
146 | |
147 | /* Bit fields */ | |
148 | ||
149 | /* Global Configuration Register */ | |
1d046793 | 150 | #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) |
f4aadbe4 | 151 | #define DWC3_GCTL_U2RSTECN (1 << 16) |
1d046793 | 152 | #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) |
72246da4 FB |
153 | #define DWC3_GCTL_CLK_BUS (0) |
154 | #define DWC3_GCTL_CLK_PIPE (1) | |
155 | #define DWC3_GCTL_CLK_PIPEHALF (2) | |
156 | #define DWC3_GCTL_CLK_MASK (3) | |
157 | ||
0b9fe32d | 158 | #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) |
1d046793 | 159 | #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) |
72246da4 FB |
160 | #define DWC3_GCTL_PRTCAP_HOST 1 |
161 | #define DWC3_GCTL_PRTCAP_DEVICE 2 | |
162 | #define DWC3_GCTL_PRTCAP_OTG 3 | |
163 | ||
2c61a8ef | 164 | #define DWC3_GCTL_CORESOFTRESET (1 << 11) |
183ca111 | 165 | #define DWC3_GCTL_SOFITPSYNC (1 << 10) |
2c61a8ef PZ |
166 | #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) |
167 | #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) | |
168 | #define DWC3_GCTL_DISSCRAMBLE (1 << 3) | |
9a5b2f31 | 169 | #define DWC3_GCTL_U2EXIT_LFPS (1 << 2) |
2c61a8ef PZ |
170 | #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) |
171 | #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) | |
72246da4 FB |
172 | |
173 | /* Global USB2 PHY Configuration Register */ | |
2c61a8ef PZ |
174 | #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) |
175 | #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) | |
72246da4 | 176 | |
b5699eee HK |
177 | /* Global USB2 PHY Vendor Control Register */ |
178 | #define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25) | |
179 | #define DWC3_GUSB2PHYACC_BUSY (1 << 23) | |
180 | #define DWC3_GUSB2PHYACC_WRITE (1 << 22) | |
181 | #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) | |
182 | #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) | |
183 | #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) | |
184 | ||
72246da4 | 185 | /* Global USB3 PIPE Control Register */ |
2c61a8ef | 186 | #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) |
b5a65c40 | 187 | #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) |
df31f5b3 | 188 | #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) |
a2a1d0f5 HR |
189 | #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) |
190 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) | |
191 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) | |
41c06ffd | 192 | #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) |
2c61a8ef | 193 | #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) |
fb67afca | 194 | #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) |
14f4ac53 | 195 | #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) |
6b6a0c9a HR |
196 | #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) |
197 | #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) | |
72246da4 | 198 | |
457e84b6 | 199 | /* Global TX Fifo Size Register */ |
2c61a8ef PZ |
200 | #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) |
201 | #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) | |
457e84b6 | 202 | |
68d6a01b FB |
203 | /* Global Event Size Registers */ |
204 | #define DWC3_GEVNTSIZ_INTMASK (1 << 31) | |
205 | #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) | |
206 | ||
aabb7075 | 207 | /* Global HWPARAMS1 Register */ |
1d046793 | 208 | #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) |
aabb7075 FB |
209 | #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 |
210 | #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 | |
2c61a8ef PZ |
211 | #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 |
212 | #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) | |
213 | #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) | |
214 | ||
0e1e5c47 PZ |
215 | /* Global HWPARAMS3 Register */ |
216 | #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) | |
217 | #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 | |
218 | #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1 | |
219 | #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) | |
220 | #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 | |
221 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 | |
222 | #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 | |
223 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 | |
224 | #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) | |
225 | #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 | |
226 | #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 | |
227 | ||
2c61a8ef PZ |
228 | /* Global HWPARAMS4 Register */ |
229 | #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) | |
230 | #define DWC3_MAX_HIBER_SCRATCHBUFS 15 | |
aabb7075 | 231 | |
946bd579 HR |
232 | /* Global HWPARAMS6 Register */ |
233 | #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) | |
234 | ||
72246da4 FB |
235 | /* Device Configuration Register */ |
236 | #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) | |
237 | #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) | |
238 | ||
239 | #define DWC3_DCFG_SPEED_MASK (7 << 0) | |
240 | #define DWC3_DCFG_SUPERSPEED (4 << 0) | |
241 | #define DWC3_DCFG_HIGHSPEED (0 << 0) | |
242 | #define DWC3_DCFG_FULLSPEED2 (1 << 0) | |
243 | #define DWC3_DCFG_LOWSPEED (2 << 0) | |
244 | #define DWC3_DCFG_FULLSPEED1 (3 << 0) | |
245 | ||
2c61a8ef PZ |
246 | #define DWC3_DCFG_LPM_CAP (1 << 22) |
247 | ||
72246da4 FB |
248 | /* Device Control Register */ |
249 | #define DWC3_DCTL_RUN_STOP (1 << 31) | |
250 | #define DWC3_DCTL_CSFTRST (1 << 30) | |
251 | #define DWC3_DCTL_LSFTRST (1 << 29) | |
252 | ||
253 | #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) | |
7e39b817 | 254 | #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) |
72246da4 FB |
255 | |
256 | #define DWC3_DCTL_APPL1RES (1 << 23) | |
257 | ||
2c61a8ef PZ |
258 | /* These apply for core versions 1.87a and earlier */ |
259 | #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) | |
260 | #define DWC3_DCTL_TRGTULST(n) ((n) << 17) | |
261 | #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) | |
262 | #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) | |
263 | #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) | |
264 | #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) | |
265 | #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) | |
266 | ||
267 | /* These apply for core versions 1.94a and later */ | |
80caf7d2 HR |
268 | #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) |
269 | #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) | |
8db7ed15 | 270 | |
80caf7d2 HR |
271 | #define DWC3_DCTL_KEEP_CONNECT (1 << 19) |
272 | #define DWC3_DCTL_L1_HIBER_EN (1 << 18) | |
273 | #define DWC3_DCTL_CRS (1 << 17) | |
274 | #define DWC3_DCTL_CSS (1 << 16) | |
275 | ||
276 | #define DWC3_DCTL_INITU2ENA (1 << 12) | |
277 | #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) | |
278 | #define DWC3_DCTL_INITU1ENA (1 << 10) | |
279 | #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) | |
280 | #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) | |
72246da4 FB |
281 | |
282 | #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) | |
283 | #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) | |
284 | ||
285 | #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) | |
286 | #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) | |
287 | #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) | |
288 | #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) | |
289 | #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) | |
290 | #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) | |
291 | #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) | |
292 | ||
293 | /* Device Event Enable Register */ | |
294 | #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) | |
295 | #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) | |
296 | #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) | |
297 | #define DWC3_DEVTEN_ERRTICERREN (1 << 9) | |
298 | #define DWC3_DEVTEN_SOFEN (1 << 7) | |
299 | #define DWC3_DEVTEN_EOPFEN (1 << 6) | |
2c61a8ef | 300 | #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) |
72246da4 FB |
301 | #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) |
302 | #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) | |
303 | #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) | |
304 | #define DWC3_DEVTEN_USBRSTEN (1 << 1) | |
305 | #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) | |
306 | ||
307 | /* Device Status Register */ | |
2c61a8ef PZ |
308 | #define DWC3_DSTS_DCNRD (1 << 29) |
309 | ||
310 | /* This applies for core versions 1.87a and earlier */ | |
72246da4 | 311 | #define DWC3_DSTS_PWRUPREQ (1 << 24) |
2c61a8ef PZ |
312 | |
313 | /* These apply for core versions 1.94a and later */ | |
314 | #define DWC3_DSTS_RSS (1 << 25) | |
315 | #define DWC3_DSTS_SSS (1 << 24) | |
316 | ||
72246da4 FB |
317 | #define DWC3_DSTS_COREIDLE (1 << 23) |
318 | #define DWC3_DSTS_DEVCTRLHLT (1 << 22) | |
319 | ||
320 | #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) | |
321 | #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) | |
322 | ||
323 | #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) | |
324 | ||
d05b8182 | 325 | #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) |
72246da4 FB |
326 | #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) |
327 | ||
328 | #define DWC3_DSTS_CONNECTSPD (7 << 0) | |
329 | ||
330 | #define DWC3_DSTS_SUPERSPEED (4 << 0) | |
331 | #define DWC3_DSTS_HIGHSPEED (0 << 0) | |
332 | #define DWC3_DSTS_FULLSPEED2 (1 << 0) | |
333 | #define DWC3_DSTS_LOWSPEED (2 << 0) | |
334 | #define DWC3_DSTS_FULLSPEED1 (3 << 0) | |
335 | ||
336 | /* Device Generic Command Register */ | |
337 | #define DWC3_DGCMD_SET_LMP 0x01 | |
338 | #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 | |
339 | #define DWC3_DGCMD_XMIT_FUNCTION 0x03 | |
2c61a8ef PZ |
340 | |
341 | /* These apply for core versions 1.94a and later */ | |
342 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 | |
343 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 | |
344 | ||
72246da4 FB |
345 | #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 |
346 | #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a | |
347 | #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c | |
348 | #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 | |
349 | ||
b09bb642 FB |
350 | #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) |
351 | #define DWC3_DGCMD_CMDACT (1 << 10) | |
2c61a8ef PZ |
352 | #define DWC3_DGCMD_CMDIOC (1 << 8) |
353 | ||
354 | /* Device Generic Command Parameter Register */ | |
355 | #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) | |
356 | #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) | |
357 | #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) | |
358 | #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) | |
359 | #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) | |
360 | #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) | |
b09bb642 | 361 | |
72246da4 FB |
362 | /* Device Endpoint Command Register */ |
363 | #define DWC3_DEPCMD_PARAM_SHIFT 16 | |
1d046793 | 364 | #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) |
835fadb4 | 365 | #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) |
b09bb642 | 366 | #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) |
72246da4 FB |
367 | #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) |
368 | #define DWC3_DEPCMD_CMDACT (1 << 10) | |
369 | #define DWC3_DEPCMD_CMDIOC (1 << 8) | |
370 | ||
371 | #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) | |
372 | #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) | |
373 | #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) | |
374 | #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) | |
375 | #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) | |
376 | #define DWC3_DEPCMD_SETSTALL (0x04 << 0) | |
2c61a8ef | 377 | /* This applies for core versions 1.90a and earlier */ |
72246da4 | 378 | #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) |
2c61a8ef PZ |
379 | /* This applies for core versions 1.94a and later */ |
380 | #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) | |
72246da4 FB |
381 | #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) |
382 | #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) | |
383 | ||
384 | /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ | |
385 | #define DWC3_DALEPENA_EP(n) (1 << n) | |
386 | ||
387 | #define DWC3_DEPCMD_TYPE_CONTROL 0 | |
388 | #define DWC3_DEPCMD_TYPE_ISOC 1 | |
389 | #define DWC3_DEPCMD_TYPE_BULK 2 | |
390 | #define DWC3_DEPCMD_TYPE_INTR 3 | |
391 | ||
392 | /* Structures */ | |
393 | ||
f6bafc6a | 394 | struct dwc3_trb; |
72246da4 FB |
395 | |
396 | /** | |
397 | * struct dwc3_event_buffer - Software event buffer representation | |
72246da4 FB |
398 | * @buf: _THE_ buffer |
399 | * @length: size of this buffer | |
abed4118 | 400 | * @lpos: event offset |
60d04bbe | 401 | * @count: cache of last read event count register |
abed4118 | 402 | * @flags: flags related to this event buffer |
72246da4 FB |
403 | * @dma: dma_addr_t |
404 | * @dwc: pointer to DWC controller | |
405 | */ | |
406 | struct dwc3_event_buffer { | |
407 | void *buf; | |
408 | unsigned length; | |
409 | unsigned int lpos; | |
60d04bbe | 410 | unsigned int count; |
abed4118 FB |
411 | unsigned int flags; |
412 | ||
413 | #define DWC3_EVENT_PENDING BIT(0) | |
72246da4 FB |
414 | |
415 | dma_addr_t dma; | |
416 | ||
417 | struct dwc3 *dwc; | |
418 | }; | |
419 | ||
420 | #define DWC3_EP_FLAG_STALLED (1 << 0) | |
421 | #define DWC3_EP_FLAG_WEDGED (1 << 1) | |
422 | ||
423 | #define DWC3_EP_DIRECTION_TX true | |
424 | #define DWC3_EP_DIRECTION_RX false | |
425 | ||
426 | #define DWC3_TRB_NUM 32 | |
427 | #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) | |
428 | ||
429 | /** | |
430 | * struct dwc3_ep - device side endpoint representation | |
431 | * @endpoint: usb endpoint | |
432 | * @request_list: list of requests for this endpoint | |
433 | * @req_queued: list of requests on this ep which have TRBs setup | |
434 | * @trb_pool: array of transaction buffers | |
435 | * @trb_pool_dma: dma address of @trb_pool | |
436 | * @free_slot: next slot which is going to be used | |
437 | * @busy_slot: first slot which is owned by HW | |
438 | * @desc: usb_endpoint_descriptor pointer | |
439 | * @dwc: pointer to DWC controller | |
4cfcf876 | 440 | * @saved_state: ep state saved during hibernation |
72246da4 | 441 | * @flags: endpoint flags (wedged, stalled, ...) |
72246da4 FB |
442 | * @number: endpoint number (1 - 15) |
443 | * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK | |
b4996a86 | 444 | * @resource_index: Resource transfer index |
c75f52fb | 445 | * @interval: the interval on which the ISOC transfer is started |
72246da4 FB |
446 | * @name: a human readable name e.g. ep1out-bulk |
447 | * @direction: true for TX, false for RX | |
879631aa | 448 | * @stream_capable: true when streams are enabled |
72246da4 FB |
449 | */ |
450 | struct dwc3_ep { | |
451 | struct usb_ep endpoint; | |
452 | struct list_head request_list; | |
453 | struct list_head req_queued; | |
454 | ||
f6bafc6a | 455 | struct dwc3_trb *trb_pool; |
72246da4 FB |
456 | dma_addr_t trb_pool_dma; |
457 | u32 free_slot; | |
458 | u32 busy_slot; | |
c90bfaec | 459 | const struct usb_ss_ep_comp_descriptor *comp_desc; |
72246da4 FB |
460 | struct dwc3 *dwc; |
461 | ||
4cfcf876 | 462 | u32 saved_state; |
72246da4 FB |
463 | unsigned flags; |
464 | #define DWC3_EP_ENABLED (1 << 0) | |
465 | #define DWC3_EP_STALL (1 << 1) | |
466 | #define DWC3_EP_WEDGE (1 << 2) | |
467 | #define DWC3_EP_BUSY (1 << 4) | |
468 | #define DWC3_EP_PENDING_REQUEST (1 << 5) | |
d6d6ec7b | 469 | #define DWC3_EP_MISSED_ISOC (1 << 6) |
72246da4 | 470 | |
984f66a6 FB |
471 | /* This last one is specific to EP0 */ |
472 | #define DWC3_EP0_DIR_IN (1 << 31) | |
473 | ||
72246da4 FB |
474 | u8 number; |
475 | u8 type; | |
b4996a86 | 476 | u8 resource_index; |
72246da4 FB |
477 | u32 interval; |
478 | ||
479 | char name[20]; | |
480 | ||
481 | unsigned direction:1; | |
879631aa | 482 | unsigned stream_capable:1; |
72246da4 FB |
483 | }; |
484 | ||
485 | enum dwc3_phy { | |
486 | DWC3_PHY_UNKNOWN = 0, | |
487 | DWC3_PHY_USB3, | |
488 | DWC3_PHY_USB2, | |
489 | }; | |
490 | ||
b53c772d FB |
491 | enum dwc3_ep0_next { |
492 | DWC3_EP0_UNKNOWN = 0, | |
493 | DWC3_EP0_COMPLETE, | |
b53c772d FB |
494 | DWC3_EP0_NRDY_DATA, |
495 | DWC3_EP0_NRDY_STATUS, | |
496 | }; | |
497 | ||
72246da4 FB |
498 | enum dwc3_ep0_state { |
499 | EP0_UNCONNECTED = 0, | |
c7fcdeb2 FB |
500 | EP0_SETUP_PHASE, |
501 | EP0_DATA_PHASE, | |
502 | EP0_STATUS_PHASE, | |
72246da4 FB |
503 | }; |
504 | ||
505 | enum dwc3_link_state { | |
506 | /* In SuperSpeed */ | |
507 | DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ | |
508 | DWC3_LINK_STATE_U1 = 0x01, | |
509 | DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ | |
510 | DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ | |
511 | DWC3_LINK_STATE_SS_DIS = 0x04, | |
512 | DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ | |
513 | DWC3_LINK_STATE_SS_INACT = 0x06, | |
514 | DWC3_LINK_STATE_POLL = 0x07, | |
515 | DWC3_LINK_STATE_RECOV = 0x08, | |
516 | DWC3_LINK_STATE_HRESET = 0x09, | |
517 | DWC3_LINK_STATE_CMPLY = 0x0a, | |
518 | DWC3_LINK_STATE_LPBK = 0x0b, | |
2c61a8ef PZ |
519 | DWC3_LINK_STATE_RESET = 0x0e, |
520 | DWC3_LINK_STATE_RESUME = 0x0f, | |
72246da4 FB |
521 | DWC3_LINK_STATE_MASK = 0x0f, |
522 | }; | |
523 | ||
f6bafc6a FB |
524 | /* TRB Length, PCM and Status */ |
525 | #define DWC3_TRB_SIZE_MASK (0x00ffffff) | |
526 | #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) | |
527 | #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) | |
389f2828 | 528 | #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) |
f6bafc6a FB |
529 | |
530 | #define DWC3_TRBSTS_OK 0 | |
531 | #define DWC3_TRBSTS_MISSED_ISOC 1 | |
532 | #define DWC3_TRBSTS_SETUP_PENDING 2 | |
2c61a8ef | 533 | #define DWC3_TRB_STS_XFER_IN_PROG 4 |
f6bafc6a FB |
534 | |
535 | /* TRB Control */ | |
536 | #define DWC3_TRB_CTRL_HWO (1 << 0) | |
537 | #define DWC3_TRB_CTRL_LST (1 << 1) | |
538 | #define DWC3_TRB_CTRL_CHN (1 << 2) | |
539 | #define DWC3_TRB_CTRL_CSP (1 << 3) | |
540 | #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) | |
541 | #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) | |
542 | #define DWC3_TRB_CTRL_IOC (1 << 11) | |
543 | #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) | |
544 | ||
545 | #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) | |
546 | #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) | |
547 | #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) | |
548 | #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) | |
549 | #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) | |
550 | #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) | |
551 | #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) | |
552 | #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) | |
72246da4 FB |
553 | |
554 | /** | |
f6bafc6a | 555 | * struct dwc3_trb - transfer request block (hw format) |
72246da4 FB |
556 | * @bpl: DW0-3 |
557 | * @bph: DW4-7 | |
558 | * @size: DW8-B | |
559 | * @trl: DWC-F | |
560 | */ | |
f6bafc6a FB |
561 | struct dwc3_trb { |
562 | u32 bpl; | |
563 | u32 bph; | |
564 | u32 size; | |
565 | u32 ctrl; | |
72246da4 FB |
566 | } __packed; |
567 | ||
a3299499 FB |
568 | /** |
569 | * dwc3_hwparams - copy of HWPARAMS registers | |
570 | * @hwparams0 - GHWPARAMS0 | |
571 | * @hwparams1 - GHWPARAMS1 | |
572 | * @hwparams2 - GHWPARAMS2 | |
573 | * @hwparams3 - GHWPARAMS3 | |
574 | * @hwparams4 - GHWPARAMS4 | |
575 | * @hwparams5 - GHWPARAMS5 | |
576 | * @hwparams6 - GHWPARAMS6 | |
577 | * @hwparams7 - GHWPARAMS7 | |
578 | * @hwparams8 - GHWPARAMS8 | |
579 | */ | |
580 | struct dwc3_hwparams { | |
581 | u32 hwparams0; | |
582 | u32 hwparams1; | |
583 | u32 hwparams2; | |
584 | u32 hwparams3; | |
585 | u32 hwparams4; | |
586 | u32 hwparams5; | |
587 | u32 hwparams6; | |
588 | u32 hwparams7; | |
589 | u32 hwparams8; | |
590 | }; | |
591 | ||
0949e99b FB |
592 | /* HWPARAMS0 */ |
593 | #define DWC3_MODE(n) ((n) & 0x7) | |
594 | ||
457e84b6 FB |
595 | #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) |
596 | ||
0949e99b | 597 | /* HWPARAMS1 */ |
457e84b6 FB |
598 | #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) |
599 | ||
789451f6 FB |
600 | /* HWPARAMS3 */ |
601 | #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) | |
602 | #define DWC3_NUM_EPS_MASK (0x3f << 12) | |
603 | #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ | |
604 | (DWC3_NUM_EPS_MASK)) >> 12) | |
605 | #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ | |
606 | (DWC3_NUM_IN_EPS_MASK)) >> 18) | |
607 | ||
457e84b6 FB |
608 | /* HWPARAMS7 */ |
609 | #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) | |
9f622b2a | 610 | |
e0ce0b0a SAS |
611 | struct dwc3_request { |
612 | struct usb_request request; | |
613 | struct list_head list; | |
614 | struct dwc3_ep *dep; | |
e5ba5ec8 | 615 | u32 start_slot; |
e0ce0b0a SAS |
616 | |
617 | u8 epnum; | |
f6bafc6a | 618 | struct dwc3_trb *trb; |
e0ce0b0a SAS |
619 | dma_addr_t trb_dma; |
620 | ||
621 | unsigned direction:1; | |
622 | unsigned mapped:1; | |
623 | unsigned queued:1; | |
624 | }; | |
625 | ||
2c61a8ef PZ |
626 | /* |
627 | * struct dwc3_scratchpad_array - hibernation scratchpad array | |
628 | * (format defined by hw) | |
629 | */ | |
630 | struct dwc3_scratchpad_array { | |
631 | __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; | |
632 | }; | |
633 | ||
72246da4 FB |
634 | /** |
635 | * struct dwc3 - representation of our controller | |
91db07dc FB |
636 | * @ctrl_req: usb control request which is used for ep0 |
637 | * @ep0_trb: trb which is used for the ctrl_req | |
5812b1c2 | 638 | * @ep0_bounce: bounce buffer for ep0 |
91db07dc FB |
639 | * @setup_buf: used while precessing STD USB requests |
640 | * @ctrl_req_addr: dma address of ctrl_req | |
641 | * @ep0_trb: dma address of ep0_trb | |
642 | * @ep0_usb_req: dummy req used while handling STD USB requests | |
5812b1c2 | 643 | * @ep0_bounce_addr: dma address of ep0_bounce |
0ffcaf37 | 644 | * @scratch_addr: dma address of scratchbuf |
72246da4 FB |
645 | * @lock: for synchronizing |
646 | * @dev: pointer to our struct device | |
d07e8819 | 647 | * @xhci: pointer to our xHCI child |
72246da4 FB |
648 | * @event_buffer_list: a list of event buffers |
649 | * @gadget: device side representation of the peripheral controller | |
650 | * @gadget_driver: pointer to the gadget driver | |
651 | * @regs: base address for our registers | |
652 | * @regs_size: address space size | |
0ffcaf37 | 653 | * @nr_scratch: number of scratch buffers |
9f622b2a | 654 | * @num_event_buffers: calculated number of event buffers |
fae2b904 | 655 | * @u1u2: only used on revisions <1.83a for workaround |
6c167fc9 | 656 | * @maximum_speed: maximum speed requested (mainly for testing purposes) |
72246da4 | 657 | * @revision: revision register contents |
a45c82b8 | 658 | * @dr_mode: requested mode of operation |
51e1e7bc FB |
659 | * @usb2_phy: pointer to USB2 PHY |
660 | * @usb3_phy: pointer to USB3 PHY | |
57303488 KVA |
661 | * @usb2_generic_phy: pointer to USB2 PHY |
662 | * @usb3_generic_phy: pointer to USB3 PHY | |
7415f17c FB |
663 | * @dcfg: saved contents of DCFG register |
664 | * @gctl: saved contents of GCTL register | |
c12a0d86 | 665 | * @isoch_delay: wValue from Set Isochronous Delay request; |
865e09e7 FB |
666 | * @u2sel: parameter from Set SEL request. |
667 | * @u2pel: parameter from Set SEL request. | |
668 | * @u1sel: parameter from Set SEL request. | |
669 | * @u1pel: parameter from Set SEL request. | |
789451f6 FB |
670 | * @num_out_eps: number of out endpoints |
671 | * @num_in_eps: number of in endpoints | |
b53c772d | 672 | * @ep0_next_event: hold the next expected event |
72246da4 FB |
673 | * @ep0state: state of endpoint zero |
674 | * @link_state: link state | |
675 | * @speed: device speed (super, high, full, low) | |
676 | * @mem: points to start of memory which is used for this struct. | |
a3299499 | 677 | * @hwparams: copy of hwparams registers |
72246da4 | 678 | * @root: debugfs root folder pointer |
f2b685d5 FB |
679 | * @regset: debugfs pointer to regdump file |
680 | * @test_mode: true when we're entering a USB test mode | |
681 | * @test_mode_nr: test feature selector | |
80caf7d2 | 682 | * @lpm_nyet_threshold: LPM NYET response threshold |
460d098c | 683 | * @hird_threshold: HIRD threshold |
f2b685d5 FB |
684 | * @delayed_status: true when gadget driver asks for delayed status |
685 | * @ep0_bounced: true when we used bounce buffer | |
686 | * @ep0_expect_in: true when we expect a DATA IN transfer | |
81bc5599 | 687 | * @has_hibernation: true when dwc3 was configured with Hibernation |
80caf7d2 HR |
688 | * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that |
689 | * there's now way for software to detect this in runtime. | |
460d098c HR |
690 | * @is_utmi_l1_suspend: the core asserts output signal |
691 | * 0 - utmi_sleep_n | |
692 | * 1 - utmi_l1_suspend_n | |
946bd579 | 693 | * @is_fpga: true when we are using the FPGA board |
f2b685d5 FB |
694 | * @needs_fifo_resize: not all users might want fifo resizing, flag it |
695 | * @pullups_connected: true when Run/Stop bit is set | |
696 | * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. | |
697 | * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround | |
698 | * @start_config_issued: true when StartConfig command has been issued | |
699 | * @three_stage_setup: set if we perform a three phase setup | |
eac68e8f | 700 | * @usb3_lpm_capable: set if hadrware supports Link Power Management |
3b81221a | 701 | * @disable_scramble_quirk: set if we enable the disable scramble quirk |
9a5b2f31 | 702 | * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk |
b5a65c40 | 703 | * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk |
df31f5b3 | 704 | * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk |
a2a1d0f5 | 705 | * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk |
41c06ffd | 706 | * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk |
fb67afca | 707 | * @lfps_filter_quirk: set if we enable LFPS filter quirk |
14f4ac53 | 708 | * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk |
59acfa20 | 709 | * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy |
0effe0a3 | 710 | * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy |
6b6a0c9a HR |
711 | * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk |
712 | * @tx_de_emphasis: Tx de-emphasis value | |
713 | * 0 - -6dB de-emphasis | |
714 | * 1 - -3.5dB de-emphasis | |
715 | * 2 - No de-emphasis | |
716 | * 3 - Reserved | |
72246da4 FB |
717 | */ |
718 | struct dwc3 { | |
719 | struct usb_ctrlrequest *ctrl_req; | |
f6bafc6a | 720 | struct dwc3_trb *ep0_trb; |
5812b1c2 | 721 | void *ep0_bounce; |
0ffcaf37 | 722 | void *scratchbuf; |
72246da4 FB |
723 | u8 *setup_buf; |
724 | dma_addr_t ctrl_req_addr; | |
725 | dma_addr_t ep0_trb_addr; | |
5812b1c2 | 726 | dma_addr_t ep0_bounce_addr; |
0ffcaf37 | 727 | dma_addr_t scratch_addr; |
e0ce0b0a | 728 | struct dwc3_request ep0_usb_req; |
789451f6 | 729 | |
72246da4 FB |
730 | /* device lock */ |
731 | spinlock_t lock; | |
789451f6 | 732 | |
72246da4 FB |
733 | struct device *dev; |
734 | ||
d07e8819 | 735 | struct platform_device *xhci; |
51249dca | 736 | struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; |
d07e8819 | 737 | |
457d3f21 | 738 | struct dwc3_event_buffer **ev_buffs; |
72246da4 FB |
739 | struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; |
740 | ||
741 | struct usb_gadget gadget; | |
742 | struct usb_gadget_driver *gadget_driver; | |
743 | ||
51e1e7bc FB |
744 | struct usb_phy *usb2_phy; |
745 | struct usb_phy *usb3_phy; | |
746 | ||
57303488 KVA |
747 | struct phy *usb2_generic_phy; |
748 | struct phy *usb3_generic_phy; | |
749 | ||
72246da4 FB |
750 | void __iomem *regs; |
751 | size_t regs_size; | |
752 | ||
a45c82b8 RK |
753 | enum usb_dr_mode dr_mode; |
754 | ||
7415f17c FB |
755 | /* used for suspend/resume */ |
756 | u32 dcfg; | |
757 | u32 gctl; | |
758 | ||
0ffcaf37 | 759 | u32 nr_scratch; |
9f622b2a | 760 | u32 num_event_buffers; |
fae2b904 | 761 | u32 u1u2; |
6c167fc9 | 762 | u32 maximum_speed; |
72246da4 FB |
763 | u32 revision; |
764 | ||
765 | #define DWC3_REVISION_173A 0x5533173a | |
766 | #define DWC3_REVISION_175A 0x5533175a | |
767 | #define DWC3_REVISION_180A 0x5533180a | |
768 | #define DWC3_REVISION_183A 0x5533183a | |
769 | #define DWC3_REVISION_185A 0x5533185a | |
2c61a8ef | 770 | #define DWC3_REVISION_187A 0x5533187a |
72246da4 FB |
771 | #define DWC3_REVISION_188A 0x5533188a |
772 | #define DWC3_REVISION_190A 0x5533190a | |
2c61a8ef | 773 | #define DWC3_REVISION_194A 0x5533194a |
1522d703 FB |
774 | #define DWC3_REVISION_200A 0x5533200a |
775 | #define DWC3_REVISION_202A 0x5533202a | |
776 | #define DWC3_REVISION_210A 0x5533210a | |
777 | #define DWC3_REVISION_220A 0x5533220a | |
7ac6a593 FB |
778 | #define DWC3_REVISION_230A 0x5533230a |
779 | #define DWC3_REVISION_240A 0x5533240a | |
780 | #define DWC3_REVISION_250A 0x5533250a | |
dbf5aaf7 FB |
781 | #define DWC3_REVISION_260A 0x5533260a |
782 | #define DWC3_REVISION_270A 0x5533270a | |
783 | #define DWC3_REVISION_280A 0x5533280a | |
72246da4 | 784 | |
b53c772d | 785 | enum dwc3_ep0_next ep0_next_event; |
72246da4 FB |
786 | enum dwc3_ep0_state ep0state; |
787 | enum dwc3_link_state link_state; | |
72246da4 | 788 | |
c12a0d86 | 789 | u16 isoch_delay; |
865e09e7 FB |
790 | u16 u2sel; |
791 | u16 u2pel; | |
792 | u8 u1sel; | |
793 | u8 u1pel; | |
794 | ||
72246da4 | 795 | u8 speed; |
865e09e7 | 796 | |
789451f6 FB |
797 | u8 num_out_eps; |
798 | u8 num_in_eps; | |
799 | ||
72246da4 FB |
800 | void *mem; |
801 | ||
a3299499 | 802 | struct dwc3_hwparams hwparams; |
72246da4 | 803 | struct dentry *root; |
d7668024 | 804 | struct debugfs_regset32 *regset; |
3b637367 GC |
805 | |
806 | u8 test_mode; | |
807 | u8 test_mode_nr; | |
80caf7d2 | 808 | u8 lpm_nyet_threshold; |
460d098c | 809 | u8 hird_threshold; |
f2b685d5 FB |
810 | |
811 | unsigned delayed_status:1; | |
812 | unsigned ep0_bounced:1; | |
813 | unsigned ep0_expect_in:1; | |
81bc5599 | 814 | unsigned has_hibernation:1; |
80caf7d2 | 815 | unsigned has_lpm_erratum:1; |
460d098c | 816 | unsigned is_utmi_l1_suspend:1; |
946bd579 | 817 | unsigned is_fpga:1; |
f2b685d5 FB |
818 | unsigned needs_fifo_resize:1; |
819 | unsigned pullups_connected:1; | |
820 | unsigned resize_fifos:1; | |
821 | unsigned setup_packet_pending:1; | |
822 | unsigned start_config_issued:1; | |
823 | unsigned three_stage_setup:1; | |
eac68e8f | 824 | unsigned usb3_lpm_capable:1; |
3b81221a HR |
825 | |
826 | unsigned disable_scramble_quirk:1; | |
9a5b2f31 | 827 | unsigned u2exit_lfps_quirk:1; |
b5a65c40 | 828 | unsigned u2ss_inp3_quirk:1; |
df31f5b3 | 829 | unsigned req_p1p2p3_quirk:1; |
a2a1d0f5 | 830 | unsigned del_p1p2p3_quirk:1; |
41c06ffd | 831 | unsigned del_phy_power_chg_quirk:1; |
fb67afca | 832 | unsigned lfps_filter_quirk:1; |
14f4ac53 | 833 | unsigned rx_detect_poll_quirk:1; |
59acfa20 | 834 | unsigned dis_u3_susphy_quirk:1; |
0effe0a3 | 835 | unsigned dis_u2_susphy_quirk:1; |
6b6a0c9a HR |
836 | |
837 | unsigned tx_de_emphasis_quirk:1; | |
838 | unsigned tx_de_emphasis:2; | |
72246da4 FB |
839 | }; |
840 | ||
841 | /* -------------------------------------------------------------------------- */ | |
842 | ||
72246da4 FB |
843 | /* -------------------------------------------------------------------------- */ |
844 | ||
845 | struct dwc3_event_type { | |
846 | u32 is_devspec:1; | |
1974d494 HR |
847 | u32 type:7; |
848 | u32 reserved8_31:24; | |
72246da4 FB |
849 | } __packed; |
850 | ||
851 | #define DWC3_DEPEVT_XFERCOMPLETE 0x01 | |
852 | #define DWC3_DEPEVT_XFERINPROGRESS 0x02 | |
853 | #define DWC3_DEPEVT_XFERNOTREADY 0x03 | |
854 | #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 | |
855 | #define DWC3_DEPEVT_STREAMEVT 0x06 | |
856 | #define DWC3_DEPEVT_EPCMDCMPLT 0x07 | |
857 | ||
858 | /** | |
859 | * struct dwc3_event_depvt - Device Endpoint Events | |
860 | * @one_bit: indicates this is an endpoint event (not used) | |
861 | * @endpoint_number: number of the endpoint | |
862 | * @endpoint_event: The event we have: | |
863 | * 0x00 - Reserved | |
864 | * 0x01 - XferComplete | |
865 | * 0x02 - XferInProgress | |
866 | * 0x03 - XferNotReady | |
867 | * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) | |
868 | * 0x05 - Reserved | |
869 | * 0x06 - StreamEvt | |
870 | * 0x07 - EPCmdCmplt | |
871 | * @reserved11_10: Reserved, don't use. | |
872 | * @status: Indicates the status of the event. Refer to databook for | |
873 | * more information. | |
874 | * @parameters: Parameters of the current event. Refer to databook for | |
875 | * more information. | |
876 | */ | |
877 | struct dwc3_event_depevt { | |
878 | u32 one_bit:1; | |
879 | u32 endpoint_number:5; | |
880 | u32 endpoint_event:4; | |
881 | u32 reserved11_10:2; | |
882 | u32 status:4; | |
40aa41fb FB |
883 | |
884 | /* Within XferNotReady */ | |
885 | #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) | |
886 | ||
887 | /* Within XferComplete */ | |
1d046793 PZ |
888 | #define DEPEVT_STATUS_BUSERR (1 << 0) |
889 | #define DEPEVT_STATUS_SHORT (1 << 1) | |
890 | #define DEPEVT_STATUS_IOC (1 << 2) | |
72246da4 | 891 | #define DEPEVT_STATUS_LST (1 << 3) |
dc137f01 | 892 | |
879631aa FB |
893 | /* Stream event only */ |
894 | #define DEPEVT_STREAMEVT_FOUND 1 | |
895 | #define DEPEVT_STREAMEVT_NOTFOUND 2 | |
896 | ||
dc137f01 | 897 | /* Control-only Status */ |
dc137f01 FB |
898 | #define DEPEVT_STATUS_CONTROL_DATA 1 |
899 | #define DEPEVT_STATUS_CONTROL_STATUS 2 | |
900 | ||
72246da4 FB |
901 | u32 parameters:16; |
902 | } __packed; | |
903 | ||
904 | /** | |
905 | * struct dwc3_event_devt - Device Events | |
906 | * @one_bit: indicates this is a non-endpoint event (not used) | |
907 | * @device_event: indicates it's a device event. Should read as 0x00 | |
908 | * @type: indicates the type of device event. | |
909 | * 0 - DisconnEvt | |
910 | * 1 - USBRst | |
911 | * 2 - ConnectDone | |
912 | * 3 - ULStChng | |
913 | * 4 - WkUpEvt | |
914 | * 5 - Reserved | |
915 | * 6 - EOPF | |
916 | * 7 - SOF | |
917 | * 8 - Reserved | |
918 | * 9 - ErrticErr | |
919 | * 10 - CmdCmplt | |
920 | * 11 - EvntOverflow | |
921 | * 12 - VndrDevTstRcved | |
922 | * @reserved15_12: Reserved, not used | |
923 | * @event_info: Information about this event | |
06f9b6e5 | 924 | * @reserved31_25: Reserved, not used |
72246da4 FB |
925 | */ |
926 | struct dwc3_event_devt { | |
927 | u32 one_bit:1; | |
928 | u32 device_event:7; | |
929 | u32 type:4; | |
930 | u32 reserved15_12:4; | |
06f9b6e5 HR |
931 | u32 event_info:9; |
932 | u32 reserved31_25:7; | |
72246da4 FB |
933 | } __packed; |
934 | ||
935 | /** | |
936 | * struct dwc3_event_gevt - Other Core Events | |
937 | * @one_bit: indicates this is a non-endpoint event (not used) | |
938 | * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. | |
939 | * @phy_port_number: self-explanatory | |
940 | * @reserved31_12: Reserved, not used. | |
941 | */ | |
942 | struct dwc3_event_gevt { | |
943 | u32 one_bit:1; | |
944 | u32 device_event:7; | |
945 | u32 phy_port_number:4; | |
946 | u32 reserved31_12:20; | |
947 | } __packed; | |
948 | ||
949 | /** | |
950 | * union dwc3_event - representation of Event Buffer contents | |
951 | * @raw: raw 32-bit event | |
952 | * @type: the type of the event | |
953 | * @depevt: Device Endpoint Event | |
954 | * @devt: Device Event | |
955 | * @gevt: Global Event | |
956 | */ | |
957 | union dwc3_event { | |
958 | u32 raw; | |
959 | struct dwc3_event_type type; | |
960 | struct dwc3_event_depevt depevt; | |
961 | struct dwc3_event_devt devt; | |
962 | struct dwc3_event_gevt gevt; | |
963 | }; | |
964 | ||
61018305 FB |
965 | /** |
966 | * struct dwc3_gadget_ep_cmd_params - representation of endpoint command | |
967 | * parameters | |
968 | * @param2: third parameter | |
969 | * @param1: second parameter | |
970 | * @param0: first parameter | |
971 | */ | |
972 | struct dwc3_gadget_ep_cmd_params { | |
973 | u32 param2; | |
974 | u32 param1; | |
975 | u32 param0; | |
976 | }; | |
977 | ||
72246da4 FB |
978 | /* |
979 | * DWC3 Features to be used as Driver Data | |
980 | */ | |
981 | ||
982 | #define DWC3_HAS_PERIPHERAL BIT(0) | |
983 | #define DWC3_HAS_XHCI BIT(1) | |
984 | #define DWC3_HAS_OTG BIT(3) | |
985 | ||
d07e8819 | 986 | /* prototypes */ |
3140e8cb | 987 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode); |
457e84b6 | 988 | int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); |
3140e8cb | 989 | |
388e5c51 | 990 | #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
d07e8819 FB |
991 | int dwc3_host_init(struct dwc3 *dwc); |
992 | void dwc3_host_exit(struct dwc3 *dwc); | |
388e5c51 VG |
993 | #else |
994 | static inline int dwc3_host_init(struct dwc3 *dwc) | |
995 | { return 0; } | |
996 | static inline void dwc3_host_exit(struct dwc3 *dwc) | |
997 | { } | |
998 | #endif | |
999 | ||
1000 | #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) | |
f80b45e7 FB |
1001 | int dwc3_gadget_init(struct dwc3 *dwc); |
1002 | void dwc3_gadget_exit(struct dwc3 *dwc); | |
61018305 FB |
1003 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); |
1004 | int dwc3_gadget_get_link_state(struct dwc3 *dwc); | |
1005 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); | |
1006 | int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, | |
1007 | unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); | |
3ece0ec4 | 1008 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); |
388e5c51 VG |
1009 | #else |
1010 | static inline int dwc3_gadget_init(struct dwc3 *dwc) | |
1011 | { return 0; } | |
1012 | static inline void dwc3_gadget_exit(struct dwc3 *dwc) | |
1013 | { } | |
61018305 FB |
1014 | static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) |
1015 | { return 0; } | |
1016 | static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
1017 | { return 0; } | |
1018 | static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, | |
1019 | enum dwc3_link_state state) | |
1020 | { return 0; } | |
1021 | ||
1022 | static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, | |
1023 | unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) | |
1024 | { return 0; } | |
1025 | static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, | |
1026 | int cmd, u32 param) | |
1027 | { return 0; } | |
388e5c51 | 1028 | #endif |
f80b45e7 | 1029 | |
7415f17c FB |
1030 | /* power management interface */ |
1031 | #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) | |
7415f17c FB |
1032 | int dwc3_gadget_suspend(struct dwc3 *dwc); |
1033 | int dwc3_gadget_resume(struct dwc3 *dwc); | |
1034 | #else | |
7415f17c FB |
1035 | static inline int dwc3_gadget_suspend(struct dwc3 *dwc) |
1036 | { | |
1037 | return 0; | |
1038 | } | |
1039 | ||
1040 | static inline int dwc3_gadget_resume(struct dwc3 *dwc) | |
1041 | { | |
1042 | return 0; | |
1043 | } | |
1044 | #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ | |
1045 | ||
72246da4 | 1046 | #endif /* __DRIVERS_USB_DWC3_CORE_H */ |