projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 72246da4 FB |
1 | /** |
| 2 | * core.h - DesignWare USB3 DRD Core Header | |
| 3 | * | |
| 4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
| 72246da4 FB |
5 | * |
| 6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
| 7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
| 8 | * | |
| 9 | * Redistribution and use in source and binary forms, with or without | |
| 10 | * modification, are permitted provided that the following conditions | |
| 11 | * are met: | |
| 12 | * 1. Redistributions of source code must retain the above copyright | |
| 13 | * notice, this list of conditions, and the following disclaimer, | |
| 14 | * without modification. | |
| 15 | * 2. Redistributions in binary form must reproduce the above copyright | |
| 16 | * notice, this list of conditions and the following disclaimer in the | |
| 17 | * documentation and/or other materials provided with the distribution. | |
| 18 | * 3. The names of the above-listed copyright holders may not be used | |
| 19 | * to endorse or promote products derived from this software without | |
| 20 | * specific prior written permission. | |
| 21 | * | |
| 22 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
| 23 | * GNU General Public License ("GPL") version 2, as published by the Free | |
| 24 | * Software Foundation. | |
| 25 | * | |
| 26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
| 27 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
| 28 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
| 29 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
| 30 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
| 31 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
| 32 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
| 33 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
| 34 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
| 35 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
| 36 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 37 | */ | |
| 38 | ||
| 39 | #ifndef __DRIVERS_USB_DWC3_CORE_H | |
| 40 | #define __DRIVERS_USB_DWC3_CORE_H | |
| 41 | ||
| 42 | #include <linux/device.h> | |
| 43 | #include <linux/spinlock.h> | |
| d07e8819 | 44 | #include <linux/ioport.h> |
| 72246da4 FB |
45 | #include <linux/list.h> |
| 46 | #include <linux/dma-mapping.h> | |
| 47 | #include <linux/mm.h> | |
| 48 | #include <linux/debugfs.h> | |
| 49 | ||
| 50 | #include <linux/usb/ch9.h> | |
| 51 | #include <linux/usb/gadget.h> | |
| 52 | ||
| 53 | /* Global constants */ | |
| 54 | #define DWC3_ENDPOINTS_NUM 32 | |
| 51249dca | 55 | #define DWC3_XHCI_RESOURCES_NUM 2 |
| 72246da4 | 56 | |
| 72246da4 FB |
57 | #define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE |
| 58 | #define DWC3_EVENT_TYPE_MASK 0xfe | |
| 59 | ||
| 60 | #define DWC3_EVENT_TYPE_DEV 0 | |
| 61 | #define DWC3_EVENT_TYPE_CARKIT 3 | |
| 62 | #define DWC3_EVENT_TYPE_I2C 4 | |
| 63 | ||
| 64 | #define DWC3_DEVICE_EVENT_DISCONNECT 0 | |
| 65 | #define DWC3_DEVICE_EVENT_RESET 1 | |
| 66 | #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 | |
| 67 | #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 | |
| 68 | #define DWC3_DEVICE_EVENT_WAKEUP 4 | |
| 69 | #define DWC3_DEVICE_EVENT_EOPF 6 | |
| 70 | #define DWC3_DEVICE_EVENT_SOF 7 | |
| 71 | #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 | |
| 72 | #define DWC3_DEVICE_EVENT_CMD_CMPL 10 | |
| 73 | #define DWC3_DEVICE_EVENT_OVERFLOW 11 | |
| 74 | ||
| 75 | #define DWC3_GEVNTCOUNT_MASK 0xfffc | |
| 76 | #define DWC3_GSNPSID_MASK 0xffff0000 | |
| 77 | #define DWC3_GSNPSREV_MASK 0xffff | |
| 78 | ||
| 51249dca IS |
79 | /* DWC3 registers memory space boundries */ |
| 80 | #define DWC3_XHCI_REGS_START 0x0 | |
| 81 | #define DWC3_XHCI_REGS_END 0x7fff | |
| 82 | #define DWC3_GLOBALS_REGS_START 0xc100 | |
| 83 | #define DWC3_GLOBALS_REGS_END 0xc6ff | |
| 84 | #define DWC3_DEVICE_REGS_START 0xc700 | |
| 85 | #define DWC3_DEVICE_REGS_END 0xcbff | |
| 86 | #define DWC3_OTG_REGS_START 0xcc00 | |
| 87 | #define DWC3_OTG_REGS_END 0xccff | |
| 88 | ||
| 72246da4 FB |
89 | /* Global Registers */ |
| 90 | #define DWC3_GSBUSCFG0 0xc100 | |
| 91 | #define DWC3_GSBUSCFG1 0xc104 | |
| 92 | #define DWC3_GTXTHRCFG 0xc108 | |
| 93 | #define DWC3_GRXTHRCFG 0xc10c | |
| 94 | #define DWC3_GCTL 0xc110 | |
| 95 | #define DWC3_GEVTEN 0xc114 | |
| 96 | #define DWC3_GSTS 0xc118 | |
| 97 | #define DWC3_GSNPSID 0xc120 | |
| 98 | #define DWC3_GGPIO 0xc124 | |
| 99 | #define DWC3_GUID 0xc128 | |
| 100 | #define DWC3_GUCTL 0xc12c | |
| 101 | #define DWC3_GBUSERRADDR0 0xc130 | |
| 102 | #define DWC3_GBUSERRADDR1 0xc134 | |
| 103 | #define DWC3_GPRTBIMAP0 0xc138 | |
| 104 | #define DWC3_GPRTBIMAP1 0xc13c | |
| 105 | #define DWC3_GHWPARAMS0 0xc140 | |
| 106 | #define DWC3_GHWPARAMS1 0xc144 | |
| 107 | #define DWC3_GHWPARAMS2 0xc148 | |
| 108 | #define DWC3_GHWPARAMS3 0xc14c | |
| 109 | #define DWC3_GHWPARAMS4 0xc150 | |
| 110 | #define DWC3_GHWPARAMS5 0xc154 | |
| 111 | #define DWC3_GHWPARAMS6 0xc158 | |
| 112 | #define DWC3_GHWPARAMS7 0xc15c | |
| 113 | #define DWC3_GDBGFIFOSPACE 0xc160 | |
| 114 | #define DWC3_GDBGLTSSM 0xc164 | |
| 115 | #define DWC3_GPRTBIMAP_HS0 0xc180 | |
| 116 | #define DWC3_GPRTBIMAP_HS1 0xc184 | |
| 117 | #define DWC3_GPRTBIMAP_FS0 0xc188 | |
| 118 | #define DWC3_GPRTBIMAP_FS1 0xc18c | |
| 119 | ||
| 120 | #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) | |
| 121 | #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) | |
| 122 | ||
| 123 | #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) | |
| 124 | ||
| 125 | #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) | |
| 126 | ||
| 127 | #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) | |
| 128 | #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) | |
| 129 | ||
| 130 | #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) | |
| 131 | #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) | |
| 132 | #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) | |
| 133 | #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) | |
| 134 | ||
| 135 | #define DWC3_GHWPARAMS8 0xc600 | |
| 136 | ||
| 137 | /* Device Registers */ | |
| 138 | #define DWC3_DCFG 0xc700 | |
| 139 | #define DWC3_DCTL 0xc704 | |
| 140 | #define DWC3_DEVTEN 0xc708 | |
| 141 | #define DWC3_DSTS 0xc70c | |
| 142 | #define DWC3_DGCMDPAR 0xc710 | |
| 143 | #define DWC3_DGCMD 0xc714 | |
| 144 | #define DWC3_DALEPENA 0xc720 | |
| 145 | #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) | |
| 146 | #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) | |
| 147 | #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) | |
| 148 | #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) | |
| 149 | ||
| 150 | /* OTG Registers */ | |
| 151 | #define DWC3_OCFG 0xcc00 | |
| 152 | #define DWC3_OCTL 0xcc04 | |
| 153 | #define DWC3_OEVTEN 0xcc08 | |
| 154 | #define DWC3_OSTS 0xcc0C | |
| 155 | ||
| 156 | /* Bit fields */ | |
| 157 | ||
| 158 | /* Global Configuration Register */ | |
| 1d046793 | 159 | #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) |
| f4aadbe4 | 160 | #define DWC3_GCTL_U2RSTECN (1 << 16) |
| 1d046793 | 161 | #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) |
| 72246da4 FB |
162 | #define DWC3_GCTL_CLK_BUS (0) |
| 163 | #define DWC3_GCTL_CLK_PIPE (1) | |
| 164 | #define DWC3_GCTL_CLK_PIPEHALF (2) | |
| 165 | #define DWC3_GCTL_CLK_MASK (3) | |
| 166 | ||
| 0b9fe32d | 167 | #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) |
| 1d046793 | 168 | #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) |
| 72246da4 FB |
169 | #define DWC3_GCTL_PRTCAP_HOST 1 |
| 170 | #define DWC3_GCTL_PRTCAP_DEVICE 2 | |
| 171 | #define DWC3_GCTL_PRTCAP_OTG 3 | |
| 172 | ||
| 173 | #define DWC3_GCTL_CORESOFTRESET (1 << 11) | |
| 1d046793 | 174 | #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) |
| 3e87c42a | 175 | #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) |
| 72246da4 | 176 | #define DWC3_GCTL_DISSCRAMBLE (1 << 3) |
| aabb7075 | 177 | #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) |
| 72246da4 FB |
178 | |
| 179 | /* Global USB2 PHY Configuration Register */ | |
| 180 | #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) | |
| 181 | #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) | |
| 182 | ||
| 183 | /* Global USB3 PIPE Control Register */ | |
| 184 | #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) | |
| 185 | #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) | |
| 186 | ||
| 457e84b6 FB |
187 | /* Global TX Fifo Size Register */ |
| 188 | #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) | |
| 189 | #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) | |
| 190 | ||
| aabb7075 | 191 | /* Global HWPARAMS1 Register */ |
| 1d046793 | 192 | #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) |
| aabb7075 FB |
193 | #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 |
| 194 | #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 | |
| 195 | ||
| 72246da4 FB |
196 | /* Device Configuration Register */ |
| 197 | #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) | |
| 198 | #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) | |
| 199 | ||
| 200 | #define DWC3_DCFG_SPEED_MASK (7 << 0) | |
| 201 | #define DWC3_DCFG_SUPERSPEED (4 << 0) | |
| 202 | #define DWC3_DCFG_HIGHSPEED (0 << 0) | |
| 203 | #define DWC3_DCFG_FULLSPEED2 (1 << 0) | |
| 204 | #define DWC3_DCFG_LOWSPEED (2 << 0) | |
| 205 | #define DWC3_DCFG_FULLSPEED1 (3 << 0) | |
| 206 | ||
| 207 | /* Device Control Register */ | |
| 208 | #define DWC3_DCTL_RUN_STOP (1 << 31) | |
| 209 | #define DWC3_DCTL_CSFTRST (1 << 30) | |
| 210 | #define DWC3_DCTL_LSFTRST (1 << 29) | |
| 211 | ||
| 212 | #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) | |
| 213 | #define DWC3_DCTL_HIRD_THRES(n) (((n) & DWC3_DCTL_HIRD_THRES_MASK) >> 24) | |
| 214 | ||
| 215 | #define DWC3_DCTL_APPL1RES (1 << 23) | |
| 216 | ||
| 8db7ed15 FB |
217 | #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) |
| 218 | #define DWC3_DCTL_TRGTULST(n) ((n) << 17) | |
| 219 | ||
| 220 | #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) | |
| 221 | #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) | |
| 222 | #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) | |
| 223 | #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) | |
| 224 | #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) | |
| 225 | ||
| 72246da4 FB |
226 | #define DWC3_DCTL_INITU2ENA (1 << 12) |
| 227 | #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) | |
| 228 | #define DWC3_DCTL_INITU1ENA (1 << 10) | |
| 229 | #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) | |
| 230 | #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) | |
| 231 | ||
| 232 | #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) | |
| 233 | #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) | |
| 234 | ||
| 235 | #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) | |
| 236 | #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) | |
| 237 | #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) | |
| 238 | #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) | |
| 239 | #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) | |
| 240 | #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) | |
| 241 | #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) | |
| 242 | ||
| 243 | /* Device Event Enable Register */ | |
| 244 | #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) | |
| 245 | #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) | |
| 246 | #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) | |
| 247 | #define DWC3_DEVTEN_ERRTICERREN (1 << 9) | |
| 248 | #define DWC3_DEVTEN_SOFEN (1 << 7) | |
| 249 | #define DWC3_DEVTEN_EOPFEN (1 << 6) | |
| 250 | #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) | |
| 251 | #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) | |
| 252 | #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) | |
| 253 | #define DWC3_DEVTEN_USBRSTEN (1 << 1) | |
| 254 | #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) | |
| 255 | ||
| 256 | /* Device Status Register */ | |
| 257 | #define DWC3_DSTS_PWRUPREQ (1 << 24) | |
| 258 | #define DWC3_DSTS_COREIDLE (1 << 23) | |
| 259 | #define DWC3_DSTS_DEVCTRLHLT (1 << 22) | |
| 260 | ||
| 261 | #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) | |
| 262 | #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) | |
| 263 | ||
| 264 | #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) | |
| 265 | ||
| 266 | #define DWC3_DSTS_SOFFN_MASK (0x3ff << 3) | |
| 267 | #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) | |
| 268 | ||
| 269 | #define DWC3_DSTS_CONNECTSPD (7 << 0) | |
| 270 | ||
| 271 | #define DWC3_DSTS_SUPERSPEED (4 << 0) | |
| 272 | #define DWC3_DSTS_HIGHSPEED (0 << 0) | |
| 273 | #define DWC3_DSTS_FULLSPEED2 (1 << 0) | |
| 274 | #define DWC3_DSTS_LOWSPEED (2 << 0) | |
| 275 | #define DWC3_DSTS_FULLSPEED1 (3 << 0) | |
| 276 | ||
| 277 | /* Device Generic Command Register */ | |
| 278 | #define DWC3_DGCMD_SET_LMP 0x01 | |
| 279 | #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 | |
| 280 | #define DWC3_DGCMD_XMIT_FUNCTION 0x03 | |
| 281 | #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 | |
| 282 | #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a | |
| 283 | #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c | |
| 284 | #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 | |
| 285 | ||
| 286 | /* Device Endpoint Command Register */ | |
| 287 | #define DWC3_DEPCMD_PARAM_SHIFT 16 | |
| 1d046793 PZ |
288 | #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) |
| 289 | #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) | |
| 72246da4 | 290 | #define DWC3_DEPCMD_STATUS_MASK (0x0f << 12) |
| 1d046793 | 291 | #define DWC3_DEPCMD_STATUS(x) (((x) & DWC3_DEPCMD_STATUS_MASK) >> 12) |
| 72246da4 FB |
292 | #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) |
| 293 | #define DWC3_DEPCMD_CMDACT (1 << 10) | |
| 294 | #define DWC3_DEPCMD_CMDIOC (1 << 8) | |
| 295 | ||
| 296 | #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) | |
| 297 | #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) | |
| 298 | #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) | |
| 299 | #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) | |
| 300 | #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) | |
| 301 | #define DWC3_DEPCMD_SETSTALL (0x04 << 0) | |
| 302 | #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) | |
| 303 | #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) | |
| 304 | #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) | |
| 305 | ||
| 306 | /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ | |
| 307 | #define DWC3_DALEPENA_EP(n) (1 << n) | |
| 308 | ||
| 309 | #define DWC3_DEPCMD_TYPE_CONTROL 0 | |
| 310 | #define DWC3_DEPCMD_TYPE_ISOC 1 | |
| 311 | #define DWC3_DEPCMD_TYPE_BULK 2 | |
| 312 | #define DWC3_DEPCMD_TYPE_INTR 3 | |
| 313 | ||
| 314 | /* Structures */ | |
| 315 | ||
| f6bafc6a | 316 | struct dwc3_trb; |
| 72246da4 FB |
317 | |
| 318 | /** | |
| 319 | * struct dwc3_event_buffer - Software event buffer representation | |
| 320 | * @list: a list of event buffers | |
| 321 | * @buf: _THE_ buffer | |
| 322 | * @length: size of this buffer | |
| 323 | * @dma: dma_addr_t | |
| 324 | * @dwc: pointer to DWC controller | |
| 325 | */ | |
| 326 | struct dwc3_event_buffer { | |
| 327 | void *buf; | |
| 328 | unsigned length; | |
| 329 | unsigned int lpos; | |
| 330 | ||
| 331 | dma_addr_t dma; | |
| 332 | ||
| 333 | struct dwc3 *dwc; | |
| 334 | }; | |
| 335 | ||
| 336 | #define DWC3_EP_FLAG_STALLED (1 << 0) | |
| 337 | #define DWC3_EP_FLAG_WEDGED (1 << 1) | |
| 338 | ||
| 339 | #define DWC3_EP_DIRECTION_TX true | |
| 340 | #define DWC3_EP_DIRECTION_RX false | |
| 341 | ||
| 342 | #define DWC3_TRB_NUM 32 | |
| 343 | #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) | |
| 344 | ||
| 345 | /** | |
| 346 | * struct dwc3_ep - device side endpoint representation | |
| 347 | * @endpoint: usb endpoint | |
| 348 | * @request_list: list of requests for this endpoint | |
| 349 | * @req_queued: list of requests on this ep which have TRBs setup | |
| 350 | * @trb_pool: array of transaction buffers | |
| 351 | * @trb_pool_dma: dma address of @trb_pool | |
| 352 | * @free_slot: next slot which is going to be used | |
| 353 | * @busy_slot: first slot which is owned by HW | |
| 354 | * @desc: usb_endpoint_descriptor pointer | |
| 355 | * @dwc: pointer to DWC controller | |
| 356 | * @flags: endpoint flags (wedged, stalled, ...) | |
| 357 | * @current_trb: index of current used trb | |
| 358 | * @number: endpoint number (1 - 15) | |
| 359 | * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK | |
| 360 | * @res_trans_idx: Resource transfer index | |
| 361 | * @interval: the intervall on which the ISOC transfer is started | |
| 362 | * @name: a human readable name e.g. ep1out-bulk | |
| 363 | * @direction: true for TX, false for RX | |
| 879631aa | 364 | * @stream_capable: true when streams are enabled |
| 72246da4 FB |
365 | */ |
| 366 | struct dwc3_ep { | |
| 367 | struct usb_ep endpoint; | |
| 368 | struct list_head request_list; | |
| 369 | struct list_head req_queued; | |
| 370 | ||
| f6bafc6a | 371 | struct dwc3_trb *trb_pool; |
| 72246da4 FB |
372 | dma_addr_t trb_pool_dma; |
| 373 | u32 free_slot; | |
| 374 | u32 busy_slot; | |
| 375 | const struct usb_endpoint_descriptor *desc; | |
| c90bfaec | 376 | const struct usb_ss_ep_comp_descriptor *comp_desc; |
| 72246da4 FB |
377 | struct dwc3 *dwc; |
| 378 | ||
| 379 | unsigned flags; | |
| 380 | #define DWC3_EP_ENABLED (1 << 0) | |
| 381 | #define DWC3_EP_STALL (1 << 1) | |
| 382 | #define DWC3_EP_WEDGE (1 << 2) | |
| 383 | #define DWC3_EP_BUSY (1 << 4) | |
| 384 | #define DWC3_EP_PENDING_REQUEST (1 << 5) | |
| 72246da4 | 385 | |
| 984f66a6 FB |
386 | /* This last one is specific to EP0 */ |
| 387 | #define DWC3_EP0_DIR_IN (1 << 31) | |
| 388 | ||
| 72246da4 FB |
389 | unsigned current_trb; |
| 390 | ||
| 391 | u8 number; | |
| 392 | u8 type; | |
| 393 | u8 res_trans_idx; | |
| 394 | u32 interval; | |
| 395 | ||
| 396 | char name[20]; | |
| 397 | ||
| 398 | unsigned direction:1; | |
| 879631aa | 399 | unsigned stream_capable:1; |
| 72246da4 FB |
400 | }; |
| 401 | ||
| 402 | enum dwc3_phy { | |
| 403 | DWC3_PHY_UNKNOWN = 0, | |
| 404 | DWC3_PHY_USB3, | |
| 405 | DWC3_PHY_USB2, | |
| 406 | }; | |
| 407 | ||
| b53c772d FB |
408 | enum dwc3_ep0_next { |
| 409 | DWC3_EP0_UNKNOWN = 0, | |
| 410 | DWC3_EP0_COMPLETE, | |
| 411 | DWC3_EP0_NRDY_SETUP, | |
| 412 | DWC3_EP0_NRDY_DATA, | |
| 413 | DWC3_EP0_NRDY_STATUS, | |
| 414 | }; | |
| 415 | ||
| 72246da4 FB |
416 | enum dwc3_ep0_state { |
| 417 | EP0_UNCONNECTED = 0, | |
| c7fcdeb2 FB |
418 | EP0_SETUP_PHASE, |
| 419 | EP0_DATA_PHASE, | |
| 420 | EP0_STATUS_PHASE, | |
| 72246da4 FB |
421 | }; |
| 422 | ||
| 423 | enum dwc3_link_state { | |
| 424 | /* In SuperSpeed */ | |
| 425 | DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ | |
| 426 | DWC3_LINK_STATE_U1 = 0x01, | |
| 427 | DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ | |
| 428 | DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ | |
| 429 | DWC3_LINK_STATE_SS_DIS = 0x04, | |
| 430 | DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ | |
| 431 | DWC3_LINK_STATE_SS_INACT = 0x06, | |
| 432 | DWC3_LINK_STATE_POLL = 0x07, | |
| 433 | DWC3_LINK_STATE_RECOV = 0x08, | |
| 434 | DWC3_LINK_STATE_HRESET = 0x09, | |
| 435 | DWC3_LINK_STATE_CMPLY = 0x0a, | |
| 436 | DWC3_LINK_STATE_LPBK = 0x0b, | |
| 437 | DWC3_LINK_STATE_MASK = 0x0f, | |
| 438 | }; | |
| 439 | ||
| 440 | enum dwc3_device_state { | |
| 441 | DWC3_DEFAULT_STATE, | |
| 442 | DWC3_ADDRESS_STATE, | |
| 443 | DWC3_CONFIGURED_STATE, | |
| 444 | }; | |
| 445 | ||
| f6bafc6a FB |
446 | /* TRB Length, PCM and Status */ |
| 447 | #define DWC3_TRB_SIZE_MASK (0x00ffffff) | |
| 448 | #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) | |
| 449 | #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) | |
| 450 | #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28) >> 28)) | |
| 451 | ||
| 452 | #define DWC3_TRBSTS_OK 0 | |
| 453 | #define DWC3_TRBSTS_MISSED_ISOC 1 | |
| 454 | #define DWC3_TRBSTS_SETUP_PENDING 2 | |
| 455 | ||
| 456 | /* TRB Control */ | |
| 457 | #define DWC3_TRB_CTRL_HWO (1 << 0) | |
| 458 | #define DWC3_TRB_CTRL_LST (1 << 1) | |
| 459 | #define DWC3_TRB_CTRL_CHN (1 << 2) | |
| 460 | #define DWC3_TRB_CTRL_CSP (1 << 3) | |
| 461 | #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) | |
| 462 | #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) | |
| 463 | #define DWC3_TRB_CTRL_IOC (1 << 11) | |
| 464 | #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) | |
| 465 | ||
| 466 | #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) | |
| 467 | #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) | |
| 468 | #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) | |
| 469 | #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) | |
| 470 | #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) | |
| 471 | #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) | |
| 472 | #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) | |
| 473 | #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) | |
| 72246da4 FB |
474 | |
| 475 | /** | |
| f6bafc6a | 476 | * struct dwc3_trb - transfer request block (hw format) |
| 72246da4 FB |
477 | * @bpl: DW0-3 |
| 478 | * @bph: DW4-7 | |
| 479 | * @size: DW8-B | |
| 480 | * @trl: DWC-F | |
| 481 | */ | |
| f6bafc6a FB |
482 | struct dwc3_trb { |
| 483 | u32 bpl; | |
| 484 | u32 bph; | |
| 485 | u32 size; | |
| 486 | u32 ctrl; | |
| 72246da4 FB |
487 | } __packed; |
| 488 | ||
| a3299499 FB |
489 | /** |
| 490 | * dwc3_hwparams - copy of HWPARAMS registers | |
| 491 | * @hwparams0 - GHWPARAMS0 | |
| 492 | * @hwparams1 - GHWPARAMS1 | |
| 493 | * @hwparams2 - GHWPARAMS2 | |
| 494 | * @hwparams3 - GHWPARAMS3 | |
| 495 | * @hwparams4 - GHWPARAMS4 | |
| 496 | * @hwparams5 - GHWPARAMS5 | |
| 497 | * @hwparams6 - GHWPARAMS6 | |
| 498 | * @hwparams7 - GHWPARAMS7 | |
| 499 | * @hwparams8 - GHWPARAMS8 | |
| 500 | */ | |
| 501 | struct dwc3_hwparams { | |
| 502 | u32 hwparams0; | |
| 503 | u32 hwparams1; | |
| 504 | u32 hwparams2; | |
| 505 | u32 hwparams3; | |
| 506 | u32 hwparams4; | |
| 507 | u32 hwparams5; | |
| 508 | u32 hwparams6; | |
| 509 | u32 hwparams7; | |
| 510 | u32 hwparams8; | |
| 511 | }; | |
| 512 | ||
| 0949e99b FB |
513 | /* HWPARAMS0 */ |
| 514 | #define DWC3_MODE(n) ((n) & 0x7) | |
| 515 | ||
| 516 | #define DWC3_MODE_DEVICE 0 | |
| 517 | #define DWC3_MODE_HOST 1 | |
| 518 | #define DWC3_MODE_DRD 2 | |
| 519 | #define DWC3_MODE_HUB 3 | |
| 520 | ||
| 457e84b6 FB |
521 | #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) |
| 522 | ||
| 0949e99b | 523 | /* HWPARAMS1 */ |
| 457e84b6 FB |
524 | #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) |
| 525 | ||
| 526 | /* HWPARAMS7 */ | |
| 527 | #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) | |
| 9f622b2a | 528 | |
| e0ce0b0a SAS |
529 | struct dwc3_request { |
| 530 | struct usb_request request; | |
| 531 | struct list_head list; | |
| 532 | struct dwc3_ep *dep; | |
| 533 | ||
| 534 | u8 epnum; | |
| f6bafc6a | 535 | struct dwc3_trb *trb; |
| e0ce0b0a SAS |
536 | dma_addr_t trb_dma; |
| 537 | ||
| 538 | unsigned direction:1; | |
| 539 | unsigned mapped:1; | |
| 540 | unsigned queued:1; | |
| 541 | }; | |
| 542 | ||
| 72246da4 FB |
543 | /** |
| 544 | * struct dwc3 - representation of our controller | |
| 91db07dc FB |
545 | * @ctrl_req: usb control request which is used for ep0 |
| 546 | * @ep0_trb: trb which is used for the ctrl_req | |
| 5812b1c2 | 547 | * @ep0_bounce: bounce buffer for ep0 |
| 91db07dc FB |
548 | * @setup_buf: used while precessing STD USB requests |
| 549 | * @ctrl_req_addr: dma address of ctrl_req | |
| 550 | * @ep0_trb: dma address of ep0_trb | |
| 551 | * @ep0_usb_req: dummy req used while handling STD USB requests | |
| 5812b1c2 | 552 | * @ep0_bounce_addr: dma address of ep0_bounce |
| 72246da4 FB |
553 | * @lock: for synchronizing |
| 554 | * @dev: pointer to our struct device | |
| d07e8819 | 555 | * @xhci: pointer to our xHCI child |
| 72246da4 FB |
556 | * @event_buffer_list: a list of event buffers |
| 557 | * @gadget: device side representation of the peripheral controller | |
| 558 | * @gadget_driver: pointer to the gadget driver | |
| 559 | * @regs: base address for our registers | |
| 560 | * @regs_size: address space size | |
| 561 | * @irq: IRQ number | |
| 9f622b2a | 562 | * @num_event_buffers: calculated number of event buffers |
| fae2b904 | 563 | * @u1u2: only used on revisions <1.83a for workaround |
| 6c167fc9 | 564 | * @maximum_speed: maximum speed requested (mainly for testing purposes) |
| 72246da4 | 565 | * @revision: revision register contents |
| 0949e99b | 566 | * @mode: mode of operation |
| 72246da4 FB |
567 | * @is_selfpowered: true when we are selfpowered |
| 568 | * @three_stage_setup: set if we perform a three phase setup | |
| 5812b1c2 | 569 | * @ep0_bounced: true when we used bounce buffer |
| 55f3fba6 | 570 | * @ep0_expect_in: true when we expect a DATA IN transfer |
| b23c8439 | 571 | * @start_config_issued: true when StartConfig command has been issued |
| df62df56 | 572 | * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround |
| 457e84b6 FB |
573 | * @needs_fifo_resize: not all users might want fifo resizing, flag it |
| 574 | * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. | |
| b53c772d | 575 | * @ep0_next_event: hold the next expected event |
| 72246da4 FB |
576 | * @ep0state: state of endpoint zero |
| 577 | * @link_state: link state | |
| 578 | * @speed: device speed (super, high, full, low) | |
| 579 | * @mem: points to start of memory which is used for this struct. | |
| a3299499 | 580 | * @hwparams: copy of hwparams registers |
| 72246da4 FB |
581 | * @root: debugfs root folder pointer |
| 582 | */ | |
| 583 | struct dwc3 { | |
| 584 | struct usb_ctrlrequest *ctrl_req; | |
| f6bafc6a | 585 | struct dwc3_trb *ep0_trb; |
| 5812b1c2 | 586 | void *ep0_bounce; |
| 72246da4 FB |
587 | u8 *setup_buf; |
| 588 | dma_addr_t ctrl_req_addr; | |
| 589 | dma_addr_t ep0_trb_addr; | |
| 5812b1c2 | 590 | dma_addr_t ep0_bounce_addr; |
| e0ce0b0a | 591 | struct dwc3_request ep0_usb_req; |
| 72246da4 FB |
592 | /* device lock */ |
| 593 | spinlock_t lock; | |
| 594 | struct device *dev; | |
| 595 | ||
| d07e8819 | 596 | struct platform_device *xhci; |
| 51249dca | 597 | struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; |
| d07e8819 | 598 | |
| 457d3f21 | 599 | struct dwc3_event_buffer **ev_buffs; |
| 72246da4 FB |
600 | struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; |
| 601 | ||
| 602 | struct usb_gadget gadget; | |
| 603 | struct usb_gadget_driver *gadget_driver; | |
| 604 | ||
| 605 | void __iomem *regs; | |
| 606 | size_t regs_size; | |
| 607 | ||
| 9f622b2a | 608 | u32 num_event_buffers; |
| fae2b904 | 609 | u32 u1u2; |
| 6c167fc9 | 610 | u32 maximum_speed; |
| 72246da4 | 611 | u32 revision; |
| 0949e99b | 612 | u32 mode; |
| 72246da4 FB |
613 | |
| 614 | #define DWC3_REVISION_173A 0x5533173a | |
| 615 | #define DWC3_REVISION_175A 0x5533175a | |
| 616 | #define DWC3_REVISION_180A 0x5533180a | |
| 617 | #define DWC3_REVISION_183A 0x5533183a | |
| 618 | #define DWC3_REVISION_185A 0x5533185a | |
| 619 | #define DWC3_REVISION_188A 0x5533188a | |
| 620 | #define DWC3_REVISION_190A 0x5533190a | |
| 1522d703 FB |
621 | #define DWC3_REVISION_200A 0x5533200a |
| 622 | #define DWC3_REVISION_202A 0x5533202a | |
| 623 | #define DWC3_REVISION_210A 0x5533210a | |
| 624 | #define DWC3_REVISION_220A 0x5533220a | |
| 72246da4 FB |
625 | |
| 626 | unsigned is_selfpowered:1; | |
| 627 | unsigned three_stage_setup:1; | |
| 5812b1c2 | 628 | unsigned ep0_bounced:1; |
| 55f3fba6 | 629 | unsigned ep0_expect_in:1; |
| b23c8439 | 630 | unsigned start_config_issued:1; |
| df62df56 | 631 | unsigned setup_packet_pending:1; |
| 5bdb1dcc | 632 | unsigned delayed_status:1; |
| 457e84b6 FB |
633 | unsigned needs_fifo_resize:1; |
| 634 | unsigned resize_fifos:1; | |
| 72246da4 | 635 | |
| b53c772d | 636 | enum dwc3_ep0_next ep0_next_event; |
| 72246da4 FB |
637 | enum dwc3_ep0_state ep0state; |
| 638 | enum dwc3_link_state link_state; | |
| 639 | enum dwc3_device_state dev_state; | |
| 640 | ||
| 641 | u8 speed; | |
| 642 | void *mem; | |
| 643 | ||
| a3299499 | 644 | struct dwc3_hwparams hwparams; |
| 72246da4 | 645 | struct dentry *root; |
| 3b637367 GC |
646 | |
| 647 | u8 test_mode; | |
| 648 | u8 test_mode_nr; | |
| 72246da4 FB |
649 | }; |
| 650 | ||
| 651 | /* -------------------------------------------------------------------------- */ | |
| 652 | ||
| 72246da4 FB |
653 | /* -------------------------------------------------------------------------- */ |
| 654 | ||
| 655 | struct dwc3_event_type { | |
| 656 | u32 is_devspec:1; | |
| 657 | u32 type:6; | |
| 658 | u32 reserved8_31:25; | |
| 659 | } __packed; | |
| 660 | ||
| 661 | #define DWC3_DEPEVT_XFERCOMPLETE 0x01 | |
| 662 | #define DWC3_DEPEVT_XFERINPROGRESS 0x02 | |
| 663 | #define DWC3_DEPEVT_XFERNOTREADY 0x03 | |
| 664 | #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 | |
| 665 | #define DWC3_DEPEVT_STREAMEVT 0x06 | |
| 666 | #define DWC3_DEPEVT_EPCMDCMPLT 0x07 | |
| 667 | ||
| 668 | /** | |
| 669 | * struct dwc3_event_depvt - Device Endpoint Events | |
| 670 | * @one_bit: indicates this is an endpoint event (not used) | |
| 671 | * @endpoint_number: number of the endpoint | |
| 672 | * @endpoint_event: The event we have: | |
| 673 | * 0x00 - Reserved | |
| 674 | * 0x01 - XferComplete | |
| 675 | * 0x02 - XferInProgress | |
| 676 | * 0x03 - XferNotReady | |
| 677 | * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) | |
| 678 | * 0x05 - Reserved | |
| 679 | * 0x06 - StreamEvt | |
| 680 | * 0x07 - EPCmdCmplt | |
| 681 | * @reserved11_10: Reserved, don't use. | |
| 682 | * @status: Indicates the status of the event. Refer to databook for | |
| 683 | * more information. | |
| 684 | * @parameters: Parameters of the current event. Refer to databook for | |
| 685 | * more information. | |
| 686 | */ | |
| 687 | struct dwc3_event_depevt { | |
| 688 | u32 one_bit:1; | |
| 689 | u32 endpoint_number:5; | |
| 690 | u32 endpoint_event:4; | |
| 691 | u32 reserved11_10:2; | |
| 692 | u32 status:4; | |
| 40aa41fb FB |
693 | |
| 694 | /* Within XferNotReady */ | |
| 695 | #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) | |
| 696 | ||
| 697 | /* Within XferComplete */ | |
| 1d046793 PZ |
698 | #define DEPEVT_STATUS_BUSERR (1 << 0) |
| 699 | #define DEPEVT_STATUS_SHORT (1 << 1) | |
| 700 | #define DEPEVT_STATUS_IOC (1 << 2) | |
| 72246da4 | 701 | #define DEPEVT_STATUS_LST (1 << 3) |
| dc137f01 | 702 | |
| 879631aa FB |
703 | /* Stream event only */ |
| 704 | #define DEPEVT_STREAMEVT_FOUND 1 | |
| 705 | #define DEPEVT_STREAMEVT_NOTFOUND 2 | |
| 706 | ||
| dc137f01 FB |
707 | /* Control-only Status */ |
| 708 | #define DEPEVT_STATUS_CONTROL_SETUP 0 | |
| 709 | #define DEPEVT_STATUS_CONTROL_DATA 1 | |
| 710 | #define DEPEVT_STATUS_CONTROL_STATUS 2 | |
| 711 | ||
| 72246da4 FB |
712 | u32 parameters:16; |
| 713 | } __packed; | |
| 714 | ||
| 715 | /** | |
| 716 | * struct dwc3_event_devt - Device Events | |
| 717 | * @one_bit: indicates this is a non-endpoint event (not used) | |
| 718 | * @device_event: indicates it's a device event. Should read as 0x00 | |
| 719 | * @type: indicates the type of device event. | |
| 720 | * 0 - DisconnEvt | |
| 721 | * 1 - USBRst | |
| 722 | * 2 - ConnectDone | |
| 723 | * 3 - ULStChng | |
| 724 | * 4 - WkUpEvt | |
| 725 | * 5 - Reserved | |
| 726 | * 6 - EOPF | |
| 727 | * 7 - SOF | |
| 728 | * 8 - Reserved | |
| 729 | * 9 - ErrticErr | |
| 730 | * 10 - CmdCmplt | |
| 731 | * 11 - EvntOverflow | |
| 732 | * 12 - VndrDevTstRcved | |
| 733 | * @reserved15_12: Reserved, not used | |
| 734 | * @event_info: Information about this event | |
| 735 | * @reserved31_24: Reserved, not used | |
| 736 | */ | |
| 737 | struct dwc3_event_devt { | |
| 738 | u32 one_bit:1; | |
| 739 | u32 device_event:7; | |
| 740 | u32 type:4; | |
| 741 | u32 reserved15_12:4; | |
| 742 | u32 event_info:8; | |
| 743 | u32 reserved31_24:8; | |
| 744 | } __packed; | |
| 745 | ||
| 746 | /** | |
| 747 | * struct dwc3_event_gevt - Other Core Events | |
| 748 | * @one_bit: indicates this is a non-endpoint event (not used) | |
| 749 | * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. | |
| 750 | * @phy_port_number: self-explanatory | |
| 751 | * @reserved31_12: Reserved, not used. | |
| 752 | */ | |
| 753 | struct dwc3_event_gevt { | |
| 754 | u32 one_bit:1; | |
| 755 | u32 device_event:7; | |
| 756 | u32 phy_port_number:4; | |
| 757 | u32 reserved31_12:20; | |
| 758 | } __packed; | |
| 759 | ||
| 760 | /** | |
| 761 | * union dwc3_event - representation of Event Buffer contents | |
| 762 | * @raw: raw 32-bit event | |
| 763 | * @type: the type of the event | |
| 764 | * @depevt: Device Endpoint Event | |
| 765 | * @devt: Device Event | |
| 766 | * @gevt: Global Event | |
| 767 | */ | |
| 768 | union dwc3_event { | |
| 769 | u32 raw; | |
| 770 | struct dwc3_event_type type; | |
| 771 | struct dwc3_event_depevt depevt; | |
| 772 | struct dwc3_event_devt devt; | |
| 773 | struct dwc3_event_gevt gevt; | |
| 774 | }; | |
| 775 | ||
| 776 | /* | |
| 777 | * DWC3 Features to be used as Driver Data | |
| 778 | */ | |
| 779 | ||
| 780 | #define DWC3_HAS_PERIPHERAL BIT(0) | |
| 781 | #define DWC3_HAS_XHCI BIT(1) | |
| 782 | #define DWC3_HAS_OTG BIT(3) | |
| 783 | ||
| d07e8819 | 784 | /* prototypes */ |
| 3140e8cb | 785 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode); |
| 457e84b6 | 786 | int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); |
| 3140e8cb | 787 | |
| d07e8819 FB |
788 | int dwc3_host_init(struct dwc3 *dwc); |
| 789 | void dwc3_host_exit(struct dwc3 *dwc); | |
| 790 | ||
| f80b45e7 FB |
791 | int dwc3_gadget_init(struct dwc3 *dwc); |
| 792 | void dwc3_gadget_exit(struct dwc3 *dwc); | |
| 793 | ||
| 8300dd23 FB |
794 | extern int dwc3_get_device_id(void); |
| 795 | extern void dwc3_put_device_id(int id); | |
| 796 | ||
| 72246da4 | 797 | #endif /* __DRIVERS_USB_DWC3_CORE_H */ |