Commit | Line | Data |
---|---|---|
b33f69f5 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
bfad65ee | 2 | /* |
72246da4 FB |
3 | * core.h - DesignWare USB3 DRD Core Header |
4 | * | |
10623b87 | 5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com |
72246da4 FB |
6 | * |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
72246da4 FB |
9 | */ |
10 | ||
11 | #ifndef __DRIVERS_USB_DWC3_CORE_H | |
12 | #define __DRIVERS_USB_DWC3_CORE_H | |
13 | ||
14 | #include <linux/device.h> | |
15 | #include <linux/spinlock.h> | |
d07e8819 | 16 | #include <linux/ioport.h> |
72246da4 | 17 | #include <linux/list.h> |
ff3f0789 | 18 | #include <linux/bitops.h> |
72246da4 FB |
19 | #include <linux/dma-mapping.h> |
20 | #include <linux/mm.h> | |
21 | #include <linux/debugfs.h> | |
76a638f8 | 22 | #include <linux/wait.h> |
41ce1456 | 23 | #include <linux/workqueue.h> |
72246da4 FB |
24 | |
25 | #include <linux/usb/ch9.h> | |
26 | #include <linux/usb/gadget.h> | |
a45c82b8 | 27 | #include <linux/usb/otg.h> |
8a0a1379 | 28 | #include <linux/usb/role.h> |
88bc9d19 | 29 | #include <linux/ulpi/interface.h> |
72246da4 | 30 | |
57303488 KVA |
31 | #include <linux/phy/phy.h> |
32 | ||
6f0764b5 RC |
33 | #include <linux/power_supply.h> |
34 | ||
2c4cbe6e FB |
35 | #define DWC3_MSG_MAX 500 |
36 | ||
72246da4 | 37 | /* Global constants */ |
bb014736 | 38 | #define DWC3_PULL_UP_TIMEOUT 500 /* ms */ |
905dc04e | 39 | #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */ |
4199c5f8 | 40 | #define DWC3_EP0_SETUP_SIZE 512 |
72246da4 | 41 | #define DWC3_ENDPOINTS_NUM 32 |
51249dca | 42 | #define DWC3_XHCI_RESOURCES_NUM 2 |
d5370106 | 43 | #define DWC3_ISOC_MAX_RETRIES 5 |
72246da4 | 44 | |
0ffcaf37 | 45 | #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ |
e71d363d | 46 | #define DWC3_EVENT_BUFFERS_SIZE 4096 |
72246da4 FB |
47 | #define DWC3_EVENT_TYPE_MASK 0xfe |
48 | ||
49 | #define DWC3_EVENT_TYPE_DEV 0 | |
50 | #define DWC3_EVENT_TYPE_CARKIT 3 | |
51 | #define DWC3_EVENT_TYPE_I2C 4 | |
52 | ||
53 | #define DWC3_DEVICE_EVENT_DISCONNECT 0 | |
54 | #define DWC3_DEVICE_EVENT_RESET 1 | |
55 | #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 | |
56 | #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 | |
57 | #define DWC3_DEVICE_EVENT_WAKEUP 4 | |
2c61a8ef | 58 | #define DWC3_DEVICE_EVENT_HIBER_REQ 5 |
72246da4 FB |
59 | #define DWC3_DEVICE_EVENT_EOPF 6 |
60 | #define DWC3_DEVICE_EVENT_SOF 7 | |
61 | #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 | |
62 | #define DWC3_DEVICE_EVENT_CMD_CMPL 10 | |
63 | #define DWC3_DEVICE_EVENT_OVERFLOW 11 | |
64 | ||
f09cc79b RQ |
65 | /* Controller's role while using the OTG block */ |
66 | #define DWC3_OTG_ROLE_IDLE 0 | |
67 | #define DWC3_OTG_ROLE_HOST 1 | |
68 | #define DWC3_OTG_ROLE_DEVICE 2 | |
69 | ||
72246da4 | 70 | #define DWC3_GEVNTCOUNT_MASK 0xfffc |
ff3f0789 | 71 | #define DWC3_GEVNTCOUNT_EHB BIT(31) |
72246da4 FB |
72 | #define DWC3_GSNPSID_MASK 0xffff0000 |
73 | #define DWC3_GSNPSREV_MASK 0xffff | |
9af21dd6 | 74 | #define DWC3_GSNPS_ID(p) (((p) & DWC3_GSNPSID_MASK) >> 16) |
72246da4 | 75 | |
51249dca IS |
76 | /* DWC3 registers memory space boundries */ |
77 | #define DWC3_XHCI_REGS_START 0x0 | |
78 | #define DWC3_XHCI_REGS_END 0x7fff | |
79 | #define DWC3_GLOBALS_REGS_START 0xc100 | |
80 | #define DWC3_GLOBALS_REGS_END 0xc6ff | |
81 | #define DWC3_DEVICE_REGS_START 0xc700 | |
82 | #define DWC3_DEVICE_REGS_END 0xcbff | |
83 | #define DWC3_OTG_REGS_START 0xcc00 | |
84 | #define DWC3_OTG_REGS_END 0xccff | |
85 | ||
72246da4 FB |
86 | /* Global Registers */ |
87 | #define DWC3_GSBUSCFG0 0xc100 | |
88 | #define DWC3_GSBUSCFG1 0xc104 | |
89 | #define DWC3_GTXTHRCFG 0xc108 | |
90 | #define DWC3_GRXTHRCFG 0xc10c | |
91 | #define DWC3_GCTL 0xc110 | |
92 | #define DWC3_GEVTEN 0xc114 | |
93 | #define DWC3_GSTS 0xc118 | |
475c8beb | 94 | #define DWC3_GUCTL1 0xc11c |
72246da4 FB |
95 | #define DWC3_GSNPSID 0xc120 |
96 | #define DWC3_GGPIO 0xc124 | |
97 | #define DWC3_GUID 0xc128 | |
98 | #define DWC3_GUCTL 0xc12c | |
99 | #define DWC3_GBUSERRADDR0 0xc130 | |
100 | #define DWC3_GBUSERRADDR1 0xc134 | |
101 | #define DWC3_GPRTBIMAP0 0xc138 | |
102 | #define DWC3_GPRTBIMAP1 0xc13c | |
103 | #define DWC3_GHWPARAMS0 0xc140 | |
104 | #define DWC3_GHWPARAMS1 0xc144 | |
105 | #define DWC3_GHWPARAMS2 0xc148 | |
106 | #define DWC3_GHWPARAMS3 0xc14c | |
107 | #define DWC3_GHWPARAMS4 0xc150 | |
108 | #define DWC3_GHWPARAMS5 0xc154 | |
109 | #define DWC3_GHWPARAMS6 0xc158 | |
110 | #define DWC3_GHWPARAMS7 0xc15c | |
111 | #define DWC3_GDBGFIFOSPACE 0xc160 | |
112 | #define DWC3_GDBGLTSSM 0xc164 | |
80b77634 TN |
113 | #define DWC3_GDBGBMU 0xc16c |
114 | #define DWC3_GDBGLSPMUX 0xc170 | |
115 | #define DWC3_GDBGLSP 0xc174 | |
116 | #define DWC3_GDBGEPINFO0 0xc178 | |
117 | #define DWC3_GDBGEPINFO1 0xc17c | |
72246da4 FB |
118 | #define DWC3_GPRTBIMAP_HS0 0xc180 |
119 | #define DWC3_GPRTBIMAP_HS1 0xc184 | |
120 | #define DWC3_GPRTBIMAP_FS0 0xc188 | |
121 | #define DWC3_GPRTBIMAP_FS1 0xc18c | |
06281d46 | 122 | #define DWC3_GUCTL2 0xc19c |
72246da4 | 123 | |
690fb371 JY |
124 | #define DWC3_VER_NUMBER 0xc1a0 |
125 | #define DWC3_VER_TYPE 0xc1a4 | |
126 | ||
8261bd4e RQ |
127 | #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04)) |
128 | #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04)) | |
72246da4 | 129 | |
8261bd4e | 130 | #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04)) |
72246da4 | 131 | |
8261bd4e | 132 | #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04)) |
72246da4 | 133 | |
8261bd4e RQ |
134 | #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04)) |
135 | #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04)) | |
72246da4 | 136 | |
8261bd4e RQ |
137 | #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10)) |
138 | #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10)) | |
139 | #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10)) | |
140 | #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) | |
72246da4 FB |
141 | |
142 | #define DWC3_GHWPARAMS8 0xc600 | |
f580170f | 143 | #define DWC3_GUCTL3 0xc60c |
db2be4e9 | 144 | #define DWC3_GFLADJ 0xc630 |
72246da4 FB |
145 | |
146 | /* Device Registers */ | |
147 | #define DWC3_DCFG 0xc700 | |
148 | #define DWC3_DCTL 0xc704 | |
149 | #define DWC3_DEVTEN 0xc708 | |
150 | #define DWC3_DSTS 0xc70c | |
151 | #define DWC3_DGCMDPAR 0xc710 | |
152 | #define DWC3_DGCMD 0xc714 | |
153 | #define DWC3_DALEPENA 0xc720 | |
2eb88016 | 154 | |
8261bd4e | 155 | #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10)) |
2eb88016 FB |
156 | #define DWC3_DEPCMDPAR2 0x00 |
157 | #define DWC3_DEPCMDPAR1 0x04 | |
158 | #define DWC3_DEPCMDPAR0 0x08 | |
159 | #define DWC3_DEPCMD 0x0c | |
72246da4 | 160 | |
8261bd4e | 161 | #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4)) |
cf40b86b | 162 | |
72246da4 FB |
163 | /* OTG Registers */ |
164 | #define DWC3_OCFG 0xcc00 | |
165 | #define DWC3_OCTL 0xcc04 | |
d4436c3a GC |
166 | #define DWC3_OEVT 0xcc08 |
167 | #define DWC3_OEVTEN 0xcc0C | |
168 | #define DWC3_OSTS 0xcc10 | |
72246da4 FB |
169 | |
170 | /* Bit fields */ | |
171 | ||
d635db55 PM |
172 | /* Global SoC Bus Configuration INCRx Register 0 */ |
173 | #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */ | |
174 | #define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */ | |
175 | #define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */ | |
176 | #define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */ | |
177 | #define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */ | |
178 | #define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */ | |
179 | #define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */ | |
180 | #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */ | |
181 | #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff | |
182 | ||
62ba09d6 TN |
183 | /* Global Debug LSP MUX Select */ |
184 | #define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */ | |
185 | #define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff) | |
186 | #define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4) | |
187 | #define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf) | |
188 | ||
cf6d867d FB |
189 | /* Global Debug Queue/FIFO Space Available Register */ |
190 | #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) | |
191 | #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) | |
192 | #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff) | |
193 | ||
2c85a181 TN |
194 | #define DWC3_TXFIFO 0 |
195 | #define DWC3_RXFIFO 1 | |
b16ea8b9 TN |
196 | #define DWC3_TXREQQ 2 |
197 | #define DWC3_RXREQQ 3 | |
198 | #define DWC3_RXINFOQ 4 | |
199 | #define DWC3_PSTATQ 5 | |
200 | #define DWC3_DESCFETCHQ 6 | |
201 | #define DWC3_EVENTQ 7 | |
202 | #define DWC3_AUXEVENTQ 8 | |
cf6d867d | 203 | |
2a58f9c1 FB |
204 | /* Global RX Threshold Configuration Register */ |
205 | #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19) | |
206 | #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24) | |
ff3f0789 | 207 | #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29) |
2a58f9c1 | 208 | |
2fbc5bdc TN |
209 | /* Global RX Threshold Configuration Register for DWC_usb31 only */ |
210 | #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16) | |
211 | #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21) | |
212 | #define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26) | |
213 | #define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15) | |
214 | #define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) | |
215 | #define DWC31_RXTHRNUMPKTSEL_PRD BIT(10) | |
216 | #define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) | |
217 | #define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f) | |
218 | ||
6743e817 TN |
219 | /* Global TX Threshold Configuration Register for DWC_usb31 only */ |
220 | #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16) | |
221 | #define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21) | |
222 | #define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26) | |
223 | #define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15) | |
224 | #define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) | |
225 | #define DWC31_TXTHRNUMPKTSEL_PRD BIT(10) | |
226 | #define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) | |
227 | #define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f) | |
228 | ||
72246da4 | 229 | /* Global Configuration Register */ |
1d046793 | 230 | #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) |
ff3f0789 | 231 | #define DWC3_GCTL_U2RSTECN BIT(16) |
1d046793 | 232 | #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) |
72246da4 FB |
233 | #define DWC3_GCTL_CLK_BUS (0) |
234 | #define DWC3_GCTL_CLK_PIPE (1) | |
235 | #define DWC3_GCTL_CLK_PIPEHALF (2) | |
236 | #define DWC3_GCTL_CLK_MASK (3) | |
237 | ||
0b9fe32d | 238 | #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) |
1d046793 | 239 | #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) |
72246da4 FB |
240 | #define DWC3_GCTL_PRTCAP_HOST 1 |
241 | #define DWC3_GCTL_PRTCAP_DEVICE 2 | |
242 | #define DWC3_GCTL_PRTCAP_OTG 3 | |
243 | ||
ff3f0789 RQ |
244 | #define DWC3_GCTL_CORESOFTRESET BIT(11) |
245 | #define DWC3_GCTL_SOFITPSYNC BIT(10) | |
2c61a8ef PZ |
246 | #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) |
247 | #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) | |
ff3f0789 RQ |
248 | #define DWC3_GCTL_DISSCRAMBLE BIT(3) |
249 | #define DWC3_GCTL_U2EXIT_LFPS BIT(2) | |
250 | #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1) | |
251 | #define DWC3_GCTL_DSBLCLKGTNG BIT(0) | |
72246da4 | 252 | |
b138e23d AKV |
253 | /* Global User Control Register */ |
254 | #define DWC3_GUCTL_HSTINAUTORETRY BIT(14) | |
255 | ||
0bb39ca1 | 256 | /* Global User Control 1 Register */ |
7ba6b09f | 257 | #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) |
65db7a0c | 258 | #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) |
ff3f0789 | 259 | #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) |
0bb39ca1 | 260 | |
4cff75c7 RQ |
261 | /* Global Status Register */ |
262 | #define DWC3_GSTS_OTG_IP BIT(10) | |
263 | #define DWC3_GSTS_BC_IP BIT(9) | |
264 | #define DWC3_GSTS_ADP_IP BIT(8) | |
265 | #define DWC3_GSTS_HOST_IP BIT(7) | |
266 | #define DWC3_GSTS_DEVICE_IP BIT(6) | |
267 | #define DWC3_GSTS_CSR_TIMEOUT BIT(5) | |
268 | #define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4) | |
62ba09d6 TN |
269 | #define DWC3_GSTS_CURMOD(n) ((n) & 0x3) |
270 | #define DWC3_GSTS_CURMOD_DEVICE 0 | |
271 | #define DWC3_GSTS_CURMOD_HOST 1 | |
4cff75c7 | 272 | |
72246da4 | 273 | /* Global USB2 PHY Configuration Register */ |
ff3f0789 RQ |
274 | #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31) |
275 | #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30) | |
276 | #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6) | |
277 | #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4) | |
278 | #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8) | |
32f2ed86 WW |
279 | #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3) |
280 | #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) | |
281 | #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10) | |
282 | #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) | |
283 | #define USBTRDTIM_UTMI_8_BIT 9 | |
284 | #define USBTRDTIM_UTMI_16_BIT 5 | |
285 | #define UTMI_PHYIF_16_BIT 1 | |
286 | #define UTMI_PHYIF_8_BIT 0 | |
72246da4 | 287 | |
b5699eee | 288 | /* Global USB2 PHY Vendor Control Register */ |
ff3f0789 | 289 | #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25) |
ce722da6 | 290 | #define DWC3_GUSB2PHYACC_DONE BIT(24) |
ff3f0789 RQ |
291 | #define DWC3_GUSB2PHYACC_BUSY BIT(23) |
292 | #define DWC3_GUSB2PHYACC_WRITE BIT(22) | |
b5699eee HK |
293 | #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) |
294 | #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) | |
295 | #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) | |
296 | ||
72246da4 | 297 | /* Global USB3 PIPE Control Register */ |
ff3f0789 RQ |
298 | #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31) |
299 | #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29) | |
300 | #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28) | |
301 | #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27) | |
302 | #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24) | |
a2a1d0f5 HR |
303 | #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) |
304 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) | |
305 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) | |
ff3f0789 RQ |
306 | #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18) |
307 | #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17) | |
308 | #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9) | |
309 | #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8) | |
6b6a0c9a HR |
310 | #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) |
311 | #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) | |
72246da4 | 312 | |
457e84b6 | 313 | /* Global TX Fifo Size Register */ |
0cab8d26 | 314 | #define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */ |
586f4335 TN |
315 | #define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */ |
316 | #define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff) | |
2c61a8ef | 317 | #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) |
457e84b6 | 318 | |
d94ea531 TN |
319 | /* Global RX Fifo Size Register */ |
320 | #define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */ | |
321 | #define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff) | |
322 | ||
68d6a01b | 323 | /* Global Event Size Registers */ |
ff3f0789 | 324 | #define DWC3_GEVNTSIZ_INTMASK BIT(31) |
68d6a01b FB |
325 | #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) |
326 | ||
4e99472b | 327 | /* Global HWPARAMS0 Register */ |
9d6173e1 TN |
328 | #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3) |
329 | #define DWC3_GHWPARAMS0_MODE_GADGET 0 | |
330 | #define DWC3_GHWPARAMS0_MODE_HOST 1 | |
331 | #define DWC3_GHWPARAMS0_MODE_DRD 2 | |
4e99472b FB |
332 | #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7) |
333 | #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3) | |
334 | #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff) | |
335 | #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff) | |
336 | #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff) | |
337 | ||
aabb7075 | 338 | /* Global HWPARAMS1 Register */ |
1d046793 | 339 | #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) |
aabb7075 FB |
340 | #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 |
341 | #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 | |
2c61a8ef PZ |
342 | #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 |
343 | #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) | |
344 | #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) | |
62ba09d6 | 345 | #define DWC3_GHWPARAMS1_ENDBC BIT(31) |
2c61a8ef | 346 | |
0e1e5c47 PZ |
347 | /* Global HWPARAMS3 Register */ |
348 | #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) | |
349 | #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 | |
1f38f88a JY |
350 | #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1 |
351 | #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */ | |
0e1e5c47 PZ |
352 | #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) |
353 | #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 | |
354 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 | |
355 | #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 | |
356 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 | |
357 | #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) | |
358 | #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 | |
359 | #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 | |
360 | ||
2c61a8ef PZ |
361 | /* Global HWPARAMS4 Register */ |
362 | #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) | |
363 | #define DWC3_MAX_HIBER_SCRATCHBUFS 15 | |
aabb7075 | 364 | |
946bd579 | 365 | /* Global HWPARAMS6 Register */ |
4cff75c7 RQ |
366 | #define DWC3_GHWPARAMS6_BCSUPPORT BIT(14) |
367 | #define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13) | |
368 | #define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12) | |
369 | #define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11) | |
370 | #define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10) | |
ff3f0789 | 371 | #define DWC3_GHWPARAMS6_EN_FPGA BIT(7) |
946bd579 | 372 | |
4244ba02 TN |
373 | /* DWC_usb32 only */ |
374 | #define DWC3_GHWPARAMS6_MDWIDTH(n) ((n) & (0x3 << 8)) | |
375 | ||
4e99472b FB |
376 | /* Global HWPARAMS7 Register */ |
377 | #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff) | |
378 | #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff) | |
379 | ||
db2be4e9 | 380 | /* Global Frame Length Adjustment Register */ |
ff3f0789 | 381 | #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7) |
db2be4e9 NB |
382 | #define DWC3_GFLADJ_30MHZ_MASK 0x3f |
383 | ||
06281d46 | 384 | /* Global User Control Register 2 */ |
ff3f0789 | 385 | #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) |
06281d46 | 386 | |
f580170f YC |
387 | /* Global User Control Register 3 */ |
388 | #define DWC3_GUCTL3_SPLITDISABLE BIT(14) | |
389 | ||
72246da4 | 390 | /* Device Configuration Register */ |
072cab8a TN |
391 | #define DWC3_DCFG_NUMLANES(n) (((n) & 0x3) << 30) /* DWC_usb32 only */ |
392 | ||
72246da4 FB |
393 | #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) |
394 | #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) | |
395 | ||
396 | #define DWC3_DCFG_SPEED_MASK (7 << 0) | |
1f38f88a | 397 | #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ |
72246da4 FB |
398 | #define DWC3_DCFG_SUPERSPEED (4 << 0) |
399 | #define DWC3_DCFG_HIGHSPEED (0 << 0) | |
ff3f0789 | 400 | #define DWC3_DCFG_FULLSPEED BIT(0) |
72246da4 | 401 | |
676e3497 | 402 | #define DWC3_DCFG_NUMP_SHIFT 17 |
97398612 | 403 | #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f) |
676e3497 | 404 | #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT) |
ff3f0789 | 405 | #define DWC3_DCFG_LPM_CAP BIT(22) |
2c61a8ef | 406 | |
72246da4 | 407 | /* Device Control Register */ |
ff3f0789 RQ |
408 | #define DWC3_DCTL_RUN_STOP BIT(31) |
409 | #define DWC3_DCTL_CSFTRST BIT(30) | |
410 | #define DWC3_DCTL_LSFTRST BIT(29) | |
72246da4 FB |
411 | |
412 | #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) | |
7e39b817 | 413 | #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) |
72246da4 | 414 | |
ff3f0789 | 415 | #define DWC3_DCTL_APPL1RES BIT(23) |
72246da4 | 416 | |
2c61a8ef PZ |
417 | /* These apply for core versions 1.87a and earlier */ |
418 | #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) | |
419 | #define DWC3_DCTL_TRGTULST(n) ((n) << 17) | |
420 | #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) | |
421 | #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) | |
422 | #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) | |
423 | #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) | |
424 | #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) | |
425 | ||
426 | /* These apply for core versions 1.94a and later */ | |
2e487d28 | 427 | #define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20) |
8db7ed15 | 428 | |
ff3f0789 RQ |
429 | #define DWC3_DCTL_KEEP_CONNECT BIT(19) |
430 | #define DWC3_DCTL_L1_HIBER_EN BIT(18) | |
431 | #define DWC3_DCTL_CRS BIT(17) | |
432 | #define DWC3_DCTL_CSS BIT(16) | |
80caf7d2 | 433 | |
ff3f0789 RQ |
434 | #define DWC3_DCTL_INITU2ENA BIT(12) |
435 | #define DWC3_DCTL_ACCEPTU2ENA BIT(11) | |
436 | #define DWC3_DCTL_INITU1ENA BIT(10) | |
437 | #define DWC3_DCTL_ACCEPTU1ENA BIT(9) | |
80caf7d2 | 438 | #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) |
72246da4 FB |
439 | |
440 | #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) | |
441 | #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) | |
442 | ||
443 | #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) | |
444 | #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) | |
445 | #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) | |
446 | #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) | |
447 | #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) | |
448 | #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) | |
449 | #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) | |
450 | ||
451 | /* Device Event Enable Register */ | |
ff3f0789 RQ |
452 | #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12) |
453 | #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11) | |
454 | #define DWC3_DEVTEN_CMDCMPLTEN BIT(10) | |
455 | #define DWC3_DEVTEN_ERRTICERREN BIT(9) | |
456 | #define DWC3_DEVTEN_SOFEN BIT(7) | |
457 | #define DWC3_DEVTEN_EOPFEN BIT(6) | |
458 | #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5) | |
459 | #define DWC3_DEVTEN_WKUPEVTEN BIT(4) | |
460 | #define DWC3_DEVTEN_ULSTCNGEN BIT(3) | |
461 | #define DWC3_DEVTEN_CONNECTDONEEN BIT(2) | |
462 | #define DWC3_DEVTEN_USBRSTEN BIT(1) | |
463 | #define DWC3_DEVTEN_DISCONNEVTEN BIT(0) | |
72246da4 | 464 | |
f551037c TN |
465 | #define DWC3_DSTS_CONNLANES(n) (((n) >> 30) & 0x3) /* DWC_usb32 only */ |
466 | ||
72246da4 | 467 | /* Device Status Register */ |
ff3f0789 | 468 | #define DWC3_DSTS_DCNRD BIT(29) |
2c61a8ef PZ |
469 | |
470 | /* This applies for core versions 1.87a and earlier */ | |
ff3f0789 | 471 | #define DWC3_DSTS_PWRUPREQ BIT(24) |
2c61a8ef PZ |
472 | |
473 | /* These apply for core versions 1.94a and later */ | |
ff3f0789 RQ |
474 | #define DWC3_DSTS_RSS BIT(25) |
475 | #define DWC3_DSTS_SSS BIT(24) | |
2c61a8ef | 476 | |
ff3f0789 RQ |
477 | #define DWC3_DSTS_COREIDLE BIT(23) |
478 | #define DWC3_DSTS_DEVCTRLHLT BIT(22) | |
72246da4 FB |
479 | |
480 | #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) | |
481 | #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) | |
482 | ||
ff3f0789 | 483 | #define DWC3_DSTS_RXFIFOEMPTY BIT(17) |
72246da4 | 484 | |
d05b8182 | 485 | #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) |
72246da4 FB |
486 | #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) |
487 | ||
488 | #define DWC3_DSTS_CONNECTSPD (7 << 0) | |
489 | ||
1f38f88a | 490 | #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ |
72246da4 FB |
491 | #define DWC3_DSTS_SUPERSPEED (4 << 0) |
492 | #define DWC3_DSTS_HIGHSPEED (0 << 0) | |
ff3f0789 | 493 | #define DWC3_DSTS_FULLSPEED BIT(0) |
72246da4 FB |
494 | |
495 | /* Device Generic Command Register */ | |
496 | #define DWC3_DGCMD_SET_LMP 0x01 | |
497 | #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 | |
498 | #define DWC3_DGCMD_XMIT_FUNCTION 0x03 | |
2c61a8ef PZ |
499 | |
500 | /* These apply for core versions 1.94a and later */ | |
501 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 | |
502 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 | |
503 | ||
72246da4 FB |
504 | #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 |
505 | #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a | |
506 | #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c | |
140ca4cf | 507 | #define DWC3_DGCMD_SET_ENDPOINT_PRIME 0x0d |
72246da4 FB |
508 | #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 |
509 | ||
459e210c | 510 | #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) |
ff3f0789 RQ |
511 | #define DWC3_DGCMD_CMDACT BIT(10) |
512 | #define DWC3_DGCMD_CMDIOC BIT(8) | |
2c61a8ef PZ |
513 | |
514 | /* Device Generic Command Parameter Register */ | |
ff3f0789 | 515 | #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0) |
2c61a8ef PZ |
516 | #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) |
517 | #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) | |
ff3f0789 | 518 | #define DWC3_DGCMDPAR_TX_FIFO BIT(5) |
2c61a8ef | 519 | #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) |
ff3f0789 | 520 | #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0) |
b09bb642 | 521 | |
72246da4 FB |
522 | /* Device Endpoint Command Register */ |
523 | #define DWC3_DEPCMD_PARAM_SHIFT 16 | |
1d046793 | 524 | #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) |
835fadb4 | 525 | #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) |
459e210c | 526 | #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) |
ff3f0789 RQ |
527 | #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11) |
528 | #define DWC3_DEPCMD_CLEARPENDIN BIT(11) | |
529 | #define DWC3_DEPCMD_CMDACT BIT(10) | |
530 | #define DWC3_DEPCMD_CMDIOC BIT(8) | |
72246da4 FB |
531 | |
532 | #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) | |
533 | #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) | |
534 | #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) | |
535 | #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) | |
536 | #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) | |
537 | #define DWC3_DEPCMD_SETSTALL (0x04 << 0) | |
2c61a8ef | 538 | /* This applies for core versions 1.90a and earlier */ |
72246da4 | 539 | #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) |
2c61a8ef PZ |
540 | /* This applies for core versions 1.94a and later */ |
541 | #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) | |
72246da4 FB |
542 | #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) |
543 | #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) | |
544 | ||
5999914f FB |
545 | #define DWC3_DEPCMD_CMD(x) ((x) & 0xf) |
546 | ||
72246da4 | 547 | /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ |
ff3f0789 | 548 | #define DWC3_DALEPENA_EP(n) BIT(n) |
72246da4 FB |
549 | |
550 | #define DWC3_DEPCMD_TYPE_CONTROL 0 | |
551 | #define DWC3_DEPCMD_TYPE_ISOC 1 | |
552 | #define DWC3_DEPCMD_TYPE_BULK 2 | |
553 | #define DWC3_DEPCMD_TYPE_INTR 3 | |
554 | ||
cf40b86b JY |
555 | #define DWC3_DEV_IMOD_COUNT_SHIFT 16 |
556 | #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16) | |
557 | #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0 | |
558 | #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0) | |
559 | ||
4cff75c7 RQ |
560 | /* OTG Configuration Register */ |
561 | #define DWC3_OCFG_DISPWRCUTTOFF BIT(5) | |
562 | #define DWC3_OCFG_HIBDISMASK BIT(4) | |
563 | #define DWC3_OCFG_SFTRSTMASK BIT(3) | |
564 | #define DWC3_OCFG_OTGVERSION BIT(2) | |
565 | #define DWC3_OCFG_HNPCAP BIT(1) | |
566 | #define DWC3_OCFG_SRPCAP BIT(0) | |
567 | ||
568 | /* OTG CTL Register */ | |
569 | #define DWC3_OCTL_OTG3GOERR BIT(7) | |
570 | #define DWC3_OCTL_PERIMODE BIT(6) | |
571 | #define DWC3_OCTL_PRTPWRCTL BIT(5) | |
572 | #define DWC3_OCTL_HNPREQ BIT(4) | |
573 | #define DWC3_OCTL_SESREQ BIT(3) | |
574 | #define DWC3_OCTL_TERMSELIDPULSE BIT(2) | |
575 | #define DWC3_OCTL_DEVSETHNPEN BIT(1) | |
576 | #define DWC3_OCTL_HSTSETHNPEN BIT(0) | |
577 | ||
578 | /* OTG Event Register */ | |
579 | #define DWC3_OEVT_DEVICEMODE BIT(31) | |
580 | #define DWC3_OEVT_XHCIRUNSTPSET BIT(27) | |
581 | #define DWC3_OEVT_DEVRUNSTPSET BIT(26) | |
582 | #define DWC3_OEVT_HIBENTRY BIT(25) | |
583 | #define DWC3_OEVT_CONIDSTSCHNG BIT(24) | |
584 | #define DWC3_OEVT_HRRCONFNOTIF BIT(23) | |
585 | #define DWC3_OEVT_HRRINITNOTIF BIT(22) | |
586 | #define DWC3_OEVT_ADEVIDLE BIT(21) | |
587 | #define DWC3_OEVT_ADEVBHOSTEND BIT(20) | |
588 | #define DWC3_OEVT_ADEVHOST BIT(19) | |
589 | #define DWC3_OEVT_ADEVHNPCHNG BIT(18) | |
590 | #define DWC3_OEVT_ADEVSRPDET BIT(17) | |
591 | #define DWC3_OEVT_ADEVSESSENDDET BIT(16) | |
592 | #define DWC3_OEVT_BDEVBHOSTEND BIT(11) | |
593 | #define DWC3_OEVT_BDEVHNPCHNG BIT(10) | |
594 | #define DWC3_OEVT_BDEVSESSVLDDET BIT(9) | |
595 | #define DWC3_OEVT_BDEVVBUSCHNG BIT(8) | |
596 | #define DWC3_OEVT_BSESSVLD BIT(3) | |
597 | #define DWC3_OEVT_HSTNEGSTS BIT(2) | |
598 | #define DWC3_OEVT_SESREQSTS BIT(1) | |
599 | #define DWC3_OEVT_ERROR BIT(0) | |
600 | ||
601 | /* OTG Event Enable Register */ | |
602 | #define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27) | |
603 | #define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26) | |
604 | #define DWC3_OEVTEN_HIBENTRYEN BIT(25) | |
605 | #define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24) | |
606 | #define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23) | |
607 | #define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22) | |
608 | #define DWC3_OEVTEN_ADEVIDLEEN BIT(21) | |
609 | #define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20) | |
610 | #define DWC3_OEVTEN_ADEVHOSTEN BIT(19) | |
611 | #define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18) | |
612 | #define DWC3_OEVTEN_ADEVSRPDETEN BIT(17) | |
613 | #define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16) | |
614 | #define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11) | |
615 | #define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10) | |
616 | #define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9) | |
617 | #define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8) | |
618 | ||
619 | /* OTG Status Register */ | |
620 | #define DWC3_OSTS_DEVRUNSTP BIT(13) | |
621 | #define DWC3_OSTS_XHCIRUNSTP BIT(12) | |
622 | #define DWC3_OSTS_PERIPHERALSTATE BIT(4) | |
623 | #define DWC3_OSTS_XHCIPRTPOWER BIT(3) | |
624 | #define DWC3_OSTS_BSESVLD BIT(2) | |
625 | #define DWC3_OSTS_VBUSVLD BIT(1) | |
626 | #define DWC3_OSTS_CONIDSTS BIT(0) | |
627 | ||
72246da4 FB |
628 | /* Structures */ |
629 | ||
f6bafc6a | 630 | struct dwc3_trb; |
72246da4 FB |
631 | |
632 | /** | |
633 | * struct dwc3_event_buffer - Software event buffer representation | |
72246da4 | 634 | * @buf: _THE_ buffer |
d9fa4c63 | 635 | * @cache: The buffer cache used in the threaded interrupt |
72246da4 | 636 | * @length: size of this buffer |
abed4118 | 637 | * @lpos: event offset |
60d04bbe | 638 | * @count: cache of last read event count register |
abed4118 | 639 | * @flags: flags related to this event buffer |
72246da4 FB |
640 | * @dma: dma_addr_t |
641 | * @dwc: pointer to DWC controller | |
642 | */ | |
643 | struct dwc3_event_buffer { | |
644 | void *buf; | |
d9fa4c63 | 645 | void *cache; |
87b923a2 | 646 | unsigned int length; |
72246da4 | 647 | unsigned int lpos; |
60d04bbe | 648 | unsigned int count; |
abed4118 FB |
649 | unsigned int flags; |
650 | ||
651 | #define DWC3_EVENT_PENDING BIT(0) | |
72246da4 FB |
652 | |
653 | dma_addr_t dma; | |
654 | ||
655 | struct dwc3 *dwc; | |
656 | }; | |
657 | ||
ff3f0789 RQ |
658 | #define DWC3_EP_FLAG_STALLED BIT(0) |
659 | #define DWC3_EP_FLAG_WEDGED BIT(1) | |
72246da4 FB |
660 | |
661 | #define DWC3_EP_DIRECTION_TX true | |
662 | #define DWC3_EP_DIRECTION_RX false | |
663 | ||
8495036e | 664 | #define DWC3_TRB_NUM 256 |
72246da4 FB |
665 | |
666 | /** | |
667 | * struct dwc3_ep - device side endpoint representation | |
668 | * @endpoint: usb endpoint | |
d5443bbf | 669 | * @cancelled_list: list of cancelled requests for this endpoint |
aa3342c8 FB |
670 | * @pending_list: list of pending requests for this endpoint |
671 | * @started_list: list of started requests on this endpoint | |
2eb88016 | 672 | * @regs: pointer to first endpoint register |
72246da4 FB |
673 | * @trb_pool: array of transaction buffers |
674 | * @trb_pool_dma: dma address of @trb_pool | |
53fd8818 FB |
675 | * @trb_enqueue: enqueue 'pointer' into TRB array |
676 | * @trb_dequeue: dequeue 'pointer' into TRB array | |
72246da4 | 677 | * @dwc: pointer to DWC controller |
4cfcf876 | 678 | * @saved_state: ep state saved during hibernation |
72246da4 | 679 | * @flags: endpoint flags (wedged, stalled, ...) |
72246da4 FB |
680 | * @number: endpoint number (1 - 15) |
681 | * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK | |
b4996a86 | 682 | * @resource_index: Resource transfer index |
502a37b9 | 683 | * @frame_number: set to the frame number we want this transfer to start (ISOC) |
c75f52fb | 684 | * @interval: the interval on which the ISOC transfer is started |
72246da4 FB |
685 | * @name: a human readable name e.g. ep1out-bulk |
686 | * @direction: true for TX, false for RX | |
879631aa | 687 | * @stream_capable: true when streams are enabled |
d92021f6 TN |
688 | * @combo_num: the test combination BIT[15:14] of the frame number to test |
689 | * isochronous START TRANSFER command failure workaround | |
690 | * @start_cmd_status: the status of testing START TRANSFER command with | |
691 | * combo_num = 'b00 | |
72246da4 FB |
692 | */ |
693 | struct dwc3_ep { | |
694 | struct usb_ep endpoint; | |
d5443bbf | 695 | struct list_head cancelled_list; |
aa3342c8 FB |
696 | struct list_head pending_list; |
697 | struct list_head started_list; | |
72246da4 | 698 | |
2eb88016 FB |
699 | void __iomem *regs; |
700 | ||
f6bafc6a | 701 | struct dwc3_trb *trb_pool; |
72246da4 | 702 | dma_addr_t trb_pool_dma; |
72246da4 FB |
703 | struct dwc3 *dwc; |
704 | ||
4cfcf876 | 705 | u32 saved_state; |
87b923a2 | 706 | unsigned int flags; |
ff3f0789 RQ |
707 | #define DWC3_EP_ENABLED BIT(0) |
708 | #define DWC3_EP_STALL BIT(1) | |
709 | #define DWC3_EP_WEDGE BIT(2) | |
5f2e7975 | 710 | #define DWC3_EP_TRANSFER_STARTED BIT(3) |
c58d8bfc | 711 | #define DWC3_EP_END_TRANSFER_PENDING BIT(4) |
ff3f0789 | 712 | #define DWC3_EP_PENDING_REQUEST BIT(5) |
da10bcdd | 713 | #define DWC3_EP_DELAY_START BIT(6) |
e0d19563 | 714 | #define DWC3_EP_WAIT_TRANSFER_COMPLETE BIT(7) |
140ca4cf TN |
715 | #define DWC3_EP_IGNORE_NEXT_NOSTREAM BIT(8) |
716 | #define DWC3_EP_FORCE_RESTART_STREAM BIT(9) | |
717 | #define DWC3_EP_FIRST_STREAM_PRIMED BIT(10) | |
d97c78a1 | 718 | #define DWC3_EP_PENDING_CLEAR_STALL BIT(11) |
72246da4 | 719 | |
984f66a6 | 720 | /* This last one is specific to EP0 */ |
ff3f0789 | 721 | #define DWC3_EP0_DIR_IN BIT(31) |
984f66a6 | 722 | |
c28f8259 FB |
723 | /* |
724 | * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will | |
725 | * use a u8 type here. If anybody decides to increase number of TRBs to | |
726 | * anything larger than 256 - I can't see why people would want to do | |
727 | * this though - then this type needs to be changed. | |
728 | * | |
729 | * By using u8 types we ensure that our % operator when incrementing | |
730 | * enqueue and dequeue get optimized away by the compiler. | |
731 | */ | |
732 | u8 trb_enqueue; | |
733 | u8 trb_dequeue; | |
734 | ||
72246da4 FB |
735 | u8 number; |
736 | u8 type; | |
b4996a86 | 737 | u8 resource_index; |
502a37b9 | 738 | u32 frame_number; |
72246da4 FB |
739 | u32 interval; |
740 | ||
741 | char name[20]; | |
742 | ||
743 | unsigned direction:1; | |
879631aa | 744 | unsigned stream_capable:1; |
d92021f6 TN |
745 | |
746 | /* For isochronous START TRANSFER workaround only */ | |
747 | u8 combo_num; | |
748 | int start_cmd_status; | |
72246da4 FB |
749 | }; |
750 | ||
751 | enum dwc3_phy { | |
752 | DWC3_PHY_UNKNOWN = 0, | |
753 | DWC3_PHY_USB3, | |
754 | DWC3_PHY_USB2, | |
755 | }; | |
756 | ||
b53c772d FB |
757 | enum dwc3_ep0_next { |
758 | DWC3_EP0_UNKNOWN = 0, | |
759 | DWC3_EP0_COMPLETE, | |
b53c772d FB |
760 | DWC3_EP0_NRDY_DATA, |
761 | DWC3_EP0_NRDY_STATUS, | |
762 | }; | |
763 | ||
72246da4 FB |
764 | enum dwc3_ep0_state { |
765 | EP0_UNCONNECTED = 0, | |
c7fcdeb2 FB |
766 | EP0_SETUP_PHASE, |
767 | EP0_DATA_PHASE, | |
768 | EP0_STATUS_PHASE, | |
72246da4 FB |
769 | }; |
770 | ||
771 | enum dwc3_link_state { | |
772 | /* In SuperSpeed */ | |
773 | DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ | |
774 | DWC3_LINK_STATE_U1 = 0x01, | |
775 | DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ | |
776 | DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ | |
777 | DWC3_LINK_STATE_SS_DIS = 0x04, | |
778 | DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ | |
779 | DWC3_LINK_STATE_SS_INACT = 0x06, | |
780 | DWC3_LINK_STATE_POLL = 0x07, | |
781 | DWC3_LINK_STATE_RECOV = 0x08, | |
782 | DWC3_LINK_STATE_HRESET = 0x09, | |
783 | DWC3_LINK_STATE_CMPLY = 0x0a, | |
784 | DWC3_LINK_STATE_LPBK = 0x0b, | |
2c61a8ef PZ |
785 | DWC3_LINK_STATE_RESET = 0x0e, |
786 | DWC3_LINK_STATE_RESUME = 0x0f, | |
72246da4 FB |
787 | DWC3_LINK_STATE_MASK = 0x0f, |
788 | }; | |
789 | ||
f6bafc6a FB |
790 | /* TRB Length, PCM and Status */ |
791 | #define DWC3_TRB_SIZE_MASK (0x00ffffff) | |
792 | #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) | |
793 | #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) | |
389f2828 | 794 | #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) |
f6bafc6a FB |
795 | |
796 | #define DWC3_TRBSTS_OK 0 | |
797 | #define DWC3_TRBSTS_MISSED_ISOC 1 | |
798 | #define DWC3_TRBSTS_SETUP_PENDING 2 | |
2c61a8ef | 799 | #define DWC3_TRB_STS_XFER_IN_PROG 4 |
f6bafc6a FB |
800 | |
801 | /* TRB Control */ | |
ff3f0789 RQ |
802 | #define DWC3_TRB_CTRL_HWO BIT(0) |
803 | #define DWC3_TRB_CTRL_LST BIT(1) | |
804 | #define DWC3_TRB_CTRL_CHN BIT(2) | |
805 | #define DWC3_TRB_CTRL_CSP BIT(3) | |
f6bafc6a | 806 | #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) |
ff3f0789 RQ |
807 | #define DWC3_TRB_CTRL_ISP_IMI BIT(10) |
808 | #define DWC3_TRB_CTRL_IOC BIT(11) | |
f6bafc6a | 809 | #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) |
6abfa0f5 | 810 | #define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14) |
f6bafc6a | 811 | |
b058f3e8 | 812 | #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4)) |
f6bafc6a FB |
813 | #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) |
814 | #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) | |
815 | #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) | |
816 | #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) | |
817 | #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) | |
818 | #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) | |
819 | #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) | |
820 | #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) | |
72246da4 FB |
821 | |
822 | /** | |
f6bafc6a | 823 | * struct dwc3_trb - transfer request block (hw format) |
72246da4 FB |
824 | * @bpl: DW0-3 |
825 | * @bph: DW4-7 | |
826 | * @size: DW8-B | |
bfad65ee | 827 | * @ctrl: DWC-F |
72246da4 | 828 | */ |
f6bafc6a FB |
829 | struct dwc3_trb { |
830 | u32 bpl; | |
831 | u32 bph; | |
832 | u32 size; | |
833 | u32 ctrl; | |
72246da4 FB |
834 | } __packed; |
835 | ||
a3299499 | 836 | /** |
bfad65ee FB |
837 | * struct dwc3_hwparams - copy of HWPARAMS registers |
838 | * @hwparams0: GHWPARAMS0 | |
839 | * @hwparams1: GHWPARAMS1 | |
840 | * @hwparams2: GHWPARAMS2 | |
841 | * @hwparams3: GHWPARAMS3 | |
842 | * @hwparams4: GHWPARAMS4 | |
843 | * @hwparams5: GHWPARAMS5 | |
844 | * @hwparams6: GHWPARAMS6 | |
845 | * @hwparams7: GHWPARAMS7 | |
846 | * @hwparams8: GHWPARAMS8 | |
a3299499 FB |
847 | */ |
848 | struct dwc3_hwparams { | |
849 | u32 hwparams0; | |
850 | u32 hwparams1; | |
851 | u32 hwparams2; | |
852 | u32 hwparams3; | |
853 | u32 hwparams4; | |
854 | u32 hwparams5; | |
855 | u32 hwparams6; | |
856 | u32 hwparams7; | |
857 | u32 hwparams8; | |
858 | }; | |
859 | ||
0949e99b FB |
860 | /* HWPARAMS0 */ |
861 | #define DWC3_MODE(n) ((n) & 0x7) | |
862 | ||
457e84b6 FB |
863 | #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) |
864 | ||
0949e99b | 865 | /* HWPARAMS1 */ |
457e84b6 FB |
866 | #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) |
867 | ||
789451f6 FB |
868 | /* HWPARAMS3 */ |
869 | #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) | |
870 | #define DWC3_NUM_EPS_MASK (0x3f << 12) | |
871 | #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ | |
872 | (DWC3_NUM_EPS_MASK)) >> 12) | |
873 | #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ | |
874 | (DWC3_NUM_IN_EPS_MASK)) >> 18) | |
875 | ||
457e84b6 FB |
876 | /* HWPARAMS7 */ |
877 | #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) | |
9f622b2a | 878 | |
5ef68c56 FB |
879 | /** |
880 | * struct dwc3_request - representation of a transfer request | |
881 | * @request: struct usb_request to be transferred | |
882 | * @list: a list_head used for request queueing | |
883 | * @dep: struct dwc3_ep owning this request | |
0b3e4af3 | 884 | * @sg: pointer to first incomplete sg |
a31e63b6 | 885 | * @start_sg: pointer to the sg which should be queued next |
0b3e4af3 | 886 | * @num_pending_sgs: counter to pending sgs |
c96e6725 | 887 | * @num_queued_sgs: counter to the number of sgs which already got queued |
e62c5bc5 | 888 | * @remaining: amount of data remaining |
a3af5e3a | 889 | * @status: internal dwc3 request status tracking |
5ef68c56 FB |
890 | * @epnum: endpoint number to which this request refers |
891 | * @trb: pointer to struct dwc3_trb | |
892 | * @trb_dma: DMA address of @trb | |
09fe1f8d | 893 | * @num_trbs: number of TRBs used by this request |
1a22ec64 FB |
894 | * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP |
895 | * or unaligned OUT) | |
5ef68c56 FB |
896 | * @direction: IN or OUT direction flag |
897 | * @mapped: true when request has been dma-mapped | |
5ef68c56 | 898 | */ |
e0ce0b0a SAS |
899 | struct dwc3_request { |
900 | struct usb_request request; | |
901 | struct list_head list; | |
902 | struct dwc3_ep *dep; | |
0b3e4af3 | 903 | struct scatterlist *sg; |
a31e63b6 | 904 | struct scatterlist *start_sg; |
e0ce0b0a | 905 | |
87b923a2 | 906 | unsigned int num_pending_sgs; |
c96e6725 | 907 | unsigned int num_queued_sgs; |
87b923a2 | 908 | unsigned int remaining; |
a3af5e3a FB |
909 | |
910 | unsigned int status; | |
911 | #define DWC3_REQUEST_STATUS_QUEUED 0 | |
912 | #define DWC3_REQUEST_STATUS_STARTED 1 | |
913 | #define DWC3_REQUEST_STATUS_CANCELLED 2 | |
914 | #define DWC3_REQUEST_STATUS_COMPLETED 3 | |
915 | #define DWC3_REQUEST_STATUS_UNKNOWN -1 | |
916 | ||
e0ce0b0a | 917 | u8 epnum; |
f6bafc6a | 918 | struct dwc3_trb *trb; |
e0ce0b0a SAS |
919 | dma_addr_t trb_dma; |
920 | ||
87b923a2 | 921 | unsigned int num_trbs; |
09fe1f8d | 922 | |
87b923a2 FB |
923 | unsigned int needs_extra_trb:1; |
924 | unsigned int direction:1; | |
925 | unsigned int mapped:1; | |
e0ce0b0a SAS |
926 | }; |
927 | ||
2c61a8ef PZ |
928 | /* |
929 | * struct dwc3_scratchpad_array - hibernation scratchpad array | |
930 | * (format defined by hw) | |
931 | */ | |
932 | struct dwc3_scratchpad_array { | |
933 | __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; | |
934 | }; | |
935 | ||
72246da4 FB |
936 | /** |
937 | * struct dwc3 - representation of our controller | |
bfad65ee | 938 | * @drd_work: workqueue used for role swapping |
91db07dc | 939 | * @ep0_trb: trb which is used for the ctrl_req |
bfad65ee FB |
940 | * @bounce: address of bounce buffer |
941 | * @scratchbuf: address of scratch buffer | |
91db07dc | 942 | * @setup_buf: used while precessing STD USB requests |
bfad65ee FB |
943 | * @ep0_trb_addr: dma address of @ep0_trb |
944 | * @bounce_addr: dma address of @bounce | |
91db07dc | 945 | * @ep0_usb_req: dummy req used while handling STD USB requests |
0ffcaf37 | 946 | * @scratch_addr: dma address of scratchbuf |
bb014736 | 947 | * @ep0_in_setup: one control transfer is completed and enter setup phase |
72246da4 FB |
948 | * @lock: for synchronizing |
949 | * @dev: pointer to our struct device | |
bfad65ee | 950 | * @sysdev: pointer to the DMA-capable device |
d07e8819 | 951 | * @xhci: pointer to our xHCI child |
bfad65ee FB |
952 | * @xhci_resources: struct resources for our @xhci child |
953 | * @ev_buf: struct dwc3_event_buffer pointer | |
954 | * @eps: endpoint array | |
72246da4 FB |
955 | * @gadget: device side representation of the peripheral controller |
956 | * @gadget_driver: pointer to the gadget driver | |
fe8abf33 MY |
957 | * @clks: array of clocks |
958 | * @num_clks: number of clocks | |
959 | * @reset: reset control | |
72246da4 FB |
960 | * @regs: base address for our registers |
961 | * @regs_size: address space size | |
bcdb3272 | 962 | * @fladj: frame length adjustment |
3f308d17 | 963 | * @irq_gadget: peripheral controller's IRQ number |
f09cc79b RQ |
964 | * @otg_irq: IRQ number for OTG IRQs |
965 | * @current_otg_role: current role of operation while using the OTG block | |
966 | * @desired_otg_role: desired role of operation while using the OTG block | |
967 | * @otg_restart_host: flag that OTG controller needs to restart host | |
0ffcaf37 | 968 | * @nr_scratch: number of scratch buffers |
fae2b904 | 969 | * @u1u2: only used on revisions <1.83a for workaround |
6c167fc9 | 970 | * @maximum_speed: maximum speed requested (mainly for testing purposes) |
67848146 | 971 | * @max_ssp_rate: SuperSpeed Plus maximum signaling rate and lane count |
5dc71f1e | 972 | * @gadget_max_speed: maximum gadget speed requested |
072cab8a TN |
973 | * @gadget_ssp_rate: Gadget driver's maximum supported SuperSpeed Plus signaling |
974 | * rate and lane count. | |
9af21dd6 TN |
975 | * @ip: controller's ID |
976 | * @revision: controller's version of an IP | |
475d8e01 | 977 | * @version_type: VERSIONTYPE register contents, a sub release of a revision |
a45c82b8 | 978 | * @dr_mode: requested mode of operation |
6b3261a2 | 979 | * @current_dr_role: current role of operation when in dual-role mode |
41ce1456 | 980 | * @desired_dr_role: desired role of operation when in dual-role mode |
9840354f RQ |
981 | * @edev: extcon handle |
982 | * @edev_nb: extcon notifier | |
32f2ed86 WW |
983 | * @hsphy_mode: UTMI phy mode, one of following: |
984 | * - USBPHY_INTERFACE_MODE_UTMI | |
985 | * - USBPHY_INTERFACE_MODE_UTMIW | |
8a0a1379 | 986 | * @role_sw: usb_role_switch handle |
98ed256a JS |
987 | * @role_switch_default_mode: default operation mode of controller while |
988 | * usb role is USB_ROLE_NONE. | |
0f3edf99 | 989 | * @usb_psy: pointer to power supply interface. |
51e1e7bc FB |
990 | * @usb2_phy: pointer to USB2 PHY |
991 | * @usb3_phy: pointer to USB3 PHY | |
57303488 KVA |
992 | * @usb2_generic_phy: pointer to USB2 PHY |
993 | * @usb3_generic_phy: pointer to USB3 PHY | |
98112041 | 994 | * @phys_ready: flag to indicate that PHYs are ready |
88bc9d19 | 995 | * @ulpi: pointer to ulpi interface |
98112041 | 996 | * @ulpi_ready: flag to indicate that ULPI is initialized |
865e09e7 FB |
997 | * @u2sel: parameter from Set SEL request. |
998 | * @u2pel: parameter from Set SEL request. | |
999 | * @u1sel: parameter from Set SEL request. | |
1000 | * @u1pel: parameter from Set SEL request. | |
47d3946e | 1001 | * @num_eps: number of endpoints |
b53c772d | 1002 | * @ep0_next_event: hold the next expected event |
72246da4 FB |
1003 | * @ep0state: state of endpoint zero |
1004 | * @link_state: link state | |
1005 | * @speed: device speed (super, high, full, low) | |
a3299499 | 1006 | * @hwparams: copy of hwparams registers |
72246da4 | 1007 | * @root: debugfs root folder pointer |
f2b685d5 | 1008 | * @regset: debugfs pointer to regdump file |
62ba09d6 | 1009 | * @dbg_lsp_select: current debug lsp mux register selection |
f2b685d5 FB |
1010 | * @test_mode: true when we're entering a USB test mode |
1011 | * @test_mode_nr: test feature selector | |
80caf7d2 | 1012 | * @lpm_nyet_threshold: LPM NYET response threshold |
460d098c | 1013 | * @hird_threshold: HIRD threshold |
938a5ad1 TN |
1014 | * @rx_thr_num_pkt_prd: periodic ESS receive packet count |
1015 | * @rx_max_burst_prd: max periodic ESS receive burst size | |
1016 | * @tx_thr_num_pkt_prd: periodic ESS transmit packet count | |
1017 | * @tx_max_burst_prd: max periodic ESS transmit burst size | |
3e10a2ce | 1018 | * @hsphy_interface: "utmi" or "ulpi" |
fc8bb91b | 1019 | * @connected: true when we're connected to a host, false otherwise |
f2b685d5 FB |
1020 | * @delayed_status: true when gadget driver asks for delayed status |
1021 | * @ep0_bounced: true when we used bounce buffer | |
1022 | * @ep0_expect_in: true when we expect a DATA IN transfer | |
81bc5599 | 1023 | * @has_hibernation: true when dwc3 was configured with Hibernation |
d64ff406 | 1024 | * @sysdev_is_parent: true when dwc3 device has a parent driver |
80caf7d2 HR |
1025 | * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that |
1026 | * there's now way for software to detect this in runtime. | |
460d098c | 1027 | * @is_utmi_l1_suspend: the core asserts output signal |
87b923a2 FB |
1028 | * 0 - utmi_sleep_n |
1029 | * 1 - utmi_l1_suspend_n | |
946bd579 | 1030 | * @is_fpga: true when we are using the FPGA board |
fc8bb91b | 1031 | * @pending_events: true when we have pending IRQs to be handled |
f2b685d5 | 1032 | * @pullups_connected: true when Run/Stop bit is set |
f2b685d5 | 1033 | * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround |
f2b685d5 | 1034 | * @three_stage_setup: set if we perform a three phase setup |
d92021f6 TN |
1035 | * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is |
1036 | * not needed for DWC_usb31 version 1.70a-ea06 and below | |
eac68e8f | 1037 | * @usb3_lpm_capable: set if hadrware supports Link Power Management |
022a0208 | 1038 | * @usb2_lpm_disable: set to disable usb2 lpm |
3b81221a | 1039 | * @disable_scramble_quirk: set if we enable the disable scramble quirk |
9a5b2f31 | 1040 | * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk |
b5a65c40 | 1041 | * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk |
df31f5b3 | 1042 | * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk |
a2a1d0f5 | 1043 | * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk |
41c06ffd | 1044 | * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk |
fb67afca | 1045 | * @lfps_filter_quirk: set if we enable LFPS filter quirk |
14f4ac53 | 1046 | * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk |
59acfa20 | 1047 | * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy |
0effe0a3 | 1048 | * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy |
ec791d14 JY |
1049 | * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, |
1050 | * disabling the suspend signal to the PHY. | |
729dcffd AKV |
1051 | * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled. |
1052 | * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled. | |
bfad65ee | 1053 | * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3 |
16199f33 WW |
1054 | * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists |
1055 | * in GUSB2PHYCFG, specify that USB2 PHY doesn't | |
1056 | * provide a free-running PHY clock. | |
00fe081d WW |
1057 | * @dis_del_phy_power_chg_quirk: set if we disable delay phy power |
1058 | * change quirk. | |
65db7a0c WW |
1059 | * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate |
1060 | * check during HS transmit. | |
7ba6b09f NA |
1061 | * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed |
1062 | * instances in park mode. | |
6b6a0c9a HR |
1063 | * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk |
1064 | * @tx_de_emphasis: Tx de-emphasis value | |
87b923a2 FB |
1065 | * 0 - -6dB de-emphasis |
1066 | * 1 - -3.5dB de-emphasis | |
1067 | * 2 - No de-emphasis | |
1068 | * 3 - Reserved | |
42bf02ec | 1069 | * @dis_metastability_quirk: set to disable metastability quirk. |
f580170f | 1070 | * @dis_split_quirk: set to disable split boundary. |
cf40b86b | 1071 | * @imod_interval: set the interrupt moderation interval in 250ns |
87b923a2 | 1072 | * increments or 0 to disable. |
72246da4 FB |
1073 | */ |
1074 | struct dwc3 { | |
41ce1456 | 1075 | struct work_struct drd_work; |
f6bafc6a | 1076 | struct dwc3_trb *ep0_trb; |
905dc04e | 1077 | void *bounce; |
0ffcaf37 | 1078 | void *scratchbuf; |
72246da4 | 1079 | u8 *setup_buf; |
72246da4 | 1080 | dma_addr_t ep0_trb_addr; |
905dc04e | 1081 | dma_addr_t bounce_addr; |
0ffcaf37 | 1082 | dma_addr_t scratch_addr; |
e0ce0b0a | 1083 | struct dwc3_request ep0_usb_req; |
bb014736 | 1084 | struct completion ep0_in_setup; |
789451f6 | 1085 | |
72246da4 FB |
1086 | /* device lock */ |
1087 | spinlock_t lock; | |
789451f6 | 1088 | |
72246da4 | 1089 | struct device *dev; |
d64ff406 | 1090 | struct device *sysdev; |
72246da4 | 1091 | |
d07e8819 | 1092 | struct platform_device *xhci; |
51249dca | 1093 | struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; |
d07e8819 | 1094 | |
696c8b12 | 1095 | struct dwc3_event_buffer *ev_buf; |
72246da4 FB |
1096 | struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; |
1097 | ||
e81a7018 | 1098 | struct usb_gadget *gadget; |
72246da4 FB |
1099 | struct usb_gadget_driver *gadget_driver; |
1100 | ||
fe8abf33 MY |
1101 | struct clk_bulk_data *clks; |
1102 | int num_clks; | |
1103 | ||
1104 | struct reset_control *reset; | |
1105 | ||
51e1e7bc FB |
1106 | struct usb_phy *usb2_phy; |
1107 | struct usb_phy *usb3_phy; | |
1108 | ||
57303488 KVA |
1109 | struct phy *usb2_generic_phy; |
1110 | struct phy *usb3_generic_phy; | |
1111 | ||
98112041 RQ |
1112 | bool phys_ready; |
1113 | ||
88bc9d19 | 1114 | struct ulpi *ulpi; |
98112041 | 1115 | bool ulpi_ready; |
88bc9d19 | 1116 | |
72246da4 FB |
1117 | void __iomem *regs; |
1118 | size_t regs_size; | |
1119 | ||
a45c82b8 | 1120 | enum usb_dr_mode dr_mode; |
6b3261a2 | 1121 | u32 current_dr_role; |
41ce1456 | 1122 | u32 desired_dr_role; |
9840354f RQ |
1123 | struct extcon_dev *edev; |
1124 | struct notifier_block edev_nb; | |
32f2ed86 | 1125 | enum usb_phy_interface hsphy_mode; |
8a0a1379 | 1126 | struct usb_role_switch *role_sw; |
98ed256a | 1127 | enum usb_dr_mode role_switch_default_mode; |
a45c82b8 | 1128 | |
6f0764b5 RC |
1129 | struct power_supply *usb_psy; |
1130 | ||
bcdb3272 | 1131 | u32 fladj; |
3f308d17 | 1132 | u32 irq_gadget; |
f09cc79b RQ |
1133 | u32 otg_irq; |
1134 | u32 current_otg_role; | |
1135 | u32 desired_otg_role; | |
1136 | bool otg_restart_host; | |
0ffcaf37 | 1137 | u32 nr_scratch; |
fae2b904 | 1138 | u32 u1u2; |
6c167fc9 | 1139 | u32 maximum_speed; |
7c9a2598 | 1140 | u32 gadget_max_speed; |
67848146 | 1141 | enum usb_ssp_rate max_ssp_rate; |
072cab8a | 1142 | enum usb_ssp_rate gadget_ssp_rate; |
690fb371 | 1143 | |
9af21dd6 TN |
1144 | u32 ip; |
1145 | ||
1146 | #define DWC3_IP 0x5533 | |
1147 | #define DWC31_IP 0x3331 | |
1148 | #define DWC32_IP 0x3332 | |
1149 | ||
72246da4 FB |
1150 | u32 revision; |
1151 | ||
9af21dd6 | 1152 | #define DWC3_REVISION_ANY 0x0 |
72246da4 FB |
1153 | #define DWC3_REVISION_173A 0x5533173a |
1154 | #define DWC3_REVISION_175A 0x5533175a | |
1155 | #define DWC3_REVISION_180A 0x5533180a | |
1156 | #define DWC3_REVISION_183A 0x5533183a | |
1157 | #define DWC3_REVISION_185A 0x5533185a | |
2c61a8ef | 1158 | #define DWC3_REVISION_187A 0x5533187a |
72246da4 FB |
1159 | #define DWC3_REVISION_188A 0x5533188a |
1160 | #define DWC3_REVISION_190A 0x5533190a | |
2c61a8ef | 1161 | #define DWC3_REVISION_194A 0x5533194a |
1522d703 FB |
1162 | #define DWC3_REVISION_200A 0x5533200a |
1163 | #define DWC3_REVISION_202A 0x5533202a | |
1164 | #define DWC3_REVISION_210A 0x5533210a | |
1165 | #define DWC3_REVISION_220A 0x5533220a | |
7ac6a593 FB |
1166 | #define DWC3_REVISION_230A 0x5533230a |
1167 | #define DWC3_REVISION_240A 0x5533240a | |
1168 | #define DWC3_REVISION_250A 0x5533250a | |
dbf5aaf7 FB |
1169 | #define DWC3_REVISION_260A 0x5533260a |
1170 | #define DWC3_REVISION_270A 0x5533270a | |
1171 | #define DWC3_REVISION_280A 0x5533280a | |
0bb39ca1 | 1172 | #define DWC3_REVISION_290A 0x5533290a |
512e4757 JY |
1173 | #define DWC3_REVISION_300A 0x5533300a |
1174 | #define DWC3_REVISION_310A 0x5533310a | |
89a9cc47 | 1175 | #define DWC3_REVISION_330A 0x5533330a |
72246da4 | 1176 | |
9af21dd6 TN |
1177 | #define DWC31_REVISION_ANY 0x0 |
1178 | #define DWC31_REVISION_110A 0x3131302a | |
1179 | #define DWC31_REVISION_120A 0x3132302a | |
1180 | #define DWC31_REVISION_160A 0x3136302a | |
1181 | #define DWC31_REVISION_170A 0x3137302a | |
1182 | #define DWC31_REVISION_180A 0x3138302a | |
1183 | #define DWC31_REVISION_190A 0x3139302a | |
690fb371 | 1184 | |
b10e1c25 TN |
1185 | #define DWC32_REVISION_ANY 0x0 |
1186 | #define DWC32_REVISION_100A 0x3130302a | |
1187 | ||
475d8e01 TN |
1188 | u32 version_type; |
1189 | ||
9af21dd6 | 1190 | #define DWC31_VERSIONTYPE_ANY 0x0 |
475d8e01 TN |
1191 | #define DWC31_VERSIONTYPE_EA01 0x65613031 |
1192 | #define DWC31_VERSIONTYPE_EA02 0x65613032 | |
1193 | #define DWC31_VERSIONTYPE_EA03 0x65613033 | |
1194 | #define DWC31_VERSIONTYPE_EA04 0x65613034 | |
1195 | #define DWC31_VERSIONTYPE_EA05 0x65613035 | |
1196 | #define DWC31_VERSIONTYPE_EA06 0x65613036 | |
1197 | ||
b53c772d | 1198 | enum dwc3_ep0_next ep0_next_event; |
72246da4 FB |
1199 | enum dwc3_ep0_state ep0state; |
1200 | enum dwc3_link_state link_state; | |
72246da4 | 1201 | |
865e09e7 FB |
1202 | u16 u2sel; |
1203 | u16 u2pel; | |
1204 | u8 u1sel; | |
1205 | u8 u1pel; | |
1206 | ||
72246da4 | 1207 | u8 speed; |
865e09e7 | 1208 | |
47d3946e | 1209 | u8 num_eps; |
789451f6 | 1210 | |
a3299499 | 1211 | struct dwc3_hwparams hwparams; |
72246da4 | 1212 | struct dentry *root; |
d7668024 | 1213 | struct debugfs_regset32 *regset; |
3b637367 | 1214 | |
62ba09d6 TN |
1215 | u32 dbg_lsp_select; |
1216 | ||
3b637367 GC |
1217 | u8 test_mode; |
1218 | u8 test_mode_nr; | |
80caf7d2 | 1219 | u8 lpm_nyet_threshold; |
460d098c | 1220 | u8 hird_threshold; |
938a5ad1 TN |
1221 | u8 rx_thr_num_pkt_prd; |
1222 | u8 rx_max_burst_prd; | |
1223 | u8 tx_thr_num_pkt_prd; | |
1224 | u8 tx_max_burst_prd; | |
f2b685d5 | 1225 | |
3e10a2ce HK |
1226 | const char *hsphy_interface; |
1227 | ||
fc8bb91b | 1228 | unsigned connected:1; |
f2b685d5 FB |
1229 | unsigned delayed_status:1; |
1230 | unsigned ep0_bounced:1; | |
1231 | unsigned ep0_expect_in:1; | |
81bc5599 | 1232 | unsigned has_hibernation:1; |
d64ff406 | 1233 | unsigned sysdev_is_parent:1; |
80caf7d2 | 1234 | unsigned has_lpm_erratum:1; |
460d098c | 1235 | unsigned is_utmi_l1_suspend:1; |
946bd579 | 1236 | unsigned is_fpga:1; |
fc8bb91b | 1237 | unsigned pending_events:1; |
f2b685d5 | 1238 | unsigned pullups_connected:1; |
f2b685d5 | 1239 | unsigned setup_packet_pending:1; |
f2b685d5 | 1240 | unsigned three_stage_setup:1; |
d92021f6 | 1241 | unsigned dis_start_transfer_quirk:1; |
eac68e8f | 1242 | unsigned usb3_lpm_capable:1; |
022a0208 | 1243 | unsigned usb2_lpm_disable:1; |
3b81221a HR |
1244 | |
1245 | unsigned disable_scramble_quirk:1; | |
9a5b2f31 | 1246 | unsigned u2exit_lfps_quirk:1; |
b5a65c40 | 1247 | unsigned u2ss_inp3_quirk:1; |
df31f5b3 | 1248 | unsigned req_p1p2p3_quirk:1; |
a2a1d0f5 | 1249 | unsigned del_p1p2p3_quirk:1; |
41c06ffd | 1250 | unsigned del_phy_power_chg_quirk:1; |
fb67afca | 1251 | unsigned lfps_filter_quirk:1; |
14f4ac53 | 1252 | unsigned rx_detect_poll_quirk:1; |
59acfa20 | 1253 | unsigned dis_u3_susphy_quirk:1; |
0effe0a3 | 1254 | unsigned dis_u2_susphy_quirk:1; |
ec791d14 | 1255 | unsigned dis_enblslpm_quirk:1; |
729dcffd AKV |
1256 | unsigned dis_u1_entry_quirk:1; |
1257 | unsigned dis_u2_entry_quirk:1; | |
e58dd357 | 1258 | unsigned dis_rxdet_inp3_quirk:1; |
16199f33 | 1259 | unsigned dis_u2_freeclk_exists_quirk:1; |
00fe081d | 1260 | unsigned dis_del_phy_power_chg_quirk:1; |
65db7a0c | 1261 | unsigned dis_tx_ipgap_linecheck_quirk:1; |
7ba6b09f | 1262 | unsigned parkmode_disable_ss_quirk:1; |
6b6a0c9a HR |
1263 | |
1264 | unsigned tx_de_emphasis_quirk:1; | |
1265 | unsigned tx_de_emphasis:2; | |
cf40b86b | 1266 | |
42bf02ec RQ |
1267 | unsigned dis_metastability_quirk:1; |
1268 | ||
f580170f YC |
1269 | unsigned dis_split_quirk:1; |
1270 | ||
cf40b86b | 1271 | u16 imod_interval; |
72246da4 FB |
1272 | }; |
1273 | ||
d9612c2f PM |
1274 | #define INCRX_BURST_MODE 0 |
1275 | #define INCRX_UNDEF_LENGTH_BURST_MODE 1 | |
1276 | ||
41ce1456 | 1277 | #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work)) |
72246da4 | 1278 | |
72246da4 FB |
1279 | /* -------------------------------------------------------------------------- */ |
1280 | ||
1281 | struct dwc3_event_type { | |
1282 | u32 is_devspec:1; | |
1974d494 HR |
1283 | u32 type:7; |
1284 | u32 reserved8_31:24; | |
72246da4 FB |
1285 | } __packed; |
1286 | ||
1287 | #define DWC3_DEPEVT_XFERCOMPLETE 0x01 | |
1288 | #define DWC3_DEPEVT_XFERINPROGRESS 0x02 | |
1289 | #define DWC3_DEPEVT_XFERNOTREADY 0x03 | |
1290 | #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 | |
1291 | #define DWC3_DEPEVT_STREAMEVT 0x06 | |
1292 | #define DWC3_DEPEVT_EPCMDCMPLT 0x07 | |
1293 | ||
1294 | /** | |
cbdc0f54 | 1295 | * struct dwc3_event_depevt - Device Endpoint Events |
72246da4 FB |
1296 | * @one_bit: indicates this is an endpoint event (not used) |
1297 | * @endpoint_number: number of the endpoint | |
1298 | * @endpoint_event: The event we have: | |
1299 | * 0x00 - Reserved | |
1300 | * 0x01 - XferComplete | |
1301 | * 0x02 - XferInProgress | |
1302 | * 0x03 - XferNotReady | |
1303 | * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) | |
1304 | * 0x05 - Reserved | |
1305 | * 0x06 - StreamEvt | |
1306 | * 0x07 - EPCmdCmplt | |
1307 | * @reserved11_10: Reserved, don't use. | |
1308 | * @status: Indicates the status of the event. Refer to databook for | |
1309 | * more information. | |
1310 | * @parameters: Parameters of the current event. Refer to databook for | |
1311 | * more information. | |
1312 | */ | |
1313 | struct dwc3_event_depevt { | |
1314 | u32 one_bit:1; | |
1315 | u32 endpoint_number:5; | |
1316 | u32 endpoint_event:4; | |
1317 | u32 reserved11_10:2; | |
1318 | u32 status:4; | |
40aa41fb FB |
1319 | |
1320 | /* Within XferNotReady */ | |
ff3f0789 | 1321 | #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3) |
40aa41fb | 1322 | |
6d8a0196 | 1323 | /* Within XferComplete or XferInProgress */ |
ff3f0789 RQ |
1324 | #define DEPEVT_STATUS_BUSERR BIT(0) |
1325 | #define DEPEVT_STATUS_SHORT BIT(1) | |
1326 | #define DEPEVT_STATUS_IOC BIT(2) | |
6d8a0196 FB |
1327 | #define DEPEVT_STATUS_LST BIT(3) /* XferComplete */ |
1328 | #define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */ | |
dc137f01 | 1329 | |
879631aa FB |
1330 | /* Stream event only */ |
1331 | #define DEPEVT_STREAMEVT_FOUND 1 | |
1332 | #define DEPEVT_STREAMEVT_NOTFOUND 2 | |
1333 | ||
140ca4cf TN |
1334 | /* Stream event parameter */ |
1335 | #define DEPEVT_STREAM_PRIME 0xfffe | |
1336 | #define DEPEVT_STREAM_NOSTREAM 0x0 | |
1337 | ||
dc137f01 | 1338 | /* Control-only Status */ |
dc137f01 FB |
1339 | #define DEPEVT_STATUS_CONTROL_DATA 1 |
1340 | #define DEPEVT_STATUS_CONTROL_STATUS 2 | |
45a2af2f | 1341 | #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3) |
dc137f01 | 1342 | |
7b9cc7a2 KL |
1343 | /* In response to Start Transfer */ |
1344 | #define DEPEVT_TRANSFER_NO_RESOURCE 1 | |
1345 | #define DEPEVT_TRANSFER_BUS_EXPIRY 2 | |
1346 | ||
72246da4 | 1347 | u32 parameters:16; |
76a638f8 BW |
1348 | |
1349 | /* For Command Complete Events */ | |
1350 | #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8) | |
72246da4 FB |
1351 | } __packed; |
1352 | ||
1353 | /** | |
1354 | * struct dwc3_event_devt - Device Events | |
1355 | * @one_bit: indicates this is a non-endpoint event (not used) | |
1356 | * @device_event: indicates it's a device event. Should read as 0x00 | |
1357 | * @type: indicates the type of device event. | |
1358 | * 0 - DisconnEvt | |
1359 | * 1 - USBRst | |
1360 | * 2 - ConnectDone | |
1361 | * 3 - ULStChng | |
1362 | * 4 - WkUpEvt | |
1363 | * 5 - Reserved | |
1364 | * 6 - EOPF | |
1365 | * 7 - SOF | |
1366 | * 8 - Reserved | |
1367 | * 9 - ErrticErr | |
1368 | * 10 - CmdCmplt | |
1369 | * 11 - EvntOverflow | |
1370 | * 12 - VndrDevTstRcved | |
1371 | * @reserved15_12: Reserved, not used | |
1372 | * @event_info: Information about this event | |
06f9b6e5 | 1373 | * @reserved31_25: Reserved, not used |
72246da4 FB |
1374 | */ |
1375 | struct dwc3_event_devt { | |
1376 | u32 one_bit:1; | |
1377 | u32 device_event:7; | |
1378 | u32 type:4; | |
1379 | u32 reserved15_12:4; | |
06f9b6e5 HR |
1380 | u32 event_info:9; |
1381 | u32 reserved31_25:7; | |
72246da4 FB |
1382 | } __packed; |
1383 | ||
1384 | /** | |
1385 | * struct dwc3_event_gevt - Other Core Events | |
1386 | * @one_bit: indicates this is a non-endpoint event (not used) | |
1387 | * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. | |
1388 | * @phy_port_number: self-explanatory | |
1389 | * @reserved31_12: Reserved, not used. | |
1390 | */ | |
1391 | struct dwc3_event_gevt { | |
1392 | u32 one_bit:1; | |
1393 | u32 device_event:7; | |
1394 | u32 phy_port_number:4; | |
1395 | u32 reserved31_12:20; | |
1396 | } __packed; | |
1397 | ||
1398 | /** | |
1399 | * union dwc3_event - representation of Event Buffer contents | |
1400 | * @raw: raw 32-bit event | |
1401 | * @type: the type of the event | |
1402 | * @depevt: Device Endpoint Event | |
1403 | * @devt: Device Event | |
1404 | * @gevt: Global Event | |
1405 | */ | |
1406 | union dwc3_event { | |
1407 | u32 raw; | |
1408 | struct dwc3_event_type type; | |
1409 | struct dwc3_event_depevt depevt; | |
1410 | struct dwc3_event_devt devt; | |
1411 | struct dwc3_event_gevt gevt; | |
1412 | }; | |
1413 | ||
61018305 FB |
1414 | /** |
1415 | * struct dwc3_gadget_ep_cmd_params - representation of endpoint command | |
1416 | * parameters | |
1417 | * @param2: third parameter | |
1418 | * @param1: second parameter | |
1419 | * @param0: first parameter | |
1420 | */ | |
1421 | struct dwc3_gadget_ep_cmd_params { | |
1422 | u32 param2; | |
1423 | u32 param1; | |
1424 | u32 param0; | |
1425 | }; | |
1426 | ||
72246da4 FB |
1427 | /* |
1428 | * DWC3 Features to be used as Driver Data | |
1429 | */ | |
1430 | ||
1431 | #define DWC3_HAS_PERIPHERAL BIT(0) | |
1432 | #define DWC3_HAS_XHCI BIT(1) | |
1433 | #define DWC3_HAS_OTG BIT(3) | |
1434 | ||
d07e8819 | 1435 | /* prototypes */ |
f09cc79b | 1436 | void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode); |
3140e8cb | 1437 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode); |
cf6d867d | 1438 | u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type); |
3140e8cb | 1439 | |
9af21dd6 TN |
1440 | #define DWC3_IP_IS(_ip) \ |
1441 | (dwc->ip == _ip##_IP) | |
1442 | ||
1443 | #define DWC3_VER_IS(_ip, _ver) \ | |
1444 | (DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver) | |
1445 | ||
1446 | #define DWC3_VER_IS_PRIOR(_ip, _ver) \ | |
1447 | (DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver) | |
1448 | ||
1449 | #define DWC3_VER_IS_WITHIN(_ip, _from, _to) \ | |
1450 | (DWC3_IP_IS(_ip) && \ | |
1451 | dwc->revision >= _ip##_REVISION_##_from && \ | |
1452 | (!(_ip##_REVISION_##_to) || \ | |
1453 | dwc->revision <= _ip##_REVISION_##_to)) | |
1454 | ||
1455 | #define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to) \ | |
1456 | (DWC3_VER_IS(_ip, _ver) && \ | |
1457 | dwc->version_type >= _ip##_VERSIONTYPE_##_from && \ | |
1458 | (!(_ip##_VERSIONTYPE_##_to) || \ | |
1459 | dwc->version_type <= _ip##_VERSIONTYPE_##_to)) | |
c4137a9c | 1460 | |
cf40b86b JY |
1461 | bool dwc3_has_imod(struct dwc3 *dwc); |
1462 | ||
f09cc79b RQ |
1463 | int dwc3_event_buffers_setup(struct dwc3 *dwc); |
1464 | void dwc3_event_buffers_cleanup(struct dwc3 *dwc); | |
1465 | ||
388e5c51 | 1466 | #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
d07e8819 FB |
1467 | int dwc3_host_init(struct dwc3 *dwc); |
1468 | void dwc3_host_exit(struct dwc3 *dwc); | |
388e5c51 VG |
1469 | #else |
1470 | static inline int dwc3_host_init(struct dwc3 *dwc) | |
1471 | { return 0; } | |
1472 | static inline void dwc3_host_exit(struct dwc3 *dwc) | |
1473 | { } | |
1474 | #endif | |
1475 | ||
1476 | #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) | |
f80b45e7 FB |
1477 | int dwc3_gadget_init(struct dwc3 *dwc); |
1478 | void dwc3_gadget_exit(struct dwc3 *dwc); | |
61018305 FB |
1479 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); |
1480 | int dwc3_gadget_get_link_state(struct dwc3 *dwc); | |
1481 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); | |
87b923a2 | 1482 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, |
2cd4718d | 1483 | struct dwc3_gadget_ep_cmd_params *params); |
87b923a2 FB |
1484 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, |
1485 | u32 param); | |
388e5c51 VG |
1486 | #else |
1487 | static inline int dwc3_gadget_init(struct dwc3 *dwc) | |
1488 | { return 0; } | |
1489 | static inline void dwc3_gadget_exit(struct dwc3 *dwc) | |
1490 | { } | |
61018305 FB |
1491 | static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) |
1492 | { return 0; } | |
1493 | static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
1494 | { return 0; } | |
1495 | static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, | |
1496 | enum dwc3_link_state state) | |
1497 | { return 0; } | |
1498 | ||
87b923a2 | 1499 | static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, |
2cd4718d | 1500 | struct dwc3_gadget_ep_cmd_params *params) |
61018305 FB |
1501 | { return 0; } |
1502 | static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, | |
1503 | int cmd, u32 param) | |
1504 | { return 0; } | |
388e5c51 | 1505 | #endif |
f80b45e7 | 1506 | |
9840354f RQ |
1507 | #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
1508 | int dwc3_drd_init(struct dwc3 *dwc); | |
1509 | void dwc3_drd_exit(struct dwc3 *dwc); | |
f09cc79b RQ |
1510 | void dwc3_otg_init(struct dwc3 *dwc); |
1511 | void dwc3_otg_exit(struct dwc3 *dwc); | |
1512 | void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus); | |
1513 | void dwc3_otg_host_init(struct dwc3 *dwc); | |
9840354f RQ |
1514 | #else |
1515 | static inline int dwc3_drd_init(struct dwc3 *dwc) | |
1516 | { return 0; } | |
1517 | static inline void dwc3_drd_exit(struct dwc3 *dwc) | |
1518 | { } | |
f09cc79b RQ |
1519 | static inline void dwc3_otg_init(struct dwc3 *dwc) |
1520 | { } | |
1521 | static inline void dwc3_otg_exit(struct dwc3 *dwc) | |
1522 | { } | |
1523 | static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) | |
1524 | { } | |
1525 | static inline void dwc3_otg_host_init(struct dwc3 *dwc) | |
1526 | { } | |
9840354f RQ |
1527 | #endif |
1528 | ||
7415f17c FB |
1529 | /* power management interface */ |
1530 | #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) | |
7415f17c FB |
1531 | int dwc3_gadget_suspend(struct dwc3 *dwc); |
1532 | int dwc3_gadget_resume(struct dwc3 *dwc); | |
fc8bb91b | 1533 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc); |
7415f17c | 1534 | #else |
7415f17c FB |
1535 | static inline int dwc3_gadget_suspend(struct dwc3 *dwc) |
1536 | { | |
1537 | return 0; | |
1538 | } | |
1539 | ||
1540 | static inline int dwc3_gadget_resume(struct dwc3 *dwc) | |
1541 | { | |
1542 | return 0; | |
1543 | } | |
fc8bb91b FB |
1544 | |
1545 | static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc) | |
1546 | { | |
1547 | } | |
7415f17c FB |
1548 | #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ |
1549 | ||
88bc9d19 HK |
1550 | #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) |
1551 | int dwc3_ulpi_init(struct dwc3 *dwc); | |
1552 | void dwc3_ulpi_exit(struct dwc3 *dwc); | |
1553 | #else | |
1554 | static inline int dwc3_ulpi_init(struct dwc3 *dwc) | |
1555 | { return 0; } | |
1556 | static inline void dwc3_ulpi_exit(struct dwc3 *dwc) | |
1557 | { } | |
1558 | #endif | |
1559 | ||
72246da4 | 1560 | #endif /* __DRIVERS_USB_DWC3_CORE_H */ |