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72246da4 FB |
1 | /** |
2 | * core.c - DesignWare USB3 DRD Controller Core file | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 | 17 | * |
5945f789 FB |
18 | * You should have received a copy of the GNU General Public License |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
72246da4 FB |
20 | */ |
21 | ||
fa0ea13e | 22 | #include <linux/version.h> |
a72e658b | 23 | #include <linux/module.h> |
72246da4 FB |
24 | #include <linux/kernel.h> |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/pm_runtime.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/list.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
457e84b6 | 35 | #include <linux/of.h> |
404905a6 | 36 | #include <linux/acpi.h> |
6344475f | 37 | #include <linux/pinctrl/consumer.h> |
72246da4 FB |
38 | |
39 | #include <linux/usb/ch9.h> | |
40 | #include <linux/usb/gadget.h> | |
f7e846f0 | 41 | #include <linux/usb/of.h> |
a45c82b8 | 42 | #include <linux/usb/otg.h> |
72246da4 FB |
43 | |
44 | #include "core.h" | |
45 | #include "gadget.h" | |
46 | #include "io.h" | |
47 | ||
48 | #include "debug.h" | |
49 | ||
fc8bb91b | 50 | #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ |
8300dd23 | 51 | |
9d6173e1 TN |
52 | /** |
53 | * dwc3_get_dr_mode - Validates and sets dr_mode | |
54 | * @dwc: pointer to our context structure | |
55 | */ | |
56 | static int dwc3_get_dr_mode(struct dwc3 *dwc) | |
57 | { | |
58 | enum usb_dr_mode mode; | |
59 | struct device *dev = dwc->dev; | |
60 | unsigned int hw_mode; | |
61 | ||
62 | if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) | |
63 | dwc->dr_mode = USB_DR_MODE_OTG; | |
64 | ||
65 | mode = dwc->dr_mode; | |
66 | hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); | |
67 | ||
68 | switch (hw_mode) { | |
69 | case DWC3_GHWPARAMS0_MODE_GADGET: | |
70 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { | |
71 | dev_err(dev, | |
72 | "Controller does not support host mode.\n"); | |
73 | return -EINVAL; | |
74 | } | |
75 | mode = USB_DR_MODE_PERIPHERAL; | |
76 | break; | |
77 | case DWC3_GHWPARAMS0_MODE_HOST: | |
78 | if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { | |
79 | dev_err(dev, | |
80 | "Controller does not support device mode.\n"); | |
81 | return -EINVAL; | |
82 | } | |
83 | mode = USB_DR_MODE_HOST; | |
84 | break; | |
85 | default: | |
86 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) | |
87 | mode = USB_DR_MODE_HOST; | |
88 | else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) | |
89 | mode = USB_DR_MODE_PERIPHERAL; | |
90 | } | |
91 | ||
92 | if (mode != dwc->dr_mode) { | |
93 | dev_warn(dev, | |
94 | "Configuration mismatch. dr_mode forced to %s\n", | |
95 | mode == USB_DR_MODE_HOST ? "host" : "gadget"); | |
96 | ||
97 | dwc->dr_mode = mode; | |
98 | } | |
99 | ||
100 | return 0; | |
101 | } | |
102 | ||
3140e8cb SAS |
103 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode) |
104 | { | |
105 | u32 reg; | |
106 | ||
107 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
108 | reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); | |
109 | reg |= DWC3_GCTL_PRTCAPDIR(mode); | |
110 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
111 | } | |
8300dd23 | 112 | |
cf6d867d FB |
113 | u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) |
114 | { | |
115 | struct dwc3 *dwc = dep->dwc; | |
116 | u32 reg; | |
117 | ||
118 | dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, | |
119 | DWC3_GDBGFIFOSPACE_NUM(dep->number) | | |
120 | DWC3_GDBGFIFOSPACE_TYPE(type)); | |
121 | ||
122 | reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); | |
123 | ||
124 | return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); | |
125 | } | |
126 | ||
72246da4 FB |
127 | /** |
128 | * dwc3_core_soft_reset - Issues core soft reset and PHY reset | |
129 | * @dwc: pointer to our context structure | |
130 | */ | |
57303488 | 131 | static int dwc3_core_soft_reset(struct dwc3 *dwc) |
72246da4 FB |
132 | { |
133 | u32 reg; | |
f59dcab1 | 134 | int retries = 1000; |
57303488 | 135 | int ret; |
72246da4 | 136 | |
51e1e7bc FB |
137 | usb_phy_init(dwc->usb2_phy); |
138 | usb_phy_init(dwc->usb3_phy); | |
57303488 KVA |
139 | ret = phy_init(dwc->usb2_generic_phy); |
140 | if (ret < 0) | |
141 | return ret; | |
142 | ||
143 | ret = phy_init(dwc->usb3_generic_phy); | |
144 | if (ret < 0) { | |
145 | phy_exit(dwc->usb2_generic_phy); | |
146 | return ret; | |
147 | } | |
72246da4 | 148 | |
f59dcab1 FB |
149 | /* |
150 | * We're resetting only the device side because, if we're in host mode, | |
151 | * XHCI driver will reset the host block. If dwc3 was configured for | |
152 | * host-only mode, then we can return early. | |
153 | */ | |
154 | if (dwc->dr_mode == USB_DR_MODE_HOST) | |
155 | return 0; | |
72246da4 | 156 | |
f59dcab1 FB |
157 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
158 | reg |= DWC3_DCTL_CSFTRST; | |
159 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 160 | |
f59dcab1 FB |
161 | do { |
162 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
163 | if (!(reg & DWC3_DCTL_CSFTRST)) | |
164 | return 0; | |
45627ac6 | 165 | |
f59dcab1 FB |
166 | udelay(1); |
167 | } while (--retries); | |
57303488 | 168 | |
f59dcab1 | 169 | return -ETIMEDOUT; |
72246da4 FB |
170 | } |
171 | ||
db2be4e9 NB |
172 | /* |
173 | * dwc3_frame_length_adjustment - Adjusts frame length if required | |
174 | * @dwc3: Pointer to our controller context structure | |
db2be4e9 | 175 | */ |
bcdb3272 | 176 | static void dwc3_frame_length_adjustment(struct dwc3 *dwc) |
db2be4e9 NB |
177 | { |
178 | u32 reg; | |
179 | u32 dft; | |
180 | ||
181 | if (dwc->revision < DWC3_REVISION_250A) | |
182 | return; | |
183 | ||
bcdb3272 | 184 | if (dwc->fladj == 0) |
db2be4e9 NB |
185 | return; |
186 | ||
187 | reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); | |
188 | dft = reg & DWC3_GFLADJ_30MHZ_MASK; | |
bcdb3272 | 189 | if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj, |
db2be4e9 NB |
190 | "request value same as default, ignoring\n")) { |
191 | reg &= ~DWC3_GFLADJ_30MHZ_MASK; | |
bcdb3272 | 192 | reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; |
db2be4e9 NB |
193 | dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); |
194 | } | |
195 | } | |
196 | ||
72246da4 FB |
197 | /** |
198 | * dwc3_free_one_event_buffer - Frees one event buffer | |
199 | * @dwc: Pointer to our controller context structure | |
200 | * @evt: Pointer to event buffer to be freed | |
201 | */ | |
202 | static void dwc3_free_one_event_buffer(struct dwc3 *dwc, | |
203 | struct dwc3_event_buffer *evt) | |
204 | { | |
d64ff406 | 205 | dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); |
72246da4 FB |
206 | } |
207 | ||
208 | /** | |
1d046793 | 209 | * dwc3_alloc_one_event_buffer - Allocates one event buffer structure |
72246da4 FB |
210 | * @dwc: Pointer to our controller context structure |
211 | * @length: size of the event buffer | |
212 | * | |
1d046793 | 213 | * Returns a pointer to the allocated event buffer structure on success |
72246da4 FB |
214 | * otherwise ERR_PTR(errno). |
215 | */ | |
67d0b500 FB |
216 | static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, |
217 | unsigned length) | |
72246da4 FB |
218 | { |
219 | struct dwc3_event_buffer *evt; | |
220 | ||
380f0d28 | 221 | evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); |
72246da4 FB |
222 | if (!evt) |
223 | return ERR_PTR(-ENOMEM); | |
224 | ||
225 | evt->dwc = dwc; | |
226 | evt->length = length; | |
d9fa4c63 JY |
227 | evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); |
228 | if (!evt->cache) | |
229 | return ERR_PTR(-ENOMEM); | |
230 | ||
d64ff406 | 231 | evt->buf = dma_alloc_coherent(dwc->sysdev, length, |
72246da4 | 232 | &evt->dma, GFP_KERNEL); |
e32672f0 | 233 | if (!evt->buf) |
72246da4 | 234 | return ERR_PTR(-ENOMEM); |
72246da4 FB |
235 | |
236 | return evt; | |
237 | } | |
238 | ||
239 | /** | |
240 | * dwc3_free_event_buffers - frees all allocated event buffers | |
241 | * @dwc: Pointer to our controller context structure | |
242 | */ | |
243 | static void dwc3_free_event_buffers(struct dwc3 *dwc) | |
244 | { | |
245 | struct dwc3_event_buffer *evt; | |
72246da4 | 246 | |
696c8b12 | 247 | evt = dwc->ev_buf; |
660e9bde FB |
248 | if (evt) |
249 | dwc3_free_one_event_buffer(dwc, evt); | |
72246da4 FB |
250 | } |
251 | ||
252 | /** | |
253 | * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length | |
1d046793 | 254 | * @dwc: pointer to our controller context structure |
72246da4 FB |
255 | * @length: size of event buffer |
256 | * | |
1d046793 | 257 | * Returns 0 on success otherwise negative errno. In the error case, dwc |
72246da4 FB |
258 | * may contain some buffers allocated but not all which were requested. |
259 | */ | |
41ac7b3a | 260 | static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) |
72246da4 | 261 | { |
660e9bde | 262 | struct dwc3_event_buffer *evt; |
72246da4 | 263 | |
660e9bde FB |
264 | evt = dwc3_alloc_one_event_buffer(dwc, length); |
265 | if (IS_ERR(evt)) { | |
266 | dev_err(dwc->dev, "can't allocate event buffer\n"); | |
267 | return PTR_ERR(evt); | |
72246da4 | 268 | } |
696c8b12 | 269 | dwc->ev_buf = evt; |
72246da4 FB |
270 | |
271 | return 0; | |
272 | } | |
273 | ||
274 | /** | |
275 | * dwc3_event_buffers_setup - setup our allocated event buffers | |
1d046793 | 276 | * @dwc: pointer to our controller context structure |
72246da4 FB |
277 | * |
278 | * Returns 0 on success otherwise negative errno. | |
279 | */ | |
7acd85e0 | 280 | static int dwc3_event_buffers_setup(struct dwc3 *dwc) |
72246da4 FB |
281 | { |
282 | struct dwc3_event_buffer *evt; | |
72246da4 | 283 | |
696c8b12 | 284 | evt = dwc->ev_buf; |
660e9bde | 285 | evt->lpos = 0; |
660e9bde FB |
286 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), |
287 | lower_32_bits(evt->dma)); | |
288 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), | |
289 | upper_32_bits(evt->dma)); | |
290 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), | |
291 | DWC3_GEVNTSIZ_SIZE(evt->length)); | |
292 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); | |
72246da4 FB |
293 | |
294 | return 0; | |
295 | } | |
296 | ||
297 | static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) | |
298 | { | |
299 | struct dwc3_event_buffer *evt; | |
72246da4 | 300 | |
696c8b12 | 301 | evt = dwc->ev_buf; |
7acd85e0 | 302 | |
660e9bde | 303 | evt->lpos = 0; |
7acd85e0 | 304 | |
660e9bde FB |
305 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); |
306 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); | |
307 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK | |
308 | | DWC3_GEVNTSIZ_SIZE(0)); | |
309 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); | |
72246da4 FB |
310 | } |
311 | ||
0ffcaf37 FB |
312 | static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) |
313 | { | |
314 | if (!dwc->has_hibernation) | |
315 | return 0; | |
316 | ||
317 | if (!dwc->nr_scratch) | |
318 | return 0; | |
319 | ||
320 | dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, | |
321 | DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); | |
322 | if (!dwc->scratchbuf) | |
323 | return -ENOMEM; | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
328 | static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) | |
329 | { | |
330 | dma_addr_t scratch_addr; | |
331 | u32 param; | |
332 | int ret; | |
333 | ||
334 | if (!dwc->has_hibernation) | |
335 | return 0; | |
336 | ||
337 | if (!dwc->nr_scratch) | |
338 | return 0; | |
339 | ||
340 | /* should never fall here */ | |
341 | if (!WARN_ON(dwc->scratchbuf)) | |
342 | return 0; | |
343 | ||
d64ff406 | 344 | scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, |
0ffcaf37 FB |
345 | dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, |
346 | DMA_BIDIRECTIONAL); | |
d64ff406 AB |
347 | if (dma_mapping_error(dwc->sysdev, scratch_addr)) { |
348 | dev_err(dwc->sysdev, "failed to map scratch buffer\n"); | |
0ffcaf37 FB |
349 | ret = -EFAULT; |
350 | goto err0; | |
351 | } | |
352 | ||
353 | dwc->scratch_addr = scratch_addr; | |
354 | ||
355 | param = lower_32_bits(scratch_addr); | |
356 | ||
357 | ret = dwc3_send_gadget_generic_command(dwc, | |
358 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); | |
359 | if (ret < 0) | |
360 | goto err1; | |
361 | ||
362 | param = upper_32_bits(scratch_addr); | |
363 | ||
364 | ret = dwc3_send_gadget_generic_command(dwc, | |
365 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); | |
366 | if (ret < 0) | |
367 | goto err1; | |
368 | ||
369 | return 0; | |
370 | ||
371 | err1: | |
d64ff406 | 372 | dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * |
0ffcaf37 FB |
373 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); |
374 | ||
375 | err0: | |
376 | return ret; | |
377 | } | |
378 | ||
379 | static void dwc3_free_scratch_buffers(struct dwc3 *dwc) | |
380 | { | |
381 | if (!dwc->has_hibernation) | |
382 | return; | |
383 | ||
384 | if (!dwc->nr_scratch) | |
385 | return; | |
386 | ||
387 | /* should never fall here */ | |
388 | if (!WARN_ON(dwc->scratchbuf)) | |
389 | return; | |
390 | ||
d64ff406 | 391 | dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * |
0ffcaf37 FB |
392 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); |
393 | kfree(dwc->scratchbuf); | |
394 | } | |
395 | ||
789451f6 FB |
396 | static void dwc3_core_num_eps(struct dwc3 *dwc) |
397 | { | |
398 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
399 | ||
47d3946e | 400 | dwc->num_eps = DWC3_NUM_EPS(parms); |
789451f6 FB |
401 | } |
402 | ||
41ac7b3a | 403 | static void dwc3_cache_hwparams(struct dwc3 *dwc) |
26ceca97 FB |
404 | { |
405 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
406 | ||
407 | parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); | |
408 | parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); | |
409 | parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); | |
410 | parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); | |
411 | parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); | |
412 | parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); | |
413 | parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); | |
414 | parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); | |
415 | parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); | |
416 | } | |
417 | ||
b5a65c40 HR |
418 | /** |
419 | * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core | |
420 | * @dwc: Pointer to our controller context structure | |
88bc9d19 HK |
421 | * |
422 | * Returns 0 on success. The USB PHY interfaces are configured but not | |
423 | * initialized. The PHY interfaces and the PHYs get initialized together with | |
424 | * the core in dwc3_core_init. | |
b5a65c40 | 425 | */ |
88bc9d19 | 426 | static int dwc3_phy_setup(struct dwc3 *dwc) |
b5a65c40 HR |
427 | { |
428 | u32 reg; | |
88bc9d19 | 429 | int ret; |
b5a65c40 HR |
430 | |
431 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
432 | ||
1966b865 FB |
433 | /* |
434 | * Make sure UX_EXIT_PX is cleared as that causes issues with some | |
435 | * PHYs. Also, this bit is not supposed to be used in normal operation. | |
436 | */ | |
437 | reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; | |
438 | ||
2164a476 HR |
439 | /* |
440 | * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY | |
441 | * to '0' during coreConsultant configuration. So default value | |
442 | * will be '0' when the core is reset. Application needs to set it | |
443 | * to '1' after the core initialization is completed. | |
444 | */ | |
445 | if (dwc->revision > DWC3_REVISION_194A) | |
446 | reg |= DWC3_GUSB3PIPECTL_SUSPHY; | |
447 | ||
b5a65c40 HR |
448 | if (dwc->u2ss_inp3_quirk) |
449 | reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; | |
450 | ||
e58dd357 RB |
451 | if (dwc->dis_rxdet_inp3_quirk) |
452 | reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; | |
453 | ||
df31f5b3 HR |
454 | if (dwc->req_p1p2p3_quirk) |
455 | reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; | |
456 | ||
a2a1d0f5 HR |
457 | if (dwc->del_p1p2p3_quirk) |
458 | reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; | |
459 | ||
41c06ffd HR |
460 | if (dwc->del_phy_power_chg_quirk) |
461 | reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; | |
462 | ||
fb67afca HR |
463 | if (dwc->lfps_filter_quirk) |
464 | reg |= DWC3_GUSB3PIPECTL_LFPSFILT; | |
465 | ||
14f4ac53 HR |
466 | if (dwc->rx_detect_poll_quirk) |
467 | reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; | |
468 | ||
6b6a0c9a HR |
469 | if (dwc->tx_de_emphasis_quirk) |
470 | reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); | |
471 | ||
cd72f890 | 472 | if (dwc->dis_u3_susphy_quirk) |
59acfa20 HR |
473 | reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; |
474 | ||
00fe081d WW |
475 | if (dwc->dis_del_phy_power_chg_quirk) |
476 | reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; | |
477 | ||
b5a65c40 HR |
478 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); |
479 | ||
2164a476 HR |
480 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
481 | ||
3e10a2ce HK |
482 | /* Select the HS PHY interface */ |
483 | switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { | |
484 | case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: | |
43cacb03 FB |
485 | if (dwc->hsphy_interface && |
486 | !strncmp(dwc->hsphy_interface, "utmi", 4)) { | |
3e10a2ce | 487 | reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; |
88bc9d19 | 488 | break; |
43cacb03 FB |
489 | } else if (dwc->hsphy_interface && |
490 | !strncmp(dwc->hsphy_interface, "ulpi", 4)) { | |
3e10a2ce | 491 | reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; |
88bc9d19 | 492 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
3e10a2ce | 493 | } else { |
88bc9d19 HK |
494 | /* Relying on default value. */ |
495 | if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) | |
496 | break; | |
3e10a2ce HK |
497 | } |
498 | /* FALLTHROUGH */ | |
88bc9d19 | 499 | case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: |
88bc9d19 HK |
500 | ret = dwc3_ulpi_init(dwc); |
501 | if (ret) | |
502 | return ret; | |
503 | /* FALLTHROUGH */ | |
3e10a2ce HK |
504 | default: |
505 | break; | |
506 | } | |
507 | ||
32f2ed86 WW |
508 | switch (dwc->hsphy_mode) { |
509 | case USBPHY_INTERFACE_MODE_UTMI: | |
510 | reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | | |
511 | DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); | |
512 | reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | | |
513 | DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); | |
514 | break; | |
515 | case USBPHY_INTERFACE_MODE_UTMIW: | |
516 | reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | | |
517 | DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); | |
518 | reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | | |
519 | DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); | |
520 | break; | |
521 | default: | |
522 | break; | |
523 | } | |
524 | ||
2164a476 HR |
525 | /* |
526 | * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to | |
527 | * '0' during coreConsultant configuration. So default value will | |
528 | * be '0' when the core is reset. Application needs to set it to | |
529 | * '1' after the core initialization is completed. | |
530 | */ | |
531 | if (dwc->revision > DWC3_REVISION_194A) | |
532 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; | |
533 | ||
cd72f890 | 534 | if (dwc->dis_u2_susphy_quirk) |
0effe0a3 HR |
535 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; |
536 | ||
ec791d14 JY |
537 | if (dwc->dis_enblslpm_quirk) |
538 | reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; | |
539 | ||
16199f33 WW |
540 | if (dwc->dis_u2_freeclk_exists_quirk) |
541 | reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; | |
542 | ||
2164a476 | 543 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
88bc9d19 HK |
544 | |
545 | return 0; | |
b5a65c40 HR |
546 | } |
547 | ||
c499ff71 FB |
548 | static void dwc3_core_exit(struct dwc3 *dwc) |
549 | { | |
550 | dwc3_event_buffers_cleanup(dwc); | |
551 | ||
552 | usb_phy_shutdown(dwc->usb2_phy); | |
553 | usb_phy_shutdown(dwc->usb3_phy); | |
554 | phy_exit(dwc->usb2_generic_phy); | |
555 | phy_exit(dwc->usb3_generic_phy); | |
556 | ||
557 | usb_phy_set_suspend(dwc->usb2_phy, 1); | |
558 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
559 | phy_power_off(dwc->usb2_generic_phy); | |
560 | phy_power_off(dwc->usb3_generic_phy); | |
561 | } | |
562 | ||
0759956f | 563 | static bool dwc3_core_is_valid(struct dwc3 *dwc) |
72246da4 | 564 | { |
0759956f | 565 | u32 reg; |
72246da4 | 566 | |
7650bd74 | 567 | reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); |
0759956f | 568 | |
7650bd74 | 569 | /* This should read as U3 followed by revision number */ |
690fb371 JY |
570 | if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { |
571 | /* Detected DWC_usb3 IP */ | |
572 | dwc->revision = reg; | |
573 | } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { | |
574 | /* Detected DWC_usb31 IP */ | |
575 | dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); | |
576 | dwc->revision |= DWC3_REVISION_IS_DWC31; | |
577 | } else { | |
0759956f | 578 | return false; |
7650bd74 | 579 | } |
7650bd74 | 580 | |
0759956f FB |
581 | return true; |
582 | } | |
58a0f23f | 583 | |
941f918e | 584 | static void dwc3_core_setup_global_control(struct dwc3 *dwc) |
0759956f | 585 | { |
941f918e FB |
586 | u32 hwparams4 = dwc->hwparams.hwparams4; |
587 | u32 reg; | |
c499ff71 | 588 | |
4878a028 | 589 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); |
3e87c42a | 590 | reg &= ~DWC3_GCTL_SCALEDOWN_MASK; |
4878a028 | 591 | |
164d7731 | 592 | switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { |
4878a028 | 593 | case DWC3_GHWPARAMS1_EN_PWROPT_CLK: |
32a4a135 FB |
594 | /** |
595 | * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an | |
596 | * issue which would cause xHCI compliance tests to fail. | |
597 | * | |
598 | * Because of that we cannot enable clock gating on such | |
599 | * configurations. | |
600 | * | |
601 | * Refers to: | |
602 | * | |
603 | * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based | |
604 | * SOF/ITP Mode Used | |
605 | */ | |
606 | if ((dwc->dr_mode == USB_DR_MODE_HOST || | |
607 | dwc->dr_mode == USB_DR_MODE_OTG) && | |
608 | (dwc->revision >= DWC3_REVISION_210A && | |
609 | dwc->revision <= DWC3_REVISION_250A)) | |
610 | reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; | |
611 | else | |
612 | reg &= ~DWC3_GCTL_DSBLCLKGTNG; | |
4878a028 | 613 | break; |
0ffcaf37 FB |
614 | case DWC3_GHWPARAMS1_EN_PWROPT_HIB: |
615 | /* enable hibernation here */ | |
616 | dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); | |
2eac3992 HR |
617 | |
618 | /* | |
619 | * REVISIT Enabling this bit so that host-mode hibernation | |
620 | * will work. Device-mode hibernation is not yet implemented. | |
621 | */ | |
622 | reg |= DWC3_GCTL_GBLHIBERNATIONEN; | |
0ffcaf37 | 623 | break; |
4878a028 | 624 | default: |
5eb30ced FB |
625 | /* nothing */ |
626 | break; | |
4878a028 SAS |
627 | } |
628 | ||
946bd579 HR |
629 | /* check if current dwc3 is on simulation board */ |
630 | if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { | |
5eb30ced | 631 | dev_info(dwc->dev, "Running with FPGA optmizations\n"); |
946bd579 HR |
632 | dwc->is_fpga = true; |
633 | } | |
634 | ||
3b81221a HR |
635 | WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, |
636 | "disable_scramble cannot be used on non-FPGA builds\n"); | |
637 | ||
638 | if (dwc->disable_scramble_quirk && dwc->is_fpga) | |
639 | reg |= DWC3_GCTL_DISSCRAMBLE; | |
640 | else | |
641 | reg &= ~DWC3_GCTL_DISSCRAMBLE; | |
642 | ||
9a5b2f31 HR |
643 | if (dwc->u2exit_lfps_quirk) |
644 | reg |= DWC3_GCTL_U2EXIT_LFPS; | |
645 | ||
4878a028 SAS |
646 | /* |
647 | * WORKAROUND: DWC3 revisions <1.90a have a bug | |
1d046793 | 648 | * where the device can fail to connect at SuperSpeed |
4878a028 | 649 | * and falls back to high-speed mode which causes |
1d046793 | 650 | * the device to enter a Connect/Disconnect loop |
4878a028 SAS |
651 | */ |
652 | if (dwc->revision < DWC3_REVISION_190A) | |
653 | reg |= DWC3_GCTL_U2RSTECN; | |
654 | ||
655 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
941f918e FB |
656 | } |
657 | ||
658 | /** | |
659 | * dwc3_core_init - Low-level initialization of DWC3 Core | |
660 | * @dwc: Pointer to our controller context structure | |
661 | * | |
662 | * Returns 0 on success otherwise negative errno. | |
663 | */ | |
664 | static int dwc3_core_init(struct dwc3 *dwc) | |
665 | { | |
666 | u32 reg; | |
667 | int ret; | |
668 | ||
669 | if (!dwc3_core_is_valid(dwc)) { | |
670 | dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); | |
671 | ret = -ENODEV; | |
672 | goto err0; | |
673 | } | |
674 | ||
675 | /* | |
676 | * Write Linux Version Code to our GUID register so it's easy to figure | |
677 | * out which kernel version a bug was found. | |
678 | */ | |
679 | dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); | |
680 | ||
681 | /* Handle USB2.0-only core configuration */ | |
682 | if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == | |
683 | DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { | |
684 | if (dwc->maximum_speed == USB_SPEED_SUPER) | |
685 | dwc->maximum_speed = USB_SPEED_HIGH; | |
686 | } | |
687 | ||
941f918e FB |
688 | ret = dwc3_core_soft_reset(dwc); |
689 | if (ret) | |
690 | goto err0; | |
4878a028 | 691 | |
941f918e FB |
692 | ret = dwc3_phy_setup(dwc); |
693 | if (ret) | |
694 | goto err0; | |
4878a028 | 695 | |
941f918e | 696 | dwc3_core_setup_global_control(dwc); |
c499ff71 | 697 | dwc3_core_num_eps(dwc); |
0ffcaf37 FB |
698 | |
699 | ret = dwc3_setup_scratch_buffers(dwc); | |
700 | if (ret) | |
c499ff71 FB |
701 | goto err1; |
702 | ||
703 | /* Adjust Frame Length */ | |
704 | dwc3_frame_length_adjustment(dwc); | |
705 | ||
706 | usb_phy_set_suspend(dwc->usb2_phy, 0); | |
707 | usb_phy_set_suspend(dwc->usb3_phy, 0); | |
708 | ret = phy_power_on(dwc->usb2_generic_phy); | |
709 | if (ret < 0) | |
0ffcaf37 FB |
710 | goto err2; |
711 | ||
c499ff71 FB |
712 | ret = phy_power_on(dwc->usb3_generic_phy); |
713 | if (ret < 0) | |
714 | goto err3; | |
715 | ||
716 | ret = dwc3_event_buffers_setup(dwc); | |
717 | if (ret) { | |
718 | dev_err(dwc->dev, "failed to setup event buffers\n"); | |
719 | goto err4; | |
720 | } | |
721 | ||
00af6233 BW |
722 | switch (dwc->dr_mode) { |
723 | case USB_DR_MODE_PERIPHERAL: | |
724 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); | |
725 | break; | |
726 | case USB_DR_MODE_HOST: | |
727 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); | |
728 | break; | |
729 | case USB_DR_MODE_OTG: | |
730 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); | |
731 | break; | |
732 | default: | |
733 | dev_warn(dwc->dev, "Unsupported mode %d\n", dwc->dr_mode); | |
734 | break; | |
735 | } | |
736 | ||
06281d46 JY |
737 | /* |
738 | * ENDXFER polling is available on version 3.10a and later of | |
739 | * the DWC_usb3 controller. It is NOT available in the | |
740 | * DWC_usb31 controller. | |
741 | */ | |
742 | if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) { | |
743 | reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); | |
744 | reg |= DWC3_GUCTL2_RST_ACTBITLATER; | |
745 | dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); | |
746 | } | |
747 | ||
0bb39ca1 JY |
748 | /* |
749 | * Enable hardware control of sending remote wakeup in HS when | |
750 | * the device is in the L1 state. | |
751 | */ | |
752 | if (dwc->revision >= DWC3_REVISION_290A) { | |
753 | reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); | |
754 | reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; | |
755 | dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); | |
756 | } | |
757 | ||
72246da4 FB |
758 | return 0; |
759 | ||
c499ff71 | 760 | err4: |
9b9d7cdd | 761 | phy_power_off(dwc->usb3_generic_phy); |
c499ff71 FB |
762 | |
763 | err3: | |
9b9d7cdd | 764 | phy_power_off(dwc->usb2_generic_phy); |
c499ff71 | 765 | |
0ffcaf37 | 766 | err2: |
c499ff71 FB |
767 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
768 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
0ffcaf37 FB |
769 | |
770 | err1: | |
771 | usb_phy_shutdown(dwc->usb2_phy); | |
772 | usb_phy_shutdown(dwc->usb3_phy); | |
57303488 KVA |
773 | phy_exit(dwc->usb2_generic_phy); |
774 | phy_exit(dwc->usb3_generic_phy); | |
0ffcaf37 | 775 | |
72246da4 FB |
776 | err0: |
777 | return ret; | |
778 | } | |
779 | ||
3c9f94ac | 780 | static int dwc3_core_get_phy(struct dwc3 *dwc) |
72246da4 | 781 | { |
3c9f94ac | 782 | struct device *dev = dwc->dev; |
941ea361 | 783 | struct device_node *node = dev->of_node; |
3c9f94ac | 784 | int ret; |
72246da4 | 785 | |
5088b6f5 KVA |
786 | if (node) { |
787 | dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); | |
788 | dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); | |
bb674907 FB |
789 | } else { |
790 | dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); | |
791 | dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); | |
5088b6f5 KVA |
792 | } |
793 | ||
d105e7f8 FB |
794 | if (IS_ERR(dwc->usb2_phy)) { |
795 | ret = PTR_ERR(dwc->usb2_phy); | |
122f06e6 KVA |
796 | if (ret == -ENXIO || ret == -ENODEV) { |
797 | dwc->usb2_phy = NULL; | |
798 | } else if (ret == -EPROBE_DEFER) { | |
d105e7f8 | 799 | return ret; |
122f06e6 KVA |
800 | } else { |
801 | dev_err(dev, "no usb2 phy configured\n"); | |
802 | return ret; | |
803 | } | |
51e1e7bc FB |
804 | } |
805 | ||
d105e7f8 | 806 | if (IS_ERR(dwc->usb3_phy)) { |
315955d7 | 807 | ret = PTR_ERR(dwc->usb3_phy); |
122f06e6 KVA |
808 | if (ret == -ENXIO || ret == -ENODEV) { |
809 | dwc->usb3_phy = NULL; | |
810 | } else if (ret == -EPROBE_DEFER) { | |
d105e7f8 | 811 | return ret; |
122f06e6 KVA |
812 | } else { |
813 | dev_err(dev, "no usb3 phy configured\n"); | |
814 | return ret; | |
815 | } | |
51e1e7bc FB |
816 | } |
817 | ||
57303488 KVA |
818 | dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); |
819 | if (IS_ERR(dwc->usb2_generic_phy)) { | |
820 | ret = PTR_ERR(dwc->usb2_generic_phy); | |
821 | if (ret == -ENOSYS || ret == -ENODEV) { | |
822 | dwc->usb2_generic_phy = NULL; | |
823 | } else if (ret == -EPROBE_DEFER) { | |
824 | return ret; | |
825 | } else { | |
826 | dev_err(dev, "no usb2 phy configured\n"); | |
827 | return ret; | |
828 | } | |
829 | } | |
830 | ||
831 | dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); | |
832 | if (IS_ERR(dwc->usb3_generic_phy)) { | |
833 | ret = PTR_ERR(dwc->usb3_generic_phy); | |
834 | if (ret == -ENOSYS || ret == -ENODEV) { | |
835 | dwc->usb3_generic_phy = NULL; | |
836 | } else if (ret == -EPROBE_DEFER) { | |
837 | return ret; | |
838 | } else { | |
839 | dev_err(dev, "no usb3 phy configured\n"); | |
840 | return ret; | |
841 | } | |
842 | } | |
843 | ||
3c9f94ac FB |
844 | return 0; |
845 | } | |
846 | ||
5f94adfe FB |
847 | static int dwc3_core_init_mode(struct dwc3 *dwc) |
848 | { | |
849 | struct device *dev = dwc->dev; | |
850 | int ret; | |
851 | ||
852 | switch (dwc->dr_mode) { | |
853 | case USB_DR_MODE_PERIPHERAL: | |
5f94adfe FB |
854 | ret = dwc3_gadget_init(dwc); |
855 | if (ret) { | |
9522def4 RQ |
856 | if (ret != -EPROBE_DEFER) |
857 | dev_err(dev, "failed to initialize gadget\n"); | |
5f94adfe FB |
858 | return ret; |
859 | } | |
860 | break; | |
861 | case USB_DR_MODE_HOST: | |
5f94adfe FB |
862 | ret = dwc3_host_init(dwc); |
863 | if (ret) { | |
9522def4 RQ |
864 | if (ret != -EPROBE_DEFER) |
865 | dev_err(dev, "failed to initialize host\n"); | |
5f94adfe FB |
866 | return ret; |
867 | } | |
868 | break; | |
869 | case USB_DR_MODE_OTG: | |
5f94adfe FB |
870 | ret = dwc3_host_init(dwc); |
871 | if (ret) { | |
9522def4 RQ |
872 | if (ret != -EPROBE_DEFER) |
873 | dev_err(dev, "failed to initialize host\n"); | |
5f94adfe FB |
874 | return ret; |
875 | } | |
876 | ||
877 | ret = dwc3_gadget_init(dwc); | |
878 | if (ret) { | |
9522def4 RQ |
879 | if (ret != -EPROBE_DEFER) |
880 | dev_err(dev, "failed to initialize gadget\n"); | |
5f94adfe FB |
881 | return ret; |
882 | } | |
883 | break; | |
884 | default: | |
885 | dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); | |
886 | return -EINVAL; | |
887 | } | |
888 | ||
889 | return 0; | |
890 | } | |
891 | ||
892 | static void dwc3_core_exit_mode(struct dwc3 *dwc) | |
893 | { | |
894 | switch (dwc->dr_mode) { | |
895 | case USB_DR_MODE_PERIPHERAL: | |
896 | dwc3_gadget_exit(dwc); | |
897 | break; | |
898 | case USB_DR_MODE_HOST: | |
899 | dwc3_host_exit(dwc); | |
900 | break; | |
901 | case USB_DR_MODE_OTG: | |
902 | dwc3_host_exit(dwc); | |
903 | dwc3_gadget_exit(dwc); | |
904 | break; | |
905 | default: | |
906 | /* do nothing */ | |
907 | break; | |
908 | } | |
909 | } | |
910 | ||
c5ac6116 | 911 | static void dwc3_get_properties(struct dwc3 *dwc) |
3c9f94ac | 912 | { |
c5ac6116 | 913 | struct device *dev = dwc->dev; |
80caf7d2 | 914 | u8 lpm_nyet_threshold; |
6b6a0c9a | 915 | u8 tx_de_emphasis; |
460d098c | 916 | u8 hird_threshold; |
3c9f94ac | 917 | |
80caf7d2 HR |
918 | /* default to highest possible threshold */ |
919 | lpm_nyet_threshold = 0xff; | |
920 | ||
6b6a0c9a HR |
921 | /* default to -3.5dB de-emphasis */ |
922 | tx_de_emphasis = 1; | |
923 | ||
460d098c HR |
924 | /* |
925 | * default to assert utmi_sleep_n and use maximum allowed HIRD | |
926 | * threshold value of 0b1100 | |
927 | */ | |
928 | hird_threshold = 12; | |
929 | ||
63863b98 | 930 | dwc->maximum_speed = usb_get_maximum_speed(dev); |
06e7114f | 931 | dwc->dr_mode = usb_get_dr_mode(dev); |
32f2ed86 | 932 | dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); |
63863b98 | 933 | |
d64ff406 AB |
934 | dwc->sysdev_is_parent = device_property_read_bool(dev, |
935 | "linux,sysdev_is_parent"); | |
936 | if (dwc->sysdev_is_parent) | |
937 | dwc->sysdev = dwc->dev->parent; | |
938 | else | |
939 | dwc->sysdev = dwc->dev; | |
940 | ||
3d128919 | 941 | dwc->has_lpm_erratum = device_property_read_bool(dev, |
80caf7d2 | 942 | "snps,has-lpm-erratum"); |
3d128919 | 943 | device_property_read_u8(dev, "snps,lpm-nyet-threshold", |
80caf7d2 | 944 | &lpm_nyet_threshold); |
3d128919 | 945 | dwc->is_utmi_l1_suspend = device_property_read_bool(dev, |
460d098c | 946 | "snps,is-utmi-l1-suspend"); |
3d128919 | 947 | device_property_read_u8(dev, "snps,hird-threshold", |
460d098c | 948 | &hird_threshold); |
3d128919 | 949 | dwc->usb3_lpm_capable = device_property_read_bool(dev, |
eac68e8f | 950 | "snps,usb3_lpm_capable"); |
3c9f94ac | 951 | |
3d128919 | 952 | dwc->disable_scramble_quirk = device_property_read_bool(dev, |
3b81221a | 953 | "snps,disable_scramble_quirk"); |
3d128919 | 954 | dwc->u2exit_lfps_quirk = device_property_read_bool(dev, |
9a5b2f31 | 955 | "snps,u2exit_lfps_quirk"); |
3d128919 | 956 | dwc->u2ss_inp3_quirk = device_property_read_bool(dev, |
b5a65c40 | 957 | "snps,u2ss_inp3_quirk"); |
3d128919 | 958 | dwc->req_p1p2p3_quirk = device_property_read_bool(dev, |
df31f5b3 | 959 | "snps,req_p1p2p3_quirk"); |
3d128919 | 960 | dwc->del_p1p2p3_quirk = device_property_read_bool(dev, |
a2a1d0f5 | 961 | "snps,del_p1p2p3_quirk"); |
3d128919 | 962 | dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, |
41c06ffd | 963 | "snps,del_phy_power_chg_quirk"); |
3d128919 | 964 | dwc->lfps_filter_quirk = device_property_read_bool(dev, |
fb67afca | 965 | "snps,lfps_filter_quirk"); |
3d128919 | 966 | dwc->rx_detect_poll_quirk = device_property_read_bool(dev, |
14f4ac53 | 967 | "snps,rx_detect_poll_quirk"); |
3d128919 | 968 | dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, |
59acfa20 | 969 | "snps,dis_u3_susphy_quirk"); |
3d128919 | 970 | dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, |
0effe0a3 | 971 | "snps,dis_u2_susphy_quirk"); |
ec791d14 JY |
972 | dwc->dis_enblslpm_quirk = device_property_read_bool(dev, |
973 | "snps,dis_enblslpm_quirk"); | |
e58dd357 RB |
974 | dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, |
975 | "snps,dis_rxdet_inp3_quirk"); | |
16199f33 WW |
976 | dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, |
977 | "snps,dis-u2-freeclk-exists-quirk"); | |
00fe081d WW |
978 | dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, |
979 | "snps,dis-del-phy-power-chg-quirk"); | |
6b6a0c9a | 980 | |
3d128919 | 981 | dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, |
6b6a0c9a | 982 | "snps,tx_de_emphasis_quirk"); |
3d128919 | 983 | device_property_read_u8(dev, "snps,tx_de_emphasis", |
6b6a0c9a | 984 | &tx_de_emphasis); |
3d128919 HK |
985 | device_property_read_string(dev, "snps,hsphy_interface", |
986 | &dwc->hsphy_interface); | |
987 | device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", | |
bcdb3272 | 988 | &dwc->fladj); |
3d128919 | 989 | |
80caf7d2 | 990 | dwc->lpm_nyet_threshold = lpm_nyet_threshold; |
6b6a0c9a | 991 | dwc->tx_de_emphasis = tx_de_emphasis; |
80caf7d2 | 992 | |
460d098c HR |
993 | dwc->hird_threshold = hird_threshold |
994 | | (dwc->is_utmi_l1_suspend << 4); | |
995 | ||
cf40b86b JY |
996 | dwc->imod_interval = 0; |
997 | } | |
998 | ||
999 | /* check whether the core supports IMOD */ | |
1000 | bool dwc3_has_imod(struct dwc3 *dwc) | |
1001 | { | |
1002 | return ((dwc3_is_usb3(dwc) && | |
1003 | dwc->revision >= DWC3_REVISION_300A) || | |
1004 | (dwc3_is_usb31(dwc) && | |
1005 | dwc->revision >= DWC3_USB31_REVISION_120A)); | |
c5ac6116 FB |
1006 | } |
1007 | ||
7ac51a12 JY |
1008 | static void dwc3_check_params(struct dwc3 *dwc) |
1009 | { | |
1010 | struct device *dev = dwc->dev; | |
1011 | ||
cf40b86b JY |
1012 | /* Check for proper value of imod_interval */ |
1013 | if (dwc->imod_interval && !dwc3_has_imod(dwc)) { | |
1014 | dev_warn(dwc->dev, "Interrupt moderation not supported\n"); | |
1015 | dwc->imod_interval = 0; | |
1016 | } | |
1017 | ||
28632b44 JY |
1018 | /* |
1019 | * Workaround for STAR 9000961433 which affects only version | |
1020 | * 3.00a of the DWC_usb3 core. This prevents the controller | |
1021 | * interrupt from being masked while handling events. IMOD | |
1022 | * allows us to work around this issue. Enable it for the | |
1023 | * affected version. | |
1024 | */ | |
1025 | if (!dwc->imod_interval && | |
1026 | (dwc->revision == DWC3_REVISION_300A)) | |
1027 | dwc->imod_interval = 1; | |
1028 | ||
7ac51a12 JY |
1029 | /* Check the maximum_speed parameter */ |
1030 | switch (dwc->maximum_speed) { | |
1031 | case USB_SPEED_LOW: | |
1032 | case USB_SPEED_FULL: | |
1033 | case USB_SPEED_HIGH: | |
1034 | case USB_SPEED_SUPER: | |
1035 | case USB_SPEED_SUPER_PLUS: | |
1036 | break; | |
1037 | default: | |
1038 | dev_err(dev, "invalid maximum_speed parameter %d\n", | |
1039 | dwc->maximum_speed); | |
1040 | /* fall through */ | |
1041 | case USB_SPEED_UNKNOWN: | |
1042 | /* default to superspeed */ | |
1043 | dwc->maximum_speed = USB_SPEED_SUPER; | |
1044 | ||
1045 | /* | |
1046 | * default to superspeed plus if we are capable. | |
1047 | */ | |
1048 | if (dwc3_is_usb31(dwc) && | |
1049 | (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == | |
1050 | DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) | |
1051 | dwc->maximum_speed = USB_SPEED_SUPER_PLUS; | |
1052 | ||
1053 | break; | |
1054 | } | |
1055 | } | |
1056 | ||
c5ac6116 FB |
1057 | static int dwc3_probe(struct platform_device *pdev) |
1058 | { | |
1059 | struct device *dev = &pdev->dev; | |
1060 | struct resource *res; | |
1061 | struct dwc3 *dwc; | |
1062 | ||
1063 | int ret; | |
1064 | ||
1065 | void __iomem *regs; | |
1066 | ||
1067 | dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); | |
1068 | if (!dwc) | |
1069 | return -ENOMEM; | |
1070 | ||
1071 | dwc->dev = dev; | |
1072 | ||
1073 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1074 | if (!res) { | |
1075 | dev_err(dev, "missing memory resource\n"); | |
1076 | return -ENODEV; | |
1077 | } | |
1078 | ||
1079 | dwc->xhci_resources[0].start = res->start; | |
1080 | dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + | |
1081 | DWC3_XHCI_REGS_END; | |
1082 | dwc->xhci_resources[0].flags = res->flags; | |
1083 | dwc->xhci_resources[0].name = res->name; | |
1084 | ||
1085 | res->start += DWC3_GLOBALS_REGS_START; | |
1086 | ||
1087 | /* | |
1088 | * Request memory region but exclude xHCI regs, | |
1089 | * since it will be requested by the xhci-plat driver. | |
1090 | */ | |
1091 | regs = devm_ioremap_resource(dev, res); | |
1092 | if (IS_ERR(regs)) { | |
1093 | ret = PTR_ERR(regs); | |
1094 | goto err0; | |
1095 | } | |
1096 | ||
1097 | dwc->regs = regs; | |
1098 | dwc->regs_size = resource_size(res); | |
1099 | ||
1100 | dwc3_get_properties(dwc); | |
1101 | ||
6c89cce0 | 1102 | platform_set_drvdata(pdev, dwc); |
2917e718 | 1103 | dwc3_cache_hwparams(dwc); |
6c89cce0 | 1104 | |
3c9f94ac FB |
1105 | ret = dwc3_core_get_phy(dwc); |
1106 | if (ret) | |
3da1f6ee | 1107 | goto err0; |
3c9f94ac | 1108 | |
72246da4 | 1109 | spin_lock_init(&dwc->lock); |
72246da4 | 1110 | |
fc8bb91b FB |
1111 | pm_runtime_set_active(dev); |
1112 | pm_runtime_use_autosuspend(dev); | |
1113 | pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); | |
802ca850 | 1114 | pm_runtime_enable(dev); |
32808237 RQ |
1115 | ret = pm_runtime_get_sync(dev); |
1116 | if (ret < 0) | |
1117 | goto err1; | |
1118 | ||
802ca850 | 1119 | pm_runtime_forbid(dev); |
72246da4 | 1120 | |
3921426b FB |
1121 | ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); |
1122 | if (ret) { | |
1123 | dev_err(dwc->dev, "failed to allocate event buffers\n"); | |
1124 | ret = -ENOMEM; | |
32808237 | 1125 | goto err2; |
3921426b FB |
1126 | } |
1127 | ||
9d6173e1 TN |
1128 | ret = dwc3_get_dr_mode(dwc); |
1129 | if (ret) | |
1130 | goto err3; | |
32a4a135 | 1131 | |
c499ff71 FB |
1132 | ret = dwc3_alloc_scratch_buffers(dwc); |
1133 | if (ret) | |
32808237 | 1134 | goto err3; |
c499ff71 | 1135 | |
72246da4 FB |
1136 | ret = dwc3_core_init(dwc); |
1137 | if (ret) { | |
802ca850 | 1138 | dev_err(dev, "failed to initialize core\n"); |
32808237 | 1139 | goto err4; |
72246da4 FB |
1140 | } |
1141 | ||
7ac51a12 | 1142 | dwc3_check_params(dwc); |
2c7f1bd9 | 1143 | |
5f94adfe FB |
1144 | ret = dwc3_core_init_mode(dwc); |
1145 | if (ret) | |
32808237 | 1146 | goto err5; |
72246da4 | 1147 | |
4e9f3118 | 1148 | dwc3_debugfs_init(dwc); |
fc8bb91b | 1149 | pm_runtime_put(dev); |
72246da4 FB |
1150 | |
1151 | return 0; | |
1152 | ||
32808237 | 1153 | err5: |
c499ff71 | 1154 | dwc3_event_buffers_cleanup(dwc); |
57303488 | 1155 | |
32808237 | 1156 | err4: |
c499ff71 | 1157 | dwc3_free_scratch_buffers(dwc); |
72246da4 | 1158 | |
32808237 | 1159 | err3: |
3921426b | 1160 | dwc3_free_event_buffers(dwc); |
88bc9d19 | 1161 | dwc3_ulpi_exit(dwc); |
3921426b | 1162 | |
32808237 RQ |
1163 | err2: |
1164 | pm_runtime_allow(&pdev->dev); | |
1165 | ||
1166 | err1: | |
1167 | pm_runtime_put_sync(&pdev->dev); | |
1168 | pm_runtime_disable(&pdev->dev); | |
1169 | ||
3da1f6ee FB |
1170 | err0: |
1171 | /* | |
1172 | * restore res->start back to its original value so that, in case the | |
1173 | * probe is deferred, we don't end up getting error in request the | |
1174 | * memory region the next time probe is called. | |
1175 | */ | |
1176 | res->start -= DWC3_GLOBALS_REGS_START; | |
1177 | ||
72246da4 FB |
1178 | return ret; |
1179 | } | |
1180 | ||
fb4e98ab | 1181 | static int dwc3_remove(struct platform_device *pdev) |
72246da4 | 1182 | { |
72246da4 | 1183 | struct dwc3 *dwc = platform_get_drvdata(pdev); |
3da1f6ee FB |
1184 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1185 | ||
fc8bb91b | 1186 | pm_runtime_get_sync(&pdev->dev); |
3da1f6ee FB |
1187 | /* |
1188 | * restore res->start back to its original value so that, in case the | |
1189 | * probe is deferred, we don't end up getting error in request the | |
1190 | * memory region the next time probe is called. | |
1191 | */ | |
1192 | res->start -= DWC3_GLOBALS_REGS_START; | |
72246da4 | 1193 | |
dc99f16f FB |
1194 | dwc3_debugfs_exit(dwc); |
1195 | dwc3_core_exit_mode(dwc); | |
8ba007a9 | 1196 | |
72246da4 | 1197 | dwc3_core_exit(dwc); |
88bc9d19 | 1198 | dwc3_ulpi_exit(dwc); |
72246da4 | 1199 | |
16b972a5 | 1200 | pm_runtime_put_sync(&pdev->dev); |
fc8bb91b | 1201 | pm_runtime_allow(&pdev->dev); |
72246da4 FB |
1202 | pm_runtime_disable(&pdev->dev); |
1203 | ||
fc8bb91b FB |
1204 | dwc3_free_event_buffers(dwc); |
1205 | dwc3_free_scratch_buffers(dwc); | |
1206 | ||
72246da4 FB |
1207 | return 0; |
1208 | } | |
1209 | ||
fc8bb91b FB |
1210 | #ifdef CONFIG_PM |
1211 | static int dwc3_suspend_common(struct dwc3 *dwc) | |
7415f17c | 1212 | { |
fc8bb91b | 1213 | unsigned long flags; |
7415f17c | 1214 | |
a45c82b8 RK |
1215 | switch (dwc->dr_mode) { |
1216 | case USB_DR_MODE_PERIPHERAL: | |
1217 | case USB_DR_MODE_OTG: | |
fc8bb91b | 1218 | spin_lock_irqsave(&dwc->lock, flags); |
7415f17c | 1219 | dwc3_gadget_suspend(dwc); |
fc8bb91b | 1220 | spin_unlock_irqrestore(&dwc->lock, flags); |
51f5d49a | 1221 | break; |
a45c82b8 | 1222 | case USB_DR_MODE_HOST: |
7415f17c | 1223 | default: |
51f5d49a | 1224 | /* do nothing */ |
7415f17c FB |
1225 | break; |
1226 | } | |
1227 | ||
51f5d49a | 1228 | dwc3_core_exit(dwc); |
5c4ad318 | 1229 | |
7415f17c FB |
1230 | return 0; |
1231 | } | |
1232 | ||
fc8bb91b | 1233 | static int dwc3_resume_common(struct dwc3 *dwc) |
7415f17c | 1234 | { |
fc8bb91b | 1235 | unsigned long flags; |
57303488 | 1236 | int ret; |
7415f17c | 1237 | |
51f5d49a FB |
1238 | ret = dwc3_core_init(dwc); |
1239 | if (ret) | |
5c4ad318 FB |
1240 | return ret; |
1241 | ||
a45c82b8 RK |
1242 | switch (dwc->dr_mode) { |
1243 | case USB_DR_MODE_PERIPHERAL: | |
1244 | case USB_DR_MODE_OTG: | |
fc8bb91b | 1245 | spin_lock_irqsave(&dwc->lock, flags); |
7415f17c | 1246 | dwc3_gadget_resume(dwc); |
fc8bb91b | 1247 | spin_unlock_irqrestore(&dwc->lock, flags); |
7415f17c | 1248 | /* FALLTHROUGH */ |
a45c82b8 | 1249 | case USB_DR_MODE_HOST: |
7415f17c FB |
1250 | default: |
1251 | /* do nothing */ | |
1252 | break; | |
1253 | } | |
1254 | ||
fc8bb91b FB |
1255 | return 0; |
1256 | } | |
1257 | ||
1258 | static int dwc3_runtime_checks(struct dwc3 *dwc) | |
1259 | { | |
1260 | switch (dwc->dr_mode) { | |
1261 | case USB_DR_MODE_PERIPHERAL: | |
1262 | case USB_DR_MODE_OTG: | |
1263 | if (dwc->connected) | |
1264 | return -EBUSY; | |
1265 | break; | |
1266 | case USB_DR_MODE_HOST: | |
1267 | default: | |
1268 | /* do nothing */ | |
1269 | break; | |
1270 | } | |
1271 | ||
1272 | return 0; | |
1273 | } | |
1274 | ||
1275 | static int dwc3_runtime_suspend(struct device *dev) | |
1276 | { | |
1277 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1278 | int ret; | |
1279 | ||
1280 | if (dwc3_runtime_checks(dwc)) | |
1281 | return -EBUSY; | |
1282 | ||
1283 | ret = dwc3_suspend_common(dwc); | |
1284 | if (ret) | |
1285 | return ret; | |
1286 | ||
1287 | device_init_wakeup(dev, true); | |
1288 | ||
1289 | return 0; | |
1290 | } | |
1291 | ||
1292 | static int dwc3_runtime_resume(struct device *dev) | |
1293 | { | |
1294 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1295 | int ret; | |
1296 | ||
1297 | device_init_wakeup(dev, false); | |
1298 | ||
1299 | ret = dwc3_resume_common(dwc); | |
1300 | if (ret) | |
1301 | return ret; | |
1302 | ||
1303 | switch (dwc->dr_mode) { | |
1304 | case USB_DR_MODE_PERIPHERAL: | |
1305 | case USB_DR_MODE_OTG: | |
1306 | dwc3_gadget_process_pending_events(dwc); | |
1307 | break; | |
1308 | case USB_DR_MODE_HOST: | |
1309 | default: | |
1310 | /* do nothing */ | |
1311 | break; | |
1312 | } | |
1313 | ||
1314 | pm_runtime_mark_last_busy(dev); | |
b74c2d87 | 1315 | pm_runtime_put(dev); |
fc8bb91b FB |
1316 | |
1317 | return 0; | |
1318 | } | |
1319 | ||
1320 | static int dwc3_runtime_idle(struct device *dev) | |
1321 | { | |
1322 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1323 | ||
1324 | switch (dwc->dr_mode) { | |
1325 | case USB_DR_MODE_PERIPHERAL: | |
1326 | case USB_DR_MODE_OTG: | |
1327 | if (dwc3_runtime_checks(dwc)) | |
1328 | return -EBUSY; | |
1329 | break; | |
1330 | case USB_DR_MODE_HOST: | |
1331 | default: | |
1332 | /* do nothing */ | |
1333 | break; | |
1334 | } | |
1335 | ||
1336 | pm_runtime_mark_last_busy(dev); | |
1337 | pm_runtime_autosuspend(dev); | |
1338 | ||
1339 | return 0; | |
1340 | } | |
1341 | #endif /* CONFIG_PM */ | |
1342 | ||
1343 | #ifdef CONFIG_PM_SLEEP | |
1344 | static int dwc3_suspend(struct device *dev) | |
1345 | { | |
1346 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1347 | int ret; | |
1348 | ||
1349 | ret = dwc3_suspend_common(dwc); | |
1350 | if (ret) | |
1351 | return ret; | |
1352 | ||
1353 | pinctrl_pm_select_sleep_state(dev); | |
1354 | ||
1355 | return 0; | |
1356 | } | |
1357 | ||
1358 | static int dwc3_resume(struct device *dev) | |
1359 | { | |
1360 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1361 | int ret; | |
1362 | ||
1363 | pinctrl_pm_select_default_state(dev); | |
1364 | ||
1365 | ret = dwc3_resume_common(dwc); | |
1366 | if (ret) | |
1367 | return ret; | |
1368 | ||
7415f17c FB |
1369 | pm_runtime_disable(dev); |
1370 | pm_runtime_set_active(dev); | |
1371 | pm_runtime_enable(dev); | |
1372 | ||
1373 | return 0; | |
1374 | } | |
7f370ed0 | 1375 | #endif /* CONFIG_PM_SLEEP */ |
7415f17c FB |
1376 | |
1377 | static const struct dev_pm_ops dwc3_dev_pm_ops = { | |
7415f17c | 1378 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) |
fc8bb91b FB |
1379 | SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, |
1380 | dwc3_runtime_idle) | |
7415f17c FB |
1381 | }; |
1382 | ||
5088b6f5 KVA |
1383 | #ifdef CONFIG_OF |
1384 | static const struct of_device_id of_dwc3_match[] = { | |
22a5aa17 FB |
1385 | { |
1386 | .compatible = "snps,dwc3" | |
1387 | }, | |
5088b6f5 KVA |
1388 | { |
1389 | .compatible = "synopsys,dwc3" | |
1390 | }, | |
1391 | { }, | |
1392 | }; | |
1393 | MODULE_DEVICE_TABLE(of, of_dwc3_match); | |
1394 | #endif | |
1395 | ||
404905a6 HK |
1396 | #ifdef CONFIG_ACPI |
1397 | ||
1398 | #define ACPI_ID_INTEL_BSW "808622B7" | |
1399 | ||
1400 | static const struct acpi_device_id dwc3_acpi_match[] = { | |
1401 | { ACPI_ID_INTEL_BSW, 0 }, | |
1402 | { }, | |
1403 | }; | |
1404 | MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); | |
1405 | #endif | |
1406 | ||
72246da4 FB |
1407 | static struct platform_driver dwc3_driver = { |
1408 | .probe = dwc3_probe, | |
7690417d | 1409 | .remove = dwc3_remove, |
72246da4 FB |
1410 | .driver = { |
1411 | .name = "dwc3", | |
5088b6f5 | 1412 | .of_match_table = of_match_ptr(of_dwc3_match), |
404905a6 | 1413 | .acpi_match_table = ACPI_PTR(dwc3_acpi_match), |
7f370ed0 | 1414 | .pm = &dwc3_dev_pm_ops, |
72246da4 | 1415 | }, |
72246da4 FB |
1416 | }; |
1417 | ||
b1116dcc TK |
1418 | module_platform_driver(dwc3_driver); |
1419 | ||
7ae4fc4d | 1420 | MODULE_ALIAS("platform:dwc3"); |
72246da4 | 1421 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); |
5945f789 | 1422 | MODULE_LICENSE("GPL v2"); |
72246da4 | 1423 | MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); |