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Merge tag 'perf-urgent-2023-11-26' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-block.git] / drivers / usb / dwc3 / core.c
CommitLineData
5fd54ace 1// SPDX-License-Identifier: GPL-2.0
cbdc0f54 2/*
72246da4
FB		 3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
10623b87 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
72246da4
FB		 6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
72246da4
FB		 9 */
10
fe8abf33 11#include <linux/clk.h>
fa0ea13e 12#include <linux/version.h>
a72e658b 13#include <linux/module.h>
72246da4
FB		 14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/io.h>
22#include <linux/list.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
457e84b6 25#include <linux/of.h>
d182c2e1 26#include <linux/of_graph.h>
404905a6 27#include <linux/acpi.h>
6344475f 28#include <linux/pinctrl/consumer.h>
fe8abf33 29#include <linux/reset.h>
7bee3188 30#include <linux/bitfield.h>
72246da4
FB		 31
32#include <linux/usb/ch9.h>
33#include <linux/usb/gadget.h>
f7e846f0 34#include <linux/usb/of.h>
a45c82b8 35#include <linux/usb/otg.h>
72246da4
FB		 36
37#include "core.h"
38#include "gadget.h"
39#include "io.h"
40
41#include "debug.h"
42
fc8bb91b 43#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
8300dd23 44
9d6173e1
TN		 45/**
46 * dwc3_get_dr_mode - Validates and sets dr_mode
47 * @dwc: pointer to our context structure
48 */
49static int dwc3_get_dr_mode(struct dwc3 *dwc)
50{
51 enum usb_dr_mode mode;
52 struct device *dev = dwc->dev;
53 unsigned int hw_mode;
54
55 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
56 dwc->dr_mode = USB_DR_MODE_OTG;
57
58 mode = dwc->dr_mode;
59 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
60
61 switch (hw_mode) {
62 case DWC3_GHWPARAMS0_MODE_GADGET:
63 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
64 dev_err(dev,
65 "Controller does not support host mode.\n");
66 return -EINVAL;
67 }
68 mode = USB_DR_MODE_PERIPHERAL;
69 break;
70 case DWC3_GHWPARAMS0_MODE_HOST:
71 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
72 dev_err(dev,
73 "Controller does not support device mode.\n");
74 return -EINVAL;
75 }
76 mode = USB_DR_MODE_HOST;
77 break;
78 default:
79 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
80 mode = USB_DR_MODE_HOST;
81 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
82 mode = USB_DR_MODE_PERIPHERAL;
a7700468
TN		 83
84 /*
89a9cc47
TN		 85 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
86 * mode. If the controller supports DRD but the dr_mode is not
87 * specified or set to OTG, then set the mode to peripheral.
a7700468 88 */
d182c2e1 89 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
8bb14308
TN		 90 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
91 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
9af21dd6 92 !DWC3_VER_IS_PRIOR(DWC3, 330A))
a7700468 93 mode = USB_DR_MODE_PERIPHERAL;
9d6173e1
TN		 94 }
95
96 if (mode != dwc->dr_mode) {
97 dev_warn(dev,
98 "Configuration mismatch. dr_mode forced to %s\n",
99 mode == USB_DR_MODE_HOST ? "host" : "gadget");
100
101 dwc->dr_mode = mode;
102 }
103
104 return 0;
105}
106
f09cc79b 107void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
3140e8cb
SAS		 108{
109 u32 reg;
110
111 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
112 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
113 reg |= DWC3_GCTL_PRTCAPDIR(mode);
114 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
c4a5153e
MG		 115
116 dwc->current_dr_role = mode;
41ce1456
RQ		 117}
118
119static void __dwc3_set_mode(struct work_struct *work)
120{
121 struct dwc3 *dwc = work_to_dwc(work);
122 unsigned long flags;
123 int ret;
f580170f 124 u32 reg;
62c73bfe 125 u32 desired_dr_role;
41ce1456 126
f88359e1 127 mutex_lock(&dwc->mutex);
62c73bfe
SP		 128 spin_lock_irqsave(&dwc->lock, flags);
129 desired_dr_role = dwc->desired_dr_role;
130 spin_unlock_irqrestore(&dwc->lock, flags);
f88359e1 131
c2cd3452
MK		 132 pm_runtime_get_sync(dwc->dev);
133
f09cc79b
RQ		 134 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
135 dwc3_otg_update(dwc, 0);
136
62c73bfe 137 if (!desired_dr_role)
c2cd3452 138 goto out;
41ce1456 139
62c73bfe 140 if (desired_dr_role == dwc->current_dr_role)
c2cd3452 141 goto out;
41ce1456 142
62c73bfe 143 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
c2cd3452 144 goto out;
41ce1456
RQ		 145
146 switch (dwc->current_dr_role) {
147 case DWC3_GCTL_PRTCAP_HOST:
148 dwc3_host_exit(dwc);
149 break;
150 case DWC3_GCTL_PRTCAP_DEVICE:
151 dwc3_gadget_exit(dwc);
152 dwc3_event_buffers_cleanup(dwc);
153 break;
f09cc79b
RQ		 154 case DWC3_GCTL_PRTCAP_OTG:
155 dwc3_otg_exit(dwc);
156 spin_lock_irqsave(&dwc->lock, flags);
157 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
158 spin_unlock_irqrestore(&dwc->lock, flags);
159 dwc3_otg_update(dwc, 1);
160 break;
41ce1456
RQ		 161 default:
162 break;
163 }
164
07903626
RK		 165 /*
166 * When current_dr_role is not set, there's no role switching.
167 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
168 */
169 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
170 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
62c73bfe 171 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
f88359e1
YC		 172 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
173 reg |= DWC3_GCTL_CORESOFTRESET;
174 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
175
176 /*
177 * Wait for internal clocks to synchronized. DWC_usb31 and
178 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
179 * keep it consistent across different IPs, let's wait up to
180 * 100ms before clearing GCTL.CORESOFTRESET.
181 */
182 msleep(100);
183
184 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
185 reg &= ~DWC3_GCTL_CORESOFTRESET;
186 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
187 }
188
41ce1456
RQ		 189 spin_lock_irqsave(&dwc->lock, flags);
190
62c73bfe 191 dwc3_set_prtcap(dwc, desired_dr_role);
6b3261a2 192
41ce1456
RQ		 193 spin_unlock_irqrestore(&dwc->lock, flags);
194
62c73bfe 195 switch (desired_dr_role) {
41ce1456
RQ		 196 case DWC3_GCTL_PRTCAP_HOST:
197 ret = dwc3_host_init(dwc);
958d1a4c 198 if (ret) {
41ce1456 199 dev_err(dwc->dev, "failed to initialize host\n");
958d1a4c
FB		 200 } else {
201 if (dwc->usb2_phy)
202 otg_set_vbus(dwc->usb2_phy->otg, true);
644cbbc3
MG		 203 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
204 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
f580170f
YC		 205 if (dwc->dis_split_quirk) {
206 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
207 reg |= DWC3_GUCTL3_SPLITDISABLE;
208 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
209 }
958d1a4c 210 }
41ce1456
RQ		 211 break;
212 case DWC3_GCTL_PRTCAP_DEVICE:
f88359e1
YC		 213 dwc3_core_soft_reset(dwc);
214
41ce1456 215 dwc3_event_buffers_setup(dwc);
958d1a4c
FB		 216
217 if (dwc->usb2_phy)
218 otg_set_vbus(dwc->usb2_phy->otg, false);
644cbbc3
MG		 219 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
220 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
958d1a4c 221
41ce1456
RQ		 222 ret = dwc3_gadget_init(dwc);
223 if (ret)
224 dev_err(dwc->dev, "failed to initialize peripheral\n");
225 break;
f09cc79b
RQ		 226 case DWC3_GCTL_PRTCAP_OTG:
227 dwc3_otg_init(dwc);
228 dwc3_otg_update(dwc, 0);
229 break;
41ce1456
RQ		 230 default:
231 break;
232 }
f09cc79b 233
c2cd3452
MK		 234out:
235 pm_runtime_mark_last_busy(dwc->dev);
236 pm_runtime_put_autosuspend(dwc->dev);
f88359e1 237 mutex_unlock(&dwc->mutex);
41ce1456
RQ		 238}
239
240void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
241{
242 unsigned long flags;
243
dc336b19
LJ		 244 if (dwc->dr_mode != USB_DR_MODE_OTG)
245 return;
246
41ce1456
RQ		 247 spin_lock_irqsave(&dwc->lock, flags);
248 dwc->desired_dr_role = mode;
249 spin_unlock_irqrestore(&dwc->lock, flags);
250
084a804e 251 queue_work(system_freezable_wq, &dwc->drd_work);
3140e8cb 252}
8300dd23 253
cf6d867d
FB		 254u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
255{
256 struct dwc3 *dwc = dep->dwc;
257 u32 reg;
258
259 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
260 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
261 DWC3_GDBGFIFOSPACE_TYPE(type));
262
263 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
264
265 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
266}
267
72246da4
FB		 268/**
269 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
270 * @dwc: pointer to our context structure
271 */
0066472d 272int dwc3_core_soft_reset(struct dwc3 *dwc)
72246da4
FB		 273{
274 u32 reg;
f59dcab1 275 int retries = 1000;
72246da4 276
f59dcab1
FB		 277 /*
278 * We're resetting only the device side because, if we're in host mode,
279 * XHCI driver will reset the host block. If dwc3 was configured for
e835c0a4 280 * host-only mode or current role is host, then we can return early.
f59dcab1 281 */
8bea147d 282 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
f59dcab1 283 return 0;
72246da4 284
8bea147d
TN		 285 /*
286 * If the dr_mode is host and the dwc->current_dr_role is not the
287 * corresponding DWC3_GCTL_PRTCAP_HOST, then the dwc3_core_init_mode
288 * isn't executed yet. Ensure the phy is ready before the controller
289 * updates the GCTL.PRTCAPDIR or other settings by soft-resetting
290 * the phy.
291 *
292 * Note: GUSB3PIPECTL[n] and GUSB2PHYCFG[n] are port settings where n
293 * is port index. If this is a multiport host, then we need to reset
294 * all active ports.
295 */
296 if (dwc->dr_mode == USB_DR_MODE_HOST) {
297 u32 usb3_port;
298 u32 usb2_port;
299
300 usb3_port = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
301 usb3_port |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
302 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port);
303
304 usb2_port = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
305 usb2_port |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
306 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port);
307
308 /* Small delay for phy reset assertion */
309 usleep_range(1000, 2000);
310
311 usb3_port &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
312 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port);
313
314 usb2_port &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
315 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port);
316
317 /* Wait for clock synchronization */
318 msleep(50);
319 return 0;
320 }
321
f59dcab1
FB		 322 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
323 reg |= DWC3_DCTL_CSFTRST;
f4fd84ae
TN		 324 reg &= ~DWC3_DCTL_RUN_STOP;
325 dwc3_gadget_dctl_write_safe(dwc, reg);
72246da4 326
4749e0e6
TN		 327 /*
328 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
329 * is cleared only after all the clocks are synchronized. This can
330 * take a little more than 50ms. Set the polling rate at 20ms
331 * for 10 times instead.
332 */
9af21dd6 333 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
4749e0e6
TN		 334 retries = 10;
335
f59dcab1
FB		 336 do {
337 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
338 if (!(reg & DWC3_DCTL_CSFTRST))
fab38333 339 goto done;
45627ac6 340
9af21dd6 341 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
4749e0e6
TN		 342 msleep(20);
343 else
344 udelay(1);
f59dcab1 345 } while (--retries);
57303488 346
859bdc35 347 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
f59dcab1 348 return -ETIMEDOUT;
fab38333
TN		 349
350done:
351 /*
4749e0e6
TN		 352 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
353 * is cleared, we must wait at least 50ms before accessing the PHY
354 * domain (synchronization delay).
fab38333 355 */
9af21dd6 356 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
fab38333
TN		 357 msleep(50);
358
359 return 0;
72246da4
FB		 360}
361
db2be4e9
NB		 362/*
363 * dwc3_frame_length_adjustment - Adjusts frame length if required
364 * @dwc3: Pointer to our controller context structure
db2be4e9 365 */
bcdb3272 366static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
db2be4e9
NB		 367{
368 u32 reg;
369 u32 dft;
370
9af21dd6 371 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
db2be4e9
NB		 372 return;
373
bcdb3272 374 if (dwc->fladj == 0)
db2be4e9
NB		 375 return;
376
377 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
378 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
a7d9874c 379 if (dft != dwc->fladj) {
db2be4e9 380 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
bcdb3272 381 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
db2be4e9
NB		 382 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
383 }
384}
385
7bee3188
BP		 386/**
387 * dwc3_ref_clk_period - Reference clock period configuration
388 * Default reference clock period depends on hardware
389 * configuration. For systems with reference clock that differs
390 * from the default, this will set clock period in DWC3_GUCTL
391 * register.
392 * @dwc: Pointer to our controller context structure
7bee3188
BP		 393 */
394static void dwc3_ref_clk_period(struct dwc3 *dwc)
395{
5114c3ee 396 unsigned long period;
596c8785
SA		 397 unsigned long fladj;
398 unsigned long decr;
5114c3ee 399 unsigned long rate;
7bee3188
BP		 400 u32 reg;
401
5114c3ee
SA		 402 if (dwc->ref_clk) {
403 rate = clk_get_rate(dwc->ref_clk);
404 if (!rate)
405 return;
406 period = NSEC_PER_SEC / rate;
407 } else if (dwc->ref_clk_per) {
408 period = dwc->ref_clk_per;
596c8785 409 rate = NSEC_PER_SEC / period;
5114c3ee 410 } else {
7bee3188 411 return;
5114c3ee 412 }
7bee3188
BP		 413
414 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
415 reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
5114c3ee 416 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
7bee3188 417 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
7bee3188 418
596c8785
SA		 419 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
420 return;
421
422 /*
423 * The calculation below is
424 *
425 * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
426 *
427 * but rearranged for fixed-point arithmetic. The division must be
428 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
429 * neither does rate * period).
430 *
431 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
432 * nanoseconds of error caused by the truncation which happened during
433 * the division when calculating rate or period (whichever one was
434 * derived from the other). We first calculate the relative error, then
435 * scale it to units of 8 ppm.
436 */
437 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
438 fladj -= 125000;
439
440 /*
441 * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
442 */
443 decr = 480000000 / rate;
444
445 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
446 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
447 & ~DWC3_GFLADJ_240MHZDECR
448 & ~DWC3_GFLADJ_240MHZDECR_PLS1;
449 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
450 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
451 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
a6fc2f1b
AS		 452
453 if (dwc->gfladj_refclk_lpm_sel)
454 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL;
455
596c8785
SA		 456 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
457}
7bee3188 458
72246da4
FB		 459/**
460 * dwc3_free_one_event_buffer - Frees one event buffer
461 * @dwc: Pointer to our controller context structure
462 * @evt: Pointer to event buffer to be freed
463 */
464static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
465 struct dwc3_event_buffer *evt)
466{
d64ff406 467 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
72246da4
FB		 468}
469
470/**
1d046793 471 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
72246da4
FB		 472 * @dwc: Pointer to our controller context structure
473 * @length: size of the event buffer
474 *
1d046793 475 * Returns a pointer to the allocated event buffer structure on success
72246da4
FB		 476 * otherwise ERR_PTR(errno).
477 */
67d0b500 478static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
ca80ca61 479 unsigned int length)
72246da4
FB		 480{
481 struct dwc3_event_buffer *evt;
482
380f0d28 483 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
72246da4
FB		 484 if (!evt)
485 return ERR_PTR(-ENOMEM);
486
487 evt->dwc = dwc;
488 evt->length = length;
d9fa4c63
JY		 489 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
490 if (!evt->cache)
491 return ERR_PTR(-ENOMEM);
492
d64ff406 493 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
72246da4 494 &evt->dma, GFP_KERNEL);
e32672f0 495 if (!evt->buf)
72246da4 496 return ERR_PTR(-ENOMEM);
72246da4
FB		 497
498 return evt;
499}
500
501/**
502 * dwc3_free_event_buffers - frees all allocated event buffers
503 * @dwc: Pointer to our controller context structure
504 */
505static void dwc3_free_event_buffers(struct dwc3 *dwc)
506{
507 struct dwc3_event_buffer *evt;
72246da4 508
696c8b12 509 evt = dwc->ev_buf;
660e9bde
FB		 510 if (evt)
511 dwc3_free_one_event_buffer(dwc, evt);
72246da4
FB		 512}
513
514/**
515 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
1d046793 516 * @dwc: pointer to our controller context structure
72246da4
FB		 517 * @length: size of event buffer
518 *
1d046793 519 * Returns 0 on success otherwise negative errno. In the error case, dwc
72246da4
FB		 520 * may contain some buffers allocated but not all which were requested.
521 */
ca80ca61 522static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
72246da4 523{
660e9bde 524 struct dwc3_event_buffer *evt;
72246da4 525
660e9bde
FB		 526 evt = dwc3_alloc_one_event_buffer(dwc, length);
527 if (IS_ERR(evt)) {
528 dev_err(dwc->dev, "can't allocate event buffer\n");
529 return PTR_ERR(evt);
72246da4 530 }
696c8b12 531 dwc->ev_buf = evt;
72246da4
FB		 532
533 return 0;
534}
535
536/**
537 * dwc3_event_buffers_setup - setup our allocated event buffers
1d046793 538 * @dwc: pointer to our controller context structure
72246da4
FB		 539 *
540 * Returns 0 on success otherwise negative errno.
541 */
f09cc79b 542int dwc3_event_buffers_setup(struct dwc3 *dwc)
72246da4
FB		 543{
544 struct dwc3_event_buffer *evt;
72246da4 545
696c8b12 546 evt = dwc->ev_buf;
660e9bde 547 evt->lpos = 0;
660e9bde
FB		 548 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
549 lower_32_bits(evt->dma));
550 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
551 upper_32_bits(evt->dma));
552 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
553 DWC3_GEVNTSIZ_SIZE(evt->length));
554 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 555
556 return 0;
557}
558
f09cc79b 559void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
72246da4
FB		 560{
561 struct dwc3_event_buffer *evt;
72246da4 562
696c8b12 563 evt = dwc->ev_buf;
7acd85e0 564
660e9bde 565 evt->lpos = 0;
7acd85e0 566
660e9bde
FB		 567 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
568 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
569 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
570 | DWC3_GEVNTSIZ_SIZE(0));
571 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 572}
573
789451f6
FB		 574static void dwc3_core_num_eps(struct dwc3 *dwc)
575{
576 struct dwc3_hwparams *parms = &dwc->hwparams;
577
47d3946e 578 dwc->num_eps = DWC3_NUM_EPS(parms);
789451f6
FB		 579}
580
41ac7b3a 581static void dwc3_cache_hwparams(struct dwc3 *dwc)
26ceca97
FB		 582{
583 struct dwc3_hwparams *parms = &dwc->hwparams;
584
585 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
586 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
587 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
588 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
589 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
590 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
591 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
592 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
593 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
16710380
TN		 594
595 if (DWC3_IP_IS(DWC32))
596 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
26ceca97
FB		 597}
598
98112041
RQ		 599static int dwc3_core_ulpi_init(struct dwc3 *dwc)
600{
601 int intf;
602 int ret = 0;
603
604 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
605
606 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
607 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
608 dwc->hsphy_interface &&
609 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
610 ret = dwc3_ulpi_init(dwc);
611
612 return ret;
613}
614
b5a65c40
HR		 615/**
616 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
617 * @dwc: Pointer to our controller context structure
88bc9d19
HK		 618 *
619 * Returns 0 on success. The USB PHY interfaces are configured but not
620 * initialized. The PHY interfaces and the PHYs get initialized together with
621 * the core in dwc3_core_init.
b5a65c40 622 */
88bc9d19 623static int dwc3_phy_setup(struct dwc3 *dwc)
b5a65c40 624{
9ba3aca8 625 unsigned int hw_mode;
b5a65c40
HR		 626 u32 reg;
627
9ba3aca8
TN		 628 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
629
b5a65c40
HR		 630 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
631
1966b865
FB		 632 /*
633 * Make sure UX_EXIT_PX is cleared as that causes issues with some
634 * PHYs. Also, this bit is not supposed to be used in normal operation.
635 */
636 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
637
2164a476
HR		 638 /*
639 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
640 * to '0' during coreConsultant configuration. So default value
641 * will be '0' when the core is reset. Application needs to set it
642 * to '1' after the core initialization is completed.
643 */
9af21dd6 644 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
2164a476
HR		 645 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
646
9ba3aca8
TN		 647 /*
648 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
649 * power-on reset, and it can be set after core initialization, which is
650 * after device soft-reset during initialization.
651 */
652 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
653 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
654
b5a65c40
HR		 655 if (dwc->u2ss_inp3_quirk)
656 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
657
e58dd357
RB		 658 if (dwc->dis_rxdet_inp3_quirk)
659 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
660
df31f5b3
HR		 661 if (dwc->req_p1p2p3_quirk)
662 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
663
a2a1d0f5
HR		 664 if (dwc->del_p1p2p3_quirk)
665 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
666
41c06ffd
HR		 667 if (dwc->del_phy_power_chg_quirk)
668 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
669
fb67afca
HR		 670 if (dwc->lfps_filter_quirk)
671 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
672
14f4ac53
HR		 673 if (dwc->rx_detect_poll_quirk)
674 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
675
6b6a0c9a
HR		 676 if (dwc->tx_de_emphasis_quirk)
677 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
678
cd72f890 679 if (dwc->dis_u3_susphy_quirk)
59acfa20
HR		 680 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
681
00fe081d
WW		 682 if (dwc->dis_del_phy_power_chg_quirk)
683 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
684
b5a65c40
HR		 685 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
686
2164a476
HR		 687 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
688
3e10a2ce
HK		 689 /* Select the HS PHY interface */
690 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
691 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
43cacb03
FB		 692 if (dwc->hsphy_interface &&
693 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
3e10a2ce 694 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 695 break;
43cacb03
FB		 696 } else if (dwc->hsphy_interface &&
697 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
3e10a2ce 698 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 699 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
3e10a2ce 700 } else {
88bc9d19
HK		 701 /* Relying on default value. */
702 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
703 break;
3e10a2ce 704 }
df561f66 705 fallthrough;
88bc9d19 706 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
3e10a2ce
HK		 707 default:
708 break;
709 }
710
32f2ed86
WW		 711 switch (dwc->hsphy_mode) {
712 case USBPHY_INTERFACE_MODE_UTMI:
713 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
714 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
715 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
716 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
717 break;
718 case USBPHY_INTERFACE_MODE_UTMIW:
719 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
720 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
721 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
722 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
723 break;
724 default:
725 break;
726 }
727
2164a476
HR		 728 /*
729 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
730 * '0' during coreConsultant configuration. So default value will
731 * be '0' when the core is reset. Application needs to set it to
732 * '1' after the core initialization is completed.
733 */
9af21dd6 734 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
2164a476
HR		 735 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
736
9ba3aca8
TN		 737 /*
738 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
739 * power-on reset, and it can be set after core initialization, which is
740 * after device soft-reset during initialization.
741 */
742 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
743 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
744
cd72f890 745 if (dwc->dis_u2_susphy_quirk)
0effe0a3
HR		 746 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
747
ec791d14
JY		 748 if (dwc->dis_enblslpm_quirk)
749 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
eafeacf1
TN		 750 else
751 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
ec791d14 752
a6fc2f1b 753 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
16199f33
WW		 754 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
755
b84ba26c
PM		 756 /*
757 * Some ULPI USB PHY does not support internal VBUS supply, to drive
758 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL
759 * bit of OTG_CTRL register. Controller configures the USB2 PHY
760 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus
761 * with an external supply.
762 */
763 if (dwc->ulpi_ext_vbus_drv)
764 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
765
2164a476 766 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
88bc9d19
HK		 767
768 return 0;
b5a65c40
HR		 769}
770
1d72fab4
JH		 771static int dwc3_phy_init(struct dwc3 *dwc)
772{
773 int ret;
774
775 usb_phy_init(dwc->usb2_phy);
776 usb_phy_init(dwc->usb3_phy);
777
778 ret = phy_init(dwc->usb2_generic_phy);
779 if (ret < 0)
780 goto err_shutdown_usb3_phy;
781
782 ret = phy_init(dwc->usb3_generic_phy);
783 if (ret < 0)
784 goto err_exit_usb2_phy;
785
786 return 0;
787
788err_exit_usb2_phy:
789 phy_exit(dwc->usb2_generic_phy);
790err_shutdown_usb3_phy:
791 usb_phy_shutdown(dwc->usb3_phy);
792 usb_phy_shutdown(dwc->usb2_phy);
793
794 return ret;
795}
796
797static void dwc3_phy_exit(struct dwc3 *dwc)
798{
799 phy_exit(dwc->usb3_generic_phy);
800 phy_exit(dwc->usb2_generic_phy);
801
802 usb_phy_shutdown(dwc->usb3_phy);
803 usb_phy_shutdown(dwc->usb2_phy);
804}
805
806static int dwc3_phy_power_on(struct dwc3 *dwc)
807{
808 int ret;
809
810 usb_phy_set_suspend(dwc->usb2_phy, 0);
811 usb_phy_set_suspend(dwc->usb3_phy, 0);
812
813 ret = phy_power_on(dwc->usb2_generic_phy);
814 if (ret < 0)
815 goto err_suspend_usb3_phy;
816
817 ret = phy_power_on(dwc->usb3_generic_phy);
818 if (ret < 0)
819 goto err_power_off_usb2_phy;
820
821 return 0;
822
823err_power_off_usb2_phy:
824 phy_power_off(dwc->usb2_generic_phy);
825err_suspend_usb3_phy:
826 usb_phy_set_suspend(dwc->usb3_phy, 1);
827 usb_phy_set_suspend(dwc->usb2_phy, 1);
828
829 return ret;
830}
831
832static void dwc3_phy_power_off(struct dwc3 *dwc)
833{
834 phy_power_off(dwc->usb3_generic_phy);
835 phy_power_off(dwc->usb2_generic_phy);
836
837 usb_phy_set_suspend(dwc->usb3_phy, 1);
838 usb_phy_set_suspend(dwc->usb2_phy, 1);
839}
840
33fb697e
SA		 841static int dwc3_clk_enable(struct dwc3 *dwc)
842{
843 int ret;
844
845 ret = clk_prepare_enable(dwc->bus_clk);
846 if (ret)
847 return ret;
848
849 ret = clk_prepare_enable(dwc->ref_clk);
850 if (ret)
851 goto disable_bus_clk;
852
853 ret = clk_prepare_enable(dwc->susp_clk);
854 if (ret)
855 goto disable_ref_clk;
856
97789b93
SR		 857 ret = clk_prepare_enable(dwc->utmi_clk);
858 if (ret)
859 goto disable_susp_clk;
860
861 ret = clk_prepare_enable(dwc->pipe_clk);
862 if (ret)
863 goto disable_utmi_clk;
864
33fb697e
SA		 865 return 0;
866
97789b93
SR		 867disable_utmi_clk:
868 clk_disable_unprepare(dwc->utmi_clk);
869disable_susp_clk:
870 clk_disable_unprepare(dwc->susp_clk);
33fb697e
SA		 871disable_ref_clk:
872 clk_disable_unprepare(dwc->ref_clk);
873disable_bus_clk:
874 clk_disable_unprepare(dwc->bus_clk);
875 return ret;
876}
877
878static void dwc3_clk_disable(struct dwc3 *dwc)
879{
97789b93
SR		 880 clk_disable_unprepare(dwc->pipe_clk);
881 clk_disable_unprepare(dwc->utmi_clk);
33fb697e
SA		 882 clk_disable_unprepare(dwc->susp_clk);
883 clk_disable_unprepare(dwc->ref_clk);
884 clk_disable_unprepare(dwc->bus_clk);
885}
886
c499ff71
FB		 887static void dwc3_core_exit(struct dwc3 *dwc)
888{
889 dwc3_event_buffers_cleanup(dwc);
1d72fab4
JH		 890 dwc3_phy_power_off(dwc);
891 dwc3_phy_exit(dwc);
33fb697e 892 dwc3_clk_disable(dwc);
fe8abf33 893 reset_control_assert(dwc->reset);
c499ff71
FB		 894}
895
0759956f 896static bool dwc3_core_is_valid(struct dwc3 *dwc)
72246da4 897{
0759956f 898 u32 reg;
72246da4 899
7650bd74 900 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
9af21dd6 901 dwc->ip = DWC3_GSNPS_ID(reg);
0759956f 902
7650bd74 903 /* This should read as U3 followed by revision number */
9af21dd6 904 if (DWC3_IP_IS(DWC3)) {
690fb371 905 dwc->revision = reg;
9af21dd6 906 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
690fb371 907 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
475d8e01 908 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
690fb371 909 } else {
0759956f 910 return false;
7650bd74 911 }
7650bd74 912
0759956f
FB		 913 return true;
914}
58a0f23f 915
941f918e 916static void dwc3_core_setup_global_control(struct dwc3 *dwc)
0759956f 917{
941f918e 918 u32 reg;
c499ff71 919
4878a028 920 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
3e87c42a 921 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
4878a028 922
164d7731 923 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
4878a028 924 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
32a4a135
FB		 925 /**
926 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
927 * issue which would cause xHCI compliance tests to fail.
928 *
929 * Because of that we cannot enable clock gating on such
930 * configurations.
931 *
932 * Refers to:
933 *
934 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
935 * SOF/ITP Mode Used
936 */
937 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
938 dwc->dr_mode == USB_DR_MODE_OTG) &&
9af21dd6 939 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
32a4a135
FB		 940 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
941 else
942 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
4878a028 943 break;
0ffcaf37 944 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
2eac3992
HR		 945 /*
946 * REVISIT Enabling this bit so that host-mode hibernation
947 * will work. Device-mode hibernation is not yet implemented.
948 */
949 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
0ffcaf37 950 break;
4878a028 951 default:
5eb30ced
FB		 952 /* nothing */
953 break;
4878a028
SAS		 954 }
955
946bd579
HR		 956 /* check if current dwc3 is on simulation board */
957 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
6af19fd1 958 dev_info(dwc->dev, "Running with FPGA optimizations\n");
946bd579
HR		 959 dwc->is_fpga = true;
960 }
961
3b81221a
HR		 962 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
963 "disable_scramble cannot be used on non-FPGA builds\n");
964
965 if (dwc->disable_scramble_quirk && dwc->is_fpga)
966 reg |= DWC3_GCTL_DISSCRAMBLE;
967 else
968 reg &= ~DWC3_GCTL_DISSCRAMBLE;
969
9a5b2f31
HR		 970 if (dwc->u2exit_lfps_quirk)
971 reg |= DWC3_GCTL_U2EXIT_LFPS;
972
4878a028
SAS		 973 /*
974 * WORKAROUND: DWC3 revisions <1.90a have a bug
1d046793 975 * where the device can fail to connect at SuperSpeed
4878a028 976 * and falls back to high-speed mode which causes
1d046793 977 * the device to enter a Connect/Disconnect loop
4878a028 978 */
9af21dd6 979 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
4878a028
SAS		 980 reg |= DWC3_GCTL_U2RSTECN;
981
982 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
941f918e
FB		 983}
984
f54edb53 985static int dwc3_core_get_phy(struct dwc3 *dwc);
98112041 986static int dwc3_core_ulpi_init(struct dwc3 *dwc);
f54edb53 987
d9612c2f
PM		 988/* set global incr burst type configuration registers */
989static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
990{
991 struct device *dev = dwc->dev;
992 /* incrx_mode : for INCR burst type. */
993 bool incrx_mode;
994 /* incrx_size : for size of INCRX burst. */
995 u32 incrx_size;
996 u32 *vals;
997 u32 cfg;
998 int ntype;
999 int ret;
1000 int i;
1001
1002 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
1003
1004 /*
1005 * Handle property "snps,incr-burst-type-adjustment".
1006 * Get the number of value from this property:
1007 * result <= 0, means this property is not supported.
1008 * result = 1, means INCRx burst mode supported.
1009 * result > 1, means undefined length burst mode supported.
1010 */
a6e5e679 1011 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
d9612c2f
PM		 1012 if (ntype <= 0)
1013 return;
1014
1015 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
4ea15088 1016 if (!vals)
d9612c2f 1017 return;
d9612c2f
PM		 1018
1019 /* Get INCR burst type, and parse it */
1020 ret = device_property_read_u32_array(dev,
1021 "snps,incr-burst-type-adjustment", vals, ntype);
1022 if (ret) {
75ecb9dd 1023 kfree(vals);
d9612c2f
PM		 1024 dev_err(dev, "Error to get property\n");
1025 return;
1026 }
1027
1028 incrx_size = *vals;
1029
1030 if (ntype > 1) {
1031 /* INCRX (undefined length) burst mode */
1032 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
1033 for (i = 1; i < ntype; i++) {
1034 if (vals[i] > incrx_size)
1035 incrx_size = vals[i];
1036 }
1037 } else {
1038 /* INCRX burst mode */
1039 incrx_mode = INCRX_BURST_MODE;
1040 }
1041
75ecb9dd
AS		 1042 kfree(vals);
1043
d9612c2f
PM		 1044 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
1045 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
1046 if (incrx_mode)
1047 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
1048 switch (incrx_size) {
1049 case 256:
1050 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1051 break;
1052 case 128:
1053 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1054 break;
1055 case 64:
1056 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1057 break;
1058 case 32:
1059 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1060 break;
1061 case 16:
1062 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1063 break;
1064 case 8:
1065 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1066 break;
1067 case 4:
1068 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1069 break;
1070 case 1:
1071 break;
1072 default:
1073 dev_err(dev, "Invalid property\n");
1074 break;
1075 }
1076
1077 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1078}
1079
3497b9a5
LJ		 1080static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
1081{
1082 u32 scale;
1083 u32 reg;
1084
1085 if (!dwc->susp_clk)
1086 return;
1087
1088 /*
1089 * The power down scale field specifies how many suspend_clk
1090 * periods fit into a 16KHz clock period. When performing
1091 * the division, round up the remainder.
1092 *
1093 * The power down scale value is calculated using the fastest
1094 * frequency of the suspend_clk. If it isn't fixed (but within
1095 * the accuracy requirement), the driver may not know the max
1096 * rate of the suspend_clk, so only update the power down scale
1097 * if the default is less than the calculated value from
1098 * clk_get_rate() or if the default is questionably high
1099 * (3x or more) to be within the requirement.
1100 */
1101 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
1102 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1103 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
1104 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
1105 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
1106 reg |= DWC3_GCTL_PWRDNSCALE(scale);
1107 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1108 }
1109}
1110
e72fc8d6
SC		 1111static void dwc3_config_threshold(struct dwc3 *dwc)
1112{
1113 u32 reg;
1114 u8 rx_thr_num;
1115 u8 rx_maxburst;
1116 u8 tx_thr_num;
1117 u8 tx_maxburst;
1118
1119 /*
1120 * Must config both number of packets and max burst settings to enable
1121 * RX and/or TX threshold.
1122 */
1123 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1124 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1125 rx_maxburst = dwc->rx_max_burst_prd;
1126 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1127 tx_maxburst = dwc->tx_max_burst_prd;
1128
1129 if (rx_thr_num && rx_maxburst) {
1130 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1131 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1132
1133 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1134 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1135
1136 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1137 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1138
1139 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1140 }
1141
1142 if (tx_thr_num && tx_maxburst) {
1143 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1144 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1145
1146 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1147 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1148
1149 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1150 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1151
1152 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1153 }
1154 }
1155
1156 rx_thr_num = dwc->rx_thr_num_pkt;
1157 rx_maxburst = dwc->rx_max_burst;
1158 tx_thr_num = dwc->tx_thr_num_pkt;
1159 tx_maxburst = dwc->tx_max_burst;
1160
1161 if (DWC3_IP_IS(DWC3)) {
1162 if (rx_thr_num && rx_maxburst) {
1163 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1164 reg |= DWC3_GRXTHRCFG_PKTCNTSEL;
1165
1166 reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0);
1167 reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1168
1169 reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1170 reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1171
1172 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1173 }
1174
1175 if (tx_thr_num && tx_maxburst) {
1176 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1177 reg |= DWC3_GTXTHRCFG_PKTCNTSEL;
1178
1179 reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0);
1180 reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1181
1182 reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1183 reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1184
1185 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1186 }
1187 } else {
1188 if (rx_thr_num && rx_maxburst) {
1189 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1190 reg |= DWC31_GRXTHRCFG_PKTCNTSEL;
1191
1192 reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0);
1193 reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1194
1195 reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1196 reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1197
1198 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1199 }
1200
1201 if (tx_thr_num && tx_maxburst) {
1202 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1203 reg |= DWC31_GTXTHRCFG_PKTCNTSEL;
1204
1205 reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0);
1206 reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1207
1208 reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1209 reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1210
1211 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1212 }
1213 }
1214}
1215
941f918e
FB		 1216/**
1217 * dwc3_core_init - Low-level initialization of DWC3 Core
1218 * @dwc: Pointer to our controller context structure
1219 *
1220 * Returns 0 on success otherwise negative errno.
1221 */
1222static int dwc3_core_init(struct dwc3 *dwc)
1223{
9ba3aca8 1224 unsigned int hw_mode;
941f918e
FB		 1225 u32 reg;
1226 int ret;
1227
9ba3aca8
TN		 1228 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1229
941f918e
FB		 1230 /*
1231 * Write Linux Version Code to our GUID register so it's easy to figure
1232 * out which kernel version a bug was found.
1233 */
1234 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1235
98112041 1236 ret = dwc3_phy_setup(dwc);
941f918e 1237 if (ret)
d2f19782 1238 return ret;
4878a028 1239
98112041
RQ		 1240 if (!dwc->ulpi_ready) {
1241 ret = dwc3_core_ulpi_init(dwc);
63130462
FT		 1242 if (ret) {
1243 if (ret == -ETIMEDOUT) {
1244 dwc3_core_soft_reset(dwc);
1245 ret = -EPROBE_DEFER;
1246 }
d2f19782 1247 return ret;
63130462 1248 }
98112041
RQ		 1249 dwc->ulpi_ready = true;
1250 }
4878a028 1251
98112041
RQ		 1252 if (!dwc->phys_ready) {
1253 ret = dwc3_core_get_phy(dwc);
1254 if (ret)
d2f19782 1255 goto err_exit_ulpi;
98112041
RQ		 1256 dwc->phys_ready = true;
1257 }
1258
1d72fab4
JH		 1259 ret = dwc3_phy_init(dwc);
1260 if (ret)
1261 goto err_exit_ulpi;
8cfac9a6 1262
98112041 1263 ret = dwc3_core_soft_reset(dwc);
f54edb53 1264 if (ret)
1d72fab4 1265 goto err_exit_phy;
f54edb53 1266
9ba3aca8 1267 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
9af21dd6 1268 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
9ba3aca8
TN		 1269 if (!dwc->dis_u3_susphy_quirk) {
1270 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1271 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1272 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1273 }
1274
1275 if (!dwc->dis_u2_susphy_quirk) {
1276 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1277 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1278 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1279 }
1280 }
1281
941f918e 1282 dwc3_core_setup_global_control(dwc);
c499ff71 1283 dwc3_core_num_eps(dwc);
0ffcaf37 1284
3497b9a5
LJ		 1285 /* Set power down scale of suspend_clk */
1286 dwc3_set_power_down_clk_scale(dwc);
1287
c499ff71
FB		 1288 /* Adjust Frame Length */
1289 dwc3_frame_length_adjustment(dwc);
1290
7bee3188
BP		 1291 /* Adjust Reference Clock Period */
1292 dwc3_ref_clk_period(dwc);
1293
d9612c2f
PM		 1294 dwc3_set_incr_burst_type(dwc);
1295
8018018d 1296 ret = dwc3_phy_power_on(dwc);
1d72fab4
JH		 1297 if (ret)
1298 goto err_exit_phy;
c499ff71
FB		 1299
1300 ret = dwc3_event_buffers_setup(dwc);
1301 if (ret) {
1302 dev_err(dwc->dev, "failed to setup event buffers\n");
1d72fab4 1303 goto err_power_off_phy;
c499ff71
FB		 1304 }
1305
06281d46
JY		 1306 /*
1307 * ENDXFER polling is available on version 3.10a and later of
1308 * the DWC_usb3 controller. It is NOT available in the
1309 * DWC_usb31 controller.
1310 */
9af21dd6 1311 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
06281d46
JY		 1312 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1313 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1314 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1315 }
1316
63d7f981
PM		 1317 /*
1318 * When configured in HOST mode, after issuing U3/L2 exit controller
1319 * fails to send proper CRC checksum in CRC5 feild. Because of this
1320 * behaviour Transaction Error is generated, resulting in reset and
1321 * re-enumeration of usb device attached. All the termsel, xcvrsel,
1322 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1
1323 * will correct this problem. This option is to support certain
1324 * legacy ULPI PHYs.
1325 */
1326 if (dwc->resume_hs_terminations) {
1327 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1328 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
1329 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1330 }
1331
9af21dd6 1332 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
0bb39ca1 1333 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
65db7a0c
WW		 1334
1335 /*
1336 * Enable hardware control of sending remote wakeup
1337 * in HS when the device is in the L1 state.
1338 */
9af21dd6 1339 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
65db7a0c
WW		 1340 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1341
843714bb
JP		 1342 /*
1343 * Decouple USB 2.0 L1 & L2 events which will allow for
1344 * gadget driver to only receive U3/L2 suspend & wakeup
1345 * events and prevent the more frequent L1 LPM transitions
1346 * from interrupting the driver.
1347 */
1348 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1349 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1350
65db7a0c
WW		 1351 if (dwc->dis_tx_ipgap_linecheck_quirk)
1352 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1353
7ba6b09f
NA		 1354 if (dwc->parkmode_disable_ss_quirk)
1355 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1356
d21a797a
SC		 1357 if (dwc->parkmode_disable_hs_quirk)
1358 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS;
1359
62b20e6e
BY		 1360 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
1361 (dwc->maximum_speed == USB_SPEED_HIGH ||
1362 dwc->maximum_speed == USB_SPEED_FULL))
1363 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1364
0bb39ca1
JY		 1365 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1366 }
1367
e72fc8d6 1368 dwc3_config_threshold(dwc);
938a5ad1 1369
72246da4
FB		 1370 return 0;
1371
1d72fab4
JH		 1372err_power_off_phy:
1373 dwc3_phy_power_off(dwc);
1374err_exit_phy:
1375 dwc3_phy_exit(dwc);
d2f19782 1376err_exit_ulpi:
98112041
RQ		 1377 dwc3_ulpi_exit(dwc);
1378
72246da4
FB		 1379 return ret;
1380}
1381
3c9f94ac 1382static int dwc3_core_get_phy(struct dwc3 *dwc)
72246da4 1383{
3c9f94ac 1384 struct device *dev = dwc->dev;
941ea361 1385 struct device_node *node = dev->of_node;
3c9f94ac 1386 int ret;
72246da4 1387
5088b6f5
KVA		 1388 if (node) {
1389 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1390 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
bb674907
FB		 1391 } else {
1392 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1393 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
5088b6f5
KVA		 1394 }
1395
d105e7f8
FB		 1396 if (IS_ERR(dwc->usb2_phy)) {
1397 ret = PTR_ERR(dwc->usb2_phy);
d090c7a2 1398 if (ret == -ENXIO || ret == -ENODEV)
122f06e6 1399 dwc->usb2_phy = NULL;
d090c7a2 1400 else
0c0a20f6 1401 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
51e1e7bc
FB		 1402 }
1403
d105e7f8 1404 if (IS_ERR(dwc->usb3_phy)) {
315955d7 1405 ret = PTR_ERR(dwc->usb3_phy);
d090c7a2 1406 if (ret == -ENXIO || ret == -ENODEV)
122f06e6 1407 dwc->usb3_phy = NULL;
d090c7a2 1408 else
0c0a20f6 1409 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
51e1e7bc
FB		 1410 }
1411
57303488
KVA		 1412 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1413 if (IS_ERR(dwc->usb2_generic_phy)) {
1414 ret = PTR_ERR(dwc->usb2_generic_phy);
fb119dcb 1415 if (ret == -ENOSYS || ret == -ENODEV)
57303488 1416 dwc->usb2_generic_phy = NULL;
d090c7a2 1417 else
0c0a20f6 1418 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
57303488
KVA		 1419 }
1420
1421 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1422 if (IS_ERR(dwc->usb3_generic_phy)) {
1423 ret = PTR_ERR(dwc->usb3_generic_phy);
fb119dcb 1424 if (ret == -ENOSYS || ret == -ENODEV)
57303488 1425 dwc->usb3_generic_phy = NULL;
d090c7a2 1426 else
0c0a20f6 1427 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
57303488
KVA		 1428 }
1429
3c9f94ac
FB		 1430 return 0;
1431}
1432
5f94adfe
FB		 1433static int dwc3_core_init_mode(struct dwc3 *dwc)
1434{
1435 struct device *dev = dwc->dev;
1436 int ret;
1437
1438 switch (dwc->dr_mode) {
1439 case USB_DR_MODE_PERIPHERAL:
41ce1456 1440 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
958d1a4c
FB		 1441
1442 if (dwc->usb2_phy)
1443 otg_set_vbus(dwc->usb2_phy->otg, false);
644cbbc3
MG		 1444 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1445 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
958d1a4c 1446
5f94adfe 1447 ret = dwc3_gadget_init(dwc);
0c0a20f6
AS		 1448 if (ret)
1449 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
5f94adfe
FB		 1450 break;
1451 case USB_DR_MODE_HOST:
41ce1456 1452 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
958d1a4c
FB		 1453
1454 if (dwc->usb2_phy)
1455 otg_set_vbus(dwc->usb2_phy->otg, true);
644cbbc3
MG		 1456 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1457 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
958d1a4c 1458
5f94adfe 1459 ret = dwc3_host_init(dwc);
0c0a20f6
AS		 1460 if (ret)
1461 return dev_err_probe(dev, ret, "failed to initialize host\n");
5f94adfe
FB		 1462 break;
1463 case USB_DR_MODE_OTG:
41ce1456 1464 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
9840354f 1465 ret = dwc3_drd_init(dwc);
0c0a20f6
AS		 1466 if (ret)
1467 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
5f94adfe
FB		 1468 break;
1469 default:
1470 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1471 return -EINVAL;
1472 }
1473
1474 return 0;
1475}
1476
1477static void dwc3_core_exit_mode(struct dwc3 *dwc)
1478{
1479 switch (dwc->dr_mode) {
1480 case USB_DR_MODE_PERIPHERAL:
1481 dwc3_gadget_exit(dwc);
1482 break;
1483 case USB_DR_MODE_HOST:
1484 dwc3_host_exit(dwc);
1485 break;
1486 case USB_DR_MODE_OTG:
9840354f 1487 dwc3_drd_exit(dwc);
5f94adfe
FB		 1488 break;
1489 default:
1490 /* do nothing */
1491 break;
1492 }
09ed259f
BL		 1493
1494 /* de-assert DRVVBUS for HOST and OTG mode */
1495 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
5f94adfe
FB		 1496}
1497
c5ac6116 1498static void dwc3_get_properties(struct dwc3 *dwc)
3c9f94ac 1499{
c5ac6116 1500 struct device *dev = dwc->dev;
80caf7d2 1501 u8 lpm_nyet_threshold;
6b6a0c9a 1502 u8 tx_de_emphasis;
460d098c 1503 u8 hird_threshold;
e72fc8d6
SC		 1504 u8 rx_thr_num_pkt = 0;
1505 u8 rx_max_burst = 0;
1506 u8 tx_thr_num_pkt = 0;
1507 u8 tx_max_burst = 0;
f28ad906
TN		 1508 u8 rx_thr_num_pkt_prd = 0;
1509 u8 rx_max_burst_prd = 0;
1510 u8 tx_thr_num_pkt_prd = 0;
1511 u8 tx_max_burst_prd = 0;
9f607a30 1512 u8 tx_fifo_resize_max_num;
6f0764b5
RC		 1513 const char *usb_psy_name;
1514 int ret;
3c9f94ac 1515
80caf7d2 1516 /* default to highest possible threshold */
8d791929 1517 lpm_nyet_threshold = 0xf;
80caf7d2 1518
6b6a0c9a
HR		 1519 /* default to -3.5dB de-emphasis */
1520 tx_de_emphasis = 1;
1521
460d098c
HR		 1522 /*
1523 * default to assert utmi_sleep_n and use maximum allowed HIRD
1524 * threshold value of 0b1100
1525 */
1526 hird_threshold = 12;
1527
9f607a30
WC		 1528 /*
1529 * default to a TXFIFO size large enough to fit 6 max packets. This
1530 * allows for systems with larger bus latencies to have some headroom
1531 * for endpoints that have a large bMaxBurst value.
1532 */
1533 tx_fifo_resize_max_num = 6;
1534
63863b98 1535 dwc->maximum_speed = usb_get_maximum_speed(dev);
67848146 1536 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
06e7114f 1537 dwc->dr_mode = usb_get_dr_mode(dev);
32f2ed86 1538 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
63863b98 1539
d64ff406
AB		 1540 dwc->sysdev_is_parent = device_property_read_bool(dev,
1541 "linux,sysdev_is_parent");
1542 if (dwc->sysdev_is_parent)
1543 dwc->sysdev = dwc->dev->parent;
1544 else
1545 dwc->sysdev = dwc->dev;
1546
6f0764b5
RC		 1547 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1548 if (ret >= 0) {
1549 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1550 if (!dwc->usb_psy)
1551 dev_err(dev, "couldn't get usb power supply\n");
1552 }
1553
3d128919 1554 dwc->has_lpm_erratum = device_property_read_bool(dev,
80caf7d2 1555 "snps,has-lpm-erratum");
3d128919 1556 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
80caf7d2 1557 &lpm_nyet_threshold);
3d128919 1558 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
460d098c 1559 "snps,is-utmi-l1-suspend");
3d128919 1560 device_property_read_u8(dev, "snps,hird-threshold",
460d098c 1561 &hird_threshold);
d92021f6
TN		 1562 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1563 "snps,dis-start-transfer-quirk");
3d128919 1564 dwc->usb3_lpm_capable = device_property_read_bool(dev,
eac68e8f 1565 "snps,usb3_lpm_capable");
022a0208
TN		 1566 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1567 "snps,usb2-lpm-disable");
475e8be5
TN		 1568 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1569 "snps,usb2-gadget-lpm-disable");
e72fc8d6
SC		 1570 device_property_read_u8(dev, "snps,rx-thr-num-pkt",
1571 &rx_thr_num_pkt);
1572 device_property_read_u8(dev, "snps,rx-max-burst",
1573 &rx_max_burst);
1574 device_property_read_u8(dev, "snps,tx-thr-num-pkt",
1575 &tx_thr_num_pkt);
1576 device_property_read_u8(dev, "snps,tx-max-burst",
1577 &tx_max_burst);
938a5ad1
TN		 1578 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1579 &rx_thr_num_pkt_prd);
1580 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1581 &rx_max_burst_prd);
1582 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1583 &tx_thr_num_pkt_prd);
1584 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1585 &tx_max_burst_prd);
9f607a30
WC		 1586 dwc->do_fifo_resize = device_property_read_bool(dev,
1587 "tx-fifo-resize");
1588 if (dwc->do_fifo_resize)
1589 device_property_read_u8(dev, "tx-fifo-max-num",
1590 &tx_fifo_resize_max_num);
3c9f94ac 1591
3d128919 1592 dwc->disable_scramble_quirk = device_property_read_bool(dev,
3b81221a 1593 "snps,disable_scramble_quirk");
3d128919 1594 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
9a5b2f31 1595 "snps,u2exit_lfps_quirk");
3d128919 1596 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
b5a65c40 1597 "snps,u2ss_inp3_quirk");
3d128919 1598 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
df31f5b3 1599 "snps,req_p1p2p3_quirk");
3d128919 1600 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
a2a1d0f5 1601 "snps,del_p1p2p3_quirk");
3d128919 1602 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
41c06ffd 1603 "snps,del_phy_power_chg_quirk");
3d128919 1604 dwc->lfps_filter_quirk = device_property_read_bool(dev,
fb67afca 1605 "snps,lfps_filter_quirk");
3d128919 1606 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
14f4ac53 1607 "snps,rx_detect_poll_quirk");
3d128919 1608 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
59acfa20 1609 "snps,dis_u3_susphy_quirk");
3d128919 1610 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
0effe0a3 1611 "snps,dis_u2_susphy_quirk");
ec791d14
JY		 1612 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1613 "snps,dis_enblslpm_quirk");
729dcffd
AKV		 1614 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1615 "snps,dis-u1-entry-quirk");
1616 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1617 "snps,dis-u2-entry-quirk");
e58dd357
RB		 1618 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1619 "snps,dis_rxdet_inp3_quirk");
16199f33
WW		 1620 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1621 "snps,dis-u2-freeclk-exists-quirk");
00fe081d
WW		 1622 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1623 "snps,dis-del-phy-power-chg-quirk");
65db7a0c
WW		 1624 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1625 "snps,dis-tx-ipgap-linecheck-quirk");
63d7f981
PM		 1626 dwc->resume_hs_terminations = device_property_read_bool(dev,
1627 "snps,resume-hs-terminations");
b84ba26c
PM		 1628 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
1629 "snps,ulpi-ext-vbus-drv");
7ba6b09f
NA		 1630 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1631 "snps,parkmode-disable-ss-quirk");
d21a797a
SC		 1632 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev,
1633 "snps,parkmode-disable-hs-quirk");
a6fc2f1b
AS		 1634 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
1635 "snps,gfladj-refclk-lpm-sel-quirk");
6b6a0c9a 1636
3d128919 1637 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
6b6a0c9a 1638 "snps,tx_de_emphasis_quirk");
3d128919 1639 device_property_read_u8(dev, "snps,tx_de_emphasis",
6b6a0c9a 1640 &tx_de_emphasis);
3d128919
HK		 1641 device_property_read_string(dev, "snps,hsphy_interface",
1642 &dwc->hsphy_interface);
1643 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
bcdb3272 1644 &dwc->fladj);
7bee3188
BP		 1645 device_property_read_u32(dev, "snps,ref-clock-period-ns",
1646 &dwc->ref_clk_per);
3d128919 1647
42bf02ec
RQ		 1648 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1649 "snps,dis_metastability_quirk");
1650
f580170f
YC		 1651 dwc->dis_split_quirk = device_property_read_bool(dev,
1652 "snps,dis-split-quirk");
1653
80caf7d2 1654 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
6b6a0c9a 1655 dwc->tx_de_emphasis = tx_de_emphasis;
80caf7d2 1656
16fe4f30 1657 dwc->hird_threshold = hird_threshold;
460d098c 1658
e72fc8d6
SC		 1659 dwc->rx_thr_num_pkt = rx_thr_num_pkt;
1660 dwc->rx_max_burst = rx_max_burst;
1661
1662 dwc->tx_thr_num_pkt = tx_thr_num_pkt;
1663 dwc->tx_max_burst = tx_max_burst;
1664
938a5ad1
TN		 1665 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1666 dwc->rx_max_burst_prd = rx_max_burst_prd;
1667
1668 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1669 dwc->tx_max_burst_prd = tx_max_burst_prd;
1670
cf40b86b 1671 dwc->imod_interval = 0;
9f607a30
WC		 1672
1673 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
cf40b86b
JY		 1674}
1675
1676/* check whether the core supports IMOD */
1677bool dwc3_has_imod(struct dwc3 *dwc)
1678{
9af21dd6
TN		 1679 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1680 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1681 DWC3_IP_IS(DWC32);
c5ac6116
FB		 1682}
1683
7ac51a12
JY		 1684static void dwc3_check_params(struct dwc3 *dwc)
1685{
1686 struct device *dev = dwc->dev;
b574ce3e
TN		 1687 unsigned int hwparam_gen =
1688 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
7ac51a12 1689
cf40b86b
JY		 1690 /* Check for proper value of imod_interval */
1691 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1692 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1693 dwc->imod_interval = 0;
1694 }
1695
28632b44
JY		 1696 /*
1697 * Workaround for STAR 9000961433 which affects only version
1698 * 3.00a of the DWC_usb3 core. This prevents the controller
1699 * interrupt from being masked while handling events. IMOD
1700 * allows us to work around this issue. Enable it for the
1701 * affected version.
1702 */
1703 if (!dwc->imod_interval &&
9af21dd6 1704 DWC3_VER_IS(DWC3, 300A))
28632b44
JY		 1705 dwc->imod_interval = 1;
1706
7ac51a12
JY		 1707 /* Check the maximum_speed parameter */
1708 switch (dwc->maximum_speed) {
7ac51a12
JY		 1709 case USB_SPEED_FULL:
1710 case USB_SPEED_HIGH:
e518bdd9 1711 break;
7ac51a12 1712 case USB_SPEED_SUPER:
e518bdd9
TN		 1713 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1714 dev_warn(dev, "UDC doesn't support Gen 1\n");
1715 break;
7ac51a12 1716 case USB_SPEED_SUPER_PLUS:
e518bdd9
TN		 1717 if ((DWC3_IP_IS(DWC32) &&
1718 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1719 (!DWC3_IP_IS(DWC32) &&
1720 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1721 dev_warn(dev, "UDC doesn't support SSP\n");
7ac51a12
JY		 1722 break;
1723 default:
1724 dev_err(dev, "invalid maximum_speed parameter %d\n",
1725 dwc->maximum_speed);
df561f66 1726 fallthrough;
7ac51a12 1727 case USB_SPEED_UNKNOWN:
b574ce3e
TN		 1728 switch (hwparam_gen) {
1729 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
7ac51a12 1730 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
b574ce3e
TN		 1731 break;
1732 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1733 if (DWC3_IP_IS(DWC32))
1734 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1735 else
1736 dwc->maximum_speed = USB_SPEED_SUPER;
1737 break;
1738 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1739 dwc->maximum_speed = USB_SPEED_HIGH;
1740 break;
1741 default:
1742 dwc->maximum_speed = USB_SPEED_SUPER;
1743 break;
1744 }
7ac51a12
JY		 1745 break;
1746 }
67848146
TN		 1747
1748 /*
1749 * Currently the controller does not have visibility into the HW
1750 * parameter to determine the maximum number of lanes the HW supports.
1751 * If the number of lanes is not specified in the device property, then
1752 * set the default to support dual-lane for DWC_usb32 and single-lane
1753 * for DWC_usb31 for super-speed-plus.
1754 */
1755 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1756 switch (dwc->max_ssp_rate) {
1757 case USB_SSP_GEN_2x1:
1758 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1759 dev_warn(dev, "UDC only supports Gen 1\n");
1760 break;
1761 case USB_SSP_GEN_1x2:
1762 case USB_SSP_GEN_2x2:
1763 if (DWC3_IP_IS(DWC31))
1764 dev_warn(dev, "UDC only supports single lane\n");
1765 break;
1766 case USB_SSP_GEN_UNKNOWN:
1767 default:
1768 switch (hwparam_gen) {
1769 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1770 if (DWC3_IP_IS(DWC32))
1771 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1772 else
1773 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1774 break;
1775 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1776 if (DWC3_IP_IS(DWC32))
1777 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1778 break;
1779 }
1780 break;
1781 }
1782 }
7ac51a12
JY		 1783}
1784
d182c2e1
AS		 1785static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1786{
1787 struct device *dev = dwc->dev;
1788 struct device_node *np_phy;
1789 struct extcon_dev *edev = NULL;
1790 const char *name;
1791
1792 if (device_property_read_bool(dev, "extcon"))
1793 return extcon_get_edev_by_phandle(dev, 0);
1794
1795 /*
1796 * Device tree platforms should get extcon via phandle.
1797 * On ACPI platforms, we get the name from a device property.
1798 * This device property is for kernel internal use only and
1799 * is expected to be set by the glue code.
1800 */
1801 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
1802 return extcon_get_extcon_dev(name);
1803
d68cc25b
JG		 1804 /*
1805 * Check explicitly if "usb-role-switch" is used since
1806 * extcon_find_edev_by_node() can not be used to check the absence of
1807 * an extcon device. In the absence of an device it will always return
1808 * EPROBE_DEFER.
1809 */
1810 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) &&
1811 device_property_read_bool(dev, "usb-role-switch"))
1812 return NULL;
1813
d182c2e1
AS		 1814 /*
1815 * Try to get an extcon device from the USB PHY controller's "port"
1816 * node. Check if it has the "port" node first, to avoid printing the
1817 * error message from underlying code, as it's a valid case: extcon
1818 * device (and "port" node) may be missing in case of "usb-role-switch"
1819 * or OTG mode.
1820 */
1821 np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1822 if (of_graph_is_present(np_phy)) {
1823 struct device_node *np_conn;
1824
1825 np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1826 if (np_conn)
1827 edev = extcon_find_edev_by_node(np_conn);
1828 of_node_put(np_conn);
1829 }
1830 of_node_put(np_phy);
1831
1832 return edev;
1833}
1834
bd828574
JH		 1835static int dwc3_get_clocks(struct dwc3 *dwc)
1836{
1837 struct device *dev = dwc->dev;
1838
1839 if (!dev->of_node)
1840 return 0;
1841
1842 /*
1843 * Clocks are optional, but new DT platforms should support all clocks
1844 * as required by the DT-binding.
1845 * Some devices have different clock names in legacy device trees,
1846 * check for them to retain backwards compatibility.
1847 */
1848 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1849 if (IS_ERR(dwc->bus_clk)) {
1850 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1851 "could not get bus clock\n");
1852 }
1853
1854 if (dwc->bus_clk == NULL) {
1855 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1856 if (IS_ERR(dwc->bus_clk)) {
1857 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1858 "could not get bus clock\n");
1859 }
1860 }
1861
1862 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1863 if (IS_ERR(dwc->ref_clk)) {
1864 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1865 "could not get ref clock\n");
1866 }
1867
1868 if (dwc->ref_clk == NULL) {
1869 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1870 if (IS_ERR(dwc->ref_clk)) {
1871 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1872 "could not get ref clock\n");
1873 }
1874 }
1875
1876 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1877 if (IS_ERR(dwc->susp_clk)) {
1878 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1879 "could not get suspend clock\n");
1880 }
1881
1882 if (dwc->susp_clk == NULL) {
1883 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1884 if (IS_ERR(dwc->susp_clk)) {
1885 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1886 "could not get suspend clock\n");
1887 }
1888 }
1889
97789b93
SR		 1890 /* specific to Rockchip RK3588 */
1891 dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
1892 if (IS_ERR(dwc->utmi_clk)) {
1893 return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
1894 "could not get utmi clock\n");
1895 }
1896
1897 /* specific to Rockchip RK3588 */
1898 dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
1899 if (IS_ERR(dwc->pipe_clk)) {
1900 return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
1901 "could not get pipe clock\n");
1902 }
1903
bd828574
JH		 1904 return 0;
1905}
1906
c5ac6116
FB		 1907static int dwc3_probe(struct platform_device *pdev)
1908{
1909 struct device *dev = &pdev->dev;
44feb8e6 1910 struct resource *res, dwc_res;
9a4d7dd1 1911 void __iomem *regs;
c5ac6116 1912 struct dwc3 *dwc;
c5ac6116
FB		 1913 int ret;
1914
c5ac6116
FB		 1915 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1916 if (!dwc)
1917 return -ENOMEM;
1918
1919 dwc->dev = dev;
1920
1921 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1922 if (!res) {
1923 dev_err(dev, "missing memory resource\n");
1924 return -ENODEV;
1925 }
1926
1927 dwc->xhci_resources[0].start = res->start;
1928 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1929 DWC3_XHCI_REGS_END;
1930 dwc->xhci_resources[0].flags = res->flags;
1931 dwc->xhci_resources[0].name = res->name;
1932
c5ac6116
FB		 1933 /*
1934 * Request memory region but exclude xHCI regs,
1935 * since it will be requested by the xhci-plat driver.
1936 */
44feb8e6
MY		 1937 dwc_res = *res;
1938 dwc_res.start += DWC3_GLOBALS_REGS_START;
1939
ec5eb438
SC		 1940 if (dev->of_node) {
1941 struct device_node *parent = of_get_parent(dev->of_node);
1942
1943 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) {
1944 dwc_res.start -= DWC3_GLOBALS_REGS_START;
1945 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
1946 }
1947
1948 of_node_put(parent);
1949 }
1950
44feb8e6
MY		 1951 regs = devm_ioremap_resource(dev, &dwc_res);
1952 if (IS_ERR(regs))
1953 return PTR_ERR(regs);
c5ac6116
FB		 1954
1955 dwc->regs = regs;
44feb8e6 1956 dwc->regs_size = resource_size(&dwc_res);
c5ac6116
FB		 1957
1958 dwc3_get_properties(dwc);
1959
babbdfc9 1960 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
2a735e4b
DC		 1961 if (IS_ERR(dwc->reset)) {
1962 ret = PTR_ERR(dwc->reset);
fe296046 1963 goto err_put_psy;
2a735e4b 1964 }
fe8abf33 1965
bd828574
JH		 1966 ret = dwc3_get_clocks(dwc);
1967 if (ret)
1968 goto err_put_psy;
fe8abf33
MY		 1969
1970 ret = reset_control_deassert(dwc->reset);
1971 if (ret)
fe296046 1972 goto err_put_psy;
fe8abf33 1973
33fb697e 1974 ret = dwc3_clk_enable(dwc);
fe8abf33 1975 if (ret)
fe296046 1976 goto err_assert_reset;
fe8abf33 1977
dc1b5d9a
EBS		 1978 if (!dwc3_core_is_valid(dwc)) {
1979 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1980 ret = -ENODEV;
fe296046 1981 goto err_disable_clks;
dc1b5d9a
EBS		 1982 }
1983
6c89cce0 1984 platform_set_drvdata(pdev, dwc);
2917e718 1985 dwc3_cache_hwparams(dwc);
6c89cce0 1986
91062e66
WW		 1987 if (!dwc->sysdev_is_parent &&
1988 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
1989 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1990 if (ret)
fe296046 1991 goto err_disable_clks;
91062e66
WW		 1992 }
1993
72246da4 1994 spin_lock_init(&dwc->lock);
f88359e1 1995 mutex_init(&dwc->mutex);
72246da4 1996
9a8ad10c 1997 pm_runtime_get_noresume(dev);
fc8bb91b
FB		 1998 pm_runtime_set_active(dev);
1999 pm_runtime_use_autosuspend(dev);
2000 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
802ca850 2001 pm_runtime_enable(dev);
32808237 2002
802ca850 2003 pm_runtime_forbid(dev);
72246da4 2004
3921426b
FB		 2005 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
2006 if (ret) {
2007 dev_err(dwc->dev, "failed to allocate event buffers\n");
2008 ret = -ENOMEM;
fe296046 2009 goto err_allow_rpm;
3921426b
FB		 2010 }
2011
d182c2e1
AS		 2012 dwc->edev = dwc3_get_extcon(dwc);
2013 if (IS_ERR(dwc->edev)) {
2014 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n");
fe296046 2015 goto err_free_event_buffers;
d182c2e1
AS		 2016 }
2017
9d6173e1
TN		 2018 ret = dwc3_get_dr_mode(dwc);
2019 if (ret)
fe296046 2020 goto err_free_event_buffers;
32a4a135 2021
72246da4
FB		 2022 ret = dwc3_core_init(dwc);
2023 if (ret) {
0c0a20f6 2024 dev_err_probe(dev, ret, "failed to initialize core\n");
fe296046 2025 goto err_free_event_buffers;
72246da4
FB		 2026 }
2027
7ac51a12 2028 dwc3_check_params(dwc);
84524d12 2029 dwc3_debugfs_init(dwc);
2c7f1bd9 2030
5f94adfe
FB		 2031 ret = dwc3_core_init_mode(dwc);
2032 if (ret)
fe296046 2033 goto err_exit_debugfs;
72246da4 2034
fc8bb91b 2035 pm_runtime_put(dev);
72246da4 2036
8bbae288
RR		 2037 dma_set_max_seg_size(dev, UINT_MAX);
2038
72246da4
FB		 2039 return 0;
2040
fe296046 2041err_exit_debugfs:
84524d12 2042 dwc3_debugfs_exit(dwc);
c499ff71 2043 dwc3_event_buffers_cleanup(dwc);
1d72fab4
JH		 2044 dwc3_phy_power_off(dwc);
2045 dwc3_phy_exit(dwc);
08fd9a82 2046 dwc3_ulpi_exit(dwc);
fe296046 2047err_free_event_buffers:
3921426b 2048 dwc3_free_event_buffers(dwc);
fe296046 2049err_allow_rpm:
9a8ad10c
JH		 2050 pm_runtime_allow(dev);
2051 pm_runtime_disable(dev);
6b3b2402 2052 pm_runtime_dont_use_autosuspend(dev);
9a8ad10c
JH		 2053 pm_runtime_set_suspended(dev);
2054 pm_runtime_put_noidle(dev);
fe296046 2055err_disable_clks:
33fb697e 2056 dwc3_clk_disable(dwc);
fe296046 2057err_assert_reset:
fe8abf33 2058 reset_control_assert(dwc->reset);
fe296046 2059err_put_psy:
b0bf77cd 2060 if (dwc->usb_psy)
6f0764b5
RC		 2061 power_supply_put(dwc->usb_psy);
2062
72246da4
FB		 2063 return ret;
2064}
2065
01765687 2066static void dwc3_remove(struct platform_device *pdev)
72246da4 2067{
72246da4 2068 struct dwc3 *dwc = platform_get_drvdata(pdev);
3da1f6ee 2069
fc8bb91b 2070 pm_runtime_get_sync(&pdev->dev);
72246da4 2071
dc99f16f 2072 dwc3_core_exit_mode(dwc);
2a042767 2073 dwc3_debugfs_exit(dwc);
8ba007a9 2074
72246da4 2075 dwc3_core_exit(dwc);
88bc9d19 2076 dwc3_ulpi_exit(dwc);
72246da4 2077
44d257e9 2078 pm_runtime_allow(&pdev->dev);
72246da4 2079 pm_runtime_disable(&pdev->dev);
6b3b2402 2080 pm_runtime_dont_use_autosuspend(&pdev->dev);
266d0493 2081 pm_runtime_put_noidle(&pdev->dev);
e3dbb657
JH		 2082 /*
2083 * HACK: Clear the driver data, which is currently accessed by parent
2084 * glue drivers, before allowing the parent to suspend.
2085 */
2086 platform_set_drvdata(pdev, NULL);
266d0493 2087 pm_runtime_set_suspended(&pdev->dev);
72246da4 2088
fc8bb91b 2089 dwc3_free_event_buffers(dwc);
fc8bb91b 2090
b0bf77cd 2091 if (dwc->usb_psy)
6f0764b5 2092 power_supply_put(dwc->usb_psy);
72246da4
FB		 2093}
2094
fc8bb91b 2095#ifdef CONFIG_PM
fe8abf33
MY		 2096static int dwc3_core_init_for_resume(struct dwc3 *dwc)
2097{
2098 int ret;
2099
2100 ret = reset_control_deassert(dwc->reset);
2101 if (ret)
2102 return ret;
2103
33fb697e 2104 ret = dwc3_clk_enable(dwc);
fe8abf33
MY		 2105 if (ret)
2106 goto assert_reset;
2107
fe8abf33
MY		 2108 ret = dwc3_core_init(dwc);
2109 if (ret)
2110 goto disable_clks;
2111
2112 return 0;
2113
2114disable_clks:
33fb697e 2115 dwc3_clk_disable(dwc);
fe8abf33
MY		 2116assert_reset:
2117 reset_control_assert(dwc->reset);
2118
2119 return ret;
2120}
2121
c4a5153e 2122static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
7415f17c 2123{
fc8bb91b 2124 unsigned long flags;
bcb12877 2125 u32 reg;
7415f17c 2126
689bf72c
MG		 2127 switch (dwc->current_dr_role) {
2128 case DWC3_GCTL_PRTCAP_DEVICE:
0227cc84
LJ		 2129 if (pm_runtime_suspended(dwc->dev))
2130 break;
7415f17c 2131 dwc3_gadget_suspend(dwc);
41a91c60 2132 synchronize_irq(dwc->irq_gadget);
689bf72c 2133 dwc3_core_exit(dwc);
51f5d49a 2134 break;
689bf72c 2135 case DWC3_GCTL_PRTCAP_HOST:
e3fafbd8 2136 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
c4a5153e 2137 dwc3_core_exit(dwc);
bcb12877
MG		 2138 break;
2139 }
2140
2141 /* Let controller to suspend HSPHY before PHY driver suspends */
2142 if (dwc->dis_u2_susphy_quirk ||
2143 dwc->dis_enblslpm_quirk) {
2144 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2145 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
2146 DWC3_GUSB2PHYCFG_SUSPHY;
2147 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2148
2149 /* Give some time for USB2 PHY to suspend */
2150 usleep_range(5000, 6000);
2151 }
2152
2153 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
2154 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
c4a5153e 2155 break;
f09cc79b
RQ		 2156 case DWC3_GCTL_PRTCAP_OTG:
2157 /* do nothing during runtime_suspend */
2158 if (PMSG_IS_AUTO(msg))
2159 break;
2160
2161 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2162 spin_lock_irqsave(&dwc->lock, flags);
2163 dwc3_gadget_suspend(dwc);
2164 spin_unlock_irqrestore(&dwc->lock, flags);
41a91c60 2165 synchronize_irq(dwc->irq_gadget);
f09cc79b
RQ		 2166 }
2167
2168 dwc3_otg_exit(dwc);
2169 dwc3_core_exit(dwc);
2170 break;
7415f17c 2171 default:
51f5d49a 2172 /* do nothing */
7415f17c
FB		 2173 break;
2174 }
2175
7415f17c
FB		 2176 return 0;
2177}
2178
c4a5153e 2179static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
7415f17c 2180{
fc8bb91b 2181 unsigned long flags;
57303488 2182 int ret;
bcb12877 2183 u32 reg;
7415f17c 2184
689bf72c
MG		 2185 switch (dwc->current_dr_role) {
2186 case DWC3_GCTL_PRTCAP_DEVICE:
fe8abf33 2187 ret = dwc3_core_init_for_resume(dwc);
689bf72c
MG		 2188 if (ret)
2189 return ret;
5c4ad318 2190
7d11c3ac 2191 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
7415f17c 2192 dwc3_gadget_resume(dwc);
689bf72c
MG		 2193 break;
2194 case DWC3_GCTL_PRTCAP_HOST:
e3fafbd8 2195 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
fe8abf33 2196 ret = dwc3_core_init_for_resume(dwc);
c4a5153e
MG		 2197 if (ret)
2198 return ret;
7d11c3ac 2199 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
bcb12877 2200 break;
c4a5153e 2201 }
bcb12877
MG		 2202 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2203 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2204 if (dwc->dis_u2_susphy_quirk)
2205 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2206
2207 if (dwc->dis_enblslpm_quirk)
2208 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2209
2210 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2211
2212 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
2213 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
f09cc79b
RQ		 2214 break;
2215 case DWC3_GCTL_PRTCAP_OTG:
2216 /* nothing to do on runtime_resume */
2217 if (PMSG_IS_AUTO(msg))
2218 break;
2219
0e5a3c82 2220 ret = dwc3_core_init_for_resume(dwc);
f09cc79b
RQ		 2221 if (ret)
2222 return ret;
2223
2224 dwc3_set_prtcap(dwc, dwc->current_dr_role);
2225
2226 dwc3_otg_init(dwc);
2227 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2228 dwc3_otg_host_init(dwc);
2229 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2230 spin_lock_irqsave(&dwc->lock, flags);
2231 dwc3_gadget_resume(dwc);
2232 spin_unlock_irqrestore(&dwc->lock, flags);
c4a5153e 2233 }
f09cc79b 2234
c4a5153e 2235 break;
7415f17c
FB		 2236 default:
2237 /* do nothing */
2238 break;
2239 }
2240
fc8bb91b
FB		 2241 return 0;
2242}
2243
2244static int dwc3_runtime_checks(struct dwc3 *dwc)
2245{
689bf72c 2246 switch (dwc->current_dr_role) {
c4a5153e 2247 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 2248 if (dwc->connected)
2249 return -EBUSY;
2250 break;
c4a5153e 2251 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 2252 default:
2253 /* do nothing */
2254 break;
2255 }
2256
2257 return 0;
2258}
2259
2260static int dwc3_runtime_suspend(struct device *dev)
2261{
2262 struct dwc3 *dwc = dev_get_drvdata(dev);
2263 int ret;
2264
2265 if (dwc3_runtime_checks(dwc))
2266 return -EBUSY;
2267
c4a5153e 2268 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
fc8bb91b
FB		 2269 if (ret)
2270 return ret;
2271
fc8bb91b
FB		 2272 return 0;
2273}
2274
2275static int dwc3_runtime_resume(struct device *dev)
2276{
2277 struct dwc3 *dwc = dev_get_drvdata(dev);
2278 int ret;
2279
c4a5153e 2280 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
fc8bb91b
FB		 2281 if (ret)
2282 return ret;
2283
689bf72c
MG		 2284 switch (dwc->current_dr_role) {
2285 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 2286 dwc3_gadget_process_pending_events(dwc);
2287 break;
689bf72c 2288 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 2289 default:
2290 /* do nothing */
2291 break;
2292 }
2293
2294 pm_runtime_mark_last_busy(dev);
2295
2296 return 0;
2297}
2298
2299static int dwc3_runtime_idle(struct device *dev)
2300{
2301 struct dwc3 *dwc = dev_get_drvdata(dev);
2302
689bf72c
MG		 2303 switch (dwc->current_dr_role) {
2304 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 2305 if (dwc3_runtime_checks(dwc))
2306 return -EBUSY;
2307 break;
689bf72c 2308 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 2309 default:
2310 /* do nothing */
2311 break;
2312 }
2313
2314 pm_runtime_mark_last_busy(dev);
2315 pm_runtime_autosuspend(dev);
2316
2317 return 0;
2318}
2319#endif /* CONFIG_PM */
2320
2321#ifdef CONFIG_PM_SLEEP
2322static int dwc3_suspend(struct device *dev)
2323{
2324 struct dwc3 *dwc = dev_get_drvdata(dev);
2325 int ret;
2326
c4a5153e 2327 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
fc8bb91b
FB		 2328 if (ret)
2329 return ret;
2330
2331 pinctrl_pm_select_sleep_state(dev);
2332
2333 return 0;
2334}
2335
2336static int dwc3_resume(struct device *dev)
2337{
2338 struct dwc3 *dwc = dev_get_drvdata(dev);
2339 int ret;
2340
2341 pinctrl_pm_select_default_state(dev);
2342
c4a5153e 2343 ret = dwc3_resume_common(dwc, PMSG_RESUME);
fc8bb91b
FB		 2344 if (ret)
2345 return ret;
2346
7415f17c
FB		 2347 pm_runtime_disable(dev);
2348 pm_runtime_set_active(dev);
2349 pm_runtime_enable(dev);
2350
2351 return 0;
2352}
f580170f
YC		 2353
2354static void dwc3_complete(struct device *dev)
2355{
2356 struct dwc3 *dwc = dev_get_drvdata(dev);
2357 u32 reg;
2358
2359 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2360 dwc->dis_split_quirk) {
2361 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2362 reg |= DWC3_GUCTL3_SPLITDISABLE;
2363 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2364 }
2365}
2366#else
2367#define dwc3_complete NULL
7f370ed0 2368#endif /* CONFIG_PM_SLEEP */
7415f17c
FB		 2369
2370static const struct dev_pm_ops dwc3_dev_pm_ops = {
7415f17c 2371 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
f580170f 2372 .complete = dwc3_complete,
fc8bb91b
FB		 2373 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2374 dwc3_runtime_idle)
7415f17c
FB		 2375};
2376
5088b6f5
KVA		 2377#ifdef CONFIG_OF
2378static const struct of_device_id of_dwc3_match[] = {
22a5aa17
FB		 2379 {
2380 .compatible = "snps,dwc3"
2381 },
5088b6f5
KVA		 2382 {
2383 .compatible = "synopsys,dwc3"
2384 },
2385 { },
2386};
2387MODULE_DEVICE_TABLE(of, of_dwc3_match);
2388#endif
2389
404905a6
HK		 2390#ifdef CONFIG_ACPI
2391
2392#define ACPI_ID_INTEL_BSW "808622B7"
2393
2394static const struct acpi_device_id dwc3_acpi_match[] = {
2395 { ACPI_ID_INTEL_BSW, 0 },
2396 { },
2397};
2398MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2399#endif
2400
72246da4
FB		 2401static struct platform_driver dwc3_driver = {
2402 .probe = dwc3_probe,
01765687 2403 .remove_new = dwc3_remove,
72246da4
FB		 2404 .driver = {
2405 .name = "dwc3",
5088b6f5 2406 .of_match_table = of_match_ptr(of_dwc3_match),
404905a6 2407 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
7f370ed0 2408 .pm = &dwc3_dev_pm_ops,
72246da4 2409 },
72246da4
FB		 2410};
2411
b1116dcc
TK		 2412module_platform_driver(dwc3_driver);
2413
7ae4fc4d 2414MODULE_ALIAS("platform:dwc3");
72246da4 2415MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
5945f789 2416MODULE_LICENSE("GPL v2");
72246da4 2417MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux 6.x block layer and io_uring tree(s)