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usb: cdns3: mark local functions static
[linux-block.git] / drivers / usb / dwc3 / core.c
CommitLineData
5fd54ace 1// SPDX-License-Identifier: GPL-2.0
72246da4
FB		 2/**
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
72246da4
FB		 9 */
10
fe8abf33 11#include <linux/clk.h>
fa0ea13e 12#include <linux/version.h>
a72e658b 13#include <linux/module.h>
72246da4
FB		 14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/io.h>
22#include <linux/list.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
457e84b6 25#include <linux/of.h>
404905a6 26#include <linux/acpi.h>
6344475f 27#include <linux/pinctrl/consumer.h>
fe8abf33 28#include <linux/reset.h>
72246da4
FB		 29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
f7e846f0 32#include <linux/usb/of.h>
a45c82b8 33#include <linux/usb/otg.h>
72246da4
FB		 34
35#include "core.h"
36#include "gadget.h"
37#include "io.h"
38
39#include "debug.h"
40
fc8bb91b 41#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
8300dd23 42
9d6173e1
TN		 43/**
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
46 */
47static int dwc3_get_dr_mode(struct dwc3 *dwc)
48{
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
51 unsigned int hw_mode;
52
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
55
56 mode = dwc->dr_mode;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
58
59 switch (hw_mode) {
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
62 dev_err(dev,
63 "Controller does not support host mode.\n");
64 return -EINVAL;
65 }
66 mode = USB_DR_MODE_PERIPHERAL;
67 break;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
70 dev_err(dev,
71 "Controller does not support device mode.\n");
72 return -EINVAL;
73 }
74 mode = USB_DR_MODE_HOST;
75 break;
76 default:
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
a7700468
TN		 81
82 /*
89a9cc47
TN		 83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
84 * mode. If the controller supports DRD but the dr_mode is not
85 * specified or set to OTG, then set the mode to peripheral.
a7700468 86 */
89a9cc47
TN		 87 if (mode == USB_DR_MODE_OTG &&
88 dwc->revision >= DWC3_REVISION_330A)
a7700468 89 mode = USB_DR_MODE_PERIPHERAL;
9d6173e1
TN		 90 }
91
92 if (mode != dwc->dr_mode) {
93 dev_warn(dev,
94 "Configuration mismatch. dr_mode forced to %s\n",
95 mode == USB_DR_MODE_HOST ? "host" : "gadget");
96
97 dwc->dr_mode = mode;
98 }
99
100 return 0;
101}
102
f09cc79b 103void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
3140e8cb
SAS		 104{
105 u32 reg;
106
107 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
108 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
109 reg |= DWC3_GCTL_PRTCAPDIR(mode);
110 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
c4a5153e
MG		 111
112 dwc->current_dr_role = mode;
41ce1456
RQ		 113}
114
115static void __dwc3_set_mode(struct work_struct *work)
116{
117 struct dwc3 *dwc = work_to_dwc(work);
118 unsigned long flags;
119 int ret;
120
f09cc79b 121 if (dwc->dr_mode != USB_DR_MODE_OTG)
41ce1456
RQ		 122 return;
123
f09cc79b
RQ		 124 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
125 dwc3_otg_update(dwc, 0);
126
41ce1456
RQ		 127 if (!dwc->desired_dr_role)
128 return;
129
130 if (dwc->desired_dr_role == dwc->current_dr_role)
131 return;
132
f09cc79b 133 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
41ce1456
RQ		 134 return;
135
136 switch (dwc->current_dr_role) {
137 case DWC3_GCTL_PRTCAP_HOST:
138 dwc3_host_exit(dwc);
139 break;
140 case DWC3_GCTL_PRTCAP_DEVICE:
141 dwc3_gadget_exit(dwc);
142 dwc3_event_buffers_cleanup(dwc);
143 break;
f09cc79b
RQ		 144 case DWC3_GCTL_PRTCAP_OTG:
145 dwc3_otg_exit(dwc);
146 spin_lock_irqsave(&dwc->lock, flags);
147 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
148 spin_unlock_irqrestore(&dwc->lock, flags);
149 dwc3_otg_update(dwc, 1);
150 break;
41ce1456
RQ		 151 default:
152 break;
153 }
154
155 spin_lock_irqsave(&dwc->lock, flags);
156
157 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
6b3261a2 158
41ce1456
RQ		 159 spin_unlock_irqrestore(&dwc->lock, flags);
160
161 switch (dwc->desired_dr_role) {
162 case DWC3_GCTL_PRTCAP_HOST:
163 ret = dwc3_host_init(dwc);
958d1a4c 164 if (ret) {
41ce1456 165 dev_err(dwc->dev, "failed to initialize host\n");
958d1a4c
FB		 166 } else {
167 if (dwc->usb2_phy)
168 otg_set_vbus(dwc->usb2_phy->otg, true);
644cbbc3
MG		 169 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
170 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
958d1a4c 171 }
41ce1456
RQ		 172 break;
173 case DWC3_GCTL_PRTCAP_DEVICE:
174 dwc3_event_buffers_setup(dwc);
958d1a4c
FB		 175
176 if (dwc->usb2_phy)
177 otg_set_vbus(dwc->usb2_phy->otg, false);
644cbbc3
MG		 178 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
179 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
958d1a4c 180
41ce1456
RQ		 181 ret = dwc3_gadget_init(dwc);
182 if (ret)
183 dev_err(dwc->dev, "failed to initialize peripheral\n");
184 break;
f09cc79b
RQ		 185 case DWC3_GCTL_PRTCAP_OTG:
186 dwc3_otg_init(dwc);
187 dwc3_otg_update(dwc, 0);
188 break;
41ce1456
RQ		 189 default:
190 break;
191 }
f09cc79b 192
41ce1456
RQ		 193}
194
195void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
196{
197 unsigned long flags;
198
199 spin_lock_irqsave(&dwc->lock, flags);
200 dwc->desired_dr_role = mode;
201 spin_unlock_irqrestore(&dwc->lock, flags);
202
084a804e 203 queue_work(system_freezable_wq, &dwc->drd_work);
3140e8cb 204}
8300dd23 205
cf6d867d
FB		 206u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
207{
208 struct dwc3 *dwc = dep->dwc;
209 u32 reg;
210
211 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
212 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
213 DWC3_GDBGFIFOSPACE_TYPE(type));
214
215 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
216
217 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
218}
219
72246da4
FB		 220/**
221 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
222 * @dwc: pointer to our context structure
223 */
57303488 224static int dwc3_core_soft_reset(struct dwc3 *dwc)
72246da4
FB		 225{
226 u32 reg;
f59dcab1 227 int retries = 1000;
57303488 228 int ret;
72246da4 229
51e1e7bc
FB		 230 usb_phy_init(dwc->usb2_phy);
231 usb_phy_init(dwc->usb3_phy);
57303488
KVA		 232 ret = phy_init(dwc->usb2_generic_phy);
233 if (ret < 0)
234 return ret;
235
236 ret = phy_init(dwc->usb3_generic_phy);
237 if (ret < 0) {
238 phy_exit(dwc->usb2_generic_phy);
239 return ret;
240 }
72246da4 241
f59dcab1
FB		 242 /*
243 * We're resetting only the device side because, if we're in host mode,
244 * XHCI driver will reset the host block. If dwc3 was configured for
245 * host-only mode, then we can return early.
246 */
c4a5153e 247 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
f59dcab1 248 return 0;
72246da4 249
f59dcab1
FB		 250 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
251 reg |= DWC3_DCTL_CSFTRST;
252 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 253
4749e0e6
TN		 254 /*
255 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
256 * is cleared only after all the clocks are synchronized. This can
257 * take a little more than 50ms. Set the polling rate at 20ms
258 * for 10 times instead.
259 */
260 if (dwc3_is_usb31(dwc) && dwc->revision >= DWC3_USB31_REVISION_190A)
261 retries = 10;
262
f59dcab1
FB		 263 do {
264 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
265 if (!(reg & DWC3_DCTL_CSFTRST))
fab38333 266 goto done;
45627ac6 267
4749e0e6
TN		 268 if (dwc3_is_usb31(dwc) &&
269 dwc->revision >= DWC3_USB31_REVISION_190A)
270 msleep(20);
271 else
272 udelay(1);
f59dcab1 273 } while (--retries);
57303488 274
00b42170
BN		 275 phy_exit(dwc->usb3_generic_phy);
276 phy_exit(dwc->usb2_generic_phy);
277
f59dcab1 278 return -ETIMEDOUT;
fab38333
TN		 279
280done:
281 /*
4749e0e6
TN		 282 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
283 * is cleared, we must wait at least 50ms before accessing the PHY
284 * domain (synchronization delay).
fab38333 285 */
4749e0e6 286 if (dwc3_is_usb31(dwc) && dwc->revision <= DWC3_USB31_REVISION_180A)
fab38333
TN		 287 msleep(50);
288
289 return 0;
72246da4
FB		 290}
291
db2be4e9
NB		 292/*
293 * dwc3_frame_length_adjustment - Adjusts frame length if required
294 * @dwc3: Pointer to our controller context structure
db2be4e9 295 */
bcdb3272 296static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
db2be4e9
NB		 297{
298 u32 reg;
299 u32 dft;
300
301 if (dwc->revision < DWC3_REVISION_250A)
302 return;
303
bcdb3272 304 if (dwc->fladj == 0)
db2be4e9
NB		 305 return;
306
307 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
308 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
a7d9874c 309 if (dft != dwc->fladj) {
db2be4e9 310 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
bcdb3272 311 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
db2be4e9
NB		 312 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
313 }
314}
315
72246da4
FB		 316/**
317 * dwc3_free_one_event_buffer - Frees one event buffer
318 * @dwc: Pointer to our controller context structure
319 * @evt: Pointer to event buffer to be freed
320 */
321static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
322 struct dwc3_event_buffer *evt)
323{
d64ff406 324 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
72246da4
FB		 325}
326
327/**
1d046793 328 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
72246da4
FB		 329 * @dwc: Pointer to our controller context structure
330 * @length: size of the event buffer
331 *
1d046793 332 * Returns a pointer to the allocated event buffer structure on success
72246da4
FB		 333 * otherwise ERR_PTR(errno).
334 */
67d0b500
FB		 335static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
336 unsigned length)
72246da4
FB		 337{
338 struct dwc3_event_buffer *evt;
339
380f0d28 340 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
72246da4
FB		 341 if (!evt)
342 return ERR_PTR(-ENOMEM);
343
344 evt->dwc = dwc;
345 evt->length = length;
d9fa4c63
JY		 346 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
347 if (!evt->cache)
348 return ERR_PTR(-ENOMEM);
349
d64ff406 350 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
72246da4 351 &evt->dma, GFP_KERNEL);
e32672f0 352 if (!evt->buf)
72246da4 353 return ERR_PTR(-ENOMEM);
72246da4
FB		 354
355 return evt;
356}
357
358/**
359 * dwc3_free_event_buffers - frees all allocated event buffers
360 * @dwc: Pointer to our controller context structure
361 */
362static void dwc3_free_event_buffers(struct dwc3 *dwc)
363{
364 struct dwc3_event_buffer *evt;
72246da4 365
696c8b12 366 evt = dwc->ev_buf;
660e9bde
FB		 367 if (evt)
368 dwc3_free_one_event_buffer(dwc, evt);
72246da4
FB		 369}
370
371/**
372 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
1d046793 373 * @dwc: pointer to our controller context structure
72246da4
FB		 374 * @length: size of event buffer
375 *
1d046793 376 * Returns 0 on success otherwise negative errno. In the error case, dwc
72246da4
FB		 377 * may contain some buffers allocated but not all which were requested.
378 */
41ac7b3a 379static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
72246da4 380{
660e9bde 381 struct dwc3_event_buffer *evt;
72246da4 382
660e9bde
FB		 383 evt = dwc3_alloc_one_event_buffer(dwc, length);
384 if (IS_ERR(evt)) {
385 dev_err(dwc->dev, "can't allocate event buffer\n");
386 return PTR_ERR(evt);
72246da4 387 }
696c8b12 388 dwc->ev_buf = evt;
72246da4
FB		 389
390 return 0;
391}
392
393/**
394 * dwc3_event_buffers_setup - setup our allocated event buffers
1d046793 395 * @dwc: pointer to our controller context structure
72246da4
FB		 396 *
397 * Returns 0 on success otherwise negative errno.
398 */
f09cc79b 399int dwc3_event_buffers_setup(struct dwc3 *dwc)
72246da4
FB		 400{
401 struct dwc3_event_buffer *evt;
72246da4 402
696c8b12 403 evt = dwc->ev_buf;
660e9bde 404 evt->lpos = 0;
660e9bde
FB		 405 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
406 lower_32_bits(evt->dma));
407 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
408 upper_32_bits(evt->dma));
409 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
410 DWC3_GEVNTSIZ_SIZE(evt->length));
411 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 412
413 return 0;
414}
415
f09cc79b 416void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
72246da4
FB		 417{
418 struct dwc3_event_buffer *evt;
72246da4 419
696c8b12 420 evt = dwc->ev_buf;
7acd85e0 421
660e9bde 422 evt->lpos = 0;
7acd85e0 423
660e9bde
FB		 424 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
425 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
426 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
427 | DWC3_GEVNTSIZ_SIZE(0));
428 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 429}
430
0ffcaf37
FB		 431static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
432{
433 if (!dwc->has_hibernation)
434 return 0;
435
436 if (!dwc->nr_scratch)
437 return 0;
438
439 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
440 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
441 if (!dwc->scratchbuf)
442 return -ENOMEM;
443
444 return 0;
445}
446
447static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
448{
449 dma_addr_t scratch_addr;
450 u32 param;
451 int ret;
452
453 if (!dwc->has_hibernation)
454 return 0;
455
456 if (!dwc->nr_scratch)
457 return 0;
458
459 /* should never fall here */
460 if (!WARN_ON(dwc->scratchbuf))
461 return 0;
462
d64ff406 463 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
0ffcaf37
FB		 464 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
465 DMA_BIDIRECTIONAL);
d64ff406
AB		 466 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
467 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
0ffcaf37
FB		 468 ret = -EFAULT;
469 goto err0;
470 }
471
472 dwc->scratch_addr = scratch_addr;
473
474 param = lower_32_bits(scratch_addr);
475
476 ret = dwc3_send_gadget_generic_command(dwc,
477 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
478 if (ret < 0)
479 goto err1;
480
481 param = upper_32_bits(scratch_addr);
482
483 ret = dwc3_send_gadget_generic_command(dwc,
484 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
485 if (ret < 0)
486 goto err1;
487
488 return 0;
489
490err1:
d64ff406 491 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
0ffcaf37
FB		 492 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
493
494err0:
495 return ret;
496}
497
498static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
499{
500 if (!dwc->has_hibernation)
501 return;
502
503 if (!dwc->nr_scratch)
504 return;
505
506 /* should never fall here */
507 if (!WARN_ON(dwc->scratchbuf))
508 return;
509
d64ff406 510 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
0ffcaf37
FB		 511 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
512 kfree(dwc->scratchbuf);
513}
514
789451f6
FB		 515static void dwc3_core_num_eps(struct dwc3 *dwc)
516{
517 struct dwc3_hwparams *parms = &dwc->hwparams;
518
47d3946e 519 dwc->num_eps = DWC3_NUM_EPS(parms);
789451f6
FB		 520}
521
41ac7b3a 522static void dwc3_cache_hwparams(struct dwc3 *dwc)
26ceca97
FB		 523{
524 struct dwc3_hwparams *parms = &dwc->hwparams;
525
526 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
527 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
528 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
529 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
530 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
531 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
532 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
533 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
534 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
535}
536
98112041
RQ		 537static int dwc3_core_ulpi_init(struct dwc3 *dwc)
538{
539 int intf;
540 int ret = 0;
541
542 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
543
544 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
545 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
546 dwc->hsphy_interface &&
547 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
548 ret = dwc3_ulpi_init(dwc);
549
550 return ret;
551}
552
b5a65c40
HR		 553/**
554 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
555 * @dwc: Pointer to our controller context structure
88bc9d19
HK		 556 *
557 * Returns 0 on success. The USB PHY interfaces are configured but not
558 * initialized. The PHY interfaces and the PHYs get initialized together with
559 * the core in dwc3_core_init.
b5a65c40 560 */
88bc9d19 561static int dwc3_phy_setup(struct dwc3 *dwc)
b5a65c40 562{
9ba3aca8 563 unsigned int hw_mode;
b5a65c40
HR		 564 u32 reg;
565
9ba3aca8
TN		 566 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
567
b5a65c40
HR		 568 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
569
1966b865
FB		 570 /*
571 * Make sure UX_EXIT_PX is cleared as that causes issues with some
572 * PHYs. Also, this bit is not supposed to be used in normal operation.
573 */
574 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
575
2164a476
HR		 576 /*
577 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
578 * to '0' during coreConsultant configuration. So default value
579 * will be '0' when the core is reset. Application needs to set it
580 * to '1' after the core initialization is completed.
581 */
582 if (dwc->revision > DWC3_REVISION_194A)
583 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
584
9ba3aca8
TN		 585 /*
586 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
587 * power-on reset, and it can be set after core initialization, which is
588 * after device soft-reset during initialization.
589 */
590 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
591 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
592
b5a65c40
HR		 593 if (dwc->u2ss_inp3_quirk)
594 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
595
e58dd357
RB		 596 if (dwc->dis_rxdet_inp3_quirk)
597 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
598
df31f5b3
HR		 599 if (dwc->req_p1p2p3_quirk)
600 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
601
a2a1d0f5
HR		 602 if (dwc->del_p1p2p3_quirk)
603 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
604
41c06ffd
HR		 605 if (dwc->del_phy_power_chg_quirk)
606 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
607
fb67afca
HR		 608 if (dwc->lfps_filter_quirk)
609 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
610
14f4ac53
HR		 611 if (dwc->rx_detect_poll_quirk)
612 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
613
6b6a0c9a
HR		 614 if (dwc->tx_de_emphasis_quirk)
615 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
616
cd72f890 617 if (dwc->dis_u3_susphy_quirk)
59acfa20
HR		 618 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
619
00fe081d
WW		 620 if (dwc->dis_del_phy_power_chg_quirk)
621 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
622
b5a65c40
HR		 623 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
624
2164a476
HR		 625 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
626
3e10a2ce
HK		 627 /* Select the HS PHY interface */
628 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
629 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
43cacb03
FB		 630 if (dwc->hsphy_interface &&
631 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
3e10a2ce 632 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 633 break;
43cacb03
FB		 634 } else if (dwc->hsphy_interface &&
635 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
3e10a2ce 636 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 637 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
3e10a2ce 638 } else {
88bc9d19
HK		 639 /* Relying on default value. */
640 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
641 break;
3e10a2ce
HK		 642 }
643 /* FALLTHROUGH */
88bc9d19 644 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
88bc9d19 645 /* FALLTHROUGH */
3e10a2ce
HK		 646 default:
647 break;
648 }
649
32f2ed86
WW		 650 switch (dwc->hsphy_mode) {
651 case USBPHY_INTERFACE_MODE_UTMI:
652 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
653 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
654 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
655 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
656 break;
657 case USBPHY_INTERFACE_MODE_UTMIW:
658 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
659 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
660 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
661 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
662 break;
663 default:
664 break;
665 }
666
2164a476
HR		 667 /*
668 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
669 * '0' during coreConsultant configuration. So default value will
670 * be '0' when the core is reset. Application needs to set it to
671 * '1' after the core initialization is completed.
672 */
673 if (dwc->revision > DWC3_REVISION_194A)
674 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
675
9ba3aca8
TN		 676 /*
677 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
678 * power-on reset, and it can be set after core initialization, which is
679 * after device soft-reset during initialization.
680 */
681 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
682 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
683
cd72f890 684 if (dwc->dis_u2_susphy_quirk)
0effe0a3
HR		 685 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
686
ec791d14
JY		 687 if (dwc->dis_enblslpm_quirk)
688 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
eafeacf1
TN		 689 else
690 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
ec791d14 691
16199f33
WW		 692 if (dwc->dis_u2_freeclk_exists_quirk)
693 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
694
2164a476 695 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
88bc9d19
HK		 696
697 return 0;
b5a65c40
HR		 698}
699
c499ff71
FB		 700static void dwc3_core_exit(struct dwc3 *dwc)
701{
702 dwc3_event_buffers_cleanup(dwc);
703
704 usb_phy_shutdown(dwc->usb2_phy);
705 usb_phy_shutdown(dwc->usb3_phy);
706 phy_exit(dwc->usb2_generic_phy);
707 phy_exit(dwc->usb3_generic_phy);
708
709 usb_phy_set_suspend(dwc->usb2_phy, 1);
710 usb_phy_set_suspend(dwc->usb3_phy, 1);
711 phy_power_off(dwc->usb2_generic_phy);
712 phy_power_off(dwc->usb3_generic_phy);
240b65dc 713 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
fe8abf33 714 reset_control_assert(dwc->reset);
c499ff71
FB		 715}
716
0759956f 717static bool dwc3_core_is_valid(struct dwc3 *dwc)
72246da4 718{
0759956f 719 u32 reg;
72246da4 720
7650bd74 721 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
0759956f 722
7650bd74 723 /* This should read as U3 followed by revision number */
690fb371
JY		 724 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
725 /* Detected DWC_usb3 IP */
726 dwc->revision = reg;
727 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
728 /* Detected DWC_usb31 IP */
729 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
730 dwc->revision |= DWC3_REVISION_IS_DWC31;
475d8e01 731 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
690fb371 732 } else {
0759956f 733 return false;
7650bd74 734 }
7650bd74 735
0759956f
FB		 736 return true;
737}
58a0f23f 738
941f918e 739static void dwc3_core_setup_global_control(struct dwc3 *dwc)
0759956f 740{
941f918e
FB		 741 u32 hwparams4 = dwc->hwparams.hwparams4;
742 u32 reg;
c499ff71 743
4878a028 744 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
3e87c42a 745 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
4878a028 746
164d7731 747 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
4878a028 748 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
32a4a135
FB		 749 /**
750 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
751 * issue which would cause xHCI compliance tests to fail.
752 *
753 * Because of that we cannot enable clock gating on such
754 * configurations.
755 *
756 * Refers to:
757 *
758 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
759 * SOF/ITP Mode Used
760 */
761 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
762 dwc->dr_mode == USB_DR_MODE_OTG) &&
763 (dwc->revision >= DWC3_REVISION_210A &&
764 dwc->revision <= DWC3_REVISION_250A))
765 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
766 else
767 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
4878a028 768 break;
0ffcaf37
FB		 769 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
770 /* enable hibernation here */
771 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
2eac3992
HR		 772
773 /*
774 * REVISIT Enabling this bit so that host-mode hibernation
775 * will work. Device-mode hibernation is not yet implemented.
776 */
777 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
0ffcaf37 778 break;
4878a028 779 default:
5eb30ced
FB		 780 /* nothing */
781 break;
4878a028
SAS		 782 }
783
946bd579
HR		 784 /* check if current dwc3 is on simulation board */
785 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
6af19fd1 786 dev_info(dwc->dev, "Running with FPGA optimizations\n");
946bd579
HR		 787 dwc->is_fpga = true;
788 }
789
3b81221a
HR		 790 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
791 "disable_scramble cannot be used on non-FPGA builds\n");
792
793 if (dwc->disable_scramble_quirk && dwc->is_fpga)
794 reg |= DWC3_GCTL_DISSCRAMBLE;
795 else
796 reg &= ~DWC3_GCTL_DISSCRAMBLE;
797
9a5b2f31
HR		 798 if (dwc->u2exit_lfps_quirk)
799 reg |= DWC3_GCTL_U2EXIT_LFPS;
800
4878a028
SAS		 801 /*
802 * WORKAROUND: DWC3 revisions <1.90a have a bug
1d046793 803 * where the device can fail to connect at SuperSpeed
4878a028 804 * and falls back to high-speed mode which causes
1d046793 805 * the device to enter a Connect/Disconnect loop
4878a028
SAS		 806 */
807 if (dwc->revision < DWC3_REVISION_190A)
808 reg |= DWC3_GCTL_U2RSTECN;
809
810 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
941f918e
FB		 811}
812
f54edb53 813static int dwc3_core_get_phy(struct dwc3 *dwc);
98112041 814static int dwc3_core_ulpi_init(struct dwc3 *dwc);
f54edb53 815
d9612c2f
PM		 816/* set global incr burst type configuration registers */
817static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
818{
819 struct device *dev = dwc->dev;
820 /* incrx_mode : for INCR burst type. */
821 bool incrx_mode;
822 /* incrx_size : for size of INCRX burst. */
823 u32 incrx_size;
824 u32 *vals;
825 u32 cfg;
826 int ntype;
827 int ret;
828 int i;
829
830 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
831
832 /*
833 * Handle property "snps,incr-burst-type-adjustment".
834 * Get the number of value from this property:
835 * result <= 0, means this property is not supported.
836 * result = 1, means INCRx burst mode supported.
837 * result > 1, means undefined length burst mode supported.
838 */
a6e5e679 839 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
d9612c2f
PM		 840 if (ntype <= 0)
841 return;
842
843 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
844 if (!vals) {
845 dev_err(dev, "Error to get memory\n");
846 return;
847 }
848
849 /* Get INCR burst type, and parse it */
850 ret = device_property_read_u32_array(dev,
851 "snps,incr-burst-type-adjustment", vals, ntype);
852 if (ret) {
75ecb9dd 853 kfree(vals);
d9612c2f
PM		 854 dev_err(dev, "Error to get property\n");
855 return;
856 }
857
858 incrx_size = *vals;
859
860 if (ntype > 1) {
861 /* INCRX (undefined length) burst mode */
862 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
863 for (i = 1; i < ntype; i++) {
864 if (vals[i] > incrx_size)
865 incrx_size = vals[i];
866 }
867 } else {
868 /* INCRX burst mode */
869 incrx_mode = INCRX_BURST_MODE;
870 }
871
75ecb9dd
AS		 872 kfree(vals);
873
d9612c2f
PM		 874 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
875 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
876 if (incrx_mode)
877 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
878 switch (incrx_size) {
879 case 256:
880 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
881 break;
882 case 128:
883 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
884 break;
885 case 64:
886 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
887 break;
888 case 32:
889 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
890 break;
891 case 16:
892 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
893 break;
894 case 8:
895 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
896 break;
897 case 4:
898 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
899 break;
900 case 1:
901 break;
902 default:
903 dev_err(dev, "Invalid property\n");
904 break;
905 }
906
907 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
908}
909
941f918e
FB		 910/**
911 * dwc3_core_init - Low-level initialization of DWC3 Core
912 * @dwc: Pointer to our controller context structure
913 *
914 * Returns 0 on success otherwise negative errno.
915 */
916static int dwc3_core_init(struct dwc3 *dwc)
917{
9ba3aca8 918 unsigned int hw_mode;
941f918e
FB		 919 u32 reg;
920 int ret;
921
9ba3aca8
TN		 922 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
923
941f918e
FB		 924 /*
925 * Write Linux Version Code to our GUID register so it's easy to figure
926 * out which kernel version a bug was found.
927 */
928 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
929
930 /* Handle USB2.0-only core configuration */
931 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
932 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
933 if (dwc->maximum_speed == USB_SPEED_SUPER)
934 dwc->maximum_speed = USB_SPEED_HIGH;
935 }
936
98112041 937 ret = dwc3_phy_setup(dwc);
941f918e
FB		 938 if (ret)
939 goto err0;
4878a028 940
98112041
RQ		 941 if (!dwc->ulpi_ready) {
942 ret = dwc3_core_ulpi_init(dwc);
943 if (ret)
944 goto err0;
945 dwc->ulpi_ready = true;
946 }
4878a028 947
98112041
RQ		 948 if (!dwc->phys_ready) {
949 ret = dwc3_core_get_phy(dwc);
950 if (ret)
951 goto err0a;
952 dwc->phys_ready = true;
953 }
954
955 ret = dwc3_core_soft_reset(dwc);
f54edb53 956 if (ret)
98112041 957 goto err0a;
f54edb53 958
9ba3aca8
TN		 959 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
960 dwc->revision > DWC3_REVISION_194A) {
961 if (!dwc->dis_u3_susphy_quirk) {
962 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
963 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
964 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
965 }
966
967 if (!dwc->dis_u2_susphy_quirk) {
968 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
969 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
970 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
971 }
972 }
973
941f918e 974 dwc3_core_setup_global_control(dwc);
c499ff71 975 dwc3_core_num_eps(dwc);
0ffcaf37
FB		 976
977 ret = dwc3_setup_scratch_buffers(dwc);
978 if (ret)
c499ff71
FB		 979 goto err1;
980
981 /* Adjust Frame Length */
982 dwc3_frame_length_adjustment(dwc);
983
d9612c2f
PM		 984 dwc3_set_incr_burst_type(dwc);
985
c499ff71
FB		 986 usb_phy_set_suspend(dwc->usb2_phy, 0);
987 usb_phy_set_suspend(dwc->usb3_phy, 0);
988 ret = phy_power_on(dwc->usb2_generic_phy);
989 if (ret < 0)
0ffcaf37
FB		 990 goto err2;
991
c499ff71
FB		 992 ret = phy_power_on(dwc->usb3_generic_phy);
993 if (ret < 0)
994 goto err3;
995
996 ret = dwc3_event_buffers_setup(dwc);
997 if (ret) {
998 dev_err(dwc->dev, "failed to setup event buffers\n");
999 goto err4;
1000 }
1001
06281d46
JY		 1002 /*
1003 * ENDXFER polling is available on version 3.10a and later of
1004 * the DWC_usb3 controller. It is NOT available in the
1005 * DWC_usb31 controller.
1006 */
1007 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
1008 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1009 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1010 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1011 }
1012
65db7a0c 1013 if (dwc->revision >= DWC3_REVISION_250A) {
0bb39ca1 1014 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
65db7a0c
WW		 1015
1016 /*
1017 * Enable hardware control of sending remote wakeup
1018 * in HS when the device is in the L1 state.
1019 */
1020 if (dwc->revision >= DWC3_REVISION_290A)
1021 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1022
1023 if (dwc->dis_tx_ipgap_linecheck_quirk)
1024 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1025
7ba6b09f
NA		 1026 if (dwc->parkmode_disable_ss_quirk)
1027 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1028
0bb39ca1
JY		 1029 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1030 }
1031
b138e23d
AKV		 1032 if (dwc->dr_mode == USB_DR_MODE_HOST ||
1033 dwc->dr_mode == USB_DR_MODE_OTG) {
1034 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1035
1036 /*
1037 * Enable Auto retry Feature to make the controller operating in
1038 * Host mode on seeing transaction errors(CRC errors or internal
1039 * overrun scenerios) on IN transfers to reply to the device
1040 * with a non-terminating retry ACK (i.e, an ACK transcation
1041 * packet with Retry=1 & Nump != 0)
1042 */
1043 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1044
1045 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1046 }
1047
938a5ad1
TN		 1048 /*
1049 * Must config both number of packets and max burst settings to enable
1050 * RX and/or TX threshold.
1051 */
1052 if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
1053 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1054 u8 rx_maxburst = dwc->rx_max_burst_prd;
1055 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1056 u8 tx_maxburst = dwc->tx_max_burst_prd;
1057
1058 if (rx_thr_num && rx_maxburst) {
1059 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1060 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1061
1062 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1063 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1064
1065 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1066 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1067
1068 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1069 }
1070
1071 if (tx_thr_num && tx_maxburst) {
1072 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1073 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1074
1075 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1076 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1077
1078 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1079 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1080
1081 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1082 }
1083 }
1084
72246da4
FB		 1085 return 0;
1086
c499ff71 1087err4:
9b9d7cdd 1088 phy_power_off(dwc->usb3_generic_phy);
c499ff71
FB		 1089
1090err3:
9b9d7cdd 1091 phy_power_off(dwc->usb2_generic_phy);
c499ff71 1092
0ffcaf37 1093err2:
c499ff71
FB		 1094 usb_phy_set_suspend(dwc->usb2_phy, 1);
1095 usb_phy_set_suspend(dwc->usb3_phy, 1);
0ffcaf37
FB		 1096
1097err1:
1098 usb_phy_shutdown(dwc->usb2_phy);
1099 usb_phy_shutdown(dwc->usb3_phy);
57303488
KVA		 1100 phy_exit(dwc->usb2_generic_phy);
1101 phy_exit(dwc->usb3_generic_phy);
0ffcaf37 1102
98112041
RQ		 1103err0a:
1104 dwc3_ulpi_exit(dwc);
1105
72246da4
FB		 1106err0:
1107 return ret;
1108}
1109
3c9f94ac 1110static int dwc3_core_get_phy(struct dwc3 *dwc)
72246da4 1111{
3c9f94ac 1112 struct device *dev = dwc->dev;
941ea361 1113 struct device_node *node = dev->of_node;
3c9f94ac 1114 int ret;
72246da4 1115
5088b6f5
KVA		 1116 if (node) {
1117 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1118 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
bb674907
FB		 1119 } else {
1120 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1121 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
5088b6f5
KVA		 1122 }
1123
d105e7f8
FB		 1124 if (IS_ERR(dwc->usb2_phy)) {
1125 ret = PTR_ERR(dwc->usb2_phy);
122f06e6
KVA		 1126 if (ret == -ENXIO || ret == -ENODEV) {
1127 dwc->usb2_phy = NULL;
1128 } else if (ret == -EPROBE_DEFER) {
d105e7f8 1129 return ret;
122f06e6
KVA		 1130 } else {
1131 dev_err(dev, "no usb2 phy configured\n");
1132 return ret;
1133 }
51e1e7bc
FB		 1134 }
1135
d105e7f8 1136 if (IS_ERR(dwc->usb3_phy)) {
315955d7 1137 ret = PTR_ERR(dwc->usb3_phy);
122f06e6
KVA		 1138 if (ret == -ENXIO || ret == -ENODEV) {
1139 dwc->usb3_phy = NULL;
1140 } else if (ret == -EPROBE_DEFER) {
d105e7f8 1141 return ret;
122f06e6
KVA		 1142 } else {
1143 dev_err(dev, "no usb3 phy configured\n");
1144 return ret;
1145 }
51e1e7bc
FB		 1146 }
1147
57303488
KVA		 1148 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1149 if (IS_ERR(dwc->usb2_generic_phy)) {
1150 ret = PTR_ERR(dwc->usb2_generic_phy);
1151 if (ret == -ENOSYS || ret == -ENODEV) {
1152 dwc->usb2_generic_phy = NULL;
1153 } else if (ret == -EPROBE_DEFER) {
1154 return ret;
1155 } else {
1156 dev_err(dev, "no usb2 phy configured\n");
1157 return ret;
1158 }
1159 }
1160
1161 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1162 if (IS_ERR(dwc->usb3_generic_phy)) {
1163 ret = PTR_ERR(dwc->usb3_generic_phy);
1164 if (ret == -ENOSYS || ret == -ENODEV) {
1165 dwc->usb3_generic_phy = NULL;
1166 } else if (ret == -EPROBE_DEFER) {
1167 return ret;
1168 } else {
1169 dev_err(dev, "no usb3 phy configured\n");
1170 return ret;
1171 }
1172 }
1173
3c9f94ac
FB		 1174 return 0;
1175}
1176
5f94adfe
FB		 1177static int dwc3_core_init_mode(struct dwc3 *dwc)
1178{
1179 struct device *dev = dwc->dev;
1180 int ret;
1181
1182 switch (dwc->dr_mode) {
1183 case USB_DR_MODE_PERIPHERAL:
41ce1456 1184 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
958d1a4c
FB		 1185
1186 if (dwc->usb2_phy)
1187 otg_set_vbus(dwc->usb2_phy->otg, false);
644cbbc3
MG		 1188 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1189 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
958d1a4c 1190
5f94adfe
FB		 1191 ret = dwc3_gadget_init(dwc);
1192 if (ret) {
9522def4
RQ		 1193 if (ret != -EPROBE_DEFER)
1194 dev_err(dev, "failed to initialize gadget\n");
5f94adfe
FB		 1195 return ret;
1196 }
1197 break;
1198 case USB_DR_MODE_HOST:
41ce1456 1199 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
958d1a4c
FB		 1200
1201 if (dwc->usb2_phy)
1202 otg_set_vbus(dwc->usb2_phy->otg, true);
644cbbc3
MG		 1203 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1204 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
958d1a4c 1205
5f94adfe
FB		 1206 ret = dwc3_host_init(dwc);
1207 if (ret) {
9522def4
RQ		 1208 if (ret != -EPROBE_DEFER)
1209 dev_err(dev, "failed to initialize host\n");
5f94adfe
FB		 1210 return ret;
1211 }
1212 break;
1213 case USB_DR_MODE_OTG:
41ce1456 1214 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
9840354f
RQ		 1215 ret = dwc3_drd_init(dwc);
1216 if (ret) {
1217 if (ret != -EPROBE_DEFER)
1218 dev_err(dev, "failed to initialize dual-role\n");
1219 return ret;
1220 }
5f94adfe
FB		 1221 break;
1222 default:
1223 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1224 return -EINVAL;
1225 }
1226
1227 return 0;
1228}
1229
1230static void dwc3_core_exit_mode(struct dwc3 *dwc)
1231{
1232 switch (dwc->dr_mode) {
1233 case USB_DR_MODE_PERIPHERAL:
1234 dwc3_gadget_exit(dwc);
1235 break;
1236 case USB_DR_MODE_HOST:
1237 dwc3_host_exit(dwc);
1238 break;
1239 case USB_DR_MODE_OTG:
9840354f 1240 dwc3_drd_exit(dwc);
5f94adfe
FB		 1241 break;
1242 default:
1243 /* do nothing */
1244 break;
1245 }
09ed259f
BL		 1246
1247 /* de-assert DRVVBUS for HOST and OTG mode */
1248 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
5f94adfe
FB		 1249}
1250
c5ac6116 1251static void dwc3_get_properties(struct dwc3 *dwc)
3c9f94ac 1252{
c5ac6116 1253 struct device *dev = dwc->dev;
80caf7d2 1254 u8 lpm_nyet_threshold;
6b6a0c9a 1255 u8 tx_de_emphasis;
460d098c 1256 u8 hird_threshold;
938a5ad1
TN		 1257 u8 rx_thr_num_pkt_prd;
1258 u8 rx_max_burst_prd;
1259 u8 tx_thr_num_pkt_prd;
1260 u8 tx_max_burst_prd;
3c9f94ac 1261
80caf7d2 1262 /* default to highest possible threshold */
8d791929 1263 lpm_nyet_threshold = 0xf;
80caf7d2 1264
6b6a0c9a
HR		 1265 /* default to -3.5dB de-emphasis */
1266 tx_de_emphasis = 1;
1267
460d098c
HR		 1268 /*
1269 * default to assert utmi_sleep_n and use maximum allowed HIRD
1270 * threshold value of 0b1100
1271 */
1272 hird_threshold = 12;
1273
63863b98 1274 dwc->maximum_speed = usb_get_maximum_speed(dev);
06e7114f 1275 dwc->dr_mode = usb_get_dr_mode(dev);
32f2ed86 1276 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
63863b98 1277
d64ff406
AB		 1278 dwc->sysdev_is_parent = device_property_read_bool(dev,
1279 "linux,sysdev_is_parent");
1280 if (dwc->sysdev_is_parent)
1281 dwc->sysdev = dwc->dev->parent;
1282 else
1283 dwc->sysdev = dwc->dev;
1284
3d128919 1285 dwc->has_lpm_erratum = device_property_read_bool(dev,
80caf7d2 1286 "snps,has-lpm-erratum");
3d128919 1287 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
80caf7d2 1288 &lpm_nyet_threshold);
3d128919 1289 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
460d098c 1290 "snps,is-utmi-l1-suspend");
3d128919 1291 device_property_read_u8(dev, "snps,hird-threshold",
460d098c 1292 &hird_threshold);
d92021f6
TN		 1293 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1294 "snps,dis-start-transfer-quirk");
3d128919 1295 dwc->usb3_lpm_capable = device_property_read_bool(dev,
eac68e8f 1296 "snps,usb3_lpm_capable");
022a0208
TN		 1297 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1298 "snps,usb2-lpm-disable");
938a5ad1
TN		 1299 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1300 &rx_thr_num_pkt_prd);
1301 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1302 &rx_max_burst_prd);
1303 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1304 &tx_thr_num_pkt_prd);
1305 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1306 &tx_max_burst_prd);
3c9f94ac 1307
3d128919 1308 dwc->disable_scramble_quirk = device_property_read_bool(dev,
3b81221a 1309 "snps,disable_scramble_quirk");
3d128919 1310 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
9a5b2f31 1311 "snps,u2exit_lfps_quirk");
3d128919 1312 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
b5a65c40 1313 "snps,u2ss_inp3_quirk");
3d128919 1314 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
df31f5b3 1315 "snps,req_p1p2p3_quirk");
3d128919 1316 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
a2a1d0f5 1317 "snps,del_p1p2p3_quirk");
3d128919 1318 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
41c06ffd 1319 "snps,del_phy_power_chg_quirk");
3d128919 1320 dwc->lfps_filter_quirk = device_property_read_bool(dev,
fb67afca 1321 "snps,lfps_filter_quirk");
3d128919 1322 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
14f4ac53 1323 "snps,rx_detect_poll_quirk");
3d128919 1324 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
59acfa20 1325 "snps,dis_u3_susphy_quirk");
3d128919 1326 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
0effe0a3 1327 "snps,dis_u2_susphy_quirk");
ec791d14
JY		 1328 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1329 "snps,dis_enblslpm_quirk");
729dcffd
AKV		 1330 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1331 "snps,dis-u1-entry-quirk");
1332 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1333 "snps,dis-u2-entry-quirk");
e58dd357
RB		 1334 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1335 "snps,dis_rxdet_inp3_quirk");
16199f33
WW		 1336 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1337 "snps,dis-u2-freeclk-exists-quirk");
00fe081d
WW		 1338 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1339 "snps,dis-del-phy-power-chg-quirk");
65db7a0c
WW		 1340 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1341 "snps,dis-tx-ipgap-linecheck-quirk");
7ba6b09f
NA		 1342 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1343 "snps,parkmode-disable-ss-quirk");
6b6a0c9a 1344
3d128919 1345 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
6b6a0c9a 1346 "snps,tx_de_emphasis_quirk");
3d128919 1347 device_property_read_u8(dev, "snps,tx_de_emphasis",
6b6a0c9a 1348 &tx_de_emphasis);
3d128919
HK		 1349 device_property_read_string(dev, "snps,hsphy_interface",
1350 &dwc->hsphy_interface);
1351 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
bcdb3272 1352 &dwc->fladj);
3d128919 1353
42bf02ec
RQ		 1354 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1355 "snps,dis_metastability_quirk");
1356
80caf7d2 1357 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
6b6a0c9a 1358 dwc->tx_de_emphasis = tx_de_emphasis;
80caf7d2 1359
16fe4f30 1360 dwc->hird_threshold = hird_threshold;
460d098c 1361
938a5ad1
TN		 1362 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1363 dwc->rx_max_burst_prd = rx_max_burst_prd;
1364
1365 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1366 dwc->tx_max_burst_prd = tx_max_burst_prd;
1367
cf40b86b
JY		 1368 dwc->imod_interval = 0;
1369}
1370
1371/* check whether the core supports IMOD */
1372bool dwc3_has_imod(struct dwc3 *dwc)
1373{
1374 return ((dwc3_is_usb3(dwc) &&
1375 dwc->revision >= DWC3_REVISION_300A) ||
1376 (dwc3_is_usb31(dwc) &&
1377 dwc->revision >= DWC3_USB31_REVISION_120A));
c5ac6116
FB		 1378}
1379
7ac51a12
JY		 1380static void dwc3_check_params(struct dwc3 *dwc)
1381{
1382 struct device *dev = dwc->dev;
1383
cf40b86b
JY		 1384 /* Check for proper value of imod_interval */
1385 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1386 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1387 dwc->imod_interval = 0;
1388 }
1389
28632b44
JY		 1390 /*
1391 * Workaround for STAR 9000961433 which affects only version
1392 * 3.00a of the DWC_usb3 core. This prevents the controller
1393 * interrupt from being masked while handling events. IMOD
1394 * allows us to work around this issue. Enable it for the
1395 * affected version.
1396 */
1397 if (!dwc->imod_interval &&
1398 (dwc->revision == DWC3_REVISION_300A))
1399 dwc->imod_interval = 1;
1400
7ac51a12
JY		 1401 /* Check the maximum_speed parameter */
1402 switch (dwc->maximum_speed) {
1403 case USB_SPEED_LOW:
1404 case USB_SPEED_FULL:
1405 case USB_SPEED_HIGH:
1406 case USB_SPEED_SUPER:
1407 case USB_SPEED_SUPER_PLUS:
1408 break;
1409 default:
1410 dev_err(dev, "invalid maximum_speed parameter %d\n",
1411 dwc->maximum_speed);
1412 /* fall through */
1413 case USB_SPEED_UNKNOWN:
1414 /* default to superspeed */
1415 dwc->maximum_speed = USB_SPEED_SUPER;
1416
1417 /*
1418 * default to superspeed plus if we are capable.
1419 */
1420 if (dwc3_is_usb31(dwc) &&
1421 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1422 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1423 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1424
1425 break;
1426 }
1427}
1428
c5ac6116
FB		 1429static int dwc3_probe(struct platform_device *pdev)
1430{
1431 struct device *dev = &pdev->dev;
44feb8e6 1432 struct resource *res, dwc_res;
c5ac6116
FB		 1433 struct dwc3 *dwc;
1434
1435 int ret;
1436
1437 void __iomem *regs;
1438
1439 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1440 if (!dwc)
1441 return -ENOMEM;
1442
1443 dwc->dev = dev;
1444
1445 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1446 if (!res) {
1447 dev_err(dev, "missing memory resource\n");
1448 return -ENODEV;
1449 }
1450
1451 dwc->xhci_resources[0].start = res->start;
1452 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1453 DWC3_XHCI_REGS_END;
1454 dwc->xhci_resources[0].flags = res->flags;
1455 dwc->xhci_resources[0].name = res->name;
1456
c5ac6116
FB		 1457 /*
1458 * Request memory region but exclude xHCI regs,
1459 * since it will be requested by the xhci-plat driver.
1460 */
44feb8e6
MY		 1461 dwc_res = *res;
1462 dwc_res.start += DWC3_GLOBALS_REGS_START;
1463
1464 regs = devm_ioremap_resource(dev, &dwc_res);
1465 if (IS_ERR(regs))
1466 return PTR_ERR(regs);
c5ac6116
FB		 1467
1468 dwc->regs = regs;
44feb8e6 1469 dwc->regs_size = resource_size(&dwc_res);
c5ac6116
FB		 1470
1471 dwc3_get_properties(dwc);
1472
4a1d042a 1473 dwc->reset = devm_reset_control_array_get(dev, true, true);
fe8abf33
MY		 1474 if (IS_ERR(dwc->reset))
1475 return PTR_ERR(dwc->reset);
1476
61527777 1477 if (dev->of_node) {
0d3a9708 1478 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
61527777
HG		 1479 if (ret == -EPROBE_DEFER)
1480 return ret;
1481 /*
1482 * Clocks are optional, but new DT platforms should support all
1483 * clocks as required by the DT-binding.
1484 */
0d3a9708 1485 if (ret < 0)
61527777 1486 dwc->num_clks = 0;
0d3a9708
JS		 1487 else
1488 dwc->num_clks = ret;
1489
61527777 1490 }
fe8abf33
MY		 1491
1492 ret = reset_control_deassert(dwc->reset);
1493 if (ret)
03bf32bb 1494 return ret;
fe8abf33 1495
240b65dc 1496 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
fe8abf33
MY		 1497 if (ret)
1498 goto assert_reset;
1499
dc1b5d9a
EBS		 1500 if (!dwc3_core_is_valid(dwc)) {
1501 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1502 ret = -ENODEV;
1503 goto disable_clks;
1504 }
1505
6c89cce0 1506 platform_set_drvdata(pdev, dwc);
2917e718 1507 dwc3_cache_hwparams(dwc);
6c89cce0 1508
72246da4 1509 spin_lock_init(&dwc->lock);
72246da4 1510
fc8bb91b
FB		 1511 pm_runtime_set_active(dev);
1512 pm_runtime_use_autosuspend(dev);
1513 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
802ca850 1514 pm_runtime_enable(dev);
32808237
RQ		 1515 ret = pm_runtime_get_sync(dev);
1516 if (ret < 0)
1517 goto err1;
1518
802ca850 1519 pm_runtime_forbid(dev);
72246da4 1520
3921426b
FB		 1521 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1522 if (ret) {
1523 dev_err(dwc->dev, "failed to allocate event buffers\n");
1524 ret = -ENOMEM;
32808237 1525 goto err2;
3921426b
FB		 1526 }
1527
9d6173e1
TN		 1528 ret = dwc3_get_dr_mode(dwc);
1529 if (ret)
1530 goto err3;
32a4a135 1531
c499ff71
FB		 1532 ret = dwc3_alloc_scratch_buffers(dwc);
1533 if (ret)
32808237 1534 goto err3;
c499ff71 1535
72246da4
FB		 1536 ret = dwc3_core_init(dwc);
1537 if (ret) {
408d3ba0
BN		 1538 if (ret != -EPROBE_DEFER)
1539 dev_err(dev, "failed to initialize core: %d\n", ret);
32808237 1540 goto err4;
72246da4
FB		 1541 }
1542
7ac51a12 1543 dwc3_check_params(dwc);
2c7f1bd9 1544
5f94adfe
FB		 1545 ret = dwc3_core_init_mode(dwc);
1546 if (ret)
32808237 1547 goto err5;
72246da4 1548
4e9f3118 1549 dwc3_debugfs_init(dwc);
fc8bb91b 1550 pm_runtime_put(dev);
72246da4
FB		 1551
1552 return 0;
1553
32808237 1554err5:
c499ff71 1555 dwc3_event_buffers_cleanup(dwc);
08fd9a82 1556 dwc3_ulpi_exit(dwc);
57303488 1557
32808237 1558err4:
c499ff71 1559 dwc3_free_scratch_buffers(dwc);
72246da4 1560
32808237 1561err3:
3921426b
FB		 1562 dwc3_free_event_buffers(dwc);
1563
32808237
RQ		 1564err2:
1565 pm_runtime_allow(&pdev->dev);
1566
1567err1:
1568 pm_runtime_put_sync(&pdev->dev);
1569 pm_runtime_disable(&pdev->dev);
1570
dc1b5d9a 1571disable_clks:
240b65dc 1572 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
fe8abf33
MY		 1573assert_reset:
1574 reset_control_assert(dwc->reset);
fe8abf33 1575
72246da4
FB		 1576 return ret;
1577}
1578
fb4e98ab 1579static int dwc3_remove(struct platform_device *pdev)
72246da4 1580{
72246da4 1581 struct dwc3 *dwc = platform_get_drvdata(pdev);
3da1f6ee 1582
fc8bb91b 1583 pm_runtime_get_sync(&pdev->dev);
72246da4 1584
dc99f16f
FB		 1585 dwc3_debugfs_exit(dwc);
1586 dwc3_core_exit_mode(dwc);
8ba007a9 1587
72246da4 1588 dwc3_core_exit(dwc);
88bc9d19 1589 dwc3_ulpi_exit(dwc);
72246da4 1590
16b972a5 1591 pm_runtime_put_sync(&pdev->dev);
fc8bb91b 1592 pm_runtime_allow(&pdev->dev);
72246da4
FB		 1593 pm_runtime_disable(&pdev->dev);
1594
fc8bb91b
FB		 1595 dwc3_free_event_buffers(dwc);
1596 dwc3_free_scratch_buffers(dwc);
1597
72246da4
FB		 1598 return 0;
1599}
1600
fc8bb91b 1601#ifdef CONFIG_PM
fe8abf33
MY		 1602static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1603{
1604 int ret;
1605
1606 ret = reset_control_deassert(dwc->reset);
1607 if (ret)
1608 return ret;
1609
240b65dc 1610 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
fe8abf33
MY		 1611 if (ret)
1612 goto assert_reset;
1613
fe8abf33
MY		 1614 ret = dwc3_core_init(dwc);
1615 if (ret)
1616 goto disable_clks;
1617
1618 return 0;
1619
1620disable_clks:
240b65dc 1621 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
fe8abf33
MY		 1622assert_reset:
1623 reset_control_assert(dwc->reset);
1624
1625 return ret;
1626}
1627
c4a5153e 1628static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
7415f17c 1629{
fc8bb91b 1630 unsigned long flags;
bcb12877 1631 u32 reg;
7415f17c 1632
689bf72c
MG		 1633 switch (dwc->current_dr_role) {
1634 case DWC3_GCTL_PRTCAP_DEVICE:
0227cc84
LJ		 1635 if (pm_runtime_suspended(dwc->dev))
1636 break;
fc8bb91b 1637 spin_lock_irqsave(&dwc->lock, flags);
7415f17c 1638 dwc3_gadget_suspend(dwc);
fc8bb91b 1639 spin_unlock_irqrestore(&dwc->lock, flags);
41a91c60 1640 synchronize_irq(dwc->irq_gadget);
689bf72c 1641 dwc3_core_exit(dwc);
51f5d49a 1642 break;
689bf72c 1643 case DWC3_GCTL_PRTCAP_HOST:
bcb12877 1644 if (!PMSG_IS_AUTO(msg)) {
c4a5153e 1645 dwc3_core_exit(dwc);
bcb12877
MG		 1646 break;
1647 }
1648
1649 /* Let controller to suspend HSPHY before PHY driver suspends */
1650 if (dwc->dis_u2_susphy_quirk ||
1651 dwc->dis_enblslpm_quirk) {
1652 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1653 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1654 DWC3_GUSB2PHYCFG_SUSPHY;
1655 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1656
1657 /* Give some time for USB2 PHY to suspend */
1658 usleep_range(5000, 6000);
1659 }
1660
1661 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1662 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
c4a5153e 1663 break;
f09cc79b
RQ		 1664 case DWC3_GCTL_PRTCAP_OTG:
1665 /* do nothing during runtime_suspend */
1666 if (PMSG_IS_AUTO(msg))
1667 break;
1668
1669 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1670 spin_lock_irqsave(&dwc->lock, flags);
1671 dwc3_gadget_suspend(dwc);
1672 spin_unlock_irqrestore(&dwc->lock, flags);
41a91c60 1673 synchronize_irq(dwc->irq_gadget);
f09cc79b
RQ		 1674 }
1675
1676 dwc3_otg_exit(dwc);
1677 dwc3_core_exit(dwc);
1678 break;
7415f17c 1679 default:
51f5d49a 1680 /* do nothing */
7415f17c
FB		 1681 break;
1682 }
1683
7415f17c
FB		 1684 return 0;
1685}
1686
c4a5153e 1687static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
7415f17c 1688{
fc8bb91b 1689 unsigned long flags;
57303488 1690 int ret;
bcb12877 1691 u32 reg;
7415f17c 1692
689bf72c
MG		 1693 switch (dwc->current_dr_role) {
1694 case DWC3_GCTL_PRTCAP_DEVICE:
fe8abf33 1695 ret = dwc3_core_init_for_resume(dwc);
689bf72c
MG		 1696 if (ret)
1697 return ret;
5c4ad318 1698
7d11c3ac 1699 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
fc8bb91b 1700 spin_lock_irqsave(&dwc->lock, flags);
7415f17c 1701 dwc3_gadget_resume(dwc);
fc8bb91b 1702 spin_unlock_irqrestore(&dwc->lock, flags);
689bf72c
MG		 1703 break;
1704 case DWC3_GCTL_PRTCAP_HOST:
c4a5153e 1705 if (!PMSG_IS_AUTO(msg)) {
fe8abf33 1706 ret = dwc3_core_init_for_resume(dwc);
c4a5153e
MG		 1707 if (ret)
1708 return ret;
7d11c3ac 1709 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
bcb12877 1710 break;
c4a5153e 1711 }
bcb12877
MG		 1712 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1713 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1714 if (dwc->dis_u2_susphy_quirk)
1715 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1716
1717 if (dwc->dis_enblslpm_quirk)
1718 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1719
1720 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1721
1722 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1723 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
f09cc79b
RQ		 1724 break;
1725 case DWC3_GCTL_PRTCAP_OTG:
1726 /* nothing to do on runtime_resume */
1727 if (PMSG_IS_AUTO(msg))
1728 break;
1729
1730 ret = dwc3_core_init(dwc);
1731 if (ret)
1732 return ret;
1733
1734 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1735
1736 dwc3_otg_init(dwc);
1737 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1738 dwc3_otg_host_init(dwc);
1739 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1740 spin_lock_irqsave(&dwc->lock, flags);
1741 dwc3_gadget_resume(dwc);
1742 spin_unlock_irqrestore(&dwc->lock, flags);
c4a5153e 1743 }
f09cc79b 1744
c4a5153e 1745 break;
7415f17c
FB		 1746 default:
1747 /* do nothing */
1748 break;
1749 }
1750
fc8bb91b
FB		 1751 return 0;
1752}
1753
1754static int dwc3_runtime_checks(struct dwc3 *dwc)
1755{
689bf72c 1756 switch (dwc->current_dr_role) {
c4a5153e 1757 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 1758 if (dwc->connected)
1759 return -EBUSY;
1760 break;
c4a5153e 1761 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 1762 default:
1763 /* do nothing */
1764 break;
1765 }
1766
1767 return 0;
1768}
1769
1770static int dwc3_runtime_suspend(struct device *dev)
1771{
1772 struct dwc3 *dwc = dev_get_drvdata(dev);
1773 int ret;
1774
1775 if (dwc3_runtime_checks(dwc))
1776 return -EBUSY;
1777
c4a5153e 1778 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
fc8bb91b
FB		 1779 if (ret)
1780 return ret;
1781
1782 device_init_wakeup(dev, true);
1783
1784 return 0;
1785}
1786
1787static int dwc3_runtime_resume(struct device *dev)
1788{
1789 struct dwc3 *dwc = dev_get_drvdata(dev);
1790 int ret;
1791
1792 device_init_wakeup(dev, false);
1793
c4a5153e 1794 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
fc8bb91b
FB		 1795 if (ret)
1796 return ret;
1797
689bf72c
MG		 1798 switch (dwc->current_dr_role) {
1799 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 1800 dwc3_gadget_process_pending_events(dwc);
1801 break;
689bf72c 1802 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 1803 default:
1804 /* do nothing */
1805 break;
1806 }
1807
1808 pm_runtime_mark_last_busy(dev);
1809
1810 return 0;
1811}
1812
1813static int dwc3_runtime_idle(struct device *dev)
1814{
1815 struct dwc3 *dwc = dev_get_drvdata(dev);
1816
689bf72c
MG		 1817 switch (dwc->current_dr_role) {
1818 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 1819 if (dwc3_runtime_checks(dwc))
1820 return -EBUSY;
1821 break;
689bf72c 1822 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 1823 default:
1824 /* do nothing */
1825 break;
1826 }
1827
1828 pm_runtime_mark_last_busy(dev);
1829 pm_runtime_autosuspend(dev);
1830
1831 return 0;
1832}
1833#endif /* CONFIG_PM */
1834
1835#ifdef CONFIG_PM_SLEEP
1836static int dwc3_suspend(struct device *dev)
1837{
1838 struct dwc3 *dwc = dev_get_drvdata(dev);
1839 int ret;
1840
c4a5153e 1841 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
fc8bb91b
FB		 1842 if (ret)
1843 return ret;
1844
1845 pinctrl_pm_select_sleep_state(dev);
1846
1847 return 0;
1848}
1849
1850static int dwc3_resume(struct device *dev)
1851{
1852 struct dwc3 *dwc = dev_get_drvdata(dev);
1853 int ret;
1854
1855 pinctrl_pm_select_default_state(dev);
1856
c4a5153e 1857 ret = dwc3_resume_common(dwc, PMSG_RESUME);
fc8bb91b
FB		 1858 if (ret)
1859 return ret;
1860
7415f17c
FB		 1861 pm_runtime_disable(dev);
1862 pm_runtime_set_active(dev);
1863 pm_runtime_enable(dev);
1864
1865 return 0;
1866}
7f370ed0 1867#endif /* CONFIG_PM_SLEEP */
7415f17c
FB		 1868
1869static const struct dev_pm_ops dwc3_dev_pm_ops = {
7415f17c 1870 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
fc8bb91b
FB		 1871 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1872 dwc3_runtime_idle)
7415f17c
FB		 1873};
1874
5088b6f5
KVA		 1875#ifdef CONFIG_OF
1876static const struct of_device_id of_dwc3_match[] = {
22a5aa17
FB		 1877 {
1878 .compatible = "snps,dwc3"
1879 },
5088b6f5
KVA		 1880 {
1881 .compatible = "synopsys,dwc3"
1882 },
1883 { },
1884};
1885MODULE_DEVICE_TABLE(of, of_dwc3_match);
1886#endif
1887
404905a6
HK		 1888#ifdef CONFIG_ACPI
1889
1890#define ACPI_ID_INTEL_BSW "808622B7"
1891
1892static const struct acpi_device_id dwc3_acpi_match[] = {
1893 { ACPI_ID_INTEL_BSW, 0 },
1894 { },
1895};
1896MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1897#endif
1898
72246da4
FB		 1899static struct platform_driver dwc3_driver = {
1900 .probe = dwc3_probe,
7690417d 1901 .remove = dwc3_remove,
72246da4
FB		 1902 .driver = {
1903 .name = "dwc3",
5088b6f5 1904 .of_match_table = of_match_ptr(of_dwc3_match),
404905a6 1905 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
7f370ed0 1906 .pm = &dwc3_dev_pm_ops,
72246da4 1907 },
72246da4
FB		 1908};
1909
b1116dcc
TK		 1910module_platform_driver(dwc3_driver);
1911
7ae4fc4d 1912MODULE_ALIAS("platform:dwc3");
72246da4 1913MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
5945f789 1914MODULE_LICENSE("GPL v2");
72246da4 1915MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux 6.x block layer and io_uring tree(s)