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[linux-block.git] / drivers / usb / dwc3 / core.c
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5fd54ace 1// SPDX-License-Identifier: GPL-2.0
72246da4
FB		 2/**
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
10623b87 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
72246da4
FB		 6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
72246da4
FB		 9 */
10
fe8abf33 11#include <linux/clk.h>
fa0ea13e 12#include <linux/version.h>
a72e658b 13#include <linux/module.h>
72246da4
FB		 14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/io.h>
22#include <linux/list.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
457e84b6 25#include <linux/of.h>
404905a6 26#include <linux/acpi.h>
6344475f 27#include <linux/pinctrl/consumer.h>
fe8abf33 28#include <linux/reset.h>
72246da4
FB		 29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
f7e846f0 32#include <linux/usb/of.h>
a45c82b8 33#include <linux/usb/otg.h>
72246da4
FB		 34
35#include "core.h"
36#include "gadget.h"
37#include "io.h"
38
39#include "debug.h"
40
fc8bb91b 41#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
8300dd23 42
9d6173e1
TN		 43/**
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
46 */
47static int dwc3_get_dr_mode(struct dwc3 *dwc)
48{
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
51 unsigned int hw_mode;
52
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
55
56 mode = dwc->dr_mode;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
58
59 switch (hw_mode) {
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
62 dev_err(dev,
63 "Controller does not support host mode.\n");
64 return -EINVAL;
65 }
66 mode = USB_DR_MODE_PERIPHERAL;
67 break;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
70 dev_err(dev,
71 "Controller does not support device mode.\n");
72 return -EINVAL;
73 }
74 mode = USB_DR_MODE_HOST;
75 break;
76 default:
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
a7700468
TN		 81
82 /*
89a9cc47
TN		 83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
84 * mode. If the controller supports DRD but the dr_mode is not
85 * specified or set to OTG, then set the mode to peripheral.
a7700468 86 */
89a9cc47 87 if (mode == USB_DR_MODE_OTG &&
8bb14308
TN		 88 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
89 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
9af21dd6 90 !DWC3_VER_IS_PRIOR(DWC3, 330A))
a7700468 91 mode = USB_DR_MODE_PERIPHERAL;
9d6173e1
TN		 92 }
93
94 if (mode != dwc->dr_mode) {
95 dev_warn(dev,
96 "Configuration mismatch. dr_mode forced to %s\n",
97 mode == USB_DR_MODE_HOST ? "host" : "gadget");
98
99 dwc->dr_mode = mode;
100 }
101
102 return 0;
103}
104
f09cc79b 105void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
3140e8cb
SAS		 106{
107 u32 reg;
108
109 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
110 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
111 reg |= DWC3_GCTL_PRTCAPDIR(mode);
112 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
c4a5153e
MG		 113
114 dwc->current_dr_role = mode;
41ce1456
RQ		 115}
116
117static void __dwc3_set_mode(struct work_struct *work)
118{
119 struct dwc3 *dwc = work_to_dwc(work);
120 unsigned long flags;
121 int ret;
122
f09cc79b 123 if (dwc->dr_mode != USB_DR_MODE_OTG)
41ce1456
RQ		 124 return;
125
c2cd3452
MK		 126 pm_runtime_get_sync(dwc->dev);
127
f09cc79b
RQ		 128 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
129 dwc3_otg_update(dwc, 0);
130
41ce1456 131 if (!dwc->desired_dr_role)
c2cd3452 132 goto out;
41ce1456
RQ		 133
134 if (dwc->desired_dr_role == dwc->current_dr_role)
c2cd3452 135 goto out;
41ce1456 136
f09cc79b 137 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
c2cd3452 138 goto out;
41ce1456
RQ		 139
140 switch (dwc->current_dr_role) {
141 case DWC3_GCTL_PRTCAP_HOST:
142 dwc3_host_exit(dwc);
143 break;
144 case DWC3_GCTL_PRTCAP_DEVICE:
145 dwc3_gadget_exit(dwc);
146 dwc3_event_buffers_cleanup(dwc);
147 break;
f09cc79b
RQ		 148 case DWC3_GCTL_PRTCAP_OTG:
149 dwc3_otg_exit(dwc);
150 spin_lock_irqsave(&dwc->lock, flags);
151 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
152 spin_unlock_irqrestore(&dwc->lock, flags);
153 dwc3_otg_update(dwc, 1);
154 break;
41ce1456
RQ		 155 default:
156 break;
157 }
158
159 spin_lock_irqsave(&dwc->lock, flags);
160
161 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
6b3261a2 162
41ce1456
RQ		 163 spin_unlock_irqrestore(&dwc->lock, flags);
164
165 switch (dwc->desired_dr_role) {
166 case DWC3_GCTL_PRTCAP_HOST:
167 ret = dwc3_host_init(dwc);
958d1a4c 168 if (ret) {
41ce1456 169 dev_err(dwc->dev, "failed to initialize host\n");
958d1a4c
FB		 170 } else {
171 if (dwc->usb2_phy)
172 otg_set_vbus(dwc->usb2_phy->otg, true);
644cbbc3
MG		 173 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
174 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
958d1a4c 175 }
41ce1456
RQ		 176 break;
177 case DWC3_GCTL_PRTCAP_DEVICE:
178 dwc3_event_buffers_setup(dwc);
958d1a4c
FB		 179
180 if (dwc->usb2_phy)
181 otg_set_vbus(dwc->usb2_phy->otg, false);
644cbbc3
MG		 182 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
183 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
958d1a4c 184
41ce1456
RQ		 185 ret = dwc3_gadget_init(dwc);
186 if (ret)
187 dev_err(dwc->dev, "failed to initialize peripheral\n");
188 break;
f09cc79b
RQ		 189 case DWC3_GCTL_PRTCAP_OTG:
190 dwc3_otg_init(dwc);
191 dwc3_otg_update(dwc, 0);
192 break;
41ce1456
RQ		 193 default:
194 break;
195 }
f09cc79b 196
c2cd3452
MK		 197out:
198 pm_runtime_mark_last_busy(dwc->dev);
199 pm_runtime_put_autosuspend(dwc->dev);
41ce1456
RQ		 200}
201
202void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
203{
204 unsigned long flags;
205
206 spin_lock_irqsave(&dwc->lock, flags);
207 dwc->desired_dr_role = mode;
208 spin_unlock_irqrestore(&dwc->lock, flags);
209
084a804e 210 queue_work(system_freezable_wq, &dwc->drd_work);
3140e8cb 211}
8300dd23 212
cf6d867d
FB		 213u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
214{
215 struct dwc3 *dwc = dep->dwc;
216 u32 reg;
217
218 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
219 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
220 DWC3_GDBGFIFOSPACE_TYPE(type));
221
222 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
223
224 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
225}
226
72246da4
FB		 227/**
228 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
229 * @dwc: pointer to our context structure
230 */
57303488 231static int dwc3_core_soft_reset(struct dwc3 *dwc)
72246da4
FB		 232{
233 u32 reg;
f59dcab1 234 int retries = 1000;
57303488 235 int ret;
72246da4 236
51e1e7bc
FB		 237 usb_phy_init(dwc->usb2_phy);
238 usb_phy_init(dwc->usb3_phy);
57303488
KVA		 239 ret = phy_init(dwc->usb2_generic_phy);
240 if (ret < 0)
241 return ret;
242
243 ret = phy_init(dwc->usb3_generic_phy);
244 if (ret < 0) {
245 phy_exit(dwc->usb2_generic_phy);
246 return ret;
247 }
72246da4 248
f59dcab1
FB		 249 /*
250 * We're resetting only the device side because, if we're in host mode,
251 * XHCI driver will reset the host block. If dwc3 was configured for
252 * host-only mode, then we can return early.
253 */
c4a5153e 254 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
f59dcab1 255 return 0;
72246da4 256
f59dcab1
FB		 257 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
258 reg |= DWC3_DCTL_CSFTRST;
259 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 260
4749e0e6
TN		 261 /*
262 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
263 * is cleared only after all the clocks are synchronized. This can
264 * take a little more than 50ms. Set the polling rate at 20ms
265 * for 10 times instead.
266 */
9af21dd6 267 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
4749e0e6
TN		 268 retries = 10;
269
f59dcab1
FB		 270 do {
271 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
272 if (!(reg & DWC3_DCTL_CSFTRST))
fab38333 273 goto done;
45627ac6 274
9af21dd6 275 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
4749e0e6
TN		 276 msleep(20);
277 else
278 udelay(1);
f59dcab1 279 } while (--retries);
57303488 280
00b42170
BN		 281 phy_exit(dwc->usb3_generic_phy);
282 phy_exit(dwc->usb2_generic_phy);
283
f59dcab1 284 return -ETIMEDOUT;
fab38333
TN		 285
286done:
287 /*
4749e0e6
TN		 288 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
289 * is cleared, we must wait at least 50ms before accessing the PHY
290 * domain (synchronization delay).
fab38333 291 */
9af21dd6 292 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
fab38333
TN		 293 msleep(50);
294
295 return 0;
72246da4
FB		 296}
297
db2be4e9
NB		 298/*
299 * dwc3_frame_length_adjustment - Adjusts frame length if required
300 * @dwc3: Pointer to our controller context structure
db2be4e9 301 */
bcdb3272 302static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
db2be4e9
NB		 303{
304 u32 reg;
305 u32 dft;
306
9af21dd6 307 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
db2be4e9
NB		 308 return;
309
bcdb3272 310 if (dwc->fladj == 0)
db2be4e9
NB		 311 return;
312
313 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
314 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
a7d9874c 315 if (dft != dwc->fladj) {
db2be4e9 316 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
bcdb3272 317 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
db2be4e9
NB		 318 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
319 }
320}
321
72246da4
FB		 322/**
323 * dwc3_free_one_event_buffer - Frees one event buffer
324 * @dwc: Pointer to our controller context structure
325 * @evt: Pointer to event buffer to be freed
326 */
327static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
328 struct dwc3_event_buffer *evt)
329{
d64ff406 330 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
72246da4
FB		 331}
332
333/**
1d046793 334 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
72246da4
FB		 335 * @dwc: Pointer to our controller context structure
336 * @length: size of the event buffer
337 *
1d046793 338 * Returns a pointer to the allocated event buffer structure on success
72246da4
FB		 339 * otherwise ERR_PTR(errno).
340 */
67d0b500
FB		 341static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
342 unsigned length)
72246da4
FB		 343{
344 struct dwc3_event_buffer *evt;
345
380f0d28 346 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
72246da4
FB		 347 if (!evt)
348 return ERR_PTR(-ENOMEM);
349
350 evt->dwc = dwc;
351 evt->length = length;
d9fa4c63
JY		 352 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
353 if (!evt->cache)
354 return ERR_PTR(-ENOMEM);
355
d64ff406 356 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
72246da4 357 &evt->dma, GFP_KERNEL);
e32672f0 358 if (!evt->buf)
72246da4 359 return ERR_PTR(-ENOMEM);
72246da4
FB		 360
361 return evt;
362}
363
364/**
365 * dwc3_free_event_buffers - frees all allocated event buffers
366 * @dwc: Pointer to our controller context structure
367 */
368static void dwc3_free_event_buffers(struct dwc3 *dwc)
369{
370 struct dwc3_event_buffer *evt;
72246da4 371
696c8b12 372 evt = dwc->ev_buf;
660e9bde
FB		 373 if (evt)
374 dwc3_free_one_event_buffer(dwc, evt);
72246da4
FB		 375}
376
377/**
378 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
1d046793 379 * @dwc: pointer to our controller context structure
72246da4
FB		 380 * @length: size of event buffer
381 *
1d046793 382 * Returns 0 on success otherwise negative errno. In the error case, dwc
72246da4
FB		 383 * may contain some buffers allocated but not all which were requested.
384 */
41ac7b3a 385static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
72246da4 386{
660e9bde 387 struct dwc3_event_buffer *evt;
72246da4 388
660e9bde
FB		 389 evt = dwc3_alloc_one_event_buffer(dwc, length);
390 if (IS_ERR(evt)) {
391 dev_err(dwc->dev, "can't allocate event buffer\n");
392 return PTR_ERR(evt);
72246da4 393 }
696c8b12 394 dwc->ev_buf = evt;
72246da4
FB		 395
396 return 0;
397}
398
399/**
400 * dwc3_event_buffers_setup - setup our allocated event buffers
1d046793 401 * @dwc: pointer to our controller context structure
72246da4
FB		 402 *
403 * Returns 0 on success otherwise negative errno.
404 */
f09cc79b 405int dwc3_event_buffers_setup(struct dwc3 *dwc)
72246da4
FB		 406{
407 struct dwc3_event_buffer *evt;
72246da4 408
696c8b12 409 evt = dwc->ev_buf;
660e9bde 410 evt->lpos = 0;
660e9bde
FB		 411 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
412 lower_32_bits(evt->dma));
413 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
414 upper_32_bits(evt->dma));
415 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
416 DWC3_GEVNTSIZ_SIZE(evt->length));
417 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 418
419 return 0;
420}
421
f09cc79b 422void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
72246da4
FB		 423{
424 struct dwc3_event_buffer *evt;
72246da4 425
696c8b12 426 evt = dwc->ev_buf;
7acd85e0 427
660e9bde 428 evt->lpos = 0;
7acd85e0 429
660e9bde
FB		 430 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
431 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
432 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
433 | DWC3_GEVNTSIZ_SIZE(0));
434 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 435}
436
0ffcaf37
FB		 437static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
438{
439 if (!dwc->has_hibernation)
440 return 0;
441
442 if (!dwc->nr_scratch)
443 return 0;
444
445 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
446 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
447 if (!dwc->scratchbuf)
448 return -ENOMEM;
449
450 return 0;
451}
452
453static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
454{
455 dma_addr_t scratch_addr;
456 u32 param;
457 int ret;
458
459 if (!dwc->has_hibernation)
460 return 0;
461
462 if (!dwc->nr_scratch)
463 return 0;
464
465 /* should never fall here */
466 if (!WARN_ON(dwc->scratchbuf))
467 return 0;
468
d64ff406 469 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
0ffcaf37
FB		 470 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
471 DMA_BIDIRECTIONAL);
d64ff406
AB		 472 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
473 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
0ffcaf37
FB		 474 ret = -EFAULT;
475 goto err0;
476 }
477
478 dwc->scratch_addr = scratch_addr;
479
480 param = lower_32_bits(scratch_addr);
481
482 ret = dwc3_send_gadget_generic_command(dwc,
483 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
484 if (ret < 0)
485 goto err1;
486
487 param = upper_32_bits(scratch_addr);
488
489 ret = dwc3_send_gadget_generic_command(dwc,
490 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
491 if (ret < 0)
492 goto err1;
493
494 return 0;
495
496err1:
d64ff406 497 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
0ffcaf37
FB		 498 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
499
500err0:
501 return ret;
502}
503
504static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
505{
506 if (!dwc->has_hibernation)
507 return;
508
509 if (!dwc->nr_scratch)
510 return;
511
512 /* should never fall here */
513 if (!WARN_ON(dwc->scratchbuf))
514 return;
515
d64ff406 516 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
0ffcaf37
FB		 517 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
518 kfree(dwc->scratchbuf);
519}
520
789451f6
FB		 521static void dwc3_core_num_eps(struct dwc3 *dwc)
522{
523 struct dwc3_hwparams *parms = &dwc->hwparams;
524
47d3946e 525 dwc->num_eps = DWC3_NUM_EPS(parms);
789451f6
FB		 526}
527
41ac7b3a 528static void dwc3_cache_hwparams(struct dwc3 *dwc)
26ceca97
FB		 529{
530 struct dwc3_hwparams *parms = &dwc->hwparams;
531
532 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
533 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
534 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
535 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
536 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
537 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
538 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
539 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
540 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
541}
542
98112041
RQ		 543static int dwc3_core_ulpi_init(struct dwc3 *dwc)
544{
545 int intf;
546 int ret = 0;
547
548 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
549
550 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
551 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
552 dwc->hsphy_interface &&
553 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
554 ret = dwc3_ulpi_init(dwc);
555
556 return ret;
557}
558
b5a65c40
HR		 559/**
560 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
561 * @dwc: Pointer to our controller context structure
88bc9d19
HK		 562 *
563 * Returns 0 on success. The USB PHY interfaces are configured but not
564 * initialized. The PHY interfaces and the PHYs get initialized together with
565 * the core in dwc3_core_init.
b5a65c40 566 */
88bc9d19 567static int dwc3_phy_setup(struct dwc3 *dwc)
b5a65c40 568{
9ba3aca8 569 unsigned int hw_mode;
b5a65c40
HR		 570 u32 reg;
571
9ba3aca8
TN		 572 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
573
b5a65c40
HR		 574 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
575
1966b865
FB		 576 /*
577 * Make sure UX_EXIT_PX is cleared as that causes issues with some
578 * PHYs. Also, this bit is not supposed to be used in normal operation.
579 */
580 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
581
2164a476
HR		 582 /*
583 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
584 * to '0' during coreConsultant configuration. So default value
585 * will be '0' when the core is reset. Application needs to set it
586 * to '1' after the core initialization is completed.
587 */
9af21dd6 588 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
2164a476
HR		 589 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
590
9ba3aca8
TN		 591 /*
592 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
593 * power-on reset, and it can be set after core initialization, which is
594 * after device soft-reset during initialization.
595 */
596 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
597 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
598
b5a65c40
HR		 599 if (dwc->u2ss_inp3_quirk)
600 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
601
e58dd357
RB		 602 if (dwc->dis_rxdet_inp3_quirk)
603 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
604
df31f5b3
HR		 605 if (dwc->req_p1p2p3_quirk)
606 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
607
a2a1d0f5
HR		 608 if (dwc->del_p1p2p3_quirk)
609 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
610
41c06ffd
HR		 611 if (dwc->del_phy_power_chg_quirk)
612 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
613
fb67afca
HR		 614 if (dwc->lfps_filter_quirk)
615 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
616
14f4ac53
HR		 617 if (dwc->rx_detect_poll_quirk)
618 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
619
6b6a0c9a
HR		 620 if (dwc->tx_de_emphasis_quirk)
621 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
622
cd72f890 623 if (dwc->dis_u3_susphy_quirk)
59acfa20
HR		 624 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
625
00fe081d
WW		 626 if (dwc->dis_del_phy_power_chg_quirk)
627 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
628
b5a65c40
HR		 629 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
630
2164a476
HR		 631 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
632
3e10a2ce
HK		 633 /* Select the HS PHY interface */
634 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
635 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
43cacb03
FB		 636 if (dwc->hsphy_interface &&
637 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
3e10a2ce 638 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 639 break;
43cacb03
FB		 640 } else if (dwc->hsphy_interface &&
641 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
3e10a2ce 642 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 643 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
3e10a2ce 644 } else {
88bc9d19
HK		 645 /* Relying on default value. */
646 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
647 break;
3e10a2ce 648 }
df561f66 649 fallthrough;
88bc9d19 650 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
3e10a2ce
HK		 651 default:
652 break;
653 }
654
32f2ed86
WW		 655 switch (dwc->hsphy_mode) {
656 case USBPHY_INTERFACE_MODE_UTMI:
657 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
658 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
659 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
660 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
661 break;
662 case USBPHY_INTERFACE_MODE_UTMIW:
663 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
664 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
665 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
666 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
667 break;
668 default:
669 break;
670 }
671
2164a476
HR		 672 /*
673 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
674 * '0' during coreConsultant configuration. So default value will
675 * be '0' when the core is reset. Application needs to set it to
676 * '1' after the core initialization is completed.
677 */
9af21dd6 678 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
2164a476
HR		 679 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
680
9ba3aca8
TN		 681 /*
682 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
683 * power-on reset, and it can be set after core initialization, which is
684 * after device soft-reset during initialization.
685 */
686 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
687 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
688
cd72f890 689 if (dwc->dis_u2_susphy_quirk)
0effe0a3
HR		 690 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
691
ec791d14
JY		 692 if (dwc->dis_enblslpm_quirk)
693 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
eafeacf1
TN		 694 else
695 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
ec791d14 696
16199f33
WW		 697 if (dwc->dis_u2_freeclk_exists_quirk)
698 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
699
2164a476 700 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
88bc9d19
HK		 701
702 return 0;
b5a65c40
HR		 703}
704
c499ff71
FB		 705static void dwc3_core_exit(struct dwc3 *dwc)
706{
707 dwc3_event_buffers_cleanup(dwc);
708
709 usb_phy_shutdown(dwc->usb2_phy);
710 usb_phy_shutdown(dwc->usb3_phy);
711 phy_exit(dwc->usb2_generic_phy);
712 phy_exit(dwc->usb3_generic_phy);
713
714 usb_phy_set_suspend(dwc->usb2_phy, 1);
715 usb_phy_set_suspend(dwc->usb3_phy, 1);
716 phy_power_off(dwc->usb2_generic_phy);
717 phy_power_off(dwc->usb3_generic_phy);
240b65dc 718 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
fe8abf33 719 reset_control_assert(dwc->reset);
c499ff71
FB		 720}
721
0759956f 722static bool dwc3_core_is_valid(struct dwc3 *dwc)
72246da4 723{
0759956f 724 u32 reg;
72246da4 725
7650bd74 726 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
9af21dd6 727 dwc->ip = DWC3_GSNPS_ID(reg);
0759956f 728
7650bd74 729 /* This should read as U3 followed by revision number */
9af21dd6 730 if (DWC3_IP_IS(DWC3)) {
690fb371 731 dwc->revision = reg;
9af21dd6 732 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
690fb371 733 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
475d8e01 734 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
690fb371 735 } else {
0759956f 736 return false;
7650bd74 737 }
7650bd74 738
0759956f
FB		 739 return true;
740}
58a0f23f 741
941f918e 742static void dwc3_core_setup_global_control(struct dwc3 *dwc)
0759956f 743{
941f918e
FB		 744 u32 hwparams4 = dwc->hwparams.hwparams4;
745 u32 reg;
c499ff71 746
4878a028 747 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
3e87c42a 748 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
4878a028 749
164d7731 750 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
4878a028 751 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
32a4a135
FB		 752 /**
753 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
754 * issue which would cause xHCI compliance tests to fail.
755 *
756 * Because of that we cannot enable clock gating on such
757 * configurations.
758 *
759 * Refers to:
760 *
761 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
762 * SOF/ITP Mode Used
763 */
764 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
765 dwc->dr_mode == USB_DR_MODE_OTG) &&
9af21dd6 766 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
32a4a135
FB		 767 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
768 else
769 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
4878a028 770 break;
0ffcaf37
FB		 771 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
772 /* enable hibernation here */
773 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
2eac3992
HR		 774
775 /*
776 * REVISIT Enabling this bit so that host-mode hibernation
777 * will work. Device-mode hibernation is not yet implemented.
778 */
779 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
0ffcaf37 780 break;
4878a028 781 default:
5eb30ced
FB		 782 /* nothing */
783 break;
4878a028
SAS		 784 }
785
946bd579
HR		 786 /* check if current dwc3 is on simulation board */
787 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
6af19fd1 788 dev_info(dwc->dev, "Running with FPGA optimizations\n");
946bd579
HR		 789 dwc->is_fpga = true;
790 }
791
3b81221a
HR		 792 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
793 "disable_scramble cannot be used on non-FPGA builds\n");
794
795 if (dwc->disable_scramble_quirk && dwc->is_fpga)
796 reg |= DWC3_GCTL_DISSCRAMBLE;
797 else
798 reg &= ~DWC3_GCTL_DISSCRAMBLE;
799
9a5b2f31
HR		 800 if (dwc->u2exit_lfps_quirk)
801 reg |= DWC3_GCTL_U2EXIT_LFPS;
802
4878a028
SAS		 803 /*
804 * WORKAROUND: DWC3 revisions <1.90a have a bug
1d046793 805 * where the device can fail to connect at SuperSpeed
4878a028 806 * and falls back to high-speed mode which causes
1d046793 807 * the device to enter a Connect/Disconnect loop
4878a028 808 */
9af21dd6 809 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
4878a028
SAS		 810 reg |= DWC3_GCTL_U2RSTECN;
811
812 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
941f918e
FB		 813}
814
f54edb53 815static int dwc3_core_get_phy(struct dwc3 *dwc);
98112041 816static int dwc3_core_ulpi_init(struct dwc3 *dwc);
f54edb53 817
d9612c2f
PM		 818/* set global incr burst type configuration registers */
819static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
820{
821 struct device *dev = dwc->dev;
822 /* incrx_mode : for INCR burst type. */
823 bool incrx_mode;
824 /* incrx_size : for size of INCRX burst. */
825 u32 incrx_size;
826 u32 *vals;
827 u32 cfg;
828 int ntype;
829 int ret;
830 int i;
831
832 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
833
834 /*
835 * Handle property "snps,incr-burst-type-adjustment".
836 * Get the number of value from this property:
837 * result <= 0, means this property is not supported.
838 * result = 1, means INCRx burst mode supported.
839 * result > 1, means undefined length burst mode supported.
840 */
a6e5e679 841 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
d9612c2f
PM		 842 if (ntype <= 0)
843 return;
844
845 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
846 if (!vals) {
847 dev_err(dev, "Error to get memory\n");
848 return;
849 }
850
851 /* Get INCR burst type, and parse it */
852 ret = device_property_read_u32_array(dev,
853 "snps,incr-burst-type-adjustment", vals, ntype);
854 if (ret) {
75ecb9dd 855 kfree(vals);
d9612c2f
PM		 856 dev_err(dev, "Error to get property\n");
857 return;
858 }
859
860 incrx_size = *vals;
861
862 if (ntype > 1) {
863 /* INCRX (undefined length) burst mode */
864 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
865 for (i = 1; i < ntype; i++) {
866 if (vals[i] > incrx_size)
867 incrx_size = vals[i];
868 }
869 } else {
870 /* INCRX burst mode */
871 incrx_mode = INCRX_BURST_MODE;
872 }
873
75ecb9dd
AS		 874 kfree(vals);
875
d9612c2f
PM		 876 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
877 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
878 if (incrx_mode)
879 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
880 switch (incrx_size) {
881 case 256:
882 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
883 break;
884 case 128:
885 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
886 break;
887 case 64:
888 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
889 break;
890 case 32:
891 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
892 break;
893 case 16:
894 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
895 break;
896 case 8:
897 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
898 break;
899 case 4:
900 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
901 break;
902 case 1:
903 break;
904 default:
905 dev_err(dev, "Invalid property\n");
906 break;
907 }
908
909 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
910}
911
941f918e
FB		 912/**
913 * dwc3_core_init - Low-level initialization of DWC3 Core
914 * @dwc: Pointer to our controller context structure
915 *
916 * Returns 0 on success otherwise negative errno.
917 */
918static int dwc3_core_init(struct dwc3 *dwc)
919{
9ba3aca8 920 unsigned int hw_mode;
941f918e
FB		 921 u32 reg;
922 int ret;
923
9ba3aca8
TN		 924 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
925
941f918e
FB		 926 /*
927 * Write Linux Version Code to our GUID register so it's easy to figure
928 * out which kernel version a bug was found.
929 */
930 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
931
932 /* Handle USB2.0-only core configuration */
933 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
934 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
935 if (dwc->maximum_speed == USB_SPEED_SUPER)
936 dwc->maximum_speed = USB_SPEED_HIGH;
937 }
938
98112041 939 ret = dwc3_phy_setup(dwc);
941f918e
FB		 940 if (ret)
941 goto err0;
4878a028 942
98112041
RQ		 943 if (!dwc->ulpi_ready) {
944 ret = dwc3_core_ulpi_init(dwc);
945 if (ret)
946 goto err0;
947 dwc->ulpi_ready = true;
948 }
4878a028 949
98112041
RQ		 950 if (!dwc->phys_ready) {
951 ret = dwc3_core_get_phy(dwc);
952 if (ret)
953 goto err0a;
954 dwc->phys_ready = true;
955 }
956
957 ret = dwc3_core_soft_reset(dwc);
f54edb53 958 if (ret)
98112041 959 goto err0a;
f54edb53 960
9ba3aca8 961 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
9af21dd6 962 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
9ba3aca8
TN		 963 if (!dwc->dis_u3_susphy_quirk) {
964 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
965 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
966 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
967 }
968
969 if (!dwc->dis_u2_susphy_quirk) {
970 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
971 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
972 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
973 }
974 }
975
941f918e 976 dwc3_core_setup_global_control(dwc);
c499ff71 977 dwc3_core_num_eps(dwc);
0ffcaf37
FB		 978
979 ret = dwc3_setup_scratch_buffers(dwc);
980 if (ret)
c499ff71
FB		 981 goto err1;
982
983 /* Adjust Frame Length */
984 dwc3_frame_length_adjustment(dwc);
985
d9612c2f
PM		 986 dwc3_set_incr_burst_type(dwc);
987
c499ff71
FB		 988 usb_phy_set_suspend(dwc->usb2_phy, 0);
989 usb_phy_set_suspend(dwc->usb3_phy, 0);
990 ret = phy_power_on(dwc->usb2_generic_phy);
991 if (ret < 0)
0ffcaf37
FB		 992 goto err2;
993
c499ff71
FB		 994 ret = phy_power_on(dwc->usb3_generic_phy);
995 if (ret < 0)
996 goto err3;
997
998 ret = dwc3_event_buffers_setup(dwc);
999 if (ret) {
1000 dev_err(dwc->dev, "failed to setup event buffers\n");
1001 goto err4;
1002 }
1003
06281d46
JY		 1004 /*
1005 * ENDXFER polling is available on version 3.10a and later of
1006 * the DWC_usb3 controller. It is NOT available in the
1007 * DWC_usb31 controller.
1008 */
9af21dd6 1009 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
06281d46
JY		 1010 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1011 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1012 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1013 }
1014
9af21dd6 1015 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
0bb39ca1 1016 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
65db7a0c
WW		 1017
1018 /*
1019 * Enable hardware control of sending remote wakeup
1020 * in HS when the device is in the L1 state.
1021 */
9af21dd6 1022 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
65db7a0c
WW		 1023 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1024
1025 if (dwc->dis_tx_ipgap_linecheck_quirk)
1026 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1027
7ba6b09f
NA		 1028 if (dwc->parkmode_disable_ss_quirk)
1029 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1030
0bb39ca1
JY		 1031 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1032 }
1033
b138e23d
AKV		 1034 if (dwc->dr_mode == USB_DR_MODE_HOST ||
1035 dwc->dr_mode == USB_DR_MODE_OTG) {
1036 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1037
1038 /*
1039 * Enable Auto retry Feature to make the controller operating in
1040 * Host mode on seeing transaction errors(CRC errors or internal
1041 * overrun scenerios) on IN transfers to reply to the device
1042 * with a non-terminating retry ACK (i.e, an ACK transcation
1043 * packet with Retry=1 & Nump != 0)
1044 */
1045 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1046
1047 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1048 }
1049
938a5ad1
TN		 1050 /*
1051 * Must config both number of packets and max burst settings to enable
1052 * RX and/or TX threshold.
1053 */
9af21dd6 1054 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
938a5ad1
TN		 1055 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1056 u8 rx_maxburst = dwc->rx_max_burst_prd;
1057 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1058 u8 tx_maxburst = dwc->tx_max_burst_prd;
1059
1060 if (rx_thr_num && rx_maxburst) {
1061 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1062 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1063
1064 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1065 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1066
1067 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1068 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1069
1070 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1071 }
1072
1073 if (tx_thr_num && tx_maxburst) {
1074 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1075 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1076
1077 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1078 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1079
1080 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1081 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1082
1083 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1084 }
1085 }
1086
72246da4
FB		 1087 return 0;
1088
c499ff71 1089err4:
9b9d7cdd 1090 phy_power_off(dwc->usb3_generic_phy);
c499ff71
FB		 1091
1092err3:
9b9d7cdd 1093 phy_power_off(dwc->usb2_generic_phy);
c499ff71 1094
0ffcaf37 1095err2:
c499ff71
FB		 1096 usb_phy_set_suspend(dwc->usb2_phy, 1);
1097 usb_phy_set_suspend(dwc->usb3_phy, 1);
0ffcaf37
FB		 1098
1099err1:
1100 usb_phy_shutdown(dwc->usb2_phy);
1101 usb_phy_shutdown(dwc->usb3_phy);
57303488
KVA		 1102 phy_exit(dwc->usb2_generic_phy);
1103 phy_exit(dwc->usb3_generic_phy);
0ffcaf37 1104
98112041
RQ		 1105err0a:
1106 dwc3_ulpi_exit(dwc);
1107
72246da4
FB		 1108err0:
1109 return ret;
1110}
1111
3c9f94ac 1112static int dwc3_core_get_phy(struct dwc3 *dwc)
72246da4 1113{
3c9f94ac 1114 struct device *dev = dwc->dev;
941ea361 1115 struct device_node *node = dev->of_node;
3c9f94ac 1116 int ret;
72246da4 1117
5088b6f5
KVA		 1118 if (node) {
1119 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1120 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
bb674907
FB		 1121 } else {
1122 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1123 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
5088b6f5
KVA		 1124 }
1125
d105e7f8
FB		 1126 if (IS_ERR(dwc->usb2_phy)) {
1127 ret = PTR_ERR(dwc->usb2_phy);
122f06e6
KVA		 1128 if (ret == -ENXIO || ret == -ENODEV) {
1129 dwc->usb2_phy = NULL;
1130 } else if (ret == -EPROBE_DEFER) {
d105e7f8 1131 return ret;
122f06e6
KVA		 1132 } else {
1133 dev_err(dev, "no usb2 phy configured\n");
1134 return ret;
1135 }
51e1e7bc
FB		 1136 }
1137
d105e7f8 1138 if (IS_ERR(dwc->usb3_phy)) {
315955d7 1139 ret = PTR_ERR(dwc->usb3_phy);
122f06e6
KVA		 1140 if (ret == -ENXIO || ret == -ENODEV) {
1141 dwc->usb3_phy = NULL;
1142 } else if (ret == -EPROBE_DEFER) {
d105e7f8 1143 return ret;
122f06e6
KVA		 1144 } else {
1145 dev_err(dev, "no usb3 phy configured\n");
1146 return ret;
1147 }
51e1e7bc
FB		 1148 }
1149
57303488
KVA		 1150 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1151 if (IS_ERR(dwc->usb2_generic_phy)) {
1152 ret = PTR_ERR(dwc->usb2_generic_phy);
1153 if (ret == -ENOSYS || ret == -ENODEV) {
1154 dwc->usb2_generic_phy = NULL;
1155 } else if (ret == -EPROBE_DEFER) {
1156 return ret;
1157 } else {
1158 dev_err(dev, "no usb2 phy configured\n");
1159 return ret;
1160 }
1161 }
1162
1163 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1164 if (IS_ERR(dwc->usb3_generic_phy)) {
1165 ret = PTR_ERR(dwc->usb3_generic_phy);
1166 if (ret == -ENOSYS || ret == -ENODEV) {
1167 dwc->usb3_generic_phy = NULL;
1168 } else if (ret == -EPROBE_DEFER) {
1169 return ret;
1170 } else {
1171 dev_err(dev, "no usb3 phy configured\n");
1172 return ret;
1173 }
1174 }
1175
3c9f94ac
FB		 1176 return 0;
1177}
1178
5f94adfe
FB		 1179static int dwc3_core_init_mode(struct dwc3 *dwc)
1180{
1181 struct device *dev = dwc->dev;
1182 int ret;
1183
1184 switch (dwc->dr_mode) {
1185 case USB_DR_MODE_PERIPHERAL:
41ce1456 1186 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
958d1a4c
FB		 1187
1188 if (dwc->usb2_phy)
1189 otg_set_vbus(dwc->usb2_phy->otg, false);
644cbbc3
MG		 1190 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1191 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
958d1a4c 1192
5f94adfe
FB		 1193 ret = dwc3_gadget_init(dwc);
1194 if (ret) {
9522def4
RQ		 1195 if (ret != -EPROBE_DEFER)
1196 dev_err(dev, "failed to initialize gadget\n");
5f94adfe
FB		 1197 return ret;
1198 }
1199 break;
1200 case USB_DR_MODE_HOST:
41ce1456 1201 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
958d1a4c
FB		 1202
1203 if (dwc->usb2_phy)
1204 otg_set_vbus(dwc->usb2_phy->otg, true);
644cbbc3
MG		 1205 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1206 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
958d1a4c 1207
5f94adfe
FB		 1208 ret = dwc3_host_init(dwc);
1209 if (ret) {
9522def4
RQ		 1210 if (ret != -EPROBE_DEFER)
1211 dev_err(dev, "failed to initialize host\n");
5f94adfe
FB		 1212 return ret;
1213 }
1214 break;
1215 case USB_DR_MODE_OTG:
41ce1456 1216 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
9840354f
RQ		 1217 ret = dwc3_drd_init(dwc);
1218 if (ret) {
1219 if (ret != -EPROBE_DEFER)
1220 dev_err(dev, "failed to initialize dual-role\n");
1221 return ret;
1222 }
5f94adfe
FB		 1223 break;
1224 default:
1225 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1226 return -EINVAL;
1227 }
1228
1229 return 0;
1230}
1231
1232static void dwc3_core_exit_mode(struct dwc3 *dwc)
1233{
1234 switch (dwc->dr_mode) {
1235 case USB_DR_MODE_PERIPHERAL:
1236 dwc3_gadget_exit(dwc);
1237 break;
1238 case USB_DR_MODE_HOST:
1239 dwc3_host_exit(dwc);
1240 break;
1241 case USB_DR_MODE_OTG:
9840354f 1242 dwc3_drd_exit(dwc);
5f94adfe
FB		 1243 break;
1244 default:
1245 /* do nothing */
1246 break;
1247 }
09ed259f
BL		 1248
1249 /* de-assert DRVVBUS for HOST and OTG mode */
1250 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
5f94adfe
FB		 1251}
1252
c5ac6116 1253static void dwc3_get_properties(struct dwc3 *dwc)
3c9f94ac 1254{
c5ac6116 1255 struct device *dev = dwc->dev;
80caf7d2 1256 u8 lpm_nyet_threshold;
6b6a0c9a 1257 u8 tx_de_emphasis;
460d098c 1258 u8 hird_threshold;
938a5ad1
TN		 1259 u8 rx_thr_num_pkt_prd;
1260 u8 rx_max_burst_prd;
1261 u8 tx_thr_num_pkt_prd;
1262 u8 tx_max_burst_prd;
3c9f94ac 1263
80caf7d2 1264 /* default to highest possible threshold */
8d791929 1265 lpm_nyet_threshold = 0xf;
80caf7d2 1266
6b6a0c9a
HR		 1267 /* default to -3.5dB de-emphasis */
1268 tx_de_emphasis = 1;
1269
460d098c
HR		 1270 /*
1271 * default to assert utmi_sleep_n and use maximum allowed HIRD
1272 * threshold value of 0b1100
1273 */
1274 hird_threshold = 12;
1275
63863b98 1276 dwc->maximum_speed = usb_get_maximum_speed(dev);
06e7114f 1277 dwc->dr_mode = usb_get_dr_mode(dev);
32f2ed86 1278 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
63863b98 1279
d64ff406
AB		 1280 dwc->sysdev_is_parent = device_property_read_bool(dev,
1281 "linux,sysdev_is_parent");
1282 if (dwc->sysdev_is_parent)
1283 dwc->sysdev = dwc->dev->parent;
1284 else
1285 dwc->sysdev = dwc->dev;
1286
3d128919 1287 dwc->has_lpm_erratum = device_property_read_bool(dev,
80caf7d2 1288 "snps,has-lpm-erratum");
3d128919 1289 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
80caf7d2 1290 &lpm_nyet_threshold);
3d128919 1291 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
460d098c 1292 "snps,is-utmi-l1-suspend");
3d128919 1293 device_property_read_u8(dev, "snps,hird-threshold",
460d098c 1294 &hird_threshold);
d92021f6
TN		 1295 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1296 "snps,dis-start-transfer-quirk");
3d128919 1297 dwc->usb3_lpm_capable = device_property_read_bool(dev,
eac68e8f 1298 "snps,usb3_lpm_capable");
022a0208
TN		 1299 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1300 "snps,usb2-lpm-disable");
938a5ad1
TN		 1301 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1302 &rx_thr_num_pkt_prd);
1303 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1304 &rx_max_burst_prd);
1305 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1306 &tx_thr_num_pkt_prd);
1307 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1308 &tx_max_burst_prd);
3c9f94ac 1309
3d128919 1310 dwc->disable_scramble_quirk = device_property_read_bool(dev,
3b81221a 1311 "snps,disable_scramble_quirk");
3d128919 1312 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
9a5b2f31 1313 "snps,u2exit_lfps_quirk");
3d128919 1314 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
b5a65c40 1315 "snps,u2ss_inp3_quirk");
3d128919 1316 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
df31f5b3 1317 "snps,req_p1p2p3_quirk");
3d128919 1318 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
a2a1d0f5 1319 "snps,del_p1p2p3_quirk");
3d128919 1320 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
41c06ffd 1321 "snps,del_phy_power_chg_quirk");
3d128919 1322 dwc->lfps_filter_quirk = device_property_read_bool(dev,
fb67afca 1323 "snps,lfps_filter_quirk");
3d128919 1324 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
14f4ac53 1325 "snps,rx_detect_poll_quirk");
3d128919 1326 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
59acfa20 1327 "snps,dis_u3_susphy_quirk");
3d128919 1328 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
0effe0a3 1329 "snps,dis_u2_susphy_quirk");
ec791d14
JY		 1330 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1331 "snps,dis_enblslpm_quirk");
729dcffd
AKV		 1332 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1333 "snps,dis-u1-entry-quirk");
1334 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1335 "snps,dis-u2-entry-quirk");
e58dd357
RB		 1336 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1337 "snps,dis_rxdet_inp3_quirk");
16199f33
WW		 1338 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1339 "snps,dis-u2-freeclk-exists-quirk");
00fe081d
WW		 1340 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1341 "snps,dis-del-phy-power-chg-quirk");
65db7a0c
WW		 1342 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1343 "snps,dis-tx-ipgap-linecheck-quirk");
7ba6b09f
NA		 1344 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1345 "snps,parkmode-disable-ss-quirk");
6b6a0c9a 1346
3d128919 1347 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
6b6a0c9a 1348 "snps,tx_de_emphasis_quirk");
3d128919 1349 device_property_read_u8(dev, "snps,tx_de_emphasis",
6b6a0c9a 1350 &tx_de_emphasis);
3d128919
HK		 1351 device_property_read_string(dev, "snps,hsphy_interface",
1352 &dwc->hsphy_interface);
1353 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
bcdb3272 1354 &dwc->fladj);
3d128919 1355
42bf02ec
RQ		 1356 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1357 "snps,dis_metastability_quirk");
1358
80caf7d2 1359 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
6b6a0c9a 1360 dwc->tx_de_emphasis = tx_de_emphasis;
80caf7d2 1361
16fe4f30 1362 dwc->hird_threshold = hird_threshold;
460d098c 1363
938a5ad1
TN		 1364 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1365 dwc->rx_max_burst_prd = rx_max_burst_prd;
1366
1367 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1368 dwc->tx_max_burst_prd = tx_max_burst_prd;
1369
cf40b86b
JY		 1370 dwc->imod_interval = 0;
1371}
1372
1373/* check whether the core supports IMOD */
1374bool dwc3_has_imod(struct dwc3 *dwc)
1375{
9af21dd6
TN		 1376 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1377 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1378 DWC3_IP_IS(DWC32);
c5ac6116
FB		 1379}
1380
7ac51a12
JY		 1381static void dwc3_check_params(struct dwc3 *dwc)
1382{
1383 struct device *dev = dwc->dev;
1384
cf40b86b
JY		 1385 /* Check for proper value of imod_interval */
1386 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1387 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1388 dwc->imod_interval = 0;
1389 }
1390
28632b44
JY		 1391 /*
1392 * Workaround for STAR 9000961433 which affects only version
1393 * 3.00a of the DWC_usb3 core. This prevents the controller
1394 * interrupt from being masked while handling events. IMOD
1395 * allows us to work around this issue. Enable it for the
1396 * affected version.
1397 */
1398 if (!dwc->imod_interval &&
9af21dd6 1399 DWC3_VER_IS(DWC3, 300A))
28632b44
JY		 1400 dwc->imod_interval = 1;
1401
7ac51a12
JY		 1402 /* Check the maximum_speed parameter */
1403 switch (dwc->maximum_speed) {
1404 case USB_SPEED_LOW:
1405 case USB_SPEED_FULL:
1406 case USB_SPEED_HIGH:
1407 case USB_SPEED_SUPER:
1408 case USB_SPEED_SUPER_PLUS:
1409 break;
1410 default:
1411 dev_err(dev, "invalid maximum_speed parameter %d\n",
1412 dwc->maximum_speed);
df561f66 1413 fallthrough;
7ac51a12
JY		 1414 case USB_SPEED_UNKNOWN:
1415 /* default to superspeed */
1416 dwc->maximum_speed = USB_SPEED_SUPER;
1417
1418 /*
1419 * default to superspeed plus if we are capable.
1420 */
9af21dd6 1421 if ((DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) &&
7ac51a12
JY		 1422 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1423 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1424 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1425
1426 break;
1427 }
1428}
1429
c5ac6116
FB		 1430static int dwc3_probe(struct platform_device *pdev)
1431{
1432 struct device *dev = &pdev->dev;
44feb8e6 1433 struct resource *res, dwc_res;
c5ac6116
FB		 1434 struct dwc3 *dwc;
1435
1436 int ret;
1437
1438 void __iomem *regs;
1439
1440 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1441 if (!dwc)
1442 return -ENOMEM;
1443
1444 dwc->dev = dev;
1445
1446 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1447 if (!res) {
1448 dev_err(dev, "missing memory resource\n");
1449 return -ENODEV;
1450 }
1451
1452 dwc->xhci_resources[0].start = res->start;
1453 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1454 DWC3_XHCI_REGS_END;
1455 dwc->xhci_resources[0].flags = res->flags;
1456 dwc->xhci_resources[0].name = res->name;
1457
c5ac6116
FB		 1458 /*
1459 * Request memory region but exclude xHCI regs,
1460 * since it will be requested by the xhci-plat driver.
1461 */
44feb8e6
MY		 1462 dwc_res = *res;
1463 dwc_res.start += DWC3_GLOBALS_REGS_START;
1464
1465 regs = devm_ioremap_resource(dev, &dwc_res);
1466 if (IS_ERR(regs))
1467 return PTR_ERR(regs);
c5ac6116
FB		 1468
1469 dwc->regs = regs;
44feb8e6 1470 dwc->regs_size = resource_size(&dwc_res);
c5ac6116
FB		 1471
1472 dwc3_get_properties(dwc);
1473
4a1d042a 1474 dwc->reset = devm_reset_control_array_get(dev, true, true);
fe8abf33
MY		 1475 if (IS_ERR(dwc->reset))
1476 return PTR_ERR(dwc->reset);
1477
61527777 1478 if (dev->of_node) {
0d3a9708 1479 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
61527777
HG		 1480 if (ret == -EPROBE_DEFER)
1481 return ret;
1482 /*
1483 * Clocks are optional, but new DT platforms should support all
1484 * clocks as required by the DT-binding.
1485 */
0d3a9708 1486 if (ret < 0)
61527777 1487 dwc->num_clks = 0;
0d3a9708
JS		 1488 else
1489 dwc->num_clks = ret;
1490
61527777 1491 }
fe8abf33
MY		 1492
1493 ret = reset_control_deassert(dwc->reset);
1494 if (ret)
03bf32bb 1495 return ret;
fe8abf33 1496
240b65dc 1497 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
fe8abf33
MY		 1498 if (ret)
1499 goto assert_reset;
1500
dc1b5d9a
EBS		 1501 if (!dwc3_core_is_valid(dwc)) {
1502 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1503 ret = -ENODEV;
1504 goto disable_clks;
1505 }
1506
6c89cce0 1507 platform_set_drvdata(pdev, dwc);
2917e718 1508 dwc3_cache_hwparams(dwc);
6c89cce0 1509
72246da4 1510 spin_lock_init(&dwc->lock);
72246da4 1511
fc8bb91b
FB		 1512 pm_runtime_set_active(dev);
1513 pm_runtime_use_autosuspend(dev);
1514 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
802ca850 1515 pm_runtime_enable(dev);
32808237
RQ		 1516 ret = pm_runtime_get_sync(dev);
1517 if (ret < 0)
1518 goto err1;
1519
802ca850 1520 pm_runtime_forbid(dev);
72246da4 1521
3921426b
FB		 1522 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1523 if (ret) {
1524 dev_err(dwc->dev, "failed to allocate event buffers\n");
1525 ret = -ENOMEM;
32808237 1526 goto err2;
3921426b
FB		 1527 }
1528
9d6173e1
TN		 1529 ret = dwc3_get_dr_mode(dwc);
1530 if (ret)
1531 goto err3;
32a4a135 1532
c499ff71
FB		 1533 ret = dwc3_alloc_scratch_buffers(dwc);
1534 if (ret)
32808237 1535 goto err3;
c499ff71 1536
72246da4
FB		 1537 ret = dwc3_core_init(dwc);
1538 if (ret) {
408d3ba0
BN		 1539 if (ret != -EPROBE_DEFER)
1540 dev_err(dev, "failed to initialize core: %d\n", ret);
32808237 1541 goto err4;
72246da4
FB		 1542 }
1543
7ac51a12 1544 dwc3_check_params(dwc);
2c7f1bd9 1545
5f94adfe
FB		 1546 ret = dwc3_core_init_mode(dwc);
1547 if (ret)
32808237 1548 goto err5;
72246da4 1549
4e9f3118 1550 dwc3_debugfs_init(dwc);
fc8bb91b 1551 pm_runtime_put(dev);
72246da4
FB		 1552
1553 return 0;
1554
32808237 1555err5:
c499ff71 1556 dwc3_event_buffers_cleanup(dwc);
08fd9a82 1557 dwc3_ulpi_exit(dwc);
57303488 1558
32808237 1559err4:
c499ff71 1560 dwc3_free_scratch_buffers(dwc);
72246da4 1561
32808237 1562err3:
3921426b
FB		 1563 dwc3_free_event_buffers(dwc);
1564
32808237
RQ		 1565err2:
1566 pm_runtime_allow(&pdev->dev);
1567
1568err1:
1569 pm_runtime_put_sync(&pdev->dev);
1570 pm_runtime_disable(&pdev->dev);
1571
dc1b5d9a 1572disable_clks:
240b65dc 1573 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
fe8abf33
MY		 1574assert_reset:
1575 reset_control_assert(dwc->reset);
fe8abf33 1576
72246da4
FB		 1577 return ret;
1578}
1579
fb4e98ab 1580static int dwc3_remove(struct platform_device *pdev)
72246da4 1581{
72246da4 1582 struct dwc3 *dwc = platform_get_drvdata(pdev);
3da1f6ee 1583
fc8bb91b 1584 pm_runtime_get_sync(&pdev->dev);
72246da4 1585
dc99f16f
FB		 1586 dwc3_debugfs_exit(dwc);
1587 dwc3_core_exit_mode(dwc);
8ba007a9 1588
72246da4 1589 dwc3_core_exit(dwc);
88bc9d19 1590 dwc3_ulpi_exit(dwc);
72246da4 1591
16b972a5 1592 pm_runtime_put_sync(&pdev->dev);
fc8bb91b 1593 pm_runtime_allow(&pdev->dev);
72246da4
FB		 1594 pm_runtime_disable(&pdev->dev);
1595
fc8bb91b
FB		 1596 dwc3_free_event_buffers(dwc);
1597 dwc3_free_scratch_buffers(dwc);
1598
72246da4
FB		 1599 return 0;
1600}
1601
fc8bb91b 1602#ifdef CONFIG_PM
fe8abf33
MY		 1603static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1604{
1605 int ret;
1606
1607 ret = reset_control_deassert(dwc->reset);
1608 if (ret)
1609 return ret;
1610
240b65dc 1611 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
fe8abf33
MY		 1612 if (ret)
1613 goto assert_reset;
1614
fe8abf33
MY		 1615 ret = dwc3_core_init(dwc);
1616 if (ret)
1617 goto disable_clks;
1618
1619 return 0;
1620
1621disable_clks:
240b65dc 1622 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
fe8abf33
MY		 1623assert_reset:
1624 reset_control_assert(dwc->reset);
1625
1626 return ret;
1627}
1628
c4a5153e 1629static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
7415f17c 1630{
fc8bb91b 1631 unsigned long flags;
bcb12877 1632 u32 reg;
7415f17c 1633
689bf72c
MG		 1634 switch (dwc->current_dr_role) {
1635 case DWC3_GCTL_PRTCAP_DEVICE:
0227cc84
LJ		 1636 if (pm_runtime_suspended(dwc->dev))
1637 break;
fc8bb91b 1638 spin_lock_irqsave(&dwc->lock, flags);
7415f17c 1639 dwc3_gadget_suspend(dwc);
fc8bb91b 1640 spin_unlock_irqrestore(&dwc->lock, flags);
41a91c60 1641 synchronize_irq(dwc->irq_gadget);
689bf72c 1642 dwc3_core_exit(dwc);
51f5d49a 1643 break;
689bf72c 1644 case DWC3_GCTL_PRTCAP_HOST:
bcb12877 1645 if (!PMSG_IS_AUTO(msg)) {
c4a5153e 1646 dwc3_core_exit(dwc);
bcb12877
MG		 1647 break;
1648 }
1649
1650 /* Let controller to suspend HSPHY before PHY driver suspends */
1651 if (dwc->dis_u2_susphy_quirk ||
1652 dwc->dis_enblslpm_quirk) {
1653 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1654 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1655 DWC3_GUSB2PHYCFG_SUSPHY;
1656 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1657
1658 /* Give some time for USB2 PHY to suspend */
1659 usleep_range(5000, 6000);
1660 }
1661
1662 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1663 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
c4a5153e 1664 break;
f09cc79b
RQ		 1665 case DWC3_GCTL_PRTCAP_OTG:
1666 /* do nothing during runtime_suspend */
1667 if (PMSG_IS_AUTO(msg))
1668 break;
1669
1670 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1671 spin_lock_irqsave(&dwc->lock, flags);
1672 dwc3_gadget_suspend(dwc);
1673 spin_unlock_irqrestore(&dwc->lock, flags);
41a91c60 1674 synchronize_irq(dwc->irq_gadget);
f09cc79b
RQ		 1675 }
1676
1677 dwc3_otg_exit(dwc);
1678 dwc3_core_exit(dwc);
1679 break;
7415f17c 1680 default:
51f5d49a 1681 /* do nothing */
7415f17c
FB		 1682 break;
1683 }
1684
7415f17c
FB		 1685 return 0;
1686}
1687
c4a5153e 1688static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
7415f17c 1689{
fc8bb91b 1690 unsigned long flags;
57303488 1691 int ret;
bcb12877 1692 u32 reg;
7415f17c 1693
689bf72c
MG		 1694 switch (dwc->current_dr_role) {
1695 case DWC3_GCTL_PRTCAP_DEVICE:
fe8abf33 1696 ret = dwc3_core_init_for_resume(dwc);
689bf72c
MG		 1697 if (ret)
1698 return ret;
5c4ad318 1699
7d11c3ac 1700 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
fc8bb91b 1701 spin_lock_irqsave(&dwc->lock, flags);
7415f17c 1702 dwc3_gadget_resume(dwc);
fc8bb91b 1703 spin_unlock_irqrestore(&dwc->lock, flags);
689bf72c
MG		 1704 break;
1705 case DWC3_GCTL_PRTCAP_HOST:
c4a5153e 1706 if (!PMSG_IS_AUTO(msg)) {
fe8abf33 1707 ret = dwc3_core_init_for_resume(dwc);
c4a5153e
MG		 1708 if (ret)
1709 return ret;
7d11c3ac 1710 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
bcb12877 1711 break;
c4a5153e 1712 }
bcb12877
MG		 1713 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1714 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1715 if (dwc->dis_u2_susphy_quirk)
1716 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1717
1718 if (dwc->dis_enblslpm_quirk)
1719 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1720
1721 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1722
1723 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1724 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
f09cc79b
RQ		 1725 break;
1726 case DWC3_GCTL_PRTCAP_OTG:
1727 /* nothing to do on runtime_resume */
1728 if (PMSG_IS_AUTO(msg))
1729 break;
1730
1731 ret = dwc3_core_init(dwc);
1732 if (ret)
1733 return ret;
1734
1735 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1736
1737 dwc3_otg_init(dwc);
1738 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1739 dwc3_otg_host_init(dwc);
1740 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1741 spin_lock_irqsave(&dwc->lock, flags);
1742 dwc3_gadget_resume(dwc);
1743 spin_unlock_irqrestore(&dwc->lock, flags);
c4a5153e 1744 }
f09cc79b 1745
c4a5153e 1746 break;
7415f17c
FB		 1747 default:
1748 /* do nothing */
1749 break;
1750 }
1751
fc8bb91b
FB		 1752 return 0;
1753}
1754
1755static int dwc3_runtime_checks(struct dwc3 *dwc)
1756{
689bf72c 1757 switch (dwc->current_dr_role) {
c4a5153e 1758 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 1759 if (dwc->connected)
1760 return -EBUSY;
1761 break;
c4a5153e 1762 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 1763 default:
1764 /* do nothing */
1765 break;
1766 }
1767
1768 return 0;
1769}
1770
1771static int dwc3_runtime_suspend(struct device *dev)
1772{
1773 struct dwc3 *dwc = dev_get_drvdata(dev);
1774 int ret;
1775
1776 if (dwc3_runtime_checks(dwc))
1777 return -EBUSY;
1778
c4a5153e 1779 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
fc8bb91b
FB		 1780 if (ret)
1781 return ret;
1782
1783 device_init_wakeup(dev, true);
1784
1785 return 0;
1786}
1787
1788static int dwc3_runtime_resume(struct device *dev)
1789{
1790 struct dwc3 *dwc = dev_get_drvdata(dev);
1791 int ret;
1792
1793 device_init_wakeup(dev, false);
1794
c4a5153e 1795 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
fc8bb91b
FB		 1796 if (ret)
1797 return ret;
1798
689bf72c
MG		 1799 switch (dwc->current_dr_role) {
1800 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 1801 dwc3_gadget_process_pending_events(dwc);
1802 break;
689bf72c 1803 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 1804 default:
1805 /* do nothing */
1806 break;
1807 }
1808
1809 pm_runtime_mark_last_busy(dev);
1810
1811 return 0;
1812}
1813
1814static int dwc3_runtime_idle(struct device *dev)
1815{
1816 struct dwc3 *dwc = dev_get_drvdata(dev);
1817
689bf72c
MG		 1818 switch (dwc->current_dr_role) {
1819 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 1820 if (dwc3_runtime_checks(dwc))
1821 return -EBUSY;
1822 break;
689bf72c 1823 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 1824 default:
1825 /* do nothing */
1826 break;
1827 }
1828
1829 pm_runtime_mark_last_busy(dev);
1830 pm_runtime_autosuspend(dev);
1831
1832 return 0;
1833}
1834#endif /* CONFIG_PM */
1835
1836#ifdef CONFIG_PM_SLEEP
1837static int dwc3_suspend(struct device *dev)
1838{
1839 struct dwc3 *dwc = dev_get_drvdata(dev);
1840 int ret;
1841
c4a5153e 1842 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
fc8bb91b
FB		 1843 if (ret)
1844 return ret;
1845
1846 pinctrl_pm_select_sleep_state(dev);
1847
1848 return 0;
1849}
1850
1851static int dwc3_resume(struct device *dev)
1852{
1853 struct dwc3 *dwc = dev_get_drvdata(dev);
1854 int ret;
1855
1856 pinctrl_pm_select_default_state(dev);
1857
c4a5153e 1858 ret = dwc3_resume_common(dwc, PMSG_RESUME);
fc8bb91b
FB		 1859 if (ret)
1860 return ret;
1861
7415f17c
FB		 1862 pm_runtime_disable(dev);
1863 pm_runtime_set_active(dev);
1864 pm_runtime_enable(dev);
1865
1866 return 0;
1867}
7f370ed0 1868#endif /* CONFIG_PM_SLEEP */
7415f17c
FB		 1869
1870static const struct dev_pm_ops dwc3_dev_pm_ops = {
7415f17c 1871 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
fc8bb91b
FB		 1872 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1873 dwc3_runtime_idle)
7415f17c
FB		 1874};
1875
5088b6f5
KVA		 1876#ifdef CONFIG_OF
1877static const struct of_device_id of_dwc3_match[] = {
22a5aa17
FB		 1878 {
1879 .compatible = "snps,dwc3"
1880 },
5088b6f5
KVA		 1881 {
1882 .compatible = "synopsys,dwc3"
1883 },
1884 { },
1885};
1886MODULE_DEVICE_TABLE(of, of_dwc3_match);
1887#endif
1888
404905a6
HK		 1889#ifdef CONFIG_ACPI
1890
1891#define ACPI_ID_INTEL_BSW "808622B7"
1892
1893static const struct acpi_device_id dwc3_acpi_match[] = {
1894 { ACPI_ID_INTEL_BSW, 0 },
1895 { },
1896};
1897MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1898#endif
1899
72246da4
FB		 1900static struct platform_driver dwc3_driver = {
1901 .probe = dwc3_probe,
7690417d 1902 .remove = dwc3_remove,
72246da4
FB		 1903 .driver = {
1904 .name = "dwc3",
5088b6f5 1905 .of_match_table = of_match_ptr(of_dwc3_match),
404905a6 1906 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
7f370ed0 1907 .pm = &dwc3_dev_pm_ops,
72246da4 1908 },
72246da4
FB		 1909};
1910
b1116dcc
TK		 1911module_platform_driver(dwc3_driver);
1912
7ae4fc4d 1913MODULE_ALIAS("platform:dwc3");
72246da4 1914MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
5945f789 1915MODULE_LICENSE("GPL v2");
72246da4 1916MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux 6.x block layer and io_uring tree(s)