Commit | Line | Data |
---|---|---|
5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
72246da4 FB |
2 | /** |
3 | * core.c - DesignWare USB3 DRD Controller Core file | |
4 | * | |
5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
6 | * |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
72246da4 FB |
9 | */ |
10 | ||
fe8abf33 | 11 | #include <linux/clk.h> |
fa0ea13e | 12 | #include <linux/version.h> |
a72e658b | 13 | #include <linux/module.h> |
72246da4 FB |
14 | #include <linux/kernel.h> |
15 | #include <linux/slab.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/pm_runtime.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/list.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/dma-mapping.h> | |
457e84b6 | 25 | #include <linux/of.h> |
404905a6 | 26 | #include <linux/acpi.h> |
6344475f | 27 | #include <linux/pinctrl/consumer.h> |
fe8abf33 | 28 | #include <linux/reset.h> |
72246da4 FB |
29 | |
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
f7e846f0 | 32 | #include <linux/usb/of.h> |
a45c82b8 | 33 | #include <linux/usb/otg.h> |
72246da4 FB |
34 | |
35 | #include "core.h" | |
36 | #include "gadget.h" | |
37 | #include "io.h" | |
38 | ||
39 | #include "debug.h" | |
40 | ||
fc8bb91b | 41 | #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ |
8300dd23 | 42 | |
9d6173e1 TN |
43 | /** |
44 | * dwc3_get_dr_mode - Validates and sets dr_mode | |
45 | * @dwc: pointer to our context structure | |
46 | */ | |
47 | static int dwc3_get_dr_mode(struct dwc3 *dwc) | |
48 | { | |
49 | enum usb_dr_mode mode; | |
50 | struct device *dev = dwc->dev; | |
51 | unsigned int hw_mode; | |
52 | ||
53 | if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) | |
54 | dwc->dr_mode = USB_DR_MODE_OTG; | |
55 | ||
56 | mode = dwc->dr_mode; | |
57 | hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); | |
58 | ||
59 | switch (hw_mode) { | |
60 | case DWC3_GHWPARAMS0_MODE_GADGET: | |
61 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { | |
62 | dev_err(dev, | |
63 | "Controller does not support host mode.\n"); | |
64 | return -EINVAL; | |
65 | } | |
66 | mode = USB_DR_MODE_PERIPHERAL; | |
67 | break; | |
68 | case DWC3_GHWPARAMS0_MODE_HOST: | |
69 | if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { | |
70 | dev_err(dev, | |
71 | "Controller does not support device mode.\n"); | |
72 | return -EINVAL; | |
73 | } | |
74 | mode = USB_DR_MODE_HOST; | |
75 | break; | |
76 | default: | |
77 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) | |
78 | mode = USB_DR_MODE_HOST; | |
79 | else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) | |
80 | mode = USB_DR_MODE_PERIPHERAL; | |
a7700468 TN |
81 | |
82 | /* | |
89a9cc47 TN |
83 | * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG |
84 | * mode. If the controller supports DRD but the dr_mode is not | |
85 | * specified or set to OTG, then set the mode to peripheral. | |
a7700468 | 86 | */ |
89a9cc47 TN |
87 | if (mode == USB_DR_MODE_OTG && |
88 | dwc->revision >= DWC3_REVISION_330A) | |
a7700468 | 89 | mode = USB_DR_MODE_PERIPHERAL; |
9d6173e1 TN |
90 | } |
91 | ||
92 | if (mode != dwc->dr_mode) { | |
93 | dev_warn(dev, | |
94 | "Configuration mismatch. dr_mode forced to %s\n", | |
95 | mode == USB_DR_MODE_HOST ? "host" : "gadget"); | |
96 | ||
97 | dwc->dr_mode = mode; | |
98 | } | |
99 | ||
100 | return 0; | |
101 | } | |
102 | ||
f09cc79b | 103 | void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) |
3140e8cb SAS |
104 | { |
105 | u32 reg; | |
106 | ||
107 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
108 | reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); | |
109 | reg |= DWC3_GCTL_PRTCAPDIR(mode); | |
110 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
c4a5153e MG |
111 | |
112 | dwc->current_dr_role = mode; | |
41ce1456 RQ |
113 | } |
114 | ||
115 | static void __dwc3_set_mode(struct work_struct *work) | |
116 | { | |
117 | struct dwc3 *dwc = work_to_dwc(work); | |
118 | unsigned long flags; | |
119 | int ret; | |
120 | ||
f09cc79b | 121 | if (dwc->dr_mode != USB_DR_MODE_OTG) |
41ce1456 RQ |
122 | return; |
123 | ||
f09cc79b RQ |
124 | if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) |
125 | dwc3_otg_update(dwc, 0); | |
126 | ||
41ce1456 RQ |
127 | if (!dwc->desired_dr_role) |
128 | return; | |
129 | ||
130 | if (dwc->desired_dr_role == dwc->current_dr_role) | |
131 | return; | |
132 | ||
f09cc79b | 133 | if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) |
41ce1456 RQ |
134 | return; |
135 | ||
136 | switch (dwc->current_dr_role) { | |
137 | case DWC3_GCTL_PRTCAP_HOST: | |
138 | dwc3_host_exit(dwc); | |
139 | break; | |
140 | case DWC3_GCTL_PRTCAP_DEVICE: | |
141 | dwc3_gadget_exit(dwc); | |
142 | dwc3_event_buffers_cleanup(dwc); | |
143 | break; | |
f09cc79b RQ |
144 | case DWC3_GCTL_PRTCAP_OTG: |
145 | dwc3_otg_exit(dwc); | |
146 | spin_lock_irqsave(&dwc->lock, flags); | |
147 | dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; | |
148 | spin_unlock_irqrestore(&dwc->lock, flags); | |
149 | dwc3_otg_update(dwc, 1); | |
150 | break; | |
41ce1456 RQ |
151 | default: |
152 | break; | |
153 | } | |
154 | ||
155 | spin_lock_irqsave(&dwc->lock, flags); | |
156 | ||
157 | dwc3_set_prtcap(dwc, dwc->desired_dr_role); | |
6b3261a2 | 158 | |
41ce1456 RQ |
159 | spin_unlock_irqrestore(&dwc->lock, flags); |
160 | ||
161 | switch (dwc->desired_dr_role) { | |
162 | case DWC3_GCTL_PRTCAP_HOST: | |
163 | ret = dwc3_host_init(dwc); | |
958d1a4c | 164 | if (ret) { |
41ce1456 | 165 | dev_err(dwc->dev, "failed to initialize host\n"); |
958d1a4c FB |
166 | } else { |
167 | if (dwc->usb2_phy) | |
168 | otg_set_vbus(dwc->usb2_phy->otg, true); | |
644cbbc3 MG |
169 | phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); |
170 | phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); | |
d8c80bb3 | 171 | phy_calibrate(dwc->usb2_generic_phy); |
958d1a4c | 172 | } |
41ce1456 RQ |
173 | break; |
174 | case DWC3_GCTL_PRTCAP_DEVICE: | |
175 | dwc3_event_buffers_setup(dwc); | |
958d1a4c FB |
176 | |
177 | if (dwc->usb2_phy) | |
178 | otg_set_vbus(dwc->usb2_phy->otg, false); | |
644cbbc3 MG |
179 | phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); |
180 | phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); | |
958d1a4c | 181 | |
41ce1456 RQ |
182 | ret = dwc3_gadget_init(dwc); |
183 | if (ret) | |
184 | dev_err(dwc->dev, "failed to initialize peripheral\n"); | |
185 | break; | |
f09cc79b RQ |
186 | case DWC3_GCTL_PRTCAP_OTG: |
187 | dwc3_otg_init(dwc); | |
188 | dwc3_otg_update(dwc, 0); | |
189 | break; | |
41ce1456 RQ |
190 | default: |
191 | break; | |
192 | } | |
f09cc79b | 193 | |
41ce1456 RQ |
194 | } |
195 | ||
196 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode) | |
197 | { | |
198 | unsigned long flags; | |
199 | ||
200 | spin_lock_irqsave(&dwc->lock, flags); | |
201 | dwc->desired_dr_role = mode; | |
202 | spin_unlock_irqrestore(&dwc->lock, flags); | |
203 | ||
084a804e | 204 | queue_work(system_freezable_wq, &dwc->drd_work); |
3140e8cb | 205 | } |
8300dd23 | 206 | |
cf6d867d FB |
207 | u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) |
208 | { | |
209 | struct dwc3 *dwc = dep->dwc; | |
210 | u32 reg; | |
211 | ||
212 | dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, | |
213 | DWC3_GDBGFIFOSPACE_NUM(dep->number) | | |
214 | DWC3_GDBGFIFOSPACE_TYPE(type)); | |
215 | ||
216 | reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); | |
217 | ||
218 | return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); | |
219 | } | |
220 | ||
72246da4 FB |
221 | /** |
222 | * dwc3_core_soft_reset - Issues core soft reset and PHY reset | |
223 | * @dwc: pointer to our context structure | |
224 | */ | |
57303488 | 225 | static int dwc3_core_soft_reset(struct dwc3 *dwc) |
72246da4 FB |
226 | { |
227 | u32 reg; | |
f59dcab1 | 228 | int retries = 1000; |
57303488 | 229 | int ret; |
72246da4 | 230 | |
51e1e7bc FB |
231 | usb_phy_init(dwc->usb2_phy); |
232 | usb_phy_init(dwc->usb3_phy); | |
57303488 KVA |
233 | ret = phy_init(dwc->usb2_generic_phy); |
234 | if (ret < 0) | |
235 | return ret; | |
236 | ||
237 | ret = phy_init(dwc->usb3_generic_phy); | |
238 | if (ret < 0) { | |
239 | phy_exit(dwc->usb2_generic_phy); | |
240 | return ret; | |
241 | } | |
72246da4 | 242 | |
f59dcab1 FB |
243 | /* |
244 | * We're resetting only the device side because, if we're in host mode, | |
245 | * XHCI driver will reset the host block. If dwc3 was configured for | |
246 | * host-only mode, then we can return early. | |
247 | */ | |
c4a5153e | 248 | if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) |
f59dcab1 | 249 | return 0; |
72246da4 | 250 | |
f59dcab1 FB |
251 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
252 | reg |= DWC3_DCTL_CSFTRST; | |
253 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 254 | |
f59dcab1 FB |
255 | do { |
256 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
257 | if (!(reg & DWC3_DCTL_CSFTRST)) | |
fab38333 | 258 | goto done; |
45627ac6 | 259 | |
f59dcab1 FB |
260 | udelay(1); |
261 | } while (--retries); | |
57303488 | 262 | |
00b42170 BN |
263 | phy_exit(dwc->usb3_generic_phy); |
264 | phy_exit(dwc->usb2_generic_phy); | |
265 | ||
f59dcab1 | 266 | return -ETIMEDOUT; |
fab38333 TN |
267 | |
268 | done: | |
269 | /* | |
270 | * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared, | |
271 | * we must wait at least 50ms before accessing the PHY domain | |
272 | * (synchronization delay). DWC_usb31 programming guide section 1.3.2. | |
273 | */ | |
274 | if (dwc3_is_usb31(dwc)) | |
275 | msleep(50); | |
276 | ||
277 | return 0; | |
72246da4 FB |
278 | } |
279 | ||
fe8abf33 MY |
280 | static const struct clk_bulk_data dwc3_core_clks[] = { |
281 | { .id = "ref" }, | |
282 | { .id = "bus_early" }, | |
283 | { .id = "suspend" }, | |
284 | }; | |
285 | ||
db2be4e9 NB |
286 | /* |
287 | * dwc3_frame_length_adjustment - Adjusts frame length if required | |
288 | * @dwc3: Pointer to our controller context structure | |
db2be4e9 | 289 | */ |
bcdb3272 | 290 | static void dwc3_frame_length_adjustment(struct dwc3 *dwc) |
db2be4e9 NB |
291 | { |
292 | u32 reg; | |
293 | u32 dft; | |
294 | ||
295 | if (dwc->revision < DWC3_REVISION_250A) | |
296 | return; | |
297 | ||
bcdb3272 | 298 | if (dwc->fladj == 0) |
db2be4e9 NB |
299 | return; |
300 | ||
301 | reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); | |
302 | dft = reg & DWC3_GFLADJ_30MHZ_MASK; | |
bcdb3272 | 303 | if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj, |
db2be4e9 NB |
304 | "request value same as default, ignoring\n")) { |
305 | reg &= ~DWC3_GFLADJ_30MHZ_MASK; | |
bcdb3272 | 306 | reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; |
db2be4e9 NB |
307 | dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); |
308 | } | |
309 | } | |
310 | ||
72246da4 FB |
311 | /** |
312 | * dwc3_free_one_event_buffer - Frees one event buffer | |
313 | * @dwc: Pointer to our controller context structure | |
314 | * @evt: Pointer to event buffer to be freed | |
315 | */ | |
316 | static void dwc3_free_one_event_buffer(struct dwc3 *dwc, | |
317 | struct dwc3_event_buffer *evt) | |
318 | { | |
d64ff406 | 319 | dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); |
72246da4 FB |
320 | } |
321 | ||
322 | /** | |
1d046793 | 323 | * dwc3_alloc_one_event_buffer - Allocates one event buffer structure |
72246da4 FB |
324 | * @dwc: Pointer to our controller context structure |
325 | * @length: size of the event buffer | |
326 | * | |
1d046793 | 327 | * Returns a pointer to the allocated event buffer structure on success |
72246da4 FB |
328 | * otherwise ERR_PTR(errno). |
329 | */ | |
67d0b500 FB |
330 | static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, |
331 | unsigned length) | |
72246da4 FB |
332 | { |
333 | struct dwc3_event_buffer *evt; | |
334 | ||
380f0d28 | 335 | evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); |
72246da4 FB |
336 | if (!evt) |
337 | return ERR_PTR(-ENOMEM); | |
338 | ||
339 | evt->dwc = dwc; | |
340 | evt->length = length; | |
d9fa4c63 JY |
341 | evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); |
342 | if (!evt->cache) | |
343 | return ERR_PTR(-ENOMEM); | |
344 | ||
d64ff406 | 345 | evt->buf = dma_alloc_coherent(dwc->sysdev, length, |
72246da4 | 346 | &evt->dma, GFP_KERNEL); |
e32672f0 | 347 | if (!evt->buf) |
72246da4 | 348 | return ERR_PTR(-ENOMEM); |
72246da4 FB |
349 | |
350 | return evt; | |
351 | } | |
352 | ||
353 | /** | |
354 | * dwc3_free_event_buffers - frees all allocated event buffers | |
355 | * @dwc: Pointer to our controller context structure | |
356 | */ | |
357 | static void dwc3_free_event_buffers(struct dwc3 *dwc) | |
358 | { | |
359 | struct dwc3_event_buffer *evt; | |
72246da4 | 360 | |
696c8b12 | 361 | evt = dwc->ev_buf; |
660e9bde FB |
362 | if (evt) |
363 | dwc3_free_one_event_buffer(dwc, evt); | |
72246da4 FB |
364 | } |
365 | ||
366 | /** | |
367 | * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length | |
1d046793 | 368 | * @dwc: pointer to our controller context structure |
72246da4 FB |
369 | * @length: size of event buffer |
370 | * | |
1d046793 | 371 | * Returns 0 on success otherwise negative errno. In the error case, dwc |
72246da4 FB |
372 | * may contain some buffers allocated but not all which were requested. |
373 | */ | |
41ac7b3a | 374 | static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) |
72246da4 | 375 | { |
660e9bde | 376 | struct dwc3_event_buffer *evt; |
72246da4 | 377 | |
660e9bde FB |
378 | evt = dwc3_alloc_one_event_buffer(dwc, length); |
379 | if (IS_ERR(evt)) { | |
380 | dev_err(dwc->dev, "can't allocate event buffer\n"); | |
381 | return PTR_ERR(evt); | |
72246da4 | 382 | } |
696c8b12 | 383 | dwc->ev_buf = evt; |
72246da4 FB |
384 | |
385 | return 0; | |
386 | } | |
387 | ||
388 | /** | |
389 | * dwc3_event_buffers_setup - setup our allocated event buffers | |
1d046793 | 390 | * @dwc: pointer to our controller context structure |
72246da4 FB |
391 | * |
392 | * Returns 0 on success otherwise negative errno. | |
393 | */ | |
f09cc79b | 394 | int dwc3_event_buffers_setup(struct dwc3 *dwc) |
72246da4 FB |
395 | { |
396 | struct dwc3_event_buffer *evt; | |
72246da4 | 397 | |
696c8b12 | 398 | evt = dwc->ev_buf; |
660e9bde | 399 | evt->lpos = 0; |
660e9bde FB |
400 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), |
401 | lower_32_bits(evt->dma)); | |
402 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), | |
403 | upper_32_bits(evt->dma)); | |
404 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), | |
405 | DWC3_GEVNTSIZ_SIZE(evt->length)); | |
406 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); | |
72246da4 FB |
407 | |
408 | return 0; | |
409 | } | |
410 | ||
f09cc79b | 411 | void dwc3_event_buffers_cleanup(struct dwc3 *dwc) |
72246da4 FB |
412 | { |
413 | struct dwc3_event_buffer *evt; | |
72246da4 | 414 | |
696c8b12 | 415 | evt = dwc->ev_buf; |
7acd85e0 | 416 | |
660e9bde | 417 | evt->lpos = 0; |
7acd85e0 | 418 | |
660e9bde FB |
419 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); |
420 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); | |
421 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK | |
422 | | DWC3_GEVNTSIZ_SIZE(0)); | |
423 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); | |
72246da4 FB |
424 | } |
425 | ||
0ffcaf37 FB |
426 | static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) |
427 | { | |
428 | if (!dwc->has_hibernation) | |
429 | return 0; | |
430 | ||
431 | if (!dwc->nr_scratch) | |
432 | return 0; | |
433 | ||
434 | dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, | |
435 | DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); | |
436 | if (!dwc->scratchbuf) | |
437 | return -ENOMEM; | |
438 | ||
439 | return 0; | |
440 | } | |
441 | ||
442 | static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) | |
443 | { | |
444 | dma_addr_t scratch_addr; | |
445 | u32 param; | |
446 | int ret; | |
447 | ||
448 | if (!dwc->has_hibernation) | |
449 | return 0; | |
450 | ||
451 | if (!dwc->nr_scratch) | |
452 | return 0; | |
453 | ||
454 | /* should never fall here */ | |
455 | if (!WARN_ON(dwc->scratchbuf)) | |
456 | return 0; | |
457 | ||
d64ff406 | 458 | scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, |
0ffcaf37 FB |
459 | dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, |
460 | DMA_BIDIRECTIONAL); | |
d64ff406 AB |
461 | if (dma_mapping_error(dwc->sysdev, scratch_addr)) { |
462 | dev_err(dwc->sysdev, "failed to map scratch buffer\n"); | |
0ffcaf37 FB |
463 | ret = -EFAULT; |
464 | goto err0; | |
465 | } | |
466 | ||
467 | dwc->scratch_addr = scratch_addr; | |
468 | ||
469 | param = lower_32_bits(scratch_addr); | |
470 | ||
471 | ret = dwc3_send_gadget_generic_command(dwc, | |
472 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); | |
473 | if (ret < 0) | |
474 | goto err1; | |
475 | ||
476 | param = upper_32_bits(scratch_addr); | |
477 | ||
478 | ret = dwc3_send_gadget_generic_command(dwc, | |
479 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); | |
480 | if (ret < 0) | |
481 | goto err1; | |
482 | ||
483 | return 0; | |
484 | ||
485 | err1: | |
d64ff406 | 486 | dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * |
0ffcaf37 FB |
487 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); |
488 | ||
489 | err0: | |
490 | return ret; | |
491 | } | |
492 | ||
493 | static void dwc3_free_scratch_buffers(struct dwc3 *dwc) | |
494 | { | |
495 | if (!dwc->has_hibernation) | |
496 | return; | |
497 | ||
498 | if (!dwc->nr_scratch) | |
499 | return; | |
500 | ||
501 | /* should never fall here */ | |
502 | if (!WARN_ON(dwc->scratchbuf)) | |
503 | return; | |
504 | ||
d64ff406 | 505 | dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * |
0ffcaf37 FB |
506 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); |
507 | kfree(dwc->scratchbuf); | |
508 | } | |
509 | ||
789451f6 FB |
510 | static void dwc3_core_num_eps(struct dwc3 *dwc) |
511 | { | |
512 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
513 | ||
47d3946e | 514 | dwc->num_eps = DWC3_NUM_EPS(parms); |
789451f6 FB |
515 | } |
516 | ||
41ac7b3a | 517 | static void dwc3_cache_hwparams(struct dwc3 *dwc) |
26ceca97 FB |
518 | { |
519 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
520 | ||
521 | parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); | |
522 | parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); | |
523 | parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); | |
524 | parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); | |
525 | parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); | |
526 | parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); | |
527 | parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); | |
528 | parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); | |
529 | parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); | |
530 | } | |
531 | ||
98112041 RQ |
532 | static int dwc3_core_ulpi_init(struct dwc3 *dwc) |
533 | { | |
534 | int intf; | |
535 | int ret = 0; | |
536 | ||
537 | intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); | |
538 | ||
539 | if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || | |
540 | (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && | |
541 | dwc->hsphy_interface && | |
542 | !strncmp(dwc->hsphy_interface, "ulpi", 4))) | |
543 | ret = dwc3_ulpi_init(dwc); | |
544 | ||
545 | return ret; | |
546 | } | |
547 | ||
b5a65c40 HR |
548 | /** |
549 | * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core | |
550 | * @dwc: Pointer to our controller context structure | |
88bc9d19 HK |
551 | * |
552 | * Returns 0 on success. The USB PHY interfaces are configured but not | |
553 | * initialized. The PHY interfaces and the PHYs get initialized together with | |
554 | * the core in dwc3_core_init. | |
b5a65c40 | 555 | */ |
88bc9d19 | 556 | static int dwc3_phy_setup(struct dwc3 *dwc) |
b5a65c40 HR |
557 | { |
558 | u32 reg; | |
559 | ||
560 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
561 | ||
1966b865 FB |
562 | /* |
563 | * Make sure UX_EXIT_PX is cleared as that causes issues with some | |
564 | * PHYs. Also, this bit is not supposed to be used in normal operation. | |
565 | */ | |
566 | reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; | |
567 | ||
2164a476 HR |
568 | /* |
569 | * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY | |
570 | * to '0' during coreConsultant configuration. So default value | |
571 | * will be '0' when the core is reset. Application needs to set it | |
572 | * to '1' after the core initialization is completed. | |
573 | */ | |
574 | if (dwc->revision > DWC3_REVISION_194A) | |
575 | reg |= DWC3_GUSB3PIPECTL_SUSPHY; | |
576 | ||
b5a65c40 HR |
577 | if (dwc->u2ss_inp3_quirk) |
578 | reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; | |
579 | ||
e58dd357 RB |
580 | if (dwc->dis_rxdet_inp3_quirk) |
581 | reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; | |
582 | ||
df31f5b3 HR |
583 | if (dwc->req_p1p2p3_quirk) |
584 | reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; | |
585 | ||
a2a1d0f5 HR |
586 | if (dwc->del_p1p2p3_quirk) |
587 | reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; | |
588 | ||
41c06ffd HR |
589 | if (dwc->del_phy_power_chg_quirk) |
590 | reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; | |
591 | ||
fb67afca HR |
592 | if (dwc->lfps_filter_quirk) |
593 | reg |= DWC3_GUSB3PIPECTL_LFPSFILT; | |
594 | ||
14f4ac53 HR |
595 | if (dwc->rx_detect_poll_quirk) |
596 | reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; | |
597 | ||
6b6a0c9a HR |
598 | if (dwc->tx_de_emphasis_quirk) |
599 | reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); | |
600 | ||
cd72f890 | 601 | if (dwc->dis_u3_susphy_quirk) |
59acfa20 HR |
602 | reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; |
603 | ||
00fe081d WW |
604 | if (dwc->dis_del_phy_power_chg_quirk) |
605 | reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; | |
606 | ||
b5a65c40 HR |
607 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); |
608 | ||
2164a476 HR |
609 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
610 | ||
3e10a2ce HK |
611 | /* Select the HS PHY interface */ |
612 | switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { | |
613 | case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: | |
43cacb03 FB |
614 | if (dwc->hsphy_interface && |
615 | !strncmp(dwc->hsphy_interface, "utmi", 4)) { | |
3e10a2ce | 616 | reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; |
88bc9d19 | 617 | break; |
43cacb03 FB |
618 | } else if (dwc->hsphy_interface && |
619 | !strncmp(dwc->hsphy_interface, "ulpi", 4)) { | |
3e10a2ce | 620 | reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; |
88bc9d19 | 621 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
3e10a2ce | 622 | } else { |
88bc9d19 HK |
623 | /* Relying on default value. */ |
624 | if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) | |
625 | break; | |
3e10a2ce HK |
626 | } |
627 | /* FALLTHROUGH */ | |
88bc9d19 | 628 | case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: |
88bc9d19 | 629 | /* FALLTHROUGH */ |
3e10a2ce HK |
630 | default: |
631 | break; | |
632 | } | |
633 | ||
32f2ed86 WW |
634 | switch (dwc->hsphy_mode) { |
635 | case USBPHY_INTERFACE_MODE_UTMI: | |
636 | reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | | |
637 | DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); | |
638 | reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | | |
639 | DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); | |
640 | break; | |
641 | case USBPHY_INTERFACE_MODE_UTMIW: | |
642 | reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | | |
643 | DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); | |
644 | reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | | |
645 | DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); | |
646 | break; | |
647 | default: | |
648 | break; | |
649 | } | |
650 | ||
2164a476 HR |
651 | /* |
652 | * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to | |
653 | * '0' during coreConsultant configuration. So default value will | |
654 | * be '0' when the core is reset. Application needs to set it to | |
655 | * '1' after the core initialization is completed. | |
656 | */ | |
657 | if (dwc->revision > DWC3_REVISION_194A) | |
658 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; | |
659 | ||
cd72f890 | 660 | if (dwc->dis_u2_susphy_quirk) |
0effe0a3 HR |
661 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; |
662 | ||
ec791d14 JY |
663 | if (dwc->dis_enblslpm_quirk) |
664 | reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; | |
eafeacf1 TN |
665 | else |
666 | reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; | |
ec791d14 | 667 | |
16199f33 WW |
668 | if (dwc->dis_u2_freeclk_exists_quirk) |
669 | reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; | |
670 | ||
2164a476 | 671 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
88bc9d19 HK |
672 | |
673 | return 0; | |
b5a65c40 HR |
674 | } |
675 | ||
c499ff71 FB |
676 | static void dwc3_core_exit(struct dwc3 *dwc) |
677 | { | |
678 | dwc3_event_buffers_cleanup(dwc); | |
679 | ||
680 | usb_phy_shutdown(dwc->usb2_phy); | |
681 | usb_phy_shutdown(dwc->usb3_phy); | |
682 | phy_exit(dwc->usb2_generic_phy); | |
683 | phy_exit(dwc->usb3_generic_phy); | |
684 | ||
685 | usb_phy_set_suspend(dwc->usb2_phy, 1); | |
686 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
687 | phy_power_off(dwc->usb2_generic_phy); | |
688 | phy_power_off(dwc->usb3_generic_phy); | |
fe8abf33 MY |
689 | clk_bulk_disable(dwc->num_clks, dwc->clks); |
690 | clk_bulk_unprepare(dwc->num_clks, dwc->clks); | |
691 | reset_control_assert(dwc->reset); | |
c499ff71 FB |
692 | } |
693 | ||
0759956f | 694 | static bool dwc3_core_is_valid(struct dwc3 *dwc) |
72246da4 | 695 | { |
0759956f | 696 | u32 reg; |
72246da4 | 697 | |
7650bd74 | 698 | reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); |
0759956f | 699 | |
7650bd74 | 700 | /* This should read as U3 followed by revision number */ |
690fb371 JY |
701 | if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { |
702 | /* Detected DWC_usb3 IP */ | |
703 | dwc->revision = reg; | |
704 | } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { | |
705 | /* Detected DWC_usb31 IP */ | |
706 | dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); | |
707 | dwc->revision |= DWC3_REVISION_IS_DWC31; | |
475d8e01 | 708 | dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); |
690fb371 | 709 | } else { |
0759956f | 710 | return false; |
7650bd74 | 711 | } |
7650bd74 | 712 | |
0759956f FB |
713 | return true; |
714 | } | |
58a0f23f | 715 | |
941f918e | 716 | static void dwc3_core_setup_global_control(struct dwc3 *dwc) |
0759956f | 717 | { |
941f918e FB |
718 | u32 hwparams4 = dwc->hwparams.hwparams4; |
719 | u32 reg; | |
c499ff71 | 720 | |
4878a028 | 721 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); |
3e87c42a | 722 | reg &= ~DWC3_GCTL_SCALEDOWN_MASK; |
4878a028 | 723 | |
164d7731 | 724 | switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { |
4878a028 | 725 | case DWC3_GHWPARAMS1_EN_PWROPT_CLK: |
32a4a135 FB |
726 | /** |
727 | * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an | |
728 | * issue which would cause xHCI compliance tests to fail. | |
729 | * | |
730 | * Because of that we cannot enable clock gating on such | |
731 | * configurations. | |
732 | * | |
733 | * Refers to: | |
734 | * | |
735 | * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based | |
736 | * SOF/ITP Mode Used | |
737 | */ | |
738 | if ((dwc->dr_mode == USB_DR_MODE_HOST || | |
739 | dwc->dr_mode == USB_DR_MODE_OTG) && | |
740 | (dwc->revision >= DWC3_REVISION_210A && | |
741 | dwc->revision <= DWC3_REVISION_250A)) | |
742 | reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; | |
743 | else | |
744 | reg &= ~DWC3_GCTL_DSBLCLKGTNG; | |
4878a028 | 745 | break; |
0ffcaf37 FB |
746 | case DWC3_GHWPARAMS1_EN_PWROPT_HIB: |
747 | /* enable hibernation here */ | |
748 | dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); | |
2eac3992 HR |
749 | |
750 | /* | |
751 | * REVISIT Enabling this bit so that host-mode hibernation | |
752 | * will work. Device-mode hibernation is not yet implemented. | |
753 | */ | |
754 | reg |= DWC3_GCTL_GBLHIBERNATIONEN; | |
0ffcaf37 | 755 | break; |
4878a028 | 756 | default: |
5eb30ced FB |
757 | /* nothing */ |
758 | break; | |
4878a028 SAS |
759 | } |
760 | ||
946bd579 HR |
761 | /* check if current dwc3 is on simulation board */ |
762 | if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { | |
6af19fd1 | 763 | dev_info(dwc->dev, "Running with FPGA optimizations\n"); |
946bd579 HR |
764 | dwc->is_fpga = true; |
765 | } | |
766 | ||
3b81221a HR |
767 | WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, |
768 | "disable_scramble cannot be used on non-FPGA builds\n"); | |
769 | ||
770 | if (dwc->disable_scramble_quirk && dwc->is_fpga) | |
771 | reg |= DWC3_GCTL_DISSCRAMBLE; | |
772 | else | |
773 | reg &= ~DWC3_GCTL_DISSCRAMBLE; | |
774 | ||
9a5b2f31 HR |
775 | if (dwc->u2exit_lfps_quirk) |
776 | reg |= DWC3_GCTL_U2EXIT_LFPS; | |
777 | ||
4878a028 SAS |
778 | /* |
779 | * WORKAROUND: DWC3 revisions <1.90a have a bug | |
1d046793 | 780 | * where the device can fail to connect at SuperSpeed |
4878a028 | 781 | * and falls back to high-speed mode which causes |
1d046793 | 782 | * the device to enter a Connect/Disconnect loop |
4878a028 SAS |
783 | */ |
784 | if (dwc->revision < DWC3_REVISION_190A) | |
785 | reg |= DWC3_GCTL_U2RSTECN; | |
786 | ||
787 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
941f918e FB |
788 | } |
789 | ||
f54edb53 | 790 | static int dwc3_core_get_phy(struct dwc3 *dwc); |
98112041 | 791 | static int dwc3_core_ulpi_init(struct dwc3 *dwc); |
f54edb53 | 792 | |
d9612c2f PM |
793 | /* set global incr burst type configuration registers */ |
794 | static void dwc3_set_incr_burst_type(struct dwc3 *dwc) | |
795 | { | |
796 | struct device *dev = dwc->dev; | |
797 | /* incrx_mode : for INCR burst type. */ | |
798 | bool incrx_mode; | |
799 | /* incrx_size : for size of INCRX burst. */ | |
800 | u32 incrx_size; | |
801 | u32 *vals; | |
802 | u32 cfg; | |
803 | int ntype; | |
804 | int ret; | |
805 | int i; | |
806 | ||
807 | cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); | |
808 | ||
809 | /* | |
810 | * Handle property "snps,incr-burst-type-adjustment". | |
811 | * Get the number of value from this property: | |
812 | * result <= 0, means this property is not supported. | |
813 | * result = 1, means INCRx burst mode supported. | |
814 | * result > 1, means undefined length burst mode supported. | |
815 | */ | |
816 | ntype = device_property_read_u32_array(dev, | |
817 | "snps,incr-burst-type-adjustment", NULL, 0); | |
818 | if (ntype <= 0) | |
819 | return; | |
820 | ||
821 | vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); | |
822 | if (!vals) { | |
823 | dev_err(dev, "Error to get memory\n"); | |
824 | return; | |
825 | } | |
826 | ||
827 | /* Get INCR burst type, and parse it */ | |
828 | ret = device_property_read_u32_array(dev, | |
829 | "snps,incr-burst-type-adjustment", vals, ntype); | |
830 | if (ret) { | |
75ecb9dd | 831 | kfree(vals); |
d9612c2f PM |
832 | dev_err(dev, "Error to get property\n"); |
833 | return; | |
834 | } | |
835 | ||
836 | incrx_size = *vals; | |
837 | ||
838 | if (ntype > 1) { | |
839 | /* INCRX (undefined length) burst mode */ | |
840 | incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; | |
841 | for (i = 1; i < ntype; i++) { | |
842 | if (vals[i] > incrx_size) | |
843 | incrx_size = vals[i]; | |
844 | } | |
845 | } else { | |
846 | /* INCRX burst mode */ | |
847 | incrx_mode = INCRX_BURST_MODE; | |
848 | } | |
849 | ||
75ecb9dd AS |
850 | kfree(vals); |
851 | ||
d9612c2f PM |
852 | /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ |
853 | cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; | |
854 | if (incrx_mode) | |
855 | cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; | |
856 | switch (incrx_size) { | |
857 | case 256: | |
858 | cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; | |
859 | break; | |
860 | case 128: | |
861 | cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; | |
862 | break; | |
863 | case 64: | |
864 | cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; | |
865 | break; | |
866 | case 32: | |
867 | cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; | |
868 | break; | |
869 | case 16: | |
870 | cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; | |
871 | break; | |
872 | case 8: | |
873 | cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; | |
874 | break; | |
875 | case 4: | |
876 | cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; | |
877 | break; | |
878 | case 1: | |
879 | break; | |
880 | default: | |
881 | dev_err(dev, "Invalid property\n"); | |
882 | break; | |
883 | } | |
884 | ||
885 | dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); | |
886 | } | |
887 | ||
941f918e FB |
888 | /** |
889 | * dwc3_core_init - Low-level initialization of DWC3 Core | |
890 | * @dwc: Pointer to our controller context structure | |
891 | * | |
892 | * Returns 0 on success otherwise negative errno. | |
893 | */ | |
894 | static int dwc3_core_init(struct dwc3 *dwc) | |
895 | { | |
896 | u32 reg; | |
897 | int ret; | |
898 | ||
941f918e FB |
899 | /* |
900 | * Write Linux Version Code to our GUID register so it's easy to figure | |
901 | * out which kernel version a bug was found. | |
902 | */ | |
903 | dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); | |
904 | ||
905 | /* Handle USB2.0-only core configuration */ | |
906 | if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == | |
907 | DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { | |
908 | if (dwc->maximum_speed == USB_SPEED_SUPER) | |
909 | dwc->maximum_speed = USB_SPEED_HIGH; | |
910 | } | |
911 | ||
98112041 | 912 | ret = dwc3_phy_setup(dwc); |
941f918e FB |
913 | if (ret) |
914 | goto err0; | |
4878a028 | 915 | |
98112041 RQ |
916 | if (!dwc->ulpi_ready) { |
917 | ret = dwc3_core_ulpi_init(dwc); | |
918 | if (ret) | |
919 | goto err0; | |
920 | dwc->ulpi_ready = true; | |
921 | } | |
4878a028 | 922 | |
98112041 RQ |
923 | if (!dwc->phys_ready) { |
924 | ret = dwc3_core_get_phy(dwc); | |
925 | if (ret) | |
926 | goto err0a; | |
927 | dwc->phys_ready = true; | |
928 | } | |
929 | ||
930 | ret = dwc3_core_soft_reset(dwc); | |
f54edb53 | 931 | if (ret) |
98112041 | 932 | goto err0a; |
f54edb53 | 933 | |
941f918e | 934 | dwc3_core_setup_global_control(dwc); |
c499ff71 | 935 | dwc3_core_num_eps(dwc); |
0ffcaf37 FB |
936 | |
937 | ret = dwc3_setup_scratch_buffers(dwc); | |
938 | if (ret) | |
c499ff71 FB |
939 | goto err1; |
940 | ||
941 | /* Adjust Frame Length */ | |
942 | dwc3_frame_length_adjustment(dwc); | |
943 | ||
d9612c2f PM |
944 | dwc3_set_incr_burst_type(dwc); |
945 | ||
c499ff71 FB |
946 | usb_phy_set_suspend(dwc->usb2_phy, 0); |
947 | usb_phy_set_suspend(dwc->usb3_phy, 0); | |
948 | ret = phy_power_on(dwc->usb2_generic_phy); | |
949 | if (ret < 0) | |
0ffcaf37 FB |
950 | goto err2; |
951 | ||
c499ff71 FB |
952 | ret = phy_power_on(dwc->usb3_generic_phy); |
953 | if (ret < 0) | |
954 | goto err3; | |
955 | ||
956 | ret = dwc3_event_buffers_setup(dwc); | |
957 | if (ret) { | |
958 | dev_err(dwc->dev, "failed to setup event buffers\n"); | |
959 | goto err4; | |
960 | } | |
961 | ||
06281d46 JY |
962 | /* |
963 | * ENDXFER polling is available on version 3.10a and later of | |
964 | * the DWC_usb3 controller. It is NOT available in the | |
965 | * DWC_usb31 controller. | |
966 | */ | |
967 | if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) { | |
968 | reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); | |
969 | reg |= DWC3_GUCTL2_RST_ACTBITLATER; | |
970 | dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); | |
971 | } | |
972 | ||
65db7a0c | 973 | if (dwc->revision >= DWC3_REVISION_250A) { |
0bb39ca1 | 974 | reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); |
65db7a0c WW |
975 | |
976 | /* | |
977 | * Enable hardware control of sending remote wakeup | |
978 | * in HS when the device is in the L1 state. | |
979 | */ | |
980 | if (dwc->revision >= DWC3_REVISION_290A) | |
981 | reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; | |
982 | ||
983 | if (dwc->dis_tx_ipgap_linecheck_quirk) | |
984 | reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; | |
985 | ||
0bb39ca1 JY |
986 | dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); |
987 | } | |
988 | ||
b138e23d AKV |
989 | if (dwc->dr_mode == USB_DR_MODE_HOST || |
990 | dwc->dr_mode == USB_DR_MODE_OTG) { | |
991 | reg = dwc3_readl(dwc->regs, DWC3_GUCTL); | |
992 | ||
993 | /* | |
994 | * Enable Auto retry Feature to make the controller operating in | |
995 | * Host mode on seeing transaction errors(CRC errors or internal | |
996 | * overrun scenerios) on IN transfers to reply to the device | |
997 | * with a non-terminating retry ACK (i.e, an ACK transcation | |
998 | * packet with Retry=1 & Nump != 0) | |
999 | */ | |
1000 | reg |= DWC3_GUCTL_HSTINAUTORETRY; | |
1001 | ||
1002 | dwc3_writel(dwc->regs, DWC3_GUCTL, reg); | |
1003 | } | |
1004 | ||
938a5ad1 TN |
1005 | /* |
1006 | * Must config both number of packets and max burst settings to enable | |
1007 | * RX and/or TX threshold. | |
1008 | */ | |
1009 | if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) { | |
1010 | u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; | |
1011 | u8 rx_maxburst = dwc->rx_max_burst_prd; | |
1012 | u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; | |
1013 | u8 tx_maxburst = dwc->tx_max_burst_prd; | |
1014 | ||
1015 | if (rx_thr_num && rx_maxburst) { | |
1016 | reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); | |
1017 | reg |= DWC31_RXTHRNUMPKTSEL_PRD; | |
1018 | ||
1019 | reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); | |
1020 | reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); | |
1021 | ||
1022 | reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); | |
1023 | reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); | |
1024 | ||
1025 | dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); | |
1026 | } | |
1027 | ||
1028 | if (tx_thr_num && tx_maxburst) { | |
1029 | reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); | |
1030 | reg |= DWC31_TXTHRNUMPKTSEL_PRD; | |
1031 | ||
1032 | reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); | |
1033 | reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); | |
1034 | ||
1035 | reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); | |
1036 | reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); | |
1037 | ||
1038 | dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); | |
1039 | } | |
1040 | } | |
1041 | ||
72246da4 FB |
1042 | return 0; |
1043 | ||
c499ff71 | 1044 | err4: |
9b9d7cdd | 1045 | phy_power_off(dwc->usb3_generic_phy); |
c499ff71 FB |
1046 | |
1047 | err3: | |
9b9d7cdd | 1048 | phy_power_off(dwc->usb2_generic_phy); |
c499ff71 | 1049 | |
0ffcaf37 | 1050 | err2: |
c499ff71 FB |
1051 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
1052 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
0ffcaf37 FB |
1053 | |
1054 | err1: | |
1055 | usb_phy_shutdown(dwc->usb2_phy); | |
1056 | usb_phy_shutdown(dwc->usb3_phy); | |
57303488 KVA |
1057 | phy_exit(dwc->usb2_generic_phy); |
1058 | phy_exit(dwc->usb3_generic_phy); | |
0ffcaf37 | 1059 | |
98112041 RQ |
1060 | err0a: |
1061 | dwc3_ulpi_exit(dwc); | |
1062 | ||
72246da4 FB |
1063 | err0: |
1064 | return ret; | |
1065 | } | |
1066 | ||
3c9f94ac | 1067 | static int dwc3_core_get_phy(struct dwc3 *dwc) |
72246da4 | 1068 | { |
3c9f94ac | 1069 | struct device *dev = dwc->dev; |
941ea361 | 1070 | struct device_node *node = dev->of_node; |
3c9f94ac | 1071 | int ret; |
72246da4 | 1072 | |
5088b6f5 KVA |
1073 | if (node) { |
1074 | dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); | |
1075 | dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); | |
bb674907 FB |
1076 | } else { |
1077 | dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); | |
1078 | dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); | |
5088b6f5 KVA |
1079 | } |
1080 | ||
d105e7f8 FB |
1081 | if (IS_ERR(dwc->usb2_phy)) { |
1082 | ret = PTR_ERR(dwc->usb2_phy); | |
122f06e6 KVA |
1083 | if (ret == -ENXIO || ret == -ENODEV) { |
1084 | dwc->usb2_phy = NULL; | |
1085 | } else if (ret == -EPROBE_DEFER) { | |
d105e7f8 | 1086 | return ret; |
122f06e6 KVA |
1087 | } else { |
1088 | dev_err(dev, "no usb2 phy configured\n"); | |
1089 | return ret; | |
1090 | } | |
51e1e7bc FB |
1091 | } |
1092 | ||
d105e7f8 | 1093 | if (IS_ERR(dwc->usb3_phy)) { |
315955d7 | 1094 | ret = PTR_ERR(dwc->usb3_phy); |
122f06e6 KVA |
1095 | if (ret == -ENXIO || ret == -ENODEV) { |
1096 | dwc->usb3_phy = NULL; | |
1097 | } else if (ret == -EPROBE_DEFER) { | |
d105e7f8 | 1098 | return ret; |
122f06e6 KVA |
1099 | } else { |
1100 | dev_err(dev, "no usb3 phy configured\n"); | |
1101 | return ret; | |
1102 | } | |
51e1e7bc FB |
1103 | } |
1104 | ||
57303488 KVA |
1105 | dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); |
1106 | if (IS_ERR(dwc->usb2_generic_phy)) { | |
1107 | ret = PTR_ERR(dwc->usb2_generic_phy); | |
1108 | if (ret == -ENOSYS || ret == -ENODEV) { | |
1109 | dwc->usb2_generic_phy = NULL; | |
1110 | } else if (ret == -EPROBE_DEFER) { | |
1111 | return ret; | |
1112 | } else { | |
1113 | dev_err(dev, "no usb2 phy configured\n"); | |
1114 | return ret; | |
1115 | } | |
1116 | } | |
1117 | ||
1118 | dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); | |
1119 | if (IS_ERR(dwc->usb3_generic_phy)) { | |
1120 | ret = PTR_ERR(dwc->usb3_generic_phy); | |
1121 | if (ret == -ENOSYS || ret == -ENODEV) { | |
1122 | dwc->usb3_generic_phy = NULL; | |
1123 | } else if (ret == -EPROBE_DEFER) { | |
1124 | return ret; | |
1125 | } else { | |
1126 | dev_err(dev, "no usb3 phy configured\n"); | |
1127 | return ret; | |
1128 | } | |
1129 | } | |
1130 | ||
3c9f94ac FB |
1131 | return 0; |
1132 | } | |
1133 | ||
5f94adfe FB |
1134 | static int dwc3_core_init_mode(struct dwc3 *dwc) |
1135 | { | |
1136 | struct device *dev = dwc->dev; | |
1137 | int ret; | |
1138 | ||
1139 | switch (dwc->dr_mode) { | |
1140 | case USB_DR_MODE_PERIPHERAL: | |
41ce1456 | 1141 | dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); |
958d1a4c FB |
1142 | |
1143 | if (dwc->usb2_phy) | |
1144 | otg_set_vbus(dwc->usb2_phy->otg, false); | |
644cbbc3 MG |
1145 | phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); |
1146 | phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); | |
958d1a4c | 1147 | |
5f94adfe FB |
1148 | ret = dwc3_gadget_init(dwc); |
1149 | if (ret) { | |
9522def4 RQ |
1150 | if (ret != -EPROBE_DEFER) |
1151 | dev_err(dev, "failed to initialize gadget\n"); | |
5f94adfe FB |
1152 | return ret; |
1153 | } | |
1154 | break; | |
1155 | case USB_DR_MODE_HOST: | |
41ce1456 | 1156 | dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); |
958d1a4c FB |
1157 | |
1158 | if (dwc->usb2_phy) | |
1159 | otg_set_vbus(dwc->usb2_phy->otg, true); | |
644cbbc3 MG |
1160 | phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); |
1161 | phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); | |
958d1a4c | 1162 | |
5f94adfe FB |
1163 | ret = dwc3_host_init(dwc); |
1164 | if (ret) { | |
9522def4 RQ |
1165 | if (ret != -EPROBE_DEFER) |
1166 | dev_err(dev, "failed to initialize host\n"); | |
5f94adfe FB |
1167 | return ret; |
1168 | } | |
d8c80bb3 | 1169 | phy_calibrate(dwc->usb2_generic_phy); |
5f94adfe FB |
1170 | break; |
1171 | case USB_DR_MODE_OTG: | |
41ce1456 | 1172 | INIT_WORK(&dwc->drd_work, __dwc3_set_mode); |
9840354f RQ |
1173 | ret = dwc3_drd_init(dwc); |
1174 | if (ret) { | |
1175 | if (ret != -EPROBE_DEFER) | |
1176 | dev_err(dev, "failed to initialize dual-role\n"); | |
1177 | return ret; | |
1178 | } | |
5f94adfe FB |
1179 | break; |
1180 | default: | |
1181 | dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); | |
1182 | return -EINVAL; | |
1183 | } | |
1184 | ||
1185 | return 0; | |
1186 | } | |
1187 | ||
1188 | static void dwc3_core_exit_mode(struct dwc3 *dwc) | |
1189 | { | |
1190 | switch (dwc->dr_mode) { | |
1191 | case USB_DR_MODE_PERIPHERAL: | |
1192 | dwc3_gadget_exit(dwc); | |
1193 | break; | |
1194 | case USB_DR_MODE_HOST: | |
1195 | dwc3_host_exit(dwc); | |
1196 | break; | |
1197 | case USB_DR_MODE_OTG: | |
9840354f | 1198 | dwc3_drd_exit(dwc); |
5f94adfe FB |
1199 | break; |
1200 | default: | |
1201 | /* do nothing */ | |
1202 | break; | |
1203 | } | |
1204 | } | |
1205 | ||
c5ac6116 | 1206 | static void dwc3_get_properties(struct dwc3 *dwc) |
3c9f94ac | 1207 | { |
c5ac6116 | 1208 | struct device *dev = dwc->dev; |
80caf7d2 | 1209 | u8 lpm_nyet_threshold; |
6b6a0c9a | 1210 | u8 tx_de_emphasis; |
460d098c | 1211 | u8 hird_threshold; |
938a5ad1 TN |
1212 | u8 rx_thr_num_pkt_prd; |
1213 | u8 rx_max_burst_prd; | |
1214 | u8 tx_thr_num_pkt_prd; | |
1215 | u8 tx_max_burst_prd; | |
3c9f94ac | 1216 | |
80caf7d2 HR |
1217 | /* default to highest possible threshold */ |
1218 | lpm_nyet_threshold = 0xff; | |
1219 | ||
6b6a0c9a HR |
1220 | /* default to -3.5dB de-emphasis */ |
1221 | tx_de_emphasis = 1; | |
1222 | ||
460d098c HR |
1223 | /* |
1224 | * default to assert utmi_sleep_n and use maximum allowed HIRD | |
1225 | * threshold value of 0b1100 | |
1226 | */ | |
1227 | hird_threshold = 12; | |
1228 | ||
63863b98 | 1229 | dwc->maximum_speed = usb_get_maximum_speed(dev); |
06e7114f | 1230 | dwc->dr_mode = usb_get_dr_mode(dev); |
32f2ed86 | 1231 | dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); |
63863b98 | 1232 | |
d64ff406 AB |
1233 | dwc->sysdev_is_parent = device_property_read_bool(dev, |
1234 | "linux,sysdev_is_parent"); | |
1235 | if (dwc->sysdev_is_parent) | |
1236 | dwc->sysdev = dwc->dev->parent; | |
1237 | else | |
1238 | dwc->sysdev = dwc->dev; | |
1239 | ||
3d128919 | 1240 | dwc->has_lpm_erratum = device_property_read_bool(dev, |
80caf7d2 | 1241 | "snps,has-lpm-erratum"); |
3d128919 | 1242 | device_property_read_u8(dev, "snps,lpm-nyet-threshold", |
80caf7d2 | 1243 | &lpm_nyet_threshold); |
3d128919 | 1244 | dwc->is_utmi_l1_suspend = device_property_read_bool(dev, |
460d098c | 1245 | "snps,is-utmi-l1-suspend"); |
3d128919 | 1246 | device_property_read_u8(dev, "snps,hird-threshold", |
460d098c | 1247 | &hird_threshold); |
d92021f6 TN |
1248 | dwc->dis_start_transfer_quirk = device_property_read_bool(dev, |
1249 | "snps,dis-start-transfer-quirk"); | |
3d128919 | 1250 | dwc->usb3_lpm_capable = device_property_read_bool(dev, |
eac68e8f | 1251 | "snps,usb3_lpm_capable"); |
022a0208 TN |
1252 | dwc->usb2_lpm_disable = device_property_read_bool(dev, |
1253 | "snps,usb2-lpm-disable"); | |
938a5ad1 TN |
1254 | device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", |
1255 | &rx_thr_num_pkt_prd); | |
1256 | device_property_read_u8(dev, "snps,rx-max-burst-prd", | |
1257 | &rx_max_burst_prd); | |
1258 | device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", | |
1259 | &tx_thr_num_pkt_prd); | |
1260 | device_property_read_u8(dev, "snps,tx-max-burst-prd", | |
1261 | &tx_max_burst_prd); | |
3c9f94ac | 1262 | |
3d128919 | 1263 | dwc->disable_scramble_quirk = device_property_read_bool(dev, |
3b81221a | 1264 | "snps,disable_scramble_quirk"); |
3d128919 | 1265 | dwc->u2exit_lfps_quirk = device_property_read_bool(dev, |
9a5b2f31 | 1266 | "snps,u2exit_lfps_quirk"); |
3d128919 | 1267 | dwc->u2ss_inp3_quirk = device_property_read_bool(dev, |
b5a65c40 | 1268 | "snps,u2ss_inp3_quirk"); |
3d128919 | 1269 | dwc->req_p1p2p3_quirk = device_property_read_bool(dev, |
df31f5b3 | 1270 | "snps,req_p1p2p3_quirk"); |
3d128919 | 1271 | dwc->del_p1p2p3_quirk = device_property_read_bool(dev, |
a2a1d0f5 | 1272 | "snps,del_p1p2p3_quirk"); |
3d128919 | 1273 | dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, |
41c06ffd | 1274 | "snps,del_phy_power_chg_quirk"); |
3d128919 | 1275 | dwc->lfps_filter_quirk = device_property_read_bool(dev, |
fb67afca | 1276 | "snps,lfps_filter_quirk"); |
3d128919 | 1277 | dwc->rx_detect_poll_quirk = device_property_read_bool(dev, |
14f4ac53 | 1278 | "snps,rx_detect_poll_quirk"); |
3d128919 | 1279 | dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, |
59acfa20 | 1280 | "snps,dis_u3_susphy_quirk"); |
3d128919 | 1281 | dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, |
0effe0a3 | 1282 | "snps,dis_u2_susphy_quirk"); |
ec791d14 JY |
1283 | dwc->dis_enblslpm_quirk = device_property_read_bool(dev, |
1284 | "snps,dis_enblslpm_quirk"); | |
e58dd357 RB |
1285 | dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, |
1286 | "snps,dis_rxdet_inp3_quirk"); | |
16199f33 WW |
1287 | dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, |
1288 | "snps,dis-u2-freeclk-exists-quirk"); | |
00fe081d WW |
1289 | dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, |
1290 | "snps,dis-del-phy-power-chg-quirk"); | |
65db7a0c WW |
1291 | dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, |
1292 | "snps,dis-tx-ipgap-linecheck-quirk"); | |
6b6a0c9a | 1293 | |
3d128919 | 1294 | dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, |
6b6a0c9a | 1295 | "snps,tx_de_emphasis_quirk"); |
3d128919 | 1296 | device_property_read_u8(dev, "snps,tx_de_emphasis", |
6b6a0c9a | 1297 | &tx_de_emphasis); |
3d128919 HK |
1298 | device_property_read_string(dev, "snps,hsphy_interface", |
1299 | &dwc->hsphy_interface); | |
1300 | device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", | |
bcdb3272 | 1301 | &dwc->fladj); |
3d128919 | 1302 | |
42bf02ec RQ |
1303 | dwc->dis_metastability_quirk = device_property_read_bool(dev, |
1304 | "snps,dis_metastability_quirk"); | |
1305 | ||
80caf7d2 | 1306 | dwc->lpm_nyet_threshold = lpm_nyet_threshold; |
6b6a0c9a | 1307 | dwc->tx_de_emphasis = tx_de_emphasis; |
80caf7d2 | 1308 | |
460d098c HR |
1309 | dwc->hird_threshold = hird_threshold |
1310 | | (dwc->is_utmi_l1_suspend << 4); | |
1311 | ||
938a5ad1 TN |
1312 | dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; |
1313 | dwc->rx_max_burst_prd = rx_max_burst_prd; | |
1314 | ||
1315 | dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; | |
1316 | dwc->tx_max_burst_prd = tx_max_burst_prd; | |
1317 | ||
cf40b86b JY |
1318 | dwc->imod_interval = 0; |
1319 | } | |
1320 | ||
1321 | /* check whether the core supports IMOD */ | |
1322 | bool dwc3_has_imod(struct dwc3 *dwc) | |
1323 | { | |
1324 | return ((dwc3_is_usb3(dwc) && | |
1325 | dwc->revision >= DWC3_REVISION_300A) || | |
1326 | (dwc3_is_usb31(dwc) && | |
1327 | dwc->revision >= DWC3_USB31_REVISION_120A)); | |
c5ac6116 FB |
1328 | } |
1329 | ||
7ac51a12 JY |
1330 | static void dwc3_check_params(struct dwc3 *dwc) |
1331 | { | |
1332 | struct device *dev = dwc->dev; | |
1333 | ||
cf40b86b JY |
1334 | /* Check for proper value of imod_interval */ |
1335 | if (dwc->imod_interval && !dwc3_has_imod(dwc)) { | |
1336 | dev_warn(dwc->dev, "Interrupt moderation not supported\n"); | |
1337 | dwc->imod_interval = 0; | |
1338 | } | |
1339 | ||
28632b44 JY |
1340 | /* |
1341 | * Workaround for STAR 9000961433 which affects only version | |
1342 | * 3.00a of the DWC_usb3 core. This prevents the controller | |
1343 | * interrupt from being masked while handling events. IMOD | |
1344 | * allows us to work around this issue. Enable it for the | |
1345 | * affected version. | |
1346 | */ | |
1347 | if (!dwc->imod_interval && | |
1348 | (dwc->revision == DWC3_REVISION_300A)) | |
1349 | dwc->imod_interval = 1; | |
1350 | ||
7ac51a12 JY |
1351 | /* Check the maximum_speed parameter */ |
1352 | switch (dwc->maximum_speed) { | |
1353 | case USB_SPEED_LOW: | |
1354 | case USB_SPEED_FULL: | |
1355 | case USB_SPEED_HIGH: | |
1356 | case USB_SPEED_SUPER: | |
1357 | case USB_SPEED_SUPER_PLUS: | |
1358 | break; | |
1359 | default: | |
1360 | dev_err(dev, "invalid maximum_speed parameter %d\n", | |
1361 | dwc->maximum_speed); | |
1362 | /* fall through */ | |
1363 | case USB_SPEED_UNKNOWN: | |
1364 | /* default to superspeed */ | |
1365 | dwc->maximum_speed = USB_SPEED_SUPER; | |
1366 | ||
1367 | /* | |
1368 | * default to superspeed plus if we are capable. | |
1369 | */ | |
1370 | if (dwc3_is_usb31(dwc) && | |
1371 | (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == | |
1372 | DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) | |
1373 | dwc->maximum_speed = USB_SPEED_SUPER_PLUS; | |
1374 | ||
1375 | break; | |
1376 | } | |
1377 | } | |
1378 | ||
c5ac6116 FB |
1379 | static int dwc3_probe(struct platform_device *pdev) |
1380 | { | |
1381 | struct device *dev = &pdev->dev; | |
44feb8e6 | 1382 | struct resource *res, dwc_res; |
c5ac6116 FB |
1383 | struct dwc3 *dwc; |
1384 | ||
1385 | int ret; | |
1386 | ||
1387 | void __iomem *regs; | |
1388 | ||
1389 | dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); | |
1390 | if (!dwc) | |
1391 | return -ENOMEM; | |
1392 | ||
fe8abf33 MY |
1393 | dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks), |
1394 | GFP_KERNEL); | |
1395 | if (!dwc->clks) | |
1396 | return -ENOMEM; | |
1397 | ||
c5ac6116 FB |
1398 | dwc->dev = dev; |
1399 | ||
1400 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1401 | if (!res) { | |
1402 | dev_err(dev, "missing memory resource\n"); | |
1403 | return -ENODEV; | |
1404 | } | |
1405 | ||
1406 | dwc->xhci_resources[0].start = res->start; | |
1407 | dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + | |
1408 | DWC3_XHCI_REGS_END; | |
1409 | dwc->xhci_resources[0].flags = res->flags; | |
1410 | dwc->xhci_resources[0].name = res->name; | |
1411 | ||
c5ac6116 FB |
1412 | /* |
1413 | * Request memory region but exclude xHCI regs, | |
1414 | * since it will be requested by the xhci-plat driver. | |
1415 | */ | |
44feb8e6 MY |
1416 | dwc_res = *res; |
1417 | dwc_res.start += DWC3_GLOBALS_REGS_START; | |
1418 | ||
1419 | regs = devm_ioremap_resource(dev, &dwc_res); | |
1420 | if (IS_ERR(regs)) | |
1421 | return PTR_ERR(regs); | |
c5ac6116 FB |
1422 | |
1423 | dwc->regs = regs; | |
44feb8e6 | 1424 | dwc->regs_size = resource_size(&dwc_res); |
c5ac6116 | 1425 | |
b873e2d0 TN |
1426 | if (!dwc3_core_is_valid(dwc)) { |
1427 | dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); | |
1428 | return -ENODEV; | |
1429 | } | |
1430 | ||
c5ac6116 FB |
1431 | dwc3_get_properties(dwc); |
1432 | ||
fe8abf33 MY |
1433 | dwc->reset = devm_reset_control_get_optional_shared(dev, NULL); |
1434 | if (IS_ERR(dwc->reset)) | |
1435 | return PTR_ERR(dwc->reset); | |
1436 | ||
61527777 HG |
1437 | if (dev->of_node) { |
1438 | dwc->num_clks = ARRAY_SIZE(dwc3_core_clks); | |
1439 | ||
1440 | ret = clk_bulk_get(dev, dwc->num_clks, dwc->clks); | |
1441 | if (ret == -EPROBE_DEFER) | |
1442 | return ret; | |
1443 | /* | |
1444 | * Clocks are optional, but new DT platforms should support all | |
1445 | * clocks as required by the DT-binding. | |
1446 | */ | |
1447 | if (ret) | |
1448 | dwc->num_clks = 0; | |
1449 | } | |
fe8abf33 MY |
1450 | |
1451 | ret = reset_control_deassert(dwc->reset); | |
1452 | if (ret) | |
1453 | goto put_clks; | |
1454 | ||
1455 | ret = clk_bulk_prepare(dwc->num_clks, dwc->clks); | |
1456 | if (ret) | |
1457 | goto assert_reset; | |
1458 | ||
1459 | ret = clk_bulk_enable(dwc->num_clks, dwc->clks); | |
1460 | if (ret) | |
1461 | goto unprepare_clks; | |
1462 | ||
6c89cce0 | 1463 | platform_set_drvdata(pdev, dwc); |
2917e718 | 1464 | dwc3_cache_hwparams(dwc); |
6c89cce0 | 1465 | |
72246da4 | 1466 | spin_lock_init(&dwc->lock); |
72246da4 | 1467 | |
fc8bb91b FB |
1468 | pm_runtime_set_active(dev); |
1469 | pm_runtime_use_autosuspend(dev); | |
1470 | pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); | |
802ca850 | 1471 | pm_runtime_enable(dev); |
32808237 RQ |
1472 | ret = pm_runtime_get_sync(dev); |
1473 | if (ret < 0) | |
1474 | goto err1; | |
1475 | ||
802ca850 | 1476 | pm_runtime_forbid(dev); |
72246da4 | 1477 | |
3921426b FB |
1478 | ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); |
1479 | if (ret) { | |
1480 | dev_err(dwc->dev, "failed to allocate event buffers\n"); | |
1481 | ret = -ENOMEM; | |
32808237 | 1482 | goto err2; |
3921426b FB |
1483 | } |
1484 | ||
9d6173e1 TN |
1485 | ret = dwc3_get_dr_mode(dwc); |
1486 | if (ret) | |
1487 | goto err3; | |
32a4a135 | 1488 | |
c499ff71 FB |
1489 | ret = dwc3_alloc_scratch_buffers(dwc); |
1490 | if (ret) | |
32808237 | 1491 | goto err3; |
c499ff71 | 1492 | |
72246da4 FB |
1493 | ret = dwc3_core_init(dwc); |
1494 | if (ret) { | |
408d3ba0 BN |
1495 | if (ret != -EPROBE_DEFER) |
1496 | dev_err(dev, "failed to initialize core: %d\n", ret); | |
32808237 | 1497 | goto err4; |
72246da4 FB |
1498 | } |
1499 | ||
7ac51a12 | 1500 | dwc3_check_params(dwc); |
2c7f1bd9 | 1501 | |
5f94adfe FB |
1502 | ret = dwc3_core_init_mode(dwc); |
1503 | if (ret) | |
32808237 | 1504 | goto err5; |
72246da4 | 1505 | |
4e9f3118 | 1506 | dwc3_debugfs_init(dwc); |
fc8bb91b | 1507 | pm_runtime_put(dev); |
72246da4 FB |
1508 | |
1509 | return 0; | |
1510 | ||
32808237 | 1511 | err5: |
c499ff71 | 1512 | dwc3_event_buffers_cleanup(dwc); |
08fd9a82 | 1513 | dwc3_ulpi_exit(dwc); |
57303488 | 1514 | |
32808237 | 1515 | err4: |
c499ff71 | 1516 | dwc3_free_scratch_buffers(dwc); |
72246da4 | 1517 | |
32808237 | 1518 | err3: |
3921426b FB |
1519 | dwc3_free_event_buffers(dwc); |
1520 | ||
32808237 RQ |
1521 | err2: |
1522 | pm_runtime_allow(&pdev->dev); | |
1523 | ||
1524 | err1: | |
1525 | pm_runtime_put_sync(&pdev->dev); | |
1526 | pm_runtime_disable(&pdev->dev); | |
1527 | ||
fe8abf33 MY |
1528 | clk_bulk_disable(dwc->num_clks, dwc->clks); |
1529 | unprepare_clks: | |
1530 | clk_bulk_unprepare(dwc->num_clks, dwc->clks); | |
1531 | assert_reset: | |
1532 | reset_control_assert(dwc->reset); | |
1533 | put_clks: | |
1534 | clk_bulk_put(dwc->num_clks, dwc->clks); | |
1535 | ||
72246da4 FB |
1536 | return ret; |
1537 | } | |
1538 | ||
fb4e98ab | 1539 | static int dwc3_remove(struct platform_device *pdev) |
72246da4 | 1540 | { |
72246da4 | 1541 | struct dwc3 *dwc = platform_get_drvdata(pdev); |
3da1f6ee | 1542 | |
fc8bb91b | 1543 | pm_runtime_get_sync(&pdev->dev); |
72246da4 | 1544 | |
dc99f16f FB |
1545 | dwc3_debugfs_exit(dwc); |
1546 | dwc3_core_exit_mode(dwc); | |
8ba007a9 | 1547 | |
72246da4 | 1548 | dwc3_core_exit(dwc); |
88bc9d19 | 1549 | dwc3_ulpi_exit(dwc); |
72246da4 | 1550 | |
16b972a5 | 1551 | pm_runtime_put_sync(&pdev->dev); |
fc8bb91b | 1552 | pm_runtime_allow(&pdev->dev); |
72246da4 FB |
1553 | pm_runtime_disable(&pdev->dev); |
1554 | ||
fc8bb91b FB |
1555 | dwc3_free_event_buffers(dwc); |
1556 | dwc3_free_scratch_buffers(dwc); | |
fe8abf33 | 1557 | clk_bulk_put(dwc->num_clks, dwc->clks); |
fc8bb91b | 1558 | |
72246da4 FB |
1559 | return 0; |
1560 | } | |
1561 | ||
fc8bb91b | 1562 | #ifdef CONFIG_PM |
fe8abf33 MY |
1563 | static int dwc3_core_init_for_resume(struct dwc3 *dwc) |
1564 | { | |
1565 | int ret; | |
1566 | ||
1567 | ret = reset_control_deassert(dwc->reset); | |
1568 | if (ret) | |
1569 | return ret; | |
1570 | ||
1571 | ret = clk_bulk_prepare(dwc->num_clks, dwc->clks); | |
1572 | if (ret) | |
1573 | goto assert_reset; | |
1574 | ||
1575 | ret = clk_bulk_enable(dwc->num_clks, dwc->clks); | |
1576 | if (ret) | |
1577 | goto unprepare_clks; | |
1578 | ||
1579 | ret = dwc3_core_init(dwc); | |
1580 | if (ret) | |
1581 | goto disable_clks; | |
1582 | ||
1583 | return 0; | |
1584 | ||
1585 | disable_clks: | |
1586 | clk_bulk_disable(dwc->num_clks, dwc->clks); | |
1587 | unprepare_clks: | |
1588 | clk_bulk_unprepare(dwc->num_clks, dwc->clks); | |
1589 | assert_reset: | |
1590 | reset_control_assert(dwc->reset); | |
1591 | ||
1592 | return ret; | |
1593 | } | |
1594 | ||
c4a5153e | 1595 | static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) |
7415f17c | 1596 | { |
fc8bb91b | 1597 | unsigned long flags; |
bcb12877 | 1598 | u32 reg; |
7415f17c | 1599 | |
689bf72c MG |
1600 | switch (dwc->current_dr_role) { |
1601 | case DWC3_GCTL_PRTCAP_DEVICE: | |
fc8bb91b | 1602 | spin_lock_irqsave(&dwc->lock, flags); |
7415f17c | 1603 | dwc3_gadget_suspend(dwc); |
fc8bb91b | 1604 | spin_unlock_irqrestore(&dwc->lock, flags); |
41a91c60 | 1605 | synchronize_irq(dwc->irq_gadget); |
689bf72c | 1606 | dwc3_core_exit(dwc); |
51f5d49a | 1607 | break; |
689bf72c | 1608 | case DWC3_GCTL_PRTCAP_HOST: |
bcb12877 | 1609 | if (!PMSG_IS_AUTO(msg)) { |
c4a5153e | 1610 | dwc3_core_exit(dwc); |
bcb12877 MG |
1611 | break; |
1612 | } | |
1613 | ||
1614 | /* Let controller to suspend HSPHY before PHY driver suspends */ | |
1615 | if (dwc->dis_u2_susphy_quirk || | |
1616 | dwc->dis_enblslpm_quirk) { | |
1617 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
1618 | reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | | |
1619 | DWC3_GUSB2PHYCFG_SUSPHY; | |
1620 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
1621 | ||
1622 | /* Give some time for USB2 PHY to suspend */ | |
1623 | usleep_range(5000, 6000); | |
1624 | } | |
1625 | ||
1626 | phy_pm_runtime_put_sync(dwc->usb2_generic_phy); | |
1627 | phy_pm_runtime_put_sync(dwc->usb3_generic_phy); | |
c4a5153e | 1628 | break; |
f09cc79b RQ |
1629 | case DWC3_GCTL_PRTCAP_OTG: |
1630 | /* do nothing during runtime_suspend */ | |
1631 | if (PMSG_IS_AUTO(msg)) | |
1632 | break; | |
1633 | ||
1634 | if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { | |
1635 | spin_lock_irqsave(&dwc->lock, flags); | |
1636 | dwc3_gadget_suspend(dwc); | |
1637 | spin_unlock_irqrestore(&dwc->lock, flags); | |
41a91c60 | 1638 | synchronize_irq(dwc->irq_gadget); |
f09cc79b RQ |
1639 | } |
1640 | ||
1641 | dwc3_otg_exit(dwc); | |
1642 | dwc3_core_exit(dwc); | |
1643 | break; | |
7415f17c | 1644 | default: |
51f5d49a | 1645 | /* do nothing */ |
7415f17c FB |
1646 | break; |
1647 | } | |
1648 | ||
7415f17c FB |
1649 | return 0; |
1650 | } | |
1651 | ||
c4a5153e | 1652 | static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) |
7415f17c | 1653 | { |
fc8bb91b | 1654 | unsigned long flags; |
57303488 | 1655 | int ret; |
bcb12877 | 1656 | u32 reg; |
7415f17c | 1657 | |
689bf72c MG |
1658 | switch (dwc->current_dr_role) { |
1659 | case DWC3_GCTL_PRTCAP_DEVICE: | |
fe8abf33 | 1660 | ret = dwc3_core_init_for_resume(dwc); |
689bf72c MG |
1661 | if (ret) |
1662 | return ret; | |
5c4ad318 | 1663 | |
7d11c3ac | 1664 | dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); |
fc8bb91b | 1665 | spin_lock_irqsave(&dwc->lock, flags); |
7415f17c | 1666 | dwc3_gadget_resume(dwc); |
fc8bb91b | 1667 | spin_unlock_irqrestore(&dwc->lock, flags); |
689bf72c MG |
1668 | break; |
1669 | case DWC3_GCTL_PRTCAP_HOST: | |
c4a5153e | 1670 | if (!PMSG_IS_AUTO(msg)) { |
fe8abf33 | 1671 | ret = dwc3_core_init_for_resume(dwc); |
c4a5153e MG |
1672 | if (ret) |
1673 | return ret; | |
7d11c3ac | 1674 | dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); |
bcb12877 | 1675 | break; |
c4a5153e | 1676 | } |
bcb12877 MG |
1677 | /* Restore GUSB2PHYCFG bits that were modified in suspend */ |
1678 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
1679 | if (dwc->dis_u2_susphy_quirk) | |
1680 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; | |
1681 | ||
1682 | if (dwc->dis_enblslpm_quirk) | |
1683 | reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; | |
1684 | ||
1685 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
1686 | ||
1687 | phy_pm_runtime_get_sync(dwc->usb2_generic_phy); | |
1688 | phy_pm_runtime_get_sync(dwc->usb3_generic_phy); | |
f09cc79b RQ |
1689 | break; |
1690 | case DWC3_GCTL_PRTCAP_OTG: | |
1691 | /* nothing to do on runtime_resume */ | |
1692 | if (PMSG_IS_AUTO(msg)) | |
1693 | break; | |
1694 | ||
1695 | ret = dwc3_core_init(dwc); | |
1696 | if (ret) | |
1697 | return ret; | |
1698 | ||
1699 | dwc3_set_prtcap(dwc, dwc->current_dr_role); | |
1700 | ||
1701 | dwc3_otg_init(dwc); | |
1702 | if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { | |
1703 | dwc3_otg_host_init(dwc); | |
1704 | } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { | |
1705 | spin_lock_irqsave(&dwc->lock, flags); | |
1706 | dwc3_gadget_resume(dwc); | |
1707 | spin_unlock_irqrestore(&dwc->lock, flags); | |
c4a5153e | 1708 | } |
f09cc79b | 1709 | |
c4a5153e | 1710 | break; |
7415f17c FB |
1711 | default: |
1712 | /* do nothing */ | |
1713 | break; | |
1714 | } | |
1715 | ||
fc8bb91b FB |
1716 | return 0; |
1717 | } | |
1718 | ||
1719 | static int dwc3_runtime_checks(struct dwc3 *dwc) | |
1720 | { | |
689bf72c | 1721 | switch (dwc->current_dr_role) { |
c4a5153e | 1722 | case DWC3_GCTL_PRTCAP_DEVICE: |
fc8bb91b FB |
1723 | if (dwc->connected) |
1724 | return -EBUSY; | |
1725 | break; | |
c4a5153e | 1726 | case DWC3_GCTL_PRTCAP_HOST: |
fc8bb91b FB |
1727 | default: |
1728 | /* do nothing */ | |
1729 | break; | |
1730 | } | |
1731 | ||
1732 | return 0; | |
1733 | } | |
1734 | ||
1735 | static int dwc3_runtime_suspend(struct device *dev) | |
1736 | { | |
1737 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1738 | int ret; | |
1739 | ||
1740 | if (dwc3_runtime_checks(dwc)) | |
1741 | return -EBUSY; | |
1742 | ||
c4a5153e | 1743 | ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); |
fc8bb91b FB |
1744 | if (ret) |
1745 | return ret; | |
1746 | ||
1747 | device_init_wakeup(dev, true); | |
1748 | ||
1749 | return 0; | |
1750 | } | |
1751 | ||
1752 | static int dwc3_runtime_resume(struct device *dev) | |
1753 | { | |
1754 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1755 | int ret; | |
1756 | ||
1757 | device_init_wakeup(dev, false); | |
1758 | ||
c4a5153e | 1759 | ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); |
fc8bb91b FB |
1760 | if (ret) |
1761 | return ret; | |
1762 | ||
689bf72c MG |
1763 | switch (dwc->current_dr_role) { |
1764 | case DWC3_GCTL_PRTCAP_DEVICE: | |
fc8bb91b FB |
1765 | dwc3_gadget_process_pending_events(dwc); |
1766 | break; | |
689bf72c | 1767 | case DWC3_GCTL_PRTCAP_HOST: |
fc8bb91b FB |
1768 | default: |
1769 | /* do nothing */ | |
1770 | break; | |
1771 | } | |
1772 | ||
1773 | pm_runtime_mark_last_busy(dev); | |
1774 | ||
1775 | return 0; | |
1776 | } | |
1777 | ||
1778 | static int dwc3_runtime_idle(struct device *dev) | |
1779 | { | |
1780 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1781 | ||
689bf72c MG |
1782 | switch (dwc->current_dr_role) { |
1783 | case DWC3_GCTL_PRTCAP_DEVICE: | |
fc8bb91b FB |
1784 | if (dwc3_runtime_checks(dwc)) |
1785 | return -EBUSY; | |
1786 | break; | |
689bf72c | 1787 | case DWC3_GCTL_PRTCAP_HOST: |
fc8bb91b FB |
1788 | default: |
1789 | /* do nothing */ | |
1790 | break; | |
1791 | } | |
1792 | ||
1793 | pm_runtime_mark_last_busy(dev); | |
1794 | pm_runtime_autosuspend(dev); | |
1795 | ||
1796 | return 0; | |
1797 | } | |
1798 | #endif /* CONFIG_PM */ | |
1799 | ||
1800 | #ifdef CONFIG_PM_SLEEP | |
1801 | static int dwc3_suspend(struct device *dev) | |
1802 | { | |
1803 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1804 | int ret; | |
1805 | ||
c4a5153e | 1806 | ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); |
fc8bb91b FB |
1807 | if (ret) |
1808 | return ret; | |
1809 | ||
1810 | pinctrl_pm_select_sleep_state(dev); | |
1811 | ||
1812 | return 0; | |
1813 | } | |
1814 | ||
1815 | static int dwc3_resume(struct device *dev) | |
1816 | { | |
1817 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1818 | int ret; | |
1819 | ||
1820 | pinctrl_pm_select_default_state(dev); | |
1821 | ||
c4a5153e | 1822 | ret = dwc3_resume_common(dwc, PMSG_RESUME); |
fc8bb91b FB |
1823 | if (ret) |
1824 | return ret; | |
1825 | ||
7415f17c FB |
1826 | pm_runtime_disable(dev); |
1827 | pm_runtime_set_active(dev); | |
1828 | pm_runtime_enable(dev); | |
1829 | ||
1830 | return 0; | |
1831 | } | |
7f370ed0 | 1832 | #endif /* CONFIG_PM_SLEEP */ |
7415f17c FB |
1833 | |
1834 | static const struct dev_pm_ops dwc3_dev_pm_ops = { | |
7415f17c | 1835 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) |
fc8bb91b FB |
1836 | SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, |
1837 | dwc3_runtime_idle) | |
7415f17c FB |
1838 | }; |
1839 | ||
5088b6f5 KVA |
1840 | #ifdef CONFIG_OF |
1841 | static const struct of_device_id of_dwc3_match[] = { | |
22a5aa17 FB |
1842 | { |
1843 | .compatible = "snps,dwc3" | |
1844 | }, | |
5088b6f5 KVA |
1845 | { |
1846 | .compatible = "synopsys,dwc3" | |
1847 | }, | |
1848 | { }, | |
1849 | }; | |
1850 | MODULE_DEVICE_TABLE(of, of_dwc3_match); | |
1851 | #endif | |
1852 | ||
404905a6 HK |
1853 | #ifdef CONFIG_ACPI |
1854 | ||
1855 | #define ACPI_ID_INTEL_BSW "808622B7" | |
1856 | ||
1857 | static const struct acpi_device_id dwc3_acpi_match[] = { | |
1858 | { ACPI_ID_INTEL_BSW, 0 }, | |
1859 | { }, | |
1860 | }; | |
1861 | MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); | |
1862 | #endif | |
1863 | ||
72246da4 FB |
1864 | static struct platform_driver dwc3_driver = { |
1865 | .probe = dwc3_probe, | |
7690417d | 1866 | .remove = dwc3_remove, |
72246da4 FB |
1867 | .driver = { |
1868 | .name = "dwc3", | |
5088b6f5 | 1869 | .of_match_table = of_match_ptr(of_dwc3_match), |
404905a6 | 1870 | .acpi_match_table = ACPI_PTR(dwc3_acpi_match), |
7f370ed0 | 1871 | .pm = &dwc3_dev_pm_ops, |
72246da4 | 1872 | }, |
72246da4 FB |
1873 | }; |
1874 | ||
b1116dcc TK |
1875 | module_platform_driver(dwc3_driver); |
1876 | ||
7ae4fc4d | 1877 | MODULE_ALIAS("platform:dwc3"); |
72246da4 | 1878 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); |
5945f789 | 1879 | MODULE_LICENSE("GPL v2"); |
72246da4 | 1880 | MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); |