Commit | Line | Data |
---|---|---|
5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
cbdc0f54 | 2 | /* |
72246da4 FB |
3 | * core.c - DesignWare USB3 DRD Controller Core file |
4 | * | |
10623b87 | 5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com |
72246da4 FB |
6 | * |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
72246da4 FB |
9 | */ |
10 | ||
fe8abf33 | 11 | #include <linux/clk.h> |
fa0ea13e | 12 | #include <linux/version.h> |
a72e658b | 13 | #include <linux/module.h> |
72246da4 FB |
14 | #include <linux/kernel.h> |
15 | #include <linux/slab.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/pm_runtime.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/list.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/dma-mapping.h> | |
457e84b6 | 25 | #include <linux/of.h> |
404905a6 | 26 | #include <linux/acpi.h> |
6344475f | 27 | #include <linux/pinctrl/consumer.h> |
fe8abf33 | 28 | #include <linux/reset.h> |
72246da4 FB |
29 | |
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
f7e846f0 | 32 | #include <linux/usb/of.h> |
a45c82b8 | 33 | #include <linux/usb/otg.h> |
72246da4 FB |
34 | |
35 | #include "core.h" | |
36 | #include "gadget.h" | |
37 | #include "io.h" | |
38 | ||
39 | #include "debug.h" | |
40 | ||
fc8bb91b | 41 | #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ |
8300dd23 | 42 | |
9d6173e1 TN |
43 | /** |
44 | * dwc3_get_dr_mode - Validates and sets dr_mode | |
45 | * @dwc: pointer to our context structure | |
46 | */ | |
47 | static int dwc3_get_dr_mode(struct dwc3 *dwc) | |
48 | { | |
49 | enum usb_dr_mode mode; | |
50 | struct device *dev = dwc->dev; | |
51 | unsigned int hw_mode; | |
52 | ||
53 | if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) | |
54 | dwc->dr_mode = USB_DR_MODE_OTG; | |
55 | ||
56 | mode = dwc->dr_mode; | |
57 | hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); | |
58 | ||
59 | switch (hw_mode) { | |
60 | case DWC3_GHWPARAMS0_MODE_GADGET: | |
61 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { | |
62 | dev_err(dev, | |
63 | "Controller does not support host mode.\n"); | |
64 | return -EINVAL; | |
65 | } | |
66 | mode = USB_DR_MODE_PERIPHERAL; | |
67 | break; | |
68 | case DWC3_GHWPARAMS0_MODE_HOST: | |
69 | if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { | |
70 | dev_err(dev, | |
71 | "Controller does not support device mode.\n"); | |
72 | return -EINVAL; | |
73 | } | |
74 | mode = USB_DR_MODE_HOST; | |
75 | break; | |
76 | default: | |
77 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) | |
78 | mode = USB_DR_MODE_HOST; | |
79 | else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) | |
80 | mode = USB_DR_MODE_PERIPHERAL; | |
a7700468 TN |
81 | |
82 | /* | |
89a9cc47 TN |
83 | * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG |
84 | * mode. If the controller supports DRD but the dr_mode is not | |
85 | * specified or set to OTG, then set the mode to peripheral. | |
a7700468 | 86 | */ |
89a9cc47 | 87 | if (mode == USB_DR_MODE_OTG && |
8bb14308 TN |
88 | (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || |
89 | !device_property_read_bool(dwc->dev, "usb-role-switch")) && | |
9af21dd6 | 90 | !DWC3_VER_IS_PRIOR(DWC3, 330A)) |
a7700468 | 91 | mode = USB_DR_MODE_PERIPHERAL; |
9d6173e1 TN |
92 | } |
93 | ||
94 | if (mode != dwc->dr_mode) { | |
95 | dev_warn(dev, | |
96 | "Configuration mismatch. dr_mode forced to %s\n", | |
97 | mode == USB_DR_MODE_HOST ? "host" : "gadget"); | |
98 | ||
99 | dwc->dr_mode = mode; | |
100 | } | |
101 | ||
102 | return 0; | |
103 | } | |
104 | ||
f09cc79b | 105 | void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) |
3140e8cb SAS |
106 | { |
107 | u32 reg; | |
108 | ||
109 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
110 | reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); | |
111 | reg |= DWC3_GCTL_PRTCAPDIR(mode); | |
112 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
c4a5153e MG |
113 | |
114 | dwc->current_dr_role = mode; | |
41ce1456 RQ |
115 | } |
116 | ||
f88359e1 YC |
117 | static int dwc3_core_soft_reset(struct dwc3 *dwc); |
118 | ||
41ce1456 RQ |
119 | static void __dwc3_set_mode(struct work_struct *work) |
120 | { | |
121 | struct dwc3 *dwc = work_to_dwc(work); | |
122 | unsigned long flags; | |
123 | int ret; | |
f580170f | 124 | u32 reg; |
41ce1456 | 125 | |
f88359e1 YC |
126 | mutex_lock(&dwc->mutex); |
127 | ||
c2cd3452 MK |
128 | pm_runtime_get_sync(dwc->dev); |
129 | ||
f09cc79b RQ |
130 | if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) |
131 | dwc3_otg_update(dwc, 0); | |
132 | ||
41ce1456 | 133 | if (!dwc->desired_dr_role) |
c2cd3452 | 134 | goto out; |
41ce1456 RQ |
135 | |
136 | if (dwc->desired_dr_role == dwc->current_dr_role) | |
c2cd3452 | 137 | goto out; |
41ce1456 | 138 | |
f09cc79b | 139 | if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) |
c2cd3452 | 140 | goto out; |
41ce1456 RQ |
141 | |
142 | switch (dwc->current_dr_role) { | |
143 | case DWC3_GCTL_PRTCAP_HOST: | |
144 | dwc3_host_exit(dwc); | |
145 | break; | |
146 | case DWC3_GCTL_PRTCAP_DEVICE: | |
147 | dwc3_gadget_exit(dwc); | |
148 | dwc3_event_buffers_cleanup(dwc); | |
149 | break; | |
f09cc79b RQ |
150 | case DWC3_GCTL_PRTCAP_OTG: |
151 | dwc3_otg_exit(dwc); | |
152 | spin_lock_irqsave(&dwc->lock, flags); | |
153 | dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; | |
154 | spin_unlock_irqrestore(&dwc->lock, flags); | |
155 | dwc3_otg_update(dwc, 1); | |
156 | break; | |
41ce1456 RQ |
157 | default: |
158 | break; | |
159 | } | |
160 | ||
f88359e1 YC |
161 | /* For DRD host or device mode only */ |
162 | if (dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG) { | |
163 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
164 | reg |= DWC3_GCTL_CORESOFTRESET; | |
165 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
166 | ||
167 | /* | |
168 | * Wait for internal clocks to synchronized. DWC_usb31 and | |
169 | * DWC_usb32 may need at least 50ms (less for DWC_usb3). To | |
170 | * keep it consistent across different IPs, let's wait up to | |
171 | * 100ms before clearing GCTL.CORESOFTRESET. | |
172 | */ | |
173 | msleep(100); | |
174 | ||
175 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
176 | reg &= ~DWC3_GCTL_CORESOFTRESET; | |
177 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
178 | } | |
179 | ||
41ce1456 RQ |
180 | spin_lock_irqsave(&dwc->lock, flags); |
181 | ||
182 | dwc3_set_prtcap(dwc, dwc->desired_dr_role); | |
6b3261a2 | 183 | |
41ce1456 RQ |
184 | spin_unlock_irqrestore(&dwc->lock, flags); |
185 | ||
186 | switch (dwc->desired_dr_role) { | |
187 | case DWC3_GCTL_PRTCAP_HOST: | |
188 | ret = dwc3_host_init(dwc); | |
958d1a4c | 189 | if (ret) { |
41ce1456 | 190 | dev_err(dwc->dev, "failed to initialize host\n"); |
958d1a4c FB |
191 | } else { |
192 | if (dwc->usb2_phy) | |
193 | otg_set_vbus(dwc->usb2_phy->otg, true); | |
644cbbc3 MG |
194 | phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); |
195 | phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); | |
f580170f YC |
196 | if (dwc->dis_split_quirk) { |
197 | reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); | |
198 | reg |= DWC3_GUCTL3_SPLITDISABLE; | |
199 | dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); | |
200 | } | |
958d1a4c | 201 | } |
41ce1456 RQ |
202 | break; |
203 | case DWC3_GCTL_PRTCAP_DEVICE: | |
f88359e1 YC |
204 | dwc3_core_soft_reset(dwc); |
205 | ||
41ce1456 | 206 | dwc3_event_buffers_setup(dwc); |
958d1a4c FB |
207 | |
208 | if (dwc->usb2_phy) | |
209 | otg_set_vbus(dwc->usb2_phy->otg, false); | |
644cbbc3 MG |
210 | phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); |
211 | phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); | |
958d1a4c | 212 | |
41ce1456 RQ |
213 | ret = dwc3_gadget_init(dwc); |
214 | if (ret) | |
215 | dev_err(dwc->dev, "failed to initialize peripheral\n"); | |
216 | break; | |
f09cc79b RQ |
217 | case DWC3_GCTL_PRTCAP_OTG: |
218 | dwc3_otg_init(dwc); | |
219 | dwc3_otg_update(dwc, 0); | |
220 | break; | |
41ce1456 RQ |
221 | default: |
222 | break; | |
223 | } | |
f09cc79b | 224 | |
c2cd3452 MK |
225 | out: |
226 | pm_runtime_mark_last_busy(dwc->dev); | |
227 | pm_runtime_put_autosuspend(dwc->dev); | |
f88359e1 | 228 | mutex_unlock(&dwc->mutex); |
41ce1456 RQ |
229 | } |
230 | ||
231 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode) | |
232 | { | |
233 | unsigned long flags; | |
234 | ||
dc336b19 LJ |
235 | if (dwc->dr_mode != USB_DR_MODE_OTG) |
236 | return; | |
237 | ||
41ce1456 RQ |
238 | spin_lock_irqsave(&dwc->lock, flags); |
239 | dwc->desired_dr_role = mode; | |
240 | spin_unlock_irqrestore(&dwc->lock, flags); | |
241 | ||
084a804e | 242 | queue_work(system_freezable_wq, &dwc->drd_work); |
3140e8cb | 243 | } |
8300dd23 | 244 | |
cf6d867d FB |
245 | u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) |
246 | { | |
247 | struct dwc3 *dwc = dep->dwc; | |
248 | u32 reg; | |
249 | ||
250 | dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, | |
251 | DWC3_GDBGFIFOSPACE_NUM(dep->number) | | |
252 | DWC3_GDBGFIFOSPACE_TYPE(type)); | |
253 | ||
254 | reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); | |
255 | ||
256 | return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); | |
257 | } | |
258 | ||
72246da4 FB |
259 | /** |
260 | * dwc3_core_soft_reset - Issues core soft reset and PHY reset | |
261 | * @dwc: pointer to our context structure | |
262 | */ | |
57303488 | 263 | static int dwc3_core_soft_reset(struct dwc3 *dwc) |
72246da4 FB |
264 | { |
265 | u32 reg; | |
f59dcab1 | 266 | int retries = 1000; |
57303488 | 267 | int ret; |
72246da4 | 268 | |
51e1e7bc FB |
269 | usb_phy_init(dwc->usb2_phy); |
270 | usb_phy_init(dwc->usb3_phy); | |
57303488 KVA |
271 | ret = phy_init(dwc->usb2_generic_phy); |
272 | if (ret < 0) | |
273 | return ret; | |
274 | ||
275 | ret = phy_init(dwc->usb3_generic_phy); | |
276 | if (ret < 0) { | |
277 | phy_exit(dwc->usb2_generic_phy); | |
278 | return ret; | |
279 | } | |
72246da4 | 280 | |
f59dcab1 FB |
281 | /* |
282 | * We're resetting only the device side because, if we're in host mode, | |
283 | * XHCI driver will reset the host block. If dwc3 was configured for | |
284 | * host-only mode, then we can return early. | |
285 | */ | |
c4a5153e | 286 | if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) |
f59dcab1 | 287 | return 0; |
72246da4 | 288 | |
f59dcab1 FB |
289 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
290 | reg |= DWC3_DCTL_CSFTRST; | |
291 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 292 | |
4749e0e6 TN |
293 | /* |
294 | * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit | |
295 | * is cleared only after all the clocks are synchronized. This can | |
296 | * take a little more than 50ms. Set the polling rate at 20ms | |
297 | * for 10 times instead. | |
298 | */ | |
9af21dd6 | 299 | if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) |
4749e0e6 TN |
300 | retries = 10; |
301 | ||
f59dcab1 FB |
302 | do { |
303 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
304 | if (!(reg & DWC3_DCTL_CSFTRST)) | |
fab38333 | 305 | goto done; |
45627ac6 | 306 | |
9af21dd6 | 307 | if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) |
4749e0e6 TN |
308 | msleep(20); |
309 | else | |
310 | udelay(1); | |
f59dcab1 | 311 | } while (--retries); |
57303488 | 312 | |
00b42170 BN |
313 | phy_exit(dwc->usb3_generic_phy); |
314 | phy_exit(dwc->usb2_generic_phy); | |
315 | ||
f59dcab1 | 316 | return -ETIMEDOUT; |
fab38333 TN |
317 | |
318 | done: | |
319 | /* | |
4749e0e6 TN |
320 | * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit |
321 | * is cleared, we must wait at least 50ms before accessing the PHY | |
322 | * domain (synchronization delay). | |
fab38333 | 323 | */ |
9af21dd6 | 324 | if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) |
fab38333 TN |
325 | msleep(50); |
326 | ||
327 | return 0; | |
72246da4 FB |
328 | } |
329 | ||
db2be4e9 NB |
330 | /* |
331 | * dwc3_frame_length_adjustment - Adjusts frame length if required | |
332 | * @dwc3: Pointer to our controller context structure | |
db2be4e9 | 333 | */ |
bcdb3272 | 334 | static void dwc3_frame_length_adjustment(struct dwc3 *dwc) |
db2be4e9 NB |
335 | { |
336 | u32 reg; | |
337 | u32 dft; | |
338 | ||
9af21dd6 | 339 | if (DWC3_VER_IS_PRIOR(DWC3, 250A)) |
db2be4e9 NB |
340 | return; |
341 | ||
bcdb3272 | 342 | if (dwc->fladj == 0) |
db2be4e9 NB |
343 | return; |
344 | ||
345 | reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); | |
346 | dft = reg & DWC3_GFLADJ_30MHZ_MASK; | |
a7d9874c | 347 | if (dft != dwc->fladj) { |
db2be4e9 | 348 | reg &= ~DWC3_GFLADJ_30MHZ_MASK; |
bcdb3272 | 349 | reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; |
db2be4e9 NB |
350 | dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); |
351 | } | |
352 | } | |
353 | ||
72246da4 FB |
354 | /** |
355 | * dwc3_free_one_event_buffer - Frees one event buffer | |
356 | * @dwc: Pointer to our controller context structure | |
357 | * @evt: Pointer to event buffer to be freed | |
358 | */ | |
359 | static void dwc3_free_one_event_buffer(struct dwc3 *dwc, | |
360 | struct dwc3_event_buffer *evt) | |
361 | { | |
d64ff406 | 362 | dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); |
72246da4 FB |
363 | } |
364 | ||
365 | /** | |
1d046793 | 366 | * dwc3_alloc_one_event_buffer - Allocates one event buffer structure |
72246da4 FB |
367 | * @dwc: Pointer to our controller context structure |
368 | * @length: size of the event buffer | |
369 | * | |
1d046793 | 370 | * Returns a pointer to the allocated event buffer structure on success |
72246da4 FB |
371 | * otherwise ERR_PTR(errno). |
372 | */ | |
67d0b500 FB |
373 | static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, |
374 | unsigned length) | |
72246da4 FB |
375 | { |
376 | struct dwc3_event_buffer *evt; | |
377 | ||
380f0d28 | 378 | evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); |
72246da4 FB |
379 | if (!evt) |
380 | return ERR_PTR(-ENOMEM); | |
381 | ||
382 | evt->dwc = dwc; | |
383 | evt->length = length; | |
d9fa4c63 JY |
384 | evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); |
385 | if (!evt->cache) | |
386 | return ERR_PTR(-ENOMEM); | |
387 | ||
d64ff406 | 388 | evt->buf = dma_alloc_coherent(dwc->sysdev, length, |
72246da4 | 389 | &evt->dma, GFP_KERNEL); |
e32672f0 | 390 | if (!evt->buf) |
72246da4 | 391 | return ERR_PTR(-ENOMEM); |
72246da4 FB |
392 | |
393 | return evt; | |
394 | } | |
395 | ||
396 | /** | |
397 | * dwc3_free_event_buffers - frees all allocated event buffers | |
398 | * @dwc: Pointer to our controller context structure | |
399 | */ | |
400 | static void dwc3_free_event_buffers(struct dwc3 *dwc) | |
401 | { | |
402 | struct dwc3_event_buffer *evt; | |
72246da4 | 403 | |
696c8b12 | 404 | evt = dwc->ev_buf; |
660e9bde FB |
405 | if (evt) |
406 | dwc3_free_one_event_buffer(dwc, evt); | |
72246da4 FB |
407 | } |
408 | ||
409 | /** | |
410 | * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length | |
1d046793 | 411 | * @dwc: pointer to our controller context structure |
72246da4 FB |
412 | * @length: size of event buffer |
413 | * | |
1d046793 | 414 | * Returns 0 on success otherwise negative errno. In the error case, dwc |
72246da4 FB |
415 | * may contain some buffers allocated but not all which were requested. |
416 | */ | |
41ac7b3a | 417 | static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) |
72246da4 | 418 | { |
660e9bde | 419 | struct dwc3_event_buffer *evt; |
72246da4 | 420 | |
660e9bde FB |
421 | evt = dwc3_alloc_one_event_buffer(dwc, length); |
422 | if (IS_ERR(evt)) { | |
423 | dev_err(dwc->dev, "can't allocate event buffer\n"); | |
424 | return PTR_ERR(evt); | |
72246da4 | 425 | } |
696c8b12 | 426 | dwc->ev_buf = evt; |
72246da4 FB |
427 | |
428 | return 0; | |
429 | } | |
430 | ||
431 | /** | |
432 | * dwc3_event_buffers_setup - setup our allocated event buffers | |
1d046793 | 433 | * @dwc: pointer to our controller context structure |
72246da4 FB |
434 | * |
435 | * Returns 0 on success otherwise negative errno. | |
436 | */ | |
f09cc79b | 437 | int dwc3_event_buffers_setup(struct dwc3 *dwc) |
72246da4 FB |
438 | { |
439 | struct dwc3_event_buffer *evt; | |
72246da4 | 440 | |
696c8b12 | 441 | evt = dwc->ev_buf; |
660e9bde | 442 | evt->lpos = 0; |
660e9bde FB |
443 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), |
444 | lower_32_bits(evt->dma)); | |
445 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), | |
446 | upper_32_bits(evt->dma)); | |
447 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), | |
448 | DWC3_GEVNTSIZ_SIZE(evt->length)); | |
449 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); | |
72246da4 FB |
450 | |
451 | return 0; | |
452 | } | |
453 | ||
f09cc79b | 454 | void dwc3_event_buffers_cleanup(struct dwc3 *dwc) |
72246da4 FB |
455 | { |
456 | struct dwc3_event_buffer *evt; | |
72246da4 | 457 | |
696c8b12 | 458 | evt = dwc->ev_buf; |
7acd85e0 | 459 | |
660e9bde | 460 | evt->lpos = 0; |
7acd85e0 | 461 | |
660e9bde FB |
462 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); |
463 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); | |
464 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK | |
465 | | DWC3_GEVNTSIZ_SIZE(0)); | |
466 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); | |
72246da4 FB |
467 | } |
468 | ||
0ffcaf37 FB |
469 | static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) |
470 | { | |
471 | if (!dwc->has_hibernation) | |
472 | return 0; | |
473 | ||
474 | if (!dwc->nr_scratch) | |
475 | return 0; | |
476 | ||
477 | dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, | |
478 | DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); | |
479 | if (!dwc->scratchbuf) | |
480 | return -ENOMEM; | |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
485 | static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) | |
486 | { | |
487 | dma_addr_t scratch_addr; | |
488 | u32 param; | |
489 | int ret; | |
490 | ||
491 | if (!dwc->has_hibernation) | |
492 | return 0; | |
493 | ||
494 | if (!dwc->nr_scratch) | |
495 | return 0; | |
496 | ||
497 | /* should never fall here */ | |
498 | if (!WARN_ON(dwc->scratchbuf)) | |
499 | return 0; | |
500 | ||
d64ff406 | 501 | scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, |
0ffcaf37 FB |
502 | dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, |
503 | DMA_BIDIRECTIONAL); | |
d64ff406 AB |
504 | if (dma_mapping_error(dwc->sysdev, scratch_addr)) { |
505 | dev_err(dwc->sysdev, "failed to map scratch buffer\n"); | |
0ffcaf37 FB |
506 | ret = -EFAULT; |
507 | goto err0; | |
508 | } | |
509 | ||
510 | dwc->scratch_addr = scratch_addr; | |
511 | ||
512 | param = lower_32_bits(scratch_addr); | |
513 | ||
514 | ret = dwc3_send_gadget_generic_command(dwc, | |
515 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); | |
516 | if (ret < 0) | |
517 | goto err1; | |
518 | ||
519 | param = upper_32_bits(scratch_addr); | |
520 | ||
521 | ret = dwc3_send_gadget_generic_command(dwc, | |
522 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); | |
523 | if (ret < 0) | |
524 | goto err1; | |
525 | ||
526 | return 0; | |
527 | ||
528 | err1: | |
d64ff406 | 529 | dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * |
0ffcaf37 FB |
530 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); |
531 | ||
532 | err0: | |
533 | return ret; | |
534 | } | |
535 | ||
536 | static void dwc3_free_scratch_buffers(struct dwc3 *dwc) | |
537 | { | |
538 | if (!dwc->has_hibernation) | |
539 | return; | |
540 | ||
541 | if (!dwc->nr_scratch) | |
542 | return; | |
543 | ||
544 | /* should never fall here */ | |
545 | if (!WARN_ON(dwc->scratchbuf)) | |
546 | return; | |
547 | ||
d64ff406 | 548 | dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * |
0ffcaf37 FB |
549 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); |
550 | kfree(dwc->scratchbuf); | |
551 | } | |
552 | ||
789451f6 FB |
553 | static void dwc3_core_num_eps(struct dwc3 *dwc) |
554 | { | |
555 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
556 | ||
47d3946e | 557 | dwc->num_eps = DWC3_NUM_EPS(parms); |
789451f6 FB |
558 | } |
559 | ||
41ac7b3a | 560 | static void dwc3_cache_hwparams(struct dwc3 *dwc) |
26ceca97 FB |
561 | { |
562 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
563 | ||
564 | parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); | |
565 | parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); | |
566 | parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); | |
567 | parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); | |
568 | parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); | |
569 | parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); | |
570 | parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); | |
571 | parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); | |
572 | parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); | |
16710380 TN |
573 | |
574 | if (DWC3_IP_IS(DWC32)) | |
575 | parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); | |
26ceca97 FB |
576 | } |
577 | ||
98112041 RQ |
578 | static int dwc3_core_ulpi_init(struct dwc3 *dwc) |
579 | { | |
580 | int intf; | |
581 | int ret = 0; | |
582 | ||
583 | intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); | |
584 | ||
585 | if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || | |
586 | (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && | |
587 | dwc->hsphy_interface && | |
588 | !strncmp(dwc->hsphy_interface, "ulpi", 4))) | |
589 | ret = dwc3_ulpi_init(dwc); | |
590 | ||
591 | return ret; | |
592 | } | |
593 | ||
b5a65c40 HR |
594 | /** |
595 | * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core | |
596 | * @dwc: Pointer to our controller context structure | |
88bc9d19 HK |
597 | * |
598 | * Returns 0 on success. The USB PHY interfaces are configured but not | |
599 | * initialized. The PHY interfaces and the PHYs get initialized together with | |
600 | * the core in dwc3_core_init. | |
b5a65c40 | 601 | */ |
88bc9d19 | 602 | static int dwc3_phy_setup(struct dwc3 *dwc) |
b5a65c40 | 603 | { |
9ba3aca8 | 604 | unsigned int hw_mode; |
b5a65c40 HR |
605 | u32 reg; |
606 | ||
9ba3aca8 TN |
607 | hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); |
608 | ||
b5a65c40 HR |
609 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); |
610 | ||
1966b865 FB |
611 | /* |
612 | * Make sure UX_EXIT_PX is cleared as that causes issues with some | |
613 | * PHYs. Also, this bit is not supposed to be used in normal operation. | |
614 | */ | |
615 | reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; | |
616 | ||
2164a476 HR |
617 | /* |
618 | * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY | |
619 | * to '0' during coreConsultant configuration. So default value | |
620 | * will be '0' when the core is reset. Application needs to set it | |
621 | * to '1' after the core initialization is completed. | |
622 | */ | |
9af21dd6 | 623 | if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) |
2164a476 HR |
624 | reg |= DWC3_GUSB3PIPECTL_SUSPHY; |
625 | ||
9ba3aca8 TN |
626 | /* |
627 | * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after | |
628 | * power-on reset, and it can be set after core initialization, which is | |
629 | * after device soft-reset during initialization. | |
630 | */ | |
631 | if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) | |
632 | reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; | |
633 | ||
b5a65c40 HR |
634 | if (dwc->u2ss_inp3_quirk) |
635 | reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; | |
636 | ||
e58dd357 RB |
637 | if (dwc->dis_rxdet_inp3_quirk) |
638 | reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; | |
639 | ||
df31f5b3 HR |
640 | if (dwc->req_p1p2p3_quirk) |
641 | reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; | |
642 | ||
a2a1d0f5 HR |
643 | if (dwc->del_p1p2p3_quirk) |
644 | reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; | |
645 | ||
41c06ffd HR |
646 | if (dwc->del_phy_power_chg_quirk) |
647 | reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; | |
648 | ||
fb67afca HR |
649 | if (dwc->lfps_filter_quirk) |
650 | reg |= DWC3_GUSB3PIPECTL_LFPSFILT; | |
651 | ||
14f4ac53 HR |
652 | if (dwc->rx_detect_poll_quirk) |
653 | reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; | |
654 | ||
6b6a0c9a HR |
655 | if (dwc->tx_de_emphasis_quirk) |
656 | reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); | |
657 | ||
cd72f890 | 658 | if (dwc->dis_u3_susphy_quirk) |
59acfa20 HR |
659 | reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; |
660 | ||
00fe081d WW |
661 | if (dwc->dis_del_phy_power_chg_quirk) |
662 | reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; | |
663 | ||
b5a65c40 HR |
664 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); |
665 | ||
2164a476 HR |
666 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
667 | ||
3e10a2ce HK |
668 | /* Select the HS PHY interface */ |
669 | switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { | |
670 | case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: | |
43cacb03 FB |
671 | if (dwc->hsphy_interface && |
672 | !strncmp(dwc->hsphy_interface, "utmi", 4)) { | |
3e10a2ce | 673 | reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; |
88bc9d19 | 674 | break; |
43cacb03 FB |
675 | } else if (dwc->hsphy_interface && |
676 | !strncmp(dwc->hsphy_interface, "ulpi", 4)) { | |
3e10a2ce | 677 | reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; |
88bc9d19 | 678 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
3e10a2ce | 679 | } else { |
88bc9d19 HK |
680 | /* Relying on default value. */ |
681 | if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) | |
682 | break; | |
3e10a2ce | 683 | } |
df561f66 | 684 | fallthrough; |
88bc9d19 | 685 | case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: |
3e10a2ce HK |
686 | default: |
687 | break; | |
688 | } | |
689 | ||
32f2ed86 WW |
690 | switch (dwc->hsphy_mode) { |
691 | case USBPHY_INTERFACE_MODE_UTMI: | |
692 | reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | | |
693 | DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); | |
694 | reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | | |
695 | DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); | |
696 | break; | |
697 | case USBPHY_INTERFACE_MODE_UTMIW: | |
698 | reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | | |
699 | DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); | |
700 | reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | | |
701 | DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); | |
702 | break; | |
703 | default: | |
704 | break; | |
705 | } | |
706 | ||
2164a476 HR |
707 | /* |
708 | * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to | |
709 | * '0' during coreConsultant configuration. So default value will | |
710 | * be '0' when the core is reset. Application needs to set it to | |
711 | * '1' after the core initialization is completed. | |
712 | */ | |
9af21dd6 | 713 | if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) |
2164a476 HR |
714 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; |
715 | ||
9ba3aca8 TN |
716 | /* |
717 | * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after | |
718 | * power-on reset, and it can be set after core initialization, which is | |
719 | * after device soft-reset during initialization. | |
720 | */ | |
721 | if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) | |
722 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; | |
723 | ||
cd72f890 | 724 | if (dwc->dis_u2_susphy_quirk) |
0effe0a3 HR |
725 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; |
726 | ||
ec791d14 JY |
727 | if (dwc->dis_enblslpm_quirk) |
728 | reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; | |
eafeacf1 TN |
729 | else |
730 | reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; | |
ec791d14 | 731 | |
16199f33 WW |
732 | if (dwc->dis_u2_freeclk_exists_quirk) |
733 | reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; | |
734 | ||
2164a476 | 735 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
88bc9d19 HK |
736 | |
737 | return 0; | |
b5a65c40 HR |
738 | } |
739 | ||
c499ff71 FB |
740 | static void dwc3_core_exit(struct dwc3 *dwc) |
741 | { | |
742 | dwc3_event_buffers_cleanup(dwc); | |
743 | ||
744 | usb_phy_shutdown(dwc->usb2_phy); | |
745 | usb_phy_shutdown(dwc->usb3_phy); | |
746 | phy_exit(dwc->usb2_generic_phy); | |
747 | phy_exit(dwc->usb3_generic_phy); | |
748 | ||
749 | usb_phy_set_suspend(dwc->usb2_phy, 1); | |
750 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
751 | phy_power_off(dwc->usb2_generic_phy); | |
752 | phy_power_off(dwc->usb3_generic_phy); | |
240b65dc | 753 | clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); |
fe8abf33 | 754 | reset_control_assert(dwc->reset); |
c499ff71 FB |
755 | } |
756 | ||
0759956f | 757 | static bool dwc3_core_is_valid(struct dwc3 *dwc) |
72246da4 | 758 | { |
0759956f | 759 | u32 reg; |
72246da4 | 760 | |
7650bd74 | 761 | reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); |
9af21dd6 | 762 | dwc->ip = DWC3_GSNPS_ID(reg); |
0759956f | 763 | |
7650bd74 | 764 | /* This should read as U3 followed by revision number */ |
9af21dd6 | 765 | if (DWC3_IP_IS(DWC3)) { |
690fb371 | 766 | dwc->revision = reg; |
9af21dd6 | 767 | } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { |
690fb371 | 768 | dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); |
475d8e01 | 769 | dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); |
690fb371 | 770 | } else { |
0759956f | 771 | return false; |
7650bd74 | 772 | } |
7650bd74 | 773 | |
0759956f FB |
774 | return true; |
775 | } | |
58a0f23f | 776 | |
941f918e | 777 | static void dwc3_core_setup_global_control(struct dwc3 *dwc) |
0759956f | 778 | { |
941f918e FB |
779 | u32 hwparams4 = dwc->hwparams.hwparams4; |
780 | u32 reg; | |
c499ff71 | 781 | |
4878a028 | 782 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); |
3e87c42a | 783 | reg &= ~DWC3_GCTL_SCALEDOWN_MASK; |
4878a028 | 784 | |
164d7731 | 785 | switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { |
4878a028 | 786 | case DWC3_GHWPARAMS1_EN_PWROPT_CLK: |
32a4a135 FB |
787 | /** |
788 | * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an | |
789 | * issue which would cause xHCI compliance tests to fail. | |
790 | * | |
791 | * Because of that we cannot enable clock gating on such | |
792 | * configurations. | |
793 | * | |
794 | * Refers to: | |
795 | * | |
796 | * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based | |
797 | * SOF/ITP Mode Used | |
798 | */ | |
799 | if ((dwc->dr_mode == USB_DR_MODE_HOST || | |
800 | dwc->dr_mode == USB_DR_MODE_OTG) && | |
9af21dd6 | 801 | DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) |
32a4a135 FB |
802 | reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; |
803 | else | |
804 | reg &= ~DWC3_GCTL_DSBLCLKGTNG; | |
4878a028 | 805 | break; |
0ffcaf37 FB |
806 | case DWC3_GHWPARAMS1_EN_PWROPT_HIB: |
807 | /* enable hibernation here */ | |
808 | dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); | |
2eac3992 HR |
809 | |
810 | /* | |
811 | * REVISIT Enabling this bit so that host-mode hibernation | |
812 | * will work. Device-mode hibernation is not yet implemented. | |
813 | */ | |
814 | reg |= DWC3_GCTL_GBLHIBERNATIONEN; | |
0ffcaf37 | 815 | break; |
4878a028 | 816 | default: |
5eb30ced FB |
817 | /* nothing */ |
818 | break; | |
4878a028 SAS |
819 | } |
820 | ||
946bd579 HR |
821 | /* check if current dwc3 is on simulation board */ |
822 | if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { | |
6af19fd1 | 823 | dev_info(dwc->dev, "Running with FPGA optimizations\n"); |
946bd579 HR |
824 | dwc->is_fpga = true; |
825 | } | |
826 | ||
3b81221a HR |
827 | WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, |
828 | "disable_scramble cannot be used on non-FPGA builds\n"); | |
829 | ||
830 | if (dwc->disable_scramble_quirk && dwc->is_fpga) | |
831 | reg |= DWC3_GCTL_DISSCRAMBLE; | |
832 | else | |
833 | reg &= ~DWC3_GCTL_DISSCRAMBLE; | |
834 | ||
9a5b2f31 HR |
835 | if (dwc->u2exit_lfps_quirk) |
836 | reg |= DWC3_GCTL_U2EXIT_LFPS; | |
837 | ||
4878a028 SAS |
838 | /* |
839 | * WORKAROUND: DWC3 revisions <1.90a have a bug | |
1d046793 | 840 | * where the device can fail to connect at SuperSpeed |
4878a028 | 841 | * and falls back to high-speed mode which causes |
1d046793 | 842 | * the device to enter a Connect/Disconnect loop |
4878a028 | 843 | */ |
9af21dd6 | 844 | if (DWC3_VER_IS_PRIOR(DWC3, 190A)) |
4878a028 SAS |
845 | reg |= DWC3_GCTL_U2RSTECN; |
846 | ||
847 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
941f918e FB |
848 | } |
849 | ||
f54edb53 | 850 | static int dwc3_core_get_phy(struct dwc3 *dwc); |
98112041 | 851 | static int dwc3_core_ulpi_init(struct dwc3 *dwc); |
f54edb53 | 852 | |
d9612c2f PM |
853 | /* set global incr burst type configuration registers */ |
854 | static void dwc3_set_incr_burst_type(struct dwc3 *dwc) | |
855 | { | |
856 | struct device *dev = dwc->dev; | |
857 | /* incrx_mode : for INCR burst type. */ | |
858 | bool incrx_mode; | |
859 | /* incrx_size : for size of INCRX burst. */ | |
860 | u32 incrx_size; | |
861 | u32 *vals; | |
862 | u32 cfg; | |
863 | int ntype; | |
864 | int ret; | |
865 | int i; | |
866 | ||
867 | cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); | |
868 | ||
869 | /* | |
870 | * Handle property "snps,incr-burst-type-adjustment". | |
871 | * Get the number of value from this property: | |
872 | * result <= 0, means this property is not supported. | |
873 | * result = 1, means INCRx burst mode supported. | |
874 | * result > 1, means undefined length burst mode supported. | |
875 | */ | |
a6e5e679 | 876 | ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); |
d9612c2f PM |
877 | if (ntype <= 0) |
878 | return; | |
879 | ||
880 | vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); | |
881 | if (!vals) { | |
882 | dev_err(dev, "Error to get memory\n"); | |
883 | return; | |
884 | } | |
885 | ||
886 | /* Get INCR burst type, and parse it */ | |
887 | ret = device_property_read_u32_array(dev, | |
888 | "snps,incr-burst-type-adjustment", vals, ntype); | |
889 | if (ret) { | |
75ecb9dd | 890 | kfree(vals); |
d9612c2f PM |
891 | dev_err(dev, "Error to get property\n"); |
892 | return; | |
893 | } | |
894 | ||
895 | incrx_size = *vals; | |
896 | ||
897 | if (ntype > 1) { | |
898 | /* INCRX (undefined length) burst mode */ | |
899 | incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; | |
900 | for (i = 1; i < ntype; i++) { | |
901 | if (vals[i] > incrx_size) | |
902 | incrx_size = vals[i]; | |
903 | } | |
904 | } else { | |
905 | /* INCRX burst mode */ | |
906 | incrx_mode = INCRX_BURST_MODE; | |
907 | } | |
908 | ||
75ecb9dd AS |
909 | kfree(vals); |
910 | ||
d9612c2f PM |
911 | /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ |
912 | cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; | |
913 | if (incrx_mode) | |
914 | cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; | |
915 | switch (incrx_size) { | |
916 | case 256: | |
917 | cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; | |
918 | break; | |
919 | case 128: | |
920 | cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; | |
921 | break; | |
922 | case 64: | |
923 | cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; | |
924 | break; | |
925 | case 32: | |
926 | cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; | |
927 | break; | |
928 | case 16: | |
929 | cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; | |
930 | break; | |
931 | case 8: | |
932 | cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; | |
933 | break; | |
934 | case 4: | |
935 | cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; | |
936 | break; | |
937 | case 1: | |
938 | break; | |
939 | default: | |
940 | dev_err(dev, "Invalid property\n"); | |
941 | break; | |
942 | } | |
943 | ||
944 | dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); | |
945 | } | |
946 | ||
941f918e FB |
947 | /** |
948 | * dwc3_core_init - Low-level initialization of DWC3 Core | |
949 | * @dwc: Pointer to our controller context structure | |
950 | * | |
951 | * Returns 0 on success otherwise negative errno. | |
952 | */ | |
953 | static int dwc3_core_init(struct dwc3 *dwc) | |
954 | { | |
9ba3aca8 | 955 | unsigned int hw_mode; |
941f918e FB |
956 | u32 reg; |
957 | int ret; | |
958 | ||
9ba3aca8 TN |
959 | hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); |
960 | ||
941f918e FB |
961 | /* |
962 | * Write Linux Version Code to our GUID register so it's easy to figure | |
963 | * out which kernel version a bug was found. | |
964 | */ | |
965 | dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); | |
966 | ||
98112041 | 967 | ret = dwc3_phy_setup(dwc); |
941f918e FB |
968 | if (ret) |
969 | goto err0; | |
4878a028 | 970 | |
98112041 RQ |
971 | if (!dwc->ulpi_ready) { |
972 | ret = dwc3_core_ulpi_init(dwc); | |
973 | if (ret) | |
974 | goto err0; | |
975 | dwc->ulpi_ready = true; | |
976 | } | |
4878a028 | 977 | |
98112041 RQ |
978 | if (!dwc->phys_ready) { |
979 | ret = dwc3_core_get_phy(dwc); | |
980 | if (ret) | |
981 | goto err0a; | |
982 | dwc->phys_ready = true; | |
983 | } | |
984 | ||
985 | ret = dwc3_core_soft_reset(dwc); | |
f54edb53 | 986 | if (ret) |
98112041 | 987 | goto err0a; |
f54edb53 | 988 | |
9ba3aca8 | 989 | if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && |
9af21dd6 | 990 | !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { |
9ba3aca8 TN |
991 | if (!dwc->dis_u3_susphy_quirk) { |
992 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
993 | reg |= DWC3_GUSB3PIPECTL_SUSPHY; | |
994 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
995 | } | |
996 | ||
997 | if (!dwc->dis_u2_susphy_quirk) { | |
998 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
999 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; | |
1000 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
1001 | } | |
1002 | } | |
1003 | ||
941f918e | 1004 | dwc3_core_setup_global_control(dwc); |
c499ff71 | 1005 | dwc3_core_num_eps(dwc); |
0ffcaf37 FB |
1006 | |
1007 | ret = dwc3_setup_scratch_buffers(dwc); | |
1008 | if (ret) | |
c499ff71 FB |
1009 | goto err1; |
1010 | ||
1011 | /* Adjust Frame Length */ | |
1012 | dwc3_frame_length_adjustment(dwc); | |
1013 | ||
d9612c2f PM |
1014 | dwc3_set_incr_burst_type(dwc); |
1015 | ||
c499ff71 FB |
1016 | usb_phy_set_suspend(dwc->usb2_phy, 0); |
1017 | usb_phy_set_suspend(dwc->usb3_phy, 0); | |
1018 | ret = phy_power_on(dwc->usb2_generic_phy); | |
1019 | if (ret < 0) | |
0ffcaf37 FB |
1020 | goto err2; |
1021 | ||
c499ff71 FB |
1022 | ret = phy_power_on(dwc->usb3_generic_phy); |
1023 | if (ret < 0) | |
1024 | goto err3; | |
1025 | ||
1026 | ret = dwc3_event_buffers_setup(dwc); | |
1027 | if (ret) { | |
1028 | dev_err(dwc->dev, "failed to setup event buffers\n"); | |
1029 | goto err4; | |
1030 | } | |
1031 | ||
06281d46 JY |
1032 | /* |
1033 | * ENDXFER polling is available on version 3.10a and later of | |
1034 | * the DWC_usb3 controller. It is NOT available in the | |
1035 | * DWC_usb31 controller. | |
1036 | */ | |
9af21dd6 | 1037 | if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { |
06281d46 JY |
1038 | reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); |
1039 | reg |= DWC3_GUCTL2_RST_ACTBITLATER; | |
1040 | dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); | |
1041 | } | |
1042 | ||
9af21dd6 | 1043 | if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { |
0bb39ca1 | 1044 | reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); |
65db7a0c WW |
1045 | |
1046 | /* | |
1047 | * Enable hardware control of sending remote wakeup | |
1048 | * in HS when the device is in the L1 state. | |
1049 | */ | |
9af21dd6 | 1050 | if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) |
65db7a0c WW |
1051 | reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; |
1052 | ||
843714bb JP |
1053 | /* |
1054 | * Decouple USB 2.0 L1 & L2 events which will allow for | |
1055 | * gadget driver to only receive U3/L2 suspend & wakeup | |
1056 | * events and prevent the more frequent L1 LPM transitions | |
1057 | * from interrupting the driver. | |
1058 | */ | |
1059 | if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) | |
1060 | reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; | |
1061 | ||
65db7a0c WW |
1062 | if (dwc->dis_tx_ipgap_linecheck_quirk) |
1063 | reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; | |
1064 | ||
7ba6b09f NA |
1065 | if (dwc->parkmode_disable_ss_quirk) |
1066 | reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; | |
1067 | ||
0bb39ca1 JY |
1068 | dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); |
1069 | } | |
1070 | ||
b138e23d AKV |
1071 | if (dwc->dr_mode == USB_DR_MODE_HOST || |
1072 | dwc->dr_mode == USB_DR_MODE_OTG) { | |
1073 | reg = dwc3_readl(dwc->regs, DWC3_GUCTL); | |
1074 | ||
1075 | /* | |
1076 | * Enable Auto retry Feature to make the controller operating in | |
1077 | * Host mode on seeing transaction errors(CRC errors or internal | |
1078 | * overrun scenerios) on IN transfers to reply to the device | |
1079 | * with a non-terminating retry ACK (i.e, an ACK transcation | |
1080 | * packet with Retry=1 & Nump != 0) | |
1081 | */ | |
1082 | reg |= DWC3_GUCTL_HSTINAUTORETRY; | |
1083 | ||
1084 | dwc3_writel(dwc->regs, DWC3_GUCTL, reg); | |
1085 | } | |
1086 | ||
938a5ad1 TN |
1087 | /* |
1088 | * Must config both number of packets and max burst settings to enable | |
1089 | * RX and/or TX threshold. | |
1090 | */ | |
9af21dd6 | 1091 | if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { |
938a5ad1 TN |
1092 | u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; |
1093 | u8 rx_maxburst = dwc->rx_max_burst_prd; | |
1094 | u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; | |
1095 | u8 tx_maxburst = dwc->tx_max_burst_prd; | |
1096 | ||
1097 | if (rx_thr_num && rx_maxburst) { | |
1098 | reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); | |
1099 | reg |= DWC31_RXTHRNUMPKTSEL_PRD; | |
1100 | ||
1101 | reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); | |
1102 | reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); | |
1103 | ||
1104 | reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); | |
1105 | reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); | |
1106 | ||
1107 | dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); | |
1108 | } | |
1109 | ||
1110 | if (tx_thr_num && tx_maxburst) { | |
1111 | reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); | |
1112 | reg |= DWC31_TXTHRNUMPKTSEL_PRD; | |
1113 | ||
1114 | reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); | |
1115 | reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); | |
1116 | ||
1117 | reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); | |
1118 | reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); | |
1119 | ||
1120 | dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); | |
1121 | } | |
1122 | } | |
1123 | ||
72246da4 FB |
1124 | return 0; |
1125 | ||
c499ff71 | 1126 | err4: |
9b9d7cdd | 1127 | phy_power_off(dwc->usb3_generic_phy); |
c499ff71 FB |
1128 | |
1129 | err3: | |
9b9d7cdd | 1130 | phy_power_off(dwc->usb2_generic_phy); |
c499ff71 | 1131 | |
0ffcaf37 | 1132 | err2: |
c499ff71 FB |
1133 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
1134 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
0ffcaf37 FB |
1135 | |
1136 | err1: | |
1137 | usb_phy_shutdown(dwc->usb2_phy); | |
1138 | usb_phy_shutdown(dwc->usb3_phy); | |
57303488 KVA |
1139 | phy_exit(dwc->usb2_generic_phy); |
1140 | phy_exit(dwc->usb3_generic_phy); | |
0ffcaf37 | 1141 | |
98112041 RQ |
1142 | err0a: |
1143 | dwc3_ulpi_exit(dwc); | |
1144 | ||
72246da4 FB |
1145 | err0: |
1146 | return ret; | |
1147 | } | |
1148 | ||
3c9f94ac | 1149 | static int dwc3_core_get_phy(struct dwc3 *dwc) |
72246da4 | 1150 | { |
3c9f94ac | 1151 | struct device *dev = dwc->dev; |
941ea361 | 1152 | struct device_node *node = dev->of_node; |
3c9f94ac | 1153 | int ret; |
72246da4 | 1154 | |
5088b6f5 KVA |
1155 | if (node) { |
1156 | dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); | |
1157 | dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); | |
bb674907 FB |
1158 | } else { |
1159 | dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); | |
1160 | dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); | |
5088b6f5 KVA |
1161 | } |
1162 | ||
d105e7f8 FB |
1163 | if (IS_ERR(dwc->usb2_phy)) { |
1164 | ret = PTR_ERR(dwc->usb2_phy); | |
122f06e6 KVA |
1165 | if (ret == -ENXIO || ret == -ENODEV) { |
1166 | dwc->usb2_phy = NULL; | |
122f06e6 | 1167 | } else { |
0c0a20f6 | 1168 | return dev_err_probe(dev, ret, "no usb2 phy configured\n"); |
122f06e6 | 1169 | } |
51e1e7bc FB |
1170 | } |
1171 | ||
d105e7f8 | 1172 | if (IS_ERR(dwc->usb3_phy)) { |
315955d7 | 1173 | ret = PTR_ERR(dwc->usb3_phy); |
122f06e6 KVA |
1174 | if (ret == -ENXIO || ret == -ENODEV) { |
1175 | dwc->usb3_phy = NULL; | |
122f06e6 | 1176 | } else { |
0c0a20f6 | 1177 | return dev_err_probe(dev, ret, "no usb3 phy configured\n"); |
122f06e6 | 1178 | } |
51e1e7bc FB |
1179 | } |
1180 | ||
57303488 KVA |
1181 | dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); |
1182 | if (IS_ERR(dwc->usb2_generic_phy)) { | |
1183 | ret = PTR_ERR(dwc->usb2_generic_phy); | |
1184 | if (ret == -ENOSYS || ret == -ENODEV) { | |
1185 | dwc->usb2_generic_phy = NULL; | |
57303488 | 1186 | } else { |
0c0a20f6 | 1187 | return dev_err_probe(dev, ret, "no usb2 phy configured\n"); |
57303488 KVA |
1188 | } |
1189 | } | |
1190 | ||
1191 | dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); | |
1192 | if (IS_ERR(dwc->usb3_generic_phy)) { | |
1193 | ret = PTR_ERR(dwc->usb3_generic_phy); | |
1194 | if (ret == -ENOSYS || ret == -ENODEV) { | |
1195 | dwc->usb3_generic_phy = NULL; | |
57303488 | 1196 | } else { |
0c0a20f6 | 1197 | return dev_err_probe(dev, ret, "no usb3 phy configured\n"); |
57303488 KVA |
1198 | } |
1199 | } | |
1200 | ||
3c9f94ac FB |
1201 | return 0; |
1202 | } | |
1203 | ||
5f94adfe FB |
1204 | static int dwc3_core_init_mode(struct dwc3 *dwc) |
1205 | { | |
1206 | struct device *dev = dwc->dev; | |
1207 | int ret; | |
1208 | ||
1209 | switch (dwc->dr_mode) { | |
1210 | case USB_DR_MODE_PERIPHERAL: | |
41ce1456 | 1211 | dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); |
958d1a4c FB |
1212 | |
1213 | if (dwc->usb2_phy) | |
1214 | otg_set_vbus(dwc->usb2_phy->otg, false); | |
644cbbc3 MG |
1215 | phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); |
1216 | phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); | |
958d1a4c | 1217 | |
5f94adfe | 1218 | ret = dwc3_gadget_init(dwc); |
0c0a20f6 AS |
1219 | if (ret) |
1220 | return dev_err_probe(dev, ret, "failed to initialize gadget\n"); | |
5f94adfe FB |
1221 | break; |
1222 | case USB_DR_MODE_HOST: | |
41ce1456 | 1223 | dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); |
958d1a4c FB |
1224 | |
1225 | if (dwc->usb2_phy) | |
1226 | otg_set_vbus(dwc->usb2_phy->otg, true); | |
644cbbc3 MG |
1227 | phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); |
1228 | phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); | |
958d1a4c | 1229 | |
5f94adfe | 1230 | ret = dwc3_host_init(dwc); |
0c0a20f6 AS |
1231 | if (ret) |
1232 | return dev_err_probe(dev, ret, "failed to initialize host\n"); | |
5f94adfe FB |
1233 | break; |
1234 | case USB_DR_MODE_OTG: | |
41ce1456 | 1235 | INIT_WORK(&dwc->drd_work, __dwc3_set_mode); |
9840354f | 1236 | ret = dwc3_drd_init(dwc); |
0c0a20f6 AS |
1237 | if (ret) |
1238 | return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); | |
5f94adfe FB |
1239 | break; |
1240 | default: | |
1241 | dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); | |
1242 | return -EINVAL; | |
1243 | } | |
1244 | ||
1245 | return 0; | |
1246 | } | |
1247 | ||
1248 | static void dwc3_core_exit_mode(struct dwc3 *dwc) | |
1249 | { | |
1250 | switch (dwc->dr_mode) { | |
1251 | case USB_DR_MODE_PERIPHERAL: | |
1252 | dwc3_gadget_exit(dwc); | |
1253 | break; | |
1254 | case USB_DR_MODE_HOST: | |
1255 | dwc3_host_exit(dwc); | |
1256 | break; | |
1257 | case USB_DR_MODE_OTG: | |
9840354f | 1258 | dwc3_drd_exit(dwc); |
5f94adfe FB |
1259 | break; |
1260 | default: | |
1261 | /* do nothing */ | |
1262 | break; | |
1263 | } | |
09ed259f BL |
1264 | |
1265 | /* de-assert DRVVBUS for HOST and OTG mode */ | |
1266 | dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); | |
5f94adfe FB |
1267 | } |
1268 | ||
c5ac6116 | 1269 | static void dwc3_get_properties(struct dwc3 *dwc) |
3c9f94ac | 1270 | { |
c5ac6116 | 1271 | struct device *dev = dwc->dev; |
80caf7d2 | 1272 | u8 lpm_nyet_threshold; |
6b6a0c9a | 1273 | u8 tx_de_emphasis; |
460d098c | 1274 | u8 hird_threshold; |
938a5ad1 TN |
1275 | u8 rx_thr_num_pkt_prd; |
1276 | u8 rx_max_burst_prd; | |
1277 | u8 tx_thr_num_pkt_prd; | |
1278 | u8 tx_max_burst_prd; | |
9f607a30 | 1279 | u8 tx_fifo_resize_max_num; |
6f0764b5 RC |
1280 | const char *usb_psy_name; |
1281 | int ret; | |
3c9f94ac | 1282 | |
80caf7d2 | 1283 | /* default to highest possible threshold */ |
8d791929 | 1284 | lpm_nyet_threshold = 0xf; |
80caf7d2 | 1285 | |
6b6a0c9a HR |
1286 | /* default to -3.5dB de-emphasis */ |
1287 | tx_de_emphasis = 1; | |
1288 | ||
460d098c HR |
1289 | /* |
1290 | * default to assert utmi_sleep_n and use maximum allowed HIRD | |
1291 | * threshold value of 0b1100 | |
1292 | */ | |
1293 | hird_threshold = 12; | |
1294 | ||
9f607a30 WC |
1295 | /* |
1296 | * default to a TXFIFO size large enough to fit 6 max packets. This | |
1297 | * allows for systems with larger bus latencies to have some headroom | |
1298 | * for endpoints that have a large bMaxBurst value. | |
1299 | */ | |
1300 | tx_fifo_resize_max_num = 6; | |
1301 | ||
63863b98 | 1302 | dwc->maximum_speed = usb_get_maximum_speed(dev); |
67848146 | 1303 | dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); |
06e7114f | 1304 | dwc->dr_mode = usb_get_dr_mode(dev); |
32f2ed86 | 1305 | dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); |
63863b98 | 1306 | |
d64ff406 AB |
1307 | dwc->sysdev_is_parent = device_property_read_bool(dev, |
1308 | "linux,sysdev_is_parent"); | |
1309 | if (dwc->sysdev_is_parent) | |
1310 | dwc->sysdev = dwc->dev->parent; | |
1311 | else | |
1312 | dwc->sysdev = dwc->dev; | |
1313 | ||
6f0764b5 RC |
1314 | ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); |
1315 | if (ret >= 0) { | |
1316 | dwc->usb_psy = power_supply_get_by_name(usb_psy_name); | |
1317 | if (!dwc->usb_psy) | |
1318 | dev_err(dev, "couldn't get usb power supply\n"); | |
1319 | } | |
1320 | ||
3d128919 | 1321 | dwc->has_lpm_erratum = device_property_read_bool(dev, |
80caf7d2 | 1322 | "snps,has-lpm-erratum"); |
3d128919 | 1323 | device_property_read_u8(dev, "snps,lpm-nyet-threshold", |
80caf7d2 | 1324 | &lpm_nyet_threshold); |
3d128919 | 1325 | dwc->is_utmi_l1_suspend = device_property_read_bool(dev, |
460d098c | 1326 | "snps,is-utmi-l1-suspend"); |
3d128919 | 1327 | device_property_read_u8(dev, "snps,hird-threshold", |
460d098c | 1328 | &hird_threshold); |
d92021f6 TN |
1329 | dwc->dis_start_transfer_quirk = device_property_read_bool(dev, |
1330 | "snps,dis-start-transfer-quirk"); | |
3d128919 | 1331 | dwc->usb3_lpm_capable = device_property_read_bool(dev, |
eac68e8f | 1332 | "snps,usb3_lpm_capable"); |
022a0208 TN |
1333 | dwc->usb2_lpm_disable = device_property_read_bool(dev, |
1334 | "snps,usb2-lpm-disable"); | |
475e8be5 TN |
1335 | dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, |
1336 | "snps,usb2-gadget-lpm-disable"); | |
938a5ad1 TN |
1337 | device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", |
1338 | &rx_thr_num_pkt_prd); | |
1339 | device_property_read_u8(dev, "snps,rx-max-burst-prd", | |
1340 | &rx_max_burst_prd); | |
1341 | device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", | |
1342 | &tx_thr_num_pkt_prd); | |
1343 | device_property_read_u8(dev, "snps,tx-max-burst-prd", | |
1344 | &tx_max_burst_prd); | |
9f607a30 WC |
1345 | dwc->do_fifo_resize = device_property_read_bool(dev, |
1346 | "tx-fifo-resize"); | |
1347 | if (dwc->do_fifo_resize) | |
1348 | device_property_read_u8(dev, "tx-fifo-max-num", | |
1349 | &tx_fifo_resize_max_num); | |
3c9f94ac | 1350 | |
3d128919 | 1351 | dwc->disable_scramble_quirk = device_property_read_bool(dev, |
3b81221a | 1352 | "snps,disable_scramble_quirk"); |
3d128919 | 1353 | dwc->u2exit_lfps_quirk = device_property_read_bool(dev, |
9a5b2f31 | 1354 | "snps,u2exit_lfps_quirk"); |
3d128919 | 1355 | dwc->u2ss_inp3_quirk = device_property_read_bool(dev, |
b5a65c40 | 1356 | "snps,u2ss_inp3_quirk"); |
3d128919 | 1357 | dwc->req_p1p2p3_quirk = device_property_read_bool(dev, |
df31f5b3 | 1358 | "snps,req_p1p2p3_quirk"); |
3d128919 | 1359 | dwc->del_p1p2p3_quirk = device_property_read_bool(dev, |
a2a1d0f5 | 1360 | "snps,del_p1p2p3_quirk"); |
3d128919 | 1361 | dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, |
41c06ffd | 1362 | "snps,del_phy_power_chg_quirk"); |
3d128919 | 1363 | dwc->lfps_filter_quirk = device_property_read_bool(dev, |
fb67afca | 1364 | "snps,lfps_filter_quirk"); |
3d128919 | 1365 | dwc->rx_detect_poll_quirk = device_property_read_bool(dev, |
14f4ac53 | 1366 | "snps,rx_detect_poll_quirk"); |
3d128919 | 1367 | dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, |
59acfa20 | 1368 | "snps,dis_u3_susphy_quirk"); |
3d128919 | 1369 | dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, |
0effe0a3 | 1370 | "snps,dis_u2_susphy_quirk"); |
ec791d14 JY |
1371 | dwc->dis_enblslpm_quirk = device_property_read_bool(dev, |
1372 | "snps,dis_enblslpm_quirk"); | |
729dcffd AKV |
1373 | dwc->dis_u1_entry_quirk = device_property_read_bool(dev, |
1374 | "snps,dis-u1-entry-quirk"); | |
1375 | dwc->dis_u2_entry_quirk = device_property_read_bool(dev, | |
1376 | "snps,dis-u2-entry-quirk"); | |
e58dd357 RB |
1377 | dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, |
1378 | "snps,dis_rxdet_inp3_quirk"); | |
16199f33 WW |
1379 | dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, |
1380 | "snps,dis-u2-freeclk-exists-quirk"); | |
00fe081d WW |
1381 | dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, |
1382 | "snps,dis-del-phy-power-chg-quirk"); | |
65db7a0c WW |
1383 | dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, |
1384 | "snps,dis-tx-ipgap-linecheck-quirk"); | |
7ba6b09f NA |
1385 | dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, |
1386 | "snps,parkmode-disable-ss-quirk"); | |
6b6a0c9a | 1387 | |
3d128919 | 1388 | dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, |
6b6a0c9a | 1389 | "snps,tx_de_emphasis_quirk"); |
3d128919 | 1390 | device_property_read_u8(dev, "snps,tx_de_emphasis", |
6b6a0c9a | 1391 | &tx_de_emphasis); |
3d128919 HK |
1392 | device_property_read_string(dev, "snps,hsphy_interface", |
1393 | &dwc->hsphy_interface); | |
1394 | device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", | |
bcdb3272 | 1395 | &dwc->fladj); |
3d128919 | 1396 | |
42bf02ec RQ |
1397 | dwc->dis_metastability_quirk = device_property_read_bool(dev, |
1398 | "snps,dis_metastability_quirk"); | |
1399 | ||
f580170f YC |
1400 | dwc->dis_split_quirk = device_property_read_bool(dev, |
1401 | "snps,dis-split-quirk"); | |
1402 | ||
80caf7d2 | 1403 | dwc->lpm_nyet_threshold = lpm_nyet_threshold; |
6b6a0c9a | 1404 | dwc->tx_de_emphasis = tx_de_emphasis; |
80caf7d2 | 1405 | |
16fe4f30 | 1406 | dwc->hird_threshold = hird_threshold; |
460d098c | 1407 | |
938a5ad1 TN |
1408 | dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; |
1409 | dwc->rx_max_burst_prd = rx_max_burst_prd; | |
1410 | ||
1411 | dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; | |
1412 | dwc->tx_max_burst_prd = tx_max_burst_prd; | |
1413 | ||
cf40b86b | 1414 | dwc->imod_interval = 0; |
9f607a30 WC |
1415 | |
1416 | dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; | |
cf40b86b JY |
1417 | } |
1418 | ||
1419 | /* check whether the core supports IMOD */ | |
1420 | bool dwc3_has_imod(struct dwc3 *dwc) | |
1421 | { | |
9af21dd6 TN |
1422 | return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || |
1423 | DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || | |
1424 | DWC3_IP_IS(DWC32); | |
c5ac6116 FB |
1425 | } |
1426 | ||
7ac51a12 JY |
1427 | static void dwc3_check_params(struct dwc3 *dwc) |
1428 | { | |
1429 | struct device *dev = dwc->dev; | |
b574ce3e TN |
1430 | unsigned int hwparam_gen = |
1431 | DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); | |
7ac51a12 | 1432 | |
cf40b86b JY |
1433 | /* Check for proper value of imod_interval */ |
1434 | if (dwc->imod_interval && !dwc3_has_imod(dwc)) { | |
1435 | dev_warn(dwc->dev, "Interrupt moderation not supported\n"); | |
1436 | dwc->imod_interval = 0; | |
1437 | } | |
1438 | ||
28632b44 JY |
1439 | /* |
1440 | * Workaround for STAR 9000961433 which affects only version | |
1441 | * 3.00a of the DWC_usb3 core. This prevents the controller | |
1442 | * interrupt from being masked while handling events. IMOD | |
1443 | * allows us to work around this issue. Enable it for the | |
1444 | * affected version. | |
1445 | */ | |
1446 | if (!dwc->imod_interval && | |
9af21dd6 | 1447 | DWC3_VER_IS(DWC3, 300A)) |
28632b44 JY |
1448 | dwc->imod_interval = 1; |
1449 | ||
7ac51a12 JY |
1450 | /* Check the maximum_speed parameter */ |
1451 | switch (dwc->maximum_speed) { | |
7ac51a12 JY |
1452 | case USB_SPEED_FULL: |
1453 | case USB_SPEED_HIGH: | |
e518bdd9 | 1454 | break; |
7ac51a12 | 1455 | case USB_SPEED_SUPER: |
e518bdd9 TN |
1456 | if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) |
1457 | dev_warn(dev, "UDC doesn't support Gen 1\n"); | |
1458 | break; | |
7ac51a12 | 1459 | case USB_SPEED_SUPER_PLUS: |
e518bdd9 TN |
1460 | if ((DWC3_IP_IS(DWC32) && |
1461 | hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || | |
1462 | (!DWC3_IP_IS(DWC32) && | |
1463 | hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) | |
1464 | dev_warn(dev, "UDC doesn't support SSP\n"); | |
7ac51a12 JY |
1465 | break; |
1466 | default: | |
1467 | dev_err(dev, "invalid maximum_speed parameter %d\n", | |
1468 | dwc->maximum_speed); | |
df561f66 | 1469 | fallthrough; |
7ac51a12 | 1470 | case USB_SPEED_UNKNOWN: |
b574ce3e TN |
1471 | switch (hwparam_gen) { |
1472 | case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: | |
7ac51a12 | 1473 | dwc->maximum_speed = USB_SPEED_SUPER_PLUS; |
b574ce3e TN |
1474 | break; |
1475 | case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: | |
1476 | if (DWC3_IP_IS(DWC32)) | |
1477 | dwc->maximum_speed = USB_SPEED_SUPER_PLUS; | |
1478 | else | |
1479 | dwc->maximum_speed = USB_SPEED_SUPER; | |
1480 | break; | |
1481 | case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: | |
1482 | dwc->maximum_speed = USB_SPEED_HIGH; | |
1483 | break; | |
1484 | default: | |
1485 | dwc->maximum_speed = USB_SPEED_SUPER; | |
1486 | break; | |
1487 | } | |
7ac51a12 JY |
1488 | break; |
1489 | } | |
67848146 TN |
1490 | |
1491 | /* | |
1492 | * Currently the controller does not have visibility into the HW | |
1493 | * parameter to determine the maximum number of lanes the HW supports. | |
1494 | * If the number of lanes is not specified in the device property, then | |
1495 | * set the default to support dual-lane for DWC_usb32 and single-lane | |
1496 | * for DWC_usb31 for super-speed-plus. | |
1497 | */ | |
1498 | if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { | |
1499 | switch (dwc->max_ssp_rate) { | |
1500 | case USB_SSP_GEN_2x1: | |
1501 | if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) | |
1502 | dev_warn(dev, "UDC only supports Gen 1\n"); | |
1503 | break; | |
1504 | case USB_SSP_GEN_1x2: | |
1505 | case USB_SSP_GEN_2x2: | |
1506 | if (DWC3_IP_IS(DWC31)) | |
1507 | dev_warn(dev, "UDC only supports single lane\n"); | |
1508 | break; | |
1509 | case USB_SSP_GEN_UNKNOWN: | |
1510 | default: | |
1511 | switch (hwparam_gen) { | |
1512 | case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: | |
1513 | if (DWC3_IP_IS(DWC32)) | |
1514 | dwc->max_ssp_rate = USB_SSP_GEN_2x2; | |
1515 | else | |
1516 | dwc->max_ssp_rate = USB_SSP_GEN_2x1; | |
1517 | break; | |
1518 | case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: | |
1519 | if (DWC3_IP_IS(DWC32)) | |
1520 | dwc->max_ssp_rate = USB_SSP_GEN_1x2; | |
1521 | break; | |
1522 | } | |
1523 | break; | |
1524 | } | |
1525 | } | |
7ac51a12 JY |
1526 | } |
1527 | ||
c5ac6116 FB |
1528 | static int dwc3_probe(struct platform_device *pdev) |
1529 | { | |
1530 | struct device *dev = &pdev->dev; | |
44feb8e6 | 1531 | struct resource *res, dwc_res; |
c5ac6116 FB |
1532 | struct dwc3 *dwc; |
1533 | ||
1534 | int ret; | |
1535 | ||
1536 | void __iomem *regs; | |
1537 | ||
1538 | dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); | |
1539 | if (!dwc) | |
1540 | return -ENOMEM; | |
1541 | ||
1542 | dwc->dev = dev; | |
1543 | ||
1544 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1545 | if (!res) { | |
1546 | dev_err(dev, "missing memory resource\n"); | |
1547 | return -ENODEV; | |
1548 | } | |
1549 | ||
1550 | dwc->xhci_resources[0].start = res->start; | |
1551 | dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + | |
1552 | DWC3_XHCI_REGS_END; | |
1553 | dwc->xhci_resources[0].flags = res->flags; | |
1554 | dwc->xhci_resources[0].name = res->name; | |
1555 | ||
c5ac6116 FB |
1556 | /* |
1557 | * Request memory region but exclude xHCI regs, | |
1558 | * since it will be requested by the xhci-plat driver. | |
1559 | */ | |
44feb8e6 MY |
1560 | dwc_res = *res; |
1561 | dwc_res.start += DWC3_GLOBALS_REGS_START; | |
1562 | ||
1563 | regs = devm_ioremap_resource(dev, &dwc_res); | |
1564 | if (IS_ERR(regs)) | |
1565 | return PTR_ERR(regs); | |
c5ac6116 FB |
1566 | |
1567 | dwc->regs = regs; | |
44feb8e6 | 1568 | dwc->regs_size = resource_size(&dwc_res); |
c5ac6116 FB |
1569 | |
1570 | dwc3_get_properties(dwc); | |
1571 | ||
45d39448 SP |
1572 | ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); |
1573 | if (ret) | |
1574 | return ret; | |
1575 | ||
babbdfc9 | 1576 | dwc->reset = devm_reset_control_array_get_optional_shared(dev); |
fe8abf33 MY |
1577 | if (IS_ERR(dwc->reset)) |
1578 | return PTR_ERR(dwc->reset); | |
1579 | ||
61527777 | 1580 | if (dev->of_node) { |
0d3a9708 | 1581 | ret = devm_clk_bulk_get_all(dev, &dwc->clks); |
61527777 HG |
1582 | if (ret == -EPROBE_DEFER) |
1583 | return ret; | |
1584 | /* | |
1585 | * Clocks are optional, but new DT platforms should support all | |
1586 | * clocks as required by the DT-binding. | |
1587 | */ | |
0d3a9708 | 1588 | if (ret < 0) |
61527777 | 1589 | dwc->num_clks = 0; |
0d3a9708 JS |
1590 | else |
1591 | dwc->num_clks = ret; | |
1592 | ||
61527777 | 1593 | } |
fe8abf33 MY |
1594 | |
1595 | ret = reset_control_deassert(dwc->reset); | |
1596 | if (ret) | |
03bf32bb | 1597 | return ret; |
fe8abf33 | 1598 | |
240b65dc | 1599 | ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); |
fe8abf33 MY |
1600 | if (ret) |
1601 | goto assert_reset; | |
1602 | ||
dc1b5d9a EBS |
1603 | if (!dwc3_core_is_valid(dwc)) { |
1604 | dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); | |
1605 | ret = -ENODEV; | |
1606 | goto disable_clks; | |
1607 | } | |
1608 | ||
6c89cce0 | 1609 | platform_set_drvdata(pdev, dwc); |
2917e718 | 1610 | dwc3_cache_hwparams(dwc); |
6c89cce0 | 1611 | |
72246da4 | 1612 | spin_lock_init(&dwc->lock); |
f88359e1 | 1613 | mutex_init(&dwc->mutex); |
72246da4 | 1614 | |
fc8bb91b FB |
1615 | pm_runtime_set_active(dev); |
1616 | pm_runtime_use_autosuspend(dev); | |
1617 | pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); | |
802ca850 | 1618 | pm_runtime_enable(dev); |
32808237 RQ |
1619 | ret = pm_runtime_get_sync(dev); |
1620 | if (ret < 0) | |
1621 | goto err1; | |
1622 | ||
802ca850 | 1623 | pm_runtime_forbid(dev); |
72246da4 | 1624 | |
3921426b FB |
1625 | ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); |
1626 | if (ret) { | |
1627 | dev_err(dwc->dev, "failed to allocate event buffers\n"); | |
1628 | ret = -ENOMEM; | |
32808237 | 1629 | goto err2; |
3921426b FB |
1630 | } |
1631 | ||
9d6173e1 TN |
1632 | ret = dwc3_get_dr_mode(dwc); |
1633 | if (ret) | |
1634 | goto err3; | |
32a4a135 | 1635 | |
c499ff71 FB |
1636 | ret = dwc3_alloc_scratch_buffers(dwc); |
1637 | if (ret) | |
32808237 | 1638 | goto err3; |
c499ff71 | 1639 | |
72246da4 FB |
1640 | ret = dwc3_core_init(dwc); |
1641 | if (ret) { | |
0c0a20f6 | 1642 | dev_err_probe(dev, ret, "failed to initialize core\n"); |
32808237 | 1643 | goto err4; |
72246da4 FB |
1644 | } |
1645 | ||
7ac51a12 | 1646 | dwc3_check_params(dwc); |
84524d12 | 1647 | dwc3_debugfs_init(dwc); |
2c7f1bd9 | 1648 | |
5f94adfe FB |
1649 | ret = dwc3_core_init_mode(dwc); |
1650 | if (ret) | |
32808237 | 1651 | goto err5; |
72246da4 | 1652 | |
fc8bb91b | 1653 | pm_runtime_put(dev); |
72246da4 FB |
1654 | |
1655 | return 0; | |
1656 | ||
32808237 | 1657 | err5: |
84524d12 | 1658 | dwc3_debugfs_exit(dwc); |
c499ff71 | 1659 | dwc3_event_buffers_cleanup(dwc); |
03c1fd62 LJ |
1660 | |
1661 | usb_phy_shutdown(dwc->usb2_phy); | |
1662 | usb_phy_shutdown(dwc->usb3_phy); | |
1663 | phy_exit(dwc->usb2_generic_phy); | |
1664 | phy_exit(dwc->usb3_generic_phy); | |
1665 | ||
1666 | usb_phy_set_suspend(dwc->usb2_phy, 1); | |
1667 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
1668 | phy_power_off(dwc->usb2_generic_phy); | |
1669 | phy_power_off(dwc->usb3_generic_phy); | |
1670 | ||
08fd9a82 | 1671 | dwc3_ulpi_exit(dwc); |
57303488 | 1672 | |
32808237 | 1673 | err4: |
c499ff71 | 1674 | dwc3_free_scratch_buffers(dwc); |
72246da4 | 1675 | |
32808237 | 1676 | err3: |
3921426b FB |
1677 | dwc3_free_event_buffers(dwc); |
1678 | ||
32808237 RQ |
1679 | err2: |
1680 | pm_runtime_allow(&pdev->dev); | |
1681 | ||
1682 | err1: | |
1683 | pm_runtime_put_sync(&pdev->dev); | |
1684 | pm_runtime_disable(&pdev->dev); | |
1685 | ||
dc1b5d9a | 1686 | disable_clks: |
240b65dc | 1687 | clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); |
fe8abf33 MY |
1688 | assert_reset: |
1689 | reset_control_assert(dwc->reset); | |
fe8abf33 | 1690 | |
b0bf77cd | 1691 | if (dwc->usb_psy) |
6f0764b5 RC |
1692 | power_supply_put(dwc->usb_psy); |
1693 | ||
72246da4 FB |
1694 | return ret; |
1695 | } | |
1696 | ||
fb4e98ab | 1697 | static int dwc3_remove(struct platform_device *pdev) |
72246da4 | 1698 | { |
72246da4 | 1699 | struct dwc3 *dwc = platform_get_drvdata(pdev); |
3da1f6ee | 1700 | |
fc8bb91b | 1701 | pm_runtime_get_sync(&pdev->dev); |
72246da4 | 1702 | |
dc99f16f | 1703 | dwc3_core_exit_mode(dwc); |
2a042767 | 1704 | dwc3_debugfs_exit(dwc); |
8ba007a9 | 1705 | |
72246da4 | 1706 | dwc3_core_exit(dwc); |
88bc9d19 | 1707 | dwc3_ulpi_exit(dwc); |
72246da4 | 1708 | |
72246da4 | 1709 | pm_runtime_disable(&pdev->dev); |
266d0493 LJ |
1710 | pm_runtime_put_noidle(&pdev->dev); |
1711 | pm_runtime_set_suspended(&pdev->dev); | |
72246da4 | 1712 | |
fc8bb91b FB |
1713 | dwc3_free_event_buffers(dwc); |
1714 | dwc3_free_scratch_buffers(dwc); | |
1715 | ||
b0bf77cd | 1716 | if (dwc->usb_psy) |
6f0764b5 RC |
1717 | power_supply_put(dwc->usb_psy); |
1718 | ||
72246da4 FB |
1719 | return 0; |
1720 | } | |
1721 | ||
fc8bb91b | 1722 | #ifdef CONFIG_PM |
fe8abf33 MY |
1723 | static int dwc3_core_init_for_resume(struct dwc3 *dwc) |
1724 | { | |
1725 | int ret; | |
1726 | ||
1727 | ret = reset_control_deassert(dwc->reset); | |
1728 | if (ret) | |
1729 | return ret; | |
1730 | ||
240b65dc | 1731 | ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); |
fe8abf33 MY |
1732 | if (ret) |
1733 | goto assert_reset; | |
1734 | ||
fe8abf33 MY |
1735 | ret = dwc3_core_init(dwc); |
1736 | if (ret) | |
1737 | goto disable_clks; | |
1738 | ||
1739 | return 0; | |
1740 | ||
1741 | disable_clks: | |
240b65dc | 1742 | clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); |
fe8abf33 MY |
1743 | assert_reset: |
1744 | reset_control_assert(dwc->reset); | |
1745 | ||
1746 | return ret; | |
1747 | } | |
1748 | ||
c4a5153e | 1749 | static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) |
7415f17c | 1750 | { |
fc8bb91b | 1751 | unsigned long flags; |
bcb12877 | 1752 | u32 reg; |
7415f17c | 1753 | |
689bf72c MG |
1754 | switch (dwc->current_dr_role) { |
1755 | case DWC3_GCTL_PRTCAP_DEVICE: | |
0227cc84 LJ |
1756 | if (pm_runtime_suspended(dwc->dev)) |
1757 | break; | |
fc8bb91b | 1758 | spin_lock_irqsave(&dwc->lock, flags); |
7415f17c | 1759 | dwc3_gadget_suspend(dwc); |
fc8bb91b | 1760 | spin_unlock_irqrestore(&dwc->lock, flags); |
41a91c60 | 1761 | synchronize_irq(dwc->irq_gadget); |
689bf72c | 1762 | dwc3_core_exit(dwc); |
51f5d49a | 1763 | break; |
689bf72c | 1764 | case DWC3_GCTL_PRTCAP_HOST: |
bcb12877 | 1765 | if (!PMSG_IS_AUTO(msg)) { |
c4a5153e | 1766 | dwc3_core_exit(dwc); |
bcb12877 MG |
1767 | break; |
1768 | } | |
1769 | ||
1770 | /* Let controller to suspend HSPHY before PHY driver suspends */ | |
1771 | if (dwc->dis_u2_susphy_quirk || | |
1772 | dwc->dis_enblslpm_quirk) { | |
1773 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
1774 | reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | | |
1775 | DWC3_GUSB2PHYCFG_SUSPHY; | |
1776 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
1777 | ||
1778 | /* Give some time for USB2 PHY to suspend */ | |
1779 | usleep_range(5000, 6000); | |
1780 | } | |
1781 | ||
1782 | phy_pm_runtime_put_sync(dwc->usb2_generic_phy); | |
1783 | phy_pm_runtime_put_sync(dwc->usb3_generic_phy); | |
c4a5153e | 1784 | break; |
f09cc79b RQ |
1785 | case DWC3_GCTL_PRTCAP_OTG: |
1786 | /* do nothing during runtime_suspend */ | |
1787 | if (PMSG_IS_AUTO(msg)) | |
1788 | break; | |
1789 | ||
1790 | if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { | |
1791 | spin_lock_irqsave(&dwc->lock, flags); | |
1792 | dwc3_gadget_suspend(dwc); | |
1793 | spin_unlock_irqrestore(&dwc->lock, flags); | |
41a91c60 | 1794 | synchronize_irq(dwc->irq_gadget); |
f09cc79b RQ |
1795 | } |
1796 | ||
1797 | dwc3_otg_exit(dwc); | |
1798 | dwc3_core_exit(dwc); | |
1799 | break; | |
7415f17c | 1800 | default: |
51f5d49a | 1801 | /* do nothing */ |
7415f17c FB |
1802 | break; |
1803 | } | |
1804 | ||
7415f17c FB |
1805 | return 0; |
1806 | } | |
1807 | ||
c4a5153e | 1808 | static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) |
7415f17c | 1809 | { |
fc8bb91b | 1810 | unsigned long flags; |
57303488 | 1811 | int ret; |
bcb12877 | 1812 | u32 reg; |
7415f17c | 1813 | |
689bf72c MG |
1814 | switch (dwc->current_dr_role) { |
1815 | case DWC3_GCTL_PRTCAP_DEVICE: | |
fe8abf33 | 1816 | ret = dwc3_core_init_for_resume(dwc); |
689bf72c MG |
1817 | if (ret) |
1818 | return ret; | |
5c4ad318 | 1819 | |
7d11c3ac | 1820 | dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); |
fc8bb91b | 1821 | spin_lock_irqsave(&dwc->lock, flags); |
7415f17c | 1822 | dwc3_gadget_resume(dwc); |
fc8bb91b | 1823 | spin_unlock_irqrestore(&dwc->lock, flags); |
689bf72c MG |
1824 | break; |
1825 | case DWC3_GCTL_PRTCAP_HOST: | |
c4a5153e | 1826 | if (!PMSG_IS_AUTO(msg)) { |
fe8abf33 | 1827 | ret = dwc3_core_init_for_resume(dwc); |
c4a5153e MG |
1828 | if (ret) |
1829 | return ret; | |
7d11c3ac | 1830 | dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); |
bcb12877 | 1831 | break; |
c4a5153e | 1832 | } |
bcb12877 MG |
1833 | /* Restore GUSB2PHYCFG bits that were modified in suspend */ |
1834 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
1835 | if (dwc->dis_u2_susphy_quirk) | |
1836 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; | |
1837 | ||
1838 | if (dwc->dis_enblslpm_quirk) | |
1839 | reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; | |
1840 | ||
1841 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
1842 | ||
1843 | phy_pm_runtime_get_sync(dwc->usb2_generic_phy); | |
1844 | phy_pm_runtime_get_sync(dwc->usb3_generic_phy); | |
f09cc79b RQ |
1845 | break; |
1846 | case DWC3_GCTL_PRTCAP_OTG: | |
1847 | /* nothing to do on runtime_resume */ | |
1848 | if (PMSG_IS_AUTO(msg)) | |
1849 | break; | |
1850 | ||
0e5a3c82 | 1851 | ret = dwc3_core_init_for_resume(dwc); |
f09cc79b RQ |
1852 | if (ret) |
1853 | return ret; | |
1854 | ||
1855 | dwc3_set_prtcap(dwc, dwc->current_dr_role); | |
1856 | ||
1857 | dwc3_otg_init(dwc); | |
1858 | if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { | |
1859 | dwc3_otg_host_init(dwc); | |
1860 | } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { | |
1861 | spin_lock_irqsave(&dwc->lock, flags); | |
1862 | dwc3_gadget_resume(dwc); | |
1863 | spin_unlock_irqrestore(&dwc->lock, flags); | |
c4a5153e | 1864 | } |
f09cc79b | 1865 | |
c4a5153e | 1866 | break; |
7415f17c FB |
1867 | default: |
1868 | /* do nothing */ | |
1869 | break; | |
1870 | } | |
1871 | ||
fc8bb91b FB |
1872 | return 0; |
1873 | } | |
1874 | ||
1875 | static int dwc3_runtime_checks(struct dwc3 *dwc) | |
1876 | { | |
689bf72c | 1877 | switch (dwc->current_dr_role) { |
c4a5153e | 1878 | case DWC3_GCTL_PRTCAP_DEVICE: |
fc8bb91b FB |
1879 | if (dwc->connected) |
1880 | return -EBUSY; | |
1881 | break; | |
c4a5153e | 1882 | case DWC3_GCTL_PRTCAP_HOST: |
fc8bb91b FB |
1883 | default: |
1884 | /* do nothing */ | |
1885 | break; | |
1886 | } | |
1887 | ||
1888 | return 0; | |
1889 | } | |
1890 | ||
1891 | static int dwc3_runtime_suspend(struct device *dev) | |
1892 | { | |
1893 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1894 | int ret; | |
1895 | ||
1896 | if (dwc3_runtime_checks(dwc)) | |
1897 | return -EBUSY; | |
1898 | ||
c4a5153e | 1899 | ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); |
fc8bb91b FB |
1900 | if (ret) |
1901 | return ret; | |
1902 | ||
1903 | device_init_wakeup(dev, true); | |
1904 | ||
1905 | return 0; | |
1906 | } | |
1907 | ||
1908 | static int dwc3_runtime_resume(struct device *dev) | |
1909 | { | |
1910 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1911 | int ret; | |
1912 | ||
1913 | device_init_wakeup(dev, false); | |
1914 | ||
c4a5153e | 1915 | ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); |
fc8bb91b FB |
1916 | if (ret) |
1917 | return ret; | |
1918 | ||
689bf72c MG |
1919 | switch (dwc->current_dr_role) { |
1920 | case DWC3_GCTL_PRTCAP_DEVICE: | |
fc8bb91b FB |
1921 | dwc3_gadget_process_pending_events(dwc); |
1922 | break; | |
689bf72c | 1923 | case DWC3_GCTL_PRTCAP_HOST: |
fc8bb91b FB |
1924 | default: |
1925 | /* do nothing */ | |
1926 | break; | |
1927 | } | |
1928 | ||
1929 | pm_runtime_mark_last_busy(dev); | |
1930 | ||
1931 | return 0; | |
1932 | } | |
1933 | ||
1934 | static int dwc3_runtime_idle(struct device *dev) | |
1935 | { | |
1936 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1937 | ||
689bf72c MG |
1938 | switch (dwc->current_dr_role) { |
1939 | case DWC3_GCTL_PRTCAP_DEVICE: | |
fc8bb91b FB |
1940 | if (dwc3_runtime_checks(dwc)) |
1941 | return -EBUSY; | |
1942 | break; | |
689bf72c | 1943 | case DWC3_GCTL_PRTCAP_HOST: |
fc8bb91b FB |
1944 | default: |
1945 | /* do nothing */ | |
1946 | break; | |
1947 | } | |
1948 | ||
1949 | pm_runtime_mark_last_busy(dev); | |
1950 | pm_runtime_autosuspend(dev); | |
1951 | ||
1952 | return 0; | |
1953 | } | |
1954 | #endif /* CONFIG_PM */ | |
1955 | ||
1956 | #ifdef CONFIG_PM_SLEEP | |
1957 | static int dwc3_suspend(struct device *dev) | |
1958 | { | |
1959 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1960 | int ret; | |
1961 | ||
c4a5153e | 1962 | ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); |
fc8bb91b FB |
1963 | if (ret) |
1964 | return ret; | |
1965 | ||
1966 | pinctrl_pm_select_sleep_state(dev); | |
1967 | ||
1968 | return 0; | |
1969 | } | |
1970 | ||
1971 | static int dwc3_resume(struct device *dev) | |
1972 | { | |
1973 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1974 | int ret; | |
1975 | ||
1976 | pinctrl_pm_select_default_state(dev); | |
1977 | ||
c4a5153e | 1978 | ret = dwc3_resume_common(dwc, PMSG_RESUME); |
fc8bb91b FB |
1979 | if (ret) |
1980 | return ret; | |
1981 | ||
7415f17c FB |
1982 | pm_runtime_disable(dev); |
1983 | pm_runtime_set_active(dev); | |
1984 | pm_runtime_enable(dev); | |
1985 | ||
1986 | return 0; | |
1987 | } | |
f580170f YC |
1988 | |
1989 | static void dwc3_complete(struct device *dev) | |
1990 | { | |
1991 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1992 | u32 reg; | |
1993 | ||
1994 | if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && | |
1995 | dwc->dis_split_quirk) { | |
1996 | reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); | |
1997 | reg |= DWC3_GUCTL3_SPLITDISABLE; | |
1998 | dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); | |
1999 | } | |
2000 | } | |
2001 | #else | |
2002 | #define dwc3_complete NULL | |
7f370ed0 | 2003 | #endif /* CONFIG_PM_SLEEP */ |
7415f17c FB |
2004 | |
2005 | static const struct dev_pm_ops dwc3_dev_pm_ops = { | |
7415f17c | 2006 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) |
f580170f | 2007 | .complete = dwc3_complete, |
fc8bb91b FB |
2008 | SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, |
2009 | dwc3_runtime_idle) | |
7415f17c FB |
2010 | }; |
2011 | ||
5088b6f5 KVA |
2012 | #ifdef CONFIG_OF |
2013 | static const struct of_device_id of_dwc3_match[] = { | |
22a5aa17 FB |
2014 | { |
2015 | .compatible = "snps,dwc3" | |
2016 | }, | |
5088b6f5 KVA |
2017 | { |
2018 | .compatible = "synopsys,dwc3" | |
2019 | }, | |
2020 | { }, | |
2021 | }; | |
2022 | MODULE_DEVICE_TABLE(of, of_dwc3_match); | |
2023 | #endif | |
2024 | ||
404905a6 HK |
2025 | #ifdef CONFIG_ACPI |
2026 | ||
2027 | #define ACPI_ID_INTEL_BSW "808622B7" | |
2028 | ||
2029 | static const struct acpi_device_id dwc3_acpi_match[] = { | |
2030 | { ACPI_ID_INTEL_BSW, 0 }, | |
2031 | { }, | |
2032 | }; | |
2033 | MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); | |
2034 | #endif | |
2035 | ||
72246da4 FB |
2036 | static struct platform_driver dwc3_driver = { |
2037 | .probe = dwc3_probe, | |
7690417d | 2038 | .remove = dwc3_remove, |
72246da4 FB |
2039 | .driver = { |
2040 | .name = "dwc3", | |
5088b6f5 | 2041 | .of_match_table = of_match_ptr(of_dwc3_match), |
404905a6 | 2042 | .acpi_match_table = ACPI_PTR(dwc3_acpi_match), |
7f370ed0 | 2043 | .pm = &dwc3_dev_pm_ops, |
72246da4 | 2044 | }, |
72246da4 FB |
2045 | }; |
2046 | ||
b1116dcc TK |
2047 | module_platform_driver(dwc3_driver); |
2048 | ||
7ae4fc4d | 2049 | MODULE_ALIAS("platform:dwc3"); |
72246da4 | 2050 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); |
5945f789 | 2051 | MODULE_LICENSE("GPL v2"); |
72246da4 | 2052 | MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); |