projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
usb: dwc3: Set default mode for dwc_usb31
[linux-2.6-block.git] / drivers / usb / dwc3 / core.c
CommitLineData
5fd54ace 1// SPDX-License-Identifier: GPL-2.0
72246da4
FB		 2/**
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
72246da4
FB		 9 */
10
fe8abf33 11#include <linux/clk.h>
fa0ea13e 12#include <linux/version.h>
a72e658b 13#include <linux/module.h>
72246da4
FB		 14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/io.h>
22#include <linux/list.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
457e84b6 25#include <linux/of.h>
404905a6 26#include <linux/acpi.h>
6344475f 27#include <linux/pinctrl/consumer.h>
fe8abf33 28#include <linux/reset.h>
72246da4
FB		 29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
f7e846f0 32#include <linux/usb/of.h>
a45c82b8 33#include <linux/usb/otg.h>
72246da4
FB		 34
35#include "core.h"
36#include "gadget.h"
37#include "io.h"
38
39#include "debug.h"
40
fc8bb91b 41#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
8300dd23 42
9d6173e1
TN		 43/**
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
46 */
47static int dwc3_get_dr_mode(struct dwc3 *dwc)
48{
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
51 unsigned int hw_mode;
52
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
55
56 mode = dwc->dr_mode;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
58
59 switch (hw_mode) {
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
62 dev_err(dev,
63 "Controller does not support host mode.\n");
64 return -EINVAL;
65 }
66 mode = USB_DR_MODE_PERIPHERAL;
67 break;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
70 dev_err(dev,
71 "Controller does not support device mode.\n");
72 return -EINVAL;
73 }
74 mode = USB_DR_MODE_HOST;
75 break;
76 default:
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
a7700468
TN		 81
82 /*
83 * dwc_usb31 does not support OTG mode. If the controller
84 * supports DRD but the dr_mode is not specified or set to OTG,
85 * then set the mode to peripheral.
86 */
87 if (mode == USB_DR_MODE_OTG && dwc3_is_usb31(dwc))
88 mode = USB_DR_MODE_PERIPHERAL;
9d6173e1
TN		 89 }
90
91 if (mode != dwc->dr_mode) {
92 dev_warn(dev,
93 "Configuration mismatch. dr_mode forced to %s\n",
94 mode == USB_DR_MODE_HOST ? "host" : "gadget");
95
96 dwc->dr_mode = mode;
97 }
98
99 return 0;
100}
101
f09cc79b 102void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
3140e8cb
SAS		 103{
104 u32 reg;
105
106 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
107 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
108 reg |= DWC3_GCTL_PRTCAPDIR(mode);
109 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
c4a5153e
MG		 110
111 dwc->current_dr_role = mode;
41ce1456
RQ		 112}
113
114static void __dwc3_set_mode(struct work_struct *work)
115{
116 struct dwc3 *dwc = work_to_dwc(work);
117 unsigned long flags;
118 int ret;
119
f09cc79b 120 if (dwc->dr_mode != USB_DR_MODE_OTG)
41ce1456
RQ		 121 return;
122
f09cc79b
RQ		 123 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
124 dwc3_otg_update(dwc, 0);
125
41ce1456
RQ		 126 if (!dwc->desired_dr_role)
127 return;
128
129 if (dwc->desired_dr_role == dwc->current_dr_role)
130 return;
131
f09cc79b 132 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
41ce1456
RQ		 133 return;
134
135 switch (dwc->current_dr_role) {
136 case DWC3_GCTL_PRTCAP_HOST:
137 dwc3_host_exit(dwc);
138 break;
139 case DWC3_GCTL_PRTCAP_DEVICE:
140 dwc3_gadget_exit(dwc);
141 dwc3_event_buffers_cleanup(dwc);
142 break;
f09cc79b
RQ		 143 case DWC3_GCTL_PRTCAP_OTG:
144 dwc3_otg_exit(dwc);
145 spin_lock_irqsave(&dwc->lock, flags);
146 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
147 spin_unlock_irqrestore(&dwc->lock, flags);
148 dwc3_otg_update(dwc, 1);
149 break;
41ce1456
RQ		 150 default:
151 break;
152 }
153
154 spin_lock_irqsave(&dwc->lock, flags);
155
156 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
6b3261a2 157
41ce1456
RQ		 158 spin_unlock_irqrestore(&dwc->lock, flags);
159
160 switch (dwc->desired_dr_role) {
161 case DWC3_GCTL_PRTCAP_HOST:
162 ret = dwc3_host_init(dwc);
958d1a4c 163 if (ret) {
41ce1456 164 dev_err(dwc->dev, "failed to initialize host\n");
958d1a4c
FB		 165 } else {
166 if (dwc->usb2_phy)
167 otg_set_vbus(dwc->usb2_phy->otg, true);
644cbbc3
MG		 168 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
169 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
d8c80bb3 170 phy_calibrate(dwc->usb2_generic_phy);
958d1a4c 171 }
41ce1456
RQ		 172 break;
173 case DWC3_GCTL_PRTCAP_DEVICE:
174 dwc3_event_buffers_setup(dwc);
958d1a4c
FB		 175
176 if (dwc->usb2_phy)
177 otg_set_vbus(dwc->usb2_phy->otg, false);
644cbbc3
MG		 178 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
179 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
958d1a4c 180
41ce1456
RQ		 181 ret = dwc3_gadget_init(dwc);
182 if (ret)
183 dev_err(dwc->dev, "failed to initialize peripheral\n");
184 break;
f09cc79b
RQ		 185 case DWC3_GCTL_PRTCAP_OTG:
186 dwc3_otg_init(dwc);
187 dwc3_otg_update(dwc, 0);
188 break;
41ce1456
RQ		 189 default:
190 break;
191 }
f09cc79b 192
41ce1456
RQ		 193}
194
195void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
196{
197 unsigned long flags;
198
199 spin_lock_irqsave(&dwc->lock, flags);
200 dwc->desired_dr_role = mode;
201 spin_unlock_irqrestore(&dwc->lock, flags);
202
084a804e 203 queue_work(system_freezable_wq, &dwc->drd_work);
3140e8cb 204}
8300dd23 205
cf6d867d
FB		 206u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
207{
208 struct dwc3 *dwc = dep->dwc;
209 u32 reg;
210
211 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
212 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
213 DWC3_GDBGFIFOSPACE_TYPE(type));
214
215 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
216
217 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
218}
219
72246da4
FB		 220/**
221 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
222 * @dwc: pointer to our context structure
223 */
57303488 224static int dwc3_core_soft_reset(struct dwc3 *dwc)
72246da4
FB		 225{
226 u32 reg;
f59dcab1 227 int retries = 1000;
57303488 228 int ret;
72246da4 229
51e1e7bc
FB		 230 usb_phy_init(dwc->usb2_phy);
231 usb_phy_init(dwc->usb3_phy);
57303488
KVA		 232 ret = phy_init(dwc->usb2_generic_phy);
233 if (ret < 0)
234 return ret;
235
236 ret = phy_init(dwc->usb3_generic_phy);
237 if (ret < 0) {
238 phy_exit(dwc->usb2_generic_phy);
239 return ret;
240 }
72246da4 241
f59dcab1
FB		 242 /*
243 * We're resetting only the device side because, if we're in host mode,
244 * XHCI driver will reset the host block. If dwc3 was configured for
245 * host-only mode, then we can return early.
246 */
c4a5153e 247 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
f59dcab1 248 return 0;
72246da4 249
f59dcab1
FB		 250 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
251 reg |= DWC3_DCTL_CSFTRST;
252 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 253
f59dcab1
FB		 254 do {
255 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
256 if (!(reg & DWC3_DCTL_CSFTRST))
fab38333 257 goto done;
45627ac6 258
f59dcab1
FB		 259 udelay(1);
260 } while (--retries);
57303488 261
00b42170
BN		 262 phy_exit(dwc->usb3_generic_phy);
263 phy_exit(dwc->usb2_generic_phy);
264
f59dcab1 265 return -ETIMEDOUT;
fab38333
TN		 266
267done:
268 /*
269 * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
270 * we must wait at least 50ms before accessing the PHY domain
271 * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
272 */
273 if (dwc3_is_usb31(dwc))
274 msleep(50);
275
276 return 0;
72246da4
FB		 277}
278
fe8abf33
MY		 279static const struct clk_bulk_data dwc3_core_clks[] = {
280 { .id = "ref" },
281 { .id = "bus_early" },
282 { .id = "suspend" },
283};
284
db2be4e9
NB		 285/*
286 * dwc3_frame_length_adjustment - Adjusts frame length if required
287 * @dwc3: Pointer to our controller context structure
db2be4e9 288 */
bcdb3272 289static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
db2be4e9
NB		 290{
291 u32 reg;
292 u32 dft;
293
294 if (dwc->revision < DWC3_REVISION_250A)
295 return;
296
bcdb3272 297 if (dwc->fladj == 0)
db2be4e9
NB		 298 return;
299
300 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
301 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
bcdb3272 302 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
db2be4e9
NB		 303 "request value same as default, ignoring\n")) {
304 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
bcdb3272 305 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
db2be4e9
NB		 306 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
307 }
308}
309
72246da4
FB		 310/**
311 * dwc3_free_one_event_buffer - Frees one event buffer
312 * @dwc: Pointer to our controller context structure
313 * @evt: Pointer to event buffer to be freed
314 */
315static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
316 struct dwc3_event_buffer *evt)
317{
d64ff406 318 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
72246da4
FB		 319}
320
321/**
1d046793 322 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
72246da4
FB		 323 * @dwc: Pointer to our controller context structure
324 * @length: size of the event buffer
325 *
1d046793 326 * Returns a pointer to the allocated event buffer structure on success
72246da4
FB		 327 * otherwise ERR_PTR(errno).
328 */
67d0b500
FB		 329static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
330 unsigned length)
72246da4
FB		 331{
332 struct dwc3_event_buffer *evt;
333
380f0d28 334 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
72246da4
FB		 335 if (!evt)
336 return ERR_PTR(-ENOMEM);
337
338 evt->dwc = dwc;
339 evt->length = length;
d9fa4c63
JY		 340 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
341 if (!evt->cache)
342 return ERR_PTR(-ENOMEM);
343
d64ff406 344 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
72246da4 345 &evt->dma, GFP_KERNEL);
e32672f0 346 if (!evt->buf)
72246da4 347 return ERR_PTR(-ENOMEM);
72246da4
FB		 348
349 return evt;
350}
351
352/**
353 * dwc3_free_event_buffers - frees all allocated event buffers
354 * @dwc: Pointer to our controller context structure
355 */
356static void dwc3_free_event_buffers(struct dwc3 *dwc)
357{
358 struct dwc3_event_buffer *evt;
72246da4 359
696c8b12 360 evt = dwc->ev_buf;
660e9bde
FB		 361 if (evt)
362 dwc3_free_one_event_buffer(dwc, evt);
72246da4
FB		 363}
364
365/**
366 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
1d046793 367 * @dwc: pointer to our controller context structure
72246da4
FB		 368 * @length: size of event buffer
369 *
1d046793 370 * Returns 0 on success otherwise negative errno. In the error case, dwc
72246da4
FB		 371 * may contain some buffers allocated but not all which were requested.
372 */
41ac7b3a 373static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
72246da4 374{
660e9bde 375 struct dwc3_event_buffer *evt;
72246da4 376
660e9bde
FB		 377 evt = dwc3_alloc_one_event_buffer(dwc, length);
378 if (IS_ERR(evt)) {
379 dev_err(dwc->dev, "can't allocate event buffer\n");
380 return PTR_ERR(evt);
72246da4 381 }
696c8b12 382 dwc->ev_buf = evt;
72246da4
FB		 383
384 return 0;
385}
386
387/**
388 * dwc3_event_buffers_setup - setup our allocated event buffers
1d046793 389 * @dwc: pointer to our controller context structure
72246da4
FB		 390 *
391 * Returns 0 on success otherwise negative errno.
392 */
f09cc79b 393int dwc3_event_buffers_setup(struct dwc3 *dwc)
72246da4
FB		 394{
395 struct dwc3_event_buffer *evt;
72246da4 396
696c8b12 397 evt = dwc->ev_buf;
660e9bde 398 evt->lpos = 0;
660e9bde
FB		 399 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
400 lower_32_bits(evt->dma));
401 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
402 upper_32_bits(evt->dma));
403 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
404 DWC3_GEVNTSIZ_SIZE(evt->length));
405 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 406
407 return 0;
408}
409
f09cc79b 410void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
72246da4
FB		 411{
412 struct dwc3_event_buffer *evt;
72246da4 413
696c8b12 414 evt = dwc->ev_buf;
7acd85e0 415
660e9bde 416 evt->lpos = 0;
7acd85e0 417
660e9bde
FB		 418 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
419 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
420 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
421 | DWC3_GEVNTSIZ_SIZE(0));
422 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 423}
424
0ffcaf37
FB		 425static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
426{
427 if (!dwc->has_hibernation)
428 return 0;
429
430 if (!dwc->nr_scratch)
431 return 0;
432
433 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
434 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
435 if (!dwc->scratchbuf)
436 return -ENOMEM;
437
438 return 0;
439}
440
441static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
442{
443 dma_addr_t scratch_addr;
444 u32 param;
445 int ret;
446
447 if (!dwc->has_hibernation)
448 return 0;
449
450 if (!dwc->nr_scratch)
451 return 0;
452
453 /* should never fall here */
454 if (!WARN_ON(dwc->scratchbuf))
455 return 0;
456
d64ff406 457 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
0ffcaf37
FB		 458 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
459 DMA_BIDIRECTIONAL);
d64ff406
AB		 460 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
461 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
0ffcaf37
FB		 462 ret = -EFAULT;
463 goto err0;
464 }
465
466 dwc->scratch_addr = scratch_addr;
467
468 param = lower_32_bits(scratch_addr);
469
470 ret = dwc3_send_gadget_generic_command(dwc,
471 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
472 if (ret < 0)
473 goto err1;
474
475 param = upper_32_bits(scratch_addr);
476
477 ret = dwc3_send_gadget_generic_command(dwc,
478 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
479 if (ret < 0)
480 goto err1;
481
482 return 0;
483
484err1:
d64ff406 485 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
0ffcaf37
FB		 486 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
487
488err0:
489 return ret;
490}
491
492static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
493{
494 if (!dwc->has_hibernation)
495 return;
496
497 if (!dwc->nr_scratch)
498 return;
499
500 /* should never fall here */
501 if (!WARN_ON(dwc->scratchbuf))
502 return;
503
d64ff406 504 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
0ffcaf37
FB		 505 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
506 kfree(dwc->scratchbuf);
507}
508
789451f6
FB		 509static void dwc3_core_num_eps(struct dwc3 *dwc)
510{
511 struct dwc3_hwparams *parms = &dwc->hwparams;
512
47d3946e 513 dwc->num_eps = DWC3_NUM_EPS(parms);
789451f6
FB		 514}
515
41ac7b3a 516static void dwc3_cache_hwparams(struct dwc3 *dwc)
26ceca97
FB		 517{
518 struct dwc3_hwparams *parms = &dwc->hwparams;
519
520 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
521 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
522 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
523 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
524 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
525 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
526 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
527 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
528 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
529}
530
98112041
RQ		 531static int dwc3_core_ulpi_init(struct dwc3 *dwc)
532{
533 int intf;
534 int ret = 0;
535
536 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
537
538 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
539 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
540 dwc->hsphy_interface &&
541 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
542 ret = dwc3_ulpi_init(dwc);
543
544 return ret;
545}
546
b5a65c40
HR		 547/**
548 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
549 * @dwc: Pointer to our controller context structure
88bc9d19
HK		 550 *
551 * Returns 0 on success. The USB PHY interfaces are configured but not
552 * initialized. The PHY interfaces and the PHYs get initialized together with
553 * the core in dwc3_core_init.
b5a65c40 554 */
88bc9d19 555static int dwc3_phy_setup(struct dwc3 *dwc)
b5a65c40
HR		 556{
557 u32 reg;
558
559 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
560
1966b865
FB		 561 /*
562 * Make sure UX_EXIT_PX is cleared as that causes issues with some
563 * PHYs. Also, this bit is not supposed to be used in normal operation.
564 */
565 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
566
2164a476
HR		 567 /*
568 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
569 * to '0' during coreConsultant configuration. So default value
570 * will be '0' when the core is reset. Application needs to set it
571 * to '1' after the core initialization is completed.
572 */
573 if (dwc->revision > DWC3_REVISION_194A)
574 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
575
b5a65c40
HR		 576 if (dwc->u2ss_inp3_quirk)
577 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
578
e58dd357
RB		 579 if (dwc->dis_rxdet_inp3_quirk)
580 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
581
df31f5b3
HR		 582 if (dwc->req_p1p2p3_quirk)
583 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
584
a2a1d0f5
HR		 585 if (dwc->del_p1p2p3_quirk)
586 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
587
41c06ffd
HR		 588 if (dwc->del_phy_power_chg_quirk)
589 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
590
fb67afca
HR		 591 if (dwc->lfps_filter_quirk)
592 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
593
14f4ac53
HR		 594 if (dwc->rx_detect_poll_quirk)
595 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
596
6b6a0c9a
HR		 597 if (dwc->tx_de_emphasis_quirk)
598 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
599
cd72f890 600 if (dwc->dis_u3_susphy_quirk)
59acfa20
HR		 601 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
602
00fe081d
WW		 603 if (dwc->dis_del_phy_power_chg_quirk)
604 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
605
b5a65c40
HR		 606 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
607
2164a476
HR		 608 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
609
3e10a2ce
HK		 610 /* Select the HS PHY interface */
611 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
612 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
43cacb03
FB		 613 if (dwc->hsphy_interface &&
614 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
3e10a2ce 615 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 616 break;
43cacb03
FB		 617 } else if (dwc->hsphy_interface &&
618 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
3e10a2ce 619 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 620 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
3e10a2ce 621 } else {
88bc9d19
HK		 622 /* Relying on default value. */
623 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
624 break;
3e10a2ce
HK		 625 }
626 /* FALLTHROUGH */
88bc9d19 627 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
88bc9d19 628 /* FALLTHROUGH */
3e10a2ce
HK		 629 default:
630 break;
631 }
632
32f2ed86
WW		 633 switch (dwc->hsphy_mode) {
634 case USBPHY_INTERFACE_MODE_UTMI:
635 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
636 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
637 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
638 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
639 break;
640 case USBPHY_INTERFACE_MODE_UTMIW:
641 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
642 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
643 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
644 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
645 break;
646 default:
647 break;
648 }
649
2164a476
HR		 650 /*
651 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
652 * '0' during coreConsultant configuration. So default value will
653 * be '0' when the core is reset. Application needs to set it to
654 * '1' after the core initialization is completed.
655 */
656 if (dwc->revision > DWC3_REVISION_194A)
657 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
658
cd72f890 659 if (dwc->dis_u2_susphy_quirk)
0effe0a3
HR		 660 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
661
ec791d14
JY		 662 if (dwc->dis_enblslpm_quirk)
663 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
664
16199f33
WW		 665 if (dwc->dis_u2_freeclk_exists_quirk)
666 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
667
2164a476 668 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
88bc9d19
HK		 669
670 return 0;
b5a65c40
HR		 671}
672
c499ff71
FB		 673static void dwc3_core_exit(struct dwc3 *dwc)
674{
675 dwc3_event_buffers_cleanup(dwc);
676
677 usb_phy_shutdown(dwc->usb2_phy);
678 usb_phy_shutdown(dwc->usb3_phy);
679 phy_exit(dwc->usb2_generic_phy);
680 phy_exit(dwc->usb3_generic_phy);
681
682 usb_phy_set_suspend(dwc->usb2_phy, 1);
683 usb_phy_set_suspend(dwc->usb3_phy, 1);
684 phy_power_off(dwc->usb2_generic_phy);
685 phy_power_off(dwc->usb3_generic_phy);
fe8abf33
MY		 686 clk_bulk_disable(dwc->num_clks, dwc->clks);
687 clk_bulk_unprepare(dwc->num_clks, dwc->clks);
688 reset_control_assert(dwc->reset);
c499ff71
FB		 689}
690
0759956f 691static bool dwc3_core_is_valid(struct dwc3 *dwc)
72246da4 692{
0759956f 693 u32 reg;
72246da4 694
7650bd74 695 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
0759956f 696
7650bd74 697 /* This should read as U3 followed by revision number */
690fb371
JY		 698 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
699 /* Detected DWC_usb3 IP */
700 dwc->revision = reg;
701 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
702 /* Detected DWC_usb31 IP */
703 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
704 dwc->revision |= DWC3_REVISION_IS_DWC31;
705 } else {
0759956f 706 return false;
7650bd74 707 }
7650bd74 708
0759956f
FB		 709 return true;
710}
58a0f23f 711
941f918e 712static void dwc3_core_setup_global_control(struct dwc3 *dwc)
0759956f 713{
941f918e
FB		 714 u32 hwparams4 = dwc->hwparams.hwparams4;
715 u32 reg;
c499ff71 716
4878a028 717 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
3e87c42a 718 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
4878a028 719
164d7731 720 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
4878a028 721 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
32a4a135
FB		 722 /**
723 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
724 * issue which would cause xHCI compliance tests to fail.
725 *
726 * Because of that we cannot enable clock gating on such
727 * configurations.
728 *
729 * Refers to:
730 *
731 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
732 * SOF/ITP Mode Used
733 */
734 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
735 dwc->dr_mode == USB_DR_MODE_OTG) &&
736 (dwc->revision >= DWC3_REVISION_210A &&
737 dwc->revision <= DWC3_REVISION_250A))
738 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
739 else
740 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
4878a028 741 break;
0ffcaf37
FB		 742 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
743 /* enable hibernation here */
744 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
2eac3992
HR		 745
746 /*
747 * REVISIT Enabling this bit so that host-mode hibernation
748 * will work. Device-mode hibernation is not yet implemented.
749 */
750 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
0ffcaf37 751 break;
4878a028 752 default:
5eb30ced
FB		 753 /* nothing */
754 break;
4878a028
SAS		 755 }
756
946bd579
HR		 757 /* check if current dwc3 is on simulation board */
758 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
5eb30ced 759 dev_info(dwc->dev, "Running with FPGA optmizations\n");
946bd579
HR		 760 dwc->is_fpga = true;
761 }
762
3b81221a
HR		 763 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
764 "disable_scramble cannot be used on non-FPGA builds\n");
765
766 if (dwc->disable_scramble_quirk && dwc->is_fpga)
767 reg |= DWC3_GCTL_DISSCRAMBLE;
768 else
769 reg &= ~DWC3_GCTL_DISSCRAMBLE;
770
9a5b2f31
HR		 771 if (dwc->u2exit_lfps_quirk)
772 reg |= DWC3_GCTL_U2EXIT_LFPS;
773
4878a028
SAS		 774 /*
775 * WORKAROUND: DWC3 revisions <1.90a have a bug
1d046793 776 * where the device can fail to connect at SuperSpeed
4878a028 777 * and falls back to high-speed mode which causes
1d046793 778 * the device to enter a Connect/Disconnect loop
4878a028
SAS		 779 */
780 if (dwc->revision < DWC3_REVISION_190A)
781 reg |= DWC3_GCTL_U2RSTECN;
782
783 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
941f918e
FB		 784}
785
f54edb53 786static int dwc3_core_get_phy(struct dwc3 *dwc);
98112041 787static int dwc3_core_ulpi_init(struct dwc3 *dwc);
f54edb53 788
d9612c2f
PM		 789/* set global incr burst type configuration registers */
790static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
791{
792 struct device *dev = dwc->dev;
793 /* incrx_mode : for INCR burst type. */
794 bool incrx_mode;
795 /* incrx_size : for size of INCRX burst. */
796 u32 incrx_size;
797 u32 *vals;
798 u32 cfg;
799 int ntype;
800 int ret;
801 int i;
802
803 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
804
805 /*
806 * Handle property "snps,incr-burst-type-adjustment".
807 * Get the number of value from this property:
808 * result <= 0, means this property is not supported.
809 * result = 1, means INCRx burst mode supported.
810 * result > 1, means undefined length burst mode supported.
811 */
812 ntype = device_property_read_u32_array(dev,
813 "snps,incr-burst-type-adjustment", NULL, 0);
814 if (ntype <= 0)
815 return;
816
817 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
818 if (!vals) {
819 dev_err(dev, "Error to get memory\n");
820 return;
821 }
822
823 /* Get INCR burst type, and parse it */
824 ret = device_property_read_u32_array(dev,
825 "snps,incr-burst-type-adjustment", vals, ntype);
826 if (ret) {
827 dev_err(dev, "Error to get property\n");
828 return;
829 }
830
831 incrx_size = *vals;
832
833 if (ntype > 1) {
834 /* INCRX (undefined length) burst mode */
835 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
836 for (i = 1; i < ntype; i++) {
837 if (vals[i] > incrx_size)
838 incrx_size = vals[i];
839 }
840 } else {
841 /* INCRX burst mode */
842 incrx_mode = INCRX_BURST_MODE;
843 }
844
845 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
846 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
847 if (incrx_mode)
848 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
849 switch (incrx_size) {
850 case 256:
851 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
852 break;
853 case 128:
854 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
855 break;
856 case 64:
857 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
858 break;
859 case 32:
860 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
861 break;
862 case 16:
863 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
864 break;
865 case 8:
866 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
867 break;
868 case 4:
869 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
870 break;
871 case 1:
872 break;
873 default:
874 dev_err(dev, "Invalid property\n");
875 break;
876 }
877
878 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
879}
880
941f918e
FB		 881/**
882 * dwc3_core_init - Low-level initialization of DWC3 Core
883 * @dwc: Pointer to our controller context structure
884 *
885 * Returns 0 on success otherwise negative errno.
886 */
887static int dwc3_core_init(struct dwc3 *dwc)
888{
889 u32 reg;
890 int ret;
891
892 if (!dwc3_core_is_valid(dwc)) {
893 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
894 ret = -ENODEV;
895 goto err0;
896 }
897
898 /*
899 * Write Linux Version Code to our GUID register so it's easy to figure
900 * out which kernel version a bug was found.
901 */
902 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
903
904 /* Handle USB2.0-only core configuration */
905 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
906 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
907 if (dwc->maximum_speed == USB_SPEED_SUPER)
908 dwc->maximum_speed = USB_SPEED_HIGH;
909 }
910
98112041 911 ret = dwc3_phy_setup(dwc);
941f918e
FB		 912 if (ret)
913 goto err0;
4878a028 914
98112041
RQ		 915 if (!dwc->ulpi_ready) {
916 ret = dwc3_core_ulpi_init(dwc);
917 if (ret)
918 goto err0;
919 dwc->ulpi_ready = true;
920 }
4878a028 921
98112041
RQ		 922 if (!dwc->phys_ready) {
923 ret = dwc3_core_get_phy(dwc);
924 if (ret)
925 goto err0a;
926 dwc->phys_ready = true;
927 }
928
929 ret = dwc3_core_soft_reset(dwc);
f54edb53 930 if (ret)
98112041 931 goto err0a;
f54edb53 932
941f918e 933 dwc3_core_setup_global_control(dwc);
c499ff71 934 dwc3_core_num_eps(dwc);
0ffcaf37
FB		 935
936 ret = dwc3_setup_scratch_buffers(dwc);
937 if (ret)
c499ff71
FB		 938 goto err1;
939
940 /* Adjust Frame Length */
941 dwc3_frame_length_adjustment(dwc);
942
d9612c2f
PM		 943 dwc3_set_incr_burst_type(dwc);
944
c499ff71
FB		 945 usb_phy_set_suspend(dwc->usb2_phy, 0);
946 usb_phy_set_suspend(dwc->usb3_phy, 0);
947 ret = phy_power_on(dwc->usb2_generic_phy);
948 if (ret < 0)
0ffcaf37
FB		 949 goto err2;
950
c499ff71
FB		 951 ret = phy_power_on(dwc->usb3_generic_phy);
952 if (ret < 0)
953 goto err3;
954
955 ret = dwc3_event_buffers_setup(dwc);
956 if (ret) {
957 dev_err(dwc->dev, "failed to setup event buffers\n");
958 goto err4;
959 }
960
06281d46
JY		 961 /*
962 * ENDXFER polling is available on version 3.10a and later of
963 * the DWC_usb3 controller. It is NOT available in the
964 * DWC_usb31 controller.
965 */
966 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
967 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
968 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
969 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
970 }
971
65db7a0c 972 if (dwc->revision >= DWC3_REVISION_250A) {
0bb39ca1 973 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
65db7a0c
WW		 974
975 /*
976 * Enable hardware control of sending remote wakeup
977 * in HS when the device is in the L1 state.
978 */
979 if (dwc->revision >= DWC3_REVISION_290A)
980 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
981
982 if (dwc->dis_tx_ipgap_linecheck_quirk)
983 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
984
0bb39ca1
JY		 985 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
986 }
987
938a5ad1
TN		 988 /*
989 * Must config both number of packets and max burst settings to enable
990 * RX and/or TX threshold.
991 */
992 if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
993 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
994 u8 rx_maxburst = dwc->rx_max_burst_prd;
995 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
996 u8 tx_maxburst = dwc->tx_max_burst_prd;
997
998 if (rx_thr_num && rx_maxburst) {
999 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1000 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1001
1002 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1003 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1004
1005 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1006 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1007
1008 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1009 }
1010
1011 if (tx_thr_num && tx_maxburst) {
1012 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1013 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1014
1015 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1016 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1017
1018 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1019 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1020
1021 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1022 }
1023 }
1024
72246da4
FB		 1025 return 0;
1026
c499ff71 1027err4:
9b9d7cdd 1028 phy_power_off(dwc->usb3_generic_phy);
c499ff71
FB		 1029
1030err3:
9b9d7cdd 1031 phy_power_off(dwc->usb2_generic_phy);
c499ff71 1032
0ffcaf37 1033err2:
c499ff71
FB		 1034 usb_phy_set_suspend(dwc->usb2_phy, 1);
1035 usb_phy_set_suspend(dwc->usb3_phy, 1);
0ffcaf37
FB		 1036
1037err1:
1038 usb_phy_shutdown(dwc->usb2_phy);
1039 usb_phy_shutdown(dwc->usb3_phy);
57303488
KVA		 1040 phy_exit(dwc->usb2_generic_phy);
1041 phy_exit(dwc->usb3_generic_phy);
0ffcaf37 1042
98112041
RQ		 1043err0a:
1044 dwc3_ulpi_exit(dwc);
1045
72246da4
FB		 1046err0:
1047 return ret;
1048}
1049
3c9f94ac 1050static int dwc3_core_get_phy(struct dwc3 *dwc)
72246da4 1051{
3c9f94ac 1052 struct device *dev = dwc->dev;
941ea361 1053 struct device_node *node = dev->of_node;
3c9f94ac 1054 int ret;
72246da4 1055
5088b6f5
KVA		 1056 if (node) {
1057 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1058 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
bb674907
FB		 1059 } else {
1060 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1061 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
5088b6f5
KVA		 1062 }
1063
d105e7f8
FB		 1064 if (IS_ERR(dwc->usb2_phy)) {
1065 ret = PTR_ERR(dwc->usb2_phy);
122f06e6
KVA		 1066 if (ret == -ENXIO || ret == -ENODEV) {
1067 dwc->usb2_phy = NULL;
1068 } else if (ret == -EPROBE_DEFER) {
d105e7f8 1069 return ret;
122f06e6
KVA		 1070 } else {
1071 dev_err(dev, "no usb2 phy configured\n");
1072 return ret;
1073 }
51e1e7bc
FB		 1074 }
1075
d105e7f8 1076 if (IS_ERR(dwc->usb3_phy)) {
315955d7 1077 ret = PTR_ERR(dwc->usb3_phy);
122f06e6
KVA		 1078 if (ret == -ENXIO || ret == -ENODEV) {
1079 dwc->usb3_phy = NULL;
1080 } else if (ret == -EPROBE_DEFER) {
d105e7f8 1081 return ret;
122f06e6
KVA		 1082 } else {
1083 dev_err(dev, "no usb3 phy configured\n");
1084 return ret;
1085 }
51e1e7bc
FB		 1086 }
1087
57303488
KVA		 1088 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1089 if (IS_ERR(dwc->usb2_generic_phy)) {
1090 ret = PTR_ERR(dwc->usb2_generic_phy);
1091 if (ret == -ENOSYS || ret == -ENODEV) {
1092 dwc->usb2_generic_phy = NULL;
1093 } else if (ret == -EPROBE_DEFER) {
1094 return ret;
1095 } else {
1096 dev_err(dev, "no usb2 phy configured\n");
1097 return ret;
1098 }
1099 }
1100
1101 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1102 if (IS_ERR(dwc->usb3_generic_phy)) {
1103 ret = PTR_ERR(dwc->usb3_generic_phy);
1104 if (ret == -ENOSYS || ret == -ENODEV) {
1105 dwc->usb3_generic_phy = NULL;
1106 } else if (ret == -EPROBE_DEFER) {
1107 return ret;
1108 } else {
1109 dev_err(dev, "no usb3 phy configured\n");
1110 return ret;
1111 }
1112 }
1113
3c9f94ac
FB		 1114 return 0;
1115}
1116
5f94adfe
FB		 1117static int dwc3_core_init_mode(struct dwc3 *dwc)
1118{
1119 struct device *dev = dwc->dev;
1120 int ret;
1121
1122 switch (dwc->dr_mode) {
1123 case USB_DR_MODE_PERIPHERAL:
41ce1456 1124 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
958d1a4c
FB		 1125
1126 if (dwc->usb2_phy)
1127 otg_set_vbus(dwc->usb2_phy->otg, false);
644cbbc3
MG		 1128 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1129 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
958d1a4c 1130
5f94adfe
FB		 1131 ret = dwc3_gadget_init(dwc);
1132 if (ret) {
9522def4
RQ		 1133 if (ret != -EPROBE_DEFER)
1134 dev_err(dev, "failed to initialize gadget\n");
5f94adfe
FB		 1135 return ret;
1136 }
1137 break;
1138 case USB_DR_MODE_HOST:
41ce1456 1139 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
958d1a4c
FB		 1140
1141 if (dwc->usb2_phy)
1142 otg_set_vbus(dwc->usb2_phy->otg, true);
644cbbc3
MG		 1143 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1144 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
958d1a4c 1145
5f94adfe
FB		 1146 ret = dwc3_host_init(dwc);
1147 if (ret) {
9522def4
RQ		 1148 if (ret != -EPROBE_DEFER)
1149 dev_err(dev, "failed to initialize host\n");
5f94adfe
FB		 1150 return ret;
1151 }
d8c80bb3 1152 phy_calibrate(dwc->usb2_generic_phy);
5f94adfe
FB		 1153 break;
1154 case USB_DR_MODE_OTG:
41ce1456 1155 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
9840354f
RQ		 1156 ret = dwc3_drd_init(dwc);
1157 if (ret) {
1158 if (ret != -EPROBE_DEFER)
1159 dev_err(dev, "failed to initialize dual-role\n");
1160 return ret;
1161 }
5f94adfe
FB		 1162 break;
1163 default:
1164 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1165 return -EINVAL;
1166 }
1167
1168 return 0;
1169}
1170
1171static void dwc3_core_exit_mode(struct dwc3 *dwc)
1172{
1173 switch (dwc->dr_mode) {
1174 case USB_DR_MODE_PERIPHERAL:
1175 dwc3_gadget_exit(dwc);
1176 break;
1177 case USB_DR_MODE_HOST:
1178 dwc3_host_exit(dwc);
1179 break;
1180 case USB_DR_MODE_OTG:
9840354f 1181 dwc3_drd_exit(dwc);
5f94adfe
FB		 1182 break;
1183 default:
1184 /* do nothing */
1185 break;
1186 }
1187}
1188
c5ac6116 1189static void dwc3_get_properties(struct dwc3 *dwc)
3c9f94ac 1190{
c5ac6116 1191 struct device *dev = dwc->dev;
80caf7d2 1192 u8 lpm_nyet_threshold;
6b6a0c9a 1193 u8 tx_de_emphasis;
460d098c 1194 u8 hird_threshold;
938a5ad1
TN		 1195 u8 rx_thr_num_pkt_prd;
1196 u8 rx_max_burst_prd;
1197 u8 tx_thr_num_pkt_prd;
1198 u8 tx_max_burst_prd;
3c9f94ac 1199
80caf7d2
HR		 1200 /* default to highest possible threshold */
1201 lpm_nyet_threshold = 0xff;
1202
6b6a0c9a
HR		 1203 /* default to -3.5dB de-emphasis */
1204 tx_de_emphasis = 1;
1205
460d098c
HR		 1206 /*
1207 * default to assert utmi_sleep_n and use maximum allowed HIRD
1208 * threshold value of 0b1100
1209 */
1210 hird_threshold = 12;
1211
63863b98 1212 dwc->maximum_speed = usb_get_maximum_speed(dev);
06e7114f 1213 dwc->dr_mode = usb_get_dr_mode(dev);
32f2ed86 1214 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
63863b98 1215
d64ff406
AB		 1216 dwc->sysdev_is_parent = device_property_read_bool(dev,
1217 "linux,sysdev_is_parent");
1218 if (dwc->sysdev_is_parent)
1219 dwc->sysdev = dwc->dev->parent;
1220 else
1221 dwc->sysdev = dwc->dev;
1222
3d128919 1223 dwc->has_lpm_erratum = device_property_read_bool(dev,
80caf7d2 1224 "snps,has-lpm-erratum");
3d128919 1225 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
80caf7d2 1226 &lpm_nyet_threshold);
3d128919 1227 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
460d098c 1228 "snps,is-utmi-l1-suspend");
3d128919 1229 device_property_read_u8(dev, "snps,hird-threshold",
460d098c 1230 &hird_threshold);
3d128919 1231 dwc->usb3_lpm_capable = device_property_read_bool(dev,
eac68e8f 1232 "snps,usb3_lpm_capable");
938a5ad1
TN		 1233 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1234 &rx_thr_num_pkt_prd);
1235 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1236 &rx_max_burst_prd);
1237 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1238 &tx_thr_num_pkt_prd);
1239 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1240 &tx_max_burst_prd);
3c9f94ac 1241
3d128919 1242 dwc->disable_scramble_quirk = device_property_read_bool(dev,
3b81221a 1243 "snps,disable_scramble_quirk");
3d128919 1244 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
9a5b2f31 1245 "snps,u2exit_lfps_quirk");
3d128919 1246 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
b5a65c40 1247 "snps,u2ss_inp3_quirk");
3d128919 1248 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
df31f5b3 1249 "snps,req_p1p2p3_quirk");
3d128919 1250 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
a2a1d0f5 1251 "snps,del_p1p2p3_quirk");
3d128919 1252 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
41c06ffd 1253 "snps,del_phy_power_chg_quirk");
3d128919 1254 dwc->lfps_filter_quirk = device_property_read_bool(dev,
fb67afca 1255 "snps,lfps_filter_quirk");
3d128919 1256 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
14f4ac53 1257 "snps,rx_detect_poll_quirk");
3d128919 1258 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
59acfa20 1259 "snps,dis_u3_susphy_quirk");
3d128919 1260 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
0effe0a3 1261 "snps,dis_u2_susphy_quirk");
ec791d14
JY		 1262 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1263 "snps,dis_enblslpm_quirk");
e58dd357
RB		 1264 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1265 "snps,dis_rxdet_inp3_quirk");
16199f33
WW		 1266 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1267 "snps,dis-u2-freeclk-exists-quirk");
00fe081d
WW		 1268 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1269 "snps,dis-del-phy-power-chg-quirk");
65db7a0c
WW		 1270 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1271 "snps,dis-tx-ipgap-linecheck-quirk");
6b6a0c9a 1272
3d128919 1273 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
6b6a0c9a 1274 "snps,tx_de_emphasis_quirk");
3d128919 1275 device_property_read_u8(dev, "snps,tx_de_emphasis",
6b6a0c9a 1276 &tx_de_emphasis);
3d128919
HK		 1277 device_property_read_string(dev, "snps,hsphy_interface",
1278 &dwc->hsphy_interface);
1279 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
bcdb3272 1280 &dwc->fladj);
3d128919 1281
42bf02ec
RQ		 1282 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1283 "snps,dis_metastability_quirk");
1284
80caf7d2 1285 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
6b6a0c9a 1286 dwc->tx_de_emphasis = tx_de_emphasis;
80caf7d2 1287
460d098c
HR		 1288 dwc->hird_threshold = hird_threshold
1289 | (dwc->is_utmi_l1_suspend << 4);
1290
938a5ad1
TN		 1291 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1292 dwc->rx_max_burst_prd = rx_max_burst_prd;
1293
1294 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1295 dwc->tx_max_burst_prd = tx_max_burst_prd;
1296
cf40b86b
JY		 1297 dwc->imod_interval = 0;
1298}
1299
1300/* check whether the core supports IMOD */
1301bool dwc3_has_imod(struct dwc3 *dwc)
1302{
1303 return ((dwc3_is_usb3(dwc) &&
1304 dwc->revision >= DWC3_REVISION_300A) ||
1305 (dwc3_is_usb31(dwc) &&
1306 dwc->revision >= DWC3_USB31_REVISION_120A));
c5ac6116
FB		 1307}
1308
7ac51a12
JY		 1309static void dwc3_check_params(struct dwc3 *dwc)
1310{
1311 struct device *dev = dwc->dev;
1312
cf40b86b
JY		 1313 /* Check for proper value of imod_interval */
1314 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1315 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1316 dwc->imod_interval = 0;
1317 }
1318
28632b44
JY		 1319 /*
1320 * Workaround for STAR 9000961433 which affects only version
1321 * 3.00a of the DWC_usb3 core. This prevents the controller
1322 * interrupt from being masked while handling events. IMOD
1323 * allows us to work around this issue. Enable it for the
1324 * affected version.
1325 */
1326 if (!dwc->imod_interval &&
1327 (dwc->revision == DWC3_REVISION_300A))
1328 dwc->imod_interval = 1;
1329
7ac51a12
JY		 1330 /* Check the maximum_speed parameter */
1331 switch (dwc->maximum_speed) {
1332 case USB_SPEED_LOW:
1333 case USB_SPEED_FULL:
1334 case USB_SPEED_HIGH:
1335 case USB_SPEED_SUPER:
1336 case USB_SPEED_SUPER_PLUS:
1337 break;
1338 default:
1339 dev_err(dev, "invalid maximum_speed parameter %d\n",
1340 dwc->maximum_speed);
1341 /* fall through */
1342 case USB_SPEED_UNKNOWN:
1343 /* default to superspeed */
1344 dwc->maximum_speed = USB_SPEED_SUPER;
1345
1346 /*
1347 * default to superspeed plus if we are capable.
1348 */
1349 if (dwc3_is_usb31(dwc) &&
1350 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1351 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1352 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1353
1354 break;
1355 }
1356}
1357
c5ac6116
FB		 1358static int dwc3_probe(struct platform_device *pdev)
1359{
1360 struct device *dev = &pdev->dev;
44feb8e6 1361 struct resource *res, dwc_res;
c5ac6116
FB		 1362 struct dwc3 *dwc;
1363
1364 int ret;
1365
1366 void __iomem *regs;
1367
1368 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1369 if (!dwc)
1370 return -ENOMEM;
1371
fe8abf33
MY		 1372 dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks),
1373 GFP_KERNEL);
1374 if (!dwc->clks)
1375 return -ENOMEM;
1376
c5ac6116
FB		 1377 dwc->dev = dev;
1378
1379 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1380 if (!res) {
1381 dev_err(dev, "missing memory resource\n");
1382 return -ENODEV;
1383 }
1384
1385 dwc->xhci_resources[0].start = res->start;
1386 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1387 DWC3_XHCI_REGS_END;
1388 dwc->xhci_resources[0].flags = res->flags;
1389 dwc->xhci_resources[0].name = res->name;
1390
c5ac6116
FB		 1391 /*
1392 * Request memory region but exclude xHCI regs,
1393 * since it will be requested by the xhci-plat driver.
1394 */
44feb8e6
MY		 1395 dwc_res = *res;
1396 dwc_res.start += DWC3_GLOBALS_REGS_START;
1397
1398 regs = devm_ioremap_resource(dev, &dwc_res);
1399 if (IS_ERR(regs))
1400 return PTR_ERR(regs);
c5ac6116
FB		 1401
1402 dwc->regs = regs;
44feb8e6 1403 dwc->regs_size = resource_size(&dwc_res);
c5ac6116
FB		 1404
1405 dwc3_get_properties(dwc);
1406
fe8abf33
MY		 1407 dwc->reset = devm_reset_control_get_optional_shared(dev, NULL);
1408 if (IS_ERR(dwc->reset))
1409 return PTR_ERR(dwc->reset);
1410
61527777
HG		 1411 if (dev->of_node) {
1412 dwc->num_clks = ARRAY_SIZE(dwc3_core_clks);
1413
1414 ret = clk_bulk_get(dev, dwc->num_clks, dwc->clks);
1415 if (ret == -EPROBE_DEFER)
1416 return ret;
1417 /*
1418 * Clocks are optional, but new DT platforms should support all
1419 * clocks as required by the DT-binding.
1420 */
1421 if (ret)
1422 dwc->num_clks = 0;
1423 }
fe8abf33
MY		 1424
1425 ret = reset_control_deassert(dwc->reset);
1426 if (ret)
1427 goto put_clks;
1428
1429 ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
1430 if (ret)
1431 goto assert_reset;
1432
1433 ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1434 if (ret)
1435 goto unprepare_clks;
1436
6c89cce0 1437 platform_set_drvdata(pdev, dwc);
2917e718 1438 dwc3_cache_hwparams(dwc);
6c89cce0 1439
72246da4 1440 spin_lock_init(&dwc->lock);
72246da4 1441
fc8bb91b
FB		 1442 pm_runtime_set_active(dev);
1443 pm_runtime_use_autosuspend(dev);
1444 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
802ca850 1445 pm_runtime_enable(dev);
32808237
RQ		 1446 ret = pm_runtime_get_sync(dev);
1447 if (ret < 0)
1448 goto err1;
1449
802ca850 1450 pm_runtime_forbid(dev);
72246da4 1451
3921426b
FB		 1452 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1453 if (ret) {
1454 dev_err(dwc->dev, "failed to allocate event buffers\n");
1455 ret = -ENOMEM;
32808237 1456 goto err2;
3921426b
FB		 1457 }
1458
9d6173e1
TN		 1459 ret = dwc3_get_dr_mode(dwc);
1460 if (ret)
1461 goto err3;
32a4a135 1462
c499ff71
FB		 1463 ret = dwc3_alloc_scratch_buffers(dwc);
1464 if (ret)
32808237 1465 goto err3;
c499ff71 1466
72246da4
FB		 1467 ret = dwc3_core_init(dwc);
1468 if (ret) {
802ca850 1469 dev_err(dev, "failed to initialize core\n");
32808237 1470 goto err4;
72246da4
FB		 1471 }
1472
7ac51a12 1473 dwc3_check_params(dwc);
2c7f1bd9 1474
5f94adfe
FB		 1475 ret = dwc3_core_init_mode(dwc);
1476 if (ret)
32808237 1477 goto err5;
72246da4 1478
4e9f3118 1479 dwc3_debugfs_init(dwc);
fc8bb91b 1480 pm_runtime_put(dev);
72246da4
FB		 1481
1482 return 0;
1483
32808237 1484err5:
c499ff71 1485 dwc3_event_buffers_cleanup(dwc);
57303488 1486
32808237 1487err4:
c499ff71 1488 dwc3_free_scratch_buffers(dwc);
72246da4 1489
32808237 1490err3:
3921426b
FB		 1491 dwc3_free_event_buffers(dwc);
1492
32808237
RQ		 1493err2:
1494 pm_runtime_allow(&pdev->dev);
1495
1496err1:
1497 pm_runtime_put_sync(&pdev->dev);
1498 pm_runtime_disable(&pdev->dev);
1499
fe8abf33
MY		 1500 clk_bulk_disable(dwc->num_clks, dwc->clks);
1501unprepare_clks:
1502 clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1503assert_reset:
1504 reset_control_assert(dwc->reset);
1505put_clks:
1506 clk_bulk_put(dwc->num_clks, dwc->clks);
1507
72246da4
FB		 1508 return ret;
1509}
1510
fb4e98ab 1511static int dwc3_remove(struct platform_device *pdev)
72246da4 1512{
72246da4 1513 struct dwc3 *dwc = platform_get_drvdata(pdev);
3da1f6ee 1514
fc8bb91b 1515 pm_runtime_get_sync(&pdev->dev);
72246da4 1516
dc99f16f
FB		 1517 dwc3_debugfs_exit(dwc);
1518 dwc3_core_exit_mode(dwc);
8ba007a9 1519
72246da4 1520 dwc3_core_exit(dwc);
88bc9d19 1521 dwc3_ulpi_exit(dwc);
72246da4 1522
16b972a5 1523 pm_runtime_put_sync(&pdev->dev);
fc8bb91b 1524 pm_runtime_allow(&pdev->dev);
72246da4
FB		 1525 pm_runtime_disable(&pdev->dev);
1526
fc8bb91b
FB		 1527 dwc3_free_event_buffers(dwc);
1528 dwc3_free_scratch_buffers(dwc);
fe8abf33 1529 clk_bulk_put(dwc->num_clks, dwc->clks);
fc8bb91b 1530
72246da4
FB		 1531 return 0;
1532}
1533
fc8bb91b 1534#ifdef CONFIG_PM
fe8abf33
MY		 1535static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1536{
1537 int ret;
1538
1539 ret = reset_control_deassert(dwc->reset);
1540 if (ret)
1541 return ret;
1542
1543 ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
1544 if (ret)
1545 goto assert_reset;
1546
1547 ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1548 if (ret)
1549 goto unprepare_clks;
1550
1551 ret = dwc3_core_init(dwc);
1552 if (ret)
1553 goto disable_clks;
1554
1555 return 0;
1556
1557disable_clks:
1558 clk_bulk_disable(dwc->num_clks, dwc->clks);
1559unprepare_clks:
1560 clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1561assert_reset:
1562 reset_control_assert(dwc->reset);
1563
1564 return ret;
1565}
1566
c4a5153e 1567static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
7415f17c 1568{
fc8bb91b 1569 unsigned long flags;
bcb12877 1570 u32 reg;
7415f17c 1571
689bf72c
MG		 1572 switch (dwc->current_dr_role) {
1573 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b 1574 spin_lock_irqsave(&dwc->lock, flags);
7415f17c 1575 dwc3_gadget_suspend(dwc);
fc8bb91b 1576 spin_unlock_irqrestore(&dwc->lock, flags);
689bf72c 1577 dwc3_core_exit(dwc);
51f5d49a 1578 break;
689bf72c 1579 case DWC3_GCTL_PRTCAP_HOST:
bcb12877 1580 if (!PMSG_IS_AUTO(msg)) {
c4a5153e 1581 dwc3_core_exit(dwc);
bcb12877
MG		 1582 break;
1583 }
1584
1585 /* Let controller to suspend HSPHY before PHY driver suspends */
1586 if (dwc->dis_u2_susphy_quirk ||
1587 dwc->dis_enblslpm_quirk) {
1588 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1589 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1590 DWC3_GUSB2PHYCFG_SUSPHY;
1591 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1592
1593 /* Give some time for USB2 PHY to suspend */
1594 usleep_range(5000, 6000);
1595 }
1596
1597 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1598 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
c4a5153e 1599 break;
f09cc79b
RQ		 1600 case DWC3_GCTL_PRTCAP_OTG:
1601 /* do nothing during runtime_suspend */
1602 if (PMSG_IS_AUTO(msg))
1603 break;
1604
1605 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1606 spin_lock_irqsave(&dwc->lock, flags);
1607 dwc3_gadget_suspend(dwc);
1608 spin_unlock_irqrestore(&dwc->lock, flags);
1609 }
1610
1611 dwc3_otg_exit(dwc);
1612 dwc3_core_exit(dwc);
1613 break;
7415f17c 1614 default:
51f5d49a 1615 /* do nothing */
7415f17c
FB		 1616 break;
1617 }
1618
7415f17c
FB		 1619 return 0;
1620}
1621
c4a5153e 1622static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
7415f17c 1623{
fc8bb91b 1624 unsigned long flags;
57303488 1625 int ret;
bcb12877 1626 u32 reg;
7415f17c 1627
689bf72c
MG		 1628 switch (dwc->current_dr_role) {
1629 case DWC3_GCTL_PRTCAP_DEVICE:
fe8abf33 1630 ret = dwc3_core_init_for_resume(dwc);
689bf72c
MG		 1631 if (ret)
1632 return ret;
5c4ad318 1633
7d11c3ac 1634 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
fc8bb91b 1635 spin_lock_irqsave(&dwc->lock, flags);
7415f17c 1636 dwc3_gadget_resume(dwc);
fc8bb91b 1637 spin_unlock_irqrestore(&dwc->lock, flags);
689bf72c
MG		 1638 break;
1639 case DWC3_GCTL_PRTCAP_HOST:
c4a5153e 1640 if (!PMSG_IS_AUTO(msg)) {
fe8abf33 1641 ret = dwc3_core_init_for_resume(dwc);
c4a5153e
MG		 1642 if (ret)
1643 return ret;
7d11c3ac 1644 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
bcb12877 1645 break;
c4a5153e 1646 }
bcb12877
MG		 1647 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1648 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1649 if (dwc->dis_u2_susphy_quirk)
1650 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1651
1652 if (dwc->dis_enblslpm_quirk)
1653 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1654
1655 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1656
1657 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1658 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
f09cc79b
RQ		 1659 break;
1660 case DWC3_GCTL_PRTCAP_OTG:
1661 /* nothing to do on runtime_resume */
1662 if (PMSG_IS_AUTO(msg))
1663 break;
1664
1665 ret = dwc3_core_init(dwc);
1666 if (ret)
1667 return ret;
1668
1669 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1670
1671 dwc3_otg_init(dwc);
1672 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1673 dwc3_otg_host_init(dwc);
1674 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1675 spin_lock_irqsave(&dwc->lock, flags);
1676 dwc3_gadget_resume(dwc);
1677 spin_unlock_irqrestore(&dwc->lock, flags);
c4a5153e 1678 }
f09cc79b 1679
c4a5153e 1680 break;
7415f17c
FB		 1681 default:
1682 /* do nothing */
1683 break;
1684 }
1685
fc8bb91b
FB		 1686 return 0;
1687}
1688
1689static int dwc3_runtime_checks(struct dwc3 *dwc)
1690{
689bf72c 1691 switch (dwc->current_dr_role) {
c4a5153e 1692 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 1693 if (dwc->connected)
1694 return -EBUSY;
1695 break;
c4a5153e 1696 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 1697 default:
1698 /* do nothing */
1699 break;
1700 }
1701
1702 return 0;
1703}
1704
1705static int dwc3_runtime_suspend(struct device *dev)
1706{
1707 struct dwc3 *dwc = dev_get_drvdata(dev);
1708 int ret;
1709
1710 if (dwc3_runtime_checks(dwc))
1711 return -EBUSY;
1712
c4a5153e 1713 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
fc8bb91b
FB		 1714 if (ret)
1715 return ret;
1716
1717 device_init_wakeup(dev, true);
1718
1719 return 0;
1720}
1721
1722static int dwc3_runtime_resume(struct device *dev)
1723{
1724 struct dwc3 *dwc = dev_get_drvdata(dev);
1725 int ret;
1726
1727 device_init_wakeup(dev, false);
1728
c4a5153e 1729 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
fc8bb91b
FB		 1730 if (ret)
1731 return ret;
1732
689bf72c
MG		 1733 switch (dwc->current_dr_role) {
1734 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 1735 dwc3_gadget_process_pending_events(dwc);
1736 break;
689bf72c 1737 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 1738 default:
1739 /* do nothing */
1740 break;
1741 }
1742
1743 pm_runtime_mark_last_busy(dev);
1744
1745 return 0;
1746}
1747
1748static int dwc3_runtime_idle(struct device *dev)
1749{
1750 struct dwc3 *dwc = dev_get_drvdata(dev);
1751
689bf72c
MG		 1752 switch (dwc->current_dr_role) {
1753 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 1754 if (dwc3_runtime_checks(dwc))
1755 return -EBUSY;
1756 break;
689bf72c 1757 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 1758 default:
1759 /* do nothing */
1760 break;
1761 }
1762
1763 pm_runtime_mark_last_busy(dev);
1764 pm_runtime_autosuspend(dev);
1765
1766 return 0;
1767}
1768#endif /* CONFIG_PM */
1769
1770#ifdef CONFIG_PM_SLEEP
1771static int dwc3_suspend(struct device *dev)
1772{
1773 struct dwc3 *dwc = dev_get_drvdata(dev);
1774 int ret;
1775
c4a5153e 1776 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
fc8bb91b
FB		 1777 if (ret)
1778 return ret;
1779
1780 pinctrl_pm_select_sleep_state(dev);
1781
1782 return 0;
1783}
1784
1785static int dwc3_resume(struct device *dev)
1786{
1787 struct dwc3 *dwc = dev_get_drvdata(dev);
1788 int ret;
1789
1790 pinctrl_pm_select_default_state(dev);
1791
c4a5153e 1792 ret = dwc3_resume_common(dwc, PMSG_RESUME);
fc8bb91b
FB		 1793 if (ret)
1794 return ret;
1795
7415f17c
FB		 1796 pm_runtime_disable(dev);
1797 pm_runtime_set_active(dev);
1798 pm_runtime_enable(dev);
1799
1800 return 0;
1801}
7f370ed0 1802#endif /* CONFIG_PM_SLEEP */
7415f17c
FB		 1803
1804static const struct dev_pm_ops dwc3_dev_pm_ops = {
7415f17c 1805 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
fc8bb91b
FB		 1806 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1807 dwc3_runtime_idle)
7415f17c
FB		 1808};
1809
5088b6f5
KVA		 1810#ifdef CONFIG_OF
1811static const struct of_device_id of_dwc3_match[] = {
22a5aa17
FB		 1812 {
1813 .compatible = "snps,dwc3"
1814 },
5088b6f5
KVA		 1815 {
1816 .compatible = "synopsys,dwc3"
1817 },
1818 { },
1819};
1820MODULE_DEVICE_TABLE(of, of_dwc3_match);
1821#endif
1822
404905a6
HK		 1823#ifdef CONFIG_ACPI
1824
1825#define ACPI_ID_INTEL_BSW "808622B7"
1826
1827static const struct acpi_device_id dwc3_acpi_match[] = {
1828 { ACPI_ID_INTEL_BSW, 0 },
1829 { },
1830};
1831MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1832#endif
1833
72246da4
FB		 1834static struct platform_driver dwc3_driver = {
1835 .probe = dwc3_probe,
7690417d 1836 .remove = dwc3_remove,
72246da4
FB		 1837 .driver = {
1838 .name = "dwc3",
5088b6f5 1839 .of_match_table = of_match_ptr(of_dwc3_match),
404905a6 1840 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
7f370ed0 1841 .pm = &dwc3_dev_pm_ops,
72246da4 1842 },
72246da4
FB		 1843};
1844
b1116dcc
TK		 1845module_platform_driver(dwc3_driver);
1846
7ae4fc4d 1847MODULE_ALIAS("platform:dwc3");
72246da4 1848MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
5945f789 1849MODULE_LICENSE("GPL v2");
72246da4 1850MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux 6.x block layer and io_uring tree(s)