projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
usb: dwc3: make macros safe to expression arguments
[linux-block.git] / drivers / usb / dwc3 / core.c
CommitLineData
72246da4
FB		 1/**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4 17 *
5945f789
FB		 18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
72246da4
FB		 20 */
21
fa0ea13e 22#include <linux/version.h>
a72e658b 23#include <linux/module.h>
72246da4
FB		 24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/spinlock.h>
27#include <linux/platform_device.h>
28#include <linux/pm_runtime.h>
29#include <linux/interrupt.h>
30#include <linux/ioport.h>
31#include <linux/io.h>
32#include <linux/list.h>
33#include <linux/delay.h>
34#include <linux/dma-mapping.h>
457e84b6 35#include <linux/of.h>
404905a6 36#include <linux/acpi.h>
6344475f 37#include <linux/pinctrl/consumer.h>
72246da4
FB		 38
39#include <linux/usb/ch9.h>
40#include <linux/usb/gadget.h>
f7e846f0 41#include <linux/usb/of.h>
a45c82b8 42#include <linux/usb/otg.h>
72246da4
FB		 43
44#include "core.h"
45#include "gadget.h"
46#include "io.h"
47
48#include "debug.h"
49
fc8bb91b 50#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
8300dd23 51
9d6173e1
TN		 52/**
53 * dwc3_get_dr_mode - Validates and sets dr_mode
54 * @dwc: pointer to our context structure
55 */
56static int dwc3_get_dr_mode(struct dwc3 *dwc)
57{
58 enum usb_dr_mode mode;
59 struct device *dev = dwc->dev;
60 unsigned int hw_mode;
61
62 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
63 dwc->dr_mode = USB_DR_MODE_OTG;
64
65 mode = dwc->dr_mode;
66 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
67
68 switch (hw_mode) {
69 case DWC3_GHWPARAMS0_MODE_GADGET:
70 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
71 dev_err(dev,
72 "Controller does not support host mode.\n");
73 return -EINVAL;
74 }
75 mode = USB_DR_MODE_PERIPHERAL;
76 break;
77 case DWC3_GHWPARAMS0_MODE_HOST:
78 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
79 dev_err(dev,
80 "Controller does not support device mode.\n");
81 return -EINVAL;
82 }
83 mode = USB_DR_MODE_HOST;
84 break;
85 default:
86 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
87 mode = USB_DR_MODE_HOST;
88 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
89 mode = USB_DR_MODE_PERIPHERAL;
90 }
91
92 if (mode != dwc->dr_mode) {
93 dev_warn(dev,
94 "Configuration mismatch. dr_mode forced to %s\n",
95 mode == USB_DR_MODE_HOST ? "host" : "gadget");
96
97 dwc->dr_mode = mode;
98 }
99
100 return 0;
101}
102
3140e8cb
SAS		 103void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
104{
105 u32 reg;
106
107 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
108 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
109 reg |= DWC3_GCTL_PRTCAPDIR(mode);
110 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
111}
8300dd23 112
cf6d867d
FB		 113u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
114{
115 struct dwc3 *dwc = dep->dwc;
116 u32 reg;
117
118 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
119 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
120 DWC3_GDBGFIFOSPACE_TYPE(type));
121
122 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
123
124 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
125}
126
72246da4
FB		 127/**
128 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
129 * @dwc: pointer to our context structure
130 */
57303488 131static int dwc3_core_soft_reset(struct dwc3 *dwc)
72246da4
FB		 132{
133 u32 reg;
f59dcab1 134 int retries = 1000;
57303488 135 int ret;
72246da4 136
51e1e7bc
FB		 137 usb_phy_init(dwc->usb2_phy);
138 usb_phy_init(dwc->usb3_phy);
57303488
KVA		 139 ret = phy_init(dwc->usb2_generic_phy);
140 if (ret < 0)
141 return ret;
142
143 ret = phy_init(dwc->usb3_generic_phy);
144 if (ret < 0) {
145 phy_exit(dwc->usb2_generic_phy);
146 return ret;
147 }
72246da4 148
f59dcab1
FB		 149 /*
150 * We're resetting only the device side because, if we're in host mode,
151 * XHCI driver will reset the host block. If dwc3 was configured for
152 * host-only mode, then we can return early.
153 */
154 if (dwc->dr_mode == USB_DR_MODE_HOST)
155 return 0;
72246da4 156
f59dcab1
FB		 157 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
158 reg |= DWC3_DCTL_CSFTRST;
159 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 160
f59dcab1
FB		 161 do {
162 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
163 if (!(reg & DWC3_DCTL_CSFTRST))
164 return 0;
45627ac6 165
f59dcab1
FB		 166 udelay(1);
167 } while (--retries);
57303488 168
f59dcab1 169 return -ETIMEDOUT;
72246da4
FB		 170}
171
db2be4e9
NB		 172/*
173 * dwc3_frame_length_adjustment - Adjusts frame length if required
174 * @dwc3: Pointer to our controller context structure
db2be4e9 175 */
bcdb3272 176static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
db2be4e9
NB		 177{
178 u32 reg;
179 u32 dft;
180
181 if (dwc->revision < DWC3_REVISION_250A)
182 return;
183
bcdb3272 184 if (dwc->fladj == 0)
db2be4e9
NB		 185 return;
186
187 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
188 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
bcdb3272 189 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
db2be4e9
NB		 190 "request value same as default, ignoring\n")) {
191 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
bcdb3272 192 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
db2be4e9
NB		 193 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
194 }
195}
196
72246da4
FB		 197/**
198 * dwc3_free_one_event_buffer - Frees one event buffer
199 * @dwc: Pointer to our controller context structure
200 * @evt: Pointer to event buffer to be freed
201 */
202static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
203 struct dwc3_event_buffer *evt)
204{
d64ff406 205 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
72246da4
FB		 206}
207
208/**
1d046793 209 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
72246da4
FB		 210 * @dwc: Pointer to our controller context structure
211 * @length: size of the event buffer
212 *
1d046793 213 * Returns a pointer to the allocated event buffer structure on success
72246da4
FB		 214 * otherwise ERR_PTR(errno).
215 */
67d0b500
FB		 216static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
217 unsigned length)
72246da4
FB		 218{
219 struct dwc3_event_buffer *evt;
220
380f0d28 221 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
72246da4
FB		 222 if (!evt)
223 return ERR_PTR(-ENOMEM);
224
225 evt->dwc = dwc;
226 evt->length = length;
d9fa4c63
JY		 227 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
228 if (!evt->cache)
229 return ERR_PTR(-ENOMEM);
230
d64ff406 231 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
72246da4 232 &evt->dma, GFP_KERNEL);
e32672f0 233 if (!evt->buf)
72246da4 234 return ERR_PTR(-ENOMEM);
72246da4
FB		 235
236 return evt;
237}
238
239/**
240 * dwc3_free_event_buffers - frees all allocated event buffers
241 * @dwc: Pointer to our controller context structure
242 */
243static void dwc3_free_event_buffers(struct dwc3 *dwc)
244{
245 struct dwc3_event_buffer *evt;
72246da4 246
696c8b12 247 evt = dwc->ev_buf;
660e9bde
FB		 248 if (evt)
249 dwc3_free_one_event_buffer(dwc, evt);
72246da4
FB		 250}
251
252/**
253 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
1d046793 254 * @dwc: pointer to our controller context structure
72246da4
FB		 255 * @length: size of event buffer
256 *
1d046793 257 * Returns 0 on success otherwise negative errno. In the error case, dwc
72246da4
FB		 258 * may contain some buffers allocated but not all which were requested.
259 */
41ac7b3a 260static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
72246da4 261{
660e9bde 262 struct dwc3_event_buffer *evt;
72246da4 263
660e9bde
FB		 264 evt = dwc3_alloc_one_event_buffer(dwc, length);
265 if (IS_ERR(evt)) {
266 dev_err(dwc->dev, "can't allocate event buffer\n");
267 return PTR_ERR(evt);
72246da4 268 }
696c8b12 269 dwc->ev_buf = evt;
72246da4
FB		 270
271 return 0;
272}
273
274/**
275 * dwc3_event_buffers_setup - setup our allocated event buffers
1d046793 276 * @dwc: pointer to our controller context structure
72246da4
FB		 277 *
278 * Returns 0 on success otherwise negative errno.
279 */
7acd85e0 280static int dwc3_event_buffers_setup(struct dwc3 *dwc)
72246da4
FB		 281{
282 struct dwc3_event_buffer *evt;
72246da4 283
696c8b12 284 evt = dwc->ev_buf;
660e9bde 285 evt->lpos = 0;
660e9bde
FB		 286 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
287 lower_32_bits(evt->dma));
288 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
289 upper_32_bits(evt->dma));
290 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
291 DWC3_GEVNTSIZ_SIZE(evt->length));
292 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 293
294 return 0;
295}
296
297static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
298{
299 struct dwc3_event_buffer *evt;
72246da4 300
696c8b12 301 evt = dwc->ev_buf;
7acd85e0 302
660e9bde 303 evt->lpos = 0;
7acd85e0 304
660e9bde
FB		 305 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
306 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
307 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
308 | DWC3_GEVNTSIZ_SIZE(0));
309 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 310}
311
0ffcaf37
FB		 312static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
313{
314 if (!dwc->has_hibernation)
315 return 0;
316
317 if (!dwc->nr_scratch)
318 return 0;
319
320 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
321 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
322 if (!dwc->scratchbuf)
323 return -ENOMEM;
324
325 return 0;
326}
327
328static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
329{
330 dma_addr_t scratch_addr;
331 u32 param;
332 int ret;
333
334 if (!dwc->has_hibernation)
335 return 0;
336
337 if (!dwc->nr_scratch)
338 return 0;
339
340 /* should never fall here */
341 if (!WARN_ON(dwc->scratchbuf))
342 return 0;
343
d64ff406 344 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
0ffcaf37
FB		 345 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
346 DMA_BIDIRECTIONAL);
d64ff406
AB		 347 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
348 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
0ffcaf37
FB		 349 ret = -EFAULT;
350 goto err0;
351 }
352
353 dwc->scratch_addr = scratch_addr;
354
355 param = lower_32_bits(scratch_addr);
356
357 ret = dwc3_send_gadget_generic_command(dwc,
358 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
359 if (ret < 0)
360 goto err1;
361
362 param = upper_32_bits(scratch_addr);
363
364 ret = dwc3_send_gadget_generic_command(dwc,
365 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
366 if (ret < 0)
367 goto err1;
368
369 return 0;
370
371err1:
d64ff406 372 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
0ffcaf37
FB		 373 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
374
375err0:
376 return ret;
377}
378
379static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
380{
381 if (!dwc->has_hibernation)
382 return;
383
384 if (!dwc->nr_scratch)
385 return;
386
387 /* should never fall here */
388 if (!WARN_ON(dwc->scratchbuf))
389 return;
390
d64ff406 391 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
0ffcaf37
FB		 392 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
393 kfree(dwc->scratchbuf);
394}
395
789451f6
FB		 396static void dwc3_core_num_eps(struct dwc3 *dwc)
397{
398 struct dwc3_hwparams *parms = &dwc->hwparams;
399
400 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
401 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
789451f6
FB		 402}
403
41ac7b3a 404static void dwc3_cache_hwparams(struct dwc3 *dwc)
26ceca97
FB		 405{
406 struct dwc3_hwparams *parms = &dwc->hwparams;
407
408 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
409 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
410 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
411 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
412 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
413 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
414 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
415 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
416 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
417}
418
b5a65c40
HR		 419/**
420 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
421 * @dwc: Pointer to our controller context structure
88bc9d19
HK		 422 *
423 * Returns 0 on success. The USB PHY interfaces are configured but not
424 * initialized. The PHY interfaces and the PHYs get initialized together with
425 * the core in dwc3_core_init.
b5a65c40 426 */
88bc9d19 427static int dwc3_phy_setup(struct dwc3 *dwc)
b5a65c40
HR		 428{
429 u32 reg;
88bc9d19 430 int ret;
b5a65c40
HR		 431
432 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
433
1966b865
FB		 434 /*
435 * Make sure UX_EXIT_PX is cleared as that causes issues with some
436 * PHYs. Also, this bit is not supposed to be used in normal operation.
437 */
438 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
439
2164a476
HR		 440 /*
441 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
442 * to '0' during coreConsultant configuration. So default value
443 * will be '0' when the core is reset. Application needs to set it
444 * to '1' after the core initialization is completed.
445 */
446 if (dwc->revision > DWC3_REVISION_194A)
447 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
448
b5a65c40
HR		 449 if (dwc->u2ss_inp3_quirk)
450 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
451
e58dd357
RB		 452 if (dwc->dis_rxdet_inp3_quirk)
453 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
454
df31f5b3
HR		 455 if (dwc->req_p1p2p3_quirk)
456 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
457
a2a1d0f5
HR		 458 if (dwc->del_p1p2p3_quirk)
459 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
460
41c06ffd
HR		 461 if (dwc->del_phy_power_chg_quirk)
462 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
463
fb67afca
HR		 464 if (dwc->lfps_filter_quirk)
465 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
466
14f4ac53
HR		 467 if (dwc->rx_detect_poll_quirk)
468 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
469
6b6a0c9a
HR		 470 if (dwc->tx_de_emphasis_quirk)
471 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
472
cd72f890 473 if (dwc->dis_u3_susphy_quirk)
59acfa20
HR		 474 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
475
00fe081d
WW		 476 if (dwc->dis_del_phy_power_chg_quirk)
477 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
478
b5a65c40
HR		 479 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
480
2164a476
HR		 481 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
482
3e10a2ce
HK		 483 /* Select the HS PHY interface */
484 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
485 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
43cacb03
FB		 486 if (dwc->hsphy_interface &&
487 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
3e10a2ce 488 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 489 break;
43cacb03
FB		 490 } else if (dwc->hsphy_interface &&
491 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
3e10a2ce 492 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 493 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
3e10a2ce 494 } else {
88bc9d19
HK		 495 /* Relying on default value. */
496 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
497 break;
3e10a2ce
HK		 498 }
499 /* FALLTHROUGH */
88bc9d19 500 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
88bc9d19
HK		 501 ret = dwc3_ulpi_init(dwc);
502 if (ret)
503 return ret;
504 /* FALLTHROUGH */
3e10a2ce
HK		 505 default:
506 break;
507 }
508
32f2ed86
WW		 509 switch (dwc->hsphy_mode) {
510 case USBPHY_INTERFACE_MODE_UTMI:
511 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
512 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
513 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
514 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
515 break;
516 case USBPHY_INTERFACE_MODE_UTMIW:
517 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
518 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
519 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
520 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
521 break;
522 default:
523 break;
524 }
525
2164a476
HR		 526 /*
527 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
528 * '0' during coreConsultant configuration. So default value will
529 * be '0' when the core is reset. Application needs to set it to
530 * '1' after the core initialization is completed.
531 */
532 if (dwc->revision > DWC3_REVISION_194A)
533 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
534
cd72f890 535 if (dwc->dis_u2_susphy_quirk)
0effe0a3
HR		 536 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
537
ec791d14
JY		 538 if (dwc->dis_enblslpm_quirk)
539 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
540
16199f33
WW		 541 if (dwc->dis_u2_freeclk_exists_quirk)
542 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
543
2164a476 544 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
88bc9d19
HK		 545
546 return 0;
b5a65c40
HR		 547}
548
c499ff71
FB		 549static void dwc3_core_exit(struct dwc3 *dwc)
550{
551 dwc3_event_buffers_cleanup(dwc);
552
553 usb_phy_shutdown(dwc->usb2_phy);
554 usb_phy_shutdown(dwc->usb3_phy);
555 phy_exit(dwc->usb2_generic_phy);
556 phy_exit(dwc->usb3_generic_phy);
557
558 usb_phy_set_suspend(dwc->usb2_phy, 1);
559 usb_phy_set_suspend(dwc->usb3_phy, 1);
560 phy_power_off(dwc->usb2_generic_phy);
561 phy_power_off(dwc->usb3_generic_phy);
562}
563
0759956f 564static bool dwc3_core_is_valid(struct dwc3 *dwc)
72246da4 565{
0759956f 566 u32 reg;
72246da4 567
7650bd74 568 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
0759956f 569
7650bd74 570 /* This should read as U3 followed by revision number */
690fb371
JY		 571 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
572 /* Detected DWC_usb3 IP */
573 dwc->revision = reg;
574 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
575 /* Detected DWC_usb31 IP */
576 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
577 dwc->revision |= DWC3_REVISION_IS_DWC31;
578 } else {
0759956f 579 return false;
7650bd74 580 }
7650bd74 581
0759956f
FB		 582 return true;
583}
58a0f23f 584
941f918e 585static void dwc3_core_setup_global_control(struct dwc3 *dwc)
0759956f 586{
941f918e
FB		 587 u32 hwparams4 = dwc->hwparams.hwparams4;
588 u32 reg;
c499ff71 589
4878a028 590 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
3e87c42a 591 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
4878a028 592
164d7731 593 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
4878a028 594 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
32a4a135
FB		 595 /**
596 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
597 * issue which would cause xHCI compliance tests to fail.
598 *
599 * Because of that we cannot enable clock gating on such
600 * configurations.
601 *
602 * Refers to:
603 *
604 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
605 * SOF/ITP Mode Used
606 */
607 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
608 dwc->dr_mode == USB_DR_MODE_OTG) &&
609 (dwc->revision >= DWC3_REVISION_210A &&
610 dwc->revision <= DWC3_REVISION_250A))
611 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
612 else
613 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
4878a028 614 break;
0ffcaf37
FB		 615 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
616 /* enable hibernation here */
617 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
2eac3992
HR		 618
619 /*
620 * REVISIT Enabling this bit so that host-mode hibernation
621 * will work. Device-mode hibernation is not yet implemented.
622 */
623 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
0ffcaf37 624 break;
4878a028 625 default:
5eb30ced
FB		 626 /* nothing */
627 break;
4878a028
SAS		 628 }
629
946bd579
HR		 630 /* check if current dwc3 is on simulation board */
631 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
5eb30ced 632 dev_info(dwc->dev, "Running with FPGA optmizations\n");
946bd579
HR		 633 dwc->is_fpga = true;
634 }
635
3b81221a
HR		 636 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
637 "disable_scramble cannot be used on non-FPGA builds\n");
638
639 if (dwc->disable_scramble_quirk && dwc->is_fpga)
640 reg |= DWC3_GCTL_DISSCRAMBLE;
641 else
642 reg &= ~DWC3_GCTL_DISSCRAMBLE;
643
9a5b2f31
HR		 644 if (dwc->u2exit_lfps_quirk)
645 reg |= DWC3_GCTL_U2EXIT_LFPS;
646
4878a028
SAS		 647 /*
648 * WORKAROUND: DWC3 revisions <1.90a have a bug
1d046793 649 * where the device can fail to connect at SuperSpeed
4878a028 650 * and falls back to high-speed mode which causes
1d046793 651 * the device to enter a Connect/Disconnect loop
4878a028
SAS		 652 */
653 if (dwc->revision < DWC3_REVISION_190A)
654 reg |= DWC3_GCTL_U2RSTECN;
655
656 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
941f918e
FB		 657}
658
659/**
660 * dwc3_core_init - Low-level initialization of DWC3 Core
661 * @dwc: Pointer to our controller context structure
662 *
663 * Returns 0 on success otherwise negative errno.
664 */
665static int dwc3_core_init(struct dwc3 *dwc)
666{
667 u32 reg;
668 int ret;
669
670 if (!dwc3_core_is_valid(dwc)) {
671 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
672 ret = -ENODEV;
673 goto err0;
674 }
675
676 /*
677 * Write Linux Version Code to our GUID register so it's easy to figure
678 * out which kernel version a bug was found.
679 */
680 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
681
682 /* Handle USB2.0-only core configuration */
683 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
684 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
685 if (dwc->maximum_speed == USB_SPEED_SUPER)
686 dwc->maximum_speed = USB_SPEED_HIGH;
687 }
688
941f918e
FB		 689 ret = dwc3_core_soft_reset(dwc);
690 if (ret)
691 goto err0;
4878a028 692
941f918e
FB		 693 ret = dwc3_phy_setup(dwc);
694 if (ret)
695 goto err0;
4878a028 696
941f918e 697 dwc3_core_setup_global_control(dwc);
c499ff71 698 dwc3_core_num_eps(dwc);
0ffcaf37
FB		 699
700 ret = dwc3_setup_scratch_buffers(dwc);
701 if (ret)
c499ff71
FB		 702 goto err1;
703
704 /* Adjust Frame Length */
705 dwc3_frame_length_adjustment(dwc);
706
707 usb_phy_set_suspend(dwc->usb2_phy, 0);
708 usb_phy_set_suspend(dwc->usb3_phy, 0);
709 ret = phy_power_on(dwc->usb2_generic_phy);
710 if (ret < 0)
0ffcaf37
FB		 711 goto err2;
712
c499ff71
FB		 713 ret = phy_power_on(dwc->usb3_generic_phy);
714 if (ret < 0)
715 goto err3;
716
717 ret = dwc3_event_buffers_setup(dwc);
718 if (ret) {
719 dev_err(dwc->dev, "failed to setup event buffers\n");
720 goto err4;
721 }
722
00af6233
BW		 723 switch (dwc->dr_mode) {
724 case USB_DR_MODE_PERIPHERAL:
725 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
726 break;
727 case USB_DR_MODE_HOST:
728 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
729 break;
730 case USB_DR_MODE_OTG:
731 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
732 break;
733 default:
734 dev_warn(dwc->dev, "Unsupported mode %d\n", dwc->dr_mode);
735 break;
736 }
737
06281d46
JY		 738 /*
739 * ENDXFER polling is available on version 3.10a and later of
740 * the DWC_usb3 controller. It is NOT available in the
741 * DWC_usb31 controller.
742 */
743 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
744 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
745 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
746 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
747 }
748
0bb39ca1
JY		 749 /*
750 * Enable hardware control of sending remote wakeup in HS when
751 * the device is in the L1 state.
752 */
753 if (dwc->revision >= DWC3_REVISION_290A) {
754 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
755 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
756 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
757 }
758
72246da4
FB		 759 return 0;
760
c499ff71 761err4:
9b9d7cdd 762 phy_power_off(dwc->usb3_generic_phy);
c499ff71
FB		 763
764err3:
9b9d7cdd 765 phy_power_off(dwc->usb2_generic_phy);
c499ff71 766
0ffcaf37 767err2:
c499ff71
FB		 768 usb_phy_set_suspend(dwc->usb2_phy, 1);
769 usb_phy_set_suspend(dwc->usb3_phy, 1);
0ffcaf37
FB		 770
771err1:
772 usb_phy_shutdown(dwc->usb2_phy);
773 usb_phy_shutdown(dwc->usb3_phy);
57303488
KVA		 774 phy_exit(dwc->usb2_generic_phy);
775 phy_exit(dwc->usb3_generic_phy);
0ffcaf37 776
72246da4
FB		 777err0:
778 return ret;
779}
780
3c9f94ac 781static int dwc3_core_get_phy(struct dwc3 *dwc)
72246da4 782{
3c9f94ac 783 struct device *dev = dwc->dev;
941ea361 784 struct device_node *node = dev->of_node;
3c9f94ac 785 int ret;
72246da4 786
5088b6f5
KVA		 787 if (node) {
788 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
789 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
bb674907
FB		 790 } else {
791 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
792 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
5088b6f5
KVA		 793 }
794
d105e7f8
FB		 795 if (IS_ERR(dwc->usb2_phy)) {
796 ret = PTR_ERR(dwc->usb2_phy);
122f06e6
KVA		 797 if (ret == -ENXIO || ret == -ENODEV) {
798 dwc->usb2_phy = NULL;
799 } else if (ret == -EPROBE_DEFER) {
d105e7f8 800 return ret;
122f06e6
KVA		 801 } else {
802 dev_err(dev, "no usb2 phy configured\n");
803 return ret;
804 }
51e1e7bc
FB		 805 }
806
d105e7f8 807 if (IS_ERR(dwc->usb3_phy)) {
315955d7 808 ret = PTR_ERR(dwc->usb3_phy);
122f06e6
KVA		 809 if (ret == -ENXIO || ret == -ENODEV) {
810 dwc->usb3_phy = NULL;
811 } else if (ret == -EPROBE_DEFER) {
d105e7f8 812 return ret;
122f06e6
KVA		 813 } else {
814 dev_err(dev, "no usb3 phy configured\n");
815 return ret;
816 }
51e1e7bc
FB		 817 }
818
57303488
KVA		 819 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
820 if (IS_ERR(dwc->usb2_generic_phy)) {
821 ret = PTR_ERR(dwc->usb2_generic_phy);
822 if (ret == -ENOSYS || ret == -ENODEV) {
823 dwc->usb2_generic_phy = NULL;
824 } else if (ret == -EPROBE_DEFER) {
825 return ret;
826 } else {
827 dev_err(dev, "no usb2 phy configured\n");
828 return ret;
829 }
830 }
831
832 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
833 if (IS_ERR(dwc->usb3_generic_phy)) {
834 ret = PTR_ERR(dwc->usb3_generic_phy);
835 if (ret == -ENOSYS || ret == -ENODEV) {
836 dwc->usb3_generic_phy = NULL;
837 } else if (ret == -EPROBE_DEFER) {
838 return ret;
839 } else {
840 dev_err(dev, "no usb3 phy configured\n");
841 return ret;
842 }
843 }
844
3c9f94ac
FB		 845 return 0;
846}
847
5f94adfe
FB		 848static int dwc3_core_init_mode(struct dwc3 *dwc)
849{
850 struct device *dev = dwc->dev;
851 int ret;
852
853 switch (dwc->dr_mode) {
854 case USB_DR_MODE_PERIPHERAL:
5f94adfe
FB		 855 ret = dwc3_gadget_init(dwc);
856 if (ret) {
9522def4
RQ		 857 if (ret != -EPROBE_DEFER)
858 dev_err(dev, "failed to initialize gadget\n");
5f94adfe
FB		 859 return ret;
860 }
861 break;
862 case USB_DR_MODE_HOST:
5f94adfe
FB		 863 ret = dwc3_host_init(dwc);
864 if (ret) {
9522def4
RQ		 865 if (ret != -EPROBE_DEFER)
866 dev_err(dev, "failed to initialize host\n");
5f94adfe
FB		 867 return ret;
868 }
869 break;
870 case USB_DR_MODE_OTG:
5f94adfe
FB		 871 ret = dwc3_host_init(dwc);
872 if (ret) {
9522def4
RQ		 873 if (ret != -EPROBE_DEFER)
874 dev_err(dev, "failed to initialize host\n");
5f94adfe
FB		 875 return ret;
876 }
877
878 ret = dwc3_gadget_init(dwc);
879 if (ret) {
9522def4
RQ		 880 if (ret != -EPROBE_DEFER)
881 dev_err(dev, "failed to initialize gadget\n");
5f94adfe
FB		 882 return ret;
883 }
884 break;
885 default:
886 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
887 return -EINVAL;
888 }
889
890 return 0;
891}
892
893static void dwc3_core_exit_mode(struct dwc3 *dwc)
894{
895 switch (dwc->dr_mode) {
896 case USB_DR_MODE_PERIPHERAL:
897 dwc3_gadget_exit(dwc);
898 break;
899 case USB_DR_MODE_HOST:
900 dwc3_host_exit(dwc);
901 break;
902 case USB_DR_MODE_OTG:
903 dwc3_host_exit(dwc);
904 dwc3_gadget_exit(dwc);
905 break;
906 default:
907 /* do nothing */
908 break;
909 }
910}
911
c5ac6116 912static void dwc3_get_properties(struct dwc3 *dwc)
3c9f94ac 913{
c5ac6116 914 struct device *dev = dwc->dev;
80caf7d2 915 u8 lpm_nyet_threshold;
6b6a0c9a 916 u8 tx_de_emphasis;
460d098c 917 u8 hird_threshold;
3c9f94ac 918
80caf7d2
HR		 919 /* default to highest possible threshold */
920 lpm_nyet_threshold = 0xff;
921
6b6a0c9a
HR		 922 /* default to -3.5dB de-emphasis */
923 tx_de_emphasis = 1;
924
460d098c
HR		 925 /*
926 * default to assert utmi_sleep_n and use maximum allowed HIRD
927 * threshold value of 0b1100
928 */
929 hird_threshold = 12;
930
63863b98 931 dwc->maximum_speed = usb_get_maximum_speed(dev);
06e7114f 932 dwc->dr_mode = usb_get_dr_mode(dev);
32f2ed86 933 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
63863b98 934
d64ff406
AB		 935 dwc->sysdev_is_parent = device_property_read_bool(dev,
936 "linux,sysdev_is_parent");
937 if (dwc->sysdev_is_parent)
938 dwc->sysdev = dwc->dev->parent;
939 else
940 dwc->sysdev = dwc->dev;
941
3d128919 942 dwc->has_lpm_erratum = device_property_read_bool(dev,
80caf7d2 943 "snps,has-lpm-erratum");
3d128919 944 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
80caf7d2 945 &lpm_nyet_threshold);
3d128919 946 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
460d098c 947 "snps,is-utmi-l1-suspend");
3d128919 948 device_property_read_u8(dev, "snps,hird-threshold",
460d098c 949 &hird_threshold);
3d128919 950 dwc->usb3_lpm_capable = device_property_read_bool(dev,
eac68e8f 951 "snps,usb3_lpm_capable");
3c9f94ac 952
3d128919 953 dwc->disable_scramble_quirk = device_property_read_bool(dev,
3b81221a 954 "snps,disable_scramble_quirk");
3d128919 955 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
9a5b2f31 956 "snps,u2exit_lfps_quirk");
3d128919 957 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
b5a65c40 958 "snps,u2ss_inp3_quirk");
3d128919 959 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
df31f5b3 960 "snps,req_p1p2p3_quirk");
3d128919 961 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
a2a1d0f5 962 "snps,del_p1p2p3_quirk");
3d128919 963 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
41c06ffd 964 "snps,del_phy_power_chg_quirk");
3d128919 965 dwc->lfps_filter_quirk = device_property_read_bool(dev,
fb67afca 966 "snps,lfps_filter_quirk");
3d128919 967 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
14f4ac53 968 "snps,rx_detect_poll_quirk");
3d128919 969 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
59acfa20 970 "snps,dis_u3_susphy_quirk");
3d128919 971 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
0effe0a3 972 "snps,dis_u2_susphy_quirk");
ec791d14
JY		 973 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
974 "snps,dis_enblslpm_quirk");
e58dd357
RB		 975 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
976 "snps,dis_rxdet_inp3_quirk");
16199f33
WW		 977 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
978 "snps,dis-u2-freeclk-exists-quirk");
00fe081d
WW		 979 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
980 "snps,dis-del-phy-power-chg-quirk");
6b6a0c9a 981
3d128919 982 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
6b6a0c9a 983 "snps,tx_de_emphasis_quirk");
3d128919 984 device_property_read_u8(dev, "snps,tx_de_emphasis",
6b6a0c9a 985 &tx_de_emphasis);
3d128919
HK		 986 device_property_read_string(dev, "snps,hsphy_interface",
987 &dwc->hsphy_interface);
988 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
bcdb3272 989 &dwc->fladj);
3d128919 990
80caf7d2 991 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
6b6a0c9a 992 dwc->tx_de_emphasis = tx_de_emphasis;
80caf7d2 993
460d098c
HR		 994 dwc->hird_threshold = hird_threshold
995 | (dwc->is_utmi_l1_suspend << 4);
996
cf40b86b
JY		 997 dwc->imod_interval = 0;
998}
999
1000/* check whether the core supports IMOD */
1001bool dwc3_has_imod(struct dwc3 *dwc)
1002{
1003 return ((dwc3_is_usb3(dwc) &&
1004 dwc->revision >= DWC3_REVISION_300A) ||
1005 (dwc3_is_usb31(dwc) &&
1006 dwc->revision >= DWC3_USB31_REVISION_120A));
c5ac6116
FB		 1007}
1008
7ac51a12
JY		 1009static void dwc3_check_params(struct dwc3 *dwc)
1010{
1011 struct device *dev = dwc->dev;
1012
cf40b86b
JY		 1013 /* Check for proper value of imod_interval */
1014 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1015 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1016 dwc->imod_interval = 0;
1017 }
1018
28632b44
JY		 1019 /*
1020 * Workaround for STAR 9000961433 which affects only version
1021 * 3.00a of the DWC_usb3 core. This prevents the controller
1022 * interrupt from being masked while handling events. IMOD
1023 * allows us to work around this issue. Enable it for the
1024 * affected version.
1025 */
1026 if (!dwc->imod_interval &&
1027 (dwc->revision == DWC3_REVISION_300A))
1028 dwc->imod_interval = 1;
1029
7ac51a12
JY		 1030 /* Check the maximum_speed parameter */
1031 switch (dwc->maximum_speed) {
1032 case USB_SPEED_LOW:
1033 case USB_SPEED_FULL:
1034 case USB_SPEED_HIGH:
1035 case USB_SPEED_SUPER:
1036 case USB_SPEED_SUPER_PLUS:
1037 break;
1038 default:
1039 dev_err(dev, "invalid maximum_speed parameter %d\n",
1040 dwc->maximum_speed);
1041 /* fall through */
1042 case USB_SPEED_UNKNOWN:
1043 /* default to superspeed */
1044 dwc->maximum_speed = USB_SPEED_SUPER;
1045
1046 /*
1047 * default to superspeed plus if we are capable.
1048 */
1049 if (dwc3_is_usb31(dwc) &&
1050 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1051 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1052 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1053
1054 break;
1055 }
1056}
1057
c5ac6116
FB		 1058static int dwc3_probe(struct platform_device *pdev)
1059{
1060 struct device *dev = &pdev->dev;
1061 struct resource *res;
1062 struct dwc3 *dwc;
1063
1064 int ret;
1065
1066 void __iomem *regs;
1067
1068 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1069 if (!dwc)
1070 return -ENOMEM;
1071
1072 dwc->dev = dev;
1073
1074 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1075 if (!res) {
1076 dev_err(dev, "missing memory resource\n");
1077 return -ENODEV;
1078 }
1079
1080 dwc->xhci_resources[0].start = res->start;
1081 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1082 DWC3_XHCI_REGS_END;
1083 dwc->xhci_resources[0].flags = res->flags;
1084 dwc->xhci_resources[0].name = res->name;
1085
1086 res->start += DWC3_GLOBALS_REGS_START;
1087
1088 /*
1089 * Request memory region but exclude xHCI regs,
1090 * since it will be requested by the xhci-plat driver.
1091 */
1092 regs = devm_ioremap_resource(dev, res);
1093 if (IS_ERR(regs)) {
1094 ret = PTR_ERR(regs);
1095 goto err0;
1096 }
1097
1098 dwc->regs = regs;
1099 dwc->regs_size = resource_size(res);
1100
1101 dwc3_get_properties(dwc);
1102
6c89cce0 1103 platform_set_drvdata(pdev, dwc);
2917e718 1104 dwc3_cache_hwparams(dwc);
6c89cce0 1105
3c9f94ac
FB		 1106 ret = dwc3_core_get_phy(dwc);
1107 if (ret)
3da1f6ee 1108 goto err0;
3c9f94ac 1109
72246da4 1110 spin_lock_init(&dwc->lock);
72246da4 1111
fc8bb91b
FB		 1112 pm_runtime_set_active(dev);
1113 pm_runtime_use_autosuspend(dev);
1114 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
802ca850 1115 pm_runtime_enable(dev);
32808237
RQ		 1116 ret = pm_runtime_get_sync(dev);
1117 if (ret < 0)
1118 goto err1;
1119
802ca850 1120 pm_runtime_forbid(dev);
72246da4 1121
3921426b
FB		 1122 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1123 if (ret) {
1124 dev_err(dwc->dev, "failed to allocate event buffers\n");
1125 ret = -ENOMEM;
32808237 1126 goto err2;
3921426b
FB		 1127 }
1128
9d6173e1
TN		 1129 ret = dwc3_get_dr_mode(dwc);
1130 if (ret)
1131 goto err3;
32a4a135 1132
c499ff71
FB		 1133 ret = dwc3_alloc_scratch_buffers(dwc);
1134 if (ret)
32808237 1135 goto err3;
c499ff71 1136
72246da4
FB		 1137 ret = dwc3_core_init(dwc);
1138 if (ret) {
802ca850 1139 dev_err(dev, "failed to initialize core\n");
32808237 1140 goto err4;
72246da4
FB		 1141 }
1142
7ac51a12 1143 dwc3_check_params(dwc);
2c7f1bd9 1144
5f94adfe
FB		 1145 ret = dwc3_core_init_mode(dwc);
1146 if (ret)
32808237 1147 goto err5;
72246da4 1148
4e9f3118 1149 dwc3_debugfs_init(dwc);
fc8bb91b 1150 pm_runtime_put(dev);
72246da4
FB		 1151
1152 return 0;
1153
32808237 1154err5:
c499ff71 1155 dwc3_event_buffers_cleanup(dwc);
57303488 1156
32808237 1157err4:
c499ff71 1158 dwc3_free_scratch_buffers(dwc);
72246da4 1159
32808237 1160err3:
3921426b 1161 dwc3_free_event_buffers(dwc);
88bc9d19 1162 dwc3_ulpi_exit(dwc);
3921426b 1163
32808237
RQ		 1164err2:
1165 pm_runtime_allow(&pdev->dev);
1166
1167err1:
1168 pm_runtime_put_sync(&pdev->dev);
1169 pm_runtime_disable(&pdev->dev);
1170
3da1f6ee
FB		 1171err0:
1172 /*
1173 * restore res->start back to its original value so that, in case the
1174 * probe is deferred, we don't end up getting error in request the
1175 * memory region the next time probe is called.
1176 */
1177 res->start -= DWC3_GLOBALS_REGS_START;
1178
72246da4
FB		 1179 return ret;
1180}
1181
fb4e98ab 1182static int dwc3_remove(struct platform_device *pdev)
72246da4 1183{
72246da4 1184 struct dwc3 *dwc = platform_get_drvdata(pdev);
3da1f6ee
FB		 1185 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1186
fc8bb91b 1187 pm_runtime_get_sync(&pdev->dev);
3da1f6ee
FB		 1188 /*
1189 * restore res->start back to its original value so that, in case the
1190 * probe is deferred, we don't end up getting error in request the
1191 * memory region the next time probe is called.
1192 */
1193 res->start -= DWC3_GLOBALS_REGS_START;
72246da4 1194
dc99f16f
FB		 1195 dwc3_debugfs_exit(dwc);
1196 dwc3_core_exit_mode(dwc);
8ba007a9 1197
72246da4 1198 dwc3_core_exit(dwc);
88bc9d19 1199 dwc3_ulpi_exit(dwc);
72246da4 1200
16b972a5 1201 pm_runtime_put_sync(&pdev->dev);
fc8bb91b 1202 pm_runtime_allow(&pdev->dev);
72246da4
FB		 1203 pm_runtime_disable(&pdev->dev);
1204
fc8bb91b
FB		 1205 dwc3_free_event_buffers(dwc);
1206 dwc3_free_scratch_buffers(dwc);
1207
72246da4
FB		 1208 return 0;
1209}
1210
fc8bb91b
FB		 1211#ifdef CONFIG_PM
1212static int dwc3_suspend_common(struct dwc3 *dwc)
7415f17c 1213{
fc8bb91b 1214 unsigned long flags;
7415f17c 1215
a45c82b8
RK		 1216 switch (dwc->dr_mode) {
1217 case USB_DR_MODE_PERIPHERAL:
1218 case USB_DR_MODE_OTG:
fc8bb91b 1219 spin_lock_irqsave(&dwc->lock, flags);
7415f17c 1220 dwc3_gadget_suspend(dwc);
fc8bb91b 1221 spin_unlock_irqrestore(&dwc->lock, flags);
51f5d49a 1222 break;
a45c82b8 1223 case USB_DR_MODE_HOST:
7415f17c 1224 default:
51f5d49a 1225 /* do nothing */
7415f17c
FB		 1226 break;
1227 }
1228
51f5d49a 1229 dwc3_core_exit(dwc);
5c4ad318 1230
7415f17c
FB		 1231 return 0;
1232}
1233
fc8bb91b 1234static int dwc3_resume_common(struct dwc3 *dwc)
7415f17c 1235{
fc8bb91b 1236 unsigned long flags;
57303488 1237 int ret;
7415f17c 1238
51f5d49a
FB		 1239 ret = dwc3_core_init(dwc);
1240 if (ret)
5c4ad318
FB		 1241 return ret;
1242
a45c82b8
RK		 1243 switch (dwc->dr_mode) {
1244 case USB_DR_MODE_PERIPHERAL:
1245 case USB_DR_MODE_OTG:
fc8bb91b 1246 spin_lock_irqsave(&dwc->lock, flags);
7415f17c 1247 dwc3_gadget_resume(dwc);
fc8bb91b 1248 spin_unlock_irqrestore(&dwc->lock, flags);
7415f17c 1249 /* FALLTHROUGH */
a45c82b8 1250 case USB_DR_MODE_HOST:
7415f17c
FB		 1251 default:
1252 /* do nothing */
1253 break;
1254 }
1255
fc8bb91b
FB		 1256 return 0;
1257}
1258
1259static int dwc3_runtime_checks(struct dwc3 *dwc)
1260{
1261 switch (dwc->dr_mode) {
1262 case USB_DR_MODE_PERIPHERAL:
1263 case USB_DR_MODE_OTG:
1264 if (dwc->connected)
1265 return -EBUSY;
1266 break;
1267 case USB_DR_MODE_HOST:
1268 default:
1269 /* do nothing */
1270 break;
1271 }
1272
1273 return 0;
1274}
1275
1276static int dwc3_runtime_suspend(struct device *dev)
1277{
1278 struct dwc3 *dwc = dev_get_drvdata(dev);
1279 int ret;
1280
1281 if (dwc3_runtime_checks(dwc))
1282 return -EBUSY;
1283
1284 ret = dwc3_suspend_common(dwc);
1285 if (ret)
1286 return ret;
1287
1288 device_init_wakeup(dev, true);
1289
1290 return 0;
1291}
1292
1293static int dwc3_runtime_resume(struct device *dev)
1294{
1295 struct dwc3 *dwc = dev_get_drvdata(dev);
1296 int ret;
1297
1298 device_init_wakeup(dev, false);
1299
1300 ret = dwc3_resume_common(dwc);
1301 if (ret)
1302 return ret;
1303
1304 switch (dwc->dr_mode) {
1305 case USB_DR_MODE_PERIPHERAL:
1306 case USB_DR_MODE_OTG:
1307 dwc3_gadget_process_pending_events(dwc);
1308 break;
1309 case USB_DR_MODE_HOST:
1310 default:
1311 /* do nothing */
1312 break;
1313 }
1314
1315 pm_runtime_mark_last_busy(dev);
b74c2d87 1316 pm_runtime_put(dev);
fc8bb91b
FB		 1317
1318 return 0;
1319}
1320
1321static int dwc3_runtime_idle(struct device *dev)
1322{
1323 struct dwc3 *dwc = dev_get_drvdata(dev);
1324
1325 switch (dwc->dr_mode) {
1326 case USB_DR_MODE_PERIPHERAL:
1327 case USB_DR_MODE_OTG:
1328 if (dwc3_runtime_checks(dwc))
1329 return -EBUSY;
1330 break;
1331 case USB_DR_MODE_HOST:
1332 default:
1333 /* do nothing */
1334 break;
1335 }
1336
1337 pm_runtime_mark_last_busy(dev);
1338 pm_runtime_autosuspend(dev);
1339
1340 return 0;
1341}
1342#endif /* CONFIG_PM */
1343
1344#ifdef CONFIG_PM_SLEEP
1345static int dwc3_suspend(struct device *dev)
1346{
1347 struct dwc3 *dwc = dev_get_drvdata(dev);
1348 int ret;
1349
1350 ret = dwc3_suspend_common(dwc);
1351 if (ret)
1352 return ret;
1353
1354 pinctrl_pm_select_sleep_state(dev);
1355
1356 return 0;
1357}
1358
1359static int dwc3_resume(struct device *dev)
1360{
1361 struct dwc3 *dwc = dev_get_drvdata(dev);
1362 int ret;
1363
1364 pinctrl_pm_select_default_state(dev);
1365
1366 ret = dwc3_resume_common(dwc);
1367 if (ret)
1368 return ret;
1369
7415f17c
FB		 1370 pm_runtime_disable(dev);
1371 pm_runtime_set_active(dev);
1372 pm_runtime_enable(dev);
1373
1374 return 0;
1375}
7f370ed0 1376#endif /* CONFIG_PM_SLEEP */
7415f17c
FB		 1377
1378static const struct dev_pm_ops dwc3_dev_pm_ops = {
7415f17c 1379 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
fc8bb91b
FB		 1380 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1381 dwc3_runtime_idle)
7415f17c
FB		 1382};
1383
5088b6f5
KVA		 1384#ifdef CONFIG_OF
1385static const struct of_device_id of_dwc3_match[] = {
22a5aa17
FB		 1386 {
1387 .compatible = "snps,dwc3"
1388 },
5088b6f5
KVA		 1389 {
1390 .compatible = "synopsys,dwc3"
1391 },
1392 { },
1393};
1394MODULE_DEVICE_TABLE(of, of_dwc3_match);
1395#endif
1396
404905a6
HK		 1397#ifdef CONFIG_ACPI
1398
1399#define ACPI_ID_INTEL_BSW "808622B7"
1400
1401static const struct acpi_device_id dwc3_acpi_match[] = {
1402 { ACPI_ID_INTEL_BSW, 0 },
1403 { },
1404};
1405MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1406#endif
1407
72246da4
FB		 1408static struct platform_driver dwc3_driver = {
1409 .probe = dwc3_probe,
7690417d 1410 .remove = dwc3_remove,
72246da4
FB		 1411 .driver = {
1412 .name = "dwc3",
5088b6f5 1413 .of_match_table = of_match_ptr(of_dwc3_match),
404905a6 1414 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
7f370ed0 1415 .pm = &dwc3_dev_pm_ops,
72246da4 1416 },
72246da4
FB		 1417};
1418
b1116dcc
TK		 1419module_platform_driver(dwc3_driver);
1420
7ae4fc4d 1421MODULE_ALIAS("platform:dwc3");
72246da4 1422MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
5945f789 1423MODULE_LICENSE("GPL v2");
72246da4 1424MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux 6.x block layer and io_uring tree(s)