Commit | Line | Data |
---|---|---|
72246da4 FB |
1 | /** |
2 | * core.c - DesignWare USB3 DRD Controller Core file | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 | 17 | * |
5945f789 FB |
18 | * You should have received a copy of the GNU General Public License |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
72246da4 FB |
20 | */ |
21 | ||
fa0ea13e | 22 | #include <linux/version.h> |
a72e658b | 23 | #include <linux/module.h> |
72246da4 FB |
24 | #include <linux/kernel.h> |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/pm_runtime.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/list.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
457e84b6 | 35 | #include <linux/of.h> |
404905a6 | 36 | #include <linux/acpi.h> |
72246da4 FB |
37 | |
38 | #include <linux/usb/ch9.h> | |
39 | #include <linux/usb/gadget.h> | |
f7e846f0 | 40 | #include <linux/usb/of.h> |
a45c82b8 | 41 | #include <linux/usb/otg.h> |
72246da4 | 42 | |
6462cbd5 | 43 | #include "platform_data.h" |
72246da4 FB |
44 | #include "core.h" |
45 | #include "gadget.h" | |
46 | #include "io.h" | |
47 | ||
48 | #include "debug.h" | |
49 | ||
8300dd23 FB |
50 | /* -------------------------------------------------------------------------- */ |
51 | ||
3140e8cb SAS |
52 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode) |
53 | { | |
54 | u32 reg; | |
55 | ||
56 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
57 | reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); | |
58 | reg |= DWC3_GCTL_PRTCAPDIR(mode); | |
59 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
60 | } | |
8300dd23 | 61 | |
72246da4 FB |
62 | /** |
63 | * dwc3_core_soft_reset - Issues core soft reset and PHY reset | |
64 | * @dwc: pointer to our context structure | |
65 | */ | |
57303488 | 66 | static int dwc3_core_soft_reset(struct dwc3 *dwc) |
72246da4 FB |
67 | { |
68 | u32 reg; | |
57303488 | 69 | int ret; |
72246da4 FB |
70 | |
71 | /* Before Resetting PHY, put Core in Reset */ | |
72 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
73 | reg |= DWC3_GCTL_CORESOFTRESET; | |
74 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
75 | ||
76 | /* Assert USB3 PHY reset */ | |
77 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
78 | reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
79 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
80 | ||
81 | /* Assert USB2 PHY reset */ | |
82 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
83 | reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
84 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
85 | ||
51e1e7bc FB |
86 | usb_phy_init(dwc->usb2_phy); |
87 | usb_phy_init(dwc->usb3_phy); | |
57303488 KVA |
88 | ret = phy_init(dwc->usb2_generic_phy); |
89 | if (ret < 0) | |
90 | return ret; | |
91 | ||
92 | ret = phy_init(dwc->usb3_generic_phy); | |
93 | if (ret < 0) { | |
94 | phy_exit(dwc->usb2_generic_phy); | |
95 | return ret; | |
96 | } | |
72246da4 FB |
97 | mdelay(100); |
98 | ||
99 | /* Clear USB3 PHY reset */ | |
100 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
101 | reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
102 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
103 | ||
104 | /* Clear USB2 PHY reset */ | |
105 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
106 | reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
107 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
108 | ||
45627ac6 PA |
109 | mdelay(100); |
110 | ||
72246da4 FB |
111 | /* After PHYs are stable we can take Core out of reset state */ |
112 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
113 | reg &= ~DWC3_GCTL_CORESOFTRESET; | |
114 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
57303488 KVA |
115 | |
116 | return 0; | |
72246da4 FB |
117 | } |
118 | ||
119 | /** | |
120 | * dwc3_free_one_event_buffer - Frees one event buffer | |
121 | * @dwc: Pointer to our controller context structure | |
122 | * @evt: Pointer to event buffer to be freed | |
123 | */ | |
124 | static void dwc3_free_one_event_buffer(struct dwc3 *dwc, | |
125 | struct dwc3_event_buffer *evt) | |
126 | { | |
127 | dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma); | |
72246da4 FB |
128 | } |
129 | ||
130 | /** | |
1d046793 | 131 | * dwc3_alloc_one_event_buffer - Allocates one event buffer structure |
72246da4 FB |
132 | * @dwc: Pointer to our controller context structure |
133 | * @length: size of the event buffer | |
134 | * | |
1d046793 | 135 | * Returns a pointer to the allocated event buffer structure on success |
72246da4 FB |
136 | * otherwise ERR_PTR(errno). |
137 | */ | |
67d0b500 FB |
138 | static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, |
139 | unsigned length) | |
72246da4 FB |
140 | { |
141 | struct dwc3_event_buffer *evt; | |
142 | ||
380f0d28 | 143 | evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); |
72246da4 FB |
144 | if (!evt) |
145 | return ERR_PTR(-ENOMEM); | |
146 | ||
147 | evt->dwc = dwc; | |
148 | evt->length = length; | |
149 | evt->buf = dma_alloc_coherent(dwc->dev, length, | |
150 | &evt->dma, GFP_KERNEL); | |
e32672f0 | 151 | if (!evt->buf) |
72246da4 | 152 | return ERR_PTR(-ENOMEM); |
72246da4 FB |
153 | |
154 | return evt; | |
155 | } | |
156 | ||
157 | /** | |
158 | * dwc3_free_event_buffers - frees all allocated event buffers | |
159 | * @dwc: Pointer to our controller context structure | |
160 | */ | |
161 | static void dwc3_free_event_buffers(struct dwc3 *dwc) | |
162 | { | |
163 | struct dwc3_event_buffer *evt; | |
164 | int i; | |
165 | ||
9f622b2a | 166 | for (i = 0; i < dwc->num_event_buffers; i++) { |
72246da4 | 167 | evt = dwc->ev_buffs[i]; |
64b6c8a7 | 168 | if (evt) |
72246da4 | 169 | dwc3_free_one_event_buffer(dwc, evt); |
72246da4 FB |
170 | } |
171 | } | |
172 | ||
173 | /** | |
174 | * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length | |
1d046793 | 175 | * @dwc: pointer to our controller context structure |
72246da4 FB |
176 | * @length: size of event buffer |
177 | * | |
1d046793 | 178 | * Returns 0 on success otherwise negative errno. In the error case, dwc |
72246da4 FB |
179 | * may contain some buffers allocated but not all which were requested. |
180 | */ | |
41ac7b3a | 181 | static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) |
72246da4 | 182 | { |
9f622b2a | 183 | int num; |
72246da4 FB |
184 | int i; |
185 | ||
9f622b2a FB |
186 | num = DWC3_NUM_INT(dwc->hwparams.hwparams1); |
187 | dwc->num_event_buffers = num; | |
188 | ||
380f0d28 FB |
189 | dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num, |
190 | GFP_KERNEL); | |
734d5a53 | 191 | if (!dwc->ev_buffs) |
457d3f21 | 192 | return -ENOMEM; |
457d3f21 | 193 | |
72246da4 FB |
194 | for (i = 0; i < num; i++) { |
195 | struct dwc3_event_buffer *evt; | |
196 | ||
197 | evt = dwc3_alloc_one_event_buffer(dwc, length); | |
198 | if (IS_ERR(evt)) { | |
199 | dev_err(dwc->dev, "can't allocate event buffer\n"); | |
200 | return PTR_ERR(evt); | |
201 | } | |
202 | dwc->ev_buffs[i] = evt; | |
203 | } | |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
208 | /** | |
209 | * dwc3_event_buffers_setup - setup our allocated event buffers | |
1d046793 | 210 | * @dwc: pointer to our controller context structure |
72246da4 FB |
211 | * |
212 | * Returns 0 on success otherwise negative errno. | |
213 | */ | |
7acd85e0 | 214 | static int dwc3_event_buffers_setup(struct dwc3 *dwc) |
72246da4 FB |
215 | { |
216 | struct dwc3_event_buffer *evt; | |
217 | int n; | |
218 | ||
9f622b2a | 219 | for (n = 0; n < dwc->num_event_buffers; n++) { |
72246da4 FB |
220 | evt = dwc->ev_buffs[n]; |
221 | dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", | |
222 | evt->buf, (unsigned long long) evt->dma, | |
223 | evt->length); | |
224 | ||
7acd85e0 PZ |
225 | evt->lpos = 0; |
226 | ||
72246da4 FB |
227 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), |
228 | lower_32_bits(evt->dma)); | |
229 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), | |
230 | upper_32_bits(evt->dma)); | |
231 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), | |
68d6a01b | 232 | DWC3_GEVNTSIZ_SIZE(evt->length)); |
72246da4 FB |
233 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); |
234 | } | |
235 | ||
236 | return 0; | |
237 | } | |
238 | ||
239 | static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) | |
240 | { | |
241 | struct dwc3_event_buffer *evt; | |
242 | int n; | |
243 | ||
9f622b2a | 244 | for (n = 0; n < dwc->num_event_buffers; n++) { |
72246da4 | 245 | evt = dwc->ev_buffs[n]; |
7acd85e0 PZ |
246 | |
247 | evt->lpos = 0; | |
248 | ||
72246da4 FB |
249 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); |
250 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); | |
68d6a01b FB |
251 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK |
252 | | DWC3_GEVNTSIZ_SIZE(0)); | |
72246da4 FB |
253 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); |
254 | } | |
255 | } | |
256 | ||
0ffcaf37 FB |
257 | static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) |
258 | { | |
259 | if (!dwc->has_hibernation) | |
260 | return 0; | |
261 | ||
262 | if (!dwc->nr_scratch) | |
263 | return 0; | |
264 | ||
265 | dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, | |
266 | DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); | |
267 | if (!dwc->scratchbuf) | |
268 | return -ENOMEM; | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
273 | static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) | |
274 | { | |
275 | dma_addr_t scratch_addr; | |
276 | u32 param; | |
277 | int ret; | |
278 | ||
279 | if (!dwc->has_hibernation) | |
280 | return 0; | |
281 | ||
282 | if (!dwc->nr_scratch) | |
283 | return 0; | |
284 | ||
285 | /* should never fall here */ | |
286 | if (!WARN_ON(dwc->scratchbuf)) | |
287 | return 0; | |
288 | ||
289 | scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf, | |
290 | dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, | |
291 | DMA_BIDIRECTIONAL); | |
292 | if (dma_mapping_error(dwc->dev, scratch_addr)) { | |
293 | dev_err(dwc->dev, "failed to map scratch buffer\n"); | |
294 | ret = -EFAULT; | |
295 | goto err0; | |
296 | } | |
297 | ||
298 | dwc->scratch_addr = scratch_addr; | |
299 | ||
300 | param = lower_32_bits(scratch_addr); | |
301 | ||
302 | ret = dwc3_send_gadget_generic_command(dwc, | |
303 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); | |
304 | if (ret < 0) | |
305 | goto err1; | |
306 | ||
307 | param = upper_32_bits(scratch_addr); | |
308 | ||
309 | ret = dwc3_send_gadget_generic_command(dwc, | |
310 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); | |
311 | if (ret < 0) | |
312 | goto err1; | |
313 | ||
314 | return 0; | |
315 | ||
316 | err1: | |
317 | dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * | |
318 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); | |
319 | ||
320 | err0: | |
321 | return ret; | |
322 | } | |
323 | ||
324 | static void dwc3_free_scratch_buffers(struct dwc3 *dwc) | |
325 | { | |
326 | if (!dwc->has_hibernation) | |
327 | return; | |
328 | ||
329 | if (!dwc->nr_scratch) | |
330 | return; | |
331 | ||
332 | /* should never fall here */ | |
333 | if (!WARN_ON(dwc->scratchbuf)) | |
334 | return; | |
335 | ||
336 | dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * | |
337 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); | |
338 | kfree(dwc->scratchbuf); | |
339 | } | |
340 | ||
789451f6 FB |
341 | static void dwc3_core_num_eps(struct dwc3 *dwc) |
342 | { | |
343 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
344 | ||
345 | dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); | |
346 | dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; | |
347 | ||
73815280 | 348 | dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints", |
789451f6 FB |
349 | dwc->num_in_eps, dwc->num_out_eps); |
350 | } | |
351 | ||
41ac7b3a | 352 | static void dwc3_cache_hwparams(struct dwc3 *dwc) |
26ceca97 FB |
353 | { |
354 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
355 | ||
356 | parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); | |
357 | parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); | |
358 | parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); | |
359 | parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); | |
360 | parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); | |
361 | parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); | |
362 | parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); | |
363 | parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); | |
364 | parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); | |
365 | } | |
366 | ||
b5a65c40 HR |
367 | /** |
368 | * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core | |
369 | * @dwc: Pointer to our controller context structure | |
370 | */ | |
371 | static void dwc3_phy_setup(struct dwc3 *dwc) | |
372 | { | |
373 | u32 reg; | |
374 | ||
375 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
376 | ||
2164a476 HR |
377 | /* |
378 | * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY | |
379 | * to '0' during coreConsultant configuration. So default value | |
380 | * will be '0' when the core is reset. Application needs to set it | |
381 | * to '1' after the core initialization is completed. | |
382 | */ | |
383 | if (dwc->revision > DWC3_REVISION_194A) | |
384 | reg |= DWC3_GUSB3PIPECTL_SUSPHY; | |
385 | ||
b5a65c40 HR |
386 | if (dwc->u2ss_inp3_quirk) |
387 | reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; | |
388 | ||
df31f5b3 HR |
389 | if (dwc->req_p1p2p3_quirk) |
390 | reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; | |
391 | ||
a2a1d0f5 HR |
392 | if (dwc->del_p1p2p3_quirk) |
393 | reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; | |
394 | ||
41c06ffd HR |
395 | if (dwc->del_phy_power_chg_quirk) |
396 | reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; | |
397 | ||
fb67afca HR |
398 | if (dwc->lfps_filter_quirk) |
399 | reg |= DWC3_GUSB3PIPECTL_LFPSFILT; | |
400 | ||
14f4ac53 HR |
401 | if (dwc->rx_detect_poll_quirk) |
402 | reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; | |
403 | ||
6b6a0c9a HR |
404 | if (dwc->tx_de_emphasis_quirk) |
405 | reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); | |
406 | ||
cd72f890 | 407 | if (dwc->dis_u3_susphy_quirk) |
59acfa20 HR |
408 | reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; |
409 | ||
b5a65c40 HR |
410 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); |
411 | ||
412 | mdelay(100); | |
2164a476 HR |
413 | |
414 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
415 | ||
416 | /* | |
417 | * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to | |
418 | * '0' during coreConsultant configuration. So default value will | |
419 | * be '0' when the core is reset. Application needs to set it to | |
420 | * '1' after the core initialization is completed. | |
421 | */ | |
422 | if (dwc->revision > DWC3_REVISION_194A) | |
423 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; | |
424 | ||
cd72f890 | 425 | if (dwc->dis_u2_susphy_quirk) |
0effe0a3 HR |
426 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; |
427 | ||
2164a476 HR |
428 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
429 | ||
430 | mdelay(100); | |
b5a65c40 HR |
431 | } |
432 | ||
72246da4 FB |
433 | /** |
434 | * dwc3_core_init - Low-level initialization of DWC3 Core | |
435 | * @dwc: Pointer to our controller context structure | |
436 | * | |
437 | * Returns 0 on success otherwise negative errno. | |
438 | */ | |
41ac7b3a | 439 | static int dwc3_core_init(struct dwc3 *dwc) |
72246da4 FB |
440 | { |
441 | unsigned long timeout; | |
0ffcaf37 | 442 | u32 hwparams4 = dwc->hwparams.hwparams4; |
72246da4 FB |
443 | u32 reg; |
444 | int ret; | |
445 | ||
7650bd74 SAS |
446 | reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); |
447 | /* This should read as U3 followed by revision number */ | |
448 | if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { | |
449 | dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); | |
450 | ret = -ENODEV; | |
451 | goto err0; | |
452 | } | |
248b122b | 453 | dwc->revision = reg; |
7650bd74 | 454 | |
fa0ea13e FB |
455 | /* |
456 | * Write Linux Version Code to our GUID register so it's easy to figure | |
457 | * out which kernel version a bug was found. | |
458 | */ | |
459 | dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); | |
460 | ||
0e1e5c47 PZ |
461 | /* Handle USB2.0-only core configuration */ |
462 | if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == | |
463 | DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { | |
464 | if (dwc->maximum_speed == USB_SPEED_SUPER) | |
465 | dwc->maximum_speed = USB_SPEED_HIGH; | |
466 | } | |
467 | ||
72246da4 FB |
468 | /* issue device SoftReset too */ |
469 | timeout = jiffies + msecs_to_jiffies(500); | |
470 | dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); | |
471 | do { | |
472 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
473 | if (!(reg & DWC3_DCTL_CSFTRST)) | |
474 | break; | |
475 | ||
476 | if (time_after(jiffies, timeout)) { | |
477 | dev_err(dwc->dev, "Reset Timed Out\n"); | |
478 | ret = -ETIMEDOUT; | |
479 | goto err0; | |
480 | } | |
481 | ||
482 | cpu_relax(); | |
483 | } while (true); | |
484 | ||
57303488 KVA |
485 | ret = dwc3_core_soft_reset(dwc); |
486 | if (ret) | |
487 | goto err0; | |
58a0f23f | 488 | |
4878a028 | 489 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); |
3e87c42a | 490 | reg &= ~DWC3_GCTL_SCALEDOWN_MASK; |
4878a028 | 491 | |
164d7731 | 492 | switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { |
4878a028 | 493 | case DWC3_GHWPARAMS1_EN_PWROPT_CLK: |
32a4a135 FB |
494 | /** |
495 | * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an | |
496 | * issue which would cause xHCI compliance tests to fail. | |
497 | * | |
498 | * Because of that we cannot enable clock gating on such | |
499 | * configurations. | |
500 | * | |
501 | * Refers to: | |
502 | * | |
503 | * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based | |
504 | * SOF/ITP Mode Used | |
505 | */ | |
506 | if ((dwc->dr_mode == USB_DR_MODE_HOST || | |
507 | dwc->dr_mode == USB_DR_MODE_OTG) && | |
508 | (dwc->revision >= DWC3_REVISION_210A && | |
509 | dwc->revision <= DWC3_REVISION_250A)) | |
510 | reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; | |
511 | else | |
512 | reg &= ~DWC3_GCTL_DSBLCLKGTNG; | |
4878a028 | 513 | break; |
0ffcaf37 FB |
514 | case DWC3_GHWPARAMS1_EN_PWROPT_HIB: |
515 | /* enable hibernation here */ | |
516 | dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); | |
2eac3992 HR |
517 | |
518 | /* | |
519 | * REVISIT Enabling this bit so that host-mode hibernation | |
520 | * will work. Device-mode hibernation is not yet implemented. | |
521 | */ | |
522 | reg |= DWC3_GCTL_GBLHIBERNATIONEN; | |
0ffcaf37 | 523 | break; |
4878a028 SAS |
524 | default: |
525 | dev_dbg(dwc->dev, "No power optimization available\n"); | |
526 | } | |
527 | ||
946bd579 HR |
528 | /* check if current dwc3 is on simulation board */ |
529 | if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { | |
530 | dev_dbg(dwc->dev, "it is on FPGA board\n"); | |
531 | dwc->is_fpga = true; | |
532 | } | |
533 | ||
3b81221a HR |
534 | WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, |
535 | "disable_scramble cannot be used on non-FPGA builds\n"); | |
536 | ||
537 | if (dwc->disable_scramble_quirk && dwc->is_fpga) | |
538 | reg |= DWC3_GCTL_DISSCRAMBLE; | |
539 | else | |
540 | reg &= ~DWC3_GCTL_DISSCRAMBLE; | |
541 | ||
9a5b2f31 HR |
542 | if (dwc->u2exit_lfps_quirk) |
543 | reg |= DWC3_GCTL_U2EXIT_LFPS; | |
544 | ||
4878a028 SAS |
545 | /* |
546 | * WORKAROUND: DWC3 revisions <1.90a have a bug | |
1d046793 | 547 | * where the device can fail to connect at SuperSpeed |
4878a028 | 548 | * and falls back to high-speed mode which causes |
1d046793 | 549 | * the device to enter a Connect/Disconnect loop |
4878a028 SAS |
550 | */ |
551 | if (dwc->revision < DWC3_REVISION_190A) | |
552 | reg |= DWC3_GCTL_U2RSTECN; | |
553 | ||
789451f6 FB |
554 | dwc3_core_num_eps(dwc); |
555 | ||
4878a028 SAS |
556 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); |
557 | ||
b5a65c40 HR |
558 | dwc3_phy_setup(dwc); |
559 | ||
0ffcaf37 FB |
560 | ret = dwc3_alloc_scratch_buffers(dwc); |
561 | if (ret) | |
562 | goto err1; | |
563 | ||
564 | ret = dwc3_setup_scratch_buffers(dwc); | |
565 | if (ret) | |
566 | goto err2; | |
567 | ||
72246da4 FB |
568 | return 0; |
569 | ||
0ffcaf37 FB |
570 | err2: |
571 | dwc3_free_scratch_buffers(dwc); | |
572 | ||
573 | err1: | |
574 | usb_phy_shutdown(dwc->usb2_phy); | |
575 | usb_phy_shutdown(dwc->usb3_phy); | |
57303488 KVA |
576 | phy_exit(dwc->usb2_generic_phy); |
577 | phy_exit(dwc->usb3_generic_phy); | |
0ffcaf37 | 578 | |
72246da4 FB |
579 | err0: |
580 | return ret; | |
581 | } | |
582 | ||
583 | static void dwc3_core_exit(struct dwc3 *dwc) | |
584 | { | |
0ffcaf37 | 585 | dwc3_free_scratch_buffers(dwc); |
01b8daf7 VG |
586 | usb_phy_shutdown(dwc->usb2_phy); |
587 | usb_phy_shutdown(dwc->usb3_phy); | |
57303488 KVA |
588 | phy_exit(dwc->usb2_generic_phy); |
589 | phy_exit(dwc->usb3_generic_phy); | |
72246da4 FB |
590 | } |
591 | ||
3c9f94ac | 592 | static int dwc3_core_get_phy(struct dwc3 *dwc) |
72246da4 | 593 | { |
3c9f94ac | 594 | struct device *dev = dwc->dev; |
941ea361 | 595 | struct device_node *node = dev->of_node; |
3c9f94ac | 596 | int ret; |
72246da4 | 597 | |
5088b6f5 KVA |
598 | if (node) { |
599 | dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); | |
600 | dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); | |
bb674907 FB |
601 | } else { |
602 | dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); | |
603 | dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); | |
5088b6f5 KVA |
604 | } |
605 | ||
d105e7f8 FB |
606 | if (IS_ERR(dwc->usb2_phy)) { |
607 | ret = PTR_ERR(dwc->usb2_phy); | |
122f06e6 KVA |
608 | if (ret == -ENXIO || ret == -ENODEV) { |
609 | dwc->usb2_phy = NULL; | |
610 | } else if (ret == -EPROBE_DEFER) { | |
d105e7f8 | 611 | return ret; |
122f06e6 KVA |
612 | } else { |
613 | dev_err(dev, "no usb2 phy configured\n"); | |
614 | return ret; | |
615 | } | |
51e1e7bc FB |
616 | } |
617 | ||
d105e7f8 | 618 | if (IS_ERR(dwc->usb3_phy)) { |
315955d7 | 619 | ret = PTR_ERR(dwc->usb3_phy); |
122f06e6 KVA |
620 | if (ret == -ENXIO || ret == -ENODEV) { |
621 | dwc->usb3_phy = NULL; | |
622 | } else if (ret == -EPROBE_DEFER) { | |
d105e7f8 | 623 | return ret; |
122f06e6 KVA |
624 | } else { |
625 | dev_err(dev, "no usb3 phy configured\n"); | |
626 | return ret; | |
627 | } | |
51e1e7bc FB |
628 | } |
629 | ||
57303488 KVA |
630 | dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); |
631 | if (IS_ERR(dwc->usb2_generic_phy)) { | |
632 | ret = PTR_ERR(dwc->usb2_generic_phy); | |
633 | if (ret == -ENOSYS || ret == -ENODEV) { | |
634 | dwc->usb2_generic_phy = NULL; | |
635 | } else if (ret == -EPROBE_DEFER) { | |
636 | return ret; | |
637 | } else { | |
638 | dev_err(dev, "no usb2 phy configured\n"); | |
639 | return ret; | |
640 | } | |
641 | } | |
642 | ||
643 | dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); | |
644 | if (IS_ERR(dwc->usb3_generic_phy)) { | |
645 | ret = PTR_ERR(dwc->usb3_generic_phy); | |
646 | if (ret == -ENOSYS || ret == -ENODEV) { | |
647 | dwc->usb3_generic_phy = NULL; | |
648 | } else if (ret == -EPROBE_DEFER) { | |
649 | return ret; | |
650 | } else { | |
651 | dev_err(dev, "no usb3 phy configured\n"); | |
652 | return ret; | |
653 | } | |
654 | } | |
655 | ||
3c9f94ac FB |
656 | return 0; |
657 | } | |
658 | ||
5f94adfe FB |
659 | static int dwc3_core_init_mode(struct dwc3 *dwc) |
660 | { | |
661 | struct device *dev = dwc->dev; | |
662 | int ret; | |
663 | ||
664 | switch (dwc->dr_mode) { | |
665 | case USB_DR_MODE_PERIPHERAL: | |
666 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); | |
667 | ret = dwc3_gadget_init(dwc); | |
668 | if (ret) { | |
669 | dev_err(dev, "failed to initialize gadget\n"); | |
670 | return ret; | |
671 | } | |
672 | break; | |
673 | case USB_DR_MODE_HOST: | |
674 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); | |
675 | ret = dwc3_host_init(dwc); | |
676 | if (ret) { | |
677 | dev_err(dev, "failed to initialize host\n"); | |
678 | return ret; | |
679 | } | |
680 | break; | |
681 | case USB_DR_MODE_OTG: | |
682 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); | |
683 | ret = dwc3_host_init(dwc); | |
684 | if (ret) { | |
685 | dev_err(dev, "failed to initialize host\n"); | |
686 | return ret; | |
687 | } | |
688 | ||
689 | ret = dwc3_gadget_init(dwc); | |
690 | if (ret) { | |
691 | dev_err(dev, "failed to initialize gadget\n"); | |
692 | return ret; | |
693 | } | |
694 | break; | |
695 | default: | |
696 | dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); | |
697 | return -EINVAL; | |
698 | } | |
699 | ||
700 | return 0; | |
701 | } | |
702 | ||
703 | static void dwc3_core_exit_mode(struct dwc3 *dwc) | |
704 | { | |
705 | switch (dwc->dr_mode) { | |
706 | case USB_DR_MODE_PERIPHERAL: | |
707 | dwc3_gadget_exit(dwc); | |
708 | break; | |
709 | case USB_DR_MODE_HOST: | |
710 | dwc3_host_exit(dwc); | |
711 | break; | |
712 | case USB_DR_MODE_OTG: | |
713 | dwc3_host_exit(dwc); | |
714 | dwc3_gadget_exit(dwc); | |
715 | break; | |
716 | default: | |
717 | /* do nothing */ | |
718 | break; | |
719 | } | |
720 | } | |
721 | ||
3c9f94ac FB |
722 | #define DWC3_ALIGN_MASK (16 - 1) |
723 | ||
724 | static int dwc3_probe(struct platform_device *pdev) | |
725 | { | |
726 | struct device *dev = &pdev->dev; | |
727 | struct dwc3_platform_data *pdata = dev_get_platdata(dev); | |
728 | struct device_node *node = dev->of_node; | |
729 | struct resource *res; | |
730 | struct dwc3 *dwc; | |
80caf7d2 | 731 | u8 lpm_nyet_threshold; |
6b6a0c9a | 732 | u8 tx_de_emphasis; |
460d098c | 733 | u8 hird_threshold; |
3c9f94ac | 734 | |
b09e99ee | 735 | int ret; |
3c9f94ac FB |
736 | |
737 | void __iomem *regs; | |
738 | void *mem; | |
739 | ||
740 | mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); | |
734d5a53 | 741 | if (!mem) |
3c9f94ac | 742 | return -ENOMEM; |
734d5a53 | 743 | |
3c9f94ac FB |
744 | dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); |
745 | dwc->mem = mem; | |
746 | dwc->dev = dev; | |
747 | ||
748 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
749 | if (!res) { | |
750 | dev_err(dev, "missing IRQ\n"); | |
751 | return -ENODEV; | |
752 | } | |
753 | dwc->xhci_resources[1].start = res->start; | |
754 | dwc->xhci_resources[1].end = res->end; | |
755 | dwc->xhci_resources[1].flags = res->flags; | |
756 | dwc->xhci_resources[1].name = res->name; | |
757 | ||
758 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
759 | if (!res) { | |
760 | dev_err(dev, "missing memory resource\n"); | |
761 | return -ENODEV; | |
762 | } | |
763 | ||
f32a5e23 VG |
764 | dwc->xhci_resources[0].start = res->start; |
765 | dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + | |
766 | DWC3_XHCI_REGS_END; | |
767 | dwc->xhci_resources[0].flags = res->flags; | |
768 | dwc->xhci_resources[0].name = res->name; | |
769 | ||
770 | res->start += DWC3_GLOBALS_REGS_START; | |
771 | ||
772 | /* | |
773 | * Request memory region but exclude xHCI regs, | |
774 | * since it will be requested by the xhci-plat driver. | |
775 | */ | |
776 | regs = devm_ioremap_resource(dev, res); | |
3da1f6ee FB |
777 | if (IS_ERR(regs)) { |
778 | ret = PTR_ERR(regs); | |
779 | goto err0; | |
780 | } | |
f32a5e23 VG |
781 | |
782 | dwc->regs = regs; | |
783 | dwc->regs_size = resource_size(res); | |
f32a5e23 | 784 | |
80caf7d2 HR |
785 | /* default to highest possible threshold */ |
786 | lpm_nyet_threshold = 0xff; | |
787 | ||
6b6a0c9a HR |
788 | /* default to -3.5dB de-emphasis */ |
789 | tx_de_emphasis = 1; | |
790 | ||
460d098c HR |
791 | /* |
792 | * default to assert utmi_sleep_n and use maximum allowed HIRD | |
793 | * threshold value of 0b1100 | |
794 | */ | |
795 | hird_threshold = 12; | |
796 | ||
3c9f94ac FB |
797 | if (node) { |
798 | dwc->maximum_speed = of_usb_get_maximum_speed(node); | |
80caf7d2 HR |
799 | dwc->has_lpm_erratum = of_property_read_bool(node, |
800 | "snps,has-lpm-erratum"); | |
801 | of_property_read_u8(node, "snps,lpm-nyet-threshold", | |
802 | &lpm_nyet_threshold); | |
460d098c HR |
803 | dwc->is_utmi_l1_suspend = of_property_read_bool(node, |
804 | "snps,is-utmi-l1-suspend"); | |
805 | of_property_read_u8(node, "snps,hird-threshold", | |
806 | &hird_threshold); | |
eac68e8f RB |
807 | dwc->usb3_lpm_capable = of_property_read_bool(node, |
808 | "snps,usb3_lpm_capable"); | |
3c9f94ac | 809 | |
80caf7d2 HR |
810 | dwc->needs_fifo_resize = of_property_read_bool(node, |
811 | "tx-fifo-resize"); | |
3c9f94ac | 812 | dwc->dr_mode = of_usb_get_dr_mode(node); |
3b81221a HR |
813 | |
814 | dwc->disable_scramble_quirk = of_property_read_bool(node, | |
815 | "snps,disable_scramble_quirk"); | |
9a5b2f31 HR |
816 | dwc->u2exit_lfps_quirk = of_property_read_bool(node, |
817 | "snps,u2exit_lfps_quirk"); | |
b5a65c40 HR |
818 | dwc->u2ss_inp3_quirk = of_property_read_bool(node, |
819 | "snps,u2ss_inp3_quirk"); | |
df31f5b3 HR |
820 | dwc->req_p1p2p3_quirk = of_property_read_bool(node, |
821 | "snps,req_p1p2p3_quirk"); | |
a2a1d0f5 HR |
822 | dwc->del_p1p2p3_quirk = of_property_read_bool(node, |
823 | "snps,del_p1p2p3_quirk"); | |
41c06ffd HR |
824 | dwc->del_phy_power_chg_quirk = of_property_read_bool(node, |
825 | "snps,del_phy_power_chg_quirk"); | |
fb67afca HR |
826 | dwc->lfps_filter_quirk = of_property_read_bool(node, |
827 | "snps,lfps_filter_quirk"); | |
14f4ac53 HR |
828 | dwc->rx_detect_poll_quirk = of_property_read_bool(node, |
829 | "snps,rx_detect_poll_quirk"); | |
59acfa20 HR |
830 | dwc->dis_u3_susphy_quirk = of_property_read_bool(node, |
831 | "snps,dis_u3_susphy_quirk"); | |
0effe0a3 HR |
832 | dwc->dis_u2_susphy_quirk = of_property_read_bool(node, |
833 | "snps,dis_u2_susphy_quirk"); | |
6b6a0c9a HR |
834 | |
835 | dwc->tx_de_emphasis_quirk = of_property_read_bool(node, | |
836 | "snps,tx_de_emphasis_quirk"); | |
837 | of_property_read_u8(node, "snps,tx_de_emphasis", | |
838 | &tx_de_emphasis); | |
3c9f94ac FB |
839 | } else if (pdata) { |
840 | dwc->maximum_speed = pdata->maximum_speed; | |
80caf7d2 HR |
841 | dwc->has_lpm_erratum = pdata->has_lpm_erratum; |
842 | if (pdata->lpm_nyet_threshold) | |
843 | lpm_nyet_threshold = pdata->lpm_nyet_threshold; | |
460d098c HR |
844 | dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend; |
845 | if (pdata->hird_threshold) | |
846 | hird_threshold = pdata->hird_threshold; | |
3c9f94ac FB |
847 | |
848 | dwc->needs_fifo_resize = pdata->tx_fifo_resize; | |
eac68e8f | 849 | dwc->usb3_lpm_capable = pdata->usb3_lpm_capable; |
3c9f94ac | 850 | dwc->dr_mode = pdata->dr_mode; |
3b81221a HR |
851 | |
852 | dwc->disable_scramble_quirk = pdata->disable_scramble_quirk; | |
9a5b2f31 | 853 | dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk; |
b5a65c40 | 854 | dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk; |
df31f5b3 | 855 | dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk; |
a2a1d0f5 | 856 | dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk; |
41c06ffd | 857 | dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk; |
fb67afca | 858 | dwc->lfps_filter_quirk = pdata->lfps_filter_quirk; |
14f4ac53 | 859 | dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk; |
59acfa20 | 860 | dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk; |
0effe0a3 | 861 | dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk; |
6b6a0c9a HR |
862 | |
863 | dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk; | |
864 | if (pdata->tx_de_emphasis) | |
865 | tx_de_emphasis = pdata->tx_de_emphasis; | |
3c9f94ac FB |
866 | } |
867 | ||
868 | /* default to superspeed if no maximum_speed passed */ | |
869 | if (dwc->maximum_speed == USB_SPEED_UNKNOWN) | |
870 | dwc->maximum_speed = USB_SPEED_SUPER; | |
871 | ||
80caf7d2 | 872 | dwc->lpm_nyet_threshold = lpm_nyet_threshold; |
6b6a0c9a | 873 | dwc->tx_de_emphasis = tx_de_emphasis; |
80caf7d2 | 874 | |
460d098c HR |
875 | dwc->hird_threshold = hird_threshold |
876 | | (dwc->is_utmi_l1_suspend << 4); | |
877 | ||
6c89cce0 HK |
878 | platform_set_drvdata(pdev, dwc); |
879 | ||
3c9f94ac FB |
880 | ret = dwc3_core_get_phy(dwc); |
881 | if (ret) | |
3da1f6ee | 882 | goto err0; |
3c9f94ac | 883 | |
72246da4 | 884 | spin_lock_init(&dwc->lock); |
72246da4 | 885 | |
19bacdc9 HK |
886 | if (!dev->dma_mask) { |
887 | dev->dma_mask = dev->parent->dma_mask; | |
888 | dev->dma_parms = dev->parent->dma_parms; | |
889 | dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask); | |
890 | } | |
ddff14f1 | 891 | |
802ca850 CP |
892 | pm_runtime_enable(dev); |
893 | pm_runtime_get_sync(dev); | |
894 | pm_runtime_forbid(dev); | |
72246da4 | 895 | |
4fd24483 KVA |
896 | dwc3_cache_hwparams(dwc); |
897 | ||
3921426b FB |
898 | ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); |
899 | if (ret) { | |
900 | dev_err(dwc->dev, "failed to allocate event buffers\n"); | |
901 | ret = -ENOMEM; | |
3da1f6ee | 902 | goto err1; |
3921426b FB |
903 | } |
904 | ||
32a4a135 FB |
905 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) |
906 | dwc->dr_mode = USB_DR_MODE_HOST; | |
907 | else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) | |
908 | dwc->dr_mode = USB_DR_MODE_PERIPHERAL; | |
909 | ||
910 | if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) | |
911 | dwc->dr_mode = USB_DR_MODE_OTG; | |
912 | ||
72246da4 FB |
913 | ret = dwc3_core_init(dwc); |
914 | if (ret) { | |
802ca850 | 915 | dev_err(dev, "failed to initialize core\n"); |
3da1f6ee | 916 | goto err1; |
72246da4 FB |
917 | } |
918 | ||
3088f108 KVA |
919 | usb_phy_set_suspend(dwc->usb2_phy, 0); |
920 | usb_phy_set_suspend(dwc->usb3_phy, 0); | |
57303488 KVA |
921 | ret = phy_power_on(dwc->usb2_generic_phy); |
922 | if (ret < 0) | |
3da1f6ee | 923 | goto err2; |
57303488 KVA |
924 | |
925 | ret = phy_power_on(dwc->usb3_generic_phy); | |
926 | if (ret < 0) | |
3da1f6ee | 927 | goto err3; |
3088f108 | 928 | |
f122d33e FB |
929 | ret = dwc3_event_buffers_setup(dwc); |
930 | if (ret) { | |
931 | dev_err(dwc->dev, "failed to setup event buffers\n"); | |
3da1f6ee | 932 | goto err4; |
f122d33e FB |
933 | } |
934 | ||
5f94adfe FB |
935 | ret = dwc3_core_init_mode(dwc); |
936 | if (ret) | |
3da1f6ee | 937 | goto err5; |
72246da4 FB |
938 | |
939 | ret = dwc3_debugfs_init(dwc); | |
940 | if (ret) { | |
802ca850 | 941 | dev_err(dev, "failed to initialize debugfs\n"); |
3da1f6ee | 942 | goto err6; |
72246da4 FB |
943 | } |
944 | ||
802ca850 | 945 | pm_runtime_allow(dev); |
72246da4 FB |
946 | |
947 | return 0; | |
948 | ||
3da1f6ee | 949 | err6: |
5f94adfe | 950 | dwc3_core_exit_mode(dwc); |
72246da4 | 951 | |
3da1f6ee | 952 | err5: |
f122d33e FB |
953 | dwc3_event_buffers_cleanup(dwc); |
954 | ||
3da1f6ee | 955 | err4: |
57303488 KVA |
956 | phy_power_off(dwc->usb3_generic_phy); |
957 | ||
3da1f6ee | 958 | err3: |
57303488 KVA |
959 | phy_power_off(dwc->usb2_generic_phy); |
960 | ||
3da1f6ee | 961 | err2: |
501fae51 KVA |
962 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
963 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
802ca850 | 964 | dwc3_core_exit(dwc); |
72246da4 | 965 | |
3da1f6ee | 966 | err1: |
3921426b FB |
967 | dwc3_free_event_buffers(dwc); |
968 | ||
3da1f6ee FB |
969 | err0: |
970 | /* | |
971 | * restore res->start back to its original value so that, in case the | |
972 | * probe is deferred, we don't end up getting error in request the | |
973 | * memory region the next time probe is called. | |
974 | */ | |
975 | res->start -= DWC3_GLOBALS_REGS_START; | |
976 | ||
72246da4 FB |
977 | return ret; |
978 | } | |
979 | ||
fb4e98ab | 980 | static int dwc3_remove(struct platform_device *pdev) |
72246da4 | 981 | { |
72246da4 | 982 | struct dwc3 *dwc = platform_get_drvdata(pdev); |
3da1f6ee FB |
983 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
984 | ||
985 | /* | |
986 | * restore res->start back to its original value so that, in case the | |
987 | * probe is deferred, we don't end up getting error in request the | |
988 | * memory region the next time probe is called. | |
989 | */ | |
990 | res->start -= DWC3_GLOBALS_REGS_START; | |
72246da4 | 991 | |
dc99f16f FB |
992 | dwc3_debugfs_exit(dwc); |
993 | dwc3_core_exit_mode(dwc); | |
994 | dwc3_event_buffers_cleanup(dwc); | |
995 | dwc3_free_event_buffers(dwc); | |
996 | ||
8ba007a9 KVA |
997 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
998 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
57303488 KVA |
999 | phy_power_off(dwc->usb2_generic_phy); |
1000 | phy_power_off(dwc->usb3_generic_phy); | |
8ba007a9 | 1001 | |
72246da4 | 1002 | dwc3_core_exit(dwc); |
72246da4 | 1003 | |
16b972a5 | 1004 | pm_runtime_put_sync(&pdev->dev); |
72246da4 FB |
1005 | pm_runtime_disable(&pdev->dev); |
1006 | ||
72246da4 FB |
1007 | return 0; |
1008 | } | |
1009 | ||
19fda7cd | 1010 | #ifdef CONFIG_PM_SLEEP |
7415f17c FB |
1011 | static int dwc3_suspend(struct device *dev) |
1012 | { | |
1013 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1014 | unsigned long flags; | |
1015 | ||
1016 | spin_lock_irqsave(&dwc->lock, flags); | |
1017 | ||
a45c82b8 RK |
1018 | switch (dwc->dr_mode) { |
1019 | case USB_DR_MODE_PERIPHERAL: | |
1020 | case USB_DR_MODE_OTG: | |
7415f17c FB |
1021 | dwc3_gadget_suspend(dwc); |
1022 | /* FALLTHROUGH */ | |
a45c82b8 | 1023 | case USB_DR_MODE_HOST: |
7415f17c | 1024 | default: |
0b0231aa | 1025 | dwc3_event_buffers_cleanup(dwc); |
7415f17c FB |
1026 | break; |
1027 | } | |
1028 | ||
1029 | dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL); | |
1030 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1031 | ||
1032 | usb_phy_shutdown(dwc->usb3_phy); | |
1033 | usb_phy_shutdown(dwc->usb2_phy); | |
57303488 KVA |
1034 | phy_exit(dwc->usb2_generic_phy); |
1035 | phy_exit(dwc->usb3_generic_phy); | |
7415f17c FB |
1036 | |
1037 | return 0; | |
1038 | } | |
1039 | ||
1040 | static int dwc3_resume(struct device *dev) | |
1041 | { | |
1042 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1043 | unsigned long flags; | |
57303488 | 1044 | int ret; |
7415f17c FB |
1045 | |
1046 | usb_phy_init(dwc->usb3_phy); | |
1047 | usb_phy_init(dwc->usb2_phy); | |
57303488 KVA |
1048 | ret = phy_init(dwc->usb2_generic_phy); |
1049 | if (ret < 0) | |
1050 | return ret; | |
1051 | ||
1052 | ret = phy_init(dwc->usb3_generic_phy); | |
1053 | if (ret < 0) | |
1054 | goto err_usb2phy_init; | |
7415f17c FB |
1055 | |
1056 | spin_lock_irqsave(&dwc->lock, flags); | |
1057 | ||
0b0231aa | 1058 | dwc3_event_buffers_setup(dwc); |
7415f17c FB |
1059 | dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl); |
1060 | ||
a45c82b8 RK |
1061 | switch (dwc->dr_mode) { |
1062 | case USB_DR_MODE_PERIPHERAL: | |
1063 | case USB_DR_MODE_OTG: | |
7415f17c FB |
1064 | dwc3_gadget_resume(dwc); |
1065 | /* FALLTHROUGH */ | |
a45c82b8 | 1066 | case USB_DR_MODE_HOST: |
7415f17c FB |
1067 | default: |
1068 | /* do nothing */ | |
1069 | break; | |
1070 | } | |
1071 | ||
1072 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1073 | ||
1074 | pm_runtime_disable(dev); | |
1075 | pm_runtime_set_active(dev); | |
1076 | pm_runtime_enable(dev); | |
1077 | ||
1078 | return 0; | |
57303488 KVA |
1079 | |
1080 | err_usb2phy_init: | |
1081 | phy_exit(dwc->usb2_generic_phy); | |
1082 | ||
1083 | return ret; | |
7415f17c FB |
1084 | } |
1085 | ||
1086 | static const struct dev_pm_ops dwc3_dev_pm_ops = { | |
7415f17c FB |
1087 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) |
1088 | }; | |
1089 | ||
1090 | #define DWC3_PM_OPS &(dwc3_dev_pm_ops) | |
1091 | #else | |
1092 | #define DWC3_PM_OPS NULL | |
1093 | #endif | |
1094 | ||
5088b6f5 KVA |
1095 | #ifdef CONFIG_OF |
1096 | static const struct of_device_id of_dwc3_match[] = { | |
22a5aa17 FB |
1097 | { |
1098 | .compatible = "snps,dwc3" | |
1099 | }, | |
5088b6f5 KVA |
1100 | { |
1101 | .compatible = "synopsys,dwc3" | |
1102 | }, | |
1103 | { }, | |
1104 | }; | |
1105 | MODULE_DEVICE_TABLE(of, of_dwc3_match); | |
1106 | #endif | |
1107 | ||
404905a6 HK |
1108 | #ifdef CONFIG_ACPI |
1109 | ||
1110 | #define ACPI_ID_INTEL_BSW "808622B7" | |
1111 | ||
1112 | static const struct acpi_device_id dwc3_acpi_match[] = { | |
1113 | { ACPI_ID_INTEL_BSW, 0 }, | |
1114 | { }, | |
1115 | }; | |
1116 | MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); | |
1117 | #endif | |
1118 | ||
72246da4 FB |
1119 | static struct platform_driver dwc3_driver = { |
1120 | .probe = dwc3_probe, | |
7690417d | 1121 | .remove = dwc3_remove, |
72246da4 FB |
1122 | .driver = { |
1123 | .name = "dwc3", | |
5088b6f5 | 1124 | .of_match_table = of_match_ptr(of_dwc3_match), |
404905a6 | 1125 | .acpi_match_table = ACPI_PTR(dwc3_acpi_match), |
7415f17c | 1126 | .pm = DWC3_PM_OPS, |
72246da4 | 1127 | }, |
72246da4 FB |
1128 | }; |
1129 | ||
b1116dcc TK |
1130 | module_platform_driver(dwc3_driver); |
1131 | ||
7ae4fc4d | 1132 | MODULE_ALIAS("platform:dwc3"); |
72246da4 | 1133 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); |
5945f789 | 1134 | MODULE_LICENSE("GPL v2"); |
72246da4 | 1135 | MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); |