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usb: dwc3: core: Check maximum_speed SSP genXxY
[linux-block.git] / drivers / usb / dwc3 / core.c
CommitLineData
5fd54ace 1// SPDX-License-Identifier: GPL-2.0
cbdc0f54 2/*
72246da4
FB		 3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
10623b87 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
72246da4
FB		 6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
72246da4
FB		 9 */
10
fe8abf33 11#include <linux/clk.h>
fa0ea13e 12#include <linux/version.h>
a72e658b 13#include <linux/module.h>
72246da4
FB		 14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/io.h>
22#include <linux/list.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
457e84b6 25#include <linux/of.h>
404905a6 26#include <linux/acpi.h>
6344475f 27#include <linux/pinctrl/consumer.h>
fe8abf33 28#include <linux/reset.h>
72246da4
FB		 29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
f7e846f0 32#include <linux/usb/of.h>
a45c82b8 33#include <linux/usb/otg.h>
72246da4
FB		 34
35#include "core.h"
36#include "gadget.h"
37#include "io.h"
38
39#include "debug.h"
40
fc8bb91b 41#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
8300dd23 42
9d6173e1
TN		 43/**
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
46 */
47static int dwc3_get_dr_mode(struct dwc3 *dwc)
48{
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
51 unsigned int hw_mode;
52
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
55
56 mode = dwc->dr_mode;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
58
59 switch (hw_mode) {
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
62 dev_err(dev,
63 "Controller does not support host mode.\n");
64 return -EINVAL;
65 }
66 mode = USB_DR_MODE_PERIPHERAL;
67 break;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
70 dev_err(dev,
71 "Controller does not support device mode.\n");
72 return -EINVAL;
73 }
74 mode = USB_DR_MODE_HOST;
75 break;
76 default:
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
a7700468
TN		 81
82 /*
89a9cc47
TN		 83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
84 * mode. If the controller supports DRD but the dr_mode is not
85 * specified or set to OTG, then set the mode to peripheral.
a7700468 86 */
89a9cc47 87 if (mode == USB_DR_MODE_OTG &&
8bb14308
TN		 88 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
89 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
9af21dd6 90 !DWC3_VER_IS_PRIOR(DWC3, 330A))
a7700468 91 mode = USB_DR_MODE_PERIPHERAL;
9d6173e1
TN		 92 }
93
94 if (mode != dwc->dr_mode) {
95 dev_warn(dev,
96 "Configuration mismatch. dr_mode forced to %s\n",
97 mode == USB_DR_MODE_HOST ? "host" : "gadget");
98
99 dwc->dr_mode = mode;
100 }
101
102 return 0;
103}
104
f09cc79b 105void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
3140e8cb
SAS		 106{
107 u32 reg;
108
109 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
110 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
111 reg |= DWC3_GCTL_PRTCAPDIR(mode);
112 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
c4a5153e
MG		 113
114 dwc->current_dr_role = mode;
41ce1456
RQ		 115}
116
117static void __dwc3_set_mode(struct work_struct *work)
118{
119 struct dwc3 *dwc = work_to_dwc(work);
120 unsigned long flags;
121 int ret;
f580170f 122 u32 reg;
41ce1456 123
c2cd3452
MK		 124 pm_runtime_get_sync(dwc->dev);
125
f09cc79b
RQ		 126 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
127 dwc3_otg_update(dwc, 0);
128
41ce1456 129 if (!dwc->desired_dr_role)
c2cd3452 130 goto out;
41ce1456
RQ		 131
132 if (dwc->desired_dr_role == dwc->current_dr_role)
c2cd3452 133 goto out;
41ce1456 134
f09cc79b 135 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
c2cd3452 136 goto out;
41ce1456
RQ		 137
138 switch (dwc->current_dr_role) {
139 case DWC3_GCTL_PRTCAP_HOST:
140 dwc3_host_exit(dwc);
141 break;
142 case DWC3_GCTL_PRTCAP_DEVICE:
143 dwc3_gadget_exit(dwc);
144 dwc3_event_buffers_cleanup(dwc);
145 break;
f09cc79b
RQ		 146 case DWC3_GCTL_PRTCAP_OTG:
147 dwc3_otg_exit(dwc);
148 spin_lock_irqsave(&dwc->lock, flags);
149 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
150 spin_unlock_irqrestore(&dwc->lock, flags);
151 dwc3_otg_update(dwc, 1);
152 break;
41ce1456
RQ		 153 default:
154 break;
155 }
156
157 spin_lock_irqsave(&dwc->lock, flags);
158
159 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
6b3261a2 160
41ce1456
RQ		 161 spin_unlock_irqrestore(&dwc->lock, flags);
162
163 switch (dwc->desired_dr_role) {
164 case DWC3_GCTL_PRTCAP_HOST:
165 ret = dwc3_host_init(dwc);
958d1a4c 166 if (ret) {
41ce1456 167 dev_err(dwc->dev, "failed to initialize host\n");
958d1a4c
FB		 168 } else {
169 if (dwc->usb2_phy)
170 otg_set_vbus(dwc->usb2_phy->otg, true);
644cbbc3
MG		 171 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
172 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
f580170f
YC		 173 if (dwc->dis_split_quirk) {
174 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
175 reg |= DWC3_GUCTL3_SPLITDISABLE;
176 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
177 }
958d1a4c 178 }
41ce1456
RQ		 179 break;
180 case DWC3_GCTL_PRTCAP_DEVICE:
181 dwc3_event_buffers_setup(dwc);
958d1a4c
FB		 182
183 if (dwc->usb2_phy)
184 otg_set_vbus(dwc->usb2_phy->otg, false);
644cbbc3
MG		 185 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
186 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
958d1a4c 187
41ce1456
RQ		 188 ret = dwc3_gadget_init(dwc);
189 if (ret)
190 dev_err(dwc->dev, "failed to initialize peripheral\n");
191 break;
f09cc79b
RQ		 192 case DWC3_GCTL_PRTCAP_OTG:
193 dwc3_otg_init(dwc);
194 dwc3_otg_update(dwc, 0);
195 break;
41ce1456
RQ		 196 default:
197 break;
198 }
f09cc79b 199
c2cd3452
MK		 200out:
201 pm_runtime_mark_last_busy(dwc->dev);
202 pm_runtime_put_autosuspend(dwc->dev);
41ce1456
RQ		 203}
204
205void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
206{
207 unsigned long flags;
208
dc336b19
LJ		 209 if (dwc->dr_mode != USB_DR_MODE_OTG)
210 return;
211
41ce1456
RQ		 212 spin_lock_irqsave(&dwc->lock, flags);
213 dwc->desired_dr_role = mode;
214 spin_unlock_irqrestore(&dwc->lock, flags);
215
084a804e 216 queue_work(system_freezable_wq, &dwc->drd_work);
3140e8cb 217}
8300dd23 218
cf6d867d
FB		 219u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
220{
221 struct dwc3 *dwc = dep->dwc;
222 u32 reg;
223
224 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
225 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
226 DWC3_GDBGFIFOSPACE_TYPE(type));
227
228 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
229
230 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
231}
232
72246da4
FB		 233/**
234 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
235 * @dwc: pointer to our context structure
236 */
57303488 237static int dwc3_core_soft_reset(struct dwc3 *dwc)
72246da4
FB		 238{
239 u32 reg;
f59dcab1 240 int retries = 1000;
57303488 241 int ret;
72246da4 242
51e1e7bc
FB		 243 usb_phy_init(dwc->usb2_phy);
244 usb_phy_init(dwc->usb3_phy);
57303488
KVA		 245 ret = phy_init(dwc->usb2_generic_phy);
246 if (ret < 0)
247 return ret;
248
249 ret = phy_init(dwc->usb3_generic_phy);
250 if (ret < 0) {
251 phy_exit(dwc->usb2_generic_phy);
252 return ret;
253 }
72246da4 254
f59dcab1
FB		 255 /*
256 * We're resetting only the device side because, if we're in host mode,
257 * XHCI driver will reset the host block. If dwc3 was configured for
258 * host-only mode, then we can return early.
259 */
c4a5153e 260 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
f59dcab1 261 return 0;
72246da4 262
f59dcab1
FB		 263 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
264 reg |= DWC3_DCTL_CSFTRST;
265 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 266
4749e0e6
TN		 267 /*
268 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
269 * is cleared only after all the clocks are synchronized. This can
270 * take a little more than 50ms. Set the polling rate at 20ms
271 * for 10 times instead.
272 */
9af21dd6 273 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
4749e0e6
TN		 274 retries = 10;
275
f59dcab1
FB		 276 do {
277 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
278 if (!(reg & DWC3_DCTL_CSFTRST))
fab38333 279 goto done;
45627ac6 280
9af21dd6 281 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
4749e0e6
TN		 282 msleep(20);
283 else
284 udelay(1);
f59dcab1 285 } while (--retries);
57303488 286
00b42170
BN		 287 phy_exit(dwc->usb3_generic_phy);
288 phy_exit(dwc->usb2_generic_phy);
289
f59dcab1 290 return -ETIMEDOUT;
fab38333
TN		 291
292done:
293 /*
4749e0e6
TN		 294 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
295 * is cleared, we must wait at least 50ms before accessing the PHY
296 * domain (synchronization delay).
fab38333 297 */
9af21dd6 298 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
fab38333
TN		 299 msleep(50);
300
301 return 0;
72246da4
FB		 302}
303
db2be4e9
NB		 304/*
305 * dwc3_frame_length_adjustment - Adjusts frame length if required
306 * @dwc3: Pointer to our controller context structure
db2be4e9 307 */
bcdb3272 308static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
db2be4e9
NB		 309{
310 u32 reg;
311 u32 dft;
312
9af21dd6 313 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
db2be4e9
NB		 314 return;
315
bcdb3272 316 if (dwc->fladj == 0)
db2be4e9
NB		 317 return;
318
319 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
320 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
a7d9874c 321 if (dft != dwc->fladj) {
db2be4e9 322 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
bcdb3272 323 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
db2be4e9
NB		 324 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
325 }
326}
327
72246da4
FB		 328/**
329 * dwc3_free_one_event_buffer - Frees one event buffer
330 * @dwc: Pointer to our controller context structure
331 * @evt: Pointer to event buffer to be freed
332 */
333static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
334 struct dwc3_event_buffer *evt)
335{
d64ff406 336 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
72246da4
FB		 337}
338
339/**
1d046793 340 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
72246da4
FB		 341 * @dwc: Pointer to our controller context structure
342 * @length: size of the event buffer
343 *
1d046793 344 * Returns a pointer to the allocated event buffer structure on success
72246da4
FB		 345 * otherwise ERR_PTR(errno).
346 */
67d0b500
FB		 347static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
348 unsigned length)
72246da4
FB		 349{
350 struct dwc3_event_buffer *evt;
351
380f0d28 352 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
72246da4
FB		 353 if (!evt)
354 return ERR_PTR(-ENOMEM);
355
356 evt->dwc = dwc;
357 evt->length = length;
d9fa4c63
JY		 358 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
359 if (!evt->cache)
360 return ERR_PTR(-ENOMEM);
361
d64ff406 362 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
72246da4 363 &evt->dma, GFP_KERNEL);
e32672f0 364 if (!evt->buf)
72246da4 365 return ERR_PTR(-ENOMEM);
72246da4
FB		 366
367 return evt;
368}
369
370/**
371 * dwc3_free_event_buffers - frees all allocated event buffers
372 * @dwc: Pointer to our controller context structure
373 */
374static void dwc3_free_event_buffers(struct dwc3 *dwc)
375{
376 struct dwc3_event_buffer *evt;
72246da4 377
696c8b12 378 evt = dwc->ev_buf;
660e9bde
FB		 379 if (evt)
380 dwc3_free_one_event_buffer(dwc, evt);
72246da4
FB		 381}
382
383/**
384 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
1d046793 385 * @dwc: pointer to our controller context structure
72246da4
FB		 386 * @length: size of event buffer
387 *
1d046793 388 * Returns 0 on success otherwise negative errno. In the error case, dwc
72246da4
FB		 389 * may contain some buffers allocated but not all which were requested.
390 */
41ac7b3a 391static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
72246da4 392{
660e9bde 393 struct dwc3_event_buffer *evt;
72246da4 394
660e9bde
FB		 395 evt = dwc3_alloc_one_event_buffer(dwc, length);
396 if (IS_ERR(evt)) {
397 dev_err(dwc->dev, "can't allocate event buffer\n");
398 return PTR_ERR(evt);
72246da4 399 }
696c8b12 400 dwc->ev_buf = evt;
72246da4
FB		 401
402 return 0;
403}
404
405/**
406 * dwc3_event_buffers_setup - setup our allocated event buffers
1d046793 407 * @dwc: pointer to our controller context structure
72246da4
FB		 408 *
409 * Returns 0 on success otherwise negative errno.
410 */
f09cc79b 411int dwc3_event_buffers_setup(struct dwc3 *dwc)
72246da4
FB		 412{
413 struct dwc3_event_buffer *evt;
72246da4 414
696c8b12 415 evt = dwc->ev_buf;
660e9bde 416 evt->lpos = 0;
660e9bde
FB		 417 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
418 lower_32_bits(evt->dma));
419 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
420 upper_32_bits(evt->dma));
421 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
422 DWC3_GEVNTSIZ_SIZE(evt->length));
423 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 424
425 return 0;
426}
427
f09cc79b 428void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
72246da4
FB		 429{
430 struct dwc3_event_buffer *evt;
72246da4 431
696c8b12 432 evt = dwc->ev_buf;
7acd85e0 433
660e9bde 434 evt->lpos = 0;
7acd85e0 435
660e9bde
FB		 436 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
437 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
438 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
439 | DWC3_GEVNTSIZ_SIZE(0));
440 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 441}
442
0ffcaf37
FB		 443static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
444{
445 if (!dwc->has_hibernation)
446 return 0;
447
448 if (!dwc->nr_scratch)
449 return 0;
450
451 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
452 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
453 if (!dwc->scratchbuf)
454 return -ENOMEM;
455
456 return 0;
457}
458
459static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
460{
461 dma_addr_t scratch_addr;
462 u32 param;
463 int ret;
464
465 if (!dwc->has_hibernation)
466 return 0;
467
468 if (!dwc->nr_scratch)
469 return 0;
470
471 /* should never fall here */
472 if (!WARN_ON(dwc->scratchbuf))
473 return 0;
474
d64ff406 475 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
0ffcaf37
FB		 476 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
477 DMA_BIDIRECTIONAL);
d64ff406
AB		 478 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
479 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
0ffcaf37
FB		 480 ret = -EFAULT;
481 goto err0;
482 }
483
484 dwc->scratch_addr = scratch_addr;
485
486 param = lower_32_bits(scratch_addr);
487
488 ret = dwc3_send_gadget_generic_command(dwc,
489 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
490 if (ret < 0)
491 goto err1;
492
493 param = upper_32_bits(scratch_addr);
494
495 ret = dwc3_send_gadget_generic_command(dwc,
496 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
497 if (ret < 0)
498 goto err1;
499
500 return 0;
501
502err1:
d64ff406 503 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
0ffcaf37
FB		 504 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
505
506err0:
507 return ret;
508}
509
510static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
511{
512 if (!dwc->has_hibernation)
513 return;
514
515 if (!dwc->nr_scratch)
516 return;
517
518 /* should never fall here */
519 if (!WARN_ON(dwc->scratchbuf))
520 return;
521
d64ff406 522 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
0ffcaf37
FB		 523 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
524 kfree(dwc->scratchbuf);
525}
526
789451f6
FB		 527static void dwc3_core_num_eps(struct dwc3 *dwc)
528{
529 struct dwc3_hwparams *parms = &dwc->hwparams;
530
47d3946e 531 dwc->num_eps = DWC3_NUM_EPS(parms);
789451f6
FB		 532}
533
41ac7b3a 534static void dwc3_cache_hwparams(struct dwc3 *dwc)
26ceca97
FB		 535{
536 struct dwc3_hwparams *parms = &dwc->hwparams;
537
538 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
539 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
540 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
541 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
542 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
543 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
544 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
545 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
546 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
547}
548
98112041
RQ		 549static int dwc3_core_ulpi_init(struct dwc3 *dwc)
550{
551 int intf;
552 int ret = 0;
553
554 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
555
556 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
557 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
558 dwc->hsphy_interface &&
559 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
560 ret = dwc3_ulpi_init(dwc);
561
562 return ret;
563}
564
b5a65c40
HR		 565/**
566 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
567 * @dwc: Pointer to our controller context structure
88bc9d19
HK		 568 *
569 * Returns 0 on success. The USB PHY interfaces are configured but not
570 * initialized. The PHY interfaces and the PHYs get initialized together with
571 * the core in dwc3_core_init.
b5a65c40 572 */
88bc9d19 573static int dwc3_phy_setup(struct dwc3 *dwc)
b5a65c40 574{
9ba3aca8 575 unsigned int hw_mode;
b5a65c40
HR		 576 u32 reg;
577
9ba3aca8
TN		 578 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
579
b5a65c40
HR		 580 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
581
1966b865
FB		 582 /*
583 * Make sure UX_EXIT_PX is cleared as that causes issues with some
584 * PHYs. Also, this bit is not supposed to be used in normal operation.
585 */
586 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
587
2164a476
HR		 588 /*
589 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
590 * to '0' during coreConsultant configuration. So default value
591 * will be '0' when the core is reset. Application needs to set it
592 * to '1' after the core initialization is completed.
593 */
9af21dd6 594 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
2164a476
HR		 595 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
596
9ba3aca8
TN		 597 /*
598 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
599 * power-on reset, and it can be set after core initialization, which is
600 * after device soft-reset during initialization.
601 */
602 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
603 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
604
b5a65c40
HR		 605 if (dwc->u2ss_inp3_quirk)
606 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
607
e58dd357
RB		 608 if (dwc->dis_rxdet_inp3_quirk)
609 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
610
df31f5b3
HR		 611 if (dwc->req_p1p2p3_quirk)
612 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
613
a2a1d0f5
HR		 614 if (dwc->del_p1p2p3_quirk)
615 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
616
41c06ffd
HR		 617 if (dwc->del_phy_power_chg_quirk)
618 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
619
fb67afca
HR		 620 if (dwc->lfps_filter_quirk)
621 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
622
14f4ac53
HR		 623 if (dwc->rx_detect_poll_quirk)
624 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
625
6b6a0c9a
HR		 626 if (dwc->tx_de_emphasis_quirk)
627 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
628
cd72f890 629 if (dwc->dis_u3_susphy_quirk)
59acfa20
HR		 630 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
631
00fe081d
WW		 632 if (dwc->dis_del_phy_power_chg_quirk)
633 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
634
b5a65c40
HR		 635 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
636
2164a476
HR		 637 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
638
3e10a2ce
HK		 639 /* Select the HS PHY interface */
640 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
641 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
43cacb03
FB		 642 if (dwc->hsphy_interface &&
643 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
3e10a2ce 644 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 645 break;
43cacb03
FB		 646 } else if (dwc->hsphy_interface &&
647 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
3e10a2ce 648 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 649 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
3e10a2ce 650 } else {
88bc9d19
HK		 651 /* Relying on default value. */
652 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
653 break;
3e10a2ce 654 }
df561f66 655 fallthrough;
88bc9d19 656 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
3e10a2ce
HK		 657 default:
658 break;
659 }
660
32f2ed86
WW		 661 switch (dwc->hsphy_mode) {
662 case USBPHY_INTERFACE_MODE_UTMI:
663 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
664 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
665 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
666 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
667 break;
668 case USBPHY_INTERFACE_MODE_UTMIW:
669 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
670 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
671 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
672 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
673 break;
674 default:
675 break;
676 }
677
2164a476
HR		 678 /*
679 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
680 * '0' during coreConsultant configuration. So default value will
681 * be '0' when the core is reset. Application needs to set it to
682 * '1' after the core initialization is completed.
683 */
9af21dd6 684 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
2164a476
HR		 685 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
686
9ba3aca8
TN		 687 /*
688 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
689 * power-on reset, and it can be set after core initialization, which is
690 * after device soft-reset during initialization.
691 */
692 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
693 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
694
cd72f890 695 if (dwc->dis_u2_susphy_quirk)
0effe0a3
HR		 696 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
697
ec791d14
JY		 698 if (dwc->dis_enblslpm_quirk)
699 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
eafeacf1
TN		 700 else
701 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
ec791d14 702
16199f33
WW		 703 if (dwc->dis_u2_freeclk_exists_quirk)
704 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
705
2164a476 706 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
88bc9d19
HK		 707
708 return 0;
b5a65c40
HR		 709}
710
c499ff71
FB		 711static void dwc3_core_exit(struct dwc3 *dwc)
712{
713 dwc3_event_buffers_cleanup(dwc);
714
715 usb_phy_shutdown(dwc->usb2_phy);
716 usb_phy_shutdown(dwc->usb3_phy);
717 phy_exit(dwc->usb2_generic_phy);
718 phy_exit(dwc->usb3_generic_phy);
719
720 usb_phy_set_suspend(dwc->usb2_phy, 1);
721 usb_phy_set_suspend(dwc->usb3_phy, 1);
722 phy_power_off(dwc->usb2_generic_phy);
723 phy_power_off(dwc->usb3_generic_phy);
240b65dc 724 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
fe8abf33 725 reset_control_assert(dwc->reset);
c499ff71
FB		 726}
727
0759956f 728static bool dwc3_core_is_valid(struct dwc3 *dwc)
72246da4 729{
0759956f 730 u32 reg;
72246da4 731
7650bd74 732 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
9af21dd6 733 dwc->ip = DWC3_GSNPS_ID(reg);
0759956f 734
7650bd74 735 /* This should read as U3 followed by revision number */
9af21dd6 736 if (DWC3_IP_IS(DWC3)) {
690fb371 737 dwc->revision = reg;
9af21dd6 738 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
690fb371 739 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
475d8e01 740 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
690fb371 741 } else {
0759956f 742 return false;
7650bd74 743 }
7650bd74 744
0759956f
FB		 745 return true;
746}
58a0f23f 747
941f918e 748static void dwc3_core_setup_global_control(struct dwc3 *dwc)
0759956f 749{
941f918e
FB		 750 u32 hwparams4 = dwc->hwparams.hwparams4;
751 u32 reg;
c499ff71 752
4878a028 753 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
3e87c42a 754 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
4878a028 755
164d7731 756 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
4878a028 757 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
32a4a135
FB		 758 /**
759 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
760 * issue which would cause xHCI compliance tests to fail.
761 *
762 * Because of that we cannot enable clock gating on such
763 * configurations.
764 *
765 * Refers to:
766 *
767 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
768 * SOF/ITP Mode Used
769 */
770 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
771 dwc->dr_mode == USB_DR_MODE_OTG) &&
9af21dd6 772 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
32a4a135
FB		 773 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
774 else
775 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
4878a028 776 break;
0ffcaf37
FB		 777 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
778 /* enable hibernation here */
779 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
2eac3992
HR		 780
781 /*
782 * REVISIT Enabling this bit so that host-mode hibernation
783 * will work. Device-mode hibernation is not yet implemented.
784 */
785 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
0ffcaf37 786 break;
4878a028 787 default:
5eb30ced
FB		 788 /* nothing */
789 break;
4878a028
SAS		 790 }
791
946bd579
HR		 792 /* check if current dwc3 is on simulation board */
793 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
6af19fd1 794 dev_info(dwc->dev, "Running with FPGA optimizations\n");
946bd579
HR		 795 dwc->is_fpga = true;
796 }
797
3b81221a
HR		 798 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
799 "disable_scramble cannot be used on non-FPGA builds\n");
800
801 if (dwc->disable_scramble_quirk && dwc->is_fpga)
802 reg |= DWC3_GCTL_DISSCRAMBLE;
803 else
804 reg &= ~DWC3_GCTL_DISSCRAMBLE;
805
9a5b2f31
HR		 806 if (dwc->u2exit_lfps_quirk)
807 reg |= DWC3_GCTL_U2EXIT_LFPS;
808
4878a028
SAS		 809 /*
810 * WORKAROUND: DWC3 revisions <1.90a have a bug
1d046793 811 * where the device can fail to connect at SuperSpeed
4878a028 812 * and falls back to high-speed mode which causes
1d046793 813 * the device to enter a Connect/Disconnect loop
4878a028 814 */
9af21dd6 815 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
4878a028
SAS		 816 reg |= DWC3_GCTL_U2RSTECN;
817
818 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
941f918e
FB		 819}
820
f54edb53 821static int dwc3_core_get_phy(struct dwc3 *dwc);
98112041 822static int dwc3_core_ulpi_init(struct dwc3 *dwc);
f54edb53 823
d9612c2f
PM		 824/* set global incr burst type configuration registers */
825static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
826{
827 struct device *dev = dwc->dev;
828 /* incrx_mode : for INCR burst type. */
829 bool incrx_mode;
830 /* incrx_size : for size of INCRX burst. */
831 u32 incrx_size;
832 u32 *vals;
833 u32 cfg;
834 int ntype;
835 int ret;
836 int i;
837
838 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
839
840 /*
841 * Handle property "snps,incr-burst-type-adjustment".
842 * Get the number of value from this property:
843 * result <= 0, means this property is not supported.
844 * result = 1, means INCRx burst mode supported.
845 * result > 1, means undefined length burst mode supported.
846 */
a6e5e679 847 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
d9612c2f
PM		 848 if (ntype <= 0)
849 return;
850
851 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
852 if (!vals) {
853 dev_err(dev, "Error to get memory\n");
854 return;
855 }
856
857 /* Get INCR burst type, and parse it */
858 ret = device_property_read_u32_array(dev,
859 "snps,incr-burst-type-adjustment", vals, ntype);
860 if (ret) {
75ecb9dd 861 kfree(vals);
d9612c2f
PM		 862 dev_err(dev, "Error to get property\n");
863 return;
864 }
865
866 incrx_size = *vals;
867
868 if (ntype > 1) {
869 /* INCRX (undefined length) burst mode */
870 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
871 for (i = 1; i < ntype; i++) {
872 if (vals[i] > incrx_size)
873 incrx_size = vals[i];
874 }
875 } else {
876 /* INCRX burst mode */
877 incrx_mode = INCRX_BURST_MODE;
878 }
879
75ecb9dd
AS		 880 kfree(vals);
881
d9612c2f
PM		 882 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
883 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
884 if (incrx_mode)
885 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
886 switch (incrx_size) {
887 case 256:
888 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
889 break;
890 case 128:
891 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
892 break;
893 case 64:
894 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
895 break;
896 case 32:
897 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
898 break;
899 case 16:
900 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
901 break;
902 case 8:
903 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
904 break;
905 case 4:
906 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
907 break;
908 case 1:
909 break;
910 default:
911 dev_err(dev, "Invalid property\n");
912 break;
913 }
914
915 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
916}
917
941f918e
FB		 918/**
919 * dwc3_core_init - Low-level initialization of DWC3 Core
920 * @dwc: Pointer to our controller context structure
921 *
922 * Returns 0 on success otherwise negative errno.
923 */
924static int dwc3_core_init(struct dwc3 *dwc)
925{
9ba3aca8 926 unsigned int hw_mode;
941f918e
FB		 927 u32 reg;
928 int ret;
929
9ba3aca8
TN		 930 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
931
941f918e
FB		 932 /*
933 * Write Linux Version Code to our GUID register so it's easy to figure
934 * out which kernel version a bug was found.
935 */
936 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
937
98112041 938 ret = dwc3_phy_setup(dwc);
941f918e
FB		 939 if (ret)
940 goto err0;
4878a028 941
98112041
RQ		 942 if (!dwc->ulpi_ready) {
943 ret = dwc3_core_ulpi_init(dwc);
944 if (ret)
945 goto err0;
946 dwc->ulpi_ready = true;
947 }
4878a028 948
98112041
RQ		 949 if (!dwc->phys_ready) {
950 ret = dwc3_core_get_phy(dwc);
951 if (ret)
952 goto err0a;
953 dwc->phys_ready = true;
954 }
955
956 ret = dwc3_core_soft_reset(dwc);
f54edb53 957 if (ret)
98112041 958 goto err0a;
f54edb53 959
9ba3aca8 960 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
9af21dd6 961 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
9ba3aca8
TN		 962 if (!dwc->dis_u3_susphy_quirk) {
963 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
964 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
965 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
966 }
967
968 if (!dwc->dis_u2_susphy_quirk) {
969 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
970 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
971 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
972 }
973 }
974
941f918e 975 dwc3_core_setup_global_control(dwc);
c499ff71 976 dwc3_core_num_eps(dwc);
0ffcaf37
FB		 977
978 ret = dwc3_setup_scratch_buffers(dwc);
979 if (ret)
c499ff71
FB		 980 goto err1;
981
982 /* Adjust Frame Length */
983 dwc3_frame_length_adjustment(dwc);
984
d9612c2f
PM		 985 dwc3_set_incr_burst_type(dwc);
986
c499ff71
FB		 987 usb_phy_set_suspend(dwc->usb2_phy, 0);
988 usb_phy_set_suspend(dwc->usb3_phy, 0);
989 ret = phy_power_on(dwc->usb2_generic_phy);
990 if (ret < 0)
0ffcaf37
FB		 991 goto err2;
992
c499ff71
FB		 993 ret = phy_power_on(dwc->usb3_generic_phy);
994 if (ret < 0)
995 goto err3;
996
997 ret = dwc3_event_buffers_setup(dwc);
998 if (ret) {
999 dev_err(dwc->dev, "failed to setup event buffers\n");
1000 goto err4;
1001 }
1002
06281d46
JY		 1003 /*
1004 * ENDXFER polling is available on version 3.10a and later of
1005 * the DWC_usb3 controller. It is NOT available in the
1006 * DWC_usb31 controller.
1007 */
9af21dd6 1008 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
06281d46
JY		 1009 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1010 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1011 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1012 }
1013
9af21dd6 1014 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
0bb39ca1 1015 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
65db7a0c
WW		 1016
1017 /*
1018 * Enable hardware control of sending remote wakeup
1019 * in HS when the device is in the L1 state.
1020 */
9af21dd6 1021 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
65db7a0c
WW		 1022 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1023
1024 if (dwc->dis_tx_ipgap_linecheck_quirk)
1025 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1026
7ba6b09f
NA		 1027 if (dwc->parkmode_disable_ss_quirk)
1028 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1029
0bb39ca1
JY		 1030 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1031 }
1032
b138e23d
AKV		 1033 if (dwc->dr_mode == USB_DR_MODE_HOST ||
1034 dwc->dr_mode == USB_DR_MODE_OTG) {
1035 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1036
1037 /*
1038 * Enable Auto retry Feature to make the controller operating in
1039 * Host mode on seeing transaction errors(CRC errors or internal
1040 * overrun scenerios) on IN transfers to reply to the device
1041 * with a non-terminating retry ACK (i.e, an ACK transcation
1042 * packet with Retry=1 & Nump != 0)
1043 */
1044 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1045
1046 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1047 }
1048
938a5ad1
TN		 1049 /*
1050 * Must config both number of packets and max burst settings to enable
1051 * RX and/or TX threshold.
1052 */
9af21dd6 1053 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
938a5ad1
TN		 1054 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1055 u8 rx_maxburst = dwc->rx_max_burst_prd;
1056 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1057 u8 tx_maxburst = dwc->tx_max_burst_prd;
1058
1059 if (rx_thr_num && rx_maxburst) {
1060 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1061 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1062
1063 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1064 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1065
1066 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1067 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1068
1069 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1070 }
1071
1072 if (tx_thr_num && tx_maxburst) {
1073 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1074 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1075
1076 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1077 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1078
1079 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1080 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1081
1082 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1083 }
1084 }
1085
72246da4
FB		 1086 return 0;
1087
c499ff71 1088err4:
9b9d7cdd 1089 phy_power_off(dwc->usb3_generic_phy);
c499ff71
FB		 1090
1091err3:
9b9d7cdd 1092 phy_power_off(dwc->usb2_generic_phy);
c499ff71 1093
0ffcaf37 1094err2:
c499ff71
FB		 1095 usb_phy_set_suspend(dwc->usb2_phy, 1);
1096 usb_phy_set_suspend(dwc->usb3_phy, 1);
0ffcaf37
FB		 1097
1098err1:
1099 usb_phy_shutdown(dwc->usb2_phy);
1100 usb_phy_shutdown(dwc->usb3_phy);
57303488
KVA		 1101 phy_exit(dwc->usb2_generic_phy);
1102 phy_exit(dwc->usb3_generic_phy);
0ffcaf37 1103
98112041
RQ		 1104err0a:
1105 dwc3_ulpi_exit(dwc);
1106
72246da4
FB		 1107err0:
1108 return ret;
1109}
1110
3c9f94ac 1111static int dwc3_core_get_phy(struct dwc3 *dwc)
72246da4 1112{
3c9f94ac 1113 struct device *dev = dwc->dev;
941ea361 1114 struct device_node *node = dev->of_node;
3c9f94ac 1115 int ret;
72246da4 1116
5088b6f5
KVA		 1117 if (node) {
1118 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1119 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
bb674907
FB		 1120 } else {
1121 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1122 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
5088b6f5
KVA		 1123 }
1124
d105e7f8
FB		 1125 if (IS_ERR(dwc->usb2_phy)) {
1126 ret = PTR_ERR(dwc->usb2_phy);
122f06e6
KVA		 1127 if (ret == -ENXIO || ret == -ENODEV) {
1128 dwc->usb2_phy = NULL;
122f06e6 1129 } else {
0c0a20f6 1130 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
122f06e6 1131 }
51e1e7bc
FB		 1132 }
1133
d105e7f8 1134 if (IS_ERR(dwc->usb3_phy)) {
315955d7 1135 ret = PTR_ERR(dwc->usb3_phy);
122f06e6
KVA		 1136 if (ret == -ENXIO || ret == -ENODEV) {
1137 dwc->usb3_phy = NULL;
122f06e6 1138 } else {
0c0a20f6 1139 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
122f06e6 1140 }
51e1e7bc
FB		 1141 }
1142
57303488
KVA		 1143 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1144 if (IS_ERR(dwc->usb2_generic_phy)) {
1145 ret = PTR_ERR(dwc->usb2_generic_phy);
1146 if (ret == -ENOSYS || ret == -ENODEV) {
1147 dwc->usb2_generic_phy = NULL;
57303488 1148 } else {
0c0a20f6 1149 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
57303488
KVA		 1150 }
1151 }
1152
1153 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1154 if (IS_ERR(dwc->usb3_generic_phy)) {
1155 ret = PTR_ERR(dwc->usb3_generic_phy);
1156 if (ret == -ENOSYS || ret == -ENODEV) {
1157 dwc->usb3_generic_phy = NULL;
57303488 1158 } else {
0c0a20f6 1159 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
57303488
KVA		 1160 }
1161 }
1162
3c9f94ac
FB		 1163 return 0;
1164}
1165
5f94adfe
FB		 1166static int dwc3_core_init_mode(struct dwc3 *dwc)
1167{
1168 struct device *dev = dwc->dev;
1169 int ret;
1170
1171 switch (dwc->dr_mode) {
1172 case USB_DR_MODE_PERIPHERAL:
41ce1456 1173 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
958d1a4c
FB		 1174
1175 if (dwc->usb2_phy)
1176 otg_set_vbus(dwc->usb2_phy->otg, false);
644cbbc3
MG		 1177 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1178 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
958d1a4c 1179
5f94adfe 1180 ret = dwc3_gadget_init(dwc);
0c0a20f6
AS		 1181 if (ret)
1182 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
5f94adfe
FB		 1183 break;
1184 case USB_DR_MODE_HOST:
41ce1456 1185 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
958d1a4c
FB		 1186
1187 if (dwc->usb2_phy)
1188 otg_set_vbus(dwc->usb2_phy->otg, true);
644cbbc3
MG		 1189 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1190 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
958d1a4c 1191
5f94adfe 1192 ret = dwc3_host_init(dwc);
0c0a20f6
AS		 1193 if (ret)
1194 return dev_err_probe(dev, ret, "failed to initialize host\n");
5f94adfe
FB		 1195 break;
1196 case USB_DR_MODE_OTG:
41ce1456 1197 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
9840354f 1198 ret = dwc3_drd_init(dwc);
0c0a20f6
AS		 1199 if (ret)
1200 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
5f94adfe
FB		 1201 break;
1202 default:
1203 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1204 return -EINVAL;
1205 }
1206
1207 return 0;
1208}
1209
1210static void dwc3_core_exit_mode(struct dwc3 *dwc)
1211{
1212 switch (dwc->dr_mode) {
1213 case USB_DR_MODE_PERIPHERAL:
1214 dwc3_gadget_exit(dwc);
1215 break;
1216 case USB_DR_MODE_HOST:
1217 dwc3_host_exit(dwc);
1218 break;
1219 case USB_DR_MODE_OTG:
9840354f 1220 dwc3_drd_exit(dwc);
5f94adfe
FB		 1221 break;
1222 default:
1223 /* do nothing */
1224 break;
1225 }
09ed259f
BL		 1226
1227 /* de-assert DRVVBUS for HOST and OTG mode */
1228 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
5f94adfe
FB		 1229}
1230
c5ac6116 1231static void dwc3_get_properties(struct dwc3 *dwc)
3c9f94ac 1232{
c5ac6116 1233 struct device *dev = dwc->dev;
80caf7d2 1234 u8 lpm_nyet_threshold;
6b6a0c9a 1235 u8 tx_de_emphasis;
460d098c 1236 u8 hird_threshold;
938a5ad1
TN		 1237 u8 rx_thr_num_pkt_prd;
1238 u8 rx_max_burst_prd;
1239 u8 tx_thr_num_pkt_prd;
1240 u8 tx_max_burst_prd;
3c9f94ac 1241
80caf7d2 1242 /* default to highest possible threshold */
8d791929 1243 lpm_nyet_threshold = 0xf;
80caf7d2 1244
6b6a0c9a
HR		 1245 /* default to -3.5dB de-emphasis */
1246 tx_de_emphasis = 1;
1247
460d098c
HR		 1248 /*
1249 * default to assert utmi_sleep_n and use maximum allowed HIRD
1250 * threshold value of 0b1100
1251 */
1252 hird_threshold = 12;
1253
63863b98 1254 dwc->maximum_speed = usb_get_maximum_speed(dev);
67848146 1255 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
06e7114f 1256 dwc->dr_mode = usb_get_dr_mode(dev);
32f2ed86 1257 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
63863b98 1258
d64ff406
AB		 1259 dwc->sysdev_is_parent = device_property_read_bool(dev,
1260 "linux,sysdev_is_parent");
1261 if (dwc->sysdev_is_parent)
1262 dwc->sysdev = dwc->dev->parent;
1263 else
1264 dwc->sysdev = dwc->dev;
1265
3d128919 1266 dwc->has_lpm_erratum = device_property_read_bool(dev,
80caf7d2 1267 "snps,has-lpm-erratum");
3d128919 1268 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
80caf7d2 1269 &lpm_nyet_threshold);
3d128919 1270 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
460d098c 1271 "snps,is-utmi-l1-suspend");
3d128919 1272 device_property_read_u8(dev, "snps,hird-threshold",
460d098c 1273 &hird_threshold);
d92021f6
TN		 1274 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1275 "snps,dis-start-transfer-quirk");
3d128919 1276 dwc->usb3_lpm_capable = device_property_read_bool(dev,
eac68e8f 1277 "snps,usb3_lpm_capable");
022a0208
TN		 1278 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1279 "snps,usb2-lpm-disable");
938a5ad1
TN		 1280 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1281 &rx_thr_num_pkt_prd);
1282 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1283 &rx_max_burst_prd);
1284 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1285 &tx_thr_num_pkt_prd);
1286 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1287 &tx_max_burst_prd);
3c9f94ac 1288
3d128919 1289 dwc->disable_scramble_quirk = device_property_read_bool(dev,
3b81221a 1290 "snps,disable_scramble_quirk");
3d128919 1291 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
9a5b2f31 1292 "snps,u2exit_lfps_quirk");
3d128919 1293 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
b5a65c40 1294 "snps,u2ss_inp3_quirk");
3d128919 1295 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
df31f5b3 1296 "snps,req_p1p2p3_quirk");
3d128919 1297 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
a2a1d0f5 1298 "snps,del_p1p2p3_quirk");
3d128919 1299 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
41c06ffd 1300 "snps,del_phy_power_chg_quirk");
3d128919 1301 dwc->lfps_filter_quirk = device_property_read_bool(dev,
fb67afca 1302 "snps,lfps_filter_quirk");
3d128919 1303 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
14f4ac53 1304 "snps,rx_detect_poll_quirk");
3d128919 1305 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
59acfa20 1306 "snps,dis_u3_susphy_quirk");
3d128919 1307 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
0effe0a3 1308 "snps,dis_u2_susphy_quirk");
ec791d14
JY		 1309 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1310 "snps,dis_enblslpm_quirk");
729dcffd
AKV		 1311 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1312 "snps,dis-u1-entry-quirk");
1313 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1314 "snps,dis-u2-entry-quirk");
e58dd357
RB		 1315 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1316 "snps,dis_rxdet_inp3_quirk");
16199f33
WW		 1317 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1318 "snps,dis-u2-freeclk-exists-quirk");
00fe081d
WW		 1319 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1320 "snps,dis-del-phy-power-chg-quirk");
65db7a0c
WW		 1321 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1322 "snps,dis-tx-ipgap-linecheck-quirk");
7ba6b09f
NA		 1323 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1324 "snps,parkmode-disable-ss-quirk");
6b6a0c9a 1325
3d128919 1326 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
6b6a0c9a 1327 "snps,tx_de_emphasis_quirk");
3d128919 1328 device_property_read_u8(dev, "snps,tx_de_emphasis",
6b6a0c9a 1329 &tx_de_emphasis);
3d128919
HK		 1330 device_property_read_string(dev, "snps,hsphy_interface",
1331 &dwc->hsphy_interface);
1332 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
bcdb3272 1333 &dwc->fladj);
3d128919 1334
42bf02ec
RQ		 1335 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1336 "snps,dis_metastability_quirk");
1337
f580170f
YC		 1338 dwc->dis_split_quirk = device_property_read_bool(dev,
1339 "snps,dis-split-quirk");
1340
80caf7d2 1341 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
6b6a0c9a 1342 dwc->tx_de_emphasis = tx_de_emphasis;
80caf7d2 1343
16fe4f30 1344 dwc->hird_threshold = hird_threshold;
460d098c 1345
938a5ad1
TN		 1346 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1347 dwc->rx_max_burst_prd = rx_max_burst_prd;
1348
1349 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1350 dwc->tx_max_burst_prd = tx_max_burst_prd;
1351
cf40b86b
JY		 1352 dwc->imod_interval = 0;
1353}
1354
1355/* check whether the core supports IMOD */
1356bool dwc3_has_imod(struct dwc3 *dwc)
1357{
9af21dd6
TN		 1358 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1359 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1360 DWC3_IP_IS(DWC32);
c5ac6116
FB		 1361}
1362
7ac51a12
JY		 1363static void dwc3_check_params(struct dwc3 *dwc)
1364{
1365 struct device *dev = dwc->dev;
b574ce3e
TN		 1366 unsigned int hwparam_gen =
1367 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
7ac51a12 1368
cf40b86b
JY		 1369 /* Check for proper value of imod_interval */
1370 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1371 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1372 dwc->imod_interval = 0;
1373 }
1374
28632b44
JY		 1375 /*
1376 * Workaround for STAR 9000961433 which affects only version
1377 * 3.00a of the DWC_usb3 core. This prevents the controller
1378 * interrupt from being masked while handling events. IMOD
1379 * allows us to work around this issue. Enable it for the
1380 * affected version.
1381 */
1382 if (!dwc->imod_interval &&
9af21dd6 1383 DWC3_VER_IS(DWC3, 300A))
28632b44
JY		 1384 dwc->imod_interval = 1;
1385
7ac51a12
JY		 1386 /* Check the maximum_speed parameter */
1387 switch (dwc->maximum_speed) {
1388 case USB_SPEED_LOW:
1389 case USB_SPEED_FULL:
1390 case USB_SPEED_HIGH:
e518bdd9 1391 break;
7ac51a12 1392 case USB_SPEED_SUPER:
e518bdd9
TN		 1393 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1394 dev_warn(dev, "UDC doesn't support Gen 1\n");
1395 break;
7ac51a12 1396 case USB_SPEED_SUPER_PLUS:
e518bdd9
TN		 1397 if ((DWC3_IP_IS(DWC32) &&
1398 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1399 (!DWC3_IP_IS(DWC32) &&
1400 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1401 dev_warn(dev, "UDC doesn't support SSP\n");
7ac51a12
JY		 1402 break;
1403 default:
1404 dev_err(dev, "invalid maximum_speed parameter %d\n",
1405 dwc->maximum_speed);
df561f66 1406 fallthrough;
7ac51a12 1407 case USB_SPEED_UNKNOWN:
b574ce3e
TN		 1408 switch (hwparam_gen) {
1409 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
7ac51a12 1410 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
b574ce3e
TN		 1411 break;
1412 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1413 if (DWC3_IP_IS(DWC32))
1414 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1415 else
1416 dwc->maximum_speed = USB_SPEED_SUPER;
1417 break;
1418 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1419 dwc->maximum_speed = USB_SPEED_HIGH;
1420 break;
1421 default:
1422 dwc->maximum_speed = USB_SPEED_SUPER;
1423 break;
1424 }
7ac51a12
JY		 1425 break;
1426 }
67848146
TN		 1427
1428 /*
1429 * Currently the controller does not have visibility into the HW
1430 * parameter to determine the maximum number of lanes the HW supports.
1431 * If the number of lanes is not specified in the device property, then
1432 * set the default to support dual-lane for DWC_usb32 and single-lane
1433 * for DWC_usb31 for super-speed-plus.
1434 */
1435 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1436 switch (dwc->max_ssp_rate) {
1437 case USB_SSP_GEN_2x1:
1438 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1439 dev_warn(dev, "UDC only supports Gen 1\n");
1440 break;
1441 case USB_SSP_GEN_1x2:
1442 case USB_SSP_GEN_2x2:
1443 if (DWC3_IP_IS(DWC31))
1444 dev_warn(dev, "UDC only supports single lane\n");
1445 break;
1446 case USB_SSP_GEN_UNKNOWN:
1447 default:
1448 switch (hwparam_gen) {
1449 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1450 if (DWC3_IP_IS(DWC32))
1451 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1452 else
1453 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1454 break;
1455 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1456 if (DWC3_IP_IS(DWC32))
1457 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1458 break;
1459 }
1460 break;
1461 }
1462 }
7ac51a12
JY		 1463}
1464
c5ac6116
FB		 1465static int dwc3_probe(struct platform_device *pdev)
1466{
1467 struct device *dev = &pdev->dev;
44feb8e6 1468 struct resource *res, dwc_res;
c5ac6116
FB		 1469 struct dwc3 *dwc;
1470
1471 int ret;
1472
1473 void __iomem *regs;
1474
1475 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1476 if (!dwc)
1477 return -ENOMEM;
1478
1479 dwc->dev = dev;
1480
1481 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1482 if (!res) {
1483 dev_err(dev, "missing memory resource\n");
1484 return -ENODEV;
1485 }
1486
1487 dwc->xhci_resources[0].start = res->start;
1488 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1489 DWC3_XHCI_REGS_END;
1490 dwc->xhci_resources[0].flags = res->flags;
1491 dwc->xhci_resources[0].name = res->name;
1492
c5ac6116
FB		 1493 /*
1494 * Request memory region but exclude xHCI regs,
1495 * since it will be requested by the xhci-plat driver.
1496 */
44feb8e6
MY		 1497 dwc_res = *res;
1498 dwc_res.start += DWC3_GLOBALS_REGS_START;
1499
1500 regs = devm_ioremap_resource(dev, &dwc_res);
1501 if (IS_ERR(regs))
1502 return PTR_ERR(regs);
c5ac6116
FB		 1503
1504 dwc->regs = regs;
44feb8e6 1505 dwc->regs_size = resource_size(&dwc_res);
c5ac6116
FB		 1506
1507 dwc3_get_properties(dwc);
1508
babbdfc9 1509 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
fe8abf33
MY		 1510 if (IS_ERR(dwc->reset))
1511 return PTR_ERR(dwc->reset);
1512
61527777 1513 if (dev->of_node) {
0d3a9708 1514 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
61527777
HG		 1515 if (ret == -EPROBE_DEFER)
1516 return ret;
1517 /*
1518 * Clocks are optional, but new DT platforms should support all
1519 * clocks as required by the DT-binding.
1520 */
0d3a9708 1521 if (ret < 0)
61527777 1522 dwc->num_clks = 0;
0d3a9708
JS		 1523 else
1524 dwc->num_clks = ret;
1525
61527777 1526 }
fe8abf33
MY		 1527
1528 ret = reset_control_deassert(dwc->reset);
1529 if (ret)
03bf32bb 1530 return ret;
fe8abf33 1531
240b65dc 1532 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
fe8abf33
MY		 1533 if (ret)
1534 goto assert_reset;
1535
dc1b5d9a
EBS		 1536 if (!dwc3_core_is_valid(dwc)) {
1537 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1538 ret = -ENODEV;
1539 goto disable_clks;
1540 }
1541
6c89cce0 1542 platform_set_drvdata(pdev, dwc);
2917e718 1543 dwc3_cache_hwparams(dwc);
6c89cce0 1544
72246da4 1545 spin_lock_init(&dwc->lock);
72246da4 1546
fc8bb91b
FB		 1547 pm_runtime_set_active(dev);
1548 pm_runtime_use_autosuspend(dev);
1549 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
802ca850 1550 pm_runtime_enable(dev);
32808237
RQ		 1551 ret = pm_runtime_get_sync(dev);
1552 if (ret < 0)
1553 goto err1;
1554
802ca850 1555 pm_runtime_forbid(dev);
72246da4 1556
3921426b
FB		 1557 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1558 if (ret) {
1559 dev_err(dwc->dev, "failed to allocate event buffers\n");
1560 ret = -ENOMEM;
32808237 1561 goto err2;
3921426b
FB		 1562 }
1563
9d6173e1
TN		 1564 ret = dwc3_get_dr_mode(dwc);
1565 if (ret)
1566 goto err3;
32a4a135 1567
c499ff71
FB		 1568 ret = dwc3_alloc_scratch_buffers(dwc);
1569 if (ret)
32808237 1570 goto err3;
c499ff71 1571
72246da4
FB		 1572 ret = dwc3_core_init(dwc);
1573 if (ret) {
0c0a20f6 1574 dev_err_probe(dev, ret, "failed to initialize core\n");
32808237 1575 goto err4;
72246da4
FB		 1576 }
1577
7ac51a12 1578 dwc3_check_params(dwc);
2c7f1bd9 1579
5f94adfe
FB		 1580 ret = dwc3_core_init_mode(dwc);
1581 if (ret)
32808237 1582 goto err5;
72246da4 1583
4e9f3118 1584 dwc3_debugfs_init(dwc);
fc8bb91b 1585 pm_runtime_put(dev);
72246da4
FB		 1586
1587 return 0;
1588
32808237 1589err5:
c499ff71 1590 dwc3_event_buffers_cleanup(dwc);
03c1fd62
LJ		 1591
1592 usb_phy_shutdown(dwc->usb2_phy);
1593 usb_phy_shutdown(dwc->usb3_phy);
1594 phy_exit(dwc->usb2_generic_phy);
1595 phy_exit(dwc->usb3_generic_phy);
1596
1597 usb_phy_set_suspend(dwc->usb2_phy, 1);
1598 usb_phy_set_suspend(dwc->usb3_phy, 1);
1599 phy_power_off(dwc->usb2_generic_phy);
1600 phy_power_off(dwc->usb3_generic_phy);
1601
08fd9a82 1602 dwc3_ulpi_exit(dwc);
57303488 1603
32808237 1604err4:
c499ff71 1605 dwc3_free_scratch_buffers(dwc);
72246da4 1606
32808237 1607err3:
3921426b
FB		 1608 dwc3_free_event_buffers(dwc);
1609
32808237
RQ		 1610err2:
1611 pm_runtime_allow(&pdev->dev);
1612
1613err1:
1614 pm_runtime_put_sync(&pdev->dev);
1615 pm_runtime_disable(&pdev->dev);
1616
dc1b5d9a 1617disable_clks:
240b65dc 1618 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
fe8abf33
MY		 1619assert_reset:
1620 reset_control_assert(dwc->reset);
fe8abf33 1621
72246da4
FB		 1622 return ret;
1623}
1624
fb4e98ab 1625static int dwc3_remove(struct platform_device *pdev)
72246da4 1626{
72246da4 1627 struct dwc3 *dwc = platform_get_drvdata(pdev);
3da1f6ee 1628
fc8bb91b 1629 pm_runtime_get_sync(&pdev->dev);
72246da4 1630
dc99f16f
FB		 1631 dwc3_debugfs_exit(dwc);
1632 dwc3_core_exit_mode(dwc);
8ba007a9 1633
72246da4 1634 dwc3_core_exit(dwc);
88bc9d19 1635 dwc3_ulpi_exit(dwc);
72246da4 1636
72246da4 1637 pm_runtime_disable(&pdev->dev);
266d0493
LJ		 1638 pm_runtime_put_noidle(&pdev->dev);
1639 pm_runtime_set_suspended(&pdev->dev);
72246da4 1640
fc8bb91b
FB		 1641 dwc3_free_event_buffers(dwc);
1642 dwc3_free_scratch_buffers(dwc);
1643
72246da4
FB		 1644 return 0;
1645}
1646
fc8bb91b 1647#ifdef CONFIG_PM
fe8abf33
MY		 1648static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1649{
1650 int ret;
1651
1652 ret = reset_control_deassert(dwc->reset);
1653 if (ret)
1654 return ret;
1655
240b65dc 1656 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
fe8abf33
MY		 1657 if (ret)
1658 goto assert_reset;
1659
fe8abf33
MY		 1660 ret = dwc3_core_init(dwc);
1661 if (ret)
1662 goto disable_clks;
1663
1664 return 0;
1665
1666disable_clks:
240b65dc 1667 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
fe8abf33
MY		 1668assert_reset:
1669 reset_control_assert(dwc->reset);
1670
1671 return ret;
1672}
1673
c4a5153e 1674static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
7415f17c 1675{
fc8bb91b 1676 unsigned long flags;
bcb12877 1677 u32 reg;
7415f17c 1678
689bf72c
MG		 1679 switch (dwc->current_dr_role) {
1680 case DWC3_GCTL_PRTCAP_DEVICE:
0227cc84
LJ		 1681 if (pm_runtime_suspended(dwc->dev))
1682 break;
fc8bb91b 1683 spin_lock_irqsave(&dwc->lock, flags);
7415f17c 1684 dwc3_gadget_suspend(dwc);
fc8bb91b 1685 spin_unlock_irqrestore(&dwc->lock, flags);
41a91c60 1686 synchronize_irq(dwc->irq_gadget);
689bf72c 1687 dwc3_core_exit(dwc);
51f5d49a 1688 break;
689bf72c 1689 case DWC3_GCTL_PRTCAP_HOST:
bcb12877 1690 if (!PMSG_IS_AUTO(msg)) {
c4a5153e 1691 dwc3_core_exit(dwc);
bcb12877
MG		 1692 break;
1693 }
1694
1695 /* Let controller to suspend HSPHY before PHY driver suspends */
1696 if (dwc->dis_u2_susphy_quirk ||
1697 dwc->dis_enblslpm_quirk) {
1698 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1699 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1700 DWC3_GUSB2PHYCFG_SUSPHY;
1701 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1702
1703 /* Give some time for USB2 PHY to suspend */
1704 usleep_range(5000, 6000);
1705 }
1706
1707 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1708 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
c4a5153e 1709 break;
f09cc79b
RQ		 1710 case DWC3_GCTL_PRTCAP_OTG:
1711 /* do nothing during runtime_suspend */
1712 if (PMSG_IS_AUTO(msg))
1713 break;
1714
1715 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1716 spin_lock_irqsave(&dwc->lock, flags);
1717 dwc3_gadget_suspend(dwc);
1718 spin_unlock_irqrestore(&dwc->lock, flags);
41a91c60 1719 synchronize_irq(dwc->irq_gadget);
f09cc79b
RQ		 1720 }
1721
1722 dwc3_otg_exit(dwc);
1723 dwc3_core_exit(dwc);
1724 break;
7415f17c 1725 default:
51f5d49a 1726 /* do nothing */
7415f17c
FB		 1727 break;
1728 }
1729
7415f17c
FB		 1730 return 0;
1731}
1732
c4a5153e 1733static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
7415f17c 1734{
fc8bb91b 1735 unsigned long flags;
57303488 1736 int ret;
bcb12877 1737 u32 reg;
7415f17c 1738
689bf72c
MG		 1739 switch (dwc->current_dr_role) {
1740 case DWC3_GCTL_PRTCAP_DEVICE:
fe8abf33 1741 ret = dwc3_core_init_for_resume(dwc);
689bf72c
MG		 1742 if (ret)
1743 return ret;
5c4ad318 1744
7d11c3ac 1745 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
fc8bb91b 1746 spin_lock_irqsave(&dwc->lock, flags);
7415f17c 1747 dwc3_gadget_resume(dwc);
fc8bb91b 1748 spin_unlock_irqrestore(&dwc->lock, flags);
689bf72c
MG		 1749 break;
1750 case DWC3_GCTL_PRTCAP_HOST:
c4a5153e 1751 if (!PMSG_IS_AUTO(msg)) {
fe8abf33 1752 ret = dwc3_core_init_for_resume(dwc);
c4a5153e
MG		 1753 if (ret)
1754 return ret;
7d11c3ac 1755 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
bcb12877 1756 break;
c4a5153e 1757 }
bcb12877
MG		 1758 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1759 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1760 if (dwc->dis_u2_susphy_quirk)
1761 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1762
1763 if (dwc->dis_enblslpm_quirk)
1764 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1765
1766 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1767
1768 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1769 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
f09cc79b
RQ		 1770 break;
1771 case DWC3_GCTL_PRTCAP_OTG:
1772 /* nothing to do on runtime_resume */
1773 if (PMSG_IS_AUTO(msg))
1774 break;
1775
1776 ret = dwc3_core_init(dwc);
1777 if (ret)
1778 return ret;
1779
1780 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1781
1782 dwc3_otg_init(dwc);
1783 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1784 dwc3_otg_host_init(dwc);
1785 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1786 spin_lock_irqsave(&dwc->lock, flags);
1787 dwc3_gadget_resume(dwc);
1788 spin_unlock_irqrestore(&dwc->lock, flags);
c4a5153e 1789 }
f09cc79b 1790
c4a5153e 1791 break;
7415f17c
FB		 1792 default:
1793 /* do nothing */
1794 break;
1795 }
1796
fc8bb91b
FB		 1797 return 0;
1798}
1799
1800static int dwc3_runtime_checks(struct dwc3 *dwc)
1801{
689bf72c 1802 switch (dwc->current_dr_role) {
c4a5153e 1803 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 1804 if (dwc->connected)
1805 return -EBUSY;
1806 break;
c4a5153e 1807 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 1808 default:
1809 /* do nothing */
1810 break;
1811 }
1812
1813 return 0;
1814}
1815
1816static int dwc3_runtime_suspend(struct device *dev)
1817{
1818 struct dwc3 *dwc = dev_get_drvdata(dev);
1819 int ret;
1820
1821 if (dwc3_runtime_checks(dwc))
1822 return -EBUSY;
1823
c4a5153e 1824 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
fc8bb91b
FB		 1825 if (ret)
1826 return ret;
1827
1828 device_init_wakeup(dev, true);
1829
1830 return 0;
1831}
1832
1833static int dwc3_runtime_resume(struct device *dev)
1834{
1835 struct dwc3 *dwc = dev_get_drvdata(dev);
1836 int ret;
1837
1838 device_init_wakeup(dev, false);
1839
c4a5153e 1840 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
fc8bb91b
FB		 1841 if (ret)
1842 return ret;
1843
689bf72c
MG		 1844 switch (dwc->current_dr_role) {
1845 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 1846 dwc3_gadget_process_pending_events(dwc);
1847 break;
689bf72c 1848 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 1849 default:
1850 /* do nothing */
1851 break;
1852 }
1853
1854 pm_runtime_mark_last_busy(dev);
1855
1856 return 0;
1857}
1858
1859static int dwc3_runtime_idle(struct device *dev)
1860{
1861 struct dwc3 *dwc = dev_get_drvdata(dev);
1862
689bf72c
MG		 1863 switch (dwc->current_dr_role) {
1864 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 1865 if (dwc3_runtime_checks(dwc))
1866 return -EBUSY;
1867 break;
689bf72c 1868 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 1869 default:
1870 /* do nothing */
1871 break;
1872 }
1873
1874 pm_runtime_mark_last_busy(dev);
1875 pm_runtime_autosuspend(dev);
1876
1877 return 0;
1878}
1879#endif /* CONFIG_PM */
1880
1881#ifdef CONFIG_PM_SLEEP
1882static int dwc3_suspend(struct device *dev)
1883{
1884 struct dwc3 *dwc = dev_get_drvdata(dev);
1885 int ret;
1886
c4a5153e 1887 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
fc8bb91b
FB		 1888 if (ret)
1889 return ret;
1890
1891 pinctrl_pm_select_sleep_state(dev);
1892
1893 return 0;
1894}
1895
1896static int dwc3_resume(struct device *dev)
1897{
1898 struct dwc3 *dwc = dev_get_drvdata(dev);
1899 int ret;
1900
1901 pinctrl_pm_select_default_state(dev);
1902
c4a5153e 1903 ret = dwc3_resume_common(dwc, PMSG_RESUME);
fc8bb91b
FB		 1904 if (ret)
1905 return ret;
1906
7415f17c
FB		 1907 pm_runtime_disable(dev);
1908 pm_runtime_set_active(dev);
1909 pm_runtime_enable(dev);
1910
1911 return 0;
1912}
f580170f
YC		 1913
1914static void dwc3_complete(struct device *dev)
1915{
1916 struct dwc3 *dwc = dev_get_drvdata(dev);
1917 u32 reg;
1918
1919 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
1920 dwc->dis_split_quirk) {
1921 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
1922 reg |= DWC3_GUCTL3_SPLITDISABLE;
1923 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
1924 }
1925}
1926#else
1927#define dwc3_complete NULL
7f370ed0 1928#endif /* CONFIG_PM_SLEEP */
7415f17c
FB		 1929
1930static const struct dev_pm_ops dwc3_dev_pm_ops = {
7415f17c 1931 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
f580170f 1932 .complete = dwc3_complete,
fc8bb91b
FB		 1933 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1934 dwc3_runtime_idle)
7415f17c
FB		 1935};
1936
5088b6f5
KVA		 1937#ifdef CONFIG_OF
1938static const struct of_device_id of_dwc3_match[] = {
22a5aa17
FB		 1939 {
1940 .compatible = "snps,dwc3"
1941 },
5088b6f5
KVA		 1942 {
1943 .compatible = "synopsys,dwc3"
1944 },
1945 { },
1946};
1947MODULE_DEVICE_TABLE(of, of_dwc3_match);
1948#endif
1949
404905a6
HK		 1950#ifdef CONFIG_ACPI
1951
1952#define ACPI_ID_INTEL_BSW "808622B7"
1953
1954static const struct acpi_device_id dwc3_acpi_match[] = {
1955 { ACPI_ID_INTEL_BSW, 0 },
1956 { },
1957};
1958MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1959#endif
1960
72246da4
FB		 1961static struct platform_driver dwc3_driver = {
1962 .probe = dwc3_probe,
7690417d 1963 .remove = dwc3_remove,
72246da4
FB		 1964 .driver = {
1965 .name = "dwc3",
5088b6f5 1966 .of_match_table = of_match_ptr(of_dwc3_match),
404905a6 1967 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
7f370ed0 1968 .pm = &dwc3_dev_pm_ops,
72246da4 1969 },
72246da4
FB		 1970};
1971
b1116dcc
TK		 1972module_platform_driver(dwc3_driver);
1973
7ae4fc4d 1974MODULE_ALIAS("platform:dwc3");
72246da4 1975MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
5945f789 1976MODULE_LICENSE("GPL v2");
72246da4 1977MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux 6.x block layer and io_uring tree(s)