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usb: mtu3: fix USB 3.0 dual-role-switch from device to host
[linux-block.git] / drivers / usb / dwc3 / core.c
CommitLineData
5fd54ace 1// SPDX-License-Identifier: GPL-2.0
cbdc0f54 2/*
72246da4
FB		 3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
10623b87 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
72246da4
FB		 6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
72246da4
FB		 9 */
10
fe8abf33 11#include <linux/clk.h>
fa0ea13e 12#include <linux/version.h>
a72e658b 13#include <linux/module.h>
72246da4
FB		 14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/io.h>
22#include <linux/list.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
457e84b6 25#include <linux/of.h>
404905a6 26#include <linux/acpi.h>
6344475f 27#include <linux/pinctrl/consumer.h>
fe8abf33 28#include <linux/reset.h>
7bee3188 29#include <linux/bitfield.h>
72246da4
FB		 30
31#include <linux/usb/ch9.h>
32#include <linux/usb/gadget.h>
f7e846f0 33#include <linux/usb/of.h>
a45c82b8 34#include <linux/usb/otg.h>
72246da4
FB		 35
36#include "core.h"
37#include "gadget.h"
38#include "io.h"
39
40#include "debug.h"
41
fc8bb91b 42#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
8300dd23 43
9d6173e1
TN		 44/**
45 * dwc3_get_dr_mode - Validates and sets dr_mode
46 * @dwc: pointer to our context structure
47 */
48static int dwc3_get_dr_mode(struct dwc3 *dwc)
49{
50 enum usb_dr_mode mode;
51 struct device *dev = dwc->dev;
52 unsigned int hw_mode;
53
54 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
55 dwc->dr_mode = USB_DR_MODE_OTG;
56
57 mode = dwc->dr_mode;
58 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
59
60 switch (hw_mode) {
61 case DWC3_GHWPARAMS0_MODE_GADGET:
62 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
63 dev_err(dev,
64 "Controller does not support host mode.\n");
65 return -EINVAL;
66 }
67 mode = USB_DR_MODE_PERIPHERAL;
68 break;
69 case DWC3_GHWPARAMS0_MODE_HOST:
70 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
71 dev_err(dev,
72 "Controller does not support device mode.\n");
73 return -EINVAL;
74 }
75 mode = USB_DR_MODE_HOST;
76 break;
77 default:
78 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
79 mode = USB_DR_MODE_HOST;
80 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
81 mode = USB_DR_MODE_PERIPHERAL;
a7700468
TN		 82
83 /*
89a9cc47
TN		 84 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
85 * mode. If the controller supports DRD but the dr_mode is not
86 * specified or set to OTG, then set the mode to peripheral.
a7700468 87 */
89a9cc47 88 if (mode == USB_DR_MODE_OTG &&
8bb14308
TN		 89 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
90 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
9af21dd6 91 !DWC3_VER_IS_PRIOR(DWC3, 330A))
a7700468 92 mode = USB_DR_MODE_PERIPHERAL;
9d6173e1
TN		 93 }
94
95 if (mode != dwc->dr_mode) {
96 dev_warn(dev,
97 "Configuration mismatch. dr_mode forced to %s\n",
98 mode == USB_DR_MODE_HOST ? "host" : "gadget");
99
100 dwc->dr_mode = mode;
101 }
102
103 return 0;
104}
105
f09cc79b 106void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
3140e8cb
SAS		 107{
108 u32 reg;
109
110 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
111 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
112 reg |= DWC3_GCTL_PRTCAPDIR(mode);
113 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
c4a5153e
MG		 114
115 dwc->current_dr_role = mode;
41ce1456
RQ		 116}
117
118static void __dwc3_set_mode(struct work_struct *work)
119{
120 struct dwc3 *dwc = work_to_dwc(work);
121 unsigned long flags;
122 int ret;
f580170f 123 u32 reg;
41ce1456 124
f88359e1
YC		 125 mutex_lock(&dwc->mutex);
126
c2cd3452
MK		 127 pm_runtime_get_sync(dwc->dev);
128
f09cc79b
RQ		 129 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
130 dwc3_otg_update(dwc, 0);
131
41ce1456 132 if (!dwc->desired_dr_role)
c2cd3452 133 goto out;
41ce1456
RQ		 134
135 if (dwc->desired_dr_role == dwc->current_dr_role)
c2cd3452 136 goto out;
41ce1456 137
f09cc79b 138 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
c2cd3452 139 goto out;
41ce1456
RQ		 140
141 switch (dwc->current_dr_role) {
142 case DWC3_GCTL_PRTCAP_HOST:
143 dwc3_host_exit(dwc);
144 break;
145 case DWC3_GCTL_PRTCAP_DEVICE:
146 dwc3_gadget_exit(dwc);
147 dwc3_event_buffers_cleanup(dwc);
148 break;
f09cc79b
RQ		 149 case DWC3_GCTL_PRTCAP_OTG:
150 dwc3_otg_exit(dwc);
151 spin_lock_irqsave(&dwc->lock, flags);
152 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
153 spin_unlock_irqrestore(&dwc->lock, flags);
154 dwc3_otg_update(dwc, 1);
155 break;
41ce1456
RQ		 156 default:
157 break;
158 }
159
f88359e1
YC		 160 /* For DRD host or device mode only */
161 if (dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG) {
162 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
163 reg |= DWC3_GCTL_CORESOFTRESET;
164 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
165
166 /*
167 * Wait for internal clocks to synchronized. DWC_usb31 and
168 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
169 * keep it consistent across different IPs, let's wait up to
170 * 100ms before clearing GCTL.CORESOFTRESET.
171 */
172 msleep(100);
173
174 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
175 reg &= ~DWC3_GCTL_CORESOFTRESET;
176 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
177 }
178
41ce1456
RQ		 179 spin_lock_irqsave(&dwc->lock, flags);
180
181 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
6b3261a2 182
41ce1456
RQ		 183 spin_unlock_irqrestore(&dwc->lock, flags);
184
185 switch (dwc->desired_dr_role) {
186 case DWC3_GCTL_PRTCAP_HOST:
187 ret = dwc3_host_init(dwc);
958d1a4c 188 if (ret) {
41ce1456 189 dev_err(dwc->dev, "failed to initialize host\n");
958d1a4c
FB		 190 } else {
191 if (dwc->usb2_phy)
192 otg_set_vbus(dwc->usb2_phy->otg, true);
644cbbc3
MG		 193 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
194 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
f580170f
YC		 195 if (dwc->dis_split_quirk) {
196 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
197 reg |= DWC3_GUCTL3_SPLITDISABLE;
198 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
199 }
958d1a4c 200 }
41ce1456
RQ		 201 break;
202 case DWC3_GCTL_PRTCAP_DEVICE:
f88359e1
YC		 203 dwc3_core_soft_reset(dwc);
204
41ce1456 205 dwc3_event_buffers_setup(dwc);
958d1a4c
FB		 206
207 if (dwc->usb2_phy)
208 otg_set_vbus(dwc->usb2_phy->otg, false);
644cbbc3
MG		 209 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
210 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
958d1a4c 211
41ce1456
RQ		 212 ret = dwc3_gadget_init(dwc);
213 if (ret)
214 dev_err(dwc->dev, "failed to initialize peripheral\n");
215 break;
f09cc79b
RQ		 216 case DWC3_GCTL_PRTCAP_OTG:
217 dwc3_otg_init(dwc);
218 dwc3_otg_update(dwc, 0);
219 break;
41ce1456
RQ		 220 default:
221 break;
222 }
f09cc79b 223
c2cd3452
MK		 224out:
225 pm_runtime_mark_last_busy(dwc->dev);
226 pm_runtime_put_autosuspend(dwc->dev);
f88359e1 227 mutex_unlock(&dwc->mutex);
41ce1456
RQ		 228}
229
230void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
231{
232 unsigned long flags;
233
dc336b19
LJ		 234 if (dwc->dr_mode != USB_DR_MODE_OTG)
235 return;
236
41ce1456
RQ		 237 spin_lock_irqsave(&dwc->lock, flags);
238 dwc->desired_dr_role = mode;
239 spin_unlock_irqrestore(&dwc->lock, flags);
240
084a804e 241 queue_work(system_freezable_wq, &dwc->drd_work);
3140e8cb 242}
8300dd23 243
cf6d867d
FB		 244u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
245{
246 struct dwc3 *dwc = dep->dwc;
247 u32 reg;
248
249 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
250 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
251 DWC3_GDBGFIFOSPACE_TYPE(type));
252
253 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
254
255 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
256}
257
72246da4
FB		 258/**
259 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
260 * @dwc: pointer to our context structure
261 */
0066472d 262int dwc3_core_soft_reset(struct dwc3 *dwc)
72246da4
FB		 263{
264 u32 reg;
f59dcab1 265 int retries = 1000;
72246da4 266
f59dcab1
FB		 267 /*
268 * We're resetting only the device side because, if we're in host mode,
269 * XHCI driver will reset the host block. If dwc3 was configured for
270 * host-only mode, then we can return early.
271 */
c4a5153e 272 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
f59dcab1 273 return 0;
72246da4 274
f59dcab1
FB		 275 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
276 reg |= DWC3_DCTL_CSFTRST;
277 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 278
4749e0e6
TN		 279 /*
280 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
281 * is cleared only after all the clocks are synchronized. This can
282 * take a little more than 50ms. Set the polling rate at 20ms
283 * for 10 times instead.
284 */
9af21dd6 285 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
4749e0e6
TN		 286 retries = 10;
287
f59dcab1
FB		 288 do {
289 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
290 if (!(reg & DWC3_DCTL_CSFTRST))
fab38333 291 goto done;
45627ac6 292
9af21dd6 293 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
4749e0e6
TN		 294 msleep(20);
295 else
296 udelay(1);
f59dcab1 297 } while (--retries);
57303488 298
f59dcab1 299 return -ETIMEDOUT;
fab38333
TN		 300
301done:
302 /*
4749e0e6
TN		 303 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
304 * is cleared, we must wait at least 50ms before accessing the PHY
305 * domain (synchronization delay).
fab38333 306 */
9af21dd6 307 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
fab38333
TN		 308 msleep(50);
309
310 return 0;
72246da4
FB		 311}
312
db2be4e9
NB		 313/*
314 * dwc3_frame_length_adjustment - Adjusts frame length if required
315 * @dwc3: Pointer to our controller context structure
db2be4e9 316 */
bcdb3272 317static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
db2be4e9
NB		 318{
319 u32 reg;
320 u32 dft;
321
9af21dd6 322 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
db2be4e9
NB		 323 return;
324
bcdb3272 325 if (dwc->fladj == 0)
db2be4e9
NB		 326 return;
327
328 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
329 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
a7d9874c 330 if (dft != dwc->fladj) {
db2be4e9 331 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
bcdb3272 332 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
db2be4e9
NB		 333 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
334 }
335}
336
7bee3188
BP		 337/**
338 * dwc3_ref_clk_period - Reference clock period configuration
339 * Default reference clock period depends on hardware
340 * configuration. For systems with reference clock that differs
341 * from the default, this will set clock period in DWC3_GUCTL
342 * register.
343 * @dwc: Pointer to our controller context structure
344 * @ref_clk_per: reference clock period in ns
345 */
346static void dwc3_ref_clk_period(struct dwc3 *dwc)
347{
5114c3ee 348 unsigned long period;
596c8785
SA		 349 unsigned long fladj;
350 unsigned long decr;
5114c3ee 351 unsigned long rate;
7bee3188
BP		 352 u32 reg;
353
5114c3ee
SA		 354 if (dwc->ref_clk) {
355 rate = clk_get_rate(dwc->ref_clk);
356 if (!rate)
357 return;
358 period = NSEC_PER_SEC / rate;
359 } else if (dwc->ref_clk_per) {
360 period = dwc->ref_clk_per;
596c8785 361 rate = NSEC_PER_SEC / period;
5114c3ee 362 } else {
7bee3188 363 return;
5114c3ee 364 }
7bee3188
BP		 365
366 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
367 reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
5114c3ee 368 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
7bee3188 369 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
7bee3188 370
596c8785
SA		 371 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
372 return;
373
374 /*
375 * The calculation below is
376 *
377 * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
378 *
379 * but rearranged for fixed-point arithmetic. The division must be
380 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
381 * neither does rate * period).
382 *
383 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
384 * nanoseconds of error caused by the truncation which happened during
385 * the division when calculating rate or period (whichever one was
386 * derived from the other). We first calculate the relative error, then
387 * scale it to units of 8 ppm.
388 */
389 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
390 fladj -= 125000;
391
392 /*
393 * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
394 */
395 decr = 480000000 / rate;
396
397 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
398 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
399 & ~DWC3_GFLADJ_240MHZDECR
400 & ~DWC3_GFLADJ_240MHZDECR_PLS1;
401 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
402 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
403 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
404 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
405}
7bee3188 406
72246da4
FB		 407/**
408 * dwc3_free_one_event_buffer - Frees one event buffer
409 * @dwc: Pointer to our controller context structure
410 * @evt: Pointer to event buffer to be freed
411 */
412static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
413 struct dwc3_event_buffer *evt)
414{
d64ff406 415 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
72246da4
FB		 416}
417
418/**
1d046793 419 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
72246da4
FB		 420 * @dwc: Pointer to our controller context structure
421 * @length: size of the event buffer
422 *
1d046793 423 * Returns a pointer to the allocated event buffer structure on success
72246da4
FB		 424 * otherwise ERR_PTR(errno).
425 */
67d0b500
FB		 426static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
427 unsigned length)
72246da4
FB		 428{
429 struct dwc3_event_buffer *evt;
430
380f0d28 431 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
72246da4
FB		 432 if (!evt)
433 return ERR_PTR(-ENOMEM);
434
435 evt->dwc = dwc;
436 evt->length = length;
d9fa4c63
JY		 437 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
438 if (!evt->cache)
439 return ERR_PTR(-ENOMEM);
440
d64ff406 441 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
72246da4 442 &evt->dma, GFP_KERNEL);
e32672f0 443 if (!evt->buf)
72246da4 444 return ERR_PTR(-ENOMEM);
72246da4
FB		 445
446 return evt;
447}
448
449/**
450 * dwc3_free_event_buffers - frees all allocated event buffers
451 * @dwc: Pointer to our controller context structure
452 */
453static void dwc3_free_event_buffers(struct dwc3 *dwc)
454{
455 struct dwc3_event_buffer *evt;
72246da4 456
696c8b12 457 evt = dwc->ev_buf;
660e9bde
FB		 458 if (evt)
459 dwc3_free_one_event_buffer(dwc, evt);
72246da4
FB		 460}
461
462/**
463 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
1d046793 464 * @dwc: pointer to our controller context structure
72246da4
FB		 465 * @length: size of event buffer
466 *
1d046793 467 * Returns 0 on success otherwise negative errno. In the error case, dwc
72246da4
FB		 468 * may contain some buffers allocated but not all which were requested.
469 */
41ac7b3a 470static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
72246da4 471{
660e9bde 472 struct dwc3_event_buffer *evt;
72246da4 473
660e9bde
FB		 474 evt = dwc3_alloc_one_event_buffer(dwc, length);
475 if (IS_ERR(evt)) {
476 dev_err(dwc->dev, "can't allocate event buffer\n");
477 return PTR_ERR(evt);
72246da4 478 }
696c8b12 479 dwc->ev_buf = evt;
72246da4
FB		 480
481 return 0;
482}
483
484/**
485 * dwc3_event_buffers_setup - setup our allocated event buffers
1d046793 486 * @dwc: pointer to our controller context structure
72246da4
FB		 487 *
488 * Returns 0 on success otherwise negative errno.
489 */
f09cc79b 490int dwc3_event_buffers_setup(struct dwc3 *dwc)
72246da4
FB		 491{
492 struct dwc3_event_buffer *evt;
72246da4 493
696c8b12 494 evt = dwc->ev_buf;
660e9bde 495 evt->lpos = 0;
660e9bde
FB		 496 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
497 lower_32_bits(evt->dma));
498 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
499 upper_32_bits(evt->dma));
500 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
501 DWC3_GEVNTSIZ_SIZE(evt->length));
502 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 503
504 return 0;
505}
506
f09cc79b 507void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
72246da4
FB		 508{
509 struct dwc3_event_buffer *evt;
72246da4 510
696c8b12 511 evt = dwc->ev_buf;
7acd85e0 512
660e9bde 513 evt->lpos = 0;
7acd85e0 514
660e9bde
FB		 515 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
516 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
517 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
518 | DWC3_GEVNTSIZ_SIZE(0));
519 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 520}
521
0ffcaf37
FB		 522static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
523{
524 if (!dwc->has_hibernation)
525 return 0;
526
527 if (!dwc->nr_scratch)
528 return 0;
529
530 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
531 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
532 if (!dwc->scratchbuf)
533 return -ENOMEM;
534
535 return 0;
536}
537
538static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
539{
540 dma_addr_t scratch_addr;
541 u32 param;
542 int ret;
543
544 if (!dwc->has_hibernation)
545 return 0;
546
547 if (!dwc->nr_scratch)
548 return 0;
549
550 /* should never fall here */
551 if (!WARN_ON(dwc->scratchbuf))
552 return 0;
553
d64ff406 554 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
0ffcaf37
FB		 555 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
556 DMA_BIDIRECTIONAL);
d64ff406
AB		 557 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
558 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
0ffcaf37
FB		 559 ret = -EFAULT;
560 goto err0;
561 }
562
563 dwc->scratch_addr = scratch_addr;
564
565 param = lower_32_bits(scratch_addr);
566
567 ret = dwc3_send_gadget_generic_command(dwc,
568 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
569 if (ret < 0)
570 goto err1;
571
572 param = upper_32_bits(scratch_addr);
573
574 ret = dwc3_send_gadget_generic_command(dwc,
575 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
576 if (ret < 0)
577 goto err1;
578
579 return 0;
580
581err1:
d64ff406 582 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
0ffcaf37
FB		 583 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
584
585err0:
586 return ret;
587}
588
589static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
590{
591 if (!dwc->has_hibernation)
592 return;
593
594 if (!dwc->nr_scratch)
595 return;
596
597 /* should never fall here */
598 if (!WARN_ON(dwc->scratchbuf))
599 return;
600
d64ff406 601 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
0ffcaf37
FB		 602 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
603 kfree(dwc->scratchbuf);
604}
605
789451f6
FB		 606static void dwc3_core_num_eps(struct dwc3 *dwc)
607{
608 struct dwc3_hwparams *parms = &dwc->hwparams;
609
47d3946e 610 dwc->num_eps = DWC3_NUM_EPS(parms);
789451f6
FB		 611}
612
41ac7b3a 613static void dwc3_cache_hwparams(struct dwc3 *dwc)
26ceca97
FB		 614{
615 struct dwc3_hwparams *parms = &dwc->hwparams;
616
617 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
618 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
619 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
620 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
621 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
622 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
623 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
624 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
625 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
16710380
TN		 626
627 if (DWC3_IP_IS(DWC32))
628 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
26ceca97
FB		 629}
630
98112041
RQ		 631static int dwc3_core_ulpi_init(struct dwc3 *dwc)
632{
633 int intf;
634 int ret = 0;
635
636 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
637
638 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
639 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
640 dwc->hsphy_interface &&
641 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
642 ret = dwc3_ulpi_init(dwc);
643
644 return ret;
645}
646
b5a65c40
HR		 647/**
648 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
649 * @dwc: Pointer to our controller context structure
88bc9d19
HK		 650 *
651 * Returns 0 on success. The USB PHY interfaces are configured but not
652 * initialized. The PHY interfaces and the PHYs get initialized together with
653 * the core in dwc3_core_init.
b5a65c40 654 */
88bc9d19 655static int dwc3_phy_setup(struct dwc3 *dwc)
b5a65c40 656{
9ba3aca8 657 unsigned int hw_mode;
b5a65c40
HR		 658 u32 reg;
659
9ba3aca8
TN		 660 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
661
b5a65c40
HR		 662 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
663
1966b865
FB		 664 /*
665 * Make sure UX_EXIT_PX is cleared as that causes issues with some
666 * PHYs. Also, this bit is not supposed to be used in normal operation.
667 */
668 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
669
2164a476
HR		 670 /*
671 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
672 * to '0' during coreConsultant configuration. So default value
673 * will be '0' when the core is reset. Application needs to set it
674 * to '1' after the core initialization is completed.
675 */
9af21dd6 676 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
2164a476
HR		 677 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
678
9ba3aca8
TN		 679 /*
680 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
681 * power-on reset, and it can be set after core initialization, which is
682 * after device soft-reset during initialization.
683 */
684 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
685 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
686
b5a65c40
HR		 687 if (dwc->u2ss_inp3_quirk)
688 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
689
e58dd357
RB		 690 if (dwc->dis_rxdet_inp3_quirk)
691 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
692
df31f5b3
HR		 693 if (dwc->req_p1p2p3_quirk)
694 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
695
a2a1d0f5
HR		 696 if (dwc->del_p1p2p3_quirk)
697 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
698
41c06ffd
HR		 699 if (dwc->del_phy_power_chg_quirk)
700 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
701
fb67afca
HR		 702 if (dwc->lfps_filter_quirk)
703 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
704
14f4ac53
HR		 705 if (dwc->rx_detect_poll_quirk)
706 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
707
6b6a0c9a
HR		 708 if (dwc->tx_de_emphasis_quirk)
709 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
710
cd72f890 711 if (dwc->dis_u3_susphy_quirk)
59acfa20
HR		 712 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
713
00fe081d
WW		 714 if (dwc->dis_del_phy_power_chg_quirk)
715 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
716
b5a65c40
HR		 717 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
718
2164a476
HR		 719 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
720
3e10a2ce
HK		 721 /* Select the HS PHY interface */
722 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
723 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
43cacb03
FB		 724 if (dwc->hsphy_interface &&
725 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
3e10a2ce 726 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 727 break;
43cacb03
FB		 728 } else if (dwc->hsphy_interface &&
729 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
3e10a2ce 730 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 731 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
3e10a2ce 732 } else {
88bc9d19
HK		 733 /* Relying on default value. */
734 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
735 break;
3e10a2ce 736 }
df561f66 737 fallthrough;
88bc9d19 738 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
3e10a2ce
HK		 739 default:
740 break;
741 }
742
32f2ed86
WW		 743 switch (dwc->hsphy_mode) {
744 case USBPHY_INTERFACE_MODE_UTMI:
745 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
746 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
747 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
748 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
749 break;
750 case USBPHY_INTERFACE_MODE_UTMIW:
751 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
752 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
753 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
754 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
755 break;
756 default:
757 break;
758 }
759
2164a476
HR		 760 /*
761 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
762 * '0' during coreConsultant configuration. So default value will
763 * be '0' when the core is reset. Application needs to set it to
764 * '1' after the core initialization is completed.
765 */
9af21dd6 766 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
2164a476
HR		 767 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
768
9ba3aca8
TN		 769 /*
770 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
771 * power-on reset, and it can be set after core initialization, which is
772 * after device soft-reset during initialization.
773 */
774 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
775 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
776
cd72f890 777 if (dwc->dis_u2_susphy_quirk)
0effe0a3
HR		 778 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
779
ec791d14
JY		 780 if (dwc->dis_enblslpm_quirk)
781 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
eafeacf1
TN		 782 else
783 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
ec791d14 784
16199f33
WW		 785 if (dwc->dis_u2_freeclk_exists_quirk)
786 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
787
2164a476 788 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
88bc9d19
HK		 789
790 return 0;
b5a65c40
HR		 791}
792
33fb697e
SA		 793static int dwc3_clk_enable(struct dwc3 *dwc)
794{
795 int ret;
796
797 ret = clk_prepare_enable(dwc->bus_clk);
798 if (ret)
799 return ret;
800
801 ret = clk_prepare_enable(dwc->ref_clk);
802 if (ret)
803 goto disable_bus_clk;
804
805 ret = clk_prepare_enable(dwc->susp_clk);
806 if (ret)
807 goto disable_ref_clk;
808
809 return 0;
810
811disable_ref_clk:
812 clk_disable_unprepare(dwc->ref_clk);
813disable_bus_clk:
814 clk_disable_unprepare(dwc->bus_clk);
815 return ret;
816}
817
818static void dwc3_clk_disable(struct dwc3 *dwc)
819{
820 clk_disable_unprepare(dwc->susp_clk);
821 clk_disable_unprepare(dwc->ref_clk);
822 clk_disable_unprepare(dwc->bus_clk);
823}
824
c499ff71
FB		 825static void dwc3_core_exit(struct dwc3 *dwc)
826{
827 dwc3_event_buffers_cleanup(dwc);
828
829 usb_phy_shutdown(dwc->usb2_phy);
830 usb_phy_shutdown(dwc->usb3_phy);
831 phy_exit(dwc->usb2_generic_phy);
832 phy_exit(dwc->usb3_generic_phy);
833
834 usb_phy_set_suspend(dwc->usb2_phy, 1);
835 usb_phy_set_suspend(dwc->usb3_phy, 1);
836 phy_power_off(dwc->usb2_generic_phy);
837 phy_power_off(dwc->usb3_generic_phy);
33fb697e 838 dwc3_clk_disable(dwc);
fe8abf33 839 reset_control_assert(dwc->reset);
c499ff71
FB		 840}
841
0759956f 842static bool dwc3_core_is_valid(struct dwc3 *dwc)
72246da4 843{
0759956f 844 u32 reg;
72246da4 845
7650bd74 846 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
9af21dd6 847 dwc->ip = DWC3_GSNPS_ID(reg);
0759956f 848
7650bd74 849 /* This should read as U3 followed by revision number */
9af21dd6 850 if (DWC3_IP_IS(DWC3)) {
690fb371 851 dwc->revision = reg;
9af21dd6 852 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
690fb371 853 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
475d8e01 854 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
690fb371 855 } else {
0759956f 856 return false;
7650bd74 857 }
7650bd74 858
0759956f
FB		 859 return true;
860}
58a0f23f 861
941f918e 862static void dwc3_core_setup_global_control(struct dwc3 *dwc)
0759956f 863{
941f918e
FB		 864 u32 hwparams4 = dwc->hwparams.hwparams4;
865 u32 reg;
c499ff71 866
4878a028 867 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
3e87c42a 868 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
4878a028 869
164d7731 870 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
4878a028 871 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
32a4a135
FB		 872 /**
873 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
874 * issue which would cause xHCI compliance tests to fail.
875 *
876 * Because of that we cannot enable clock gating on such
877 * configurations.
878 *
879 * Refers to:
880 *
881 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
882 * SOF/ITP Mode Used
883 */
884 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
885 dwc->dr_mode == USB_DR_MODE_OTG) &&
9af21dd6 886 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
32a4a135
FB		 887 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
888 else
889 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
4878a028 890 break;
0ffcaf37
FB		 891 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
892 /* enable hibernation here */
893 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
2eac3992
HR		 894
895 /*
896 * REVISIT Enabling this bit so that host-mode hibernation
897 * will work. Device-mode hibernation is not yet implemented.
898 */
899 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
0ffcaf37 900 break;
4878a028 901 default:
5eb30ced
FB		 902 /* nothing */
903 break;
4878a028
SAS		 904 }
905
946bd579
HR		 906 /* check if current dwc3 is on simulation board */
907 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
6af19fd1 908 dev_info(dwc->dev, "Running with FPGA optimizations\n");
946bd579
HR		 909 dwc->is_fpga = true;
910 }
911
3b81221a
HR		 912 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
913 "disable_scramble cannot be used on non-FPGA builds\n");
914
915 if (dwc->disable_scramble_quirk && dwc->is_fpga)
916 reg |= DWC3_GCTL_DISSCRAMBLE;
917 else
918 reg &= ~DWC3_GCTL_DISSCRAMBLE;
919
9a5b2f31
HR		 920 if (dwc->u2exit_lfps_quirk)
921 reg |= DWC3_GCTL_U2EXIT_LFPS;
922
4878a028
SAS		 923 /*
924 * WORKAROUND: DWC3 revisions <1.90a have a bug
1d046793 925 * where the device can fail to connect at SuperSpeed
4878a028 926 * and falls back to high-speed mode which causes
1d046793 927 * the device to enter a Connect/Disconnect loop
4878a028 928 */
9af21dd6 929 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
4878a028
SAS		 930 reg |= DWC3_GCTL_U2RSTECN;
931
932 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
941f918e
FB		 933}
934
f54edb53 935static int dwc3_core_get_phy(struct dwc3 *dwc);
98112041 936static int dwc3_core_ulpi_init(struct dwc3 *dwc);
f54edb53 937
d9612c2f
PM		 938/* set global incr burst type configuration registers */
939static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
940{
941 struct device *dev = dwc->dev;
942 /* incrx_mode : for INCR burst type. */
943 bool incrx_mode;
944 /* incrx_size : for size of INCRX burst. */
945 u32 incrx_size;
946 u32 *vals;
947 u32 cfg;
948 int ntype;
949 int ret;
950 int i;
951
952 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
953
954 /*
955 * Handle property "snps,incr-burst-type-adjustment".
956 * Get the number of value from this property:
957 * result <= 0, means this property is not supported.
958 * result = 1, means INCRx burst mode supported.
959 * result > 1, means undefined length burst mode supported.
960 */
a6e5e679 961 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
d9612c2f
PM		 962 if (ntype <= 0)
963 return;
964
965 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
966 if (!vals) {
967 dev_err(dev, "Error to get memory\n");
968 return;
969 }
970
971 /* Get INCR burst type, and parse it */
972 ret = device_property_read_u32_array(dev,
973 "snps,incr-burst-type-adjustment", vals, ntype);
974 if (ret) {
75ecb9dd 975 kfree(vals);
d9612c2f
PM		 976 dev_err(dev, "Error to get property\n");
977 return;
978 }
979
980 incrx_size = *vals;
981
982 if (ntype > 1) {
983 /* INCRX (undefined length) burst mode */
984 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
985 for (i = 1; i < ntype; i++) {
986 if (vals[i] > incrx_size)
987 incrx_size = vals[i];
988 }
989 } else {
990 /* INCRX burst mode */
991 incrx_mode = INCRX_BURST_MODE;
992 }
993
75ecb9dd
AS		 994 kfree(vals);
995
d9612c2f
PM		 996 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
997 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
998 if (incrx_mode)
999 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
1000 switch (incrx_size) {
1001 case 256:
1002 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1003 break;
1004 case 128:
1005 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1006 break;
1007 case 64:
1008 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1009 break;
1010 case 32:
1011 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1012 break;
1013 case 16:
1014 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1015 break;
1016 case 8:
1017 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1018 break;
1019 case 4:
1020 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1021 break;
1022 case 1:
1023 break;
1024 default:
1025 dev_err(dev, "Invalid property\n");
1026 break;
1027 }
1028
1029 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1030}
1031
941f918e
FB		 1032/**
1033 * dwc3_core_init - Low-level initialization of DWC3 Core
1034 * @dwc: Pointer to our controller context structure
1035 *
1036 * Returns 0 on success otherwise negative errno.
1037 */
1038static int dwc3_core_init(struct dwc3 *dwc)
1039{
9ba3aca8 1040 unsigned int hw_mode;
941f918e
FB		 1041 u32 reg;
1042 int ret;
1043
9ba3aca8
TN		 1044 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1045
941f918e
FB		 1046 /*
1047 * Write Linux Version Code to our GUID register so it's easy to figure
1048 * out which kernel version a bug was found.
1049 */
1050 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1051
98112041 1052 ret = dwc3_phy_setup(dwc);
941f918e
FB		 1053 if (ret)
1054 goto err0;
4878a028 1055
98112041
RQ		 1056 if (!dwc->ulpi_ready) {
1057 ret = dwc3_core_ulpi_init(dwc);
1058 if (ret)
1059 goto err0;
1060 dwc->ulpi_ready = true;
1061 }
4878a028 1062
98112041
RQ		 1063 if (!dwc->phys_ready) {
1064 ret = dwc3_core_get_phy(dwc);
1065 if (ret)
1066 goto err0a;
1067 dwc->phys_ready = true;
1068 }
1069
8cfac9a6
LJ		 1070 usb_phy_init(dwc->usb2_phy);
1071 usb_phy_init(dwc->usb3_phy);
1072 ret = phy_init(dwc->usb2_generic_phy);
1073 if (ret < 0)
1074 goto err0a;
1075
1076 ret = phy_init(dwc->usb3_generic_phy);
1077 if (ret < 0) {
1078 phy_exit(dwc->usb2_generic_phy);
1079 goto err0a;
1080 }
1081
98112041 1082 ret = dwc3_core_soft_reset(dwc);
f54edb53 1083 if (ret)
8cfac9a6 1084 goto err1;
f54edb53 1085
9ba3aca8 1086 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
9af21dd6 1087 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
9ba3aca8
TN		 1088 if (!dwc->dis_u3_susphy_quirk) {
1089 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1090 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1091 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1092 }
1093
1094 if (!dwc->dis_u2_susphy_quirk) {
1095 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1096 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1097 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1098 }
1099 }
1100
941f918e 1101 dwc3_core_setup_global_control(dwc);
c499ff71 1102 dwc3_core_num_eps(dwc);
0ffcaf37
FB		 1103
1104 ret = dwc3_setup_scratch_buffers(dwc);
1105 if (ret)
c499ff71
FB		 1106 goto err1;
1107
1108 /* Adjust Frame Length */
1109 dwc3_frame_length_adjustment(dwc);
1110
7bee3188
BP		 1111 /* Adjust Reference Clock Period */
1112 dwc3_ref_clk_period(dwc);
1113
d9612c2f
PM		 1114 dwc3_set_incr_burst_type(dwc);
1115
c499ff71
FB		 1116 usb_phy_set_suspend(dwc->usb2_phy, 0);
1117 usb_phy_set_suspend(dwc->usb3_phy, 0);
1118 ret = phy_power_on(dwc->usb2_generic_phy);
1119 if (ret < 0)
0ffcaf37
FB		 1120 goto err2;
1121
c499ff71
FB		 1122 ret = phy_power_on(dwc->usb3_generic_phy);
1123 if (ret < 0)
1124 goto err3;
1125
1126 ret = dwc3_event_buffers_setup(dwc);
1127 if (ret) {
1128 dev_err(dwc->dev, "failed to setup event buffers\n");
1129 goto err4;
1130 }
1131
06281d46
JY		 1132 /*
1133 * ENDXFER polling is available on version 3.10a and later of
1134 * the DWC_usb3 controller. It is NOT available in the
1135 * DWC_usb31 controller.
1136 */
9af21dd6 1137 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
06281d46
JY		 1138 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1139 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1140 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1141 }
1142
9af21dd6 1143 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
0bb39ca1 1144 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
65db7a0c
WW		 1145
1146 /*
1147 * Enable hardware control of sending remote wakeup
1148 * in HS when the device is in the L1 state.
1149 */
9af21dd6 1150 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
65db7a0c
WW		 1151 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1152
843714bb
JP		 1153 /*
1154 * Decouple USB 2.0 L1 & L2 events which will allow for
1155 * gadget driver to only receive U3/L2 suspend & wakeup
1156 * events and prevent the more frequent L1 LPM transitions
1157 * from interrupting the driver.
1158 */
1159 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1160 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1161
65db7a0c
WW		 1162 if (dwc->dis_tx_ipgap_linecheck_quirk)
1163 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1164
7ba6b09f
NA		 1165 if (dwc->parkmode_disable_ss_quirk)
1166 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1167
62b20e6e
BY		 1168 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
1169 (dwc->maximum_speed == USB_SPEED_HIGH ||
1170 dwc->maximum_speed == USB_SPEED_FULL))
1171 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1172
0bb39ca1
JY		 1173 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1174 }
1175
b138e23d
AKV		 1176 if (dwc->dr_mode == USB_DR_MODE_HOST ||
1177 dwc->dr_mode == USB_DR_MODE_OTG) {
1178 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1179
1180 /*
1181 * Enable Auto retry Feature to make the controller operating in
1182 * Host mode on seeing transaction errors(CRC errors or internal
1183 * overrun scenerios) on IN transfers to reply to the device
1184 * with a non-terminating retry ACK (i.e, an ACK transcation
1185 * packet with Retry=1 & Nump != 0)
1186 */
1187 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1188
1189 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1190 }
1191
938a5ad1
TN		 1192 /*
1193 * Must config both number of packets and max burst settings to enable
1194 * RX and/or TX threshold.
1195 */
9af21dd6 1196 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
938a5ad1
TN		 1197 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1198 u8 rx_maxburst = dwc->rx_max_burst_prd;
1199 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1200 u8 tx_maxburst = dwc->tx_max_burst_prd;
1201
1202 if (rx_thr_num && rx_maxburst) {
1203 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1204 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1205
1206 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1207 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1208
1209 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1210 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1211
1212 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1213 }
1214
1215 if (tx_thr_num && tx_maxburst) {
1216 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1217 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1218
1219 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1220 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1221
1222 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1223 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1224
1225 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1226 }
1227 }
1228
72246da4
FB		 1229 return 0;
1230
c499ff71 1231err4:
9b9d7cdd 1232 phy_power_off(dwc->usb3_generic_phy);
c499ff71
FB		 1233
1234err3:
9b9d7cdd 1235 phy_power_off(dwc->usb2_generic_phy);
c499ff71 1236
0ffcaf37 1237err2:
c499ff71
FB		 1238 usb_phy_set_suspend(dwc->usb2_phy, 1);
1239 usb_phy_set_suspend(dwc->usb3_phy, 1);
0ffcaf37
FB		 1240
1241err1:
1242 usb_phy_shutdown(dwc->usb2_phy);
1243 usb_phy_shutdown(dwc->usb3_phy);
57303488
KVA		 1244 phy_exit(dwc->usb2_generic_phy);
1245 phy_exit(dwc->usb3_generic_phy);
0ffcaf37 1246
98112041
RQ		 1247err0a:
1248 dwc3_ulpi_exit(dwc);
1249
72246da4
FB		 1250err0:
1251 return ret;
1252}
1253
3c9f94ac 1254static int dwc3_core_get_phy(struct dwc3 *dwc)
72246da4 1255{
3c9f94ac 1256 struct device *dev = dwc->dev;
941ea361 1257 struct device_node *node = dev->of_node;
3c9f94ac 1258 int ret;
72246da4 1259
5088b6f5
KVA		 1260 if (node) {
1261 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1262 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
bb674907
FB		 1263 } else {
1264 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1265 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
5088b6f5
KVA		 1266 }
1267
d105e7f8
FB		 1268 if (IS_ERR(dwc->usb2_phy)) {
1269 ret = PTR_ERR(dwc->usb2_phy);
122f06e6
KVA		 1270 if (ret == -ENXIO || ret == -ENODEV) {
1271 dwc->usb2_phy = NULL;
122f06e6 1272 } else {
0c0a20f6 1273 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
122f06e6 1274 }
51e1e7bc
FB		 1275 }
1276
d105e7f8 1277 if (IS_ERR(dwc->usb3_phy)) {
315955d7 1278 ret = PTR_ERR(dwc->usb3_phy);
122f06e6
KVA		 1279 if (ret == -ENXIO || ret == -ENODEV) {
1280 dwc->usb3_phy = NULL;
122f06e6 1281 } else {
0c0a20f6 1282 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
122f06e6 1283 }
51e1e7bc
FB		 1284 }
1285
57303488
KVA		 1286 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1287 if (IS_ERR(dwc->usb2_generic_phy)) {
1288 ret = PTR_ERR(dwc->usb2_generic_phy);
1289 if (ret == -ENOSYS || ret == -ENODEV) {
1290 dwc->usb2_generic_phy = NULL;
57303488 1291 } else {
0c0a20f6 1292 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
57303488
KVA		 1293 }
1294 }
1295
1296 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1297 if (IS_ERR(dwc->usb3_generic_phy)) {
1298 ret = PTR_ERR(dwc->usb3_generic_phy);
1299 if (ret == -ENOSYS || ret == -ENODEV) {
1300 dwc->usb3_generic_phy = NULL;
57303488 1301 } else {
0c0a20f6 1302 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
57303488
KVA		 1303 }
1304 }
1305
3c9f94ac
FB		 1306 return 0;
1307}
1308
5f94adfe
FB		 1309static int dwc3_core_init_mode(struct dwc3 *dwc)
1310{
1311 struct device *dev = dwc->dev;
1312 int ret;
1313
1314 switch (dwc->dr_mode) {
1315 case USB_DR_MODE_PERIPHERAL:
41ce1456 1316 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
958d1a4c
FB		 1317
1318 if (dwc->usb2_phy)
1319 otg_set_vbus(dwc->usb2_phy->otg, false);
644cbbc3
MG		 1320 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1321 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
958d1a4c 1322
5f94adfe 1323 ret = dwc3_gadget_init(dwc);
0c0a20f6
AS		 1324 if (ret)
1325 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
5f94adfe
FB		 1326 break;
1327 case USB_DR_MODE_HOST:
41ce1456 1328 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
958d1a4c
FB		 1329
1330 if (dwc->usb2_phy)
1331 otg_set_vbus(dwc->usb2_phy->otg, true);
644cbbc3
MG		 1332 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1333 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
958d1a4c 1334
5f94adfe 1335 ret = dwc3_host_init(dwc);
0c0a20f6
AS		 1336 if (ret)
1337 return dev_err_probe(dev, ret, "failed to initialize host\n");
5f94adfe
FB		 1338 break;
1339 case USB_DR_MODE_OTG:
41ce1456 1340 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
9840354f 1341 ret = dwc3_drd_init(dwc);
0c0a20f6
AS		 1342 if (ret)
1343 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
5f94adfe
FB		 1344 break;
1345 default:
1346 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1347 return -EINVAL;
1348 }
1349
1350 return 0;
1351}
1352
1353static void dwc3_core_exit_mode(struct dwc3 *dwc)
1354{
1355 switch (dwc->dr_mode) {
1356 case USB_DR_MODE_PERIPHERAL:
1357 dwc3_gadget_exit(dwc);
1358 break;
1359 case USB_DR_MODE_HOST:
1360 dwc3_host_exit(dwc);
1361 break;
1362 case USB_DR_MODE_OTG:
9840354f 1363 dwc3_drd_exit(dwc);
5f94adfe
FB		 1364 break;
1365 default:
1366 /* do nothing */
1367 break;
1368 }
09ed259f
BL		 1369
1370 /* de-assert DRVVBUS for HOST and OTG mode */
1371 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
5f94adfe
FB		 1372}
1373
c5ac6116 1374static void dwc3_get_properties(struct dwc3 *dwc)
3c9f94ac 1375{
c5ac6116 1376 struct device *dev = dwc->dev;
80caf7d2 1377 u8 lpm_nyet_threshold;
6b6a0c9a 1378 u8 tx_de_emphasis;
460d098c 1379 u8 hird_threshold;
938a5ad1
TN		 1380 u8 rx_thr_num_pkt_prd;
1381 u8 rx_max_burst_prd;
1382 u8 tx_thr_num_pkt_prd;
1383 u8 tx_max_burst_prd;
9f607a30 1384 u8 tx_fifo_resize_max_num;
6f0764b5
RC		 1385 const char *usb_psy_name;
1386 int ret;
3c9f94ac 1387
80caf7d2 1388 /* default to highest possible threshold */
8d791929 1389 lpm_nyet_threshold = 0xf;
80caf7d2 1390
6b6a0c9a
HR		 1391 /* default to -3.5dB de-emphasis */
1392 tx_de_emphasis = 1;
1393
460d098c
HR		 1394 /*
1395 * default to assert utmi_sleep_n and use maximum allowed HIRD
1396 * threshold value of 0b1100
1397 */
1398 hird_threshold = 12;
1399
9f607a30
WC		 1400 /*
1401 * default to a TXFIFO size large enough to fit 6 max packets. This
1402 * allows for systems with larger bus latencies to have some headroom
1403 * for endpoints that have a large bMaxBurst value.
1404 */
1405 tx_fifo_resize_max_num = 6;
1406
63863b98 1407 dwc->maximum_speed = usb_get_maximum_speed(dev);
67848146 1408 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
06e7114f 1409 dwc->dr_mode = usb_get_dr_mode(dev);
32f2ed86 1410 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
63863b98 1411
d64ff406
AB		 1412 dwc->sysdev_is_parent = device_property_read_bool(dev,
1413 "linux,sysdev_is_parent");
1414 if (dwc->sysdev_is_parent)
1415 dwc->sysdev = dwc->dev->parent;
1416 else
1417 dwc->sysdev = dwc->dev;
1418
6f0764b5
RC		 1419 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1420 if (ret >= 0) {
1421 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1422 if (!dwc->usb_psy)
1423 dev_err(dev, "couldn't get usb power supply\n");
1424 }
1425
3d128919 1426 dwc->has_lpm_erratum = device_property_read_bool(dev,
80caf7d2 1427 "snps,has-lpm-erratum");
3d128919 1428 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
80caf7d2 1429 &lpm_nyet_threshold);
3d128919 1430 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
460d098c 1431 "snps,is-utmi-l1-suspend");
3d128919 1432 device_property_read_u8(dev, "snps,hird-threshold",
460d098c 1433 &hird_threshold);
d92021f6
TN		 1434 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1435 "snps,dis-start-transfer-quirk");
3d128919 1436 dwc->usb3_lpm_capable = device_property_read_bool(dev,
eac68e8f 1437 "snps,usb3_lpm_capable");
022a0208
TN		 1438 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1439 "snps,usb2-lpm-disable");
475e8be5
TN		 1440 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1441 "snps,usb2-gadget-lpm-disable");
938a5ad1
TN		 1442 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1443 &rx_thr_num_pkt_prd);
1444 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1445 &rx_max_burst_prd);
1446 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1447 &tx_thr_num_pkt_prd);
1448 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1449 &tx_max_burst_prd);
9f607a30
WC		 1450 dwc->do_fifo_resize = device_property_read_bool(dev,
1451 "tx-fifo-resize");
1452 if (dwc->do_fifo_resize)
1453 device_property_read_u8(dev, "tx-fifo-max-num",
1454 &tx_fifo_resize_max_num);
3c9f94ac 1455
3d128919 1456 dwc->disable_scramble_quirk = device_property_read_bool(dev,
3b81221a 1457 "snps,disable_scramble_quirk");
3d128919 1458 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
9a5b2f31 1459 "snps,u2exit_lfps_quirk");
3d128919 1460 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
b5a65c40 1461 "snps,u2ss_inp3_quirk");
3d128919 1462 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
df31f5b3 1463 "snps,req_p1p2p3_quirk");
3d128919 1464 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
a2a1d0f5 1465 "snps,del_p1p2p3_quirk");
3d128919 1466 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
41c06ffd 1467 "snps,del_phy_power_chg_quirk");
3d128919 1468 dwc->lfps_filter_quirk = device_property_read_bool(dev,
fb67afca 1469 "snps,lfps_filter_quirk");
3d128919 1470 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
14f4ac53 1471 "snps,rx_detect_poll_quirk");
3d128919 1472 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
59acfa20 1473 "snps,dis_u3_susphy_quirk");
3d128919 1474 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
0effe0a3 1475 "snps,dis_u2_susphy_quirk");
ec791d14
JY		 1476 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1477 "snps,dis_enblslpm_quirk");
729dcffd
AKV		 1478 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1479 "snps,dis-u1-entry-quirk");
1480 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1481 "snps,dis-u2-entry-quirk");
e58dd357
RB		 1482 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1483 "snps,dis_rxdet_inp3_quirk");
16199f33
WW		 1484 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1485 "snps,dis-u2-freeclk-exists-quirk");
00fe081d
WW		 1486 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1487 "snps,dis-del-phy-power-chg-quirk");
65db7a0c
WW		 1488 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1489 "snps,dis-tx-ipgap-linecheck-quirk");
7ba6b09f
NA		 1490 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1491 "snps,parkmode-disable-ss-quirk");
6b6a0c9a 1492
3d128919 1493 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
6b6a0c9a 1494 "snps,tx_de_emphasis_quirk");
3d128919 1495 device_property_read_u8(dev, "snps,tx_de_emphasis",
6b6a0c9a 1496 &tx_de_emphasis);
3d128919
HK		 1497 device_property_read_string(dev, "snps,hsphy_interface",
1498 &dwc->hsphy_interface);
1499 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
bcdb3272 1500 &dwc->fladj);
7bee3188
BP		 1501 device_property_read_u32(dev, "snps,ref-clock-period-ns",
1502 &dwc->ref_clk_per);
3d128919 1503
42bf02ec
RQ		 1504 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1505 "snps,dis_metastability_quirk");
1506
f580170f
YC		 1507 dwc->dis_split_quirk = device_property_read_bool(dev,
1508 "snps,dis-split-quirk");
1509
80caf7d2 1510 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
6b6a0c9a 1511 dwc->tx_de_emphasis = tx_de_emphasis;
80caf7d2 1512
16fe4f30 1513 dwc->hird_threshold = hird_threshold;
460d098c 1514
938a5ad1
TN		 1515 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1516 dwc->rx_max_burst_prd = rx_max_burst_prd;
1517
1518 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1519 dwc->tx_max_burst_prd = tx_max_burst_prd;
1520
cf40b86b 1521 dwc->imod_interval = 0;
9f607a30
WC		 1522
1523 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
cf40b86b
JY		 1524}
1525
1526/* check whether the core supports IMOD */
1527bool dwc3_has_imod(struct dwc3 *dwc)
1528{
9af21dd6
TN		 1529 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1530 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1531 DWC3_IP_IS(DWC32);
c5ac6116
FB		 1532}
1533
7ac51a12
JY		 1534static void dwc3_check_params(struct dwc3 *dwc)
1535{
1536 struct device *dev = dwc->dev;
b574ce3e
TN		 1537 unsigned int hwparam_gen =
1538 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
7ac51a12 1539
cf40b86b
JY		 1540 /* Check for proper value of imod_interval */
1541 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1542 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1543 dwc->imod_interval = 0;
1544 }
1545
28632b44
JY		 1546 /*
1547 * Workaround for STAR 9000961433 which affects only version
1548 * 3.00a of the DWC_usb3 core. This prevents the controller
1549 * interrupt from being masked while handling events. IMOD
1550 * allows us to work around this issue. Enable it for the
1551 * affected version.
1552 */
1553 if (!dwc->imod_interval &&
9af21dd6 1554 DWC3_VER_IS(DWC3, 300A))
28632b44
JY		 1555 dwc->imod_interval = 1;
1556
7ac51a12
JY		 1557 /* Check the maximum_speed parameter */
1558 switch (dwc->maximum_speed) {
7ac51a12
JY		 1559 case USB_SPEED_FULL:
1560 case USB_SPEED_HIGH:
e518bdd9 1561 break;
7ac51a12 1562 case USB_SPEED_SUPER:
e518bdd9
TN		 1563 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1564 dev_warn(dev, "UDC doesn't support Gen 1\n");
1565 break;
7ac51a12 1566 case USB_SPEED_SUPER_PLUS:
e518bdd9
TN		 1567 if ((DWC3_IP_IS(DWC32) &&
1568 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1569 (!DWC3_IP_IS(DWC32) &&
1570 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1571 dev_warn(dev, "UDC doesn't support SSP\n");
7ac51a12
JY		 1572 break;
1573 default:
1574 dev_err(dev, "invalid maximum_speed parameter %d\n",
1575 dwc->maximum_speed);
df561f66 1576 fallthrough;
7ac51a12 1577 case USB_SPEED_UNKNOWN:
b574ce3e
TN		 1578 switch (hwparam_gen) {
1579 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
7ac51a12 1580 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
b574ce3e
TN		 1581 break;
1582 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1583 if (DWC3_IP_IS(DWC32))
1584 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1585 else
1586 dwc->maximum_speed = USB_SPEED_SUPER;
1587 break;
1588 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1589 dwc->maximum_speed = USB_SPEED_HIGH;
1590 break;
1591 default:
1592 dwc->maximum_speed = USB_SPEED_SUPER;
1593 break;
1594 }
7ac51a12
JY		 1595 break;
1596 }
67848146
TN		 1597
1598 /*
1599 * Currently the controller does not have visibility into the HW
1600 * parameter to determine the maximum number of lanes the HW supports.
1601 * If the number of lanes is not specified in the device property, then
1602 * set the default to support dual-lane for DWC_usb32 and single-lane
1603 * for DWC_usb31 for super-speed-plus.
1604 */
1605 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1606 switch (dwc->max_ssp_rate) {
1607 case USB_SSP_GEN_2x1:
1608 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1609 dev_warn(dev, "UDC only supports Gen 1\n");
1610 break;
1611 case USB_SSP_GEN_1x2:
1612 case USB_SSP_GEN_2x2:
1613 if (DWC3_IP_IS(DWC31))
1614 dev_warn(dev, "UDC only supports single lane\n");
1615 break;
1616 case USB_SSP_GEN_UNKNOWN:
1617 default:
1618 switch (hwparam_gen) {
1619 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1620 if (DWC3_IP_IS(DWC32))
1621 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1622 else
1623 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1624 break;
1625 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1626 if (DWC3_IP_IS(DWC32))
1627 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1628 break;
1629 }
1630 break;
1631 }
1632 }
7ac51a12
JY		 1633}
1634
c5ac6116
FB		 1635static int dwc3_probe(struct platform_device *pdev)
1636{
1637 struct device *dev = &pdev->dev;
44feb8e6 1638 struct resource *res, dwc_res;
c5ac6116
FB		 1639 struct dwc3 *dwc;
1640
1641 int ret;
1642
1643 void __iomem *regs;
1644
1645 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1646 if (!dwc)
1647 return -ENOMEM;
1648
1649 dwc->dev = dev;
1650
1651 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1652 if (!res) {
1653 dev_err(dev, "missing memory resource\n");
1654 return -ENODEV;
1655 }
1656
1657 dwc->xhci_resources[0].start = res->start;
1658 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1659 DWC3_XHCI_REGS_END;
1660 dwc->xhci_resources[0].flags = res->flags;
1661 dwc->xhci_resources[0].name = res->name;
1662
c5ac6116
FB		 1663 /*
1664 * Request memory region but exclude xHCI regs,
1665 * since it will be requested by the xhci-plat driver.
1666 */
44feb8e6
MY		 1667 dwc_res = *res;
1668 dwc_res.start += DWC3_GLOBALS_REGS_START;
1669
1670 regs = devm_ioremap_resource(dev, &dwc_res);
1671 if (IS_ERR(regs))
1672 return PTR_ERR(regs);
c5ac6116
FB		 1673
1674 dwc->regs = regs;
44feb8e6 1675 dwc->regs_size = resource_size(&dwc_res);
c5ac6116
FB		 1676
1677 dwc3_get_properties(dwc);
1678
47ce4590
FA		 1679 if (!dwc->sysdev_is_parent) {
1680 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1681 if (ret)
1682 return ret;
1683 }
45d39448 1684
babbdfc9 1685 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
fe8abf33
MY		 1686 if (IS_ERR(dwc->reset))
1687 return PTR_ERR(dwc->reset);
1688
61527777 1689 if (dev->of_node) {
61527777
HG		 1690 /*
1691 * Clocks are optional, but new DT platforms should support all
1692 * clocks as required by the DT-binding.
4e64cd77
PG		 1693 * Some devices have different clock names in legacy device trees,
1694 * check for them to retain backwards compatibility.
61527777 1695 */
33fb697e
SA		 1696 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1697 if (IS_ERR(dwc->bus_clk))
1698 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1699 "could not get bus clock\n");
1700
4e64cd77
PG		 1701 if (dwc->bus_clk == NULL) {
1702 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1703 if (IS_ERR(dwc->bus_clk))
1704 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1705 "could not get bus clock\n");
1706 }
1707
33fb697e
SA		 1708 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1709 if (IS_ERR(dwc->ref_clk))
1710 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1711 "could not get ref clock\n");
1712
4e64cd77
PG		 1713 if (dwc->ref_clk == NULL) {
1714 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1715 if (IS_ERR(dwc->ref_clk))
1716 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1717 "could not get ref clock\n");
1718 }
1719
33fb697e
SA		 1720 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1721 if (IS_ERR(dwc->susp_clk))
1722 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1723 "could not get suspend clock\n");
4e64cd77
PG		 1724
1725 if (dwc->susp_clk == NULL) {
1726 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1727 if (IS_ERR(dwc->susp_clk))
1728 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1729 "could not get suspend clock\n");
1730 }
61527777 1731 }
fe8abf33
MY		 1732
1733 ret = reset_control_deassert(dwc->reset);
1734 if (ret)
03bf32bb 1735 return ret;
fe8abf33 1736
33fb697e 1737 ret = dwc3_clk_enable(dwc);
fe8abf33
MY		 1738 if (ret)
1739 goto assert_reset;
1740
dc1b5d9a
EBS		 1741 if (!dwc3_core_is_valid(dwc)) {
1742 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1743 ret = -ENODEV;
1744 goto disable_clks;
1745 }
1746
6c89cce0 1747 platform_set_drvdata(pdev, dwc);
2917e718 1748 dwc3_cache_hwparams(dwc);
6c89cce0 1749
72246da4 1750 spin_lock_init(&dwc->lock);
f88359e1 1751 mutex_init(&dwc->mutex);
72246da4 1752
fc8bb91b
FB		 1753 pm_runtime_set_active(dev);
1754 pm_runtime_use_autosuspend(dev);
1755 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
802ca850 1756 pm_runtime_enable(dev);
32808237
RQ		 1757 ret = pm_runtime_get_sync(dev);
1758 if (ret < 0)
1759 goto err1;
1760
802ca850 1761 pm_runtime_forbid(dev);
72246da4 1762
3921426b
FB		 1763 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1764 if (ret) {
1765 dev_err(dwc->dev, "failed to allocate event buffers\n");
1766 ret = -ENOMEM;
32808237 1767 goto err2;
3921426b
FB		 1768 }
1769
9d6173e1
TN		 1770 ret = dwc3_get_dr_mode(dwc);
1771 if (ret)
1772 goto err3;
32a4a135 1773
c499ff71
FB		 1774 ret = dwc3_alloc_scratch_buffers(dwc);
1775 if (ret)
32808237 1776 goto err3;
c499ff71 1777
72246da4
FB		 1778 ret = dwc3_core_init(dwc);
1779 if (ret) {
0c0a20f6 1780 dev_err_probe(dev, ret, "failed to initialize core\n");
32808237 1781 goto err4;
72246da4
FB		 1782 }
1783
7ac51a12 1784 dwc3_check_params(dwc);
84524d12 1785 dwc3_debugfs_init(dwc);
2c7f1bd9 1786
5f94adfe
FB		 1787 ret = dwc3_core_init_mode(dwc);
1788 if (ret)
32808237 1789 goto err5;
72246da4 1790
fc8bb91b 1791 pm_runtime_put(dev);
72246da4
FB		 1792
1793 return 0;
1794
32808237 1795err5:
84524d12 1796 dwc3_debugfs_exit(dwc);
c499ff71 1797 dwc3_event_buffers_cleanup(dwc);
03c1fd62
LJ		 1798
1799 usb_phy_shutdown(dwc->usb2_phy);
1800 usb_phy_shutdown(dwc->usb3_phy);
1801 phy_exit(dwc->usb2_generic_phy);
1802 phy_exit(dwc->usb3_generic_phy);
1803
1804 usb_phy_set_suspend(dwc->usb2_phy, 1);
1805 usb_phy_set_suspend(dwc->usb3_phy, 1);
1806 phy_power_off(dwc->usb2_generic_phy);
1807 phy_power_off(dwc->usb3_generic_phy);
1808
08fd9a82 1809 dwc3_ulpi_exit(dwc);
57303488 1810
32808237 1811err4:
c499ff71 1812 dwc3_free_scratch_buffers(dwc);
72246da4 1813
32808237 1814err3:
3921426b
FB		 1815 dwc3_free_event_buffers(dwc);
1816
32808237
RQ		 1817err2:
1818 pm_runtime_allow(&pdev->dev);
1819
1820err1:
1821 pm_runtime_put_sync(&pdev->dev);
1822 pm_runtime_disable(&pdev->dev);
1823
dc1b5d9a 1824disable_clks:
33fb697e 1825 dwc3_clk_disable(dwc);
fe8abf33
MY		 1826assert_reset:
1827 reset_control_assert(dwc->reset);
fe8abf33 1828
b0bf77cd 1829 if (dwc->usb_psy)
6f0764b5
RC		 1830 power_supply_put(dwc->usb_psy);
1831
72246da4
FB		 1832 return ret;
1833}
1834
fb4e98ab 1835static int dwc3_remove(struct platform_device *pdev)
72246da4 1836{
72246da4 1837 struct dwc3 *dwc = platform_get_drvdata(pdev);
3da1f6ee 1838
fc8bb91b 1839 pm_runtime_get_sync(&pdev->dev);
72246da4 1840
dc99f16f 1841 dwc3_core_exit_mode(dwc);
2a042767 1842 dwc3_debugfs_exit(dwc);
8ba007a9 1843
72246da4 1844 dwc3_core_exit(dwc);
88bc9d19 1845 dwc3_ulpi_exit(dwc);
72246da4 1846
72246da4 1847 pm_runtime_disable(&pdev->dev);
266d0493
LJ		 1848 pm_runtime_put_noidle(&pdev->dev);
1849 pm_runtime_set_suspended(&pdev->dev);
72246da4 1850
fc8bb91b
FB		 1851 dwc3_free_event_buffers(dwc);
1852 dwc3_free_scratch_buffers(dwc);
1853
b0bf77cd 1854 if (dwc->usb_psy)
6f0764b5
RC		 1855 power_supply_put(dwc->usb_psy);
1856
72246da4
FB		 1857 return 0;
1858}
1859
fc8bb91b 1860#ifdef CONFIG_PM
fe8abf33
MY		 1861static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1862{
1863 int ret;
1864
1865 ret = reset_control_deassert(dwc->reset);
1866 if (ret)
1867 return ret;
1868
33fb697e 1869 ret = dwc3_clk_enable(dwc);
fe8abf33
MY		 1870 if (ret)
1871 goto assert_reset;
1872
fe8abf33
MY		 1873 ret = dwc3_core_init(dwc);
1874 if (ret)
1875 goto disable_clks;
1876
1877 return 0;
1878
1879disable_clks:
33fb697e 1880 dwc3_clk_disable(dwc);
fe8abf33
MY		 1881assert_reset:
1882 reset_control_assert(dwc->reset);
1883
1884 return ret;
1885}
1886
c4a5153e 1887static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
7415f17c 1888{
fc8bb91b 1889 unsigned long flags;
bcb12877 1890 u32 reg;
7415f17c 1891
689bf72c
MG		 1892 switch (dwc->current_dr_role) {
1893 case DWC3_GCTL_PRTCAP_DEVICE:
0227cc84
LJ		 1894 if (pm_runtime_suspended(dwc->dev))
1895 break;
fc8bb91b 1896 spin_lock_irqsave(&dwc->lock, flags);
7415f17c 1897 dwc3_gadget_suspend(dwc);
fc8bb91b 1898 spin_unlock_irqrestore(&dwc->lock, flags);
41a91c60 1899 synchronize_irq(dwc->irq_gadget);
689bf72c 1900 dwc3_core_exit(dwc);
51f5d49a 1901 break;
689bf72c 1902 case DWC3_GCTL_PRTCAP_HOST:
bcb12877 1903 if (!PMSG_IS_AUTO(msg)) {
c4a5153e 1904 dwc3_core_exit(dwc);
bcb12877
MG		 1905 break;
1906 }
1907
1908 /* Let controller to suspend HSPHY before PHY driver suspends */
1909 if (dwc->dis_u2_susphy_quirk ||
1910 dwc->dis_enblslpm_quirk) {
1911 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1912 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1913 DWC3_GUSB2PHYCFG_SUSPHY;
1914 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1915
1916 /* Give some time for USB2 PHY to suspend */
1917 usleep_range(5000, 6000);
1918 }
1919
1920 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1921 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
c4a5153e 1922 break;
f09cc79b
RQ		 1923 case DWC3_GCTL_PRTCAP_OTG:
1924 /* do nothing during runtime_suspend */
1925 if (PMSG_IS_AUTO(msg))
1926 break;
1927
1928 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1929 spin_lock_irqsave(&dwc->lock, flags);
1930 dwc3_gadget_suspend(dwc);
1931 spin_unlock_irqrestore(&dwc->lock, flags);
41a91c60 1932 synchronize_irq(dwc->irq_gadget);
f09cc79b
RQ		 1933 }
1934
1935 dwc3_otg_exit(dwc);
1936 dwc3_core_exit(dwc);
1937 break;
7415f17c 1938 default:
51f5d49a 1939 /* do nothing */
7415f17c
FB		 1940 break;
1941 }
1942
7415f17c
FB		 1943 return 0;
1944}
1945
c4a5153e 1946static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
7415f17c 1947{
fc8bb91b 1948 unsigned long flags;
57303488 1949 int ret;
bcb12877 1950 u32 reg;
7415f17c 1951
689bf72c
MG		 1952 switch (dwc->current_dr_role) {
1953 case DWC3_GCTL_PRTCAP_DEVICE:
fe8abf33 1954 ret = dwc3_core_init_for_resume(dwc);
689bf72c
MG		 1955 if (ret)
1956 return ret;
5c4ad318 1957
7d11c3ac 1958 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
fc8bb91b 1959 spin_lock_irqsave(&dwc->lock, flags);
7415f17c 1960 dwc3_gadget_resume(dwc);
fc8bb91b 1961 spin_unlock_irqrestore(&dwc->lock, flags);
689bf72c
MG		 1962 break;
1963 case DWC3_GCTL_PRTCAP_HOST:
c4a5153e 1964 if (!PMSG_IS_AUTO(msg)) {
fe8abf33 1965 ret = dwc3_core_init_for_resume(dwc);
c4a5153e
MG		 1966 if (ret)
1967 return ret;
7d11c3ac 1968 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
bcb12877 1969 break;
c4a5153e 1970 }
bcb12877
MG		 1971 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1972 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1973 if (dwc->dis_u2_susphy_quirk)
1974 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1975
1976 if (dwc->dis_enblslpm_quirk)
1977 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1978
1979 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1980
1981 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1982 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
f09cc79b
RQ		 1983 break;
1984 case DWC3_GCTL_PRTCAP_OTG:
1985 /* nothing to do on runtime_resume */
1986 if (PMSG_IS_AUTO(msg))
1987 break;
1988
0e5a3c82 1989 ret = dwc3_core_init_for_resume(dwc);
f09cc79b
RQ		 1990 if (ret)
1991 return ret;
1992
1993 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1994
1995 dwc3_otg_init(dwc);
1996 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1997 dwc3_otg_host_init(dwc);
1998 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1999 spin_lock_irqsave(&dwc->lock, flags);
2000 dwc3_gadget_resume(dwc);
2001 spin_unlock_irqrestore(&dwc->lock, flags);
c4a5153e 2002 }
f09cc79b 2003
c4a5153e 2004 break;
7415f17c
FB		 2005 default:
2006 /* do nothing */
2007 break;
2008 }
2009
fc8bb91b
FB		 2010 return 0;
2011}
2012
2013static int dwc3_runtime_checks(struct dwc3 *dwc)
2014{
689bf72c 2015 switch (dwc->current_dr_role) {
c4a5153e 2016 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 2017 if (dwc->connected)
2018 return -EBUSY;
2019 break;
c4a5153e 2020 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 2021 default:
2022 /* do nothing */
2023 break;
2024 }
2025
2026 return 0;
2027}
2028
2029static int dwc3_runtime_suspend(struct device *dev)
2030{
2031 struct dwc3 *dwc = dev_get_drvdata(dev);
2032 int ret;
2033
2034 if (dwc3_runtime_checks(dwc))
2035 return -EBUSY;
2036
c4a5153e 2037 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
fc8bb91b
FB		 2038 if (ret)
2039 return ret;
2040
2041 device_init_wakeup(dev, true);
2042
2043 return 0;
2044}
2045
2046static int dwc3_runtime_resume(struct device *dev)
2047{
2048 struct dwc3 *dwc = dev_get_drvdata(dev);
2049 int ret;
2050
2051 device_init_wakeup(dev, false);
2052
c4a5153e 2053 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
fc8bb91b
FB		 2054 if (ret)
2055 return ret;
2056
689bf72c
MG		 2057 switch (dwc->current_dr_role) {
2058 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 2059 dwc3_gadget_process_pending_events(dwc);
2060 break;
689bf72c 2061 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 2062 default:
2063 /* do nothing */
2064 break;
2065 }
2066
2067 pm_runtime_mark_last_busy(dev);
2068
2069 return 0;
2070}
2071
2072static int dwc3_runtime_idle(struct device *dev)
2073{
2074 struct dwc3 *dwc = dev_get_drvdata(dev);
2075
689bf72c
MG		 2076 switch (dwc->current_dr_role) {
2077 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 2078 if (dwc3_runtime_checks(dwc))
2079 return -EBUSY;
2080 break;
689bf72c 2081 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 2082 default:
2083 /* do nothing */
2084 break;
2085 }
2086
2087 pm_runtime_mark_last_busy(dev);
2088 pm_runtime_autosuspend(dev);
2089
2090 return 0;
2091}
2092#endif /* CONFIG_PM */
2093
2094#ifdef CONFIG_PM_SLEEP
2095static int dwc3_suspend(struct device *dev)
2096{
2097 struct dwc3 *dwc = dev_get_drvdata(dev);
2098 int ret;
2099
c4a5153e 2100 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
fc8bb91b
FB		 2101 if (ret)
2102 return ret;
2103
2104 pinctrl_pm_select_sleep_state(dev);
2105
2106 return 0;
2107}
2108
2109static int dwc3_resume(struct device *dev)
2110{
2111 struct dwc3 *dwc = dev_get_drvdata(dev);
2112 int ret;
2113
2114 pinctrl_pm_select_default_state(dev);
2115
c4a5153e 2116 ret = dwc3_resume_common(dwc, PMSG_RESUME);
fc8bb91b
FB		 2117 if (ret)
2118 return ret;
2119
7415f17c
FB		 2120 pm_runtime_disable(dev);
2121 pm_runtime_set_active(dev);
2122 pm_runtime_enable(dev);
2123
2124 return 0;
2125}
f580170f
YC		 2126
2127static void dwc3_complete(struct device *dev)
2128{
2129 struct dwc3 *dwc = dev_get_drvdata(dev);
2130 u32 reg;
2131
2132 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2133 dwc->dis_split_quirk) {
2134 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2135 reg |= DWC3_GUCTL3_SPLITDISABLE;
2136 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2137 }
2138}
2139#else
2140#define dwc3_complete NULL
7f370ed0 2141#endif /* CONFIG_PM_SLEEP */
7415f17c
FB		 2142
2143static const struct dev_pm_ops dwc3_dev_pm_ops = {
7415f17c 2144 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
f580170f 2145 .complete = dwc3_complete,
fc8bb91b
FB		 2146 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2147 dwc3_runtime_idle)
7415f17c
FB		 2148};
2149
5088b6f5
KVA		 2150#ifdef CONFIG_OF
2151static const struct of_device_id of_dwc3_match[] = {
22a5aa17
FB		 2152 {
2153 .compatible = "snps,dwc3"
2154 },
5088b6f5
KVA		 2155 {
2156 .compatible = "synopsys,dwc3"
2157 },
2158 { },
2159};
2160MODULE_DEVICE_TABLE(of, of_dwc3_match);
2161#endif
2162
404905a6
HK		 2163#ifdef CONFIG_ACPI
2164
2165#define ACPI_ID_INTEL_BSW "808622B7"
2166
2167static const struct acpi_device_id dwc3_acpi_match[] = {
2168 { ACPI_ID_INTEL_BSW, 0 },
2169 { },
2170};
2171MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2172#endif
2173
72246da4
FB		 2174static struct platform_driver dwc3_driver = {
2175 .probe = dwc3_probe,
7690417d 2176 .remove = dwc3_remove,
72246da4
FB		 2177 .driver = {
2178 .name = "dwc3",
5088b6f5 2179 .of_match_table = of_match_ptr(of_dwc3_match),
404905a6 2180 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
7f370ed0 2181 .pm = &dwc3_dev_pm_ops,
72246da4 2182 },
72246da4
FB		 2183};
2184
b1116dcc
TK		 2185module_platform_driver(dwc3_driver);
2186
7ae4fc4d 2187MODULE_ALIAS("platform:dwc3");
72246da4 2188MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
5945f789 2189MODULE_LICENSE("GPL v2");
72246da4 2190MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux 6.x block layer and io_uring tree(s)