projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
usb: gadget: udc: renesas_usb3: Add register of usb role switch
[linux-block.git] / drivers / usb / dwc3 / core.c
CommitLineData
5fd54ace 1// SPDX-License-Identifier: GPL-2.0
72246da4
FB		 2/**
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
72246da4
FB		 9 */
10
fe8abf33 11#include <linux/clk.h>
fa0ea13e 12#include <linux/version.h>
a72e658b 13#include <linux/module.h>
72246da4
FB		 14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/io.h>
22#include <linux/list.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
457e84b6 25#include <linux/of.h>
404905a6 26#include <linux/acpi.h>
6344475f 27#include <linux/pinctrl/consumer.h>
fe8abf33 28#include <linux/reset.h>
72246da4
FB		 29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
f7e846f0 32#include <linux/usb/of.h>
a45c82b8 33#include <linux/usb/otg.h>
72246da4
FB		 34
35#include "core.h"
36#include "gadget.h"
37#include "io.h"
38
39#include "debug.h"
40
fc8bb91b 41#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
8300dd23 42
9d6173e1
TN		 43/**
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
46 */
47static int dwc3_get_dr_mode(struct dwc3 *dwc)
48{
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
51 unsigned int hw_mode;
52
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
55
56 mode = dwc->dr_mode;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
58
59 switch (hw_mode) {
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
62 dev_err(dev,
63 "Controller does not support host mode.\n");
64 return -EINVAL;
65 }
66 mode = USB_DR_MODE_PERIPHERAL;
67 break;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
70 dev_err(dev,
71 "Controller does not support device mode.\n");
72 return -EINVAL;
73 }
74 mode = USB_DR_MODE_HOST;
75 break;
76 default:
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
81 }
82
83 if (mode != dwc->dr_mode) {
84 dev_warn(dev,
85 "Configuration mismatch. dr_mode forced to %s\n",
86 mode == USB_DR_MODE_HOST ? "host" : "gadget");
87
88 dwc->dr_mode = mode;
89 }
90
91 return 0;
92}
93
f09cc79b 94void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
3140e8cb
SAS		 95{
96 u32 reg;
97
98 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
99 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
100 reg |= DWC3_GCTL_PRTCAPDIR(mode);
101 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
c4a5153e
MG		 102
103 dwc->current_dr_role = mode;
41ce1456
RQ		 104}
105
106static void __dwc3_set_mode(struct work_struct *work)
107{
108 struct dwc3 *dwc = work_to_dwc(work);
109 unsigned long flags;
110 int ret;
111
f09cc79b 112 if (dwc->dr_mode != USB_DR_MODE_OTG)
41ce1456
RQ		 113 return;
114
f09cc79b
RQ		 115 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
116 dwc3_otg_update(dwc, 0);
117
41ce1456
RQ		 118 if (!dwc->desired_dr_role)
119 return;
120
121 if (dwc->desired_dr_role == dwc->current_dr_role)
122 return;
123
f09cc79b 124 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
41ce1456
RQ		 125 return;
126
127 switch (dwc->current_dr_role) {
128 case DWC3_GCTL_PRTCAP_HOST:
129 dwc3_host_exit(dwc);
130 break;
131 case DWC3_GCTL_PRTCAP_DEVICE:
132 dwc3_gadget_exit(dwc);
133 dwc3_event_buffers_cleanup(dwc);
134 break;
f09cc79b
RQ		 135 case DWC3_GCTL_PRTCAP_OTG:
136 dwc3_otg_exit(dwc);
137 spin_lock_irqsave(&dwc->lock, flags);
138 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
139 spin_unlock_irqrestore(&dwc->lock, flags);
140 dwc3_otg_update(dwc, 1);
141 break;
41ce1456
RQ		 142 default:
143 break;
144 }
145
146 spin_lock_irqsave(&dwc->lock, flags);
147
148 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
6b3261a2 149
41ce1456
RQ		 150 spin_unlock_irqrestore(&dwc->lock, flags);
151
152 switch (dwc->desired_dr_role) {
153 case DWC3_GCTL_PRTCAP_HOST:
154 ret = dwc3_host_init(dwc);
958d1a4c 155 if (ret) {
41ce1456 156 dev_err(dwc->dev, "failed to initialize host\n");
958d1a4c
FB		 157 } else {
158 if (dwc->usb2_phy)
159 otg_set_vbus(dwc->usb2_phy->otg, true);
644cbbc3
MG		 160 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
161 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
d8c80bb3 162 phy_calibrate(dwc->usb2_generic_phy);
958d1a4c 163 }
41ce1456
RQ		 164 break;
165 case DWC3_GCTL_PRTCAP_DEVICE:
166 dwc3_event_buffers_setup(dwc);
958d1a4c
FB		 167
168 if (dwc->usb2_phy)
169 otg_set_vbus(dwc->usb2_phy->otg, false);
644cbbc3
MG		 170 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
171 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
958d1a4c 172
41ce1456
RQ		 173 ret = dwc3_gadget_init(dwc);
174 if (ret)
175 dev_err(dwc->dev, "failed to initialize peripheral\n");
176 break;
f09cc79b
RQ		 177 case DWC3_GCTL_PRTCAP_OTG:
178 dwc3_otg_init(dwc);
179 dwc3_otg_update(dwc, 0);
180 break;
41ce1456
RQ		 181 default:
182 break;
183 }
f09cc79b 184
41ce1456
RQ		 185}
186
187void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
188{
189 unsigned long flags;
190
191 spin_lock_irqsave(&dwc->lock, flags);
192 dwc->desired_dr_role = mode;
193 spin_unlock_irqrestore(&dwc->lock, flags);
194
084a804e 195 queue_work(system_freezable_wq, &dwc->drd_work);
3140e8cb 196}
8300dd23 197
cf6d867d
FB		 198u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
199{
200 struct dwc3 *dwc = dep->dwc;
201 u32 reg;
202
203 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
204 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
205 DWC3_GDBGFIFOSPACE_TYPE(type));
206
207 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
208
209 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
210}
211
72246da4
FB		 212/**
213 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
214 * @dwc: pointer to our context structure
215 */
57303488 216static int dwc3_core_soft_reset(struct dwc3 *dwc)
72246da4
FB		 217{
218 u32 reg;
f59dcab1 219 int retries = 1000;
57303488 220 int ret;
72246da4 221
51e1e7bc
FB		 222 usb_phy_init(dwc->usb2_phy);
223 usb_phy_init(dwc->usb3_phy);
57303488
KVA		 224 ret = phy_init(dwc->usb2_generic_phy);
225 if (ret < 0)
226 return ret;
227
228 ret = phy_init(dwc->usb3_generic_phy);
229 if (ret < 0) {
230 phy_exit(dwc->usb2_generic_phy);
231 return ret;
232 }
72246da4 233
f59dcab1
FB		 234 /*
235 * We're resetting only the device side because, if we're in host mode,
236 * XHCI driver will reset the host block. If dwc3 was configured for
237 * host-only mode, then we can return early.
238 */
c4a5153e 239 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
f59dcab1 240 return 0;
72246da4 241
f59dcab1
FB		 242 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
243 reg |= DWC3_DCTL_CSFTRST;
244 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 245
f59dcab1
FB		 246 do {
247 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
248 if (!(reg & DWC3_DCTL_CSFTRST))
fab38333 249 goto done;
45627ac6 250
f59dcab1
FB		 251 udelay(1);
252 } while (--retries);
57303488 253
00b42170
BN		 254 phy_exit(dwc->usb3_generic_phy);
255 phy_exit(dwc->usb2_generic_phy);
256
f59dcab1 257 return -ETIMEDOUT;
fab38333
TN		 258
259done:
260 /*
261 * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
262 * we must wait at least 50ms before accessing the PHY domain
263 * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
264 */
265 if (dwc3_is_usb31(dwc))
266 msleep(50);
267
268 return 0;
72246da4
FB		 269}
270
fe8abf33
MY		 271static const struct clk_bulk_data dwc3_core_clks[] = {
272 { .id = "ref" },
273 { .id = "bus_early" },
274 { .id = "suspend" },
275};
276
db2be4e9
NB		 277/*
278 * dwc3_frame_length_adjustment - Adjusts frame length if required
279 * @dwc3: Pointer to our controller context structure
db2be4e9 280 */
bcdb3272 281static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
db2be4e9
NB		 282{
283 u32 reg;
284 u32 dft;
285
286 if (dwc->revision < DWC3_REVISION_250A)
287 return;
288
bcdb3272 289 if (dwc->fladj == 0)
db2be4e9
NB		 290 return;
291
292 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
293 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
bcdb3272 294 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
db2be4e9
NB		 295 "request value same as default, ignoring\n")) {
296 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
bcdb3272 297 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
db2be4e9
NB		 298 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
299 }
300}
301
72246da4
FB		 302/**
303 * dwc3_free_one_event_buffer - Frees one event buffer
304 * @dwc: Pointer to our controller context structure
305 * @evt: Pointer to event buffer to be freed
306 */
307static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
308 struct dwc3_event_buffer *evt)
309{
d64ff406 310 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
72246da4
FB		 311}
312
313/**
1d046793 314 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
72246da4
FB		 315 * @dwc: Pointer to our controller context structure
316 * @length: size of the event buffer
317 *
1d046793 318 * Returns a pointer to the allocated event buffer structure on success
72246da4
FB		 319 * otherwise ERR_PTR(errno).
320 */
67d0b500
FB		 321static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
322 unsigned length)
72246da4
FB		 323{
324 struct dwc3_event_buffer *evt;
325
380f0d28 326 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
72246da4
FB		 327 if (!evt)
328 return ERR_PTR(-ENOMEM);
329
330 evt->dwc = dwc;
331 evt->length = length;
d9fa4c63
JY		 332 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
333 if (!evt->cache)
334 return ERR_PTR(-ENOMEM);
335
d64ff406 336 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
72246da4 337 &evt->dma, GFP_KERNEL);
e32672f0 338 if (!evt->buf)
72246da4 339 return ERR_PTR(-ENOMEM);
72246da4
FB		 340
341 return evt;
342}
343
344/**
345 * dwc3_free_event_buffers - frees all allocated event buffers
346 * @dwc: Pointer to our controller context structure
347 */
348static void dwc3_free_event_buffers(struct dwc3 *dwc)
349{
350 struct dwc3_event_buffer *evt;
72246da4 351
696c8b12 352 evt = dwc->ev_buf;
660e9bde
FB		 353 if (evt)
354 dwc3_free_one_event_buffer(dwc, evt);
72246da4
FB		 355}
356
357/**
358 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
1d046793 359 * @dwc: pointer to our controller context structure
72246da4
FB		 360 * @length: size of event buffer
361 *
1d046793 362 * Returns 0 on success otherwise negative errno. In the error case, dwc
72246da4
FB		 363 * may contain some buffers allocated but not all which were requested.
364 */
41ac7b3a 365static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
72246da4 366{
660e9bde 367 struct dwc3_event_buffer *evt;
72246da4 368
660e9bde
FB		 369 evt = dwc3_alloc_one_event_buffer(dwc, length);
370 if (IS_ERR(evt)) {
371 dev_err(dwc->dev, "can't allocate event buffer\n");
372 return PTR_ERR(evt);
72246da4 373 }
696c8b12 374 dwc->ev_buf = evt;
72246da4
FB		 375
376 return 0;
377}
378
379/**
380 * dwc3_event_buffers_setup - setup our allocated event buffers
1d046793 381 * @dwc: pointer to our controller context structure
72246da4
FB		 382 *
383 * Returns 0 on success otherwise negative errno.
384 */
f09cc79b 385int dwc3_event_buffers_setup(struct dwc3 *dwc)
72246da4
FB		 386{
387 struct dwc3_event_buffer *evt;
72246da4 388
696c8b12 389 evt = dwc->ev_buf;
660e9bde 390 evt->lpos = 0;
660e9bde
FB		 391 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
392 lower_32_bits(evt->dma));
393 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
394 upper_32_bits(evt->dma));
395 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
396 DWC3_GEVNTSIZ_SIZE(evt->length));
397 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 398
399 return 0;
400}
401
f09cc79b 402void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
72246da4
FB		 403{
404 struct dwc3_event_buffer *evt;
72246da4 405
696c8b12 406 evt = dwc->ev_buf;
7acd85e0 407
660e9bde 408 evt->lpos = 0;
7acd85e0 409
660e9bde
FB		 410 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
411 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
412 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
413 | DWC3_GEVNTSIZ_SIZE(0));
414 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 415}
416
0ffcaf37
FB		 417static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
418{
419 if (!dwc->has_hibernation)
420 return 0;
421
422 if (!dwc->nr_scratch)
423 return 0;
424
425 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
426 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
427 if (!dwc->scratchbuf)
428 return -ENOMEM;
429
430 return 0;
431}
432
433static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
434{
435 dma_addr_t scratch_addr;
436 u32 param;
437 int ret;
438
439 if (!dwc->has_hibernation)
440 return 0;
441
442 if (!dwc->nr_scratch)
443 return 0;
444
445 /* should never fall here */
446 if (!WARN_ON(dwc->scratchbuf))
447 return 0;
448
d64ff406 449 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
0ffcaf37
FB		 450 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
451 DMA_BIDIRECTIONAL);
d64ff406
AB		 452 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
453 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
0ffcaf37
FB		 454 ret = -EFAULT;
455 goto err0;
456 }
457
458 dwc->scratch_addr = scratch_addr;
459
460 param = lower_32_bits(scratch_addr);
461
462 ret = dwc3_send_gadget_generic_command(dwc,
463 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
464 if (ret < 0)
465 goto err1;
466
467 param = upper_32_bits(scratch_addr);
468
469 ret = dwc3_send_gadget_generic_command(dwc,
470 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
471 if (ret < 0)
472 goto err1;
473
474 return 0;
475
476err1:
d64ff406 477 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
0ffcaf37
FB		 478 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
479
480err0:
481 return ret;
482}
483
484static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
485{
486 if (!dwc->has_hibernation)
487 return;
488
489 if (!dwc->nr_scratch)
490 return;
491
492 /* should never fall here */
493 if (!WARN_ON(dwc->scratchbuf))
494 return;
495
d64ff406 496 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
0ffcaf37
FB		 497 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
498 kfree(dwc->scratchbuf);
499}
500
789451f6
FB		 501static void dwc3_core_num_eps(struct dwc3 *dwc)
502{
503 struct dwc3_hwparams *parms = &dwc->hwparams;
504
47d3946e 505 dwc->num_eps = DWC3_NUM_EPS(parms);
789451f6
FB		 506}
507
41ac7b3a 508static void dwc3_cache_hwparams(struct dwc3 *dwc)
26ceca97
FB		 509{
510 struct dwc3_hwparams *parms = &dwc->hwparams;
511
512 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
513 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
514 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
515 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
516 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
517 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
518 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
519 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
520 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
521}
522
98112041
RQ		 523static int dwc3_core_ulpi_init(struct dwc3 *dwc)
524{
525 int intf;
526 int ret = 0;
527
528 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
529
530 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
531 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
532 dwc->hsphy_interface &&
533 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
534 ret = dwc3_ulpi_init(dwc);
535
536 return ret;
537}
538
b5a65c40
HR		 539/**
540 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
541 * @dwc: Pointer to our controller context structure
88bc9d19
HK		 542 *
543 * Returns 0 on success. The USB PHY interfaces are configured but not
544 * initialized. The PHY interfaces and the PHYs get initialized together with
545 * the core in dwc3_core_init.
b5a65c40 546 */
88bc9d19 547static int dwc3_phy_setup(struct dwc3 *dwc)
b5a65c40
HR		 548{
549 u32 reg;
550
551 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
552
1966b865
FB		 553 /*
554 * Make sure UX_EXIT_PX is cleared as that causes issues with some
555 * PHYs. Also, this bit is not supposed to be used in normal operation.
556 */
557 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
558
2164a476
HR		 559 /*
560 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
561 * to '0' during coreConsultant configuration. So default value
562 * will be '0' when the core is reset. Application needs to set it
563 * to '1' after the core initialization is completed.
564 */
565 if (dwc->revision > DWC3_REVISION_194A)
566 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
567
b5a65c40
HR		 568 if (dwc->u2ss_inp3_quirk)
569 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
570
e58dd357
RB		 571 if (dwc->dis_rxdet_inp3_quirk)
572 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
573
df31f5b3
HR		 574 if (dwc->req_p1p2p3_quirk)
575 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
576
a2a1d0f5
HR		 577 if (dwc->del_p1p2p3_quirk)
578 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
579
41c06ffd
HR		 580 if (dwc->del_phy_power_chg_quirk)
581 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
582
fb67afca
HR		 583 if (dwc->lfps_filter_quirk)
584 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
585
14f4ac53
HR		 586 if (dwc->rx_detect_poll_quirk)
587 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
588
6b6a0c9a
HR		 589 if (dwc->tx_de_emphasis_quirk)
590 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
591
cd72f890 592 if (dwc->dis_u3_susphy_quirk)
59acfa20
HR		 593 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
594
00fe081d
WW		 595 if (dwc->dis_del_phy_power_chg_quirk)
596 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
597
b5a65c40
HR		 598 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
599
2164a476
HR		 600 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
601
3e10a2ce
HK		 602 /* Select the HS PHY interface */
603 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
604 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
43cacb03
FB		 605 if (dwc->hsphy_interface &&
606 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
3e10a2ce 607 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 608 break;
43cacb03
FB		 609 } else if (dwc->hsphy_interface &&
610 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
3e10a2ce 611 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 612 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
3e10a2ce 613 } else {
88bc9d19
HK		 614 /* Relying on default value. */
615 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
616 break;
3e10a2ce
HK		 617 }
618 /* FALLTHROUGH */
88bc9d19 619 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
88bc9d19 620 /* FALLTHROUGH */
3e10a2ce
HK		 621 default:
622 break;
623 }
624
32f2ed86
WW		 625 switch (dwc->hsphy_mode) {
626 case USBPHY_INTERFACE_MODE_UTMI:
627 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
628 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
629 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
630 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
631 break;
632 case USBPHY_INTERFACE_MODE_UTMIW:
633 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
634 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
635 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
636 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
637 break;
638 default:
639 break;
640 }
641
2164a476
HR		 642 /*
643 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
644 * '0' during coreConsultant configuration. So default value will
645 * be '0' when the core is reset. Application needs to set it to
646 * '1' after the core initialization is completed.
647 */
648 if (dwc->revision > DWC3_REVISION_194A)
649 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
650
cd72f890 651 if (dwc->dis_u2_susphy_quirk)
0effe0a3
HR		 652 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
653
ec791d14
JY		 654 if (dwc->dis_enblslpm_quirk)
655 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
656
16199f33
WW		 657 if (dwc->dis_u2_freeclk_exists_quirk)
658 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
659
2164a476 660 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
88bc9d19
HK		 661
662 return 0;
b5a65c40
HR		 663}
664
c499ff71
FB		 665static void dwc3_core_exit(struct dwc3 *dwc)
666{
667 dwc3_event_buffers_cleanup(dwc);
668
669 usb_phy_shutdown(dwc->usb2_phy);
670 usb_phy_shutdown(dwc->usb3_phy);
671 phy_exit(dwc->usb2_generic_phy);
672 phy_exit(dwc->usb3_generic_phy);
673
674 usb_phy_set_suspend(dwc->usb2_phy, 1);
675 usb_phy_set_suspend(dwc->usb3_phy, 1);
676 phy_power_off(dwc->usb2_generic_phy);
677 phy_power_off(dwc->usb3_generic_phy);
fe8abf33
MY		 678 clk_bulk_disable(dwc->num_clks, dwc->clks);
679 clk_bulk_unprepare(dwc->num_clks, dwc->clks);
680 reset_control_assert(dwc->reset);
c499ff71
FB		 681}
682
0759956f 683static bool dwc3_core_is_valid(struct dwc3 *dwc)
72246da4 684{
0759956f 685 u32 reg;
72246da4 686
7650bd74 687 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
0759956f 688
7650bd74 689 /* This should read as U3 followed by revision number */
690fb371
JY		 690 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
691 /* Detected DWC_usb3 IP */
692 dwc->revision = reg;
693 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
694 /* Detected DWC_usb31 IP */
695 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
696 dwc->revision |= DWC3_REVISION_IS_DWC31;
697 } else {
0759956f 698 return false;
7650bd74 699 }
7650bd74 700
0759956f
FB		 701 return true;
702}
58a0f23f 703
941f918e 704static void dwc3_core_setup_global_control(struct dwc3 *dwc)
0759956f 705{
941f918e
FB		 706 u32 hwparams4 = dwc->hwparams.hwparams4;
707 u32 reg;
c499ff71 708
4878a028 709 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
3e87c42a 710 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
4878a028 711
164d7731 712 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
4878a028 713 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
32a4a135
FB		 714 /**
715 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
716 * issue which would cause xHCI compliance tests to fail.
717 *
718 * Because of that we cannot enable clock gating on such
719 * configurations.
720 *
721 * Refers to:
722 *
723 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
724 * SOF/ITP Mode Used
725 */
726 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
727 dwc->dr_mode == USB_DR_MODE_OTG) &&
728 (dwc->revision >= DWC3_REVISION_210A &&
729 dwc->revision <= DWC3_REVISION_250A))
730 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
731 else
732 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
4878a028 733 break;
0ffcaf37
FB		 734 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
735 /* enable hibernation here */
736 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
2eac3992
HR		 737
738 /*
739 * REVISIT Enabling this bit so that host-mode hibernation
740 * will work. Device-mode hibernation is not yet implemented.
741 */
742 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
0ffcaf37 743 break;
4878a028 744 default:
5eb30ced
FB		 745 /* nothing */
746 break;
4878a028
SAS		 747 }
748
946bd579
HR		 749 /* check if current dwc3 is on simulation board */
750 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
5eb30ced 751 dev_info(dwc->dev, "Running with FPGA optmizations\n");
946bd579
HR		 752 dwc->is_fpga = true;
753 }
754
3b81221a
HR		 755 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
756 "disable_scramble cannot be used on non-FPGA builds\n");
757
758 if (dwc->disable_scramble_quirk && dwc->is_fpga)
759 reg |= DWC3_GCTL_DISSCRAMBLE;
760 else
761 reg &= ~DWC3_GCTL_DISSCRAMBLE;
762
9a5b2f31
HR		 763 if (dwc->u2exit_lfps_quirk)
764 reg |= DWC3_GCTL_U2EXIT_LFPS;
765
4878a028
SAS		 766 /*
767 * WORKAROUND: DWC3 revisions <1.90a have a bug
1d046793 768 * where the device can fail to connect at SuperSpeed
4878a028 769 * and falls back to high-speed mode which causes
1d046793 770 * the device to enter a Connect/Disconnect loop
4878a028
SAS		 771 */
772 if (dwc->revision < DWC3_REVISION_190A)
773 reg |= DWC3_GCTL_U2RSTECN;
774
775 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
941f918e
FB		 776}
777
f54edb53 778static int dwc3_core_get_phy(struct dwc3 *dwc);
98112041 779static int dwc3_core_ulpi_init(struct dwc3 *dwc);
f54edb53 780
d9612c2f
PM		 781/* set global incr burst type configuration registers */
782static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
783{
784 struct device *dev = dwc->dev;
785 /* incrx_mode : for INCR burst type. */
786 bool incrx_mode;
787 /* incrx_size : for size of INCRX burst. */
788 u32 incrx_size;
789 u32 *vals;
790 u32 cfg;
791 int ntype;
792 int ret;
793 int i;
794
795 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
796
797 /*
798 * Handle property "snps,incr-burst-type-adjustment".
799 * Get the number of value from this property:
800 * result <= 0, means this property is not supported.
801 * result = 1, means INCRx burst mode supported.
802 * result > 1, means undefined length burst mode supported.
803 */
804 ntype = device_property_read_u32_array(dev,
805 "snps,incr-burst-type-adjustment", NULL, 0);
806 if (ntype <= 0)
807 return;
808
809 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
810 if (!vals) {
811 dev_err(dev, "Error to get memory\n");
812 return;
813 }
814
815 /* Get INCR burst type, and parse it */
816 ret = device_property_read_u32_array(dev,
817 "snps,incr-burst-type-adjustment", vals, ntype);
818 if (ret) {
819 dev_err(dev, "Error to get property\n");
820 return;
821 }
822
823 incrx_size = *vals;
824
825 if (ntype > 1) {
826 /* INCRX (undefined length) burst mode */
827 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
828 for (i = 1; i < ntype; i++) {
829 if (vals[i] > incrx_size)
830 incrx_size = vals[i];
831 }
832 } else {
833 /* INCRX burst mode */
834 incrx_mode = INCRX_BURST_MODE;
835 }
836
837 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
838 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
839 if (incrx_mode)
840 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
841 switch (incrx_size) {
842 case 256:
843 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
844 break;
845 case 128:
846 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
847 break;
848 case 64:
849 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
850 break;
851 case 32:
852 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
853 break;
854 case 16:
855 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
856 break;
857 case 8:
858 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
859 break;
860 case 4:
861 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
862 break;
863 case 1:
864 break;
865 default:
866 dev_err(dev, "Invalid property\n");
867 break;
868 }
869
870 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
871}
872
941f918e
FB		 873/**
874 * dwc3_core_init - Low-level initialization of DWC3 Core
875 * @dwc: Pointer to our controller context structure
876 *
877 * Returns 0 on success otherwise negative errno.
878 */
879static int dwc3_core_init(struct dwc3 *dwc)
880{
881 u32 reg;
882 int ret;
883
884 if (!dwc3_core_is_valid(dwc)) {
885 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
886 ret = -ENODEV;
887 goto err0;
888 }
889
890 /*
891 * Write Linux Version Code to our GUID register so it's easy to figure
892 * out which kernel version a bug was found.
893 */
894 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
895
896 /* Handle USB2.0-only core configuration */
897 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
898 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
899 if (dwc->maximum_speed == USB_SPEED_SUPER)
900 dwc->maximum_speed = USB_SPEED_HIGH;
901 }
902
98112041 903 ret = dwc3_phy_setup(dwc);
941f918e
FB		 904 if (ret)
905 goto err0;
4878a028 906
98112041
RQ		 907 if (!dwc->ulpi_ready) {
908 ret = dwc3_core_ulpi_init(dwc);
909 if (ret)
910 goto err0;
911 dwc->ulpi_ready = true;
912 }
4878a028 913
98112041
RQ		 914 if (!dwc->phys_ready) {
915 ret = dwc3_core_get_phy(dwc);
916 if (ret)
917 goto err0a;
918 dwc->phys_ready = true;
919 }
920
921 ret = dwc3_core_soft_reset(dwc);
f54edb53 922 if (ret)
98112041 923 goto err0a;
f54edb53 924
941f918e 925 dwc3_core_setup_global_control(dwc);
c499ff71 926 dwc3_core_num_eps(dwc);
0ffcaf37
FB		 927
928 ret = dwc3_setup_scratch_buffers(dwc);
929 if (ret)
c499ff71
FB		 930 goto err1;
931
932 /* Adjust Frame Length */
933 dwc3_frame_length_adjustment(dwc);
934
d9612c2f
PM		 935 dwc3_set_incr_burst_type(dwc);
936
c499ff71
FB		 937 usb_phy_set_suspend(dwc->usb2_phy, 0);
938 usb_phy_set_suspend(dwc->usb3_phy, 0);
939 ret = phy_power_on(dwc->usb2_generic_phy);
940 if (ret < 0)
0ffcaf37
FB		 941 goto err2;
942
c499ff71
FB		 943 ret = phy_power_on(dwc->usb3_generic_phy);
944 if (ret < 0)
945 goto err3;
946
947 ret = dwc3_event_buffers_setup(dwc);
948 if (ret) {
949 dev_err(dwc->dev, "failed to setup event buffers\n");
950 goto err4;
951 }
952
06281d46
JY		 953 /*
954 * ENDXFER polling is available on version 3.10a and later of
955 * the DWC_usb3 controller. It is NOT available in the
956 * DWC_usb31 controller.
957 */
958 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
959 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
960 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
961 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
962 }
963
65db7a0c 964 if (dwc->revision >= DWC3_REVISION_250A) {
0bb39ca1 965 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
65db7a0c
WW		 966
967 /*
968 * Enable hardware control of sending remote wakeup
969 * in HS when the device is in the L1 state.
970 */
971 if (dwc->revision >= DWC3_REVISION_290A)
972 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
973
974 if (dwc->dis_tx_ipgap_linecheck_quirk)
975 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
976
0bb39ca1
JY		 977 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
978 }
979
938a5ad1
TN		 980 /*
981 * Must config both number of packets and max burst settings to enable
982 * RX and/or TX threshold.
983 */
984 if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
985 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
986 u8 rx_maxburst = dwc->rx_max_burst_prd;
987 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
988 u8 tx_maxburst = dwc->tx_max_burst_prd;
989
990 if (rx_thr_num && rx_maxburst) {
991 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
992 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
993
994 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
995 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
996
997 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
998 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
999
1000 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1001 }
1002
1003 if (tx_thr_num && tx_maxburst) {
1004 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1005 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1006
1007 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1008 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1009
1010 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1011 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1012
1013 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1014 }
1015 }
1016
72246da4
FB		 1017 return 0;
1018
c499ff71 1019err4:
9b9d7cdd 1020 phy_power_off(dwc->usb3_generic_phy);
c499ff71
FB		 1021
1022err3:
9b9d7cdd 1023 phy_power_off(dwc->usb2_generic_phy);
c499ff71 1024
0ffcaf37 1025err2:
c499ff71
FB		 1026 usb_phy_set_suspend(dwc->usb2_phy, 1);
1027 usb_phy_set_suspend(dwc->usb3_phy, 1);
0ffcaf37
FB		 1028
1029err1:
1030 usb_phy_shutdown(dwc->usb2_phy);
1031 usb_phy_shutdown(dwc->usb3_phy);
57303488
KVA		 1032 phy_exit(dwc->usb2_generic_phy);
1033 phy_exit(dwc->usb3_generic_phy);
0ffcaf37 1034
98112041
RQ		 1035err0a:
1036 dwc3_ulpi_exit(dwc);
1037
72246da4
FB		 1038err0:
1039 return ret;
1040}
1041
3c9f94ac 1042static int dwc3_core_get_phy(struct dwc3 *dwc)
72246da4 1043{
3c9f94ac 1044 struct device *dev = dwc->dev;
941ea361 1045 struct device_node *node = dev->of_node;
3c9f94ac 1046 int ret;
72246da4 1047
5088b6f5
KVA		 1048 if (node) {
1049 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1050 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
bb674907
FB		 1051 } else {
1052 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1053 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
5088b6f5
KVA		 1054 }
1055
d105e7f8
FB		 1056 if (IS_ERR(dwc->usb2_phy)) {
1057 ret = PTR_ERR(dwc->usb2_phy);
122f06e6
KVA		 1058 if (ret == -ENXIO || ret == -ENODEV) {
1059 dwc->usb2_phy = NULL;
1060 } else if (ret == -EPROBE_DEFER) {
d105e7f8 1061 return ret;
122f06e6
KVA		 1062 } else {
1063 dev_err(dev, "no usb2 phy configured\n");
1064 return ret;
1065 }
51e1e7bc
FB		 1066 }
1067
d105e7f8 1068 if (IS_ERR(dwc->usb3_phy)) {
315955d7 1069 ret = PTR_ERR(dwc->usb3_phy);
122f06e6
KVA		 1070 if (ret == -ENXIO || ret == -ENODEV) {
1071 dwc->usb3_phy = NULL;
1072 } else if (ret == -EPROBE_DEFER) {
d105e7f8 1073 return ret;
122f06e6
KVA		 1074 } else {
1075 dev_err(dev, "no usb3 phy configured\n");
1076 return ret;
1077 }
51e1e7bc
FB		 1078 }
1079
57303488
KVA		 1080 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1081 if (IS_ERR(dwc->usb2_generic_phy)) {
1082 ret = PTR_ERR(dwc->usb2_generic_phy);
1083 if (ret == -ENOSYS || ret == -ENODEV) {
1084 dwc->usb2_generic_phy = NULL;
1085 } else if (ret == -EPROBE_DEFER) {
1086 return ret;
1087 } else {
1088 dev_err(dev, "no usb2 phy configured\n");
1089 return ret;
1090 }
1091 }
1092
1093 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1094 if (IS_ERR(dwc->usb3_generic_phy)) {
1095 ret = PTR_ERR(dwc->usb3_generic_phy);
1096 if (ret == -ENOSYS || ret == -ENODEV) {
1097 dwc->usb3_generic_phy = NULL;
1098 } else if (ret == -EPROBE_DEFER) {
1099 return ret;
1100 } else {
1101 dev_err(dev, "no usb3 phy configured\n");
1102 return ret;
1103 }
1104 }
1105
3c9f94ac
FB		 1106 return 0;
1107}
1108
5f94adfe
FB		 1109static int dwc3_core_init_mode(struct dwc3 *dwc)
1110{
1111 struct device *dev = dwc->dev;
1112 int ret;
1113
1114 switch (dwc->dr_mode) {
1115 case USB_DR_MODE_PERIPHERAL:
41ce1456 1116 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
958d1a4c
FB		 1117
1118 if (dwc->usb2_phy)
1119 otg_set_vbus(dwc->usb2_phy->otg, false);
644cbbc3
MG		 1120 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1121 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
958d1a4c 1122
5f94adfe
FB		 1123 ret = dwc3_gadget_init(dwc);
1124 if (ret) {
9522def4
RQ		 1125 if (ret != -EPROBE_DEFER)
1126 dev_err(dev, "failed to initialize gadget\n");
5f94adfe
FB		 1127 return ret;
1128 }
1129 break;
1130 case USB_DR_MODE_HOST:
41ce1456 1131 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
958d1a4c
FB		 1132
1133 if (dwc->usb2_phy)
1134 otg_set_vbus(dwc->usb2_phy->otg, true);
644cbbc3
MG		 1135 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1136 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
958d1a4c 1137
5f94adfe
FB		 1138 ret = dwc3_host_init(dwc);
1139 if (ret) {
9522def4
RQ		 1140 if (ret != -EPROBE_DEFER)
1141 dev_err(dev, "failed to initialize host\n");
5f94adfe
FB		 1142 return ret;
1143 }
d8c80bb3 1144 phy_calibrate(dwc->usb2_generic_phy);
5f94adfe
FB		 1145 break;
1146 case USB_DR_MODE_OTG:
41ce1456 1147 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
9840354f
RQ		 1148 ret = dwc3_drd_init(dwc);
1149 if (ret) {
1150 if (ret != -EPROBE_DEFER)
1151 dev_err(dev, "failed to initialize dual-role\n");
1152 return ret;
1153 }
5f94adfe
FB		 1154 break;
1155 default:
1156 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1157 return -EINVAL;
1158 }
1159
1160 return 0;
1161}
1162
1163static void dwc3_core_exit_mode(struct dwc3 *dwc)
1164{
1165 switch (dwc->dr_mode) {
1166 case USB_DR_MODE_PERIPHERAL:
1167 dwc3_gadget_exit(dwc);
1168 break;
1169 case USB_DR_MODE_HOST:
1170 dwc3_host_exit(dwc);
1171 break;
1172 case USB_DR_MODE_OTG:
9840354f 1173 dwc3_drd_exit(dwc);
5f94adfe
FB		 1174 break;
1175 default:
1176 /* do nothing */
1177 break;
1178 }
1179}
1180
c5ac6116 1181static void dwc3_get_properties(struct dwc3 *dwc)
3c9f94ac 1182{
c5ac6116 1183 struct device *dev = dwc->dev;
80caf7d2 1184 u8 lpm_nyet_threshold;
6b6a0c9a 1185 u8 tx_de_emphasis;
460d098c 1186 u8 hird_threshold;
938a5ad1
TN		 1187 u8 rx_thr_num_pkt_prd;
1188 u8 rx_max_burst_prd;
1189 u8 tx_thr_num_pkt_prd;
1190 u8 tx_max_burst_prd;
3c9f94ac 1191
80caf7d2
HR		 1192 /* default to highest possible threshold */
1193 lpm_nyet_threshold = 0xff;
1194
6b6a0c9a
HR		 1195 /* default to -3.5dB de-emphasis */
1196 tx_de_emphasis = 1;
1197
460d098c
HR		 1198 /*
1199 * default to assert utmi_sleep_n and use maximum allowed HIRD
1200 * threshold value of 0b1100
1201 */
1202 hird_threshold = 12;
1203
63863b98 1204 dwc->maximum_speed = usb_get_maximum_speed(dev);
06e7114f 1205 dwc->dr_mode = usb_get_dr_mode(dev);
32f2ed86 1206 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
63863b98 1207
d64ff406
AB		 1208 dwc->sysdev_is_parent = device_property_read_bool(dev,
1209 "linux,sysdev_is_parent");
1210 if (dwc->sysdev_is_parent)
1211 dwc->sysdev = dwc->dev->parent;
1212 else
1213 dwc->sysdev = dwc->dev;
1214
3d128919 1215 dwc->has_lpm_erratum = device_property_read_bool(dev,
80caf7d2 1216 "snps,has-lpm-erratum");
3d128919 1217 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
80caf7d2 1218 &lpm_nyet_threshold);
3d128919 1219 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
460d098c 1220 "snps,is-utmi-l1-suspend");
3d128919 1221 device_property_read_u8(dev, "snps,hird-threshold",
460d098c 1222 &hird_threshold);
3d128919 1223 dwc->usb3_lpm_capable = device_property_read_bool(dev,
eac68e8f 1224 "snps,usb3_lpm_capable");
938a5ad1
TN		 1225 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1226 &rx_thr_num_pkt_prd);
1227 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1228 &rx_max_burst_prd);
1229 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1230 &tx_thr_num_pkt_prd);
1231 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1232 &tx_max_burst_prd);
3c9f94ac 1233
3d128919 1234 dwc->disable_scramble_quirk = device_property_read_bool(dev,
3b81221a 1235 "snps,disable_scramble_quirk");
3d128919 1236 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
9a5b2f31 1237 "snps,u2exit_lfps_quirk");
3d128919 1238 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
b5a65c40 1239 "snps,u2ss_inp3_quirk");
3d128919 1240 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
df31f5b3 1241 "snps,req_p1p2p3_quirk");
3d128919 1242 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
a2a1d0f5 1243 "snps,del_p1p2p3_quirk");
3d128919 1244 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
41c06ffd 1245 "snps,del_phy_power_chg_quirk");
3d128919 1246 dwc->lfps_filter_quirk = device_property_read_bool(dev,
fb67afca 1247 "snps,lfps_filter_quirk");
3d128919 1248 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
14f4ac53 1249 "snps,rx_detect_poll_quirk");
3d128919 1250 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
59acfa20 1251 "snps,dis_u3_susphy_quirk");
3d128919 1252 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
0effe0a3 1253 "snps,dis_u2_susphy_quirk");
ec791d14
JY		 1254 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1255 "snps,dis_enblslpm_quirk");
e58dd357
RB		 1256 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1257 "snps,dis_rxdet_inp3_quirk");
16199f33
WW		 1258 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1259 "snps,dis-u2-freeclk-exists-quirk");
00fe081d
WW		 1260 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1261 "snps,dis-del-phy-power-chg-quirk");
65db7a0c
WW		 1262 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1263 "snps,dis-tx-ipgap-linecheck-quirk");
6b6a0c9a 1264
3d128919 1265 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
6b6a0c9a 1266 "snps,tx_de_emphasis_quirk");
3d128919 1267 device_property_read_u8(dev, "snps,tx_de_emphasis",
6b6a0c9a 1268 &tx_de_emphasis);
3d128919
HK		 1269 device_property_read_string(dev, "snps,hsphy_interface",
1270 &dwc->hsphy_interface);
1271 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
bcdb3272 1272 &dwc->fladj);
3d128919 1273
42bf02ec
RQ		 1274 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1275 "snps,dis_metastability_quirk");
1276
80caf7d2 1277 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
6b6a0c9a 1278 dwc->tx_de_emphasis = tx_de_emphasis;
80caf7d2 1279
460d098c
HR		 1280 dwc->hird_threshold = hird_threshold
1281 | (dwc->is_utmi_l1_suspend << 4);
1282
938a5ad1
TN		 1283 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1284 dwc->rx_max_burst_prd = rx_max_burst_prd;
1285
1286 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1287 dwc->tx_max_burst_prd = tx_max_burst_prd;
1288
cf40b86b
JY		 1289 dwc->imod_interval = 0;
1290}
1291
1292/* check whether the core supports IMOD */
1293bool dwc3_has_imod(struct dwc3 *dwc)
1294{
1295 return ((dwc3_is_usb3(dwc) &&
1296 dwc->revision >= DWC3_REVISION_300A) ||
1297 (dwc3_is_usb31(dwc) &&
1298 dwc->revision >= DWC3_USB31_REVISION_120A));
c5ac6116
FB		 1299}
1300
7ac51a12
JY		 1301static void dwc3_check_params(struct dwc3 *dwc)
1302{
1303 struct device *dev = dwc->dev;
1304
cf40b86b
JY		 1305 /* Check for proper value of imod_interval */
1306 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1307 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1308 dwc->imod_interval = 0;
1309 }
1310
28632b44
JY		 1311 /*
1312 * Workaround for STAR 9000961433 which affects only version
1313 * 3.00a of the DWC_usb3 core. This prevents the controller
1314 * interrupt from being masked while handling events. IMOD
1315 * allows us to work around this issue. Enable it for the
1316 * affected version.
1317 */
1318 if (!dwc->imod_interval &&
1319 (dwc->revision == DWC3_REVISION_300A))
1320 dwc->imod_interval = 1;
1321
7ac51a12
JY		 1322 /* Check the maximum_speed parameter */
1323 switch (dwc->maximum_speed) {
1324 case USB_SPEED_LOW:
1325 case USB_SPEED_FULL:
1326 case USB_SPEED_HIGH:
1327 case USB_SPEED_SUPER:
1328 case USB_SPEED_SUPER_PLUS:
1329 break;
1330 default:
1331 dev_err(dev, "invalid maximum_speed parameter %d\n",
1332 dwc->maximum_speed);
1333 /* fall through */
1334 case USB_SPEED_UNKNOWN:
1335 /* default to superspeed */
1336 dwc->maximum_speed = USB_SPEED_SUPER;
1337
1338 /*
1339 * default to superspeed plus if we are capable.
1340 */
1341 if (dwc3_is_usb31(dwc) &&
1342 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1343 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1344 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1345
1346 break;
1347 }
1348}
1349
c5ac6116
FB		 1350static int dwc3_probe(struct platform_device *pdev)
1351{
1352 struct device *dev = &pdev->dev;
44feb8e6 1353 struct resource *res, dwc_res;
c5ac6116
FB		 1354 struct dwc3 *dwc;
1355
1356 int ret;
1357
1358 void __iomem *regs;
1359
1360 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1361 if (!dwc)
1362 return -ENOMEM;
1363
fe8abf33
MY		 1364 dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks),
1365 GFP_KERNEL);
1366 if (!dwc->clks)
1367 return -ENOMEM;
1368
c5ac6116
FB		 1369 dwc->dev = dev;
1370
1371 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1372 if (!res) {
1373 dev_err(dev, "missing memory resource\n");
1374 return -ENODEV;
1375 }
1376
1377 dwc->xhci_resources[0].start = res->start;
1378 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1379 DWC3_XHCI_REGS_END;
1380 dwc->xhci_resources[0].flags = res->flags;
1381 dwc->xhci_resources[0].name = res->name;
1382
c5ac6116
FB		 1383 /*
1384 * Request memory region but exclude xHCI regs,
1385 * since it will be requested by the xhci-plat driver.
1386 */
44feb8e6
MY		 1387 dwc_res = *res;
1388 dwc_res.start += DWC3_GLOBALS_REGS_START;
1389
1390 regs = devm_ioremap_resource(dev, &dwc_res);
1391 if (IS_ERR(regs))
1392 return PTR_ERR(regs);
c5ac6116
FB		 1393
1394 dwc->regs = regs;
44feb8e6 1395 dwc->regs_size = resource_size(&dwc_res);
c5ac6116
FB		 1396
1397 dwc3_get_properties(dwc);
1398
fe8abf33
MY		 1399 dwc->reset = devm_reset_control_get_optional_shared(dev, NULL);
1400 if (IS_ERR(dwc->reset))
1401 return PTR_ERR(dwc->reset);
1402
61527777
HG		 1403 if (dev->of_node) {
1404 dwc->num_clks = ARRAY_SIZE(dwc3_core_clks);
1405
1406 ret = clk_bulk_get(dev, dwc->num_clks, dwc->clks);
1407 if (ret == -EPROBE_DEFER)
1408 return ret;
1409 /*
1410 * Clocks are optional, but new DT platforms should support all
1411 * clocks as required by the DT-binding.
1412 */
1413 if (ret)
1414 dwc->num_clks = 0;
1415 }
fe8abf33
MY		 1416
1417 ret = reset_control_deassert(dwc->reset);
1418 if (ret)
1419 goto put_clks;
1420
1421 ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
1422 if (ret)
1423 goto assert_reset;
1424
1425 ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1426 if (ret)
1427 goto unprepare_clks;
1428
6c89cce0 1429 platform_set_drvdata(pdev, dwc);
2917e718 1430 dwc3_cache_hwparams(dwc);
6c89cce0 1431
72246da4 1432 spin_lock_init(&dwc->lock);
72246da4 1433
fc8bb91b
FB		 1434 pm_runtime_set_active(dev);
1435 pm_runtime_use_autosuspend(dev);
1436 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
802ca850 1437 pm_runtime_enable(dev);
32808237
RQ		 1438 ret = pm_runtime_get_sync(dev);
1439 if (ret < 0)
1440 goto err1;
1441
802ca850 1442 pm_runtime_forbid(dev);
72246da4 1443
3921426b
FB		 1444 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1445 if (ret) {
1446 dev_err(dwc->dev, "failed to allocate event buffers\n");
1447 ret = -ENOMEM;
32808237 1448 goto err2;
3921426b
FB		 1449 }
1450
9d6173e1
TN		 1451 ret = dwc3_get_dr_mode(dwc);
1452 if (ret)
1453 goto err3;
32a4a135 1454
c499ff71
FB		 1455 ret = dwc3_alloc_scratch_buffers(dwc);
1456 if (ret)
32808237 1457 goto err3;
c499ff71 1458
72246da4
FB		 1459 ret = dwc3_core_init(dwc);
1460 if (ret) {
802ca850 1461 dev_err(dev, "failed to initialize core\n");
32808237 1462 goto err4;
72246da4
FB		 1463 }
1464
7ac51a12 1465 dwc3_check_params(dwc);
2c7f1bd9 1466
5f94adfe
FB		 1467 ret = dwc3_core_init_mode(dwc);
1468 if (ret)
32808237 1469 goto err5;
72246da4 1470
4e9f3118 1471 dwc3_debugfs_init(dwc);
fc8bb91b 1472 pm_runtime_put(dev);
72246da4
FB		 1473
1474 return 0;
1475
32808237 1476err5:
c499ff71 1477 dwc3_event_buffers_cleanup(dwc);
57303488 1478
32808237 1479err4:
c499ff71 1480 dwc3_free_scratch_buffers(dwc);
72246da4 1481
32808237 1482err3:
3921426b
FB		 1483 dwc3_free_event_buffers(dwc);
1484
32808237
RQ		 1485err2:
1486 pm_runtime_allow(&pdev->dev);
1487
1488err1:
1489 pm_runtime_put_sync(&pdev->dev);
1490 pm_runtime_disable(&pdev->dev);
1491
fe8abf33
MY		 1492 clk_bulk_disable(dwc->num_clks, dwc->clks);
1493unprepare_clks:
1494 clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1495assert_reset:
1496 reset_control_assert(dwc->reset);
1497put_clks:
1498 clk_bulk_put(dwc->num_clks, dwc->clks);
1499
72246da4
FB		 1500 return ret;
1501}
1502
fb4e98ab 1503static int dwc3_remove(struct platform_device *pdev)
72246da4 1504{
72246da4 1505 struct dwc3 *dwc = platform_get_drvdata(pdev);
3da1f6ee 1506
fc8bb91b 1507 pm_runtime_get_sync(&pdev->dev);
72246da4 1508
dc99f16f
FB		 1509 dwc3_debugfs_exit(dwc);
1510 dwc3_core_exit_mode(dwc);
8ba007a9 1511
72246da4 1512 dwc3_core_exit(dwc);
88bc9d19 1513 dwc3_ulpi_exit(dwc);
72246da4 1514
16b972a5 1515 pm_runtime_put_sync(&pdev->dev);
fc8bb91b 1516 pm_runtime_allow(&pdev->dev);
72246da4
FB		 1517 pm_runtime_disable(&pdev->dev);
1518
fc8bb91b
FB		 1519 dwc3_free_event_buffers(dwc);
1520 dwc3_free_scratch_buffers(dwc);
fe8abf33 1521 clk_bulk_put(dwc->num_clks, dwc->clks);
fc8bb91b 1522
72246da4
FB		 1523 return 0;
1524}
1525
fc8bb91b 1526#ifdef CONFIG_PM
fe8abf33
MY		 1527static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1528{
1529 int ret;
1530
1531 ret = reset_control_deassert(dwc->reset);
1532 if (ret)
1533 return ret;
1534
1535 ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
1536 if (ret)
1537 goto assert_reset;
1538
1539 ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1540 if (ret)
1541 goto unprepare_clks;
1542
1543 ret = dwc3_core_init(dwc);
1544 if (ret)
1545 goto disable_clks;
1546
1547 return 0;
1548
1549disable_clks:
1550 clk_bulk_disable(dwc->num_clks, dwc->clks);
1551unprepare_clks:
1552 clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1553assert_reset:
1554 reset_control_assert(dwc->reset);
1555
1556 return ret;
1557}
1558
c4a5153e 1559static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
7415f17c 1560{
fc8bb91b 1561 unsigned long flags;
bcb12877 1562 u32 reg;
7415f17c 1563
689bf72c
MG		 1564 switch (dwc->current_dr_role) {
1565 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b 1566 spin_lock_irqsave(&dwc->lock, flags);
7415f17c 1567 dwc3_gadget_suspend(dwc);
fc8bb91b 1568 spin_unlock_irqrestore(&dwc->lock, flags);
689bf72c 1569 dwc3_core_exit(dwc);
51f5d49a 1570 break;
689bf72c 1571 case DWC3_GCTL_PRTCAP_HOST:
bcb12877 1572 if (!PMSG_IS_AUTO(msg)) {
c4a5153e 1573 dwc3_core_exit(dwc);
bcb12877
MG		 1574 break;
1575 }
1576
1577 /* Let controller to suspend HSPHY before PHY driver suspends */
1578 if (dwc->dis_u2_susphy_quirk ||
1579 dwc->dis_enblslpm_quirk) {
1580 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1581 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1582 DWC3_GUSB2PHYCFG_SUSPHY;
1583 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1584
1585 /* Give some time for USB2 PHY to suspend */
1586 usleep_range(5000, 6000);
1587 }
1588
1589 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1590 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
c4a5153e 1591 break;
f09cc79b
RQ		 1592 case DWC3_GCTL_PRTCAP_OTG:
1593 /* do nothing during runtime_suspend */
1594 if (PMSG_IS_AUTO(msg))
1595 break;
1596
1597 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1598 spin_lock_irqsave(&dwc->lock, flags);
1599 dwc3_gadget_suspend(dwc);
1600 spin_unlock_irqrestore(&dwc->lock, flags);
1601 }
1602
1603 dwc3_otg_exit(dwc);
1604 dwc3_core_exit(dwc);
1605 break;
7415f17c 1606 default:
51f5d49a 1607 /* do nothing */
7415f17c
FB		 1608 break;
1609 }
1610
7415f17c
FB		 1611 return 0;
1612}
1613
c4a5153e 1614static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
7415f17c 1615{
fc8bb91b 1616 unsigned long flags;
57303488 1617 int ret;
bcb12877 1618 u32 reg;
7415f17c 1619
689bf72c
MG		 1620 switch (dwc->current_dr_role) {
1621 case DWC3_GCTL_PRTCAP_DEVICE:
fe8abf33 1622 ret = dwc3_core_init_for_resume(dwc);
689bf72c
MG		 1623 if (ret)
1624 return ret;
5c4ad318 1625
7d11c3ac 1626 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
fc8bb91b 1627 spin_lock_irqsave(&dwc->lock, flags);
7415f17c 1628 dwc3_gadget_resume(dwc);
fc8bb91b 1629 spin_unlock_irqrestore(&dwc->lock, flags);
689bf72c
MG		 1630 break;
1631 case DWC3_GCTL_PRTCAP_HOST:
c4a5153e 1632 if (!PMSG_IS_AUTO(msg)) {
fe8abf33 1633 ret = dwc3_core_init_for_resume(dwc);
c4a5153e
MG		 1634 if (ret)
1635 return ret;
7d11c3ac 1636 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
bcb12877 1637 break;
c4a5153e 1638 }
bcb12877
MG		 1639 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1640 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1641 if (dwc->dis_u2_susphy_quirk)
1642 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1643
1644 if (dwc->dis_enblslpm_quirk)
1645 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1646
1647 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1648
1649 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1650 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
f09cc79b
RQ		 1651 break;
1652 case DWC3_GCTL_PRTCAP_OTG:
1653 /* nothing to do on runtime_resume */
1654 if (PMSG_IS_AUTO(msg))
1655 break;
1656
1657 ret = dwc3_core_init(dwc);
1658 if (ret)
1659 return ret;
1660
1661 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1662
1663 dwc3_otg_init(dwc);
1664 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1665 dwc3_otg_host_init(dwc);
1666 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1667 spin_lock_irqsave(&dwc->lock, flags);
1668 dwc3_gadget_resume(dwc);
1669 spin_unlock_irqrestore(&dwc->lock, flags);
c4a5153e 1670 }
f09cc79b 1671
c4a5153e 1672 break;
7415f17c
FB		 1673 default:
1674 /* do nothing */
1675 break;
1676 }
1677
fc8bb91b
FB		 1678 return 0;
1679}
1680
1681static int dwc3_runtime_checks(struct dwc3 *dwc)
1682{
689bf72c 1683 switch (dwc->current_dr_role) {
c4a5153e 1684 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 1685 if (dwc->connected)
1686 return -EBUSY;
1687 break;
c4a5153e 1688 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 1689 default:
1690 /* do nothing */
1691 break;
1692 }
1693
1694 return 0;
1695}
1696
1697static int dwc3_runtime_suspend(struct device *dev)
1698{
1699 struct dwc3 *dwc = dev_get_drvdata(dev);
1700 int ret;
1701
1702 if (dwc3_runtime_checks(dwc))
1703 return -EBUSY;
1704
c4a5153e 1705 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
fc8bb91b
FB		 1706 if (ret)
1707 return ret;
1708
1709 device_init_wakeup(dev, true);
1710
1711 return 0;
1712}
1713
1714static int dwc3_runtime_resume(struct device *dev)
1715{
1716 struct dwc3 *dwc = dev_get_drvdata(dev);
1717 int ret;
1718
1719 device_init_wakeup(dev, false);
1720
c4a5153e 1721 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
fc8bb91b
FB		 1722 if (ret)
1723 return ret;
1724
689bf72c
MG		 1725 switch (dwc->current_dr_role) {
1726 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 1727 dwc3_gadget_process_pending_events(dwc);
1728 break;
689bf72c 1729 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 1730 default:
1731 /* do nothing */
1732 break;
1733 }
1734
1735 pm_runtime_mark_last_busy(dev);
1736
1737 return 0;
1738}
1739
1740static int dwc3_runtime_idle(struct device *dev)
1741{
1742 struct dwc3 *dwc = dev_get_drvdata(dev);
1743
689bf72c
MG		 1744 switch (dwc->current_dr_role) {
1745 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 1746 if (dwc3_runtime_checks(dwc))
1747 return -EBUSY;
1748 break;
689bf72c 1749 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 1750 default:
1751 /* do nothing */
1752 break;
1753 }
1754
1755 pm_runtime_mark_last_busy(dev);
1756 pm_runtime_autosuspend(dev);
1757
1758 return 0;
1759}
1760#endif /* CONFIG_PM */
1761
1762#ifdef CONFIG_PM_SLEEP
1763static int dwc3_suspend(struct device *dev)
1764{
1765 struct dwc3 *dwc = dev_get_drvdata(dev);
1766 int ret;
1767
c4a5153e 1768 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
fc8bb91b
FB		 1769 if (ret)
1770 return ret;
1771
1772 pinctrl_pm_select_sleep_state(dev);
1773
1774 return 0;
1775}
1776
1777static int dwc3_resume(struct device *dev)
1778{
1779 struct dwc3 *dwc = dev_get_drvdata(dev);
1780 int ret;
1781
1782 pinctrl_pm_select_default_state(dev);
1783
c4a5153e 1784 ret = dwc3_resume_common(dwc, PMSG_RESUME);
fc8bb91b
FB		 1785 if (ret)
1786 return ret;
1787
7415f17c
FB		 1788 pm_runtime_disable(dev);
1789 pm_runtime_set_active(dev);
1790 pm_runtime_enable(dev);
1791
1792 return 0;
1793}
7f370ed0 1794#endif /* CONFIG_PM_SLEEP */
7415f17c
FB		 1795
1796static const struct dev_pm_ops dwc3_dev_pm_ops = {
7415f17c 1797 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
fc8bb91b
FB		 1798 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1799 dwc3_runtime_idle)
7415f17c
FB		 1800};
1801
5088b6f5
KVA		 1802#ifdef CONFIG_OF
1803static const struct of_device_id of_dwc3_match[] = {
22a5aa17
FB		 1804 {
1805 .compatible = "snps,dwc3"
1806 },
5088b6f5
KVA		 1807 {
1808 .compatible = "synopsys,dwc3"
1809 },
1810 { },
1811};
1812MODULE_DEVICE_TABLE(of, of_dwc3_match);
1813#endif
1814
404905a6
HK		 1815#ifdef CONFIG_ACPI
1816
1817#define ACPI_ID_INTEL_BSW "808622B7"
1818
1819static const struct acpi_device_id dwc3_acpi_match[] = {
1820 { ACPI_ID_INTEL_BSW, 0 },
1821 { },
1822};
1823MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1824#endif
1825
72246da4
FB		 1826static struct platform_driver dwc3_driver = {
1827 .probe = dwc3_probe,
7690417d 1828 .remove = dwc3_remove,
72246da4
FB		 1829 .driver = {
1830 .name = "dwc3",
5088b6f5 1831 .of_match_table = of_match_ptr(of_dwc3_match),
404905a6 1832 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
7f370ed0 1833 .pm = &dwc3_dev_pm_ops,
72246da4 1834 },
72246da4
FB		 1835};
1836
b1116dcc
TK		 1837module_platform_driver(dwc3_driver);
1838
7ae4fc4d 1839MODULE_ALIAS("platform:dwc3");
72246da4 1840MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
5945f789 1841MODULE_LICENSE("GPL v2");
72246da4 1842MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux 6.x block layer and io_uring tree(s)