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72246da4 FB |
1 | /** |
2 | * core.c - DesignWare USB3 DRD Controller Core file | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 | 17 | * |
5945f789 FB |
18 | * You should have received a copy of the GNU General Public License |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
72246da4 FB |
20 | */ |
21 | ||
fa0ea13e | 22 | #include <linux/version.h> |
a72e658b | 23 | #include <linux/module.h> |
72246da4 FB |
24 | #include <linux/kernel.h> |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/pm_runtime.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/list.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
457e84b6 | 35 | #include <linux/of.h> |
404905a6 | 36 | #include <linux/acpi.h> |
6344475f | 37 | #include <linux/pinctrl/consumer.h> |
72246da4 FB |
38 | |
39 | #include <linux/usb/ch9.h> | |
40 | #include <linux/usb/gadget.h> | |
f7e846f0 | 41 | #include <linux/usb/of.h> |
a45c82b8 | 42 | #include <linux/usb/otg.h> |
72246da4 FB |
43 | |
44 | #include "core.h" | |
45 | #include "gadget.h" | |
46 | #include "io.h" | |
47 | ||
48 | #include "debug.h" | |
49 | ||
fc8bb91b | 50 | #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ |
8300dd23 | 51 | |
9d6173e1 TN |
52 | /** |
53 | * dwc3_get_dr_mode - Validates and sets dr_mode | |
54 | * @dwc: pointer to our context structure | |
55 | */ | |
56 | static int dwc3_get_dr_mode(struct dwc3 *dwc) | |
57 | { | |
58 | enum usb_dr_mode mode; | |
59 | struct device *dev = dwc->dev; | |
60 | unsigned int hw_mode; | |
61 | ||
62 | if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) | |
63 | dwc->dr_mode = USB_DR_MODE_OTG; | |
64 | ||
65 | mode = dwc->dr_mode; | |
66 | hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); | |
67 | ||
68 | switch (hw_mode) { | |
69 | case DWC3_GHWPARAMS0_MODE_GADGET: | |
70 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { | |
71 | dev_err(dev, | |
72 | "Controller does not support host mode.\n"); | |
73 | return -EINVAL; | |
74 | } | |
75 | mode = USB_DR_MODE_PERIPHERAL; | |
76 | break; | |
77 | case DWC3_GHWPARAMS0_MODE_HOST: | |
78 | if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { | |
79 | dev_err(dev, | |
80 | "Controller does not support device mode.\n"); | |
81 | return -EINVAL; | |
82 | } | |
83 | mode = USB_DR_MODE_HOST; | |
84 | break; | |
85 | default: | |
86 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) | |
87 | mode = USB_DR_MODE_HOST; | |
88 | else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) | |
89 | mode = USB_DR_MODE_PERIPHERAL; | |
90 | } | |
91 | ||
92 | if (mode != dwc->dr_mode) { | |
93 | dev_warn(dev, | |
94 | "Configuration mismatch. dr_mode forced to %s\n", | |
95 | mode == USB_DR_MODE_HOST ? "host" : "gadget"); | |
96 | ||
97 | dwc->dr_mode = mode; | |
98 | } | |
99 | ||
100 | return 0; | |
101 | } | |
102 | ||
3140e8cb SAS |
103 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode) |
104 | { | |
105 | u32 reg; | |
106 | ||
107 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
108 | reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); | |
109 | reg |= DWC3_GCTL_PRTCAPDIR(mode); | |
110 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
111 | } | |
8300dd23 | 112 | |
cf6d867d FB |
113 | u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) |
114 | { | |
115 | struct dwc3 *dwc = dep->dwc; | |
116 | u32 reg; | |
117 | ||
118 | dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, | |
119 | DWC3_GDBGFIFOSPACE_NUM(dep->number) | | |
120 | DWC3_GDBGFIFOSPACE_TYPE(type)); | |
121 | ||
122 | reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); | |
123 | ||
124 | return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); | |
125 | } | |
126 | ||
72246da4 FB |
127 | /** |
128 | * dwc3_core_soft_reset - Issues core soft reset and PHY reset | |
129 | * @dwc: pointer to our context structure | |
130 | */ | |
57303488 | 131 | static int dwc3_core_soft_reset(struct dwc3 *dwc) |
72246da4 FB |
132 | { |
133 | u32 reg; | |
f59dcab1 | 134 | int retries = 1000; |
57303488 | 135 | int ret; |
72246da4 | 136 | |
51e1e7bc FB |
137 | usb_phy_init(dwc->usb2_phy); |
138 | usb_phy_init(dwc->usb3_phy); | |
57303488 KVA |
139 | ret = phy_init(dwc->usb2_generic_phy); |
140 | if (ret < 0) | |
141 | return ret; | |
142 | ||
143 | ret = phy_init(dwc->usb3_generic_phy); | |
144 | if (ret < 0) { | |
145 | phy_exit(dwc->usb2_generic_phy); | |
146 | return ret; | |
147 | } | |
72246da4 | 148 | |
f59dcab1 FB |
149 | /* |
150 | * We're resetting only the device side because, if we're in host mode, | |
151 | * XHCI driver will reset the host block. If dwc3 was configured for | |
152 | * host-only mode, then we can return early. | |
153 | */ | |
154 | if (dwc->dr_mode == USB_DR_MODE_HOST) | |
155 | return 0; | |
72246da4 | 156 | |
f59dcab1 FB |
157 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
158 | reg |= DWC3_DCTL_CSFTRST; | |
159 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 160 | |
f59dcab1 FB |
161 | do { |
162 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
163 | if (!(reg & DWC3_DCTL_CSFTRST)) | |
164 | return 0; | |
45627ac6 | 165 | |
f59dcab1 FB |
166 | udelay(1); |
167 | } while (--retries); | |
57303488 | 168 | |
f59dcab1 | 169 | return -ETIMEDOUT; |
72246da4 FB |
170 | } |
171 | ||
c5cc74e8 HK |
172 | /** |
173 | * dwc3_soft_reset - Issue soft reset | |
174 | * @dwc: Pointer to our controller context structure | |
175 | */ | |
176 | static int dwc3_soft_reset(struct dwc3 *dwc) | |
177 | { | |
178 | unsigned long timeout; | |
179 | u32 reg; | |
180 | ||
181 | timeout = jiffies + msecs_to_jiffies(500); | |
182 | dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); | |
183 | do { | |
184 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
185 | if (!(reg & DWC3_DCTL_CSFTRST)) | |
186 | break; | |
187 | ||
188 | if (time_after(jiffies, timeout)) { | |
189 | dev_err(dwc->dev, "Reset Timed Out\n"); | |
190 | return -ETIMEDOUT; | |
191 | } | |
192 | ||
193 | cpu_relax(); | |
194 | } while (true); | |
195 | ||
196 | return 0; | |
197 | } | |
198 | ||
db2be4e9 NB |
199 | /* |
200 | * dwc3_frame_length_adjustment - Adjusts frame length if required | |
201 | * @dwc3: Pointer to our controller context structure | |
db2be4e9 | 202 | */ |
bcdb3272 | 203 | static void dwc3_frame_length_adjustment(struct dwc3 *dwc) |
db2be4e9 NB |
204 | { |
205 | u32 reg; | |
206 | u32 dft; | |
207 | ||
208 | if (dwc->revision < DWC3_REVISION_250A) | |
209 | return; | |
210 | ||
bcdb3272 | 211 | if (dwc->fladj == 0) |
db2be4e9 NB |
212 | return; |
213 | ||
214 | reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); | |
215 | dft = reg & DWC3_GFLADJ_30MHZ_MASK; | |
bcdb3272 | 216 | if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj, |
db2be4e9 NB |
217 | "request value same as default, ignoring\n")) { |
218 | reg &= ~DWC3_GFLADJ_30MHZ_MASK; | |
bcdb3272 | 219 | reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; |
db2be4e9 NB |
220 | dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); |
221 | } | |
222 | } | |
223 | ||
72246da4 FB |
224 | /** |
225 | * dwc3_free_one_event_buffer - Frees one event buffer | |
226 | * @dwc: Pointer to our controller context structure | |
227 | * @evt: Pointer to event buffer to be freed | |
228 | */ | |
229 | static void dwc3_free_one_event_buffer(struct dwc3 *dwc, | |
230 | struct dwc3_event_buffer *evt) | |
231 | { | |
232 | dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma); | |
72246da4 FB |
233 | } |
234 | ||
235 | /** | |
1d046793 | 236 | * dwc3_alloc_one_event_buffer - Allocates one event buffer structure |
72246da4 FB |
237 | * @dwc: Pointer to our controller context structure |
238 | * @length: size of the event buffer | |
239 | * | |
1d046793 | 240 | * Returns a pointer to the allocated event buffer structure on success |
72246da4 FB |
241 | * otherwise ERR_PTR(errno). |
242 | */ | |
67d0b500 FB |
243 | static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, |
244 | unsigned length) | |
72246da4 FB |
245 | { |
246 | struct dwc3_event_buffer *evt; | |
247 | ||
380f0d28 | 248 | evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); |
72246da4 FB |
249 | if (!evt) |
250 | return ERR_PTR(-ENOMEM); | |
251 | ||
252 | evt->dwc = dwc; | |
253 | evt->length = length; | |
254 | evt->buf = dma_alloc_coherent(dwc->dev, length, | |
255 | &evt->dma, GFP_KERNEL); | |
e32672f0 | 256 | if (!evt->buf) |
72246da4 | 257 | return ERR_PTR(-ENOMEM); |
72246da4 FB |
258 | |
259 | return evt; | |
260 | } | |
261 | ||
262 | /** | |
263 | * dwc3_free_event_buffers - frees all allocated event buffers | |
264 | * @dwc: Pointer to our controller context structure | |
265 | */ | |
266 | static void dwc3_free_event_buffers(struct dwc3 *dwc) | |
267 | { | |
268 | struct dwc3_event_buffer *evt; | |
72246da4 | 269 | |
696c8b12 | 270 | evt = dwc->ev_buf; |
660e9bde FB |
271 | if (evt) |
272 | dwc3_free_one_event_buffer(dwc, evt); | |
72246da4 FB |
273 | } |
274 | ||
275 | /** | |
276 | * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length | |
1d046793 | 277 | * @dwc: pointer to our controller context structure |
72246da4 FB |
278 | * @length: size of event buffer |
279 | * | |
1d046793 | 280 | * Returns 0 on success otherwise negative errno. In the error case, dwc |
72246da4 FB |
281 | * may contain some buffers allocated but not all which were requested. |
282 | */ | |
41ac7b3a | 283 | static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) |
72246da4 | 284 | { |
660e9bde | 285 | struct dwc3_event_buffer *evt; |
72246da4 | 286 | |
660e9bde FB |
287 | evt = dwc3_alloc_one_event_buffer(dwc, length); |
288 | if (IS_ERR(evt)) { | |
289 | dev_err(dwc->dev, "can't allocate event buffer\n"); | |
290 | return PTR_ERR(evt); | |
72246da4 | 291 | } |
696c8b12 | 292 | dwc->ev_buf = evt; |
72246da4 FB |
293 | |
294 | return 0; | |
295 | } | |
296 | ||
297 | /** | |
298 | * dwc3_event_buffers_setup - setup our allocated event buffers | |
1d046793 | 299 | * @dwc: pointer to our controller context structure |
72246da4 FB |
300 | * |
301 | * Returns 0 on success otherwise negative errno. | |
302 | */ | |
7acd85e0 | 303 | static int dwc3_event_buffers_setup(struct dwc3 *dwc) |
72246da4 FB |
304 | { |
305 | struct dwc3_event_buffer *evt; | |
72246da4 | 306 | |
696c8b12 | 307 | evt = dwc->ev_buf; |
660e9bde FB |
308 | dwc3_trace(trace_dwc3_core, |
309 | "Event buf %p dma %08llx length %d\n", | |
310 | evt->buf, (unsigned long long) evt->dma, | |
311 | evt->length); | |
312 | ||
313 | evt->lpos = 0; | |
314 | ||
315 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), | |
316 | lower_32_bits(evt->dma)); | |
317 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), | |
318 | upper_32_bits(evt->dma)); | |
319 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), | |
320 | DWC3_GEVNTSIZ_SIZE(evt->length)); | |
321 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); | |
72246da4 FB |
322 | |
323 | return 0; | |
324 | } | |
325 | ||
326 | static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) | |
327 | { | |
328 | struct dwc3_event_buffer *evt; | |
72246da4 | 329 | |
696c8b12 | 330 | evt = dwc->ev_buf; |
7acd85e0 | 331 | |
660e9bde | 332 | evt->lpos = 0; |
7acd85e0 | 333 | |
660e9bde FB |
334 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); |
335 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); | |
336 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK | |
337 | | DWC3_GEVNTSIZ_SIZE(0)); | |
338 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); | |
72246da4 FB |
339 | } |
340 | ||
0ffcaf37 FB |
341 | static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) |
342 | { | |
343 | if (!dwc->has_hibernation) | |
344 | return 0; | |
345 | ||
346 | if (!dwc->nr_scratch) | |
347 | return 0; | |
348 | ||
349 | dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, | |
350 | DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); | |
351 | if (!dwc->scratchbuf) | |
352 | return -ENOMEM; | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
357 | static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) | |
358 | { | |
359 | dma_addr_t scratch_addr; | |
360 | u32 param; | |
361 | int ret; | |
362 | ||
363 | if (!dwc->has_hibernation) | |
364 | return 0; | |
365 | ||
366 | if (!dwc->nr_scratch) | |
367 | return 0; | |
368 | ||
369 | /* should never fall here */ | |
370 | if (!WARN_ON(dwc->scratchbuf)) | |
371 | return 0; | |
372 | ||
373 | scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf, | |
374 | dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, | |
375 | DMA_BIDIRECTIONAL); | |
376 | if (dma_mapping_error(dwc->dev, scratch_addr)) { | |
377 | dev_err(dwc->dev, "failed to map scratch buffer\n"); | |
378 | ret = -EFAULT; | |
379 | goto err0; | |
380 | } | |
381 | ||
382 | dwc->scratch_addr = scratch_addr; | |
383 | ||
384 | param = lower_32_bits(scratch_addr); | |
385 | ||
386 | ret = dwc3_send_gadget_generic_command(dwc, | |
387 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); | |
388 | if (ret < 0) | |
389 | goto err1; | |
390 | ||
391 | param = upper_32_bits(scratch_addr); | |
392 | ||
393 | ret = dwc3_send_gadget_generic_command(dwc, | |
394 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); | |
395 | if (ret < 0) | |
396 | goto err1; | |
397 | ||
398 | return 0; | |
399 | ||
400 | err1: | |
401 | dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * | |
402 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); | |
403 | ||
404 | err0: | |
405 | return ret; | |
406 | } | |
407 | ||
408 | static void dwc3_free_scratch_buffers(struct dwc3 *dwc) | |
409 | { | |
410 | if (!dwc->has_hibernation) | |
411 | return; | |
412 | ||
413 | if (!dwc->nr_scratch) | |
414 | return; | |
415 | ||
416 | /* should never fall here */ | |
417 | if (!WARN_ON(dwc->scratchbuf)) | |
418 | return; | |
419 | ||
420 | dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * | |
421 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); | |
422 | kfree(dwc->scratchbuf); | |
423 | } | |
424 | ||
789451f6 FB |
425 | static void dwc3_core_num_eps(struct dwc3 *dwc) |
426 | { | |
427 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
428 | ||
429 | dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); | |
430 | dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; | |
431 | ||
73815280 | 432 | dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints", |
789451f6 FB |
433 | dwc->num_in_eps, dwc->num_out_eps); |
434 | } | |
435 | ||
41ac7b3a | 436 | static void dwc3_cache_hwparams(struct dwc3 *dwc) |
26ceca97 FB |
437 | { |
438 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
439 | ||
440 | parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); | |
441 | parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); | |
442 | parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); | |
443 | parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); | |
444 | parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); | |
445 | parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); | |
446 | parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); | |
447 | parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); | |
448 | parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); | |
449 | } | |
450 | ||
b5a65c40 HR |
451 | /** |
452 | * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core | |
453 | * @dwc: Pointer to our controller context structure | |
88bc9d19 HK |
454 | * |
455 | * Returns 0 on success. The USB PHY interfaces are configured but not | |
456 | * initialized. The PHY interfaces and the PHYs get initialized together with | |
457 | * the core in dwc3_core_init. | |
b5a65c40 | 458 | */ |
88bc9d19 | 459 | static int dwc3_phy_setup(struct dwc3 *dwc) |
b5a65c40 HR |
460 | { |
461 | u32 reg; | |
88bc9d19 | 462 | int ret; |
b5a65c40 HR |
463 | |
464 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
465 | ||
2164a476 HR |
466 | /* |
467 | * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY | |
468 | * to '0' during coreConsultant configuration. So default value | |
469 | * will be '0' when the core is reset. Application needs to set it | |
470 | * to '1' after the core initialization is completed. | |
471 | */ | |
472 | if (dwc->revision > DWC3_REVISION_194A) | |
473 | reg |= DWC3_GUSB3PIPECTL_SUSPHY; | |
474 | ||
b5a65c40 HR |
475 | if (dwc->u2ss_inp3_quirk) |
476 | reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; | |
477 | ||
e58dd357 RB |
478 | if (dwc->dis_rxdet_inp3_quirk) |
479 | reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; | |
480 | ||
df31f5b3 HR |
481 | if (dwc->req_p1p2p3_quirk) |
482 | reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; | |
483 | ||
a2a1d0f5 HR |
484 | if (dwc->del_p1p2p3_quirk) |
485 | reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; | |
486 | ||
41c06ffd HR |
487 | if (dwc->del_phy_power_chg_quirk) |
488 | reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; | |
489 | ||
fb67afca HR |
490 | if (dwc->lfps_filter_quirk) |
491 | reg |= DWC3_GUSB3PIPECTL_LFPSFILT; | |
492 | ||
14f4ac53 HR |
493 | if (dwc->rx_detect_poll_quirk) |
494 | reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; | |
495 | ||
6b6a0c9a HR |
496 | if (dwc->tx_de_emphasis_quirk) |
497 | reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); | |
498 | ||
cd72f890 | 499 | if (dwc->dis_u3_susphy_quirk) |
59acfa20 HR |
500 | reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; |
501 | ||
00fe081d WW |
502 | if (dwc->dis_del_phy_power_chg_quirk) |
503 | reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; | |
504 | ||
b5a65c40 HR |
505 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); |
506 | ||
2164a476 HR |
507 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
508 | ||
3e10a2ce HK |
509 | /* Select the HS PHY interface */ |
510 | switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { | |
511 | case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: | |
43cacb03 FB |
512 | if (dwc->hsphy_interface && |
513 | !strncmp(dwc->hsphy_interface, "utmi", 4)) { | |
3e10a2ce | 514 | reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; |
88bc9d19 | 515 | break; |
43cacb03 FB |
516 | } else if (dwc->hsphy_interface && |
517 | !strncmp(dwc->hsphy_interface, "ulpi", 4)) { | |
3e10a2ce | 518 | reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; |
88bc9d19 | 519 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
3e10a2ce | 520 | } else { |
88bc9d19 HK |
521 | /* Relying on default value. */ |
522 | if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) | |
523 | break; | |
3e10a2ce HK |
524 | } |
525 | /* FALLTHROUGH */ | |
88bc9d19 HK |
526 | case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: |
527 | /* Making sure the interface and PHY are operational */ | |
528 | ret = dwc3_soft_reset(dwc); | |
529 | if (ret) | |
530 | return ret; | |
531 | ||
532 | udelay(1); | |
533 | ||
534 | ret = dwc3_ulpi_init(dwc); | |
535 | if (ret) | |
536 | return ret; | |
537 | /* FALLTHROUGH */ | |
3e10a2ce HK |
538 | default: |
539 | break; | |
540 | } | |
541 | ||
32f2ed86 WW |
542 | switch (dwc->hsphy_mode) { |
543 | case USBPHY_INTERFACE_MODE_UTMI: | |
544 | reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | | |
545 | DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); | |
546 | reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | | |
547 | DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); | |
548 | break; | |
549 | case USBPHY_INTERFACE_MODE_UTMIW: | |
550 | reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | | |
551 | DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); | |
552 | reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | | |
553 | DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); | |
554 | break; | |
555 | default: | |
556 | break; | |
557 | } | |
558 | ||
2164a476 HR |
559 | /* |
560 | * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to | |
561 | * '0' during coreConsultant configuration. So default value will | |
562 | * be '0' when the core is reset. Application needs to set it to | |
563 | * '1' after the core initialization is completed. | |
564 | */ | |
565 | if (dwc->revision > DWC3_REVISION_194A) | |
566 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; | |
567 | ||
cd72f890 | 568 | if (dwc->dis_u2_susphy_quirk) |
0effe0a3 HR |
569 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; |
570 | ||
ec791d14 JY |
571 | if (dwc->dis_enblslpm_quirk) |
572 | reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; | |
573 | ||
16199f33 WW |
574 | if (dwc->dis_u2_freeclk_exists_quirk) |
575 | reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; | |
576 | ||
2164a476 | 577 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
88bc9d19 HK |
578 | |
579 | return 0; | |
b5a65c40 HR |
580 | } |
581 | ||
c499ff71 FB |
582 | static void dwc3_core_exit(struct dwc3 *dwc) |
583 | { | |
584 | dwc3_event_buffers_cleanup(dwc); | |
585 | ||
586 | usb_phy_shutdown(dwc->usb2_phy); | |
587 | usb_phy_shutdown(dwc->usb3_phy); | |
588 | phy_exit(dwc->usb2_generic_phy); | |
589 | phy_exit(dwc->usb3_generic_phy); | |
590 | ||
591 | usb_phy_set_suspend(dwc->usb2_phy, 1); | |
592 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
593 | phy_power_off(dwc->usb2_generic_phy); | |
594 | phy_power_off(dwc->usb3_generic_phy); | |
595 | } | |
596 | ||
0759956f | 597 | static bool dwc3_core_is_valid(struct dwc3 *dwc) |
72246da4 | 598 | { |
0759956f | 599 | u32 reg; |
72246da4 | 600 | |
7650bd74 | 601 | reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); |
0759956f | 602 | |
7650bd74 | 603 | /* This should read as U3 followed by revision number */ |
690fb371 JY |
604 | if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { |
605 | /* Detected DWC_usb3 IP */ | |
606 | dwc->revision = reg; | |
607 | } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { | |
608 | /* Detected DWC_usb31 IP */ | |
609 | dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); | |
610 | dwc->revision |= DWC3_REVISION_IS_DWC31; | |
611 | } else { | |
0759956f FB |
612 | return false; |
613 | } | |
614 | ||
615 | return true; | |
616 | } | |
617 | ||
618 | /** | |
619 | * dwc3_core_init - Low-level initialization of DWC3 Core | |
620 | * @dwc: Pointer to our controller context structure | |
621 | * | |
622 | * Returns 0 on success otherwise negative errno. | |
623 | */ | |
624 | static int dwc3_core_init(struct dwc3 *dwc) | |
625 | { | |
626 | u32 hwparams4 = dwc->hwparams.hwparams4; | |
627 | u32 reg; | |
628 | int ret; | |
629 | ||
630 | if (!dwc3_core_is_valid(dwc)) { | |
7650bd74 SAS |
631 | dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); |
632 | ret = -ENODEV; | |
633 | goto err0; | |
634 | } | |
7650bd74 | 635 | |
fa0ea13e FB |
636 | /* |
637 | * Write Linux Version Code to our GUID register so it's easy to figure | |
638 | * out which kernel version a bug was found. | |
639 | */ | |
640 | dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); | |
641 | ||
0e1e5c47 PZ |
642 | /* Handle USB2.0-only core configuration */ |
643 | if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == | |
644 | DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { | |
645 | if (dwc->maximum_speed == USB_SPEED_SUPER) | |
646 | dwc->maximum_speed = USB_SPEED_HIGH; | |
647 | } | |
648 | ||
72246da4 | 649 | /* issue device SoftReset too */ |
c5cc74e8 HK |
650 | ret = dwc3_soft_reset(dwc); |
651 | if (ret) | |
652 | goto err0; | |
72246da4 | 653 | |
57303488 KVA |
654 | ret = dwc3_core_soft_reset(dwc); |
655 | if (ret) | |
656 | goto err0; | |
58a0f23f | 657 | |
c499ff71 FB |
658 | ret = dwc3_phy_setup(dwc); |
659 | if (ret) | |
660 | goto err0; | |
661 | ||
4878a028 | 662 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); |
3e87c42a | 663 | reg &= ~DWC3_GCTL_SCALEDOWN_MASK; |
4878a028 | 664 | |
164d7731 | 665 | switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { |
4878a028 | 666 | case DWC3_GHWPARAMS1_EN_PWROPT_CLK: |
32a4a135 FB |
667 | /** |
668 | * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an | |
669 | * issue which would cause xHCI compliance tests to fail. | |
670 | * | |
671 | * Because of that we cannot enable clock gating on such | |
672 | * configurations. | |
673 | * | |
674 | * Refers to: | |
675 | * | |
676 | * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based | |
677 | * SOF/ITP Mode Used | |
678 | */ | |
679 | if ((dwc->dr_mode == USB_DR_MODE_HOST || | |
680 | dwc->dr_mode == USB_DR_MODE_OTG) && | |
681 | (dwc->revision >= DWC3_REVISION_210A && | |
682 | dwc->revision <= DWC3_REVISION_250A)) | |
683 | reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; | |
684 | else | |
685 | reg &= ~DWC3_GCTL_DSBLCLKGTNG; | |
4878a028 | 686 | break; |
0ffcaf37 FB |
687 | case DWC3_GHWPARAMS1_EN_PWROPT_HIB: |
688 | /* enable hibernation here */ | |
689 | dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); | |
2eac3992 HR |
690 | |
691 | /* | |
692 | * REVISIT Enabling this bit so that host-mode hibernation | |
693 | * will work. Device-mode hibernation is not yet implemented. | |
694 | */ | |
695 | reg |= DWC3_GCTL_GBLHIBERNATIONEN; | |
0ffcaf37 | 696 | break; |
4878a028 | 697 | default: |
1407bf13 | 698 | dwc3_trace(trace_dwc3_core, "No power optimization available\n"); |
4878a028 SAS |
699 | } |
700 | ||
946bd579 HR |
701 | /* check if current dwc3 is on simulation board */ |
702 | if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { | |
1407bf13 FB |
703 | dwc3_trace(trace_dwc3_core, |
704 | "running on FPGA platform\n"); | |
946bd579 HR |
705 | dwc->is_fpga = true; |
706 | } | |
707 | ||
3b81221a HR |
708 | WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, |
709 | "disable_scramble cannot be used on non-FPGA builds\n"); | |
710 | ||
711 | if (dwc->disable_scramble_quirk && dwc->is_fpga) | |
712 | reg |= DWC3_GCTL_DISSCRAMBLE; | |
713 | else | |
714 | reg &= ~DWC3_GCTL_DISSCRAMBLE; | |
715 | ||
9a5b2f31 HR |
716 | if (dwc->u2exit_lfps_quirk) |
717 | reg |= DWC3_GCTL_U2EXIT_LFPS; | |
718 | ||
4878a028 SAS |
719 | /* |
720 | * WORKAROUND: DWC3 revisions <1.90a have a bug | |
1d046793 | 721 | * where the device can fail to connect at SuperSpeed |
4878a028 | 722 | * and falls back to high-speed mode which causes |
1d046793 | 723 | * the device to enter a Connect/Disconnect loop |
4878a028 SAS |
724 | */ |
725 | if (dwc->revision < DWC3_REVISION_190A) | |
726 | reg |= DWC3_GCTL_U2RSTECN; | |
727 | ||
728 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
729 | ||
c499ff71 | 730 | dwc3_core_num_eps(dwc); |
0ffcaf37 FB |
731 | |
732 | ret = dwc3_setup_scratch_buffers(dwc); | |
733 | if (ret) | |
c499ff71 FB |
734 | goto err1; |
735 | ||
736 | /* Adjust Frame Length */ | |
737 | dwc3_frame_length_adjustment(dwc); | |
738 | ||
739 | usb_phy_set_suspend(dwc->usb2_phy, 0); | |
740 | usb_phy_set_suspend(dwc->usb3_phy, 0); | |
741 | ret = phy_power_on(dwc->usb2_generic_phy); | |
742 | if (ret < 0) | |
0ffcaf37 FB |
743 | goto err2; |
744 | ||
c499ff71 FB |
745 | ret = phy_power_on(dwc->usb3_generic_phy); |
746 | if (ret < 0) | |
747 | goto err3; | |
748 | ||
749 | ret = dwc3_event_buffers_setup(dwc); | |
750 | if (ret) { | |
751 | dev_err(dwc->dev, "failed to setup event buffers\n"); | |
752 | goto err4; | |
753 | } | |
754 | ||
00af6233 BW |
755 | switch (dwc->dr_mode) { |
756 | case USB_DR_MODE_PERIPHERAL: | |
757 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); | |
758 | break; | |
759 | case USB_DR_MODE_HOST: | |
760 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); | |
761 | break; | |
762 | case USB_DR_MODE_OTG: | |
763 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); | |
764 | break; | |
765 | default: | |
766 | dev_warn(dwc->dev, "Unsupported mode %d\n", dwc->dr_mode); | |
767 | break; | |
768 | } | |
769 | ||
06281d46 JY |
770 | /* |
771 | * ENDXFER polling is available on version 3.10a and later of | |
772 | * the DWC_usb3 controller. It is NOT available in the | |
773 | * DWC_usb31 controller. | |
774 | */ | |
775 | if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) { | |
776 | reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); | |
777 | reg |= DWC3_GUCTL2_RST_ACTBITLATER; | |
778 | dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); | |
779 | } | |
780 | ||
0bb39ca1 JY |
781 | /* |
782 | * Enable hardware control of sending remote wakeup in HS when | |
783 | * the device is in the L1 state. | |
784 | */ | |
785 | if (dwc->revision >= DWC3_REVISION_290A) { | |
786 | reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); | |
787 | reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; | |
788 | dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); | |
789 | } | |
790 | ||
72246da4 FB |
791 | return 0; |
792 | ||
c499ff71 FB |
793 | err4: |
794 | phy_power_off(dwc->usb2_generic_phy); | |
795 | ||
796 | err3: | |
797 | phy_power_off(dwc->usb3_generic_phy); | |
798 | ||
0ffcaf37 | 799 | err2: |
c499ff71 FB |
800 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
801 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
802 | dwc3_core_exit(dwc); | |
0ffcaf37 FB |
803 | |
804 | err1: | |
805 | usb_phy_shutdown(dwc->usb2_phy); | |
806 | usb_phy_shutdown(dwc->usb3_phy); | |
57303488 KVA |
807 | phy_exit(dwc->usb2_generic_phy); |
808 | phy_exit(dwc->usb3_generic_phy); | |
0ffcaf37 | 809 | |
72246da4 FB |
810 | err0: |
811 | return ret; | |
812 | } | |
813 | ||
3c9f94ac | 814 | static int dwc3_core_get_phy(struct dwc3 *dwc) |
72246da4 | 815 | { |
3c9f94ac | 816 | struct device *dev = dwc->dev; |
941ea361 | 817 | struct device_node *node = dev->of_node; |
3c9f94ac | 818 | int ret; |
72246da4 | 819 | |
5088b6f5 KVA |
820 | if (node) { |
821 | dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); | |
822 | dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); | |
bb674907 FB |
823 | } else { |
824 | dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); | |
825 | dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); | |
5088b6f5 KVA |
826 | } |
827 | ||
d105e7f8 FB |
828 | if (IS_ERR(dwc->usb2_phy)) { |
829 | ret = PTR_ERR(dwc->usb2_phy); | |
122f06e6 KVA |
830 | if (ret == -ENXIO || ret == -ENODEV) { |
831 | dwc->usb2_phy = NULL; | |
832 | } else if (ret == -EPROBE_DEFER) { | |
d105e7f8 | 833 | return ret; |
122f06e6 KVA |
834 | } else { |
835 | dev_err(dev, "no usb2 phy configured\n"); | |
836 | return ret; | |
837 | } | |
51e1e7bc FB |
838 | } |
839 | ||
d105e7f8 | 840 | if (IS_ERR(dwc->usb3_phy)) { |
315955d7 | 841 | ret = PTR_ERR(dwc->usb3_phy); |
122f06e6 KVA |
842 | if (ret == -ENXIO || ret == -ENODEV) { |
843 | dwc->usb3_phy = NULL; | |
844 | } else if (ret == -EPROBE_DEFER) { | |
d105e7f8 | 845 | return ret; |
122f06e6 KVA |
846 | } else { |
847 | dev_err(dev, "no usb3 phy configured\n"); | |
848 | return ret; | |
849 | } | |
51e1e7bc FB |
850 | } |
851 | ||
57303488 KVA |
852 | dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); |
853 | if (IS_ERR(dwc->usb2_generic_phy)) { | |
854 | ret = PTR_ERR(dwc->usb2_generic_phy); | |
855 | if (ret == -ENOSYS || ret == -ENODEV) { | |
856 | dwc->usb2_generic_phy = NULL; | |
857 | } else if (ret == -EPROBE_DEFER) { | |
858 | return ret; | |
859 | } else { | |
860 | dev_err(dev, "no usb2 phy configured\n"); | |
861 | return ret; | |
862 | } | |
863 | } | |
864 | ||
865 | dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); | |
866 | if (IS_ERR(dwc->usb3_generic_phy)) { | |
867 | ret = PTR_ERR(dwc->usb3_generic_phy); | |
868 | if (ret == -ENOSYS || ret == -ENODEV) { | |
869 | dwc->usb3_generic_phy = NULL; | |
870 | } else if (ret == -EPROBE_DEFER) { | |
871 | return ret; | |
872 | } else { | |
873 | dev_err(dev, "no usb3 phy configured\n"); | |
874 | return ret; | |
875 | } | |
876 | } | |
877 | ||
3c9f94ac FB |
878 | return 0; |
879 | } | |
880 | ||
5f94adfe FB |
881 | static int dwc3_core_init_mode(struct dwc3 *dwc) |
882 | { | |
883 | struct device *dev = dwc->dev; | |
884 | int ret; | |
885 | ||
886 | switch (dwc->dr_mode) { | |
887 | case USB_DR_MODE_PERIPHERAL: | |
5f94adfe FB |
888 | ret = dwc3_gadget_init(dwc); |
889 | if (ret) { | |
9522def4 RQ |
890 | if (ret != -EPROBE_DEFER) |
891 | dev_err(dev, "failed to initialize gadget\n"); | |
5f94adfe FB |
892 | return ret; |
893 | } | |
894 | break; | |
895 | case USB_DR_MODE_HOST: | |
5f94adfe FB |
896 | ret = dwc3_host_init(dwc); |
897 | if (ret) { | |
9522def4 RQ |
898 | if (ret != -EPROBE_DEFER) |
899 | dev_err(dev, "failed to initialize host\n"); | |
5f94adfe FB |
900 | return ret; |
901 | } | |
902 | break; | |
903 | case USB_DR_MODE_OTG: | |
5f94adfe FB |
904 | ret = dwc3_host_init(dwc); |
905 | if (ret) { | |
9522def4 RQ |
906 | if (ret != -EPROBE_DEFER) |
907 | dev_err(dev, "failed to initialize host\n"); | |
5f94adfe FB |
908 | return ret; |
909 | } | |
910 | ||
911 | ret = dwc3_gadget_init(dwc); | |
912 | if (ret) { | |
9522def4 RQ |
913 | if (ret != -EPROBE_DEFER) |
914 | dev_err(dev, "failed to initialize gadget\n"); | |
5f94adfe FB |
915 | return ret; |
916 | } | |
917 | break; | |
918 | default: | |
919 | dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); | |
920 | return -EINVAL; | |
921 | } | |
922 | ||
923 | return 0; | |
924 | } | |
925 | ||
926 | static void dwc3_core_exit_mode(struct dwc3 *dwc) | |
927 | { | |
928 | switch (dwc->dr_mode) { | |
929 | case USB_DR_MODE_PERIPHERAL: | |
930 | dwc3_gadget_exit(dwc); | |
931 | break; | |
932 | case USB_DR_MODE_HOST: | |
933 | dwc3_host_exit(dwc); | |
934 | break; | |
935 | case USB_DR_MODE_OTG: | |
936 | dwc3_host_exit(dwc); | |
937 | dwc3_gadget_exit(dwc); | |
938 | break; | |
939 | default: | |
940 | /* do nothing */ | |
941 | break; | |
942 | } | |
943 | } | |
944 | ||
3c9f94ac FB |
945 | #define DWC3_ALIGN_MASK (16 - 1) |
946 | ||
947 | static int dwc3_probe(struct platform_device *pdev) | |
948 | { | |
949 | struct device *dev = &pdev->dev; | |
3c9f94ac FB |
950 | struct resource *res; |
951 | struct dwc3 *dwc; | |
80caf7d2 | 952 | u8 lpm_nyet_threshold; |
6b6a0c9a | 953 | u8 tx_de_emphasis; |
460d098c | 954 | u8 hird_threshold; |
3c9f94ac | 955 | |
b09e99ee | 956 | int ret; |
3c9f94ac FB |
957 | |
958 | void __iomem *regs; | |
959 | void *mem; | |
960 | ||
961 | mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); | |
734d5a53 | 962 | if (!mem) |
3c9f94ac | 963 | return -ENOMEM; |
734d5a53 | 964 | |
3c9f94ac | 965 | dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); |
3c9f94ac FB |
966 | dwc->dev = dev; |
967 | ||
3c9f94ac FB |
968 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
969 | if (!res) { | |
970 | dev_err(dev, "missing memory resource\n"); | |
971 | return -ENODEV; | |
972 | } | |
973 | ||
f32a5e23 VG |
974 | dwc->xhci_resources[0].start = res->start; |
975 | dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + | |
976 | DWC3_XHCI_REGS_END; | |
977 | dwc->xhci_resources[0].flags = res->flags; | |
978 | dwc->xhci_resources[0].name = res->name; | |
979 | ||
980 | res->start += DWC3_GLOBALS_REGS_START; | |
981 | ||
982 | /* | |
983 | * Request memory region but exclude xHCI regs, | |
984 | * since it will be requested by the xhci-plat driver. | |
985 | */ | |
986 | regs = devm_ioremap_resource(dev, res); | |
3da1f6ee FB |
987 | if (IS_ERR(regs)) { |
988 | ret = PTR_ERR(regs); | |
989 | goto err0; | |
990 | } | |
f32a5e23 VG |
991 | |
992 | dwc->regs = regs; | |
993 | dwc->regs_size = resource_size(res); | |
f32a5e23 | 994 | |
80caf7d2 HR |
995 | /* default to highest possible threshold */ |
996 | lpm_nyet_threshold = 0xff; | |
997 | ||
6b6a0c9a HR |
998 | /* default to -3.5dB de-emphasis */ |
999 | tx_de_emphasis = 1; | |
1000 | ||
460d098c HR |
1001 | /* |
1002 | * default to assert utmi_sleep_n and use maximum allowed HIRD | |
1003 | * threshold value of 0b1100 | |
1004 | */ | |
1005 | hird_threshold = 12; | |
1006 | ||
63863b98 | 1007 | dwc->maximum_speed = usb_get_maximum_speed(dev); |
06e7114f | 1008 | dwc->dr_mode = usb_get_dr_mode(dev); |
32f2ed86 | 1009 | dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); |
63863b98 | 1010 | |
3d128919 | 1011 | dwc->has_lpm_erratum = device_property_read_bool(dev, |
80caf7d2 | 1012 | "snps,has-lpm-erratum"); |
3d128919 | 1013 | device_property_read_u8(dev, "snps,lpm-nyet-threshold", |
80caf7d2 | 1014 | &lpm_nyet_threshold); |
3d128919 | 1015 | dwc->is_utmi_l1_suspend = device_property_read_bool(dev, |
460d098c | 1016 | "snps,is-utmi-l1-suspend"); |
3d128919 | 1017 | device_property_read_u8(dev, "snps,hird-threshold", |
460d098c | 1018 | &hird_threshold); |
3d128919 | 1019 | dwc->usb3_lpm_capable = device_property_read_bool(dev, |
eac68e8f | 1020 | "snps,usb3_lpm_capable"); |
3c9f94ac | 1021 | |
3d128919 | 1022 | dwc->disable_scramble_quirk = device_property_read_bool(dev, |
3b81221a | 1023 | "snps,disable_scramble_quirk"); |
3d128919 | 1024 | dwc->u2exit_lfps_quirk = device_property_read_bool(dev, |
9a5b2f31 | 1025 | "snps,u2exit_lfps_quirk"); |
3d128919 | 1026 | dwc->u2ss_inp3_quirk = device_property_read_bool(dev, |
b5a65c40 | 1027 | "snps,u2ss_inp3_quirk"); |
3d128919 | 1028 | dwc->req_p1p2p3_quirk = device_property_read_bool(dev, |
df31f5b3 | 1029 | "snps,req_p1p2p3_quirk"); |
3d128919 | 1030 | dwc->del_p1p2p3_quirk = device_property_read_bool(dev, |
a2a1d0f5 | 1031 | "snps,del_p1p2p3_quirk"); |
3d128919 | 1032 | dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, |
41c06ffd | 1033 | "snps,del_phy_power_chg_quirk"); |
3d128919 | 1034 | dwc->lfps_filter_quirk = device_property_read_bool(dev, |
fb67afca | 1035 | "snps,lfps_filter_quirk"); |
3d128919 | 1036 | dwc->rx_detect_poll_quirk = device_property_read_bool(dev, |
14f4ac53 | 1037 | "snps,rx_detect_poll_quirk"); |
3d128919 | 1038 | dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, |
59acfa20 | 1039 | "snps,dis_u3_susphy_quirk"); |
3d128919 | 1040 | dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, |
0effe0a3 | 1041 | "snps,dis_u2_susphy_quirk"); |
ec791d14 JY |
1042 | dwc->dis_enblslpm_quirk = device_property_read_bool(dev, |
1043 | "snps,dis_enblslpm_quirk"); | |
e58dd357 RB |
1044 | dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, |
1045 | "snps,dis_rxdet_inp3_quirk"); | |
16199f33 WW |
1046 | dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, |
1047 | "snps,dis-u2-freeclk-exists-quirk"); | |
00fe081d WW |
1048 | dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, |
1049 | "snps,dis-del-phy-power-chg-quirk"); | |
6b6a0c9a | 1050 | |
3d128919 | 1051 | dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, |
6b6a0c9a | 1052 | "snps,tx_de_emphasis_quirk"); |
3d128919 | 1053 | device_property_read_u8(dev, "snps,tx_de_emphasis", |
6b6a0c9a | 1054 | &tx_de_emphasis); |
3d128919 HK |
1055 | device_property_read_string(dev, "snps,hsphy_interface", |
1056 | &dwc->hsphy_interface); | |
1057 | device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", | |
bcdb3272 | 1058 | &dwc->fladj); |
3d128919 | 1059 | |
80caf7d2 | 1060 | dwc->lpm_nyet_threshold = lpm_nyet_threshold; |
6b6a0c9a | 1061 | dwc->tx_de_emphasis = tx_de_emphasis; |
80caf7d2 | 1062 | |
460d098c HR |
1063 | dwc->hird_threshold = hird_threshold |
1064 | | (dwc->is_utmi_l1_suspend << 4); | |
1065 | ||
6c89cce0 | 1066 | platform_set_drvdata(pdev, dwc); |
2917e718 | 1067 | dwc3_cache_hwparams(dwc); |
6c89cce0 | 1068 | |
3c9f94ac FB |
1069 | ret = dwc3_core_get_phy(dwc); |
1070 | if (ret) | |
3da1f6ee | 1071 | goto err0; |
3c9f94ac | 1072 | |
72246da4 | 1073 | spin_lock_init(&dwc->lock); |
72246da4 | 1074 | |
19bacdc9 HK |
1075 | if (!dev->dma_mask) { |
1076 | dev->dma_mask = dev->parent->dma_mask; | |
1077 | dev->dma_parms = dev->parent->dma_parms; | |
1078 | dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask); | |
1079 | } | |
ddff14f1 | 1080 | |
fc8bb91b FB |
1081 | pm_runtime_set_active(dev); |
1082 | pm_runtime_use_autosuspend(dev); | |
1083 | pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); | |
802ca850 | 1084 | pm_runtime_enable(dev); |
32808237 RQ |
1085 | ret = pm_runtime_get_sync(dev); |
1086 | if (ret < 0) | |
1087 | goto err1; | |
1088 | ||
802ca850 | 1089 | pm_runtime_forbid(dev); |
72246da4 | 1090 | |
3921426b FB |
1091 | ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); |
1092 | if (ret) { | |
1093 | dev_err(dwc->dev, "failed to allocate event buffers\n"); | |
1094 | ret = -ENOMEM; | |
32808237 | 1095 | goto err2; |
3921426b FB |
1096 | } |
1097 | ||
9d6173e1 TN |
1098 | ret = dwc3_get_dr_mode(dwc); |
1099 | if (ret) | |
1100 | goto err3; | |
32a4a135 | 1101 | |
c499ff71 FB |
1102 | ret = dwc3_alloc_scratch_buffers(dwc); |
1103 | if (ret) | |
32808237 | 1104 | goto err3; |
c499ff71 | 1105 | |
72246da4 FB |
1106 | ret = dwc3_core_init(dwc); |
1107 | if (ret) { | |
802ca850 | 1108 | dev_err(dev, "failed to initialize core\n"); |
32808237 | 1109 | goto err4; |
72246da4 FB |
1110 | } |
1111 | ||
77966eb8 JY |
1112 | /* Check the maximum_speed parameter */ |
1113 | switch (dwc->maximum_speed) { | |
1114 | case USB_SPEED_LOW: | |
1115 | case USB_SPEED_FULL: | |
1116 | case USB_SPEED_HIGH: | |
1117 | case USB_SPEED_SUPER: | |
1118 | case USB_SPEED_SUPER_PLUS: | |
1119 | break; | |
1120 | default: | |
1121 | dev_err(dev, "invalid maximum_speed parameter %d\n", | |
1122 | dwc->maximum_speed); | |
1123 | /* fall through */ | |
1124 | case USB_SPEED_UNKNOWN: | |
1125 | /* default to superspeed */ | |
2c7f1bd9 JY |
1126 | dwc->maximum_speed = USB_SPEED_SUPER; |
1127 | ||
1128 | /* | |
1129 | * default to superspeed plus if we are capable. | |
1130 | */ | |
1131 | if (dwc3_is_usb31(dwc) && | |
1132 | (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == | |
1133 | DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) | |
1134 | dwc->maximum_speed = USB_SPEED_SUPER_PLUS; | |
77966eb8 JY |
1135 | |
1136 | break; | |
2c7f1bd9 JY |
1137 | } |
1138 | ||
5f94adfe FB |
1139 | ret = dwc3_core_init_mode(dwc); |
1140 | if (ret) | |
32808237 | 1141 | goto err5; |
72246da4 | 1142 | |
4e9f3118 | 1143 | dwc3_debugfs_init(dwc); |
fc8bb91b | 1144 | pm_runtime_put(dev); |
72246da4 FB |
1145 | |
1146 | return 0; | |
1147 | ||
32808237 | 1148 | err5: |
c499ff71 | 1149 | dwc3_event_buffers_cleanup(dwc); |
57303488 | 1150 | |
32808237 | 1151 | err4: |
c499ff71 | 1152 | dwc3_free_scratch_buffers(dwc); |
72246da4 | 1153 | |
32808237 | 1154 | err3: |
3921426b | 1155 | dwc3_free_event_buffers(dwc); |
88bc9d19 | 1156 | dwc3_ulpi_exit(dwc); |
3921426b | 1157 | |
32808237 RQ |
1158 | err2: |
1159 | pm_runtime_allow(&pdev->dev); | |
1160 | ||
1161 | err1: | |
1162 | pm_runtime_put_sync(&pdev->dev); | |
1163 | pm_runtime_disable(&pdev->dev); | |
1164 | ||
3da1f6ee FB |
1165 | err0: |
1166 | /* | |
1167 | * restore res->start back to its original value so that, in case the | |
1168 | * probe is deferred, we don't end up getting error in request the | |
1169 | * memory region the next time probe is called. | |
1170 | */ | |
1171 | res->start -= DWC3_GLOBALS_REGS_START; | |
1172 | ||
72246da4 FB |
1173 | return ret; |
1174 | } | |
1175 | ||
fb4e98ab | 1176 | static int dwc3_remove(struct platform_device *pdev) |
72246da4 | 1177 | { |
72246da4 | 1178 | struct dwc3 *dwc = platform_get_drvdata(pdev); |
3da1f6ee FB |
1179 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1180 | ||
fc8bb91b | 1181 | pm_runtime_get_sync(&pdev->dev); |
3da1f6ee FB |
1182 | /* |
1183 | * restore res->start back to its original value so that, in case the | |
1184 | * probe is deferred, we don't end up getting error in request the | |
1185 | * memory region the next time probe is called. | |
1186 | */ | |
1187 | res->start -= DWC3_GLOBALS_REGS_START; | |
72246da4 | 1188 | |
dc99f16f FB |
1189 | dwc3_debugfs_exit(dwc); |
1190 | dwc3_core_exit_mode(dwc); | |
8ba007a9 | 1191 | |
72246da4 | 1192 | dwc3_core_exit(dwc); |
88bc9d19 | 1193 | dwc3_ulpi_exit(dwc); |
72246da4 | 1194 | |
16b972a5 | 1195 | pm_runtime_put_sync(&pdev->dev); |
fc8bb91b | 1196 | pm_runtime_allow(&pdev->dev); |
72246da4 FB |
1197 | pm_runtime_disable(&pdev->dev); |
1198 | ||
fc8bb91b FB |
1199 | dwc3_free_event_buffers(dwc); |
1200 | dwc3_free_scratch_buffers(dwc); | |
1201 | ||
72246da4 FB |
1202 | return 0; |
1203 | } | |
1204 | ||
fc8bb91b FB |
1205 | #ifdef CONFIG_PM |
1206 | static int dwc3_suspend_common(struct dwc3 *dwc) | |
7415f17c | 1207 | { |
fc8bb91b | 1208 | unsigned long flags; |
7415f17c | 1209 | |
a45c82b8 RK |
1210 | switch (dwc->dr_mode) { |
1211 | case USB_DR_MODE_PERIPHERAL: | |
1212 | case USB_DR_MODE_OTG: | |
fc8bb91b | 1213 | spin_lock_irqsave(&dwc->lock, flags); |
7415f17c | 1214 | dwc3_gadget_suspend(dwc); |
fc8bb91b | 1215 | spin_unlock_irqrestore(&dwc->lock, flags); |
51f5d49a | 1216 | break; |
a45c82b8 | 1217 | case USB_DR_MODE_HOST: |
7415f17c | 1218 | default: |
51f5d49a | 1219 | /* do nothing */ |
7415f17c FB |
1220 | break; |
1221 | } | |
1222 | ||
51f5d49a | 1223 | dwc3_core_exit(dwc); |
5c4ad318 | 1224 | |
7415f17c FB |
1225 | return 0; |
1226 | } | |
1227 | ||
fc8bb91b | 1228 | static int dwc3_resume_common(struct dwc3 *dwc) |
7415f17c | 1229 | { |
fc8bb91b | 1230 | unsigned long flags; |
57303488 | 1231 | int ret; |
7415f17c | 1232 | |
51f5d49a FB |
1233 | ret = dwc3_core_init(dwc); |
1234 | if (ret) | |
5c4ad318 FB |
1235 | return ret; |
1236 | ||
a45c82b8 RK |
1237 | switch (dwc->dr_mode) { |
1238 | case USB_DR_MODE_PERIPHERAL: | |
1239 | case USB_DR_MODE_OTG: | |
fc8bb91b | 1240 | spin_lock_irqsave(&dwc->lock, flags); |
7415f17c | 1241 | dwc3_gadget_resume(dwc); |
fc8bb91b | 1242 | spin_unlock_irqrestore(&dwc->lock, flags); |
7415f17c | 1243 | /* FALLTHROUGH */ |
a45c82b8 | 1244 | case USB_DR_MODE_HOST: |
7415f17c FB |
1245 | default: |
1246 | /* do nothing */ | |
1247 | break; | |
1248 | } | |
1249 | ||
fc8bb91b FB |
1250 | return 0; |
1251 | } | |
1252 | ||
1253 | static int dwc3_runtime_checks(struct dwc3 *dwc) | |
1254 | { | |
1255 | switch (dwc->dr_mode) { | |
1256 | case USB_DR_MODE_PERIPHERAL: | |
1257 | case USB_DR_MODE_OTG: | |
1258 | if (dwc->connected) | |
1259 | return -EBUSY; | |
1260 | break; | |
1261 | case USB_DR_MODE_HOST: | |
1262 | default: | |
1263 | /* do nothing */ | |
1264 | break; | |
1265 | } | |
1266 | ||
1267 | return 0; | |
1268 | } | |
1269 | ||
1270 | static int dwc3_runtime_suspend(struct device *dev) | |
1271 | { | |
1272 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1273 | int ret; | |
1274 | ||
1275 | if (dwc3_runtime_checks(dwc)) | |
1276 | return -EBUSY; | |
1277 | ||
1278 | ret = dwc3_suspend_common(dwc); | |
1279 | if (ret) | |
1280 | return ret; | |
1281 | ||
1282 | device_init_wakeup(dev, true); | |
1283 | ||
1284 | return 0; | |
1285 | } | |
1286 | ||
1287 | static int dwc3_runtime_resume(struct device *dev) | |
1288 | { | |
1289 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1290 | int ret; | |
1291 | ||
1292 | device_init_wakeup(dev, false); | |
1293 | ||
1294 | ret = dwc3_resume_common(dwc); | |
1295 | if (ret) | |
1296 | return ret; | |
1297 | ||
1298 | switch (dwc->dr_mode) { | |
1299 | case USB_DR_MODE_PERIPHERAL: | |
1300 | case USB_DR_MODE_OTG: | |
1301 | dwc3_gadget_process_pending_events(dwc); | |
1302 | break; | |
1303 | case USB_DR_MODE_HOST: | |
1304 | default: | |
1305 | /* do nothing */ | |
1306 | break; | |
1307 | } | |
1308 | ||
1309 | pm_runtime_mark_last_busy(dev); | |
b74c2d87 | 1310 | pm_runtime_put(dev); |
fc8bb91b FB |
1311 | |
1312 | return 0; | |
1313 | } | |
1314 | ||
1315 | static int dwc3_runtime_idle(struct device *dev) | |
1316 | { | |
1317 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1318 | ||
1319 | switch (dwc->dr_mode) { | |
1320 | case USB_DR_MODE_PERIPHERAL: | |
1321 | case USB_DR_MODE_OTG: | |
1322 | if (dwc3_runtime_checks(dwc)) | |
1323 | return -EBUSY; | |
1324 | break; | |
1325 | case USB_DR_MODE_HOST: | |
1326 | default: | |
1327 | /* do nothing */ | |
1328 | break; | |
1329 | } | |
1330 | ||
1331 | pm_runtime_mark_last_busy(dev); | |
1332 | pm_runtime_autosuspend(dev); | |
1333 | ||
1334 | return 0; | |
1335 | } | |
1336 | #endif /* CONFIG_PM */ | |
1337 | ||
1338 | #ifdef CONFIG_PM_SLEEP | |
1339 | static int dwc3_suspend(struct device *dev) | |
1340 | { | |
1341 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1342 | int ret; | |
1343 | ||
1344 | ret = dwc3_suspend_common(dwc); | |
1345 | if (ret) | |
1346 | return ret; | |
1347 | ||
1348 | pinctrl_pm_select_sleep_state(dev); | |
1349 | ||
1350 | return 0; | |
1351 | } | |
1352 | ||
1353 | static int dwc3_resume(struct device *dev) | |
1354 | { | |
1355 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1356 | int ret; | |
1357 | ||
1358 | pinctrl_pm_select_default_state(dev); | |
1359 | ||
1360 | ret = dwc3_resume_common(dwc); | |
1361 | if (ret) | |
1362 | return ret; | |
1363 | ||
7415f17c FB |
1364 | pm_runtime_disable(dev); |
1365 | pm_runtime_set_active(dev); | |
1366 | pm_runtime_enable(dev); | |
1367 | ||
1368 | return 0; | |
1369 | } | |
7f370ed0 | 1370 | #endif /* CONFIG_PM_SLEEP */ |
7415f17c FB |
1371 | |
1372 | static const struct dev_pm_ops dwc3_dev_pm_ops = { | |
7415f17c | 1373 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) |
fc8bb91b FB |
1374 | SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, |
1375 | dwc3_runtime_idle) | |
7415f17c FB |
1376 | }; |
1377 | ||
5088b6f5 KVA |
1378 | #ifdef CONFIG_OF |
1379 | static const struct of_device_id of_dwc3_match[] = { | |
22a5aa17 FB |
1380 | { |
1381 | .compatible = "snps,dwc3" | |
1382 | }, | |
5088b6f5 KVA |
1383 | { |
1384 | .compatible = "synopsys,dwc3" | |
1385 | }, | |
1386 | { }, | |
1387 | }; | |
1388 | MODULE_DEVICE_TABLE(of, of_dwc3_match); | |
1389 | #endif | |
1390 | ||
404905a6 HK |
1391 | #ifdef CONFIG_ACPI |
1392 | ||
1393 | #define ACPI_ID_INTEL_BSW "808622B7" | |
1394 | ||
1395 | static const struct acpi_device_id dwc3_acpi_match[] = { | |
1396 | { ACPI_ID_INTEL_BSW, 0 }, | |
1397 | { }, | |
1398 | }; | |
1399 | MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); | |
1400 | #endif | |
1401 | ||
72246da4 FB |
1402 | static struct platform_driver dwc3_driver = { |
1403 | .probe = dwc3_probe, | |
7690417d | 1404 | .remove = dwc3_remove, |
72246da4 FB |
1405 | .driver = { |
1406 | .name = "dwc3", | |
5088b6f5 | 1407 | .of_match_table = of_match_ptr(of_dwc3_match), |
404905a6 | 1408 | .acpi_match_table = ACPI_PTR(dwc3_acpi_match), |
7f370ed0 | 1409 | .pm = &dwc3_dev_pm_ops, |
72246da4 | 1410 | }, |
72246da4 FB |
1411 | }; |
1412 | ||
b1116dcc TK |
1413 | module_platform_driver(dwc3_driver); |
1414 | ||
7ae4fc4d | 1415 | MODULE_ALIAS("platform:dwc3"); |
72246da4 | 1416 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); |
5945f789 | 1417 | MODULE_LICENSE("GPL v2"); |
72246da4 | 1418 | MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); |