projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
usb: dwc3: ulpi: make dwc3_ulpi_ops constant
[linux-block.git] / drivers / usb / dwc3 / core.c
CommitLineData
72246da4
FB		 1/**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4 17 *
5945f789
FB		 18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
72246da4
FB		 20 */
21
fa0ea13e 22#include <linux/version.h>
a72e658b 23#include <linux/module.h>
72246da4
FB		 24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/spinlock.h>
27#include <linux/platform_device.h>
28#include <linux/pm_runtime.h>
29#include <linux/interrupt.h>
30#include <linux/ioport.h>
31#include <linux/io.h>
32#include <linux/list.h>
33#include <linux/delay.h>
34#include <linux/dma-mapping.h>
457e84b6 35#include <linux/of.h>
404905a6 36#include <linux/acpi.h>
6344475f 37#include <linux/pinctrl/consumer.h>
72246da4
FB		 38
39#include <linux/usb/ch9.h>
40#include <linux/usb/gadget.h>
f7e846f0 41#include <linux/usb/of.h>
a45c82b8 42#include <linux/usb/otg.h>
72246da4
FB		 43
44#include "core.h"
45#include "gadget.h"
46#include "io.h"
47
48#include "debug.h"
49
fc8bb91b 50#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
8300dd23 51
3140e8cb
SAS		 52void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
53{
54 u32 reg;
55
56 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
57 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
58 reg |= DWC3_GCTL_PRTCAPDIR(mode);
59 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
60}
8300dd23 61
cf6d867d
FB		 62u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
63{
64 struct dwc3 *dwc = dep->dwc;
65 u32 reg;
66
67 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
68 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
69 DWC3_GDBGFIFOSPACE_TYPE(type));
70
71 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
72
73 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
74}
75
72246da4
FB		 76/**
77 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
78 * @dwc: pointer to our context structure
79 */
57303488 80static int dwc3_core_soft_reset(struct dwc3 *dwc)
72246da4
FB		 81{
82 u32 reg;
f59dcab1 83 int retries = 1000;
57303488 84 int ret;
72246da4 85
51e1e7bc
FB		 86 usb_phy_init(dwc->usb2_phy);
87 usb_phy_init(dwc->usb3_phy);
57303488
KVA		 88 ret = phy_init(dwc->usb2_generic_phy);
89 if (ret < 0)
90 return ret;
91
92 ret = phy_init(dwc->usb3_generic_phy);
93 if (ret < 0) {
94 phy_exit(dwc->usb2_generic_phy);
95 return ret;
96 }
72246da4 97
f59dcab1
FB		 98 /*
99 * We're resetting only the device side because, if we're in host mode,
100 * XHCI driver will reset the host block. If dwc3 was configured for
101 * host-only mode, then we can return early.
102 */
103 if (dwc->dr_mode == USB_DR_MODE_HOST)
104 return 0;
72246da4 105
f59dcab1
FB		 106 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
107 reg |= DWC3_DCTL_CSFTRST;
108 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 109
f59dcab1
FB		 110 do {
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 if (!(reg & DWC3_DCTL_CSFTRST))
113 return 0;
45627ac6 114
f59dcab1
FB		 115 udelay(1);
116 } while (--retries);
57303488 117
f59dcab1 118 return -ETIMEDOUT;
72246da4
FB		 119}
120
c5cc74e8
HK		 121/**
122 * dwc3_soft_reset - Issue soft reset
123 * @dwc: Pointer to our controller context structure
124 */
125static int dwc3_soft_reset(struct dwc3 *dwc)
126{
127 unsigned long timeout;
128 u32 reg;
129
130 timeout = jiffies + msecs_to_jiffies(500);
131 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
132 do {
133 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
134 if (!(reg & DWC3_DCTL_CSFTRST))
135 break;
136
137 if (time_after(jiffies, timeout)) {
138 dev_err(dwc->dev, "Reset Timed Out\n");
139 return -ETIMEDOUT;
140 }
141
142 cpu_relax();
143 } while (true);
144
145 return 0;
146}
147
db2be4e9
NB		 148/*
149 * dwc3_frame_length_adjustment - Adjusts frame length if required
150 * @dwc3: Pointer to our controller context structure
db2be4e9 151 */
bcdb3272 152static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
db2be4e9
NB		 153{
154 u32 reg;
155 u32 dft;
156
157 if (dwc->revision < DWC3_REVISION_250A)
158 return;
159
bcdb3272 160 if (dwc->fladj == 0)
db2be4e9
NB		 161 return;
162
163 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
164 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
bcdb3272 165 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
db2be4e9
NB		 166 "request value same as default, ignoring\n")) {
167 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
bcdb3272 168 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
db2be4e9
NB		 169 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
170 }
171}
172
72246da4
FB		 173/**
174 * dwc3_free_one_event_buffer - Frees one event buffer
175 * @dwc: Pointer to our controller context structure
176 * @evt: Pointer to event buffer to be freed
177 */
178static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
179 struct dwc3_event_buffer *evt)
180{
181 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
72246da4
FB		 182}
183
184/**
1d046793 185 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
72246da4
FB		 186 * @dwc: Pointer to our controller context structure
187 * @length: size of the event buffer
188 *
1d046793 189 * Returns a pointer to the allocated event buffer structure on success
72246da4
FB		 190 * otherwise ERR_PTR(errno).
191 */
67d0b500
FB		 192static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
193 unsigned length)
72246da4
FB		 194{
195 struct dwc3_event_buffer *evt;
196
380f0d28 197 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
72246da4
FB		 198 if (!evt)
199 return ERR_PTR(-ENOMEM);
200
201 evt->dwc = dwc;
202 evt->length = length;
203 evt->buf = dma_alloc_coherent(dwc->dev, length,
204 &evt->dma, GFP_KERNEL);
e32672f0 205 if (!evt->buf)
72246da4 206 return ERR_PTR(-ENOMEM);
72246da4
FB		 207
208 return evt;
209}
210
211/**
212 * dwc3_free_event_buffers - frees all allocated event buffers
213 * @dwc: Pointer to our controller context structure
214 */
215static void dwc3_free_event_buffers(struct dwc3 *dwc)
216{
217 struct dwc3_event_buffer *evt;
72246da4 218
696c8b12 219 evt = dwc->ev_buf;
660e9bde
FB		 220 if (evt)
221 dwc3_free_one_event_buffer(dwc, evt);
72246da4
FB		 222}
223
224/**
225 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
1d046793 226 * @dwc: pointer to our controller context structure
72246da4
FB		 227 * @length: size of event buffer
228 *
1d046793 229 * Returns 0 on success otherwise negative errno. In the error case, dwc
72246da4
FB		 230 * may contain some buffers allocated but not all which were requested.
231 */
41ac7b3a 232static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
72246da4 233{
660e9bde 234 struct dwc3_event_buffer *evt;
72246da4 235
660e9bde
FB		 236 evt = dwc3_alloc_one_event_buffer(dwc, length);
237 if (IS_ERR(evt)) {
238 dev_err(dwc->dev, "can't allocate event buffer\n");
239 return PTR_ERR(evt);
72246da4 240 }
696c8b12 241 dwc->ev_buf = evt;
72246da4
FB		 242
243 return 0;
244}
245
246/**
247 * dwc3_event_buffers_setup - setup our allocated event buffers
1d046793 248 * @dwc: pointer to our controller context structure
72246da4
FB		 249 *
250 * Returns 0 on success otherwise negative errno.
251 */
7acd85e0 252static int dwc3_event_buffers_setup(struct dwc3 *dwc)
72246da4
FB		 253{
254 struct dwc3_event_buffer *evt;
72246da4 255
696c8b12 256 evt = dwc->ev_buf;
660e9bde
FB		 257 dwc3_trace(trace_dwc3_core,
258 "Event buf %p dma %08llx length %d\n",
259 evt->buf, (unsigned long long) evt->dma,
260 evt->length);
261
262 evt->lpos = 0;
263
264 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
265 lower_32_bits(evt->dma));
266 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
267 upper_32_bits(evt->dma));
268 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
269 DWC3_GEVNTSIZ_SIZE(evt->length));
270 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 271
272 return 0;
273}
274
275static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
276{
277 struct dwc3_event_buffer *evt;
72246da4 278
696c8b12 279 evt = dwc->ev_buf;
7acd85e0 280
660e9bde 281 evt->lpos = 0;
7acd85e0 282
660e9bde
FB		 283 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
284 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
285 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
286 | DWC3_GEVNTSIZ_SIZE(0));
287 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 288}
289
0ffcaf37
FB		 290static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
291{
292 if (!dwc->has_hibernation)
293 return 0;
294
295 if (!dwc->nr_scratch)
296 return 0;
297
298 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
299 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
300 if (!dwc->scratchbuf)
301 return -ENOMEM;
302
303 return 0;
304}
305
306static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
307{
308 dma_addr_t scratch_addr;
309 u32 param;
310 int ret;
311
312 if (!dwc->has_hibernation)
313 return 0;
314
315 if (!dwc->nr_scratch)
316 return 0;
317
318 /* should never fall here */
319 if (!WARN_ON(dwc->scratchbuf))
320 return 0;
321
322 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
323 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
324 DMA_BIDIRECTIONAL);
325 if (dma_mapping_error(dwc->dev, scratch_addr)) {
326 dev_err(dwc->dev, "failed to map scratch buffer\n");
327 ret = -EFAULT;
328 goto err0;
329 }
330
331 dwc->scratch_addr = scratch_addr;
332
333 param = lower_32_bits(scratch_addr);
334
335 ret = dwc3_send_gadget_generic_command(dwc,
336 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
337 if (ret < 0)
338 goto err1;
339
340 param = upper_32_bits(scratch_addr);
341
342 ret = dwc3_send_gadget_generic_command(dwc,
343 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
344 if (ret < 0)
345 goto err1;
346
347 return 0;
348
349err1:
350 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
351 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
352
353err0:
354 return ret;
355}
356
357static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
358{
359 if (!dwc->has_hibernation)
360 return;
361
362 if (!dwc->nr_scratch)
363 return;
364
365 /* should never fall here */
366 if (!WARN_ON(dwc->scratchbuf))
367 return;
368
369 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
370 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
371 kfree(dwc->scratchbuf);
372}
373
789451f6
FB		 374static void dwc3_core_num_eps(struct dwc3 *dwc)
375{
376 struct dwc3_hwparams *parms = &dwc->hwparams;
377
378 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
379 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
380
73815280 381 dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
789451f6
FB		 382 dwc->num_in_eps, dwc->num_out_eps);
383}
384
41ac7b3a 385static void dwc3_cache_hwparams(struct dwc3 *dwc)
26ceca97
FB		 386{
387 struct dwc3_hwparams *parms = &dwc->hwparams;
388
389 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
390 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
391 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
392 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
393 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
394 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
395 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
396 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
397 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
398}
399
b5a65c40
HR		 400/**
401 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
402 * @dwc: Pointer to our controller context structure
88bc9d19
HK		 403 *
404 * Returns 0 on success. The USB PHY interfaces are configured but not
405 * initialized. The PHY interfaces and the PHYs get initialized together with
406 * the core in dwc3_core_init.
b5a65c40 407 */
88bc9d19 408static int dwc3_phy_setup(struct dwc3 *dwc)
b5a65c40
HR		 409{
410 u32 reg;
88bc9d19 411 int ret;
b5a65c40
HR		 412
413 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
414
2164a476
HR		 415 /*
416 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
417 * to '0' during coreConsultant configuration. So default value
418 * will be '0' when the core is reset. Application needs to set it
419 * to '1' after the core initialization is completed.
420 */
421 if (dwc->revision > DWC3_REVISION_194A)
422 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
423
b5a65c40
HR		 424 if (dwc->u2ss_inp3_quirk)
425 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
426
e58dd357
RB		 427 if (dwc->dis_rxdet_inp3_quirk)
428 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
429
df31f5b3
HR		 430 if (dwc->req_p1p2p3_quirk)
431 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
432
a2a1d0f5
HR		 433 if (dwc->del_p1p2p3_quirk)
434 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
435
41c06ffd
HR		 436 if (dwc->del_phy_power_chg_quirk)
437 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
438
fb67afca
HR		 439 if (dwc->lfps_filter_quirk)
440 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
441
14f4ac53
HR		 442 if (dwc->rx_detect_poll_quirk)
443 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
444
6b6a0c9a
HR		 445 if (dwc->tx_de_emphasis_quirk)
446 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
447
cd72f890 448 if (dwc->dis_u3_susphy_quirk)
59acfa20
HR		 449 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
450
00fe081d
WW		 451 if (dwc->dis_del_phy_power_chg_quirk)
452 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
453
b5a65c40
HR		 454 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
455
2164a476
HR		 456 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
457
3e10a2ce
HK		 458 /* Select the HS PHY interface */
459 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
460 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
43cacb03
FB		 461 if (dwc->hsphy_interface &&
462 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
3e10a2ce 463 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 464 break;
43cacb03
FB		 465 } else if (dwc->hsphy_interface &&
466 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
3e10a2ce 467 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 468 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
3e10a2ce 469 } else {
88bc9d19
HK		 470 /* Relying on default value. */
471 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
472 break;
3e10a2ce
HK		 473 }
474 /* FALLTHROUGH */
88bc9d19
HK		 475 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
476 /* Making sure the interface and PHY are operational */
477 ret = dwc3_soft_reset(dwc);
478 if (ret)
479 return ret;
480
481 udelay(1);
482
483 ret = dwc3_ulpi_init(dwc);
484 if (ret)
485 return ret;
486 /* FALLTHROUGH */
3e10a2ce
HK		 487 default:
488 break;
489 }
490
32f2ed86
WW		 491 switch (dwc->hsphy_mode) {
492 case USBPHY_INTERFACE_MODE_UTMI:
493 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
494 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
495 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
496 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
497 break;
498 case USBPHY_INTERFACE_MODE_UTMIW:
499 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
500 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
501 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
502 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
503 break;
504 default:
505 break;
506 }
507
2164a476
HR		 508 /*
509 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
510 * '0' during coreConsultant configuration. So default value will
511 * be '0' when the core is reset. Application needs to set it to
512 * '1' after the core initialization is completed.
513 */
514 if (dwc->revision > DWC3_REVISION_194A)
515 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
516
cd72f890 517 if (dwc->dis_u2_susphy_quirk)
0effe0a3
HR		 518 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
519
ec791d14
JY		 520 if (dwc->dis_enblslpm_quirk)
521 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
522
16199f33
WW		 523 if (dwc->dis_u2_freeclk_exists_quirk)
524 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
525
2164a476 526 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
88bc9d19
HK		 527
528 return 0;
b5a65c40
HR		 529}
530
c499ff71
FB		 531static void dwc3_core_exit(struct dwc3 *dwc)
532{
533 dwc3_event_buffers_cleanup(dwc);
534
535 usb_phy_shutdown(dwc->usb2_phy);
536 usb_phy_shutdown(dwc->usb3_phy);
537 phy_exit(dwc->usb2_generic_phy);
538 phy_exit(dwc->usb3_generic_phy);
539
540 usb_phy_set_suspend(dwc->usb2_phy, 1);
541 usb_phy_set_suspend(dwc->usb3_phy, 1);
542 phy_power_off(dwc->usb2_generic_phy);
543 phy_power_off(dwc->usb3_generic_phy);
544}
545
72246da4
FB		 546/**
547 * dwc3_core_init - Low-level initialization of DWC3 Core
548 * @dwc: Pointer to our controller context structure
549 *
550 * Returns 0 on success otherwise negative errno.
551 */
41ac7b3a 552static int dwc3_core_init(struct dwc3 *dwc)
72246da4 553{
0ffcaf37 554 u32 hwparams4 = dwc->hwparams.hwparams4;
72246da4
FB		 555 u32 reg;
556 int ret;
557
7650bd74
SAS		 558 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
559 /* This should read as U3 followed by revision number */
690fb371
JY		 560 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
561 /* Detected DWC_usb3 IP */
562 dwc->revision = reg;
563 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
564 /* Detected DWC_usb31 IP */
565 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
566 dwc->revision |= DWC3_REVISION_IS_DWC31;
567 } else {
7650bd74
SAS		 568 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
569 ret = -ENODEV;
570 goto err0;
571 }
7650bd74 572
fa0ea13e
FB		 573 /*
574 * Write Linux Version Code to our GUID register so it's easy to figure
575 * out which kernel version a bug was found.
576 */
577 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
578
0e1e5c47
PZ		 579 /* Handle USB2.0-only core configuration */
580 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
581 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
582 if (dwc->maximum_speed == USB_SPEED_SUPER)
583 dwc->maximum_speed = USB_SPEED_HIGH;
584 }
585
72246da4 586 /* issue device SoftReset too */
c5cc74e8
HK		 587 ret = dwc3_soft_reset(dwc);
588 if (ret)
589 goto err0;
72246da4 590
57303488
KVA		 591 ret = dwc3_core_soft_reset(dwc);
592 if (ret)
593 goto err0;
58a0f23f 594
c499ff71
FB		 595 ret = dwc3_phy_setup(dwc);
596 if (ret)
597 goto err0;
598
4878a028 599 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
3e87c42a 600 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
4878a028 601
164d7731 602 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
4878a028 603 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
32a4a135
FB		 604 /**
605 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
606 * issue which would cause xHCI compliance tests to fail.
607 *
608 * Because of that we cannot enable clock gating on such
609 * configurations.
610 *
611 * Refers to:
612 *
613 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
614 * SOF/ITP Mode Used
615 */
616 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
617 dwc->dr_mode == USB_DR_MODE_OTG) &&
618 (dwc->revision >= DWC3_REVISION_210A &&
619 dwc->revision <= DWC3_REVISION_250A))
620 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
621 else
622 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
4878a028 623 break;
0ffcaf37
FB		 624 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
625 /* enable hibernation here */
626 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
2eac3992
HR		 627
628 /*
629 * REVISIT Enabling this bit so that host-mode hibernation
630 * will work. Device-mode hibernation is not yet implemented.
631 */
632 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
0ffcaf37 633 break;
4878a028 634 default:
1407bf13 635 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
4878a028
SAS		 636 }
637
946bd579
HR		 638 /* check if current dwc3 is on simulation board */
639 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
1407bf13
FB		 640 dwc3_trace(trace_dwc3_core,
641 "running on FPGA platform\n");
946bd579
HR		 642 dwc->is_fpga = true;
643 }
644
3b81221a
HR		 645 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
646 "disable_scramble cannot be used on non-FPGA builds\n");
647
648 if (dwc->disable_scramble_quirk && dwc->is_fpga)
649 reg |= DWC3_GCTL_DISSCRAMBLE;
650 else
651 reg &= ~DWC3_GCTL_DISSCRAMBLE;
652
9a5b2f31
HR		 653 if (dwc->u2exit_lfps_quirk)
654 reg |= DWC3_GCTL_U2EXIT_LFPS;
655
4878a028
SAS		 656 /*
657 * WORKAROUND: DWC3 revisions <1.90a have a bug
1d046793 658 * where the device can fail to connect at SuperSpeed
4878a028 659 * and falls back to high-speed mode which causes
1d046793 660 * the device to enter a Connect/Disconnect loop
4878a028
SAS		 661 */
662 if (dwc->revision < DWC3_REVISION_190A)
663 reg |= DWC3_GCTL_U2RSTECN;
664
665 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
666
c499ff71 667 dwc3_core_num_eps(dwc);
0ffcaf37
FB		 668
669 ret = dwc3_setup_scratch_buffers(dwc);
670 if (ret)
c499ff71
FB		 671 goto err1;
672
673 /* Adjust Frame Length */
674 dwc3_frame_length_adjustment(dwc);
675
676 usb_phy_set_suspend(dwc->usb2_phy, 0);
677 usb_phy_set_suspend(dwc->usb3_phy, 0);
678 ret = phy_power_on(dwc->usb2_generic_phy);
679 if (ret < 0)
0ffcaf37
FB		 680 goto err2;
681
c499ff71
FB		 682 ret = phy_power_on(dwc->usb3_generic_phy);
683 if (ret < 0)
684 goto err3;
685
686 ret = dwc3_event_buffers_setup(dwc);
687 if (ret) {
688 dev_err(dwc->dev, "failed to setup event buffers\n");
689 goto err4;
690 }
691
00af6233
BW		 692 switch (dwc->dr_mode) {
693 case USB_DR_MODE_PERIPHERAL:
694 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
695 break;
696 case USB_DR_MODE_HOST:
697 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
698 break;
699 case USB_DR_MODE_OTG:
700 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
701 break;
702 default:
703 dev_warn(dwc->dev, "Unsupported mode %d\n", dwc->dr_mode);
704 break;
705 }
706
06281d46
JY		 707 /*
708 * ENDXFER polling is available on version 3.10a and later of
709 * the DWC_usb3 controller. It is NOT available in the
710 * DWC_usb31 controller.
711 */
712 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
713 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
714 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
715 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
716 }
717
72246da4
FB		 718 return 0;
719
c499ff71
FB		 720err4:
721 phy_power_off(dwc->usb2_generic_phy);
722
723err3:
724 phy_power_off(dwc->usb3_generic_phy);
725
0ffcaf37 726err2:
c499ff71
FB		 727 usb_phy_set_suspend(dwc->usb2_phy, 1);
728 usb_phy_set_suspend(dwc->usb3_phy, 1);
729 dwc3_core_exit(dwc);
0ffcaf37
FB		 730
731err1:
732 usb_phy_shutdown(dwc->usb2_phy);
733 usb_phy_shutdown(dwc->usb3_phy);
57303488
KVA		 734 phy_exit(dwc->usb2_generic_phy);
735 phy_exit(dwc->usb3_generic_phy);
0ffcaf37 736
72246da4
FB		 737err0:
738 return ret;
739}
740
3c9f94ac 741static int dwc3_core_get_phy(struct dwc3 *dwc)
72246da4 742{
3c9f94ac 743 struct device *dev = dwc->dev;
941ea361 744 struct device_node *node = dev->of_node;
3c9f94ac 745 int ret;
72246da4 746
5088b6f5
KVA		 747 if (node) {
748 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
749 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
bb674907
FB		 750 } else {
751 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
752 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
5088b6f5
KVA		 753 }
754
d105e7f8
FB		 755 if (IS_ERR(dwc->usb2_phy)) {
756 ret = PTR_ERR(dwc->usb2_phy);
122f06e6
KVA		 757 if (ret == -ENXIO || ret == -ENODEV) {
758 dwc->usb2_phy = NULL;
759 } else if (ret == -EPROBE_DEFER) {
d105e7f8 760 return ret;
122f06e6
KVA		 761 } else {
762 dev_err(dev, "no usb2 phy configured\n");
763 return ret;
764 }
51e1e7bc
FB		 765 }
766
d105e7f8 767 if (IS_ERR(dwc->usb3_phy)) {
315955d7 768 ret = PTR_ERR(dwc->usb3_phy);
122f06e6
KVA		 769 if (ret == -ENXIO || ret == -ENODEV) {
770 dwc->usb3_phy = NULL;
771 } else if (ret == -EPROBE_DEFER) {
d105e7f8 772 return ret;
122f06e6
KVA		 773 } else {
774 dev_err(dev, "no usb3 phy configured\n");
775 return ret;
776 }
51e1e7bc
FB		 777 }
778
57303488
KVA		 779 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
780 if (IS_ERR(dwc->usb2_generic_phy)) {
781 ret = PTR_ERR(dwc->usb2_generic_phy);
782 if (ret == -ENOSYS || ret == -ENODEV) {
783 dwc->usb2_generic_phy = NULL;
784 } else if (ret == -EPROBE_DEFER) {
785 return ret;
786 } else {
787 dev_err(dev, "no usb2 phy configured\n");
788 return ret;
789 }
790 }
791
792 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
793 if (IS_ERR(dwc->usb3_generic_phy)) {
794 ret = PTR_ERR(dwc->usb3_generic_phy);
795 if (ret == -ENOSYS || ret == -ENODEV) {
796 dwc->usb3_generic_phy = NULL;
797 } else if (ret == -EPROBE_DEFER) {
798 return ret;
799 } else {
800 dev_err(dev, "no usb3 phy configured\n");
801 return ret;
802 }
803 }
804
3c9f94ac
FB		 805 return 0;
806}
807
5f94adfe
FB		 808static int dwc3_core_init_mode(struct dwc3 *dwc)
809{
810 struct device *dev = dwc->dev;
811 int ret;
812
813 switch (dwc->dr_mode) {
814 case USB_DR_MODE_PERIPHERAL:
5f94adfe
FB		 815 ret = dwc3_gadget_init(dwc);
816 if (ret) {
9522def4
RQ		 817 if (ret != -EPROBE_DEFER)
818 dev_err(dev, "failed to initialize gadget\n");
5f94adfe
FB		 819 return ret;
820 }
821 break;
822 case USB_DR_MODE_HOST:
5f94adfe
FB		 823 ret = dwc3_host_init(dwc);
824 if (ret) {
9522def4
RQ		 825 if (ret != -EPROBE_DEFER)
826 dev_err(dev, "failed to initialize host\n");
5f94adfe
FB		 827 return ret;
828 }
829 break;
830 case USB_DR_MODE_OTG:
5f94adfe
FB		 831 ret = dwc3_host_init(dwc);
832 if (ret) {
9522def4
RQ		 833 if (ret != -EPROBE_DEFER)
834 dev_err(dev, "failed to initialize host\n");
5f94adfe
FB		 835 return ret;
836 }
837
838 ret = dwc3_gadget_init(dwc);
839 if (ret) {
9522def4
RQ		 840 if (ret != -EPROBE_DEFER)
841 dev_err(dev, "failed to initialize gadget\n");
5f94adfe
FB		 842 return ret;
843 }
844 break;
845 default:
846 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
847 return -EINVAL;
848 }
849
850 return 0;
851}
852
853static void dwc3_core_exit_mode(struct dwc3 *dwc)
854{
855 switch (dwc->dr_mode) {
856 case USB_DR_MODE_PERIPHERAL:
857 dwc3_gadget_exit(dwc);
858 break;
859 case USB_DR_MODE_HOST:
860 dwc3_host_exit(dwc);
861 break;
862 case USB_DR_MODE_OTG:
863 dwc3_host_exit(dwc);
864 dwc3_gadget_exit(dwc);
865 break;
866 default:
867 /* do nothing */
868 break;
869 }
870}
871
3c9f94ac
FB		 872#define DWC3_ALIGN_MASK (16 - 1)
873
874static int dwc3_probe(struct platform_device *pdev)
875{
876 struct device *dev = &pdev->dev;
3c9f94ac
FB		 877 struct resource *res;
878 struct dwc3 *dwc;
80caf7d2 879 u8 lpm_nyet_threshold;
6b6a0c9a 880 u8 tx_de_emphasis;
460d098c 881 u8 hird_threshold;
3c9f94ac 882
b09e99ee 883 int ret;
3c9f94ac
FB		 884
885 void __iomem *regs;
886 void *mem;
887
888 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
734d5a53 889 if (!mem)
3c9f94ac 890 return -ENOMEM;
734d5a53 891
3c9f94ac
FB		 892 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
893 dwc->mem = mem;
894 dwc->dev = dev;
895
3c9f94ac
FB		 896 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
897 if (!res) {
898 dev_err(dev, "missing memory resource\n");
899 return -ENODEV;
900 }
901
f32a5e23
VG		 902 dwc->xhci_resources[0].start = res->start;
903 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
904 DWC3_XHCI_REGS_END;
905 dwc->xhci_resources[0].flags = res->flags;
906 dwc->xhci_resources[0].name = res->name;
907
908 res->start += DWC3_GLOBALS_REGS_START;
909
910 /*
911 * Request memory region but exclude xHCI regs,
912 * since it will be requested by the xhci-plat driver.
913 */
914 regs = devm_ioremap_resource(dev, res);
3da1f6ee
FB		 915 if (IS_ERR(regs)) {
916 ret = PTR_ERR(regs);
917 goto err0;
918 }
f32a5e23
VG		 919
920 dwc->regs = regs;
921 dwc->regs_size = resource_size(res);
f32a5e23 922
80caf7d2
HR		 923 /* default to highest possible threshold */
924 lpm_nyet_threshold = 0xff;
925
6b6a0c9a
HR		 926 /* default to -3.5dB de-emphasis */
927 tx_de_emphasis = 1;
928
460d098c
HR		 929 /*
930 * default to assert utmi_sleep_n and use maximum allowed HIRD
931 * threshold value of 0b1100
932 */
933 hird_threshold = 12;
934
63863b98 935 dwc->maximum_speed = usb_get_maximum_speed(dev);
06e7114f 936 dwc->dr_mode = usb_get_dr_mode(dev);
32f2ed86 937 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
63863b98 938
3d128919 939 dwc->has_lpm_erratum = device_property_read_bool(dev,
80caf7d2 940 "snps,has-lpm-erratum");
3d128919 941 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
80caf7d2 942 &lpm_nyet_threshold);
3d128919 943 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
460d098c 944 "snps,is-utmi-l1-suspend");
3d128919 945 device_property_read_u8(dev, "snps,hird-threshold",
460d098c 946 &hird_threshold);
3d128919 947 dwc->usb3_lpm_capable = device_property_read_bool(dev,
eac68e8f 948 "snps,usb3_lpm_capable");
3c9f94ac 949
3d128919 950 dwc->disable_scramble_quirk = device_property_read_bool(dev,
3b81221a 951 "snps,disable_scramble_quirk");
3d128919 952 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
9a5b2f31 953 "snps,u2exit_lfps_quirk");
3d128919 954 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
b5a65c40 955 "snps,u2ss_inp3_quirk");
3d128919 956 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
df31f5b3 957 "snps,req_p1p2p3_quirk");
3d128919 958 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
a2a1d0f5 959 "snps,del_p1p2p3_quirk");
3d128919 960 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
41c06ffd 961 "snps,del_phy_power_chg_quirk");
3d128919 962 dwc->lfps_filter_quirk = device_property_read_bool(dev,
fb67afca 963 "snps,lfps_filter_quirk");
3d128919 964 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
14f4ac53 965 "snps,rx_detect_poll_quirk");
3d128919 966 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
59acfa20 967 "snps,dis_u3_susphy_quirk");
3d128919 968 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
0effe0a3 969 "snps,dis_u2_susphy_quirk");
ec791d14
JY		 970 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
971 "snps,dis_enblslpm_quirk");
e58dd357
RB		 972 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
973 "snps,dis_rxdet_inp3_quirk");
16199f33
WW		 974 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
975 "snps,dis-u2-freeclk-exists-quirk");
00fe081d
WW		 976 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
977 "snps,dis-del-phy-power-chg-quirk");
6b6a0c9a 978
3d128919 979 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
6b6a0c9a 980 "snps,tx_de_emphasis_quirk");
3d128919 981 device_property_read_u8(dev, "snps,tx_de_emphasis",
6b6a0c9a 982 &tx_de_emphasis);
3d128919
HK		 983 device_property_read_string(dev, "snps,hsphy_interface",
984 &dwc->hsphy_interface);
985 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
bcdb3272 986 &dwc->fladj);
3d128919 987
80caf7d2 988 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
6b6a0c9a 989 dwc->tx_de_emphasis = tx_de_emphasis;
80caf7d2 990
460d098c
HR		 991 dwc->hird_threshold = hird_threshold
992 | (dwc->is_utmi_l1_suspend << 4);
993
6c89cce0 994 platform_set_drvdata(pdev, dwc);
2917e718 995 dwc3_cache_hwparams(dwc);
6c89cce0 996
3c9f94ac
FB		 997 ret = dwc3_core_get_phy(dwc);
998 if (ret)
3da1f6ee 999 goto err0;
3c9f94ac 1000
72246da4 1001 spin_lock_init(&dwc->lock);
72246da4 1002
19bacdc9
HK		 1003 if (!dev->dma_mask) {
1004 dev->dma_mask = dev->parent->dma_mask;
1005 dev->dma_parms = dev->parent->dma_parms;
1006 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
1007 }
ddff14f1 1008
fc8bb91b
FB		 1009 pm_runtime_set_active(dev);
1010 pm_runtime_use_autosuspend(dev);
1011 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
802ca850 1012 pm_runtime_enable(dev);
32808237
RQ		 1013 ret = pm_runtime_get_sync(dev);
1014 if (ret < 0)
1015 goto err1;
1016
802ca850 1017 pm_runtime_forbid(dev);
72246da4 1018
3921426b
FB		 1019 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1020 if (ret) {
1021 dev_err(dwc->dev, "failed to allocate event buffers\n");
1022 ret = -ENOMEM;
32808237 1023 goto err2;
3921426b
FB		 1024 }
1025
5f82279a
FB		 1026 if (IS_ENABLED(CONFIG_USB_DWC3_HOST) &&
1027 (dwc->dr_mode == USB_DR_MODE_OTG ||
1028 dwc->dr_mode == USB_DR_MODE_UNKNOWN))
32a4a135 1029 dwc->dr_mode = USB_DR_MODE_HOST;
5f82279a
FB		 1030 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET) &&
1031 (dwc->dr_mode == USB_DR_MODE_OTG ||
1032 dwc->dr_mode == USB_DR_MODE_UNKNOWN))
32a4a135
FB		 1033 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1034
1035 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
1036 dwc->dr_mode = USB_DR_MODE_OTG;
1037
c499ff71
FB		 1038 ret = dwc3_alloc_scratch_buffers(dwc);
1039 if (ret)
32808237 1040 goto err3;
c499ff71 1041
72246da4
FB		 1042 ret = dwc3_core_init(dwc);
1043 if (ret) {
802ca850 1044 dev_err(dev, "failed to initialize core\n");
32808237 1045 goto err4;
72246da4
FB		 1046 }
1047
77966eb8
JY		 1048 /* Check the maximum_speed parameter */
1049 switch (dwc->maximum_speed) {
1050 case USB_SPEED_LOW:
1051 case USB_SPEED_FULL:
1052 case USB_SPEED_HIGH:
1053 case USB_SPEED_SUPER:
1054 case USB_SPEED_SUPER_PLUS:
1055 break;
1056 default:
1057 dev_err(dev, "invalid maximum_speed parameter %d\n",
1058 dwc->maximum_speed);
1059 /* fall through */
1060 case USB_SPEED_UNKNOWN:
1061 /* default to superspeed */
2c7f1bd9
JY		 1062 dwc->maximum_speed = USB_SPEED_SUPER;
1063
1064 /*
1065 * default to superspeed plus if we are capable.
1066 */
1067 if (dwc3_is_usb31(dwc) &&
1068 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1069 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1070 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
77966eb8
JY		 1071
1072 break;
2c7f1bd9
JY		 1073 }
1074
5f94adfe
FB		 1075 ret = dwc3_core_init_mode(dwc);
1076 if (ret)
32808237 1077 goto err5;
72246da4 1078
4e9f3118 1079 dwc3_debugfs_init(dwc);
fc8bb91b 1080 pm_runtime_put(dev);
72246da4
FB		 1081
1082 return 0;
1083
32808237 1084err5:
c499ff71 1085 dwc3_event_buffers_cleanup(dwc);
57303488 1086
32808237 1087err4:
c499ff71 1088 dwc3_free_scratch_buffers(dwc);
72246da4 1089
32808237 1090err3:
3921426b 1091 dwc3_free_event_buffers(dwc);
88bc9d19 1092 dwc3_ulpi_exit(dwc);
3921426b 1093
32808237
RQ		 1094err2:
1095 pm_runtime_allow(&pdev->dev);
1096
1097err1:
1098 pm_runtime_put_sync(&pdev->dev);
1099 pm_runtime_disable(&pdev->dev);
1100
3da1f6ee
FB		 1101err0:
1102 /*
1103 * restore res->start back to its original value so that, in case the
1104 * probe is deferred, we don't end up getting error in request the
1105 * memory region the next time probe is called.
1106 */
1107 res->start -= DWC3_GLOBALS_REGS_START;
1108
72246da4
FB		 1109 return ret;
1110}
1111
fb4e98ab 1112static int dwc3_remove(struct platform_device *pdev)
72246da4 1113{
72246da4 1114 struct dwc3 *dwc = platform_get_drvdata(pdev);
3da1f6ee
FB		 1115 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1116
fc8bb91b 1117 pm_runtime_get_sync(&pdev->dev);
3da1f6ee
FB		 1118 /*
1119 * restore res->start back to its original value so that, in case the
1120 * probe is deferred, we don't end up getting error in request the
1121 * memory region the next time probe is called.
1122 */
1123 res->start -= DWC3_GLOBALS_REGS_START;
72246da4 1124
dc99f16f
FB		 1125 dwc3_debugfs_exit(dwc);
1126 dwc3_core_exit_mode(dwc);
8ba007a9 1127
72246da4 1128 dwc3_core_exit(dwc);
88bc9d19 1129 dwc3_ulpi_exit(dwc);
72246da4 1130
16b972a5 1131 pm_runtime_put_sync(&pdev->dev);
fc8bb91b 1132 pm_runtime_allow(&pdev->dev);
72246da4
FB		 1133 pm_runtime_disable(&pdev->dev);
1134
fc8bb91b
FB		 1135 dwc3_free_event_buffers(dwc);
1136 dwc3_free_scratch_buffers(dwc);
1137
72246da4
FB		 1138 return 0;
1139}
1140
fc8bb91b
FB		 1141#ifdef CONFIG_PM
1142static int dwc3_suspend_common(struct dwc3 *dwc)
7415f17c 1143{
fc8bb91b 1144 unsigned long flags;
7415f17c 1145
a45c82b8
RK		 1146 switch (dwc->dr_mode) {
1147 case USB_DR_MODE_PERIPHERAL:
1148 case USB_DR_MODE_OTG:
fc8bb91b 1149 spin_lock_irqsave(&dwc->lock, flags);
7415f17c 1150 dwc3_gadget_suspend(dwc);
fc8bb91b 1151 spin_unlock_irqrestore(&dwc->lock, flags);
51f5d49a 1152 break;
a45c82b8 1153 case USB_DR_MODE_HOST:
7415f17c 1154 default:
51f5d49a 1155 /* do nothing */
7415f17c
FB		 1156 break;
1157 }
1158
51f5d49a 1159 dwc3_core_exit(dwc);
5c4ad318 1160
7415f17c
FB		 1161 return 0;
1162}
1163
fc8bb91b 1164static int dwc3_resume_common(struct dwc3 *dwc)
7415f17c 1165{
fc8bb91b 1166 unsigned long flags;
57303488 1167 int ret;
7415f17c 1168
51f5d49a
FB		 1169 ret = dwc3_core_init(dwc);
1170 if (ret)
5c4ad318
FB		 1171 return ret;
1172
a45c82b8
RK		 1173 switch (dwc->dr_mode) {
1174 case USB_DR_MODE_PERIPHERAL:
1175 case USB_DR_MODE_OTG:
fc8bb91b 1176 spin_lock_irqsave(&dwc->lock, flags);
7415f17c 1177 dwc3_gadget_resume(dwc);
fc8bb91b 1178 spin_unlock_irqrestore(&dwc->lock, flags);
7415f17c 1179 /* FALLTHROUGH */
a45c82b8 1180 case USB_DR_MODE_HOST:
7415f17c
FB		 1181 default:
1182 /* do nothing */
1183 break;
1184 }
1185
fc8bb91b
FB		 1186 return 0;
1187}
1188
1189static int dwc3_runtime_checks(struct dwc3 *dwc)
1190{
1191 switch (dwc->dr_mode) {
1192 case USB_DR_MODE_PERIPHERAL:
1193 case USB_DR_MODE_OTG:
1194 if (dwc->connected)
1195 return -EBUSY;
1196 break;
1197 case USB_DR_MODE_HOST:
1198 default:
1199 /* do nothing */
1200 break;
1201 }
1202
1203 return 0;
1204}
1205
1206static int dwc3_runtime_suspend(struct device *dev)
1207{
1208 struct dwc3 *dwc = dev_get_drvdata(dev);
1209 int ret;
1210
1211 if (dwc3_runtime_checks(dwc))
1212 return -EBUSY;
1213
1214 ret = dwc3_suspend_common(dwc);
1215 if (ret)
1216 return ret;
1217
1218 device_init_wakeup(dev, true);
1219
1220 return 0;
1221}
1222
1223static int dwc3_runtime_resume(struct device *dev)
1224{
1225 struct dwc3 *dwc = dev_get_drvdata(dev);
1226 int ret;
1227
1228 device_init_wakeup(dev, false);
1229
1230 ret = dwc3_resume_common(dwc);
1231 if (ret)
1232 return ret;
1233
1234 switch (dwc->dr_mode) {
1235 case USB_DR_MODE_PERIPHERAL:
1236 case USB_DR_MODE_OTG:
1237 dwc3_gadget_process_pending_events(dwc);
1238 break;
1239 case USB_DR_MODE_HOST:
1240 default:
1241 /* do nothing */
1242 break;
1243 }
1244
1245 pm_runtime_mark_last_busy(dev);
1246
1247 return 0;
1248}
1249
1250static int dwc3_runtime_idle(struct device *dev)
1251{
1252 struct dwc3 *dwc = dev_get_drvdata(dev);
1253
1254 switch (dwc->dr_mode) {
1255 case USB_DR_MODE_PERIPHERAL:
1256 case USB_DR_MODE_OTG:
1257 if (dwc3_runtime_checks(dwc))
1258 return -EBUSY;
1259 break;
1260 case USB_DR_MODE_HOST:
1261 default:
1262 /* do nothing */
1263 break;
1264 }
1265
1266 pm_runtime_mark_last_busy(dev);
1267 pm_runtime_autosuspend(dev);
1268
1269 return 0;
1270}
1271#endif /* CONFIG_PM */
1272
1273#ifdef CONFIG_PM_SLEEP
1274static int dwc3_suspend(struct device *dev)
1275{
1276 struct dwc3 *dwc = dev_get_drvdata(dev);
1277 int ret;
1278
1279 ret = dwc3_suspend_common(dwc);
1280 if (ret)
1281 return ret;
1282
1283 pinctrl_pm_select_sleep_state(dev);
1284
1285 return 0;
1286}
1287
1288static int dwc3_resume(struct device *dev)
1289{
1290 struct dwc3 *dwc = dev_get_drvdata(dev);
1291 int ret;
1292
1293 pinctrl_pm_select_default_state(dev);
1294
1295 ret = dwc3_resume_common(dwc);
1296 if (ret)
1297 return ret;
1298
7415f17c
FB		 1299 pm_runtime_disable(dev);
1300 pm_runtime_set_active(dev);
1301 pm_runtime_enable(dev);
1302
1303 return 0;
1304}
7f370ed0 1305#endif /* CONFIG_PM_SLEEP */
7415f17c
FB		 1306
1307static const struct dev_pm_ops dwc3_dev_pm_ops = {
7415f17c 1308 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
fc8bb91b
FB		 1309 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1310 dwc3_runtime_idle)
7415f17c
FB		 1311};
1312
5088b6f5
KVA		 1313#ifdef CONFIG_OF
1314static const struct of_device_id of_dwc3_match[] = {
22a5aa17
FB		 1315 {
1316 .compatible = "snps,dwc3"
1317 },
5088b6f5
KVA		 1318 {
1319 .compatible = "synopsys,dwc3"
1320 },
1321 { },
1322};
1323MODULE_DEVICE_TABLE(of, of_dwc3_match);
1324#endif
1325
404905a6
HK		 1326#ifdef CONFIG_ACPI
1327
1328#define ACPI_ID_INTEL_BSW "808622B7"
1329
1330static const struct acpi_device_id dwc3_acpi_match[] = {
1331 { ACPI_ID_INTEL_BSW, 0 },
1332 { },
1333};
1334MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1335#endif
1336
72246da4
FB		 1337static struct platform_driver dwc3_driver = {
1338 .probe = dwc3_probe,
7690417d 1339 .remove = dwc3_remove,
72246da4
FB		 1340 .driver = {
1341 .name = "dwc3",
5088b6f5 1342 .of_match_table = of_match_ptr(of_dwc3_match),
404905a6 1343 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
7f370ed0 1344 .pm = &dwc3_dev_pm_ops,
72246da4 1345 },
72246da4
FB		 1346};
1347
b1116dcc
TK		 1348module_platform_driver(dwc3_driver);
1349
7ae4fc4d 1350MODULE_ALIAS("platform:dwc3");
72246da4 1351MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
5945f789 1352MODULE_LICENSE("GPL v2");
72246da4 1353MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux 6.x block layer and io_uring tree(s)