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Merge tag 'char-misc-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh...
[linux-block.git] / drivers / usb / dwc3 / core.c
CommitLineData
5fd54ace 1// SPDX-License-Identifier: GPL-2.0
cbdc0f54 2/*
72246da4
FB		 3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
10623b87 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
72246da4
FB		 6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
72246da4
FB		 9 */
10
fe8abf33 11#include <linux/clk.h>
fa0ea13e 12#include <linux/version.h>
a72e658b 13#include <linux/module.h>
72246da4
FB		 14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/io.h>
22#include <linux/list.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
457e84b6 25#include <linux/of.h>
d182c2e1 26#include <linux/of_graph.h>
404905a6 27#include <linux/acpi.h>
6344475f 28#include <linux/pinctrl/consumer.h>
fe8abf33 29#include <linux/reset.h>
7bee3188 30#include <linux/bitfield.h>
72246da4
FB		 31
32#include <linux/usb/ch9.h>
33#include <linux/usb/gadget.h>
f7e846f0 34#include <linux/usb/of.h>
a45c82b8 35#include <linux/usb/otg.h>
72246da4
FB		 36
37#include "core.h"
38#include "gadget.h"
39#include "io.h"
40
41#include "debug.h"
42
fc8bb91b 43#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
8300dd23 44
9d6173e1
TN		 45/**
46 * dwc3_get_dr_mode - Validates and sets dr_mode
47 * @dwc: pointer to our context structure
48 */
49static int dwc3_get_dr_mode(struct dwc3 *dwc)
50{
51 enum usb_dr_mode mode;
52 struct device *dev = dwc->dev;
53 unsigned int hw_mode;
54
55 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
56 dwc->dr_mode = USB_DR_MODE_OTG;
57
58 mode = dwc->dr_mode;
59 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
60
61 switch (hw_mode) {
62 case DWC3_GHWPARAMS0_MODE_GADGET:
63 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
64 dev_err(dev,
65 "Controller does not support host mode.\n");
66 return -EINVAL;
67 }
68 mode = USB_DR_MODE_PERIPHERAL;
69 break;
70 case DWC3_GHWPARAMS0_MODE_HOST:
71 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
72 dev_err(dev,
73 "Controller does not support device mode.\n");
74 return -EINVAL;
75 }
76 mode = USB_DR_MODE_HOST;
77 break;
78 default:
79 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
80 mode = USB_DR_MODE_HOST;
81 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
82 mode = USB_DR_MODE_PERIPHERAL;
a7700468
TN		 83
84 /*
89a9cc47
TN		 85 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
86 * mode. If the controller supports DRD but the dr_mode is not
87 * specified or set to OTG, then set the mode to peripheral.
a7700468 88 */
d182c2e1 89 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
8bb14308
TN		 90 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
91 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
9af21dd6 92 !DWC3_VER_IS_PRIOR(DWC3, 330A))
a7700468 93 mode = USB_DR_MODE_PERIPHERAL;
9d6173e1
TN		 94 }
95
96 if (mode != dwc->dr_mode) {
97 dev_warn(dev,
98 "Configuration mismatch. dr_mode forced to %s\n",
99 mode == USB_DR_MODE_HOST ? "host" : "gadget");
100
101 dwc->dr_mode = mode;
102 }
103
104 return 0;
105}
106
f09cc79b 107void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
3140e8cb
SAS		 108{
109 u32 reg;
110
111 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
112 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
113 reg |= DWC3_GCTL_PRTCAPDIR(mode);
114 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
c4a5153e
MG		 115
116 dwc->current_dr_role = mode;
41ce1456
RQ		 117}
118
119static void __dwc3_set_mode(struct work_struct *work)
120{
121 struct dwc3 *dwc = work_to_dwc(work);
122 unsigned long flags;
123 int ret;
f580170f 124 u32 reg;
62c73bfe 125 u32 desired_dr_role;
41ce1456 126
f88359e1 127 mutex_lock(&dwc->mutex);
62c73bfe
SP		 128 spin_lock_irqsave(&dwc->lock, flags);
129 desired_dr_role = dwc->desired_dr_role;
130 spin_unlock_irqrestore(&dwc->lock, flags);
f88359e1 131
c2cd3452
MK		 132 pm_runtime_get_sync(dwc->dev);
133
f09cc79b
RQ		 134 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
135 dwc3_otg_update(dwc, 0);
136
62c73bfe 137 if (!desired_dr_role)
c2cd3452 138 goto out;
41ce1456 139
62c73bfe 140 if (desired_dr_role == dwc->current_dr_role)
c2cd3452 141 goto out;
41ce1456 142
62c73bfe 143 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
c2cd3452 144 goto out;
41ce1456
RQ		 145
146 switch (dwc->current_dr_role) {
147 case DWC3_GCTL_PRTCAP_HOST:
148 dwc3_host_exit(dwc);
149 break;
150 case DWC3_GCTL_PRTCAP_DEVICE:
151 dwc3_gadget_exit(dwc);
152 dwc3_event_buffers_cleanup(dwc);
153 break;
f09cc79b
RQ		 154 case DWC3_GCTL_PRTCAP_OTG:
155 dwc3_otg_exit(dwc);
156 spin_lock_irqsave(&dwc->lock, flags);
157 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
158 spin_unlock_irqrestore(&dwc->lock, flags);
159 dwc3_otg_update(dwc, 1);
160 break;
41ce1456
RQ		 161 default:
162 break;
163 }
164
07903626
RK		 165 /*
166 * When current_dr_role is not set, there's no role switching.
167 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
168 */
169 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
170 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
62c73bfe 171 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
f88359e1
YC		 172 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
173 reg |= DWC3_GCTL_CORESOFTRESET;
174 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
175
176 /*
177 * Wait for internal clocks to synchronized. DWC_usb31 and
178 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
179 * keep it consistent across different IPs, let's wait up to
180 * 100ms before clearing GCTL.CORESOFTRESET.
181 */
182 msleep(100);
183
184 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
185 reg &= ~DWC3_GCTL_CORESOFTRESET;
186 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
187 }
188
41ce1456
RQ		 189 spin_lock_irqsave(&dwc->lock, flags);
190
62c73bfe 191 dwc3_set_prtcap(dwc, desired_dr_role);
6b3261a2 192
41ce1456
RQ		 193 spin_unlock_irqrestore(&dwc->lock, flags);
194
62c73bfe 195 switch (desired_dr_role) {
41ce1456
RQ		 196 case DWC3_GCTL_PRTCAP_HOST:
197 ret = dwc3_host_init(dwc);
958d1a4c 198 if (ret) {
41ce1456 199 dev_err(dwc->dev, "failed to initialize host\n");
958d1a4c
FB		 200 } else {
201 if (dwc->usb2_phy)
202 otg_set_vbus(dwc->usb2_phy->otg, true);
644cbbc3
MG		 203 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
204 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
f580170f
YC		 205 if (dwc->dis_split_quirk) {
206 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
207 reg |= DWC3_GUCTL3_SPLITDISABLE;
208 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
209 }
958d1a4c 210 }
41ce1456
RQ		 211 break;
212 case DWC3_GCTL_PRTCAP_DEVICE:
f88359e1
YC		 213 dwc3_core_soft_reset(dwc);
214
41ce1456 215 dwc3_event_buffers_setup(dwc);
958d1a4c
FB		 216
217 if (dwc->usb2_phy)
218 otg_set_vbus(dwc->usb2_phy->otg, false);
644cbbc3
MG		 219 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
220 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
958d1a4c 221
41ce1456
RQ		 222 ret = dwc3_gadget_init(dwc);
223 if (ret)
224 dev_err(dwc->dev, "failed to initialize peripheral\n");
225 break;
f09cc79b
RQ		 226 case DWC3_GCTL_PRTCAP_OTG:
227 dwc3_otg_init(dwc);
228 dwc3_otg_update(dwc, 0);
229 break;
41ce1456
RQ		 230 default:
231 break;
232 }
f09cc79b 233
c2cd3452
MK		 234out:
235 pm_runtime_mark_last_busy(dwc->dev);
236 pm_runtime_put_autosuspend(dwc->dev);
f88359e1 237 mutex_unlock(&dwc->mutex);
41ce1456
RQ		 238}
239
240void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
241{
242 unsigned long flags;
243
dc336b19
LJ		 244 if (dwc->dr_mode != USB_DR_MODE_OTG)
245 return;
246
41ce1456
RQ		 247 spin_lock_irqsave(&dwc->lock, flags);
248 dwc->desired_dr_role = mode;
249 spin_unlock_irqrestore(&dwc->lock, flags);
250
084a804e 251 queue_work(system_freezable_wq, &dwc->drd_work);
3140e8cb 252}
8300dd23 253
cf6d867d
FB		 254u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
255{
256 struct dwc3 *dwc = dep->dwc;
257 u32 reg;
258
259 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
260 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
261 DWC3_GDBGFIFOSPACE_TYPE(type));
262
263 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
264
265 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
266}
267
72246da4
FB		 268/**
269 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
270 * @dwc: pointer to our context structure
271 */
0066472d 272int dwc3_core_soft_reset(struct dwc3 *dwc)
72246da4
FB		 273{
274 u32 reg;
f59dcab1 275 int retries = 1000;
72246da4 276
f59dcab1
FB		 277 /*
278 * We're resetting only the device side because, if we're in host mode,
279 * XHCI driver will reset the host block. If dwc3 was configured for
280 * host-only mode, then we can return early.
281 */
c4a5153e 282 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
f59dcab1 283 return 0;
72246da4 284
f59dcab1
FB		 285 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
286 reg |= DWC3_DCTL_CSFTRST;
f4fd84ae
TN		 287 reg &= ~DWC3_DCTL_RUN_STOP;
288 dwc3_gadget_dctl_write_safe(dwc, reg);
72246da4 289
4749e0e6
TN		 290 /*
291 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
292 * is cleared only after all the clocks are synchronized. This can
293 * take a little more than 50ms. Set the polling rate at 20ms
294 * for 10 times instead.
295 */
9af21dd6 296 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
4749e0e6
TN		 297 retries = 10;
298
f59dcab1
FB		 299 do {
300 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
301 if (!(reg & DWC3_DCTL_CSFTRST))
fab38333 302 goto done;
45627ac6 303
9af21dd6 304 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
4749e0e6
TN		 305 msleep(20);
306 else
307 udelay(1);
f59dcab1 308 } while (--retries);
57303488 309
859bdc35 310 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
f59dcab1 311 return -ETIMEDOUT;
fab38333
TN		 312
313done:
314 /*
4749e0e6
TN		 315 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
316 * is cleared, we must wait at least 50ms before accessing the PHY
317 * domain (synchronization delay).
fab38333 318 */
9af21dd6 319 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
fab38333
TN		 320 msleep(50);
321
322 return 0;
72246da4
FB		 323}
324
db2be4e9
NB		 325/*
326 * dwc3_frame_length_adjustment - Adjusts frame length if required
327 * @dwc3: Pointer to our controller context structure
db2be4e9 328 */
bcdb3272 329static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
db2be4e9
NB		 330{
331 u32 reg;
332 u32 dft;
333
9af21dd6 334 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
db2be4e9
NB		 335 return;
336
bcdb3272 337 if (dwc->fladj == 0)
db2be4e9
NB		 338 return;
339
340 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
341 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
a7d9874c 342 if (dft != dwc->fladj) {
db2be4e9 343 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
bcdb3272 344 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
db2be4e9
NB		 345 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
346 }
347}
348
7bee3188
BP		 349/**
350 * dwc3_ref_clk_period - Reference clock period configuration
351 * Default reference clock period depends on hardware
352 * configuration. For systems with reference clock that differs
353 * from the default, this will set clock period in DWC3_GUCTL
354 * register.
355 * @dwc: Pointer to our controller context structure
7bee3188
BP		 356 */
357static void dwc3_ref_clk_period(struct dwc3 *dwc)
358{
5114c3ee 359 unsigned long period;
596c8785
SA		 360 unsigned long fladj;
361 unsigned long decr;
5114c3ee 362 unsigned long rate;
7bee3188
BP		 363 u32 reg;
364
5114c3ee
SA		 365 if (dwc->ref_clk) {
366 rate = clk_get_rate(dwc->ref_clk);
367 if (!rate)
368 return;
369 period = NSEC_PER_SEC / rate;
370 } else if (dwc->ref_clk_per) {
371 period = dwc->ref_clk_per;
596c8785 372 rate = NSEC_PER_SEC / period;
5114c3ee 373 } else {
7bee3188 374 return;
5114c3ee 375 }
7bee3188
BP		 376
377 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
378 reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
5114c3ee 379 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
7bee3188 380 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
7bee3188 381
596c8785
SA		 382 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
383 return;
384
385 /*
386 * The calculation below is
387 *
388 * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
389 *
390 * but rearranged for fixed-point arithmetic. The division must be
391 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
392 * neither does rate * period).
393 *
394 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
395 * nanoseconds of error caused by the truncation which happened during
396 * the division when calculating rate or period (whichever one was
397 * derived from the other). We first calculate the relative error, then
398 * scale it to units of 8 ppm.
399 */
400 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
401 fladj -= 125000;
402
403 /*
404 * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
405 */
406 decr = 480000000 / rate;
407
408 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
409 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
410 & ~DWC3_GFLADJ_240MHZDECR
411 & ~DWC3_GFLADJ_240MHZDECR_PLS1;
412 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
413 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
414 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
a6fc2f1b
AS		 415
416 if (dwc->gfladj_refclk_lpm_sel)
417 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL;
418
596c8785
SA		 419 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
420}
7bee3188 421
72246da4
FB		 422/**
423 * dwc3_free_one_event_buffer - Frees one event buffer
424 * @dwc: Pointer to our controller context structure
425 * @evt: Pointer to event buffer to be freed
426 */
427static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
428 struct dwc3_event_buffer *evt)
429{
d64ff406 430 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
72246da4
FB		 431}
432
433/**
1d046793 434 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
72246da4
FB		 435 * @dwc: Pointer to our controller context structure
436 * @length: size of the event buffer
437 *
1d046793 438 * Returns a pointer to the allocated event buffer structure on success
72246da4
FB		 439 * otherwise ERR_PTR(errno).
440 */
67d0b500 441static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
ca80ca61 442 unsigned int length)
72246da4
FB		 443{
444 struct dwc3_event_buffer *evt;
445
380f0d28 446 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
72246da4
FB		 447 if (!evt)
448 return ERR_PTR(-ENOMEM);
449
450 evt->dwc = dwc;
451 evt->length = length;
d9fa4c63
JY		 452 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
453 if (!evt->cache)
454 return ERR_PTR(-ENOMEM);
455
d64ff406 456 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
72246da4 457 &evt->dma, GFP_KERNEL);
e32672f0 458 if (!evt->buf)
72246da4 459 return ERR_PTR(-ENOMEM);
72246da4
FB		 460
461 return evt;
462}
463
464/**
465 * dwc3_free_event_buffers - frees all allocated event buffers
466 * @dwc: Pointer to our controller context structure
467 */
468static void dwc3_free_event_buffers(struct dwc3 *dwc)
469{
470 struct dwc3_event_buffer *evt;
72246da4 471
696c8b12 472 evt = dwc->ev_buf;
660e9bde
FB		 473 if (evt)
474 dwc3_free_one_event_buffer(dwc, evt);
72246da4
FB		 475}
476
477/**
478 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
1d046793 479 * @dwc: pointer to our controller context structure
72246da4
FB		 480 * @length: size of event buffer
481 *
1d046793 482 * Returns 0 on success otherwise negative errno. In the error case, dwc
72246da4
FB		 483 * may contain some buffers allocated but not all which were requested.
484 */
ca80ca61 485static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
72246da4 486{
660e9bde 487 struct dwc3_event_buffer *evt;
72246da4 488
660e9bde
FB		 489 evt = dwc3_alloc_one_event_buffer(dwc, length);
490 if (IS_ERR(evt)) {
491 dev_err(dwc->dev, "can't allocate event buffer\n");
492 return PTR_ERR(evt);
72246da4 493 }
696c8b12 494 dwc->ev_buf = evt;
72246da4
FB		 495
496 return 0;
497}
498
499/**
500 * dwc3_event_buffers_setup - setup our allocated event buffers
1d046793 501 * @dwc: pointer to our controller context structure
72246da4
FB		 502 *
503 * Returns 0 on success otherwise negative errno.
504 */
f09cc79b 505int dwc3_event_buffers_setup(struct dwc3 *dwc)
72246da4
FB		 506{
507 struct dwc3_event_buffer *evt;
72246da4 508
696c8b12 509 evt = dwc->ev_buf;
660e9bde 510 evt->lpos = 0;
660e9bde
FB		 511 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
512 lower_32_bits(evt->dma));
513 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
514 upper_32_bits(evt->dma));
515 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
516 DWC3_GEVNTSIZ_SIZE(evt->length));
517 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 518
519 return 0;
520}
521
f09cc79b 522void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
72246da4
FB		 523{
524 struct dwc3_event_buffer *evt;
72246da4 525
696c8b12 526 evt = dwc->ev_buf;
7acd85e0 527
660e9bde 528 evt->lpos = 0;
7acd85e0 529
660e9bde
FB		 530 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
531 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
532 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
533 | DWC3_GEVNTSIZ_SIZE(0));
534 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
72246da4
FB		 535}
536
789451f6
FB		 537static void dwc3_core_num_eps(struct dwc3 *dwc)
538{
539 struct dwc3_hwparams *parms = &dwc->hwparams;
540
47d3946e 541 dwc->num_eps = DWC3_NUM_EPS(parms);
789451f6
FB		 542}
543
41ac7b3a 544static void dwc3_cache_hwparams(struct dwc3 *dwc)
26ceca97
FB		 545{
546 struct dwc3_hwparams *parms = &dwc->hwparams;
547
548 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
549 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
550 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
551 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
552 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
553 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
554 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
555 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
556 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
16710380
TN		 557
558 if (DWC3_IP_IS(DWC32))
559 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
26ceca97
FB		 560}
561
98112041
RQ		 562static int dwc3_core_ulpi_init(struct dwc3 *dwc)
563{
564 int intf;
565 int ret = 0;
566
567 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
568
569 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
570 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
571 dwc->hsphy_interface &&
572 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
573 ret = dwc3_ulpi_init(dwc);
574
575 return ret;
576}
577
b5a65c40
HR		 578/**
579 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
580 * @dwc: Pointer to our controller context structure
88bc9d19
HK		 581 *
582 * Returns 0 on success. The USB PHY interfaces are configured but not
583 * initialized. The PHY interfaces and the PHYs get initialized together with
584 * the core in dwc3_core_init.
b5a65c40 585 */
88bc9d19 586static int dwc3_phy_setup(struct dwc3 *dwc)
b5a65c40 587{
9ba3aca8 588 unsigned int hw_mode;
b5a65c40
HR		 589 u32 reg;
590
9ba3aca8
TN		 591 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
592
b5a65c40
HR		 593 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
594
1966b865
FB		 595 /*
596 * Make sure UX_EXIT_PX is cleared as that causes issues with some
597 * PHYs. Also, this bit is not supposed to be used in normal operation.
598 */
599 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
600
2164a476
HR		 601 /*
602 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
603 * to '0' during coreConsultant configuration. So default value
604 * will be '0' when the core is reset. Application needs to set it
605 * to '1' after the core initialization is completed.
606 */
9af21dd6 607 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
2164a476
HR		 608 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
609
9ba3aca8
TN		 610 /*
611 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
612 * power-on reset, and it can be set after core initialization, which is
613 * after device soft-reset during initialization.
614 */
615 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
616 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
617
b5a65c40
HR		 618 if (dwc->u2ss_inp3_quirk)
619 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
620
e58dd357
RB		 621 if (dwc->dis_rxdet_inp3_quirk)
622 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
623
df31f5b3
HR		 624 if (dwc->req_p1p2p3_quirk)
625 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
626
a2a1d0f5
HR		 627 if (dwc->del_p1p2p3_quirk)
628 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
629
41c06ffd
HR		 630 if (dwc->del_phy_power_chg_quirk)
631 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
632
fb67afca
HR		 633 if (dwc->lfps_filter_quirk)
634 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
635
14f4ac53
HR		 636 if (dwc->rx_detect_poll_quirk)
637 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
638
6b6a0c9a
HR		 639 if (dwc->tx_de_emphasis_quirk)
640 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
641
cd72f890 642 if (dwc->dis_u3_susphy_quirk)
59acfa20
HR		 643 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
644
00fe081d
WW		 645 if (dwc->dis_del_phy_power_chg_quirk)
646 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
647
b5a65c40
HR		 648 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
649
2164a476
HR		 650 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
651
3e10a2ce
HK		 652 /* Select the HS PHY interface */
653 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
654 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
43cacb03
FB		 655 if (dwc->hsphy_interface &&
656 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
3e10a2ce 657 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 658 break;
43cacb03
FB		 659 } else if (dwc->hsphy_interface &&
660 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
3e10a2ce 661 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
88bc9d19 662 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
3e10a2ce 663 } else {
88bc9d19
HK		 664 /* Relying on default value. */
665 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
666 break;
3e10a2ce 667 }
df561f66 668 fallthrough;
88bc9d19 669 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
3e10a2ce
HK		 670 default:
671 break;
672 }
673
32f2ed86
WW		 674 switch (dwc->hsphy_mode) {
675 case USBPHY_INTERFACE_MODE_UTMI:
676 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
677 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
678 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
679 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
680 break;
681 case USBPHY_INTERFACE_MODE_UTMIW:
682 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
683 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
684 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
685 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
686 break;
687 default:
688 break;
689 }
690
2164a476
HR		 691 /*
692 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
693 * '0' during coreConsultant configuration. So default value will
694 * be '0' when the core is reset. Application needs to set it to
695 * '1' after the core initialization is completed.
696 */
9af21dd6 697 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
2164a476
HR		 698 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
699
9ba3aca8
TN		 700 /*
701 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
702 * power-on reset, and it can be set after core initialization, which is
703 * after device soft-reset during initialization.
704 */
705 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
706 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
707
cd72f890 708 if (dwc->dis_u2_susphy_quirk)
0effe0a3
HR		 709 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
710
ec791d14
JY		 711 if (dwc->dis_enblslpm_quirk)
712 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
eafeacf1
TN		 713 else
714 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
ec791d14 715
a6fc2f1b 716 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
16199f33
WW		 717 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
718
b84ba26c
PM		 719 /*
720 * Some ULPI USB PHY does not support internal VBUS supply, to drive
721 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL
722 * bit of OTG_CTRL register. Controller configures the USB2 PHY
723 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus
724 * with an external supply.
725 */
726 if (dwc->ulpi_ext_vbus_drv)
727 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
728
2164a476 729 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
88bc9d19
HK		 730
731 return 0;
b5a65c40
HR		 732}
733
1d72fab4
JH		 734static int dwc3_phy_init(struct dwc3 *dwc)
735{
736 int ret;
737
738 usb_phy_init(dwc->usb2_phy);
739 usb_phy_init(dwc->usb3_phy);
740
741 ret = phy_init(dwc->usb2_generic_phy);
742 if (ret < 0)
743 goto err_shutdown_usb3_phy;
744
745 ret = phy_init(dwc->usb3_generic_phy);
746 if (ret < 0)
747 goto err_exit_usb2_phy;
748
749 return 0;
750
751err_exit_usb2_phy:
752 phy_exit(dwc->usb2_generic_phy);
753err_shutdown_usb3_phy:
754 usb_phy_shutdown(dwc->usb3_phy);
755 usb_phy_shutdown(dwc->usb2_phy);
756
757 return ret;
758}
759
760static void dwc3_phy_exit(struct dwc3 *dwc)
761{
762 phy_exit(dwc->usb3_generic_phy);
763 phy_exit(dwc->usb2_generic_phy);
764
765 usb_phy_shutdown(dwc->usb3_phy);
766 usb_phy_shutdown(dwc->usb2_phy);
767}
768
769static int dwc3_phy_power_on(struct dwc3 *dwc)
770{
771 int ret;
772
773 usb_phy_set_suspend(dwc->usb2_phy, 0);
774 usb_phy_set_suspend(dwc->usb3_phy, 0);
775
776 ret = phy_power_on(dwc->usb2_generic_phy);
777 if (ret < 0)
778 goto err_suspend_usb3_phy;
779
780 ret = phy_power_on(dwc->usb3_generic_phy);
781 if (ret < 0)
782 goto err_power_off_usb2_phy;
783
784 return 0;
785
786err_power_off_usb2_phy:
787 phy_power_off(dwc->usb2_generic_phy);
788err_suspend_usb3_phy:
789 usb_phy_set_suspend(dwc->usb3_phy, 1);
790 usb_phy_set_suspend(dwc->usb2_phy, 1);
791
792 return ret;
793}
794
795static void dwc3_phy_power_off(struct dwc3 *dwc)
796{
797 phy_power_off(dwc->usb3_generic_phy);
798 phy_power_off(dwc->usb2_generic_phy);
799
800 usb_phy_set_suspend(dwc->usb3_phy, 1);
801 usb_phy_set_suspend(dwc->usb2_phy, 1);
802}
803
33fb697e
SA		 804static int dwc3_clk_enable(struct dwc3 *dwc)
805{
806 int ret;
807
808 ret = clk_prepare_enable(dwc->bus_clk);
809 if (ret)
810 return ret;
811
812 ret = clk_prepare_enable(dwc->ref_clk);
813 if (ret)
814 goto disable_bus_clk;
815
816 ret = clk_prepare_enable(dwc->susp_clk);
817 if (ret)
818 goto disable_ref_clk;
819
820 return 0;
821
822disable_ref_clk:
823 clk_disable_unprepare(dwc->ref_clk);
824disable_bus_clk:
825 clk_disable_unprepare(dwc->bus_clk);
826 return ret;
827}
828
829static void dwc3_clk_disable(struct dwc3 *dwc)
830{
831 clk_disable_unprepare(dwc->susp_clk);
832 clk_disable_unprepare(dwc->ref_clk);
833 clk_disable_unprepare(dwc->bus_clk);
834}
835
c499ff71
FB		 836static void dwc3_core_exit(struct dwc3 *dwc)
837{
838 dwc3_event_buffers_cleanup(dwc);
1d72fab4
JH		 839 dwc3_phy_power_off(dwc);
840 dwc3_phy_exit(dwc);
33fb697e 841 dwc3_clk_disable(dwc);
fe8abf33 842 reset_control_assert(dwc->reset);
c499ff71
FB		 843}
844
0759956f 845static bool dwc3_core_is_valid(struct dwc3 *dwc)
72246da4 846{
0759956f 847 u32 reg;
72246da4 848
7650bd74 849 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
9af21dd6 850 dwc->ip = DWC3_GSNPS_ID(reg);
0759956f 851
7650bd74 852 /* This should read as U3 followed by revision number */
9af21dd6 853 if (DWC3_IP_IS(DWC3)) {
690fb371 854 dwc->revision = reg;
9af21dd6 855 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
690fb371 856 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
475d8e01 857 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
690fb371 858 } else {
0759956f 859 return false;
7650bd74 860 }
7650bd74 861
0759956f
FB		 862 return true;
863}
58a0f23f 864
941f918e 865static void dwc3_core_setup_global_control(struct dwc3 *dwc)
0759956f 866{
941f918e 867 u32 reg;
c499ff71 868
4878a028 869 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
3e87c42a 870 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
4878a028 871
164d7731 872 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
4878a028 873 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
32a4a135
FB		 874 /**
875 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
876 * issue which would cause xHCI compliance tests to fail.
877 *
878 * Because of that we cannot enable clock gating on such
879 * configurations.
880 *
881 * Refers to:
882 *
883 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
884 * SOF/ITP Mode Used
885 */
886 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
887 dwc->dr_mode == USB_DR_MODE_OTG) &&
9af21dd6 888 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
32a4a135
FB		 889 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
890 else
891 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
4878a028 892 break;
0ffcaf37 893 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
2eac3992
HR		 894 /*
895 * REVISIT Enabling this bit so that host-mode hibernation
896 * will work. Device-mode hibernation is not yet implemented.
897 */
898 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
0ffcaf37 899 break;
4878a028 900 default:
5eb30ced
FB		 901 /* nothing */
902 break;
4878a028
SAS		 903 }
904
946bd579
HR		 905 /* check if current dwc3 is on simulation board */
906 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
6af19fd1 907 dev_info(dwc->dev, "Running with FPGA optimizations\n");
946bd579
HR		 908 dwc->is_fpga = true;
909 }
910
3b81221a
HR		 911 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
912 "disable_scramble cannot be used on non-FPGA builds\n");
913
914 if (dwc->disable_scramble_quirk && dwc->is_fpga)
915 reg |= DWC3_GCTL_DISSCRAMBLE;
916 else
917 reg &= ~DWC3_GCTL_DISSCRAMBLE;
918
9a5b2f31
HR		 919 if (dwc->u2exit_lfps_quirk)
920 reg |= DWC3_GCTL_U2EXIT_LFPS;
921
4878a028
SAS		 922 /*
923 * WORKAROUND: DWC3 revisions <1.90a have a bug
1d046793 924 * where the device can fail to connect at SuperSpeed
4878a028 925 * and falls back to high-speed mode which causes
1d046793 926 * the device to enter a Connect/Disconnect loop
4878a028 927 */
9af21dd6 928 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
4878a028
SAS		 929 reg |= DWC3_GCTL_U2RSTECN;
930
931 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
941f918e
FB		 932}
933
f54edb53 934static int dwc3_core_get_phy(struct dwc3 *dwc);
98112041 935static int dwc3_core_ulpi_init(struct dwc3 *dwc);
f54edb53 936
d9612c2f
PM		 937/* set global incr burst type configuration registers */
938static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
939{
940 struct device *dev = dwc->dev;
941 /* incrx_mode : for INCR burst type. */
942 bool incrx_mode;
943 /* incrx_size : for size of INCRX burst. */
944 u32 incrx_size;
945 u32 *vals;
946 u32 cfg;
947 int ntype;
948 int ret;
949 int i;
950
951 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
952
953 /*
954 * Handle property "snps,incr-burst-type-adjustment".
955 * Get the number of value from this property:
956 * result <= 0, means this property is not supported.
957 * result = 1, means INCRx burst mode supported.
958 * result > 1, means undefined length burst mode supported.
959 */
a6e5e679 960 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
d9612c2f
PM		 961 if (ntype <= 0)
962 return;
963
964 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
4ea15088 965 if (!vals)
d9612c2f 966 return;
d9612c2f
PM		 967
968 /* Get INCR burst type, and parse it */
969 ret = device_property_read_u32_array(dev,
970 "snps,incr-burst-type-adjustment", vals, ntype);
971 if (ret) {
75ecb9dd 972 kfree(vals);
d9612c2f
PM		 973 dev_err(dev, "Error to get property\n");
974 return;
975 }
976
977 incrx_size = *vals;
978
979 if (ntype > 1) {
980 /* INCRX (undefined length) burst mode */
981 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
982 for (i = 1; i < ntype; i++) {
983 if (vals[i] > incrx_size)
984 incrx_size = vals[i];
985 }
986 } else {
987 /* INCRX burst mode */
988 incrx_mode = INCRX_BURST_MODE;
989 }
990
75ecb9dd
AS		 991 kfree(vals);
992
d9612c2f
PM		 993 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
994 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
995 if (incrx_mode)
996 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
997 switch (incrx_size) {
998 case 256:
999 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1000 break;
1001 case 128:
1002 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1003 break;
1004 case 64:
1005 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1006 break;
1007 case 32:
1008 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1009 break;
1010 case 16:
1011 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1012 break;
1013 case 8:
1014 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1015 break;
1016 case 4:
1017 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1018 break;
1019 case 1:
1020 break;
1021 default:
1022 dev_err(dev, "Invalid property\n");
1023 break;
1024 }
1025
1026 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1027}
1028
3497b9a5
LJ		 1029static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
1030{
1031 u32 scale;
1032 u32 reg;
1033
1034 if (!dwc->susp_clk)
1035 return;
1036
1037 /*
1038 * The power down scale field specifies how many suspend_clk
1039 * periods fit into a 16KHz clock period. When performing
1040 * the division, round up the remainder.
1041 *
1042 * The power down scale value is calculated using the fastest
1043 * frequency of the suspend_clk. If it isn't fixed (but within
1044 * the accuracy requirement), the driver may not know the max
1045 * rate of the suspend_clk, so only update the power down scale
1046 * if the default is less than the calculated value from
1047 * clk_get_rate() or if the default is questionably high
1048 * (3x or more) to be within the requirement.
1049 */
1050 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
1051 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1052 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
1053 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
1054 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
1055 reg |= DWC3_GCTL_PWRDNSCALE(scale);
1056 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1057 }
1058}
1059
941f918e
FB		 1060/**
1061 * dwc3_core_init - Low-level initialization of DWC3 Core
1062 * @dwc: Pointer to our controller context structure
1063 *
1064 * Returns 0 on success otherwise negative errno.
1065 */
1066static int dwc3_core_init(struct dwc3 *dwc)
1067{
9ba3aca8 1068 unsigned int hw_mode;
941f918e
FB		 1069 u32 reg;
1070 int ret;
1071
9ba3aca8
TN		 1072 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1073
941f918e
FB		 1074 /*
1075 * Write Linux Version Code to our GUID register so it's easy to figure
1076 * out which kernel version a bug was found.
1077 */
1078 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1079
98112041 1080 ret = dwc3_phy_setup(dwc);
941f918e 1081 if (ret)
d2f19782 1082 return ret;
4878a028 1083
98112041
RQ		 1084 if (!dwc->ulpi_ready) {
1085 ret = dwc3_core_ulpi_init(dwc);
63130462
FT		 1086 if (ret) {
1087 if (ret == -ETIMEDOUT) {
1088 dwc3_core_soft_reset(dwc);
1089 ret = -EPROBE_DEFER;
1090 }
d2f19782 1091 return ret;
63130462 1092 }
98112041
RQ		 1093 dwc->ulpi_ready = true;
1094 }
4878a028 1095
98112041
RQ		 1096 if (!dwc->phys_ready) {
1097 ret = dwc3_core_get_phy(dwc);
1098 if (ret)
d2f19782 1099 goto err_exit_ulpi;
98112041
RQ		 1100 dwc->phys_ready = true;
1101 }
1102
1d72fab4
JH		 1103 ret = dwc3_phy_init(dwc);
1104 if (ret)
1105 goto err_exit_ulpi;
8cfac9a6 1106
98112041 1107 ret = dwc3_core_soft_reset(dwc);
f54edb53 1108 if (ret)
1d72fab4 1109 goto err_exit_phy;
f54edb53 1110
9ba3aca8 1111 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
9af21dd6 1112 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
9ba3aca8
TN		 1113 if (!dwc->dis_u3_susphy_quirk) {
1114 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1115 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1116 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1117 }
1118
1119 if (!dwc->dis_u2_susphy_quirk) {
1120 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1121 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1122 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1123 }
1124 }
1125
941f918e 1126 dwc3_core_setup_global_control(dwc);
c499ff71 1127 dwc3_core_num_eps(dwc);
0ffcaf37 1128
3497b9a5
LJ		 1129 /* Set power down scale of suspend_clk */
1130 dwc3_set_power_down_clk_scale(dwc);
1131
c499ff71
FB		 1132 /* Adjust Frame Length */
1133 dwc3_frame_length_adjustment(dwc);
1134
7bee3188
BP		 1135 /* Adjust Reference Clock Period */
1136 dwc3_ref_clk_period(dwc);
1137
d9612c2f
PM		 1138 dwc3_set_incr_burst_type(dwc);
1139
1d72fab4
JH		 1140 dwc3_phy_power_on(dwc);
1141 if (ret)
1142 goto err_exit_phy;
c499ff71
FB		 1143
1144 ret = dwc3_event_buffers_setup(dwc);
1145 if (ret) {
1146 dev_err(dwc->dev, "failed to setup event buffers\n");
1d72fab4 1147 goto err_power_off_phy;
c499ff71
FB		 1148 }
1149
06281d46
JY		 1150 /*
1151 * ENDXFER polling is available on version 3.10a and later of
1152 * the DWC_usb3 controller. It is NOT available in the
1153 * DWC_usb31 controller.
1154 */
9af21dd6 1155 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
06281d46
JY		 1156 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1157 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1158 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1159 }
1160
63d7f981
PM		 1161 /*
1162 * When configured in HOST mode, after issuing U3/L2 exit controller
1163 * fails to send proper CRC checksum in CRC5 feild. Because of this
1164 * behaviour Transaction Error is generated, resulting in reset and
1165 * re-enumeration of usb device attached. All the termsel, xcvrsel,
1166 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1
1167 * will correct this problem. This option is to support certain
1168 * legacy ULPI PHYs.
1169 */
1170 if (dwc->resume_hs_terminations) {
1171 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1172 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
1173 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1174 }
1175
9af21dd6 1176 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
0bb39ca1 1177 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
65db7a0c
WW		 1178
1179 /*
1180 * Enable hardware control of sending remote wakeup
1181 * in HS when the device is in the L1 state.
1182 */
9af21dd6 1183 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
65db7a0c
WW		 1184 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1185
843714bb
JP		 1186 /*
1187 * Decouple USB 2.0 L1 & L2 events which will allow for
1188 * gadget driver to only receive U3/L2 suspend & wakeup
1189 * events and prevent the more frequent L1 LPM transitions
1190 * from interrupting the driver.
1191 */
1192 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1193 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1194
65db7a0c
WW		 1195 if (dwc->dis_tx_ipgap_linecheck_quirk)
1196 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1197
7ba6b09f
NA		 1198 if (dwc->parkmode_disable_ss_quirk)
1199 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1200
d21a797a
SC		 1201 if (dwc->parkmode_disable_hs_quirk)
1202 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS;
1203
62b20e6e
BY		 1204 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
1205 (dwc->maximum_speed == USB_SPEED_HIGH ||
1206 dwc->maximum_speed == USB_SPEED_FULL))
1207 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1208
0bb39ca1
JY		 1209 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1210 }
1211
b138e23d
AKV		 1212 if (dwc->dr_mode == USB_DR_MODE_HOST ||
1213 dwc->dr_mode == USB_DR_MODE_OTG) {
1214 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1215
1216 /*
1217 * Enable Auto retry Feature to make the controller operating in
1218 * Host mode on seeing transaction errors(CRC errors or internal
1219 * overrun scenerios) on IN transfers to reply to the device
1220 * with a non-terminating retry ACK (i.e, an ACK transcation
1221 * packet with Retry=1 & Nump != 0)
1222 */
1223 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1224
1225 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1226 }
1227
938a5ad1
TN		 1228 /*
1229 * Must config both number of packets and max burst settings to enable
1230 * RX and/or TX threshold.
1231 */
9af21dd6 1232 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
938a5ad1
TN		 1233 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1234 u8 rx_maxburst = dwc->rx_max_burst_prd;
1235 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1236 u8 tx_maxburst = dwc->tx_max_burst_prd;
1237
1238 if (rx_thr_num && rx_maxburst) {
1239 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1240 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1241
1242 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1243 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1244
1245 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1246 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1247
1248 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1249 }
1250
1251 if (tx_thr_num && tx_maxburst) {
1252 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1253 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1254
1255 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1256 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1257
1258 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1259 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1260
1261 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1262 }
1263 }
1264
72246da4
FB		 1265 return 0;
1266
1d72fab4
JH		 1267err_power_off_phy:
1268 dwc3_phy_power_off(dwc);
1269err_exit_phy:
1270 dwc3_phy_exit(dwc);
d2f19782 1271err_exit_ulpi:
98112041
RQ		 1272 dwc3_ulpi_exit(dwc);
1273
72246da4
FB		 1274 return ret;
1275}
1276
3c9f94ac 1277static int dwc3_core_get_phy(struct dwc3 *dwc)
72246da4 1278{
3c9f94ac 1279 struct device *dev = dwc->dev;
941ea361 1280 struct device_node *node = dev->of_node;
3c9f94ac 1281 int ret;
72246da4 1282
5088b6f5
KVA		 1283 if (node) {
1284 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1285 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
bb674907
FB		 1286 } else {
1287 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1288 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
5088b6f5
KVA		 1289 }
1290
d105e7f8
FB		 1291 if (IS_ERR(dwc->usb2_phy)) {
1292 ret = PTR_ERR(dwc->usb2_phy);
d090c7a2 1293 if (ret == -ENXIO || ret == -ENODEV)
122f06e6 1294 dwc->usb2_phy = NULL;
d090c7a2 1295 else
0c0a20f6 1296 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
51e1e7bc
FB		 1297 }
1298
d105e7f8 1299 if (IS_ERR(dwc->usb3_phy)) {
315955d7 1300 ret = PTR_ERR(dwc->usb3_phy);
d090c7a2 1301 if (ret == -ENXIO || ret == -ENODEV)
122f06e6 1302 dwc->usb3_phy = NULL;
d090c7a2 1303 else
0c0a20f6 1304 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
51e1e7bc
FB		 1305 }
1306
57303488
KVA		 1307 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1308 if (IS_ERR(dwc->usb2_generic_phy)) {
1309 ret = PTR_ERR(dwc->usb2_generic_phy);
fb119dcb 1310 if (ret == -ENOSYS || ret == -ENODEV)
57303488 1311 dwc->usb2_generic_phy = NULL;
d090c7a2 1312 else
0c0a20f6 1313 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
57303488
KVA		 1314 }
1315
1316 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1317 if (IS_ERR(dwc->usb3_generic_phy)) {
1318 ret = PTR_ERR(dwc->usb3_generic_phy);
fb119dcb 1319 if (ret == -ENOSYS || ret == -ENODEV)
57303488 1320 dwc->usb3_generic_phy = NULL;
d090c7a2 1321 else
0c0a20f6 1322 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
57303488
KVA		 1323 }
1324
3c9f94ac
FB		 1325 return 0;
1326}
1327
5f94adfe
FB		 1328static int dwc3_core_init_mode(struct dwc3 *dwc)
1329{
1330 struct device *dev = dwc->dev;
1331 int ret;
1332
1333 switch (dwc->dr_mode) {
1334 case USB_DR_MODE_PERIPHERAL:
41ce1456 1335 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
958d1a4c
FB		 1336
1337 if (dwc->usb2_phy)
1338 otg_set_vbus(dwc->usb2_phy->otg, false);
644cbbc3
MG		 1339 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1340 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
958d1a4c 1341
5f94adfe 1342 ret = dwc3_gadget_init(dwc);
0c0a20f6
AS		 1343 if (ret)
1344 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
5f94adfe
FB		 1345 break;
1346 case USB_DR_MODE_HOST:
41ce1456 1347 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
958d1a4c
FB		 1348
1349 if (dwc->usb2_phy)
1350 otg_set_vbus(dwc->usb2_phy->otg, true);
644cbbc3
MG		 1351 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1352 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
958d1a4c 1353
5f94adfe 1354 ret = dwc3_host_init(dwc);
0c0a20f6
AS		 1355 if (ret)
1356 return dev_err_probe(dev, ret, "failed to initialize host\n");
5f94adfe
FB		 1357 break;
1358 case USB_DR_MODE_OTG:
41ce1456 1359 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
9840354f 1360 ret = dwc3_drd_init(dwc);
0c0a20f6
AS		 1361 if (ret)
1362 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
5f94adfe
FB		 1363 break;
1364 default:
1365 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1366 return -EINVAL;
1367 }
1368
1369 return 0;
1370}
1371
1372static void dwc3_core_exit_mode(struct dwc3 *dwc)
1373{
1374 switch (dwc->dr_mode) {
1375 case USB_DR_MODE_PERIPHERAL:
1376 dwc3_gadget_exit(dwc);
1377 break;
1378 case USB_DR_MODE_HOST:
1379 dwc3_host_exit(dwc);
1380 break;
1381 case USB_DR_MODE_OTG:
9840354f 1382 dwc3_drd_exit(dwc);
5f94adfe
FB		 1383 break;
1384 default:
1385 /* do nothing */
1386 break;
1387 }
09ed259f
BL		 1388
1389 /* de-assert DRVVBUS for HOST and OTG mode */
1390 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
5f94adfe
FB		 1391}
1392
c5ac6116 1393static void dwc3_get_properties(struct dwc3 *dwc)
3c9f94ac 1394{
c5ac6116 1395 struct device *dev = dwc->dev;
80caf7d2 1396 u8 lpm_nyet_threshold;
6b6a0c9a 1397 u8 tx_de_emphasis;
460d098c 1398 u8 hird_threshold;
f28ad906
TN		 1399 u8 rx_thr_num_pkt_prd = 0;
1400 u8 rx_max_burst_prd = 0;
1401 u8 tx_thr_num_pkt_prd = 0;
1402 u8 tx_max_burst_prd = 0;
9f607a30 1403 u8 tx_fifo_resize_max_num;
6f0764b5
RC		 1404 const char *usb_psy_name;
1405 int ret;
3c9f94ac 1406
80caf7d2 1407 /* default to highest possible threshold */
8d791929 1408 lpm_nyet_threshold = 0xf;
80caf7d2 1409
6b6a0c9a
HR		 1410 /* default to -3.5dB de-emphasis */
1411 tx_de_emphasis = 1;
1412
460d098c
HR		 1413 /*
1414 * default to assert utmi_sleep_n and use maximum allowed HIRD
1415 * threshold value of 0b1100
1416 */
1417 hird_threshold = 12;
1418
9f607a30
WC		 1419 /*
1420 * default to a TXFIFO size large enough to fit 6 max packets. This
1421 * allows for systems with larger bus latencies to have some headroom
1422 * for endpoints that have a large bMaxBurst value.
1423 */
1424 tx_fifo_resize_max_num = 6;
1425
63863b98 1426 dwc->maximum_speed = usb_get_maximum_speed(dev);
67848146 1427 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
06e7114f 1428 dwc->dr_mode = usb_get_dr_mode(dev);
32f2ed86 1429 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
63863b98 1430
d64ff406
AB		 1431 dwc->sysdev_is_parent = device_property_read_bool(dev,
1432 "linux,sysdev_is_parent");
1433 if (dwc->sysdev_is_parent)
1434 dwc->sysdev = dwc->dev->parent;
1435 else
1436 dwc->sysdev = dwc->dev;
1437
6f0764b5
RC		 1438 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1439 if (ret >= 0) {
1440 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1441 if (!dwc->usb_psy)
1442 dev_err(dev, "couldn't get usb power supply\n");
1443 }
1444
3d128919 1445 dwc->has_lpm_erratum = device_property_read_bool(dev,
80caf7d2 1446 "snps,has-lpm-erratum");
3d128919 1447 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
80caf7d2 1448 &lpm_nyet_threshold);
3d128919 1449 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
460d098c 1450 "snps,is-utmi-l1-suspend");
3d128919 1451 device_property_read_u8(dev, "snps,hird-threshold",
460d098c 1452 &hird_threshold);
d92021f6
TN		 1453 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1454 "snps,dis-start-transfer-quirk");
3d128919 1455 dwc->usb3_lpm_capable = device_property_read_bool(dev,
eac68e8f 1456 "snps,usb3_lpm_capable");
022a0208
TN		 1457 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1458 "snps,usb2-lpm-disable");
475e8be5
TN		 1459 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1460 "snps,usb2-gadget-lpm-disable");
938a5ad1
TN		 1461 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1462 &rx_thr_num_pkt_prd);
1463 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1464 &rx_max_burst_prd);
1465 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1466 &tx_thr_num_pkt_prd);
1467 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1468 &tx_max_burst_prd);
9f607a30
WC		 1469 dwc->do_fifo_resize = device_property_read_bool(dev,
1470 "tx-fifo-resize");
1471 if (dwc->do_fifo_resize)
1472 device_property_read_u8(dev, "tx-fifo-max-num",
1473 &tx_fifo_resize_max_num);
3c9f94ac 1474
3d128919 1475 dwc->disable_scramble_quirk = device_property_read_bool(dev,
3b81221a 1476 "snps,disable_scramble_quirk");
3d128919 1477 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
9a5b2f31 1478 "snps,u2exit_lfps_quirk");
3d128919 1479 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
b5a65c40 1480 "snps,u2ss_inp3_quirk");
3d128919 1481 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
df31f5b3 1482 "snps,req_p1p2p3_quirk");
3d128919 1483 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
a2a1d0f5 1484 "snps,del_p1p2p3_quirk");
3d128919 1485 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
41c06ffd 1486 "snps,del_phy_power_chg_quirk");
3d128919 1487 dwc->lfps_filter_quirk = device_property_read_bool(dev,
fb67afca 1488 "snps,lfps_filter_quirk");
3d128919 1489 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
14f4ac53 1490 "snps,rx_detect_poll_quirk");
3d128919 1491 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
59acfa20 1492 "snps,dis_u3_susphy_quirk");
3d128919 1493 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
0effe0a3 1494 "snps,dis_u2_susphy_quirk");
ec791d14
JY		 1495 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1496 "snps,dis_enblslpm_quirk");
729dcffd
AKV		 1497 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1498 "snps,dis-u1-entry-quirk");
1499 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1500 "snps,dis-u2-entry-quirk");
e58dd357
RB		 1501 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1502 "snps,dis_rxdet_inp3_quirk");
16199f33
WW		 1503 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1504 "snps,dis-u2-freeclk-exists-quirk");
00fe081d
WW		 1505 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1506 "snps,dis-del-phy-power-chg-quirk");
65db7a0c
WW		 1507 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1508 "snps,dis-tx-ipgap-linecheck-quirk");
63d7f981
PM		 1509 dwc->resume_hs_terminations = device_property_read_bool(dev,
1510 "snps,resume-hs-terminations");
b84ba26c
PM		 1511 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
1512 "snps,ulpi-ext-vbus-drv");
7ba6b09f
NA		 1513 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1514 "snps,parkmode-disable-ss-quirk");
d21a797a
SC		 1515 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev,
1516 "snps,parkmode-disable-hs-quirk");
a6fc2f1b
AS		 1517 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
1518 "snps,gfladj-refclk-lpm-sel-quirk");
6b6a0c9a 1519
3d128919 1520 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
6b6a0c9a 1521 "snps,tx_de_emphasis_quirk");
3d128919 1522 device_property_read_u8(dev, "snps,tx_de_emphasis",
6b6a0c9a 1523 &tx_de_emphasis);
3d128919
HK		 1524 device_property_read_string(dev, "snps,hsphy_interface",
1525 &dwc->hsphy_interface);
1526 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
bcdb3272 1527 &dwc->fladj);
7bee3188
BP		 1528 device_property_read_u32(dev, "snps,ref-clock-period-ns",
1529 &dwc->ref_clk_per);
3d128919 1530
42bf02ec
RQ		 1531 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1532 "snps,dis_metastability_quirk");
1533
f580170f
YC		 1534 dwc->dis_split_quirk = device_property_read_bool(dev,
1535 "snps,dis-split-quirk");
1536
80caf7d2 1537 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
6b6a0c9a 1538 dwc->tx_de_emphasis = tx_de_emphasis;
80caf7d2 1539
16fe4f30 1540 dwc->hird_threshold = hird_threshold;
460d098c 1541
938a5ad1
TN		 1542 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1543 dwc->rx_max_burst_prd = rx_max_burst_prd;
1544
1545 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1546 dwc->tx_max_burst_prd = tx_max_burst_prd;
1547
cf40b86b 1548 dwc->imod_interval = 0;
9f607a30
WC		 1549
1550 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
cf40b86b
JY		 1551}
1552
1553/* check whether the core supports IMOD */
1554bool dwc3_has_imod(struct dwc3 *dwc)
1555{
9af21dd6
TN		 1556 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1557 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1558 DWC3_IP_IS(DWC32);
c5ac6116
FB		 1559}
1560
7ac51a12
JY		 1561static void dwc3_check_params(struct dwc3 *dwc)
1562{
1563 struct device *dev = dwc->dev;
b574ce3e
TN		 1564 unsigned int hwparam_gen =
1565 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
7ac51a12 1566
cf40b86b
JY		 1567 /* Check for proper value of imod_interval */
1568 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1569 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1570 dwc->imod_interval = 0;
1571 }
1572
28632b44
JY		 1573 /*
1574 * Workaround for STAR 9000961433 which affects only version
1575 * 3.00a of the DWC_usb3 core. This prevents the controller
1576 * interrupt from being masked while handling events. IMOD
1577 * allows us to work around this issue. Enable it for the
1578 * affected version.
1579 */
1580 if (!dwc->imod_interval &&
9af21dd6 1581 DWC3_VER_IS(DWC3, 300A))
28632b44
JY		 1582 dwc->imod_interval = 1;
1583
7ac51a12
JY		 1584 /* Check the maximum_speed parameter */
1585 switch (dwc->maximum_speed) {
7ac51a12
JY		 1586 case USB_SPEED_FULL:
1587 case USB_SPEED_HIGH:
e518bdd9 1588 break;
7ac51a12 1589 case USB_SPEED_SUPER:
e518bdd9
TN		 1590 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1591 dev_warn(dev, "UDC doesn't support Gen 1\n");
1592 break;
7ac51a12 1593 case USB_SPEED_SUPER_PLUS:
e518bdd9
TN		 1594 if ((DWC3_IP_IS(DWC32) &&
1595 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1596 (!DWC3_IP_IS(DWC32) &&
1597 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1598 dev_warn(dev, "UDC doesn't support SSP\n");
7ac51a12
JY		 1599 break;
1600 default:
1601 dev_err(dev, "invalid maximum_speed parameter %d\n",
1602 dwc->maximum_speed);
df561f66 1603 fallthrough;
7ac51a12 1604 case USB_SPEED_UNKNOWN:
b574ce3e
TN		 1605 switch (hwparam_gen) {
1606 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
7ac51a12 1607 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
b574ce3e
TN		 1608 break;
1609 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1610 if (DWC3_IP_IS(DWC32))
1611 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1612 else
1613 dwc->maximum_speed = USB_SPEED_SUPER;
1614 break;
1615 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1616 dwc->maximum_speed = USB_SPEED_HIGH;
1617 break;
1618 default:
1619 dwc->maximum_speed = USB_SPEED_SUPER;
1620 break;
1621 }
7ac51a12
JY		 1622 break;
1623 }
67848146
TN		 1624
1625 /*
1626 * Currently the controller does not have visibility into the HW
1627 * parameter to determine the maximum number of lanes the HW supports.
1628 * If the number of lanes is not specified in the device property, then
1629 * set the default to support dual-lane for DWC_usb32 and single-lane
1630 * for DWC_usb31 for super-speed-plus.
1631 */
1632 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1633 switch (dwc->max_ssp_rate) {
1634 case USB_SSP_GEN_2x1:
1635 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1636 dev_warn(dev, "UDC only supports Gen 1\n");
1637 break;
1638 case USB_SSP_GEN_1x2:
1639 case USB_SSP_GEN_2x2:
1640 if (DWC3_IP_IS(DWC31))
1641 dev_warn(dev, "UDC only supports single lane\n");
1642 break;
1643 case USB_SSP_GEN_UNKNOWN:
1644 default:
1645 switch (hwparam_gen) {
1646 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1647 if (DWC3_IP_IS(DWC32))
1648 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1649 else
1650 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1651 break;
1652 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1653 if (DWC3_IP_IS(DWC32))
1654 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1655 break;
1656 }
1657 break;
1658 }
1659 }
7ac51a12
JY		 1660}
1661
d182c2e1
AS		 1662static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1663{
1664 struct device *dev = dwc->dev;
1665 struct device_node *np_phy;
1666 struct extcon_dev *edev = NULL;
1667 const char *name;
1668
1669 if (device_property_read_bool(dev, "extcon"))
1670 return extcon_get_edev_by_phandle(dev, 0);
1671
1672 /*
1673 * Device tree platforms should get extcon via phandle.
1674 * On ACPI platforms, we get the name from a device property.
1675 * This device property is for kernel internal use only and
1676 * is expected to be set by the glue code.
1677 */
1678 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
1679 return extcon_get_extcon_dev(name);
1680
d68cc25b
JG		 1681 /*
1682 * Check explicitly if "usb-role-switch" is used since
1683 * extcon_find_edev_by_node() can not be used to check the absence of
1684 * an extcon device. In the absence of an device it will always return
1685 * EPROBE_DEFER.
1686 */
1687 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) &&
1688 device_property_read_bool(dev, "usb-role-switch"))
1689 return NULL;
1690
d182c2e1
AS		 1691 /*
1692 * Try to get an extcon device from the USB PHY controller's "port"
1693 * node. Check if it has the "port" node first, to avoid printing the
1694 * error message from underlying code, as it's a valid case: extcon
1695 * device (and "port" node) may be missing in case of "usb-role-switch"
1696 * or OTG mode.
1697 */
1698 np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1699 if (of_graph_is_present(np_phy)) {
1700 struct device_node *np_conn;
1701
1702 np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1703 if (np_conn)
1704 edev = extcon_find_edev_by_node(np_conn);
1705 of_node_put(np_conn);
1706 }
1707 of_node_put(np_phy);
1708
1709 return edev;
1710}
1711
bd828574
JH		 1712static int dwc3_get_clocks(struct dwc3 *dwc)
1713{
1714 struct device *dev = dwc->dev;
1715
1716 if (!dev->of_node)
1717 return 0;
1718
1719 /*
1720 * Clocks are optional, but new DT platforms should support all clocks
1721 * as required by the DT-binding.
1722 * Some devices have different clock names in legacy device trees,
1723 * check for them to retain backwards compatibility.
1724 */
1725 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1726 if (IS_ERR(dwc->bus_clk)) {
1727 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1728 "could not get bus clock\n");
1729 }
1730
1731 if (dwc->bus_clk == NULL) {
1732 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1733 if (IS_ERR(dwc->bus_clk)) {
1734 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1735 "could not get bus clock\n");
1736 }
1737 }
1738
1739 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1740 if (IS_ERR(dwc->ref_clk)) {
1741 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1742 "could not get ref clock\n");
1743 }
1744
1745 if (dwc->ref_clk == NULL) {
1746 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1747 if (IS_ERR(dwc->ref_clk)) {
1748 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1749 "could not get ref clock\n");
1750 }
1751 }
1752
1753 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1754 if (IS_ERR(dwc->susp_clk)) {
1755 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1756 "could not get suspend clock\n");
1757 }
1758
1759 if (dwc->susp_clk == NULL) {
1760 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1761 if (IS_ERR(dwc->susp_clk)) {
1762 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1763 "could not get suspend clock\n");
1764 }
1765 }
1766
1767 return 0;
1768}
1769
c5ac6116
FB		 1770static int dwc3_probe(struct platform_device *pdev)
1771{
1772 struct device *dev = &pdev->dev;
44feb8e6 1773 struct resource *res, dwc_res;
9a4d7dd1 1774 void __iomem *regs;
c5ac6116 1775 struct dwc3 *dwc;
c5ac6116
FB		 1776 int ret;
1777
c5ac6116
FB		 1778 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1779 if (!dwc)
1780 return -ENOMEM;
1781
1782 dwc->dev = dev;
1783
1784 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1785 if (!res) {
1786 dev_err(dev, "missing memory resource\n");
1787 return -ENODEV;
1788 }
1789
1790 dwc->xhci_resources[0].start = res->start;
1791 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1792 DWC3_XHCI_REGS_END;
1793 dwc->xhci_resources[0].flags = res->flags;
1794 dwc->xhci_resources[0].name = res->name;
1795
c5ac6116
FB		 1796 /*
1797 * Request memory region but exclude xHCI regs,
1798 * since it will be requested by the xhci-plat driver.
1799 */
44feb8e6
MY		 1800 dwc_res = *res;
1801 dwc_res.start += DWC3_GLOBALS_REGS_START;
1802
1803 regs = devm_ioremap_resource(dev, &dwc_res);
1804 if (IS_ERR(regs))
1805 return PTR_ERR(regs);
c5ac6116
FB		 1806
1807 dwc->regs = regs;
44feb8e6 1808 dwc->regs_size = resource_size(&dwc_res);
c5ac6116
FB		 1809
1810 dwc3_get_properties(dwc);
1811
babbdfc9 1812 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
2a735e4b
DC		 1813 if (IS_ERR(dwc->reset)) {
1814 ret = PTR_ERR(dwc->reset);
fe296046 1815 goto err_put_psy;
2a735e4b 1816 }
fe8abf33 1817
bd828574
JH		 1818 ret = dwc3_get_clocks(dwc);
1819 if (ret)
1820 goto err_put_psy;
fe8abf33
MY		 1821
1822 ret = reset_control_deassert(dwc->reset);
1823 if (ret)
fe296046 1824 goto err_put_psy;
fe8abf33 1825
33fb697e 1826 ret = dwc3_clk_enable(dwc);
fe8abf33 1827 if (ret)
fe296046 1828 goto err_assert_reset;
fe8abf33 1829
dc1b5d9a
EBS		 1830 if (!dwc3_core_is_valid(dwc)) {
1831 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1832 ret = -ENODEV;
fe296046 1833 goto err_disable_clks;
dc1b5d9a
EBS		 1834 }
1835
6c89cce0 1836 platform_set_drvdata(pdev, dwc);
2917e718 1837 dwc3_cache_hwparams(dwc);
6c89cce0 1838
91062e66
WW		 1839 if (!dwc->sysdev_is_parent &&
1840 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
1841 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1842 if (ret)
fe296046 1843 goto err_disable_clks;
91062e66
WW		 1844 }
1845
72246da4 1846 spin_lock_init(&dwc->lock);
f88359e1 1847 mutex_init(&dwc->mutex);
72246da4 1848
9a8ad10c 1849 pm_runtime_get_noresume(dev);
fc8bb91b
FB		 1850 pm_runtime_set_active(dev);
1851 pm_runtime_use_autosuspend(dev);
1852 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
802ca850 1853 pm_runtime_enable(dev);
32808237 1854
802ca850 1855 pm_runtime_forbid(dev);
72246da4 1856
3921426b
FB		 1857 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1858 if (ret) {
1859 dev_err(dwc->dev, "failed to allocate event buffers\n");
1860 ret = -ENOMEM;
fe296046 1861 goto err_allow_rpm;
3921426b
FB		 1862 }
1863
d182c2e1
AS		 1864 dwc->edev = dwc3_get_extcon(dwc);
1865 if (IS_ERR(dwc->edev)) {
1866 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n");
fe296046 1867 goto err_free_event_buffers;
d182c2e1
AS		 1868 }
1869
9d6173e1
TN		 1870 ret = dwc3_get_dr_mode(dwc);
1871 if (ret)
fe296046 1872 goto err_free_event_buffers;
32a4a135 1873
72246da4
FB		 1874 ret = dwc3_core_init(dwc);
1875 if (ret) {
0c0a20f6 1876 dev_err_probe(dev, ret, "failed to initialize core\n");
fe296046 1877 goto err_free_event_buffers;
72246da4
FB		 1878 }
1879
7ac51a12 1880 dwc3_check_params(dwc);
84524d12 1881 dwc3_debugfs_init(dwc);
2c7f1bd9 1882
5f94adfe
FB		 1883 ret = dwc3_core_init_mode(dwc);
1884 if (ret)
fe296046 1885 goto err_exit_debugfs;
72246da4 1886
fc8bb91b 1887 pm_runtime_put(dev);
72246da4
FB		 1888
1889 return 0;
1890
fe296046 1891err_exit_debugfs:
84524d12 1892 dwc3_debugfs_exit(dwc);
c499ff71 1893 dwc3_event_buffers_cleanup(dwc);
1d72fab4
JH		 1894 dwc3_phy_power_off(dwc);
1895 dwc3_phy_exit(dwc);
08fd9a82 1896 dwc3_ulpi_exit(dwc);
fe296046 1897err_free_event_buffers:
3921426b 1898 dwc3_free_event_buffers(dwc);
fe296046 1899err_allow_rpm:
9a8ad10c
JH		 1900 pm_runtime_allow(dev);
1901 pm_runtime_disable(dev);
6b3b2402 1902 pm_runtime_dont_use_autosuspend(dev);
9a8ad10c
JH		 1903 pm_runtime_set_suspended(dev);
1904 pm_runtime_put_noidle(dev);
fe296046 1905err_disable_clks:
33fb697e 1906 dwc3_clk_disable(dwc);
fe296046 1907err_assert_reset:
fe8abf33 1908 reset_control_assert(dwc->reset);
fe296046 1909err_put_psy:
b0bf77cd 1910 if (dwc->usb_psy)
6f0764b5
RC		 1911 power_supply_put(dwc->usb_psy);
1912
72246da4
FB		 1913 return ret;
1914}
1915
fb4e98ab 1916static int dwc3_remove(struct platform_device *pdev)
72246da4 1917{
72246da4 1918 struct dwc3 *dwc = platform_get_drvdata(pdev);
3da1f6ee 1919
fc8bb91b 1920 pm_runtime_get_sync(&pdev->dev);
72246da4 1921
dc99f16f 1922 dwc3_core_exit_mode(dwc);
2a042767 1923 dwc3_debugfs_exit(dwc);
8ba007a9 1924
72246da4 1925 dwc3_core_exit(dwc);
88bc9d19 1926 dwc3_ulpi_exit(dwc);
72246da4 1927
44d257e9 1928 pm_runtime_allow(&pdev->dev);
72246da4 1929 pm_runtime_disable(&pdev->dev);
6b3b2402 1930 pm_runtime_dont_use_autosuspend(&pdev->dev);
266d0493
LJ		 1931 pm_runtime_put_noidle(&pdev->dev);
1932 pm_runtime_set_suspended(&pdev->dev);
72246da4 1933
fc8bb91b 1934 dwc3_free_event_buffers(dwc);
fc8bb91b 1935
b0bf77cd 1936 if (dwc->usb_psy)
6f0764b5
RC		 1937 power_supply_put(dwc->usb_psy);
1938
72246da4
FB		 1939 return 0;
1940}
1941
fc8bb91b 1942#ifdef CONFIG_PM
fe8abf33
MY		 1943static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1944{
1945 int ret;
1946
1947 ret = reset_control_deassert(dwc->reset);
1948 if (ret)
1949 return ret;
1950
33fb697e 1951 ret = dwc3_clk_enable(dwc);
fe8abf33
MY		 1952 if (ret)
1953 goto assert_reset;
1954
fe8abf33
MY		 1955 ret = dwc3_core_init(dwc);
1956 if (ret)
1957 goto disable_clks;
1958
1959 return 0;
1960
1961disable_clks:
33fb697e 1962 dwc3_clk_disable(dwc);
fe8abf33
MY		 1963assert_reset:
1964 reset_control_assert(dwc->reset);
1965
1966 return ret;
1967}
1968
c4a5153e 1969static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
7415f17c 1970{
fc8bb91b 1971 unsigned long flags;
bcb12877 1972 u32 reg;
7415f17c 1973
689bf72c
MG		 1974 switch (dwc->current_dr_role) {
1975 case DWC3_GCTL_PRTCAP_DEVICE:
0227cc84
LJ		 1976 if (pm_runtime_suspended(dwc->dev))
1977 break;
7415f17c 1978 dwc3_gadget_suspend(dwc);
41a91c60 1979 synchronize_irq(dwc->irq_gadget);
689bf72c 1980 dwc3_core_exit(dwc);
51f5d49a 1981 break;
689bf72c 1982 case DWC3_GCTL_PRTCAP_HOST:
e3fafbd8 1983 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
c4a5153e 1984 dwc3_core_exit(dwc);
bcb12877
MG		 1985 break;
1986 }
1987
1988 /* Let controller to suspend HSPHY before PHY driver suspends */
1989 if (dwc->dis_u2_susphy_quirk ||
1990 dwc->dis_enblslpm_quirk) {
1991 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1992 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1993 DWC3_GUSB2PHYCFG_SUSPHY;
1994 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1995
1996 /* Give some time for USB2 PHY to suspend */
1997 usleep_range(5000, 6000);
1998 }
1999
2000 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
2001 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
c4a5153e 2002 break;
f09cc79b
RQ		 2003 case DWC3_GCTL_PRTCAP_OTG:
2004 /* do nothing during runtime_suspend */
2005 if (PMSG_IS_AUTO(msg))
2006 break;
2007
2008 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2009 spin_lock_irqsave(&dwc->lock, flags);
2010 dwc3_gadget_suspend(dwc);
2011 spin_unlock_irqrestore(&dwc->lock, flags);
41a91c60 2012 synchronize_irq(dwc->irq_gadget);
f09cc79b
RQ		 2013 }
2014
2015 dwc3_otg_exit(dwc);
2016 dwc3_core_exit(dwc);
2017 break;
7415f17c 2018 default:
51f5d49a 2019 /* do nothing */
7415f17c
FB		 2020 break;
2021 }
2022
7415f17c
FB		 2023 return 0;
2024}
2025
c4a5153e 2026static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
7415f17c 2027{
fc8bb91b 2028 unsigned long flags;
57303488 2029 int ret;
bcb12877 2030 u32 reg;
7415f17c 2031
689bf72c
MG		 2032 switch (dwc->current_dr_role) {
2033 case DWC3_GCTL_PRTCAP_DEVICE:
fe8abf33 2034 ret = dwc3_core_init_for_resume(dwc);
689bf72c
MG		 2035 if (ret)
2036 return ret;
5c4ad318 2037
7d11c3ac 2038 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
7415f17c 2039 dwc3_gadget_resume(dwc);
689bf72c
MG		 2040 break;
2041 case DWC3_GCTL_PRTCAP_HOST:
e3fafbd8 2042 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
fe8abf33 2043 ret = dwc3_core_init_for_resume(dwc);
c4a5153e
MG		 2044 if (ret)
2045 return ret;
7d11c3ac 2046 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
bcb12877 2047 break;
c4a5153e 2048 }
bcb12877
MG		 2049 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2050 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2051 if (dwc->dis_u2_susphy_quirk)
2052 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2053
2054 if (dwc->dis_enblslpm_quirk)
2055 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2056
2057 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2058
2059 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
2060 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
f09cc79b
RQ		 2061 break;
2062 case DWC3_GCTL_PRTCAP_OTG:
2063 /* nothing to do on runtime_resume */
2064 if (PMSG_IS_AUTO(msg))
2065 break;
2066
0e5a3c82 2067 ret = dwc3_core_init_for_resume(dwc);
f09cc79b
RQ		 2068 if (ret)
2069 return ret;
2070
2071 dwc3_set_prtcap(dwc, dwc->current_dr_role);
2072
2073 dwc3_otg_init(dwc);
2074 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2075 dwc3_otg_host_init(dwc);
2076 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2077 spin_lock_irqsave(&dwc->lock, flags);
2078 dwc3_gadget_resume(dwc);
2079 spin_unlock_irqrestore(&dwc->lock, flags);
c4a5153e 2080 }
f09cc79b 2081
c4a5153e 2082 break;
7415f17c
FB		 2083 default:
2084 /* do nothing */
2085 break;
2086 }
2087
fc8bb91b
FB		 2088 return 0;
2089}
2090
2091static int dwc3_runtime_checks(struct dwc3 *dwc)
2092{
689bf72c 2093 switch (dwc->current_dr_role) {
c4a5153e 2094 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 2095 if (dwc->connected)
2096 return -EBUSY;
2097 break;
c4a5153e 2098 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 2099 default:
2100 /* do nothing */
2101 break;
2102 }
2103
2104 return 0;
2105}
2106
2107static int dwc3_runtime_suspend(struct device *dev)
2108{
2109 struct dwc3 *dwc = dev_get_drvdata(dev);
2110 int ret;
2111
2112 if (dwc3_runtime_checks(dwc))
2113 return -EBUSY;
2114
c4a5153e 2115 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
fc8bb91b
FB		 2116 if (ret)
2117 return ret;
2118
fc8bb91b
FB		 2119 return 0;
2120}
2121
2122static int dwc3_runtime_resume(struct device *dev)
2123{
2124 struct dwc3 *dwc = dev_get_drvdata(dev);
2125 int ret;
2126
c4a5153e 2127 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
fc8bb91b
FB		 2128 if (ret)
2129 return ret;
2130
689bf72c
MG		 2131 switch (dwc->current_dr_role) {
2132 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 2133 dwc3_gadget_process_pending_events(dwc);
2134 break;
689bf72c 2135 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 2136 default:
2137 /* do nothing */
2138 break;
2139 }
2140
2141 pm_runtime_mark_last_busy(dev);
2142
2143 return 0;
2144}
2145
2146static int dwc3_runtime_idle(struct device *dev)
2147{
2148 struct dwc3 *dwc = dev_get_drvdata(dev);
2149
689bf72c
MG		 2150 switch (dwc->current_dr_role) {
2151 case DWC3_GCTL_PRTCAP_DEVICE:
fc8bb91b
FB		 2152 if (dwc3_runtime_checks(dwc))
2153 return -EBUSY;
2154 break;
689bf72c 2155 case DWC3_GCTL_PRTCAP_HOST:
fc8bb91b
FB		 2156 default:
2157 /* do nothing */
2158 break;
2159 }
2160
2161 pm_runtime_mark_last_busy(dev);
2162 pm_runtime_autosuspend(dev);
2163
2164 return 0;
2165}
2166#endif /* CONFIG_PM */
2167
2168#ifdef CONFIG_PM_SLEEP
2169static int dwc3_suspend(struct device *dev)
2170{
2171 struct dwc3 *dwc = dev_get_drvdata(dev);
2172 int ret;
2173
c4a5153e 2174 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
fc8bb91b
FB		 2175 if (ret)
2176 return ret;
2177
2178 pinctrl_pm_select_sleep_state(dev);
2179
2180 return 0;
2181}
2182
2183static int dwc3_resume(struct device *dev)
2184{
2185 struct dwc3 *dwc = dev_get_drvdata(dev);
2186 int ret;
2187
2188 pinctrl_pm_select_default_state(dev);
2189
c4a5153e 2190 ret = dwc3_resume_common(dwc, PMSG_RESUME);
fc8bb91b
FB		 2191 if (ret)
2192 return ret;
2193
7415f17c
FB		 2194 pm_runtime_disable(dev);
2195 pm_runtime_set_active(dev);
2196 pm_runtime_enable(dev);
2197
2198 return 0;
2199}
f580170f
YC		 2200
2201static void dwc3_complete(struct device *dev)
2202{
2203 struct dwc3 *dwc = dev_get_drvdata(dev);
2204 u32 reg;
2205
2206 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2207 dwc->dis_split_quirk) {
2208 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2209 reg |= DWC3_GUCTL3_SPLITDISABLE;
2210 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2211 }
2212}
2213#else
2214#define dwc3_complete NULL
7f370ed0 2215#endif /* CONFIG_PM_SLEEP */
7415f17c
FB		 2216
2217static const struct dev_pm_ops dwc3_dev_pm_ops = {
7415f17c 2218 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
f580170f 2219 .complete = dwc3_complete,
fc8bb91b
FB		 2220 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2221 dwc3_runtime_idle)
7415f17c
FB		 2222};
2223
5088b6f5
KVA		 2224#ifdef CONFIG_OF
2225static const struct of_device_id of_dwc3_match[] = {
22a5aa17
FB		 2226 {
2227 .compatible = "snps,dwc3"
2228 },
5088b6f5
KVA		 2229 {
2230 .compatible = "synopsys,dwc3"
2231 },
2232 { },
2233};
2234MODULE_DEVICE_TABLE(of, of_dwc3_match);
2235#endif
2236
404905a6
HK		 2237#ifdef CONFIG_ACPI
2238
2239#define ACPI_ID_INTEL_BSW "808622B7"
2240
2241static const struct acpi_device_id dwc3_acpi_match[] = {
2242 { ACPI_ID_INTEL_BSW, 0 },
2243 { },
2244};
2245MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2246#endif
2247
72246da4
FB		 2248static struct platform_driver dwc3_driver = {
2249 .probe = dwc3_probe,
7690417d 2250 .remove = dwc3_remove,
72246da4
FB		 2251 .driver = {
2252 .name = "dwc3",
5088b6f5 2253 .of_match_table = of_match_ptr(of_dwc3_match),
404905a6 2254 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
7f370ed0 2255 .pm = &dwc3_dev_pm_ops,
72246da4 2256 },
72246da4
FB		 2257};
2258
b1116dcc
TK		 2259module_platform_driver(dwc3_driver);
2260
7ae4fc4d 2261MODULE_ALIAS("platform:dwc3");
72246da4 2262MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
5945f789 2263MODULE_LICENSE("GPL v2");
72246da4 2264MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux 6.x block layer and io_uring tree(s)