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5fd54ace | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
5b9974b1 MK |
2 | /* |
3 | * platform.c - DesignWare HS OTG Controller platform driver | |
4 | * | |
5 | * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl> | |
6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | |
10 | * 1. Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions, and the following disclaimer, | |
12 | * without modification. | |
13 | * 2. Redistributions in binary form must reproduce the above copyright | |
14 | * notice, this list of conditions and the following disclaimer in the | |
15 | * documentation and/or other materials provided with the distribution. | |
16 | * 3. The names of the above-listed copyright holders may not be used | |
17 | * to endorse or promote products derived from this software without | |
18 | * specific prior written permission. | |
19 | * | |
20 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
21 | * GNU General Public License ("GPL") as published by the Free Software | |
22 | * Foundation; either version 2 of the License, or (at your option) any | |
23 | * later version. | |
24 | * | |
25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
26 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
27 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
28 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
29 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
30 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
31 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
32 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
33 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
34 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
35 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
36 | */ | |
37 | ||
38 | #include <linux/kernel.h> | |
39 | #include <linux/module.h> | |
40 | #include <linux/slab.h> | |
09a75e85 | 41 | #include <linux/clk.h> |
5b9974b1 MK |
42 | #include <linux/device.h> |
43 | #include <linux/dma-mapping.h> | |
831eae69 | 44 | #include <linux/of_device.h> |
7ad8096e | 45 | #include <linux/mutex.h> |
5b9974b1 | 46 | #include <linux/platform_device.h> |
09a75e85 MS |
47 | #include <linux/phy/phy.h> |
48 | #include <linux/platform_data/s3c-hsotg.h> | |
83f8da56 | 49 | #include <linux/reset.h> |
5b9974b1 | 50 | |
c0155b9d KY |
51 | #include <linux/usb/of.h> |
52 | ||
5b9974b1 MK |
53 | #include "core.h" |
54 | #include "hcd.h" | |
f91eea44 | 55 | #include "debug.h" |
5b9974b1 MK |
56 | |
57 | static const char dwc2_driver_name[] = "dwc2"; | |
58 | ||
5268ed9d JY |
59 | /* |
60 | * Check the dr_mode against the module configuration and hardware | |
61 | * capabilities. | |
62 | * | |
63 | * The hardware, module, and dr_mode, can each be set to host, device, | |
64 | * or otg. Check that all these values are compatible and adjust the | |
65 | * value of dr_mode if possible. | |
66 | * | |
67 | * actual | |
68 | * HW MOD dr_mode dr_mode | |
69 | * ------------------------------ | |
70 | * HST HST any : HST | |
71 | * HST DEV any : --- | |
72 | * HST OTG any : HST | |
73 | * | |
74 | * DEV HST any : --- | |
75 | * DEV DEV any : DEV | |
76 | * DEV OTG any : DEV | |
77 | * | |
78 | * OTG HST any : HST | |
79 | * OTG DEV any : DEV | |
80 | * OTG OTG any : dr_mode | |
81 | */ | |
82 | static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg) | |
83 | { | |
84 | enum usb_dr_mode mode; | |
85 | ||
86 | hsotg->dr_mode = usb_get_dr_mode(hsotg->dev); | |
87 | if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN) | |
88 | hsotg->dr_mode = USB_DR_MODE_OTG; | |
89 | ||
90 | mode = hsotg->dr_mode; | |
91 | ||
92 | if (dwc2_hw_is_device(hsotg)) { | |
93 | if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) { | |
94 | dev_err(hsotg->dev, | |
95 | "Controller does not support host mode.\n"); | |
96 | return -EINVAL; | |
97 | } | |
98 | mode = USB_DR_MODE_PERIPHERAL; | |
99 | } else if (dwc2_hw_is_host(hsotg)) { | |
100 | if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) { | |
101 | dev_err(hsotg->dev, | |
102 | "Controller does not support device mode.\n"); | |
103 | return -EINVAL; | |
104 | } | |
105 | mode = USB_DR_MODE_HOST; | |
106 | } else { | |
107 | if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) | |
108 | mode = USB_DR_MODE_HOST; | |
109 | else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) | |
110 | mode = USB_DR_MODE_PERIPHERAL; | |
111 | } | |
112 | ||
113 | if (mode != hsotg->dr_mode) { | |
114 | dev_warn(hsotg->dev, | |
9da51974 | 115 | "Configuration mismatch. dr_mode forced to %s\n", |
5268ed9d JY |
116 | mode == USB_DR_MODE_HOST ? "host" : "device"); |
117 | ||
118 | hsotg->dr_mode = mode; | |
119 | } | |
120 | ||
121 | return 0; | |
122 | } | |
123 | ||
09a75e85 MS |
124 | static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg) |
125 | { | |
126 | struct platform_device *pdev = to_platform_device(hsotg->dev); | |
127 | int ret; | |
128 | ||
129 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), | |
130 | hsotg->supplies); | |
131 | if (ret) | |
132 | return ret; | |
133 | ||
8aa90cf2 SW |
134 | if (hsotg->clk) { |
135 | ret = clk_prepare_enable(hsotg->clk); | |
136 | if (ret) | |
137 | return ret; | |
138 | } | |
09a75e85 | 139 | |
34c0887f | 140 | if (hsotg->uphy) { |
09a75e85 | 141 | ret = usb_phy_init(hsotg->uphy); |
34c0887f | 142 | } else if (hsotg->plat && hsotg->plat->phy_init) { |
09a75e85 | 143 | ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type); |
34c0887f | 144 | } else { |
09a75e85 MS |
145 | ret = phy_power_on(hsotg->phy); |
146 | if (ret == 0) | |
147 | ret = phy_init(hsotg->phy); | |
148 | } | |
149 | ||
150 | return ret; | |
151 | } | |
152 | ||
153 | /** | |
154 | * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources | |
155 | * @hsotg: The driver state | |
156 | * | |
157 | * A wrapper for platform code responsible for controlling | |
158 | * low-level USB platform resources (phy, clock, regulators) | |
159 | */ | |
160 | int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg) | |
161 | { | |
162 | int ret = __dwc2_lowlevel_hw_enable(hsotg); | |
163 | ||
164 | if (ret == 0) | |
165 | hsotg->ll_hw_enabled = true; | |
166 | return ret; | |
167 | } | |
168 | ||
169 | static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg) | |
170 | { | |
171 | struct platform_device *pdev = to_platform_device(hsotg->dev); | |
172 | int ret = 0; | |
173 | ||
34c0887f | 174 | if (hsotg->uphy) { |
09a75e85 | 175 | usb_phy_shutdown(hsotg->uphy); |
34c0887f | 176 | } else if (hsotg->plat && hsotg->plat->phy_exit) { |
09a75e85 | 177 | ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type); |
34c0887f | 178 | } else { |
09a75e85 MS |
179 | ret = phy_exit(hsotg->phy); |
180 | if (ret == 0) | |
181 | ret = phy_power_off(hsotg->phy); | |
182 | } | |
183 | if (ret) | |
184 | return ret; | |
185 | ||
8aa90cf2 SW |
186 | if (hsotg->clk) |
187 | clk_disable_unprepare(hsotg->clk); | |
09a75e85 MS |
188 | |
189 | ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
190 | hsotg->supplies); | |
191 | ||
192 | return ret; | |
193 | } | |
194 | ||
195 | /** | |
196 | * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources | |
197 | * @hsotg: The driver state | |
198 | * | |
199 | * A wrapper for platform code responsible for controlling | |
200 | * low-level USB platform resources (phy, clock, regulators) | |
201 | */ | |
202 | int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg) | |
203 | { | |
204 | int ret = __dwc2_lowlevel_hw_disable(hsotg); | |
205 | ||
206 | if (ret == 0) | |
207 | hsotg->ll_hw_enabled = false; | |
208 | return ret; | |
209 | } | |
210 | ||
211 | static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg) | |
212 | { | |
213 | int i, ret; | |
214 | ||
83f8da56 DN |
215 | hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2"); |
216 | if (IS_ERR(hsotg->reset)) { | |
217 | ret = PTR_ERR(hsotg->reset); | |
8ec32c38 PZ |
218 | dev_err(hsotg->dev, "error getting reset control %d\n", ret); |
219 | return ret; | |
83f8da56 DN |
220 | } |
221 | ||
8ec32c38 | 222 | reset_control_deassert(hsotg->reset); |
83f8da56 | 223 | |
f2830ad4 DN |
224 | hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc"); |
225 | if (IS_ERR(hsotg->reset_ecc)) { | |
226 | ret = PTR_ERR(hsotg->reset_ecc); | |
227 | dev_err(hsotg->dev, "error getting reset control for ecc %d\n", ret); | |
228 | return ret; | |
229 | } | |
230 | ||
231 | reset_control_deassert(hsotg->reset_ecc); | |
232 | ||
09a75e85 MS |
233 | /* |
234 | * Attempt to find a generic PHY, then look for an old style | |
235 | * USB PHY and then fall back to pdata | |
236 | */ | |
237 | hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy"); | |
238 | if (IS_ERR(hsotg->phy)) { | |
6c2dad69 SW |
239 | ret = PTR_ERR(hsotg->phy); |
240 | switch (ret) { | |
241 | case -ENODEV: | |
242 | case -ENOSYS: | |
243 | hsotg->phy = NULL; | |
244 | break; | |
245 | case -EPROBE_DEFER: | |
246 | return ret; | |
247 | default: | |
248 | dev_err(hsotg->dev, "error getting phy %d\n", ret); | |
249 | return ret; | |
250 | } | |
251 | } | |
252 | ||
253 | if (!hsotg->phy) { | |
09a75e85 | 254 | hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2); |
6c2dad69 SW |
255 | if (IS_ERR(hsotg->uphy)) { |
256 | ret = PTR_ERR(hsotg->uphy); | |
257 | switch (ret) { | |
258 | case -ENODEV: | |
259 | case -ENXIO: | |
260 | hsotg->uphy = NULL; | |
261 | break; | |
262 | case -EPROBE_DEFER: | |
263 | return ret; | |
264 | default: | |
265 | dev_err(hsotg->dev, "error getting usb phy %d\n", | |
266 | ret); | |
267 | return ret; | |
268 | } | |
269 | } | |
09a75e85 MS |
270 | } |
271 | ||
6c2dad69 SW |
272 | hsotg->plat = dev_get_platdata(hsotg->dev); |
273 | ||
09a75e85 | 274 | /* Clock */ |
60722c4e | 275 | hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg"); |
09a75e85 | 276 | if (IS_ERR(hsotg->clk)) { |
60722c4e CY |
277 | dev_err(hsotg->dev, "cannot get otg clock\n"); |
278 | return PTR_ERR(hsotg->clk); | |
09a75e85 MS |
279 | } |
280 | ||
281 | /* Regulators */ | |
282 | for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++) | |
283 | hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i]; | |
284 | ||
285 | ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies), | |
286 | hsotg->supplies); | |
287 | if (ret) { | |
288 | dev_err(hsotg->dev, "failed to request supplies: %d\n", ret); | |
289 | return ret; | |
290 | } | |
291 | return 0; | |
292 | } | |
293 | ||
5b9974b1 MK |
294 | /** |
295 | * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the | |
296 | * DWC_otg driver | |
297 | * | |
298 | * @dev: Platform device | |
299 | * | |
300 | * This routine is called, for example, when the rmmod command is executed. The | |
301 | * device may or may not be electrically present. If it is present, the driver | |
302 | * stops device processing. Any resources used on behalf of this device are | |
303 | * freed. | |
304 | */ | |
305 | static int dwc2_driver_remove(struct platform_device *dev) | |
306 | { | |
307 | struct dwc2_hsotg *hsotg = platform_get_drvdata(dev); | |
308 | ||
f91eea44 | 309 | dwc2_debugfs_exit(hsotg); |
e39af88f MS |
310 | if (hsotg->hcd_enabled) |
311 | dwc2_hcd_remove(hsotg); | |
312 | if (hsotg->gadget_enabled) | |
1f91b4cc | 313 | dwc2_hsotg_remove(hsotg); |
5b9974b1 | 314 | |
09a75e85 MS |
315 | if (hsotg->ll_hw_enabled) |
316 | dwc2_lowlevel_hw_disable(hsotg); | |
317 | ||
8ec32c38 | 318 | reset_control_assert(hsotg->reset); |
f2830ad4 | 319 | reset_control_assert(hsotg->reset_ecc); |
83f8da56 | 320 | |
5b9974b1 MK |
321 | return 0; |
322 | } | |
323 | ||
a40a0031 HS |
324 | /** |
325 | * dwc2_driver_shutdown() - Called on device shutdown | |
326 | * | |
327 | * @dev: Platform device | |
328 | * | |
329 | * In specific conditions (involving usb hubs) dwc2 devices can create a | |
330 | * lot of interrupts, even to the point of overwhelming devices running | |
331 | * at low frequencies. Some devices need to do special clock handling | |
332 | * at shutdown-time which may bring the system clock below the threshold | |
333 | * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs | |
334 | * prevents reboots/poweroffs from getting stuck in such cases. | |
335 | */ | |
336 | static void dwc2_driver_shutdown(struct platform_device *dev) | |
337 | { | |
338 | struct dwc2_hsotg *hsotg = platform_get_drvdata(dev); | |
339 | ||
340 | disable_irq(hsotg->irq); | |
341 | } | |
342 | ||
fe369e18 GS |
343 | /** |
344 | * dwc2_check_core_endianness() - Returns true if core and AHB have | |
345 | * opposite endianness. | |
346 | * @hsotg: Programming view of the DWC_otg controller. | |
347 | */ | |
348 | static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg) | |
349 | { | |
350 | u32 snpsid; | |
351 | ||
352 | snpsid = ioread32(hsotg->regs + GSNPSID); | |
353 | if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID || | |
354 | (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID || | |
355 | (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID) | |
356 | return false; | |
357 | return true; | |
358 | } | |
359 | ||
5b9974b1 MK |
360 | /** |
361 | * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg | |
362 | * driver | |
363 | * | |
364 | * @dev: Platform device | |
365 | * | |
366 | * This routine creates the driver components required to control the device | |
367 | * (core, HCD, and PCD) and initializes the device. The driver components are | |
368 | * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved | |
369 | * in the device private data. This allows the driver to access the dwc2_hsotg | |
370 | * structure on subsequent calls to driver methods for this device. | |
371 | */ | |
372 | static int dwc2_driver_probe(struct platform_device *dev) | |
373 | { | |
374 | struct dwc2_hsotg *hsotg; | |
375 | struct resource *res; | |
376 | int retval; | |
5b9974b1 | 377 | |
5b9974b1 MK |
378 | hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL); |
379 | if (!hsotg) | |
380 | return -ENOMEM; | |
381 | ||
382 | hsotg->dev = &dev->dev; | |
383 | ||
642f2ecc MK |
384 | /* |
385 | * Use reasonable defaults so platforms don't have to provide these. | |
386 | */ | |
387 | if (!dev->dev.dma_mask) | |
388 | dev->dev.dma_mask = &dev->dev.coherent_dma_mask; | |
4cdbb4ff | 389 | retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32)); |
42c6a252 SW |
390 | if (retval) { |
391 | dev_err(&dev->dev, "can't set coherent DMA mask: %d\n", retval); | |
4cdbb4ff | 392 | return retval; |
42c6a252 | 393 | } |
642f2ecc | 394 | |
5b9974b1 | 395 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
5b9974b1 MK |
396 | hsotg->regs = devm_ioremap_resource(&dev->dev, res); |
397 | if (IS_ERR(hsotg->regs)) | |
398 | return PTR_ERR(hsotg->regs); | |
399 | ||
400 | dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n", | |
401 | (unsigned long)res->start, hsotg->regs); | |
402 | ||
09a75e85 | 403 | retval = dwc2_lowlevel_hw_init(hsotg); |
ecb176c6 MYK |
404 | if (retval) |
405 | return retval; | |
406 | ||
09a75e85 MS |
407 | spin_lock_init(&hsotg->lock); |
408 | ||
a40a0031 HS |
409 | hsotg->irq = platform_get_irq(dev, 0); |
410 | if (hsotg->irq < 0) { | |
f74875dc | 411 | dev_err(&dev->dev, "missing IRQ resource\n"); |
a40a0031 | 412 | return hsotg->irq; |
f74875dc SW |
413 | } |
414 | ||
415 | dev_dbg(hsotg->dev, "registering common handler for irq%d\n", | |
a40a0031 HS |
416 | hsotg->irq); |
417 | retval = devm_request_irq(hsotg->dev, hsotg->irq, | |
f74875dc SW |
418 | dwc2_handle_common_intr, IRQF_SHARED, |
419 | dev_name(hsotg->dev), hsotg); | |
420 | if (retval) | |
421 | return retval; | |
422 | ||
e0f681c2 FG |
423 | hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus"); |
424 | if (IS_ERR(hsotg->vbus_supply)) { | |
425 | retval = PTR_ERR(hsotg->vbus_supply); | |
426 | hsotg->vbus_supply = NULL; | |
427 | if (retval != -ENODEV) | |
428 | return retval; | |
429 | } | |
430 | ||
09a75e85 MS |
431 | retval = dwc2_lowlevel_hw_enable(hsotg); |
432 | if (retval) | |
433 | return retval; | |
434 | ||
d9707490 BMH |
435 | hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg); |
436 | ||
5268ed9d JY |
437 | retval = dwc2_get_dr_mode(hsotg); |
438 | if (retval) | |
a6ef3e02 | 439 | goto error; |
5268ed9d | 440 | |
c846b03f DA |
441 | hsotg->need_phy_for_wake = |
442 | of_property_read_bool(dev->dev.of_node, | |
443 | "snps,need-phy-for-wake"); | |
444 | ||
03b32e4c JY |
445 | /* |
446 | * Reset before dwc2_get_hwparams() then it could get power-on real | |
447 | * reset value form registers. | |
448 | */ | |
13b1f8e2 VM |
449 | retval = dwc2_core_reset(hsotg, false); |
450 | if (retval) | |
451 | goto error; | |
03b32e4c JY |
452 | |
453 | /* Detect config values from hardware */ | |
09a75e85 MS |
454 | retval = dwc2_get_hwparams(hsotg); |
455 | if (retval) | |
456 | goto error; | |
457 | ||
13b1f8e2 VM |
458 | /* |
459 | * For OTG cores, set the force mode bits to reflect the value | |
460 | * of dr_mode. Force mode bits should not be touched at any | |
461 | * other time after this. | |
462 | */ | |
25362d31 | 463 | dwc2_force_dr_mode(hsotg); |
263b7fb5 | 464 | |
334bbd4e JY |
465 | retval = dwc2_init_params(hsotg); |
466 | if (retval) | |
467 | goto error; | |
468 | ||
e39af88f | 469 | if (hsotg->dr_mode != USB_DR_MODE_HOST) { |
f3768997 | 470 | retval = dwc2_gadget_init(hsotg); |
e39af88f | 471 | if (retval) |
09a75e85 | 472 | goto error; |
e39af88f MS |
473 | hsotg->gadget_enabled = 1; |
474 | } | |
475 | ||
c846b03f DA |
476 | /* |
477 | * If we need PHY for wakeup we must be wakeup capable. | |
478 | * When we have a device that can wake without the PHY we | |
479 | * can adjust this condition. | |
480 | */ | |
481 | if (hsotg->need_phy_for_wake) | |
482 | device_set_wakeup_capable(&dev->dev, true); | |
483 | ||
c40cf770 DA |
484 | hsotg->reset_phy_on_wake = |
485 | of_property_read_bool(dev->dev.of_node, | |
486 | "snps,reset-phy-on-wake"); | |
487 | if (hsotg->reset_phy_on_wake && !hsotg->phy) { | |
488 | dev_warn(hsotg->dev, | |
489 | "Quirk reset-phy-on-wake only supports generic PHYs\n"); | |
490 | hsotg->reset_phy_on_wake = false; | |
491 | } | |
492 | ||
e39af88f | 493 | if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) { |
4fe160d5 | 494 | retval = dwc2_hcd_init(hsotg); |
e39af88f MS |
495 | if (retval) { |
496 | if (hsotg->gadget_enabled) | |
1f91b4cc | 497 | dwc2_hsotg_remove(hsotg); |
09a75e85 | 498 | goto error; |
e39af88f MS |
499 | } |
500 | hsotg->hcd_enabled = 1; | |
501 | } | |
5b9974b1 MK |
502 | |
503 | platform_set_drvdata(dev, hsotg); | |
20fe4409 | 504 | hsotg->hibernated = 0; |
5b9974b1 | 505 | |
f91eea44 MYK |
506 | dwc2_debugfs_init(hsotg); |
507 | ||
09a75e85 MS |
508 | /* Gadget code manages lowlevel hw on its own */ |
509 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) | |
510 | dwc2_lowlevel_hw_disable(hsotg); | |
511 | ||
512 | return 0; | |
513 | ||
514 | error: | |
515 | dwc2_lowlevel_hw_disable(hsotg); | |
5b9974b1 MK |
516 | return retval; |
517 | } | |
518 | ||
da9f3289 | 519 | static int __maybe_unused dwc2_suspend(struct device *dev) |
117777b2 | 520 | { |
bcc06078 | 521 | struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev); |
c846b03f | 522 | bool is_device_mode = dwc2_is_device_mode(dwc2); |
117777b2 DN |
523 | int ret = 0; |
524 | ||
c846b03f | 525 | if (is_device_mode) |
09a75e85 MS |
526 | dwc2_hsotg_suspend(dwc2); |
527 | ||
c846b03f DA |
528 | if (dwc2->ll_hw_enabled && |
529 | (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) { | |
09a75e85 | 530 | ret = __dwc2_lowlevel_hw_disable(dwc2); |
c846b03f DA |
531 | dwc2->phy_off_for_suspend = true; |
532 | } | |
135b3c43 | 533 | |
117777b2 DN |
534 | return ret; |
535 | } | |
536 | ||
da9f3289 | 537 | static int __maybe_unused dwc2_resume(struct device *dev) |
117777b2 | 538 | { |
bcc06078 | 539 | struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev); |
117777b2 DN |
540 | int ret = 0; |
541 | ||
c846b03f | 542 | if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) { |
09a75e85 MS |
543 | ret = __dwc2_lowlevel_hw_enable(dwc2); |
544 | if (ret) | |
545 | return ret; | |
546 | } | |
c846b03f | 547 | dwc2->phy_off_for_suspend = false; |
09a75e85 MS |
548 | |
549 | if (dwc2_is_device_mode(dwc2)) | |
1f91b4cc | 550 | ret = dwc2_hsotg_resume(dwc2); |
135b3c43 | 551 | |
117777b2 DN |
552 | return ret; |
553 | } | |
554 | ||
bcc06078 DN |
555 | static const struct dev_pm_ops dwc2_dev_pm_ops = { |
556 | SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume) | |
557 | }; | |
558 | ||
5b9974b1 MK |
559 | static struct platform_driver dwc2_platform_driver = { |
560 | .driver = { | |
1c126bc6 | 561 | .name = dwc2_driver_name, |
5b9974b1 | 562 | .of_match_table = dwc2_of_match_table, |
bcc06078 | 563 | .pm = &dwc2_dev_pm_ops, |
5b9974b1 MK |
564 | }, |
565 | .probe = dwc2_driver_probe, | |
566 | .remove = dwc2_driver_remove, | |
a40a0031 | 567 | .shutdown = dwc2_driver_shutdown, |
5b9974b1 MK |
568 | }; |
569 | ||
570 | module_platform_driver(dwc2_platform_driver); | |
571 | ||
572 | MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue"); | |
573 | MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>"); | |
574 | MODULE_LICENSE("Dual BSD/GPL"); |