Commit | Line | Data |
---|---|---|
323230ef JY |
1 | /* |
2 | * Copyright (C) 2004-2016 Synopsys, Inc. | |
3 | * | |
4 | * Redistribution and use in source and binary forms, with or without | |
5 | * modification, are permitted provided that the following conditions | |
6 | * are met: | |
7 | * 1. Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions, and the following disclaimer, | |
9 | * without modification. | |
10 | * 2. Redistributions in binary form must reproduce the above copyright | |
11 | * notice, this list of conditions and the following disclaimer in the | |
12 | * documentation and/or other materials provided with the distribution. | |
13 | * 3. The names of the above-listed copyright holders may not be used | |
14 | * to endorse or promote products derived from this software without | |
15 | * specific prior written permission. | |
16 | * | |
17 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
18 | * GNU General Public License ("GPL") as published by the Free Software | |
19 | * Foundation; either version 2 of the License, or (at your option) any | |
20 | * later version. | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
23 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
24 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
25 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
26 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
27 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
28 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
29 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
30 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
31 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
32 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/of_device.h> | |
38 | ||
39 | #include "core.h" | |
40 | ||
41 | static const struct dwc2_core_params params_hi6220 = { | |
42 | .otg_cap = 2, /* No HNP/SRP capable */ | |
43 | .otg_ver = 0, /* 1.3 */ | |
323230ef JY |
44 | .dma_desc_enable = 0, |
45 | .dma_desc_fs_enable = 0, | |
46 | .speed = 0, /* High Speed */ | |
47 | .enable_dynamic_fifo = 1, | |
48 | .en_multiple_tx_fifo = 1, | |
49 | .host_rx_fifo_size = 512, | |
50 | .host_nperio_tx_fifo_size = 512, | |
51 | .host_perio_tx_fifo_size = 512, | |
52 | .max_transfer_size = 65535, | |
53 | .max_packet_count = 511, | |
54 | .host_channels = 16, | |
55 | .phy_type = 1, /* UTMI */ | |
56 | .phy_utmi_width = 8, | |
57 | .phy_ulpi_ddr = 0, /* Single */ | |
58 | .phy_ulpi_ext_vbus = 0, | |
59 | .i2c_enable = 0, | |
60 | .ulpi_fs_ls = 0, | |
61 | .host_support_fs_ls_low_power = 0, | |
62 | .host_ls_low_power_phy_clk = 0, /* 48 MHz */ | |
63 | .ts_dline = 0, | |
64 | .reload_ctl = 0, | |
65 | .ahbcfg = GAHBCFG_HBSTLEN_INCR16 << | |
66 | GAHBCFG_HBSTLEN_SHIFT, | |
67 | .uframe_sched = 0, | |
68 | .external_id_pin_ctl = -1, | |
69 | .hibernation = -1, | |
70 | }; | |
71 | ||
72 | static const struct dwc2_core_params params_bcm2835 = { | |
73 | .otg_cap = 0, /* HNP/SRP capable */ | |
74 | .otg_ver = 0, /* 1.3 */ | |
323230ef JY |
75 | .dma_desc_enable = 0, |
76 | .dma_desc_fs_enable = 0, | |
77 | .speed = 0, /* High Speed */ | |
78 | .enable_dynamic_fifo = 1, | |
79 | .en_multiple_tx_fifo = 1, | |
80 | .host_rx_fifo_size = 774, /* 774 DWORDs */ | |
81 | .host_nperio_tx_fifo_size = 256, /* 256 DWORDs */ | |
82 | .host_perio_tx_fifo_size = 512, /* 512 DWORDs */ | |
83 | .max_transfer_size = 65535, | |
84 | .max_packet_count = 511, | |
85 | .host_channels = 8, | |
86 | .phy_type = 1, /* UTMI */ | |
87 | .phy_utmi_width = 8, /* 8 bits */ | |
88 | .phy_ulpi_ddr = 0, /* Single */ | |
89 | .phy_ulpi_ext_vbus = 0, | |
90 | .i2c_enable = 0, | |
91 | .ulpi_fs_ls = 0, | |
92 | .host_support_fs_ls_low_power = 0, | |
93 | .host_ls_low_power_phy_clk = 0, /* 48 MHz */ | |
94 | .ts_dline = 0, | |
95 | .reload_ctl = 0, | |
96 | .ahbcfg = 0x10, | |
97 | .uframe_sched = 0, | |
98 | .external_id_pin_ctl = -1, | |
99 | .hibernation = -1, | |
100 | }; | |
101 | ||
102 | static const struct dwc2_core_params params_rk3066 = { | |
103 | .otg_cap = 2, /* non-HNP/non-SRP */ | |
104 | .otg_ver = -1, | |
323230ef JY |
105 | .dma_desc_enable = 0, |
106 | .dma_desc_fs_enable = 0, | |
107 | .speed = -1, | |
108 | .enable_dynamic_fifo = 1, | |
109 | .en_multiple_tx_fifo = -1, | |
110 | .host_rx_fifo_size = 525, /* 525 DWORDs */ | |
111 | .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */ | |
112 | .host_perio_tx_fifo_size = 256, /* 256 DWORDs */ | |
113 | .max_transfer_size = -1, | |
114 | .max_packet_count = -1, | |
115 | .host_channels = -1, | |
116 | .phy_type = -1, | |
117 | .phy_utmi_width = -1, | |
118 | .phy_ulpi_ddr = -1, | |
119 | .phy_ulpi_ext_vbus = -1, | |
120 | .i2c_enable = -1, | |
121 | .ulpi_fs_ls = -1, | |
122 | .host_support_fs_ls_low_power = -1, | |
123 | .host_ls_low_power_phy_clk = -1, | |
124 | .ts_dline = -1, | |
125 | .reload_ctl = -1, | |
126 | .ahbcfg = GAHBCFG_HBSTLEN_INCR16 << | |
127 | GAHBCFG_HBSTLEN_SHIFT, | |
128 | .uframe_sched = -1, | |
129 | .external_id_pin_ctl = -1, | |
130 | .hibernation = -1, | |
131 | }; | |
132 | ||
133 | static const struct dwc2_core_params params_ltq = { | |
134 | .otg_cap = 2, /* non-HNP/non-SRP */ | |
135 | .otg_ver = -1, | |
323230ef JY |
136 | .dma_desc_enable = -1, |
137 | .dma_desc_fs_enable = -1, | |
138 | .speed = -1, | |
139 | .enable_dynamic_fifo = -1, | |
140 | .en_multiple_tx_fifo = -1, | |
141 | .host_rx_fifo_size = 288, /* 288 DWORDs */ | |
142 | .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */ | |
143 | .host_perio_tx_fifo_size = 96, /* 96 DWORDs */ | |
144 | .max_transfer_size = 65535, | |
145 | .max_packet_count = 511, | |
146 | .host_channels = -1, | |
147 | .phy_type = -1, | |
148 | .phy_utmi_width = -1, | |
149 | .phy_ulpi_ddr = -1, | |
150 | .phy_ulpi_ext_vbus = -1, | |
151 | .i2c_enable = -1, | |
152 | .ulpi_fs_ls = -1, | |
153 | .host_support_fs_ls_low_power = -1, | |
154 | .host_ls_low_power_phy_clk = -1, | |
155 | .ts_dline = -1, | |
156 | .reload_ctl = -1, | |
157 | .ahbcfg = GAHBCFG_HBSTLEN_INCR16 << | |
158 | GAHBCFG_HBSTLEN_SHIFT, | |
159 | .uframe_sched = -1, | |
160 | .external_id_pin_ctl = -1, | |
161 | .hibernation = -1, | |
162 | }; | |
163 | ||
164 | static const struct dwc2_core_params params_amlogic = { | |
165 | .otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE, | |
166 | .otg_ver = -1, | |
323230ef JY |
167 | .dma_desc_enable = 0, |
168 | .dma_desc_fs_enable = 0, | |
169 | .speed = DWC2_SPEED_PARAM_HIGH, | |
170 | .enable_dynamic_fifo = 1, | |
171 | .en_multiple_tx_fifo = -1, | |
172 | .host_rx_fifo_size = 512, | |
173 | .host_nperio_tx_fifo_size = 500, | |
174 | .host_perio_tx_fifo_size = 500, | |
175 | .max_transfer_size = -1, | |
176 | .max_packet_count = -1, | |
177 | .host_channels = 16, | |
178 | .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, | |
179 | .phy_utmi_width = -1, | |
180 | .phy_ulpi_ddr = -1, | |
181 | .phy_ulpi_ext_vbus = -1, | |
182 | .i2c_enable = -1, | |
183 | .ulpi_fs_ls = -1, | |
184 | .host_support_fs_ls_low_power = -1, | |
185 | .host_ls_low_power_phy_clk = -1, | |
186 | .ts_dline = -1, | |
187 | .reload_ctl = 1, | |
188 | .ahbcfg = GAHBCFG_HBSTLEN_INCR8 << | |
189 | GAHBCFG_HBSTLEN_SHIFT, | |
190 | .uframe_sched = 0, | |
191 | .external_id_pin_ctl = -1, | |
192 | .hibernation = -1, | |
193 | }; | |
194 | ||
0a7d0d7f JY |
195 | static const struct dwc2_core_params params_default = { |
196 | .otg_cap = -1, | |
197 | .otg_ver = -1, | |
0a7d0d7f JY |
198 | |
199 | /* | |
200 | * Disable descriptor dma mode by default as the HW can support | |
201 | * it, but does not support it for SPLIT transactions. | |
202 | * Disable it for FS devices as well. | |
203 | */ | |
204 | .dma_desc_enable = 0, | |
205 | .dma_desc_fs_enable = 0, | |
206 | ||
207 | .speed = -1, | |
208 | .enable_dynamic_fifo = -1, | |
209 | .en_multiple_tx_fifo = -1, | |
210 | .host_rx_fifo_size = -1, | |
211 | .host_nperio_tx_fifo_size = -1, | |
212 | .host_perio_tx_fifo_size = -1, | |
213 | .max_transfer_size = -1, | |
214 | .max_packet_count = -1, | |
215 | .host_channels = -1, | |
216 | .phy_type = -1, | |
217 | .phy_utmi_width = -1, | |
218 | .phy_ulpi_ddr = -1, | |
219 | .phy_ulpi_ext_vbus = -1, | |
220 | .i2c_enable = -1, | |
221 | .ulpi_fs_ls = -1, | |
222 | .host_support_fs_ls_low_power = -1, | |
223 | .host_ls_low_power_phy_clk = -1, | |
224 | .ts_dline = -1, | |
225 | .reload_ctl = -1, | |
226 | .ahbcfg = -1, | |
227 | .uframe_sched = -1, | |
228 | .external_id_pin_ctl = -1, | |
229 | .hibernation = -1, | |
230 | }; | |
231 | ||
323230ef JY |
232 | const struct of_device_id dwc2_of_match_table[] = { |
233 | { .compatible = "brcm,bcm2835-usb", .data = ¶ms_bcm2835 }, | |
234 | { .compatible = "hisilicon,hi6220-usb", .data = ¶ms_hi6220 }, | |
235 | { .compatible = "rockchip,rk3066-usb", .data = ¶ms_rk3066 }, | |
236 | { .compatible = "lantiq,arx100-usb", .data = ¶ms_ltq }, | |
237 | { .compatible = "lantiq,xrx200-usb", .data = ¶ms_ltq }, | |
238 | { .compatible = "snps,dwc2", .data = NULL }, | |
239 | { .compatible = "samsung,s3c6400-hsotg", .data = NULL}, | |
240 | { .compatible = "amlogic,meson8b-usb", .data = ¶ms_amlogic }, | |
241 | { .compatible = "amlogic,meson-gxbb-usb", .data = ¶ms_amlogic }, | |
242 | {}, | |
243 | }; | |
244 | MODULE_DEVICE_TABLE(of, dwc2_of_match_table); | |
245 | ||
05ee799f JY |
246 | static void dwc2_get_device_property(struct dwc2_hsotg *hsotg, |
247 | char *property, u8 size, u64 *value) | |
248 | { | |
249 | u8 val8; | |
250 | u16 val16; | |
251 | u32 val32; | |
252 | ||
253 | switch (size) { | |
254 | case 0: | |
255 | *value = device_property_read_bool(hsotg->dev, property); | |
256 | break; | |
257 | case 1: | |
258 | if (device_property_read_u8(hsotg->dev, property, &val8)) | |
259 | return; | |
260 | ||
261 | *value = val8; | |
262 | break; | |
263 | case 2: | |
264 | if (device_property_read_u16(hsotg->dev, property, &val16)) | |
265 | return; | |
266 | ||
267 | *value = val16; | |
268 | break; | |
269 | case 4: | |
270 | if (device_property_read_u32(hsotg->dev, property, &val32)) | |
271 | return; | |
272 | ||
273 | *value = val32; | |
274 | break; | |
275 | case 8: | |
276 | if (device_property_read_u64(hsotg->dev, property, value)) | |
277 | return; | |
278 | ||
279 | break; | |
280 | default: | |
281 | /* | |
282 | * The size is checked by the only function that calls | |
283 | * this so this should never happen. | |
284 | */ | |
285 | WARN_ON(1); | |
286 | return; | |
287 | } | |
288 | } | |
289 | ||
290 | static void dwc2_set_core_param(void *param, u8 size, u64 value) | |
291 | { | |
292 | switch (size) { | |
293 | case 0: | |
294 | *((bool *)param) = !!value; | |
295 | break; | |
296 | case 1: | |
297 | *((u8 *)param) = (u8)value; | |
298 | break; | |
299 | case 2: | |
300 | *((u16 *)param) = (u16)value; | |
301 | break; | |
302 | case 4: | |
303 | *((u32 *)param) = (u32)value; | |
304 | break; | |
305 | case 8: | |
306 | *((u64 *)param) = (u64)value; | |
307 | break; | |
308 | default: | |
309 | /* | |
310 | * The size is checked by the only function that calls | |
311 | * this so this should never happen. | |
312 | */ | |
313 | WARN_ON(1); | |
314 | return; | |
315 | } | |
316 | } | |
317 | ||
318 | /** | |
319 | * dwc2_set_param() - Set a core parameter | |
320 | * | |
321 | * @hsotg: Programming view of the DWC_otg controller | |
322 | * @param: Pointer to the parameter to set | |
323 | * @lookup: True if the property should be looked up | |
324 | * @property: The device property to read | |
325 | * @legacy: The param value to set if @property is not available. This | |
326 | * will typically be the legacy value set in the static | |
327 | * params structure. | |
328 | * @def: The default value | |
329 | * @min: The minimum value | |
330 | * @max: The maximum value | |
331 | * @size: The size of the core parameter in bytes, or 0 for bool. | |
332 | * | |
333 | * This function looks up @property and sets the @param to that value. | |
334 | * If the property doesn't exist it uses the passed-in @value. It will | |
335 | * verify that the value falls between @min and @max. If it doesn't, | |
336 | * it will output an error and set the parameter to either @def or, | |
337 | * failing that, to @min. | |
338 | * | |
339 | * The @size is used to write to @param and to query the device | |
340 | * properties so that this same function can be used with different | |
341 | * types of parameters. | |
342 | */ | |
343 | static void dwc2_set_param(struct dwc2_hsotg *hsotg, void *param, | |
344 | bool lookup, char *property, u64 legacy, | |
345 | u64 def, u64 min, u64 max, u8 size) | |
346 | { | |
347 | u64 sizemax; | |
348 | u64 value; | |
349 | ||
350 | if (WARN_ON(!hsotg || !param || !property)) | |
351 | return; | |
352 | ||
353 | if (WARN((size > 8) || ((size & (size - 1)) != 0), | |
354 | "Invalid size %d for %s\n", size, property)) | |
355 | return; | |
356 | ||
357 | dev_vdbg(hsotg->dev, "%s: Setting %s: legacy=%llu, def=%llu, min=%llu, max=%llu, size=%d\n", | |
358 | __func__, property, legacy, def, min, max, size); | |
359 | ||
360 | sizemax = (1ULL << (size * 8)) - 1; | |
361 | value = legacy; | |
362 | ||
363 | /* Override legacy settings. */ | |
364 | if (lookup) | |
365 | dwc2_get_device_property(hsotg, property, size, &value); | |
366 | ||
367 | /* | |
368 | * While the value is not valid, try setting it to the default | |
369 | * value, and failing that, set it to the minimum. | |
370 | */ | |
371 | while ((value < min) || (value > max)) { | |
372 | /* Print an error unless the value is set to auto. */ | |
373 | if (value != sizemax) | |
374 | dev_err(hsotg->dev, "Invalid value %llu for param %s\n", | |
375 | value, property); | |
376 | ||
377 | /* | |
378 | * If we are already the default, just set it to the | |
379 | * minimum. | |
380 | */ | |
381 | if (value == def) { | |
382 | dev_vdbg(hsotg->dev, "%s: setting value to min=%llu\n", | |
383 | __func__, min); | |
384 | value = min; | |
385 | break; | |
386 | } | |
387 | ||
388 | /* Try the default value */ | |
389 | dev_vdbg(hsotg->dev, "%s: setting value to default=%llu\n", | |
390 | __func__, def); | |
391 | value = def; | |
392 | } | |
393 | ||
394 | dev_dbg(hsotg->dev, "Setting %s to %llu\n", property, value); | |
395 | dwc2_set_core_param(param, size, value); | |
396 | } | |
397 | ||
398 | /** | |
399 | * dwc2_set_param_u16() - Set a u16 parameter | |
400 | * | |
401 | * See dwc2_set_param(). | |
402 | */ | |
403 | static void dwc2_set_param_u16(struct dwc2_hsotg *hsotg, u16 *param, | |
404 | bool lookup, char *property, u16 legacy, | |
405 | u16 def, u16 min, u16 max) | |
406 | { | |
407 | dwc2_set_param(hsotg, param, lookup, property, | |
408 | legacy, def, min, max, 2); | |
409 | } | |
410 | ||
411 | /** | |
412 | * dwc2_set_param_bool() - Set a bool parameter | |
413 | * | |
414 | * See dwc2_set_param(). | |
415 | * | |
416 | * Note: there is no 'legacy' argument here because there is no legacy | |
417 | * source of bool params. | |
418 | */ | |
419 | static void dwc2_set_param_bool(struct dwc2_hsotg *hsotg, bool *param, | |
420 | bool lookup, char *property, | |
421 | bool def, bool min, bool max) | |
422 | { | |
423 | dwc2_set_param(hsotg, param, lookup, property, | |
424 | def, def, min, max, 0); | |
425 | } | |
426 | ||
323230ef JY |
427 | #define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c)) |
428 | ||
429 | /* Parameter access functions */ | |
c1d286cf | 430 | static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val) |
323230ef JY |
431 | { |
432 | int valid = 1; | |
433 | ||
434 | switch (val) { | |
435 | case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: | |
436 | if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) | |
437 | valid = 0; | |
438 | break; | |
439 | case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: | |
440 | switch (hsotg->hw_params.op_mode) { | |
441 | case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: | |
442 | case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: | |
443 | case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: | |
444 | case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: | |
445 | break; | |
446 | default: | |
447 | valid = 0; | |
448 | break; | |
449 | } | |
450 | break; | |
451 | case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE: | |
452 | /* always valid */ | |
453 | break; | |
454 | default: | |
455 | valid = 0; | |
456 | break; | |
457 | } | |
458 | ||
459 | if (!valid) { | |
460 | if (val >= 0) | |
461 | dev_err(hsotg->dev, | |
462 | "%d invalid for otg_cap parameter. Check HW configuration.\n", | |
463 | val); | |
464 | switch (hsotg->hw_params.op_mode) { | |
465 | case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: | |
466 | val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; | |
467 | break; | |
468 | case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: | |
469 | case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: | |
470 | case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: | |
471 | val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; | |
472 | break; | |
473 | default: | |
474 | val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; | |
475 | break; | |
476 | } | |
477 | dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val); | |
478 | } | |
479 | ||
bea8e86c | 480 | hsotg->params.otg_cap = val; |
323230ef JY |
481 | } |
482 | ||
c1d286cf | 483 | static void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val) |
323230ef JY |
484 | { |
485 | int valid = 1; | |
486 | ||
e7839f99 | 487 | if (val > 0 && (hsotg->params.host_dma <= 0 || |
323230ef JY |
488 | !hsotg->hw_params.dma_desc_enable)) |
489 | valid = 0; | |
490 | if (val < 0) | |
491 | valid = 0; | |
492 | ||
493 | if (!valid) { | |
494 | if (val >= 0) | |
495 | dev_err(hsotg->dev, | |
496 | "%d invalid for dma_desc_enable parameter. Check HW configuration.\n", | |
497 | val); | |
e7839f99 | 498 | val = (hsotg->params.host_dma > 0 && |
323230ef JY |
499 | hsotg->hw_params.dma_desc_enable); |
500 | dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val); | |
501 | } | |
502 | ||
bea8e86c | 503 | hsotg->params.dma_desc_enable = val; |
323230ef JY |
504 | } |
505 | ||
c1d286cf | 506 | static void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val) |
323230ef JY |
507 | { |
508 | int valid = 1; | |
509 | ||
e7839f99 | 510 | if (val > 0 && (hsotg->params.host_dma <= 0 || |
323230ef JY |
511 | !hsotg->hw_params.dma_desc_enable)) |
512 | valid = 0; | |
513 | if (val < 0) | |
514 | valid = 0; | |
515 | ||
516 | if (!valid) { | |
517 | if (val >= 0) | |
518 | dev_err(hsotg->dev, | |
519 | "%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n", | |
520 | val); | |
e7839f99 | 521 | val = (hsotg->params.host_dma > 0 && |
323230ef JY |
522 | hsotg->hw_params.dma_desc_enable); |
523 | } | |
524 | ||
bea8e86c | 525 | hsotg->params.dma_desc_fs_enable = val; |
323230ef JY |
526 | dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val); |
527 | } | |
528 | ||
c1d286cf JY |
529 | static void |
530 | dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg, | |
531 | int val) | |
323230ef JY |
532 | { |
533 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { | |
534 | if (val >= 0) { | |
535 | dev_err(hsotg->dev, | |
536 | "Wrong value for host_support_fs_low_power\n"); | |
537 | dev_err(hsotg->dev, | |
538 | "host_support_fs_low_power must be 0 or 1\n"); | |
539 | } | |
540 | val = 0; | |
541 | dev_dbg(hsotg->dev, | |
542 | "Setting host_support_fs_low_power to %d\n", val); | |
543 | } | |
544 | ||
bea8e86c | 545 | hsotg->params.host_support_fs_ls_low_power = val; |
323230ef JY |
546 | } |
547 | ||
c1d286cf JY |
548 | static void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, |
549 | int val) | |
323230ef JY |
550 | { |
551 | int valid = 1; | |
552 | ||
553 | if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo) | |
554 | valid = 0; | |
555 | if (val < 0) | |
556 | valid = 0; | |
557 | ||
558 | if (!valid) { | |
559 | if (val >= 0) | |
560 | dev_err(hsotg->dev, | |
561 | "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n", | |
562 | val); | |
563 | val = hsotg->hw_params.enable_dynamic_fifo; | |
564 | dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val); | |
565 | } | |
566 | ||
bea8e86c | 567 | hsotg->params.enable_dynamic_fifo = val; |
323230ef JY |
568 | } |
569 | ||
c1d286cf | 570 | static void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val) |
323230ef JY |
571 | { |
572 | int valid = 1; | |
573 | ||
d1531319 | 574 | if (val < 16 || val > hsotg->hw_params.rx_fifo_size) |
323230ef JY |
575 | valid = 0; |
576 | ||
577 | if (!valid) { | |
578 | if (val >= 0) | |
579 | dev_err(hsotg->dev, | |
580 | "%d invalid for host_rx_fifo_size. Check HW configuration.\n", | |
581 | val); | |
d1531319 | 582 | val = hsotg->hw_params.rx_fifo_size; |
323230ef JY |
583 | dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val); |
584 | } | |
585 | ||
bea8e86c | 586 | hsotg->params.host_rx_fifo_size = val; |
323230ef JY |
587 | } |
588 | ||
c1d286cf JY |
589 | static void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, |
590 | int val) | |
323230ef JY |
591 | { |
592 | int valid = 1; | |
593 | ||
594 | if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size) | |
595 | valid = 0; | |
596 | ||
597 | if (!valid) { | |
598 | if (val >= 0) | |
599 | dev_err(hsotg->dev, | |
600 | "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n", | |
601 | val); | |
602 | val = hsotg->hw_params.host_nperio_tx_fifo_size; | |
603 | dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n", | |
604 | val); | |
605 | } | |
606 | ||
bea8e86c | 607 | hsotg->params.host_nperio_tx_fifo_size = val; |
323230ef JY |
608 | } |
609 | ||
c1d286cf JY |
610 | static void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, |
611 | int val) | |
323230ef JY |
612 | { |
613 | int valid = 1; | |
614 | ||
615 | if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size) | |
616 | valid = 0; | |
617 | ||
618 | if (!valid) { | |
619 | if (val >= 0) | |
620 | dev_err(hsotg->dev, | |
621 | "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n", | |
622 | val); | |
623 | val = hsotg->hw_params.host_perio_tx_fifo_size; | |
624 | dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n", | |
625 | val); | |
626 | } | |
627 | ||
bea8e86c | 628 | hsotg->params.host_perio_tx_fifo_size = val; |
323230ef JY |
629 | } |
630 | ||
c1d286cf | 631 | static void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val) |
323230ef JY |
632 | { |
633 | int valid = 1; | |
634 | ||
635 | if (val < 2047 || val > hsotg->hw_params.max_transfer_size) | |
636 | valid = 0; | |
637 | ||
638 | if (!valid) { | |
639 | if (val >= 0) | |
640 | dev_err(hsotg->dev, | |
641 | "%d invalid for max_transfer_size. Check HW configuration.\n", | |
642 | val); | |
643 | val = hsotg->hw_params.max_transfer_size; | |
644 | dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val); | |
645 | } | |
646 | ||
bea8e86c | 647 | hsotg->params.max_transfer_size = val; |
323230ef JY |
648 | } |
649 | ||
c1d286cf | 650 | static void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val) |
323230ef JY |
651 | { |
652 | int valid = 1; | |
653 | ||
654 | if (val < 15 || val > hsotg->hw_params.max_packet_count) | |
655 | valid = 0; | |
656 | ||
657 | if (!valid) { | |
658 | if (val >= 0) | |
659 | dev_err(hsotg->dev, | |
660 | "%d invalid for max_packet_count. Check HW configuration.\n", | |
661 | val); | |
662 | val = hsotg->hw_params.max_packet_count; | |
663 | dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val); | |
664 | } | |
665 | ||
bea8e86c | 666 | hsotg->params.max_packet_count = val; |
323230ef JY |
667 | } |
668 | ||
c1d286cf | 669 | static void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val) |
323230ef JY |
670 | { |
671 | int valid = 1; | |
672 | ||
673 | if (val < 1 || val > hsotg->hw_params.host_channels) | |
674 | valid = 0; | |
675 | ||
676 | if (!valid) { | |
677 | if (val >= 0) | |
678 | dev_err(hsotg->dev, | |
679 | "%d invalid for host_channels. Check HW configuration.\n", | |
680 | val); | |
681 | val = hsotg->hw_params.host_channels; | |
682 | dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val); | |
683 | } | |
684 | ||
bea8e86c | 685 | hsotg->params.host_channels = val; |
323230ef JY |
686 | } |
687 | ||
c1d286cf | 688 | static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val) |
323230ef JY |
689 | { |
690 | int valid = 0; | |
691 | u32 hs_phy_type, fs_phy_type; | |
692 | ||
693 | if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS, | |
694 | DWC2_PHY_TYPE_PARAM_ULPI)) { | |
695 | if (val >= 0) { | |
696 | dev_err(hsotg->dev, "Wrong value for phy_type\n"); | |
697 | dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n"); | |
698 | } | |
699 | ||
700 | valid = 0; | |
701 | } | |
702 | ||
703 | hs_phy_type = hsotg->hw_params.hs_phy_type; | |
704 | fs_phy_type = hsotg->hw_params.fs_phy_type; | |
705 | if (val == DWC2_PHY_TYPE_PARAM_UTMI && | |
706 | (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || | |
707 | hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) | |
708 | valid = 1; | |
709 | else if (val == DWC2_PHY_TYPE_PARAM_ULPI && | |
710 | (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI || | |
711 | hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) | |
712 | valid = 1; | |
713 | else if (val == DWC2_PHY_TYPE_PARAM_FS && | |
714 | fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) | |
715 | valid = 1; | |
716 | ||
717 | if (!valid) { | |
718 | if (val >= 0) | |
719 | dev_err(hsotg->dev, | |
720 | "%d invalid for phy_type. Check HW configuration.\n", | |
721 | val); | |
722 | val = DWC2_PHY_TYPE_PARAM_FS; | |
723 | if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { | |
724 | if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || | |
725 | hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) | |
726 | val = DWC2_PHY_TYPE_PARAM_UTMI; | |
727 | else | |
728 | val = DWC2_PHY_TYPE_PARAM_ULPI; | |
729 | } | |
730 | dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val); | |
731 | } | |
732 | ||
bea8e86c | 733 | hsotg->params.phy_type = val; |
323230ef JY |
734 | } |
735 | ||
736 | static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg) | |
737 | { | |
bea8e86c | 738 | return hsotg->params.phy_type; |
323230ef JY |
739 | } |
740 | ||
c1d286cf | 741 | static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val) |
323230ef JY |
742 | { |
743 | int valid = 1; | |
744 | ||
745 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { | |
746 | if (val >= 0) { | |
747 | dev_err(hsotg->dev, "Wrong value for speed parameter\n"); | |
748 | dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n"); | |
749 | } | |
750 | valid = 0; | |
751 | } | |
752 | ||
753 | if (val == DWC2_SPEED_PARAM_HIGH && | |
754 | dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) | |
755 | valid = 0; | |
756 | ||
757 | if (!valid) { | |
758 | if (val >= 0) | |
759 | dev_err(hsotg->dev, | |
760 | "%d invalid for speed parameter. Check HW configuration.\n", | |
761 | val); | |
762 | val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ? | |
763 | DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; | |
764 | dev_dbg(hsotg->dev, "Setting speed to %d\n", val); | |
765 | } | |
766 | ||
bea8e86c | 767 | hsotg->params.speed = val; |
323230ef JY |
768 | } |
769 | ||
c1d286cf JY |
770 | static void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, |
771 | int val) | |
323230ef JY |
772 | { |
773 | int valid = 1; | |
774 | ||
775 | if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ, | |
776 | DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) { | |
777 | if (val >= 0) { | |
778 | dev_err(hsotg->dev, | |
779 | "Wrong value for host_ls_low_power_phy_clk parameter\n"); | |
780 | dev_err(hsotg->dev, | |
781 | "host_ls_low_power_phy_clk must be 0 or 1\n"); | |
782 | } | |
783 | valid = 0; | |
784 | } | |
785 | ||
786 | if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ && | |
787 | dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) | |
788 | valid = 0; | |
789 | ||
790 | if (!valid) { | |
791 | if (val >= 0) | |
792 | dev_err(hsotg->dev, | |
793 | "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n", | |
794 | val); | |
795 | val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS | |
796 | ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ | |
797 | : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ; | |
798 | dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n", | |
799 | val); | |
800 | } | |
801 | ||
bea8e86c | 802 | hsotg->params.host_ls_low_power_phy_clk = val; |
323230ef JY |
803 | } |
804 | ||
c1d286cf | 805 | static void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val) |
323230ef JY |
806 | { |
807 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { | |
808 | if (val >= 0) { | |
809 | dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n"); | |
810 | dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n"); | |
811 | } | |
812 | val = 0; | |
813 | dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val); | |
814 | } | |
815 | ||
bea8e86c | 816 | hsotg->params.phy_ulpi_ddr = val; |
323230ef JY |
817 | } |
818 | ||
c1d286cf | 819 | static void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val) |
323230ef JY |
820 | { |
821 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { | |
822 | if (val >= 0) { | |
823 | dev_err(hsotg->dev, | |
824 | "Wrong value for phy_ulpi_ext_vbus\n"); | |
825 | dev_err(hsotg->dev, | |
826 | "phy_ulpi_ext_vbus must be 0 or 1\n"); | |
827 | } | |
828 | val = 0; | |
829 | dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val); | |
830 | } | |
831 | ||
bea8e86c | 832 | hsotg->params.phy_ulpi_ext_vbus = val; |
323230ef JY |
833 | } |
834 | ||
c1d286cf | 835 | static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val) |
323230ef JY |
836 | { |
837 | int valid = 0; | |
838 | ||
839 | switch (hsotg->hw_params.utmi_phy_data_width) { | |
840 | case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: | |
841 | valid = (val == 8); | |
842 | break; | |
843 | case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: | |
844 | valid = (val == 16); | |
845 | break; | |
846 | case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: | |
847 | valid = (val == 8 || val == 16); | |
848 | break; | |
849 | } | |
850 | ||
851 | if (!valid) { | |
852 | if (val >= 0) { | |
853 | dev_err(hsotg->dev, | |
854 | "%d invalid for phy_utmi_width. Check HW configuration.\n", | |
855 | val); | |
856 | } | |
857 | val = (hsotg->hw_params.utmi_phy_data_width == | |
858 | GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; | |
859 | dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val); | |
860 | } | |
861 | ||
bea8e86c | 862 | hsotg->params.phy_utmi_width = val; |
323230ef JY |
863 | } |
864 | ||
c1d286cf | 865 | static void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val) |
323230ef JY |
866 | { |
867 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { | |
868 | if (val >= 0) { | |
869 | dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n"); | |
870 | dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n"); | |
871 | } | |
872 | val = 0; | |
873 | dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val); | |
874 | } | |
875 | ||
bea8e86c | 876 | hsotg->params.ulpi_fs_ls = val; |
323230ef JY |
877 | } |
878 | ||
c1d286cf | 879 | static void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val) |
323230ef JY |
880 | { |
881 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { | |
882 | if (val >= 0) { | |
883 | dev_err(hsotg->dev, "Wrong value for ts_dline\n"); | |
884 | dev_err(hsotg->dev, "ts_dline must be 0 or 1\n"); | |
885 | } | |
886 | val = 0; | |
887 | dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val); | |
888 | } | |
889 | ||
bea8e86c | 890 | hsotg->params.ts_dline = val; |
323230ef JY |
891 | } |
892 | ||
c1d286cf | 893 | static void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val) |
323230ef JY |
894 | { |
895 | int valid = 1; | |
896 | ||
897 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { | |
898 | if (val >= 0) { | |
899 | dev_err(hsotg->dev, "Wrong value for i2c_enable\n"); | |
900 | dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n"); | |
901 | } | |
902 | ||
903 | valid = 0; | |
904 | } | |
905 | ||
906 | if (val == 1 && !(hsotg->hw_params.i2c_enable)) | |
907 | valid = 0; | |
908 | ||
909 | if (!valid) { | |
910 | if (val >= 0) | |
911 | dev_err(hsotg->dev, | |
912 | "%d invalid for i2c_enable. Check HW configuration.\n", | |
913 | val); | |
914 | val = hsotg->hw_params.i2c_enable; | |
915 | dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val); | |
916 | } | |
917 | ||
bea8e86c | 918 | hsotg->params.i2c_enable = val; |
323230ef JY |
919 | } |
920 | ||
c1d286cf JY |
921 | static void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, |
922 | int val) | |
323230ef JY |
923 | { |
924 | int valid = 1; | |
925 | ||
926 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { | |
927 | if (val >= 0) { | |
928 | dev_err(hsotg->dev, | |
929 | "Wrong value for en_multiple_tx_fifo,\n"); | |
930 | dev_err(hsotg->dev, | |
931 | "en_multiple_tx_fifo must be 0 or 1\n"); | |
932 | } | |
933 | valid = 0; | |
934 | } | |
935 | ||
936 | if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo) | |
937 | valid = 0; | |
938 | ||
939 | if (!valid) { | |
940 | if (val >= 0) | |
941 | dev_err(hsotg->dev, | |
942 | "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n", | |
943 | val); | |
944 | val = hsotg->hw_params.en_multiple_tx_fifo; | |
945 | dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val); | |
946 | } | |
947 | ||
bea8e86c | 948 | hsotg->params.en_multiple_tx_fifo = val; |
323230ef JY |
949 | } |
950 | ||
c1d286cf | 951 | static void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val) |
323230ef JY |
952 | { |
953 | int valid = 1; | |
954 | ||
955 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { | |
956 | if (val >= 0) { | |
957 | dev_err(hsotg->dev, | |
958 | "'%d' invalid for parameter reload_ctl\n", val); | |
959 | dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n"); | |
960 | } | |
961 | valid = 0; | |
962 | } | |
963 | ||
964 | if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a) | |
965 | valid = 0; | |
966 | ||
967 | if (!valid) { | |
968 | if (val >= 0) | |
969 | dev_err(hsotg->dev, | |
970 | "%d invalid for parameter reload_ctl. Check HW configuration.\n", | |
971 | val); | |
972 | val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a; | |
973 | dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val); | |
974 | } | |
975 | ||
bea8e86c | 976 | hsotg->params.reload_ctl = val; |
323230ef JY |
977 | } |
978 | ||
c1d286cf | 979 | static void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val) |
323230ef JY |
980 | { |
981 | if (val != -1) | |
bea8e86c | 982 | hsotg->params.ahbcfg = val; |
323230ef | 983 | else |
bea8e86c | 984 | hsotg->params.ahbcfg = GAHBCFG_HBSTLEN_INCR4 << |
323230ef JY |
985 | GAHBCFG_HBSTLEN_SHIFT; |
986 | } | |
987 | ||
c1d286cf | 988 | static void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val) |
323230ef JY |
989 | { |
990 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { | |
991 | if (val >= 0) { | |
992 | dev_err(hsotg->dev, | |
993 | "'%d' invalid for parameter otg_ver\n", val); | |
994 | dev_err(hsotg->dev, | |
995 | "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n"); | |
996 | } | |
997 | val = 0; | |
998 | dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val); | |
999 | } | |
1000 | ||
bea8e86c | 1001 | hsotg->params.otg_ver = val; |
323230ef JY |
1002 | } |
1003 | ||
1004 | static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val) | |
1005 | { | |
1006 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { | |
1007 | if (val >= 0) { | |
1008 | dev_err(hsotg->dev, | |
1009 | "'%d' invalid for parameter uframe_sched\n", | |
1010 | val); | |
1011 | dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n"); | |
1012 | } | |
1013 | val = 1; | |
1014 | dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val); | |
1015 | } | |
1016 | ||
bea8e86c | 1017 | hsotg->params.uframe_sched = val; |
323230ef JY |
1018 | } |
1019 | ||
1020 | static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg, | |
1021 | int val) | |
1022 | { | |
1023 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { | |
1024 | if (val >= 0) { | |
1025 | dev_err(hsotg->dev, | |
1026 | "'%d' invalid for parameter external_id_pin_ctl\n", | |
1027 | val); | |
1028 | dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n"); | |
1029 | } | |
1030 | val = 0; | |
1031 | dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val); | |
1032 | } | |
1033 | ||
bea8e86c | 1034 | hsotg->params.external_id_pin_ctl = val; |
323230ef JY |
1035 | } |
1036 | ||
1037 | static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg, | |
1038 | int val) | |
1039 | { | |
1040 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { | |
1041 | if (val >= 0) { | |
1042 | dev_err(hsotg->dev, | |
1043 | "'%d' invalid for parameter hibernation\n", | |
1044 | val); | |
1045 | dev_err(hsotg->dev, "hibernation must be 0 or 1\n"); | |
1046 | } | |
1047 | val = 0; | |
1048 | dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val); | |
1049 | } | |
1050 | ||
bea8e86c | 1051 | hsotg->params.hibernation = val; |
323230ef JY |
1052 | } |
1053 | ||
05ee799f JY |
1054 | static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) |
1055 | { | |
1056 | int i; | |
1057 | int num; | |
1058 | char *property = "g-tx-fifo-size"; | |
1059 | struct dwc2_core_params *p = &hsotg->params; | |
1060 | ||
1061 | memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); | |
1062 | ||
1063 | /* Read tx fifo sizes */ | |
1064 | num = device_property_read_u32_array(hsotg->dev, property, NULL, 0); | |
1065 | ||
1066 | if (num > 0) { | |
1067 | device_property_read_u32_array(hsotg->dev, property, | |
1068 | &p->g_tx_fifo_size[1], | |
1069 | num); | |
1070 | } else { | |
1071 | u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE; | |
1072 | ||
1073 | memcpy(&p->g_tx_fifo_size[1], | |
1074 | p_tx_fifo, | |
1075 | sizeof(p_tx_fifo)); | |
1076 | ||
1077 | num = ARRAY_SIZE(p_tx_fifo); | |
1078 | } | |
1079 | ||
1080 | for (i = 0; i < num; i++) { | |
1081 | if ((i + 1) >= ARRAY_SIZE(p->g_tx_fifo_size)) | |
1082 | break; | |
1083 | ||
1084 | dev_dbg(hsotg->dev, "Setting %s[%d] to %d\n", | |
1085 | property, i + 1, p->g_tx_fifo_size[i + 1]); | |
1086 | } | |
1087 | } | |
1088 | ||
9962b62f JY |
1089 | static void dwc2_set_gadget_dma(struct dwc2_hsotg *hsotg) |
1090 | { | |
1091 | struct dwc2_hw_params *hw = &hsotg->hw_params; | |
1092 | struct dwc2_core_params *p = &hsotg->params; | |
1093 | bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); | |
1094 | ||
1095 | /* Buffer DMA */ | |
1096 | dwc2_set_param_bool(hsotg, &p->g_dma, | |
1097 | false, "gadget-dma", | |
1098 | true, false, | |
1099 | dma_capable); | |
dec4b556 VA |
1100 | |
1101 | /* DMA Descriptor */ | |
1102 | dwc2_set_param_bool(hsotg, &p->g_dma_desc, false, | |
1103 | "gadget-dma-desc", | |
1104 | p->g_dma, false, | |
1105 | !!hw->dma_desc_enable); | |
9962b62f JY |
1106 | } |
1107 | ||
05ee799f JY |
1108 | /** |
1109 | * dwc2_set_parameters() - Set all core parameters. | |
1110 | * | |
1111 | * @hsotg: Programming view of the DWC_otg controller | |
1112 | * @params: The parameters to set | |
323230ef | 1113 | */ |
c1d286cf JY |
1114 | static void dwc2_set_parameters(struct dwc2_hsotg *hsotg, |
1115 | const struct dwc2_core_params *params) | |
323230ef | 1116 | { |
05ee799f JY |
1117 | struct dwc2_hw_params *hw = &hsotg->hw_params; |
1118 | struct dwc2_core_params *p = &hsotg->params; | |
6b66ce51 | 1119 | bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); |
323230ef JY |
1120 | |
1121 | dwc2_set_param_otg_cap(hsotg, params->otg_cap); | |
323230ef JY |
1122 | dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable); |
1123 | dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable); | |
6b66ce51 JY |
1124 | |
1125 | if ((hsotg->dr_mode == USB_DR_MODE_HOST) || | |
1126 | (hsotg->dr_mode == USB_DR_MODE_OTG)) { | |
1127 | bool disable; | |
1128 | ||
1129 | dev_dbg(hsotg->dev, "Setting HOST parameters\n"); | |
1130 | ||
1131 | disable = device_property_read_bool(hsotg->dev, | |
1132 | "snps,host-dma-disable"); | |
1133 | ||
1134 | dwc2_set_param_bool(hsotg, &p->host_dma, | |
1135 | false, "host-dma", | |
1136 | !disable, false, | |
1137 | dma_capable); | |
1138 | } | |
1139 | ||
323230ef JY |
1140 | dwc2_set_param_host_support_fs_ls_low_power(hsotg, |
1141 | params->host_support_fs_ls_low_power); | |
1142 | dwc2_set_param_enable_dynamic_fifo(hsotg, | |
1143 | params->enable_dynamic_fifo); | |
1144 | dwc2_set_param_host_rx_fifo_size(hsotg, | |
1145 | params->host_rx_fifo_size); | |
1146 | dwc2_set_param_host_nperio_tx_fifo_size(hsotg, | |
1147 | params->host_nperio_tx_fifo_size); | |
1148 | dwc2_set_param_host_perio_tx_fifo_size(hsotg, | |
1149 | params->host_perio_tx_fifo_size); | |
1150 | dwc2_set_param_max_transfer_size(hsotg, | |
1151 | params->max_transfer_size); | |
1152 | dwc2_set_param_max_packet_count(hsotg, | |
1153 | params->max_packet_count); | |
1154 | dwc2_set_param_host_channels(hsotg, params->host_channels); | |
1155 | dwc2_set_param_phy_type(hsotg, params->phy_type); | |
1156 | dwc2_set_param_speed(hsotg, params->speed); | |
1157 | dwc2_set_param_host_ls_low_power_phy_clk(hsotg, | |
1158 | params->host_ls_low_power_phy_clk); | |
1159 | dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr); | |
1160 | dwc2_set_param_phy_ulpi_ext_vbus(hsotg, | |
1161 | params->phy_ulpi_ext_vbus); | |
1162 | dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width); | |
1163 | dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls); | |
1164 | dwc2_set_param_ts_dline(hsotg, params->ts_dline); | |
1165 | dwc2_set_param_i2c_enable(hsotg, params->i2c_enable); | |
1166 | dwc2_set_param_en_multiple_tx_fifo(hsotg, | |
1167 | params->en_multiple_tx_fifo); | |
1168 | dwc2_set_param_reload_ctl(hsotg, params->reload_ctl); | |
1169 | dwc2_set_param_ahbcfg(hsotg, params->ahbcfg); | |
1170 | dwc2_set_param_otg_ver(hsotg, params->otg_ver); | |
1171 | dwc2_set_param_uframe_sched(hsotg, params->uframe_sched); | |
1172 | dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl); | |
1173 | dwc2_set_param_hibernation(hsotg, params->hibernation); | |
05ee799f JY |
1174 | |
1175 | /* | |
1176 | * Set devicetree-only parameters. These parameters do not | |
1177 | * take any values from @params. | |
1178 | */ | |
1179 | if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || | |
1180 | (hsotg->dr_mode == USB_DR_MODE_OTG)) { | |
1181 | dev_dbg(hsotg->dev, "Setting peripheral device properties\n"); | |
1182 | ||
9962b62f | 1183 | dwc2_set_gadget_dma(hsotg); |
05ee799f JY |
1184 | |
1185 | /* | |
1186 | * The values for g_rx_fifo_size (2048) and | |
1187 | * g_np_tx_fifo_size (1024) come from the legacy s3c | |
1188 | * gadget driver. These defaults have been hard-coded | |
1189 | * for some time so many platforms depend on these | |
1190 | * values. Leave them as defaults for now and only | |
1191 | * auto-detect if the hardware does not support the | |
1192 | * default. | |
1193 | */ | |
1194 | dwc2_set_param_u16(hsotg, &p->g_rx_fifo_size, | |
1195 | true, "g-rx-fifo-size", 2048, | |
1196 | hw->rx_fifo_size, | |
1197 | 16, hw->rx_fifo_size); | |
1198 | ||
1199 | dwc2_set_param_u16(hsotg, &p->g_np_tx_fifo_size, | |
1200 | true, "g-np-tx-fifo-size", 1024, | |
1201 | hw->dev_nperio_tx_fifo_size, | |
1202 | 16, hw->dev_nperio_tx_fifo_size); | |
1203 | ||
1204 | dwc2_set_param_tx_fifo_sizes(hsotg); | |
1205 | } | |
323230ef JY |
1206 | } |
1207 | ||
1208 | /* | |
1209 | * Gets host hardware parameters. Forces host mode if not currently in | |
1210 | * host mode. Should be called immediately after a core soft reset in | |
1211 | * order to get the reset values. | |
1212 | */ | |
1213 | static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) | |
1214 | { | |
1215 | struct dwc2_hw_params *hw = &hsotg->hw_params; | |
1216 | u32 gnptxfsiz; | |
1217 | u32 hptxfsiz; | |
1218 | bool forced; | |
1219 | ||
1220 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) | |
1221 | return; | |
1222 | ||
1223 | forced = dwc2_force_mode_if_needed(hsotg, true); | |
1224 | ||
1225 | gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); | |
1226 | hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); | |
1227 | dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); | |
1228 | dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); | |
1229 | ||
1230 | if (forced) | |
1231 | dwc2_clear_force_mode(hsotg); | |
1232 | ||
1233 | hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> | |
1234 | FIFOSIZE_DEPTH_SHIFT; | |
1235 | hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> | |
1236 | FIFOSIZE_DEPTH_SHIFT; | |
1237 | } | |
1238 | ||
1239 | /* | |
1240 | * Gets device hardware parameters. Forces device mode if not | |
1241 | * currently in device mode. Should be called immediately after a core | |
1242 | * soft reset in order to get the reset values. | |
1243 | */ | |
1244 | static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) | |
1245 | { | |
1246 | struct dwc2_hw_params *hw = &hsotg->hw_params; | |
1247 | bool forced; | |
1248 | u32 gnptxfsiz; | |
1249 | ||
1250 | if (hsotg->dr_mode == USB_DR_MODE_HOST) | |
1251 | return; | |
1252 | ||
1253 | forced = dwc2_force_mode_if_needed(hsotg, false); | |
1254 | ||
1255 | gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); | |
1256 | dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); | |
1257 | ||
1258 | if (forced) | |
1259 | dwc2_clear_force_mode(hsotg); | |
1260 | ||
1261 | hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> | |
1262 | FIFOSIZE_DEPTH_SHIFT; | |
1263 | } | |
1264 | ||
1265 | /** | |
1266 | * During device initialization, read various hardware configuration | |
1267 | * registers and interpret the contents. | |
1268 | */ | |
1269 | int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) | |
1270 | { | |
1271 | struct dwc2_hw_params *hw = &hsotg->hw_params; | |
1272 | unsigned int width; | |
1273 | u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; | |
1274 | u32 grxfsiz; | |
1275 | ||
1276 | /* | |
1277 | * Attempt to ensure this device is really a DWC_otg Controller. | |
1278 | * Read and verify the GSNPSID register contents. The value should be | |
1279 | * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", | |
1280 | * as in "OTG version 2.xx" or "OTG version 3.xx". | |
1281 | */ | |
1282 | hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID); | |
1283 | if ((hw->snpsid & 0xfffff000) != 0x4f542000 && | |
1284 | (hw->snpsid & 0xfffff000) != 0x4f543000) { | |
1285 | dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", | |
1286 | hw->snpsid); | |
1287 | return -ENODEV; | |
1288 | } | |
1289 | ||
1290 | dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", | |
1291 | hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, | |
1292 | hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); | |
1293 | ||
1294 | hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); | |
1295 | hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); | |
1296 | hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); | |
1297 | hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); | |
1298 | grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); | |
1299 | ||
1300 | dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1); | |
1301 | dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2); | |
1302 | dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3); | |
1303 | dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4); | |
1304 | dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); | |
1305 | ||
1306 | /* | |
1307 | * Host specific hardware parameters. Reading these parameters | |
1308 | * requires the controller to be in host mode. The mode will | |
1309 | * be forced, if necessary, to read these values. | |
1310 | */ | |
1311 | dwc2_get_host_hwparams(hsotg); | |
1312 | dwc2_get_dev_hwparams(hsotg); | |
1313 | ||
1314 | /* hwcfg1 */ | |
1315 | hw->dev_ep_dirs = hwcfg1; | |
1316 | ||
1317 | /* hwcfg2 */ | |
1318 | hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> | |
1319 | GHWCFG2_OP_MODE_SHIFT; | |
1320 | hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> | |
1321 | GHWCFG2_ARCHITECTURE_SHIFT; | |
1322 | hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); | |
1323 | hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> | |
1324 | GHWCFG2_NUM_HOST_CHAN_SHIFT); | |
1325 | hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> | |
1326 | GHWCFG2_HS_PHY_TYPE_SHIFT; | |
1327 | hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> | |
1328 | GHWCFG2_FS_PHY_TYPE_SHIFT; | |
1329 | hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> | |
1330 | GHWCFG2_NUM_DEV_EP_SHIFT; | |
1331 | hw->nperio_tx_q_depth = | |
1332 | (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> | |
1333 | GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; | |
1334 | hw->host_perio_tx_q_depth = | |
1335 | (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> | |
1336 | GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; | |
1337 | hw->dev_token_q_depth = | |
1338 | (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> | |
1339 | GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; | |
1340 | ||
1341 | /* hwcfg3 */ | |
1342 | width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> | |
1343 | GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; | |
1344 | hw->max_transfer_size = (1 << (width + 11)) - 1; | |
1345 | width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> | |
1346 | GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; | |
1347 | hw->max_packet_count = (1 << (width + 4)) - 1; | |
1348 | hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); | |
1349 | hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> | |
1350 | GHWCFG3_DFIFO_DEPTH_SHIFT; | |
1351 | ||
1352 | /* hwcfg4 */ | |
1353 | hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); | |
1354 | hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> | |
1355 | GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; | |
1356 | hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); | |
1357 | hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); | |
1358 | hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> | |
1359 | GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; | |
1360 | ||
1361 | /* fifo sizes */ | |
d1531319 | 1362 | hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> |
323230ef JY |
1363 | GRXFSIZ_DEPTH_SHIFT; |
1364 | ||
1365 | dev_dbg(hsotg->dev, "Detected values from hardware:\n"); | |
1366 | dev_dbg(hsotg->dev, " op_mode=%d\n", | |
1367 | hw->op_mode); | |
1368 | dev_dbg(hsotg->dev, " arch=%d\n", | |
1369 | hw->arch); | |
1370 | dev_dbg(hsotg->dev, " dma_desc_enable=%d\n", | |
1371 | hw->dma_desc_enable); | |
1372 | dev_dbg(hsotg->dev, " power_optimized=%d\n", | |
1373 | hw->power_optimized); | |
1374 | dev_dbg(hsotg->dev, " i2c_enable=%d\n", | |
1375 | hw->i2c_enable); | |
1376 | dev_dbg(hsotg->dev, " hs_phy_type=%d\n", | |
1377 | hw->hs_phy_type); | |
1378 | dev_dbg(hsotg->dev, " fs_phy_type=%d\n", | |
1379 | hw->fs_phy_type); | |
1380 | dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n", | |
1381 | hw->utmi_phy_data_width); | |
1382 | dev_dbg(hsotg->dev, " num_dev_ep=%d\n", | |
1383 | hw->num_dev_ep); | |
1384 | dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n", | |
1385 | hw->num_dev_perio_in_ep); | |
1386 | dev_dbg(hsotg->dev, " host_channels=%d\n", | |
1387 | hw->host_channels); | |
1388 | dev_dbg(hsotg->dev, " max_transfer_size=%d\n", | |
1389 | hw->max_transfer_size); | |
1390 | dev_dbg(hsotg->dev, " max_packet_count=%d\n", | |
1391 | hw->max_packet_count); | |
1392 | dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n", | |
1393 | hw->nperio_tx_q_depth); | |
1394 | dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n", | |
1395 | hw->host_perio_tx_q_depth); | |
1396 | dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n", | |
1397 | hw->dev_token_q_depth); | |
1398 | dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n", | |
1399 | hw->enable_dynamic_fifo); | |
1400 | dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n", | |
1401 | hw->en_multiple_tx_fifo); | |
1402 | dev_dbg(hsotg->dev, " total_fifo_size=%d\n", | |
1403 | hw->total_fifo_size); | |
d1531319 JY |
1404 | dev_dbg(hsotg->dev, " rx_fifo_size=%d\n", |
1405 | hw->rx_fifo_size); | |
323230ef JY |
1406 | dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n", |
1407 | hw->host_nperio_tx_fifo_size); | |
1408 | dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n", | |
1409 | hw->host_perio_tx_fifo_size); | |
1410 | dev_dbg(hsotg->dev, "\n"); | |
1411 | ||
1412 | return 0; | |
1413 | } | |
1414 | ||
334bbd4e JY |
1415 | int dwc2_init_params(struct dwc2_hsotg *hsotg) |
1416 | { | |
1417 | const struct of_device_id *match; | |
0a7d0d7f | 1418 | struct dwc2_core_params params; |
334bbd4e JY |
1419 | |
1420 | match = of_match_device(dwc2_of_match_table, hsotg->dev); | |
0a7d0d7f JY |
1421 | if (match && match->data) |
1422 | params = *((struct dwc2_core_params *)match->data); | |
1423 | else | |
1424 | params = params_default; | |
334bbd4e | 1425 | |
0a7d0d7f | 1426 | dwc2_set_parameters(hsotg, ¶ms); |
334bbd4e JY |
1427 | |
1428 | return 0; | |
1429 | } |