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5fd54ace | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
7359d482 PZ |
2 | /* |
3 | * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling | |
4 | * | |
5 | * Copyright (C) 2004-2013 Synopsys, Inc. | |
6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | |
10 | * 1. Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions, and the following disclaimer, | |
12 | * without modification. | |
13 | * 2. Redistributions in binary form must reproduce the above copyright | |
14 | * notice, this list of conditions and the following disclaimer in the | |
15 | * documentation and/or other materials provided with the distribution. | |
16 | * 3. The names of the above-listed copyright holders may not be used | |
17 | * to endorse or promote products derived from this software without | |
18 | * specific prior written permission. | |
19 | * | |
20 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
21 | * GNU General Public License ("GPL") as published by the Free Software | |
22 | * Foundation; either version 2 of the License, or (at your option) any | |
23 | * later version. | |
24 | * | |
25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
26 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
27 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
28 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
29 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
30 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
31 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
32 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
33 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
34 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
35 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
36 | */ | |
37 | ||
38 | /* | |
39 | * This file contains the interrupt handlers for Host mode | |
40 | */ | |
41 | #include <linux/kernel.h> | |
42 | #include <linux/module.h> | |
43 | #include <linux/spinlock.h> | |
44 | #include <linux/interrupt.h> | |
45 | #include <linux/dma-mapping.h> | |
46 | #include <linux/io.h> | |
47 | #include <linux/slab.h> | |
48 | #include <linux/usb.h> | |
49 | ||
50 | #include <linux/usb/hcd.h> | |
51 | #include <linux/usb/ch11.h> | |
52 | ||
53 | #include "core.h" | |
54 | #include "hcd.h" | |
55 | ||
56 | /* This function is for debug only */ | |
57 | static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg) | |
58 | { | |
7359d482 | 59 | u16 curr_frame_number = hsotg->frame_number; |
483bb254 DA |
60 | u16 expected = dwc2_frame_num_inc(hsotg->last_frame_num, 1); |
61 | ||
62 | if (expected != curr_frame_number) | |
63 | dwc2_sch_vdbg(hsotg, "MISSED SOF %04x != %04x\n", | |
9da51974 | 64 | expected, curr_frame_number); |
7359d482 | 65 | |
483bb254 | 66 | #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS |
7359d482 | 67 | if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) { |
483bb254 | 68 | if (expected != curr_frame_number) { |
7359d482 PZ |
69 | hsotg->frame_num_array[hsotg->frame_num_idx] = |
70 | curr_frame_number; | |
71 | hsotg->last_frame_num_array[hsotg->frame_num_idx] = | |
72 | hsotg->last_frame_num; | |
73 | hsotg->frame_num_idx++; | |
74 | } | |
75 | } else if (!hsotg->dumped_frame_num_array) { | |
76 | int i; | |
77 | ||
78 | dev_info(hsotg->dev, "Frame Last Frame\n"); | |
79 | dev_info(hsotg->dev, "----- ----------\n"); | |
80 | for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) { | |
81 | dev_info(hsotg->dev, "0x%04x 0x%04x\n", | |
82 | hsotg->frame_num_array[i], | |
83 | hsotg->last_frame_num_array[i]); | |
84 | } | |
85 | hsotg->dumped_frame_num_array = 1; | |
86 | } | |
7359d482 | 87 | #endif |
483bb254 | 88 | hsotg->last_frame_num = curr_frame_number; |
7359d482 PZ |
89 | } |
90 | ||
91 | static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg, | |
92 | struct dwc2_host_chan *chan, | |
93 | struct dwc2_qtd *qtd) | |
94 | { | |
d82a810e | 95 | struct usb_device *root_hub = dwc2_hsotg_to_hcd(hsotg)->self.root_hub; |
7359d482 PZ |
96 | struct urb *usb_urb; |
97 | ||
399fdf9e PZ |
98 | if (!chan->qh) |
99 | return; | |
100 | ||
101 | if (chan->qh->dev_speed == USB_SPEED_HIGH) | |
102 | return; | |
103 | ||
104 | if (!qtd->urb) | |
7359d482 PZ |
105 | return; |
106 | ||
107 | usb_urb = qtd->urb->priv; | |
399fdf9e | 108 | if (!usb_urb || !usb_urb->dev || !usb_urb->dev->tt) |
7359d482 PZ |
109 | return; |
110 | ||
d82a810e DA |
111 | /* |
112 | * The root hub doesn't really have a TT, but Linux thinks it | |
113 | * does because how could you have a "high speed hub" that | |
114 | * directly talks directly to low speed devices without a TT? | |
115 | * It's all lies. Lies, I tell you. | |
116 | */ | |
117 | if (usb_urb->dev->tt->hub == root_hub) | |
118 | return; | |
119 | ||
399fdf9e | 120 | if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) { |
7359d482 PZ |
121 | chan->qh->tt_buffer_dirty = 1; |
122 | if (usb_hub_clear_tt_buffer(usb_urb)) | |
123 | /* Clear failed; let's hope things work anyway */ | |
124 | chan->qh->tt_buffer_dirty = 0; | |
125 | } | |
126 | } | |
127 | ||
128 | /* | |
129 | * Handles the start-of-frame interrupt in host mode. Non-periodic | |
130 | * transactions may be queued to the DWC_otg controller for the current | |
131 | * (micro)frame. Periodic transactions may be queued to the controller | |
132 | * for the next (micro)frame. | |
133 | */ | |
134 | static void dwc2_sof_intr(struct dwc2_hsotg *hsotg) | |
135 | { | |
136 | struct list_head *qh_entry; | |
137 | struct dwc2_qh *qh; | |
7359d482 PZ |
138 | enum dwc2_transaction_type tr_type; |
139 | ||
29539019 DA |
140 | /* Clear interrupt */ |
141 | dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS); | |
142 | ||
7359d482 PZ |
143 | #ifdef DEBUG_SOF |
144 | dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n"); | |
145 | #endif | |
146 | ||
37e1dcc2 | 147 | hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg); |
7359d482 PZ |
148 | |
149 | dwc2_track_missed_sofs(hsotg); | |
150 | ||
151 | /* Determine whether any periodic QHs should be executed */ | |
152 | qh_entry = hsotg->periodic_sched_inactive.next; | |
153 | while (qh_entry != &hsotg->periodic_sched_inactive) { | |
154 | qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry); | |
155 | qh_entry = qh_entry->next; | |
ced9eee1 DA |
156 | if (dwc2_frame_num_le(qh->next_active_frame, |
157 | hsotg->frame_number)) { | |
158 | dwc2_sch_vdbg(hsotg, "QH=%p ready fn=%04x, nxt=%04x\n", | |
159 | qh, hsotg->frame_number, | |
160 | qh->next_active_frame); | |
74fc4a75 | 161 | |
7359d482 PZ |
162 | /* |
163 | * Move QH to the ready list to be executed next | |
164 | * (micro)frame | |
165 | */ | |
94ef7aee | 166 | list_move_tail(&qh->qh_list_entry, |
9da51974 | 167 | &hsotg->periodic_sched_ready); |
74fc4a75 | 168 | } |
7359d482 PZ |
169 | } |
170 | tr_type = dwc2_hcd_select_transactions(hsotg); | |
171 | if (tr_type != DWC2_TRANSACTION_NONE) | |
172 | dwc2_hcd_queue_transactions(hsotg, tr_type); | |
7359d482 PZ |
173 | } |
174 | ||
175 | /* | |
176 | * Handles the Rx FIFO Level Interrupt, which indicates that there is | |
177 | * at least one packet in the Rx FIFO. The packets are moved from the FIFO to | |
178 | * memory if the DWC_otg controller is operating in Slave mode. | |
179 | */ | |
180 | static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg) | |
181 | { | |
182 | u32 grxsts, chnum, bcnt, dpid, pktsts; | |
183 | struct dwc2_host_chan *chan; | |
184 | ||
b49977a6 MK |
185 | if (dbg_perio()) |
186 | dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n"); | |
7359d482 | 187 | |
95c8bc36 | 188 | grxsts = dwc2_readl(hsotg->regs + GRXSTSP); |
d6ec53e0 | 189 | chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT; |
7359d482 PZ |
190 | chan = hsotg->hc_ptr_array[chnum]; |
191 | if (!chan) { | |
192 | dev_err(hsotg->dev, "Unable to get corresponding channel\n"); | |
193 | return; | |
194 | } | |
195 | ||
d6ec53e0 MK |
196 | bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT; |
197 | dpid = (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT; | |
f9234633 | 198 | pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT; |
7359d482 PZ |
199 | |
200 | /* Packet Status */ | |
b49977a6 MK |
201 | if (dbg_perio()) { |
202 | dev_vdbg(hsotg->dev, " Ch num = %d\n", chnum); | |
203 | dev_vdbg(hsotg->dev, " Count = %d\n", bcnt); | |
204 | dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n", dpid, | |
205 | chan->data_pid_start); | |
f9234633 | 206 | dev_vdbg(hsotg->dev, " PStatus = %d\n", pktsts); |
b49977a6 | 207 | } |
7359d482 PZ |
208 | |
209 | switch (pktsts) { | |
210 | case GRXSTS_PKTSTS_HCHIN: | |
211 | /* Read the data into the host buffer */ | |
212 | if (bcnt > 0) { | |
213 | dwc2_read_packet(hsotg, chan->xfer_buf, bcnt); | |
214 | ||
215 | /* Update the HC fields for the next packet received */ | |
216 | chan->xfer_count += bcnt; | |
217 | chan->xfer_buf += bcnt; | |
218 | } | |
219 | break; | |
220 | case GRXSTS_PKTSTS_HCHIN_XFER_COMP: | |
221 | case GRXSTS_PKTSTS_DATATOGGLEERR: | |
222 | case GRXSTS_PKTSTS_HCHHALTED: | |
223 | /* Handled in interrupt, just ignore data */ | |
224 | break; | |
225 | default: | |
226 | dev_err(hsotg->dev, | |
227 | "RxFIFO Level Interrupt: Unknown status %d\n", pktsts); | |
228 | break; | |
229 | } | |
230 | } | |
231 | ||
232 | /* | |
233 | * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More | |
234 | * data packets may be written to the FIFO for OUT transfers. More requests | |
235 | * may be written to the non-periodic request queue for IN transfers. This | |
236 | * interrupt is enabled only in Slave mode. | |
237 | */ | |
238 | static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg) | |
239 | { | |
240 | dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n"); | |
241 | dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC); | |
242 | } | |
243 | ||
244 | /* | |
245 | * This interrupt occurs when the periodic Tx FIFO is half-empty. More data | |
246 | * packets may be written to the FIFO for OUT transfers. More requests may be | |
247 | * written to the periodic request queue for IN transfers. This interrupt is | |
248 | * enabled only in Slave mode. | |
249 | */ | |
250 | static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg) | |
251 | { | |
b49977a6 MK |
252 | if (dbg_perio()) |
253 | dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n"); | |
7359d482 PZ |
254 | dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC); |
255 | } | |
256 | ||
257 | static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, | |
258 | u32 *hprt0_modify) | |
259 | { | |
bea8e86c | 260 | struct dwc2_core_params *params = &hsotg->params; |
7359d482 PZ |
261 | int do_reset = 0; |
262 | u32 usbcfg; | |
263 | u32 prtspd; | |
264 | u32 hcfg; | |
bcc5defa | 265 | u32 fslspclksel; |
7359d482 PZ |
266 | u32 hfir; |
267 | ||
268 | dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); | |
269 | ||
270 | /* Every time when port enables calculate HFIR.FrInterval */ | |
95c8bc36 | 271 | hfir = dwc2_readl(hsotg->regs + HFIR); |
7359d482 PZ |
272 | hfir &= ~HFIR_FRINT_MASK; |
273 | hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT & | |
274 | HFIR_FRINT_MASK; | |
95c8bc36 | 275 | dwc2_writel(hfir, hsotg->regs + HFIR); |
7359d482 PZ |
276 | |
277 | /* Check if we need to adjust the PHY clock speed for low power */ | |
278 | if (!params->host_support_fs_ls_low_power) { | |
279 | /* Port has been enabled, set the reset change flag */ | |
280 | hsotg->flags.b.port_reset_change = 1; | |
281 | return; | |
282 | } | |
283 | ||
95c8bc36 | 284 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); |
f9234633 | 285 | prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; |
7359d482 PZ |
286 | |
287 | if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) { | |
288 | /* Low power */ | |
289 | if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) { | |
290 | /* Set PHY low power clock select for FS/LS devices */ | |
291 | usbcfg |= GUSBCFG_PHY_LP_CLK_SEL; | |
95c8bc36 | 292 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); |
7359d482 PZ |
293 | do_reset = 1; |
294 | } | |
295 | ||
95c8bc36 | 296 | hcfg = dwc2_readl(hsotg->regs + HCFG); |
f9234633 MK |
297 | fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >> |
298 | HCFG_FSLSPCLKSEL_SHIFT; | |
7359d482 PZ |
299 | |
300 | if (prtspd == HPRT0_SPD_LOW_SPEED && | |
95832c00 | 301 | params->host_ls_low_power_phy_clk) { |
7359d482 PZ |
302 | /* 6 MHZ */ |
303 | dev_vdbg(hsotg->dev, | |
304 | "FS_PHY programming HCFG to 6 MHz\n"); | |
bcc5defa | 305 | if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) { |
f9234633 | 306 | fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ; |
7359d482 | 307 | hcfg &= ~HCFG_FSLSPCLKSEL_MASK; |
f9234633 | 308 | hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; |
95c8bc36 | 309 | dwc2_writel(hcfg, hsotg->regs + HCFG); |
7359d482 PZ |
310 | do_reset = 1; |
311 | } | |
312 | } else { | |
313 | /* 48 MHZ */ | |
314 | dev_vdbg(hsotg->dev, | |
315 | "FS_PHY programming HCFG to 48 MHz\n"); | |
bcc5defa | 316 | if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) { |
f9234633 | 317 | fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ; |
7359d482 | 318 | hcfg &= ~HCFG_FSLSPCLKSEL_MASK; |
f9234633 | 319 | hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; |
95c8bc36 | 320 | dwc2_writel(hcfg, hsotg->regs + HCFG); |
7359d482 PZ |
321 | do_reset = 1; |
322 | } | |
323 | } | |
324 | } else { | |
325 | /* Not low power */ | |
326 | if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) { | |
327 | usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL; | |
95c8bc36 | 328 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); |
7359d482 PZ |
329 | do_reset = 1; |
330 | } | |
331 | } | |
332 | ||
333 | if (do_reset) { | |
334 | *hprt0_modify |= HPRT0_RST; | |
29539019 | 335 | dwc2_writel(*hprt0_modify, hsotg->regs + HPRT0); |
7359d482 PZ |
336 | queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work, |
337 | msecs_to_jiffies(60)); | |
338 | } else { | |
339 | /* Port has been enabled, set the reset change flag */ | |
340 | hsotg->flags.b.port_reset_change = 1; | |
341 | } | |
342 | } | |
343 | ||
344 | /* | |
345 | * There are multiple conditions that can cause a port interrupt. This function | |
346 | * determines which interrupt conditions have occurred and handles them | |
347 | * appropriately. | |
348 | */ | |
349 | static void dwc2_port_intr(struct dwc2_hsotg *hsotg) | |
350 | { | |
351 | u32 hprt0; | |
352 | u32 hprt0_modify; | |
353 | ||
354 | dev_vdbg(hsotg->dev, "--Port Interrupt--\n"); | |
355 | ||
95c8bc36 | 356 | hprt0 = dwc2_readl(hsotg->regs + HPRT0); |
7359d482 PZ |
357 | hprt0_modify = hprt0; |
358 | ||
359 | /* | |
360 | * Clear appropriate bits in HPRT0 to clear the interrupt bit in | |
361 | * GINTSTS | |
362 | */ | |
363 | hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | | |
364 | HPRT0_OVRCURRCHG); | |
365 | ||
366 | /* | |
367 | * Port Connect Detected | |
368 | * Set flag and clear if detected | |
369 | */ | |
370 | if (hprt0 & HPRT0_CONNDET) { | |
29539019 DA |
371 | dwc2_writel(hprt0_modify | HPRT0_CONNDET, hsotg->regs + HPRT0); |
372 | ||
7359d482 PZ |
373 | dev_vdbg(hsotg->dev, |
374 | "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n", | |
375 | hprt0); | |
6a659531 | 376 | dwc2_hcd_connect(hsotg); |
7359d482 PZ |
377 | |
378 | /* | |
379 | * The Hub driver asserts a reset when it sees port connect | |
380 | * status change flag | |
381 | */ | |
382 | } | |
383 | ||
384 | /* | |
385 | * Port Enable Changed | |
386 | * Clear if detected - Set internal flag if disabled | |
387 | */ | |
388 | if (hprt0 & HPRT0_ENACHG) { | |
29539019 | 389 | dwc2_writel(hprt0_modify | HPRT0_ENACHG, hsotg->regs + HPRT0); |
7359d482 PZ |
390 | dev_vdbg(hsotg->dev, |
391 | " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n", | |
392 | hprt0, !!(hprt0 & HPRT0_ENA)); | |
fbb9e22b MYK |
393 | if (hprt0 & HPRT0_ENA) { |
394 | hsotg->new_connection = true; | |
7359d482 | 395 | dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify); |
fbb9e22b | 396 | } else { |
7359d482 | 397 | hsotg->flags.b.port_enable_change = 1; |
bea8e86c | 398 | if (hsotg->params.dma_desc_fs_enable) { |
fbb9e22b MYK |
399 | u32 hcfg; |
400 | ||
95832c00 | 401 | hsotg->params.dma_desc_enable = false; |
fbb9e22b MYK |
402 | hsotg->new_connection = false; |
403 | hcfg = dwc2_readl(hsotg->regs + HCFG); | |
404 | hcfg &= ~HCFG_DESCDMA; | |
405 | dwc2_writel(hcfg, hsotg->regs + HCFG); | |
406 | } | |
407 | } | |
7359d482 PZ |
408 | } |
409 | ||
410 | /* Overcurrent Change Interrupt */ | |
411 | if (hprt0 & HPRT0_OVRCURRCHG) { | |
29539019 DA |
412 | dwc2_writel(hprt0_modify | HPRT0_OVRCURRCHG, |
413 | hsotg->regs + HPRT0); | |
7359d482 PZ |
414 | dev_vdbg(hsotg->dev, |
415 | " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n", | |
416 | hprt0); | |
417 | hsotg->flags.b.port_over_current_change = 1; | |
7359d482 | 418 | } |
7359d482 PZ |
419 | } |
420 | ||
421 | /* | |
422 | * Gets the actual length of a transfer after the transfer halts. halt_status | |
423 | * holds the reason for the halt. | |
424 | * | |
425 | * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read | |
426 | * is set to 1 upon return if less than the requested number of bytes were | |
427 | * transferred. short_read may also be NULL on entry, in which case it remains | |
428 | * unchanged. | |
429 | */ | |
430 | static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg, | |
431 | struct dwc2_host_chan *chan, int chnum, | |
432 | struct dwc2_qtd *qtd, | |
433 | enum dwc2_halt_status halt_status, | |
434 | int *short_read) | |
435 | { | |
436 | u32 hctsiz, count, length; | |
437 | ||
95c8bc36 | 438 | hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); |
7359d482 PZ |
439 | |
440 | if (halt_status == DWC2_HC_XFER_COMPLETE) { | |
441 | if (chan->ep_is_in) { | |
d6ec53e0 MK |
442 | count = (hctsiz & TSIZ_XFERSIZE_MASK) >> |
443 | TSIZ_XFERSIZE_SHIFT; | |
7359d482 | 444 | length = chan->xfer_len - count; |
9da51974 | 445 | if (short_read) |
7359d482 PZ |
446 | *short_read = (count != 0); |
447 | } else if (chan->qh->do_split) { | |
448 | length = qtd->ssplit_out_xfer_count; | |
449 | } else { | |
450 | length = chan->xfer_len; | |
451 | } | |
452 | } else { | |
453 | /* | |
454 | * Must use the hctsiz.pktcnt field to determine how much data | |
455 | * has been transferred. This field reflects the number of | |
456 | * packets that have been transferred via the USB. This is | |
457 | * always an integral number of packets if the transfer was | |
458 | * halted before its normal completion. (Can't use the | |
459 | * hctsiz.xfersize field because that reflects the number of | |
460 | * bytes transferred via the AHB, not the USB). | |
461 | */ | |
d6ec53e0 | 462 | count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT; |
7359d482 PZ |
463 | length = (chan->start_pkt_count - count) * chan->max_packet; |
464 | } | |
465 | ||
466 | return length; | |
467 | } | |
468 | ||
469 | /** | |
470 | * dwc2_update_urb_state() - Updates the state of the URB after a Transfer | |
471 | * Complete interrupt on the host channel. Updates the actual_length field | |
472 | * of the URB based on the number of bytes transferred via the host channel. | |
473 | * Sets the URB status if the data transfer is finished. | |
474 | * | |
475 | * Return: 1 if the data transfer specified by the URB is completely finished, | |
476 | * 0 otherwise | |
477 | */ | |
478 | static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg, | |
479 | struct dwc2_host_chan *chan, int chnum, | |
480 | struct dwc2_hcd_urb *urb, | |
481 | struct dwc2_qtd *qtd) | |
482 | { | |
483 | u32 hctsiz; | |
484 | int xfer_done = 0; | |
485 | int short_read = 0; | |
486 | int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd, | |
487 | DWC2_HC_XFER_COMPLETE, | |
488 | &short_read); | |
489 | ||
490 | if (urb->actual_length + xfer_length > urb->length) { | |
491 | dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__); | |
492 | xfer_length = urb->length - urb->actual_length; | |
493 | } | |
494 | ||
7359d482 PZ |
495 | dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n", |
496 | urb->actual_length, xfer_length); | |
497 | urb->actual_length += xfer_length; | |
498 | ||
499 | if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK && | |
500 | (urb->flags & URB_SEND_ZERO_PACKET) && | |
501 | urb->actual_length >= urb->length && | |
502 | !(urb->length % chan->max_packet)) { | |
503 | xfer_done = 0; | |
504 | } else if (short_read || urb->actual_length >= urb->length) { | |
505 | xfer_done = 1; | |
506 | urb->status = 0; | |
507 | } | |
508 | ||
95c8bc36 | 509 | hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); |
7359d482 PZ |
510 | dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", |
511 | __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); | |
512 | dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len); | |
513 | dev_vdbg(hsotg->dev, " hctsiz.xfersize %d\n", | |
d6ec53e0 | 514 | (hctsiz & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT); |
7359d482 PZ |
515 | dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", urb->length); |
516 | dev_vdbg(hsotg->dev, " urb->actual_length %d\n", urb->actual_length); | |
517 | dev_vdbg(hsotg->dev, " short_read %d, xfer_done %d\n", short_read, | |
518 | xfer_done); | |
519 | ||
520 | return xfer_done; | |
521 | } | |
522 | ||
523 | /* | |
524 | * Save the starting data toggle for the next transfer. The data toggle is | |
525 | * saved in the QH for non-control transfers and it's saved in the QTD for | |
526 | * control transfers. | |
527 | */ | |
528 | void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, | |
529 | struct dwc2_host_chan *chan, int chnum, | |
530 | struct dwc2_qtd *qtd) | |
531 | { | |
95c8bc36 | 532 | u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); |
f9234633 | 533 | u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT; |
7359d482 PZ |
534 | |
535 | if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) { | |
62943b7d TJ |
536 | if (WARN(!chan || !chan->qh, |
537 | "chan->qh must be specified for non-control eps\n")) | |
538 | return; | |
539 | ||
7359d482 PZ |
540 | if (pid == TSIZ_SC_MC_PID_DATA0) |
541 | chan->qh->data_toggle = DWC2_HC_PID_DATA0; | |
542 | else | |
543 | chan->qh->data_toggle = DWC2_HC_PID_DATA1; | |
544 | } else { | |
62943b7d TJ |
545 | if (WARN(!qtd, |
546 | "qtd must be specified for control eps\n")) | |
547 | return; | |
548 | ||
7359d482 PZ |
549 | if (pid == TSIZ_SC_MC_PID_DATA0) |
550 | qtd->data_toggle = DWC2_HC_PID_DATA0; | |
551 | else | |
552 | qtd->data_toggle = DWC2_HC_PID_DATA1; | |
553 | } | |
554 | } | |
555 | ||
556 | /** | |
557 | * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when | |
558 | * the transfer is stopped for any reason. The fields of the current entry in | |
559 | * the frame descriptor array are set based on the transfer state and the input | |
560 | * halt_status. Completes the Isochronous URB if all the URB frames have been | |
561 | * completed. | |
562 | * | |
563 | * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be | |
564 | * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE. | |
565 | */ | |
566 | static enum dwc2_halt_status dwc2_update_isoc_urb_state( | |
567 | struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, | |
568 | int chnum, struct dwc2_qtd *qtd, | |
569 | enum dwc2_halt_status halt_status) | |
570 | { | |
571 | struct dwc2_hcd_iso_packet_desc *frame_desc; | |
572 | struct dwc2_hcd_urb *urb = qtd->urb; | |
573 | ||
574 | if (!urb) | |
575 | return DWC2_HC_XFER_NO_HALT_STATUS; | |
576 | ||
577 | frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; | |
578 | ||
579 | switch (halt_status) { | |
580 | case DWC2_HC_XFER_COMPLETE: | |
581 | frame_desc->status = 0; | |
582 | frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg, | |
583 | chan, chnum, qtd, halt_status, NULL); | |
7359d482 PZ |
584 | break; |
585 | case DWC2_HC_XFER_FRAME_OVERRUN: | |
586 | urb->error_count++; | |
587 | if (chan->ep_is_in) | |
588 | frame_desc->status = -ENOSR; | |
589 | else | |
590 | frame_desc->status = -ECOMM; | |
591 | frame_desc->actual_length = 0; | |
592 | break; | |
593 | case DWC2_HC_XFER_BABBLE_ERR: | |
594 | urb->error_count++; | |
595 | frame_desc->status = -EOVERFLOW; | |
596 | /* Don't need to update actual_length in this case */ | |
597 | break; | |
598 | case DWC2_HC_XFER_XACT_ERR: | |
599 | urb->error_count++; | |
600 | frame_desc->status = -EPROTO; | |
601 | frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg, | |
602 | chan, chnum, qtd, halt_status, NULL); | |
603 | ||
7359d482 PZ |
604 | /* Skip whole frame */ |
605 | if (chan->qh->do_split && | |
606 | chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in && | |
95832c00 | 607 | hsotg->params.host_dma) { |
7359d482 PZ |
608 | qtd->complete_split = 0; |
609 | qtd->isoc_split_offset = 0; | |
610 | } | |
611 | ||
612 | break; | |
613 | default: | |
614 | dev_err(hsotg->dev, "Unhandled halt_status (%d)\n", | |
615 | halt_status); | |
616 | break; | |
617 | } | |
618 | ||
619 | if (++qtd->isoc_frame_index == urb->packet_count) { | |
620 | /* | |
621 | * urb->status is not used for isoc transfers. The individual | |
622 | * frame_desc statuses are used instead. | |
623 | */ | |
0d012b98 | 624 | dwc2_host_complete(hsotg, qtd, 0); |
7359d482 PZ |
625 | halt_status = DWC2_HC_XFER_URB_COMPLETE; |
626 | } else { | |
627 | halt_status = DWC2_HC_XFER_COMPLETE; | |
628 | } | |
629 | ||
630 | return halt_status; | |
631 | } | |
632 | ||
633 | /* | |
634 | * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic | |
635 | * QHs, removes the QH from the active non-periodic schedule. If any QTDs are | |
636 | * still linked to the QH, the QH is added to the end of the inactive | |
637 | * non-periodic schedule. For periodic QHs, removes the QH from the periodic | |
638 | * schedule if no more QTDs are linked to the QH. | |
639 | */ | |
640 | static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, | |
641 | int free_qtd) | |
642 | { | |
643 | int continue_split = 0; | |
644 | struct dwc2_qtd *qtd; | |
645 | ||
b49977a6 MK |
646 | if (dbg_qh(qh)) |
647 | dev_vdbg(hsotg->dev, " %s(%p,%p,%d)\n", __func__, | |
648 | hsotg, qh, free_qtd); | |
7359d482 PZ |
649 | |
650 | if (list_empty(&qh->qtd_list)) { | |
651 | dev_dbg(hsotg->dev, "## QTD list empty ##\n"); | |
652 | goto no_qtd; | |
653 | } | |
654 | ||
655 | qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); | |
656 | ||
657 | if (qtd->complete_split) | |
658 | continue_split = 1; | |
659 | else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID || | |
660 | qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END) | |
661 | continue_split = 1; | |
662 | ||
663 | if (free_qtd) { | |
664 | dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); | |
665 | continue_split = 0; | |
666 | } | |
667 | ||
668 | no_qtd: | |
7359d482 PZ |
669 | qh->channel = NULL; |
670 | dwc2_hcd_qh_deactivate(hsotg, qh, continue_split); | |
671 | } | |
672 | ||
673 | /** | |
674 | * dwc2_release_channel() - Releases a host channel for use by other transfers | |
675 | * | |
676 | * @hsotg: The HCD state structure | |
677 | * @chan: The host channel to release | |
678 | * @qtd: The QTD associated with the host channel. This QTD may be | |
679 | * freed if the transfer is complete or an error has occurred. | |
680 | * @halt_status: Reason the channel is being released. This status | |
681 | * determines the actions taken by this function. | |
682 | * | |
683 | * Also attempts to select and queue more transactions since at least one host | |
684 | * channel is available. | |
685 | */ | |
686 | static void dwc2_release_channel(struct dwc2_hsotg *hsotg, | |
687 | struct dwc2_host_chan *chan, | |
688 | struct dwc2_qtd *qtd, | |
689 | enum dwc2_halt_status halt_status) | |
690 | { | |
691 | enum dwc2_transaction_type tr_type; | |
692 | u32 haintmsk; | |
693 | int free_qtd = 0; | |
694 | ||
b49977a6 MK |
695 | if (dbg_hc(chan)) |
696 | dev_vdbg(hsotg->dev, " %s: channel %d, halt_status %d\n", | |
697 | __func__, chan->hc_num, halt_status); | |
7359d482 PZ |
698 | |
699 | switch (halt_status) { | |
700 | case DWC2_HC_XFER_URB_COMPLETE: | |
701 | free_qtd = 1; | |
702 | break; | |
703 | case DWC2_HC_XFER_AHB_ERR: | |
704 | case DWC2_HC_XFER_STALL: | |
705 | case DWC2_HC_XFER_BABBLE_ERR: | |
706 | free_qtd = 1; | |
707 | break; | |
708 | case DWC2_HC_XFER_XACT_ERR: | |
8509f2f4 | 709 | if (qtd && qtd->error_count >= 3) { |
7359d482 PZ |
710 | dev_vdbg(hsotg->dev, |
711 | " Complete URB with transaction error\n"); | |
712 | free_qtd = 1; | |
0d012b98 | 713 | dwc2_host_complete(hsotg, qtd, -EPROTO); |
7359d482 PZ |
714 | } |
715 | break; | |
716 | case DWC2_HC_XFER_URB_DEQUEUE: | |
717 | /* | |
718 | * The QTD has already been removed and the QH has been | |
719 | * deactivated. Don't want to do anything except release the | |
720 | * host channel and try to queue more transfers. | |
721 | */ | |
722 | goto cleanup; | |
723 | case DWC2_HC_XFER_PERIODIC_INCOMPLETE: | |
724 | dev_vdbg(hsotg->dev, " Complete URB with I/O error\n"); | |
725 | free_qtd = 1; | |
0d012b98 | 726 | dwc2_host_complete(hsotg, qtd, -EIO); |
7359d482 PZ |
727 | break; |
728 | case DWC2_HC_XFER_NO_HALT_STATUS: | |
729 | default: | |
730 | break; | |
731 | } | |
732 | ||
733 | dwc2_deactivate_qh(hsotg, chan->qh, free_qtd); | |
734 | ||
735 | cleanup: | |
736 | /* | |
737 | * Release the host channel for use by other transfers. The cleanup | |
738 | * function clears the channel interrupt enables and conditions, so | |
739 | * there's no need to clear the Channel Halted interrupt separately. | |
740 | */ | |
741 | if (!list_empty(&chan->hc_list_entry)) | |
742 | list_del(&chan->hc_list_entry); | |
743 | dwc2_hc_cleanup(hsotg, chan); | |
744 | list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); | |
745 | ||
95832c00 | 746 | if (hsotg->params.uframe_sched) { |
20f2eb9c DC |
747 | hsotg->available_host_channels++; |
748 | } else { | |
749 | switch (chan->ep_type) { | |
750 | case USB_ENDPOINT_XFER_CONTROL: | |
751 | case USB_ENDPOINT_XFER_BULK: | |
752 | hsotg->non_periodic_channels--; | |
753 | break; | |
754 | default: | |
755 | /* | |
756 | * Don't release reservations for periodic channels | |
757 | * here. That's done when a periodic transfer is | |
758 | * descheduled (i.e. when the QH is removed from the | |
759 | * periodic schedule). | |
760 | */ | |
761 | break; | |
762 | } | |
7359d482 PZ |
763 | } |
764 | ||
95c8bc36 | 765 | haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); |
7359d482 | 766 | haintmsk &= ~(1 << chan->hc_num); |
95c8bc36 | 767 | dwc2_writel(haintmsk, hsotg->regs + HAINTMSK); |
7359d482 PZ |
768 | |
769 | /* Try to queue more transfers now that there's a free channel */ | |
770 | tr_type = dwc2_hcd_select_transactions(hsotg); | |
771 | if (tr_type != DWC2_TRANSACTION_NONE) | |
772 | dwc2_hcd_queue_transactions(hsotg, tr_type); | |
773 | } | |
774 | ||
775 | /* | |
776 | * Halts a host channel. If the channel cannot be halted immediately because | |
777 | * the request queue is full, this function ensures that the FIFO empty | |
778 | * interrupt for the appropriate queue is enabled so that the halt request can | |
779 | * be queued when there is space in the request queue. | |
780 | * | |
781 | * This function may also be called in DMA mode. In that case, the channel is | |
782 | * simply released since the core always halts the channel automatically in | |
783 | * DMA mode. | |
784 | */ | |
785 | static void dwc2_halt_channel(struct dwc2_hsotg *hsotg, | |
786 | struct dwc2_host_chan *chan, struct dwc2_qtd *qtd, | |
787 | enum dwc2_halt_status halt_status) | |
788 | { | |
b49977a6 MK |
789 | if (dbg_hc(chan)) |
790 | dev_vdbg(hsotg->dev, "%s()\n", __func__); | |
7359d482 | 791 | |
95832c00 | 792 | if (hsotg->params.host_dma) { |
b49977a6 MK |
793 | if (dbg_hc(chan)) |
794 | dev_vdbg(hsotg->dev, "DMA enabled\n"); | |
7359d482 PZ |
795 | dwc2_release_channel(hsotg, chan, qtd, halt_status); |
796 | return; | |
797 | } | |
798 | ||
799 | /* Slave mode processing */ | |
800 | dwc2_hc_halt(hsotg, chan, halt_status); | |
801 | ||
802 | if (chan->halt_on_queue) { | |
803 | u32 gintmsk; | |
804 | ||
805 | dev_vdbg(hsotg->dev, "Halt on queue\n"); | |
806 | if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || | |
807 | chan->ep_type == USB_ENDPOINT_XFER_BULK) { | |
808 | dev_vdbg(hsotg->dev, "control/bulk\n"); | |
809 | /* | |
810 | * Make sure the Non-periodic Tx FIFO empty interrupt | |
811 | * is enabled so that the non-periodic schedule will | |
812 | * be processed | |
813 | */ | |
95c8bc36 | 814 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
7359d482 | 815 | gintmsk |= GINTSTS_NPTXFEMP; |
95c8bc36 | 816 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); |
7359d482 PZ |
817 | } else { |
818 | dev_vdbg(hsotg->dev, "isoc/intr\n"); | |
819 | /* | |
820 | * Move the QH from the periodic queued schedule to | |
821 | * the periodic assigned schedule. This allows the | |
822 | * halt to be queued when the periodic schedule is | |
823 | * processed. | |
824 | */ | |
94ef7aee | 825 | list_move_tail(&chan->qh->qh_list_entry, |
9da51974 | 826 | &hsotg->periodic_sched_assigned); |
7359d482 PZ |
827 | |
828 | /* | |
829 | * Make sure the Periodic Tx FIFO Empty interrupt is | |
830 | * enabled so that the periodic schedule will be | |
831 | * processed | |
832 | */ | |
95c8bc36 | 833 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
7359d482 | 834 | gintmsk |= GINTSTS_PTXFEMP; |
95c8bc36 | 835 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); |
7359d482 PZ |
836 | } |
837 | } | |
838 | } | |
839 | ||
840 | /* | |
841 | * Performs common cleanup for non-periodic transfers after a Transfer | |
842 | * Complete interrupt. This function should be called after any endpoint type | |
843 | * specific handling is finished to release the host channel. | |
844 | */ | |
845 | static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg, | |
846 | struct dwc2_host_chan *chan, | |
847 | int chnum, struct dwc2_qtd *qtd, | |
848 | enum dwc2_halt_status halt_status) | |
849 | { | |
850 | dev_vdbg(hsotg->dev, "%s()\n", __func__); | |
851 | ||
852 | qtd->error_count = 0; | |
853 | ||
854 | if (chan->hcint & HCINTMSK_NYET) { | |
855 | /* | |
856 | * Got a NYET on the last transaction of the transfer. This | |
857 | * means that the endpoint should be in the PING state at the | |
858 | * beginning of the next transfer. | |
859 | */ | |
860 | dev_vdbg(hsotg->dev, "got NYET\n"); | |
861 | chan->qh->ping_state = 1; | |
862 | } | |
863 | ||
864 | /* | |
865 | * Always halt and release the host channel to make it available for | |
866 | * more transfers. There may still be more phases for a control | |
867 | * transfer or more data packets for a bulk transfer at this point, | |
868 | * but the host channel is still halted. A channel will be reassigned | |
869 | * to the transfer when the non-periodic schedule is processed after | |
870 | * the channel is released. This allows transactions to be queued | |
871 | * properly via dwc2_hcd_queue_transactions, which also enables the | |
872 | * Tx FIFO Empty interrupt if necessary. | |
873 | */ | |
874 | if (chan->ep_is_in) { | |
875 | /* | |
876 | * IN transfers in Slave mode require an explicit disable to | |
877 | * halt the channel. (In DMA mode, this call simply releases | |
878 | * the channel.) | |
879 | */ | |
880 | dwc2_halt_channel(hsotg, chan, qtd, halt_status); | |
881 | } else { | |
882 | /* | |
883 | * The channel is automatically disabled by the core for OUT | |
884 | * transfers in Slave mode | |
885 | */ | |
886 | dwc2_release_channel(hsotg, chan, qtd, halt_status); | |
887 | } | |
888 | } | |
889 | ||
890 | /* | |
891 | * Performs common cleanup for periodic transfers after a Transfer Complete | |
892 | * interrupt. This function should be called after any endpoint type specific | |
893 | * handling is finished to release the host channel. | |
894 | */ | |
895 | static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg, | |
896 | struct dwc2_host_chan *chan, int chnum, | |
897 | struct dwc2_qtd *qtd, | |
898 | enum dwc2_halt_status halt_status) | |
899 | { | |
95c8bc36 | 900 | u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); |
7359d482 PZ |
901 | |
902 | qtd->error_count = 0; | |
903 | ||
904 | if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0) | |
905 | /* Core halts channel in these cases */ | |
906 | dwc2_release_channel(hsotg, chan, qtd, halt_status); | |
907 | else | |
908 | /* Flush any outstanding requests from the Tx queue */ | |
909 | dwc2_halt_channel(hsotg, chan, qtd, halt_status); | |
910 | } | |
911 | ||
912 | static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg, | |
913 | struct dwc2_host_chan *chan, int chnum, | |
914 | struct dwc2_qtd *qtd) | |
915 | { | |
916 | struct dwc2_hcd_iso_packet_desc *frame_desc; | |
917 | u32 len; | |
9d8da857 SA |
918 | u32 hctsiz; |
919 | u32 pid; | |
7359d482 PZ |
920 | |
921 | if (!qtd->urb) | |
922 | return 0; | |
923 | ||
924 | frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; | |
925 | len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd, | |
926 | DWC2_HC_XFER_COMPLETE, NULL); | |
927 | if (!len) { | |
928 | qtd->complete_split = 0; | |
929 | qtd->isoc_split_offset = 0; | |
930 | return 0; | |
931 | } | |
932 | ||
933 | frame_desc->actual_length += len; | |
934 | ||
7359d482 PZ |
935 | qtd->isoc_split_offset += len; |
936 | ||
9d8da857 SA |
937 | hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); |
938 | pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT; | |
939 | ||
940 | if (frame_desc->actual_length >= frame_desc->length || pid == 0) { | |
7359d482 PZ |
941 | frame_desc->status = 0; |
942 | qtd->isoc_frame_index++; | |
943 | qtd->complete_split = 0; | |
944 | qtd->isoc_split_offset = 0; | |
945 | } | |
946 | ||
947 | if (qtd->isoc_frame_index == qtd->urb->packet_count) { | |
0d012b98 | 948 | dwc2_host_complete(hsotg, qtd, 0); |
7359d482 PZ |
949 | dwc2_release_channel(hsotg, chan, qtd, |
950 | DWC2_HC_XFER_URB_COMPLETE); | |
951 | } else { | |
952 | dwc2_release_channel(hsotg, chan, qtd, | |
953 | DWC2_HC_XFER_NO_HALT_STATUS); | |
954 | } | |
955 | ||
956 | return 1; /* Indicates that channel released */ | |
957 | } | |
958 | ||
959 | /* | |
960 | * Handles a host channel Transfer Complete interrupt. This handler may be | |
961 | * called in either DMA mode or Slave mode. | |
962 | */ | |
963 | static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg, | |
964 | struct dwc2_host_chan *chan, int chnum, | |
965 | struct dwc2_qtd *qtd) | |
966 | { | |
967 | struct dwc2_hcd_urb *urb = qtd->urb; | |
7359d482 | 968 | enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE; |
2b54fa6b | 969 | int pipe_type; |
7359d482 PZ |
970 | int urb_xfer_done; |
971 | ||
b49977a6 MK |
972 | if (dbg_hc(chan)) |
973 | dev_vdbg(hsotg->dev, | |
974 | "--Host Channel %d Interrupt: Transfer Complete--\n", | |
975 | chnum); | |
7359d482 | 976 | |
2b54fa6b PZ |
977 | if (!urb) |
978 | goto handle_xfercomp_done; | |
979 | ||
980 | pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); | |
981 | ||
95832c00 | 982 | if (hsotg->params.dma_desc_enable) { |
7359d482 PZ |
983 | dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status); |
984 | if (pipe_type == USB_ENDPOINT_XFER_ISOC) | |
985 | /* Do not disable the interrupt, just clear it */ | |
986 | return; | |
987 | goto handle_xfercomp_done; | |
988 | } | |
989 | ||
990 | /* Handle xfer complete on CSPLIT */ | |
991 | if (chan->qh->do_split) { | |
992 | if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in && | |
95832c00 | 993 | hsotg->params.host_dma) { |
7359d482 PZ |
994 | if (qtd->complete_split && |
995 | dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum, | |
996 | qtd)) | |
997 | goto handle_xfercomp_done; | |
998 | } else { | |
999 | qtd->complete_split = 0; | |
1000 | } | |
1001 | } | |
1002 | ||
7359d482 PZ |
1003 | /* Update the QTD and URB states */ |
1004 | switch (pipe_type) { | |
1005 | case USB_ENDPOINT_XFER_CONTROL: | |
1006 | switch (qtd->control_phase) { | |
1007 | case DWC2_CONTROL_SETUP: | |
1008 | if (urb->length > 0) | |
1009 | qtd->control_phase = DWC2_CONTROL_DATA; | |
1010 | else | |
1011 | qtd->control_phase = DWC2_CONTROL_STATUS; | |
1012 | dev_vdbg(hsotg->dev, | |
1013 | " Control setup transaction done\n"); | |
1014 | halt_status = DWC2_HC_XFER_COMPLETE; | |
1015 | break; | |
1016 | case DWC2_CONTROL_DATA: | |
1017 | urb_xfer_done = dwc2_update_urb_state(hsotg, chan, | |
1018 | chnum, urb, qtd); | |
1019 | if (urb_xfer_done) { | |
1020 | qtd->control_phase = DWC2_CONTROL_STATUS; | |
1021 | dev_vdbg(hsotg->dev, | |
1022 | " Control data transfer done\n"); | |
1023 | } else { | |
1024 | dwc2_hcd_save_data_toggle(hsotg, chan, chnum, | |
1025 | qtd); | |
1026 | } | |
1027 | halt_status = DWC2_HC_XFER_COMPLETE; | |
1028 | break; | |
1029 | case DWC2_CONTROL_STATUS: | |
1030 | dev_vdbg(hsotg->dev, " Control transfer complete\n"); | |
1031 | if (urb->status == -EINPROGRESS) | |
1032 | urb->status = 0; | |
0d012b98 | 1033 | dwc2_host_complete(hsotg, qtd, urb->status); |
7359d482 PZ |
1034 | halt_status = DWC2_HC_XFER_URB_COMPLETE; |
1035 | break; | |
1036 | } | |
1037 | ||
1038 | dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd, | |
1039 | halt_status); | |
1040 | break; | |
1041 | case USB_ENDPOINT_XFER_BULK: | |
1042 | dev_vdbg(hsotg->dev, " Bulk transfer complete\n"); | |
1043 | urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb, | |
1044 | qtd); | |
1045 | if (urb_xfer_done) { | |
0d012b98 | 1046 | dwc2_host_complete(hsotg, qtd, urb->status); |
7359d482 PZ |
1047 | halt_status = DWC2_HC_XFER_URB_COMPLETE; |
1048 | } else { | |
1049 | halt_status = DWC2_HC_XFER_COMPLETE; | |
1050 | } | |
1051 | ||
1052 | dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); | |
1053 | dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd, | |
1054 | halt_status); | |
1055 | break; | |
1056 | case USB_ENDPOINT_XFER_INT: | |
1057 | dev_vdbg(hsotg->dev, " Interrupt transfer complete\n"); | |
1058 | urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb, | |
1059 | qtd); | |
1060 | ||
1061 | /* | |
1062 | * Interrupt URB is done on the first transfer complete | |
1063 | * interrupt | |
1064 | */ | |
1065 | if (urb_xfer_done) { | |
0d012b98 PZ |
1066 | dwc2_host_complete(hsotg, qtd, urb->status); |
1067 | halt_status = DWC2_HC_XFER_URB_COMPLETE; | |
7359d482 | 1068 | } else { |
0d012b98 | 1069 | halt_status = DWC2_HC_XFER_COMPLETE; |
7359d482 PZ |
1070 | } |
1071 | ||
1072 | dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); | |
1073 | dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd, | |
1074 | halt_status); | |
1075 | break; | |
1076 | case USB_ENDPOINT_XFER_ISOC: | |
b49977a6 MK |
1077 | if (dbg_perio()) |
1078 | dev_vdbg(hsotg->dev, " Isochronous transfer complete\n"); | |
7359d482 PZ |
1079 | if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL) |
1080 | halt_status = dwc2_update_isoc_urb_state(hsotg, chan, | |
b98866c2 JY |
1081 | chnum, qtd, |
1082 | DWC2_HC_XFER_COMPLETE); | |
7359d482 PZ |
1083 | dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd, |
1084 | halt_status); | |
1085 | break; | |
1086 | } | |
1087 | ||
1088 | handle_xfercomp_done: | |
1089 | disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL); | |
1090 | } | |
1091 | ||
1092 | /* | |
1093 | * Handles a host channel STALL interrupt. This handler may be called in | |
1094 | * either DMA mode or Slave mode. | |
1095 | */ | |
1096 | static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg, | |
1097 | struct dwc2_host_chan *chan, int chnum, | |
1098 | struct dwc2_qtd *qtd) | |
1099 | { | |
1100 | struct dwc2_hcd_urb *urb = qtd->urb; | |
2b54fa6b | 1101 | int pipe_type; |
7359d482 PZ |
1102 | |
1103 | dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n", | |
1104 | chnum); | |
1105 | ||
95832c00 | 1106 | if (hsotg->params.dma_desc_enable) { |
7359d482 PZ |
1107 | dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, |
1108 | DWC2_HC_XFER_STALL); | |
1109 | goto handle_stall_done; | |
1110 | } | |
1111 | ||
1112 | if (!urb) | |
1113 | goto handle_stall_halt; | |
1114 | ||
2b54fa6b PZ |
1115 | pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); |
1116 | ||
7359d482 | 1117 | if (pipe_type == USB_ENDPOINT_XFER_CONTROL) |
0d012b98 | 1118 | dwc2_host_complete(hsotg, qtd, -EPIPE); |
7359d482 PZ |
1119 | |
1120 | if (pipe_type == USB_ENDPOINT_XFER_BULK || | |
1121 | pipe_type == USB_ENDPOINT_XFER_INT) { | |
0d012b98 | 1122 | dwc2_host_complete(hsotg, qtd, -EPIPE); |
7359d482 PZ |
1123 | /* |
1124 | * USB protocol requires resetting the data toggle for bulk | |
1125 | * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT) | |
1126 | * setup command is issued to the endpoint. Anticipate the | |
1127 | * CLEAR_FEATURE command since a STALL has occurred and reset | |
1128 | * the data toggle now. | |
1129 | */ | |
1130 | chan->qh->data_toggle = 0; | |
1131 | } | |
1132 | ||
1133 | handle_stall_halt: | |
1134 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL); | |
1135 | ||
1136 | handle_stall_done: | |
1137 | disable_hc_int(hsotg, chnum, HCINTMSK_STALL); | |
1138 | } | |
1139 | ||
1140 | /* | |
1141 | * Updates the state of the URB when a transfer has been stopped due to an | |
1142 | * abnormal condition before the transfer completes. Modifies the | |
1143 | * actual_length field of the URB to reflect the number of bytes that have | |
1144 | * actually been transferred via the host channel. | |
1145 | */ | |
1146 | static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg, | |
1147 | struct dwc2_host_chan *chan, int chnum, | |
1148 | struct dwc2_hcd_urb *urb, | |
1149 | struct dwc2_qtd *qtd, | |
1150 | enum dwc2_halt_status halt_status) | |
1151 | { | |
1152 | u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, | |
1153 | qtd, halt_status, NULL); | |
1154 | u32 hctsiz; | |
1155 | ||
1156 | if (urb->actual_length + xfer_length > urb->length) { | |
1157 | dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__); | |
1158 | xfer_length = urb->length - urb->actual_length; | |
1159 | } | |
1160 | ||
7359d482 PZ |
1161 | urb->actual_length += xfer_length; |
1162 | ||
95c8bc36 | 1163 | hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); |
7359d482 PZ |
1164 | dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", |
1165 | __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); | |
1166 | dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n", | |
1167 | chan->start_pkt_count); | |
1168 | dev_vdbg(hsotg->dev, " hctsiz.pktcnt %d\n", | |
d6ec53e0 | 1169 | (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT); |
7359d482 PZ |
1170 | dev_vdbg(hsotg->dev, " chan->max_packet %d\n", chan->max_packet); |
1171 | dev_vdbg(hsotg->dev, " bytes_transferred %d\n", | |
1172 | xfer_length); | |
1173 | dev_vdbg(hsotg->dev, " urb->actual_length %d\n", | |
1174 | urb->actual_length); | |
1175 | dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", | |
1176 | urb->length); | |
1177 | } | |
1178 | ||
1179 | /* | |
1180 | * Handles a host channel NAK interrupt. This handler may be called in either | |
1181 | * DMA mode or Slave mode. | |
1182 | */ | |
1183 | static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg, | |
1184 | struct dwc2_host_chan *chan, int chnum, | |
1185 | struct dwc2_qtd *qtd) | |
1186 | { | |
e499123e GH |
1187 | if (!qtd) { |
1188 | dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__); | |
1189 | return; | |
1190 | } | |
1191 | ||
1192 | if (!qtd->urb) { | |
1193 | dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__); | |
1194 | return; | |
1195 | } | |
1196 | ||
b49977a6 MK |
1197 | if (dbg_hc(chan)) |
1198 | dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n", | |
1199 | chnum); | |
7359d482 PZ |
1200 | |
1201 | /* | |
1202 | * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and | |
1203 | * interrupt. Re-start the SSPLIT transfer. | |
1204 | */ | |
1205 | if (chan->do_split) { | |
1206 | if (chan->complete_split) | |
1207 | qtd->error_count = 0; | |
1208 | qtd->complete_split = 0; | |
1209 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK); | |
1210 | goto handle_nak_done; | |
1211 | } | |
1212 | ||
1213 | switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { | |
1214 | case USB_ENDPOINT_XFER_CONTROL: | |
1215 | case USB_ENDPOINT_XFER_BULK: | |
95832c00 | 1216 | if (hsotg->params.host_dma && chan->ep_is_in) { |
7359d482 PZ |
1217 | /* |
1218 | * NAK interrupts are enabled on bulk/control IN | |
1219 | * transfers in DMA mode for the sole purpose of | |
1220 | * resetting the error count after a transaction error | |
1221 | * occurs. The core will continue transferring data. | |
1222 | */ | |
1223 | qtd->error_count = 0; | |
1224 | break; | |
1225 | } | |
1226 | ||
1227 | /* | |
1228 | * NAK interrupts normally occur during OUT transfers in DMA | |
1229 | * or Slave mode. For IN transfers, more requests will be | |
1230 | * queued as request queue space is available. | |
1231 | */ | |
1232 | qtd->error_count = 0; | |
1233 | ||
1234 | if (!chan->qh->ping_state) { | |
1235 | dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, | |
1236 | qtd, DWC2_HC_XFER_NAK); | |
1237 | dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); | |
1238 | ||
1239 | if (chan->speed == USB_SPEED_HIGH) | |
1240 | chan->qh->ping_state = 1; | |
1241 | } | |
1242 | ||
1243 | /* | |
1244 | * Halt the channel so the transfer can be re-started from | |
1245 | * the appropriate point or the PING protocol will | |
1246 | * start/continue | |
1247 | */ | |
1248 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK); | |
1249 | break; | |
1250 | case USB_ENDPOINT_XFER_INT: | |
1251 | qtd->error_count = 0; | |
1252 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK); | |
1253 | break; | |
1254 | case USB_ENDPOINT_XFER_ISOC: | |
1255 | /* Should never get called for isochronous transfers */ | |
1256 | dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n"); | |
1257 | break; | |
1258 | } | |
1259 | ||
1260 | handle_nak_done: | |
1261 | disable_hc_int(hsotg, chnum, HCINTMSK_NAK); | |
1262 | } | |
1263 | ||
1264 | /* | |
1265 | * Handles a host channel ACK interrupt. This interrupt is enabled when | |
1266 | * performing the PING protocol in Slave mode, when errors occur during | |
1267 | * either Slave mode or DMA mode, and during Start Split transactions. | |
1268 | */ | |
1269 | static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg, | |
1270 | struct dwc2_host_chan *chan, int chnum, | |
1271 | struct dwc2_qtd *qtd) | |
1272 | { | |
1273 | struct dwc2_hcd_iso_packet_desc *frame_desc; | |
1274 | ||
b49977a6 MK |
1275 | if (dbg_hc(chan)) |
1276 | dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n", | |
1277 | chnum); | |
7359d482 PZ |
1278 | |
1279 | if (chan->do_split) { | |
1280 | /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */ | |
1281 | if (!chan->ep_is_in && | |
1282 | chan->data_pid_start != DWC2_HC_PID_SETUP) | |
1283 | qtd->ssplit_out_xfer_count = chan->xfer_len; | |
1284 | ||
1285 | if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) { | |
1286 | qtd->complete_split = 1; | |
1287 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK); | |
1288 | } else { | |
1289 | /* ISOC OUT */ | |
1290 | switch (chan->xact_pos) { | |
1291 | case DWC2_HCSPLT_XACTPOS_ALL: | |
1292 | break; | |
1293 | case DWC2_HCSPLT_XACTPOS_END: | |
1294 | qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL; | |
1295 | qtd->isoc_split_offset = 0; | |
1296 | break; | |
1297 | case DWC2_HCSPLT_XACTPOS_BEGIN: | |
1298 | case DWC2_HCSPLT_XACTPOS_MID: | |
1299 | /* | |
1300 | * For BEGIN or MID, calculate the length for | |
1301 | * the next microframe to determine the correct | |
1302 | * SSPLIT token, either MID or END | |
1303 | */ | |
1304 | frame_desc = &qtd->urb->iso_descs[ | |
1305 | qtd->isoc_frame_index]; | |
1306 | qtd->isoc_split_offset += 188; | |
1307 | ||
1308 | if (frame_desc->length - qtd->isoc_split_offset | |
1309 | <= 188) | |
1310 | qtd->isoc_split_pos = | |
1311 | DWC2_HCSPLT_XACTPOS_END; | |
1312 | else | |
1313 | qtd->isoc_split_pos = | |
1314 | DWC2_HCSPLT_XACTPOS_MID; | |
1315 | break; | |
1316 | } | |
1317 | } | |
1318 | } else { | |
1319 | qtd->error_count = 0; | |
1320 | ||
1321 | if (chan->qh->ping_state) { | |
1322 | chan->qh->ping_state = 0; | |
1323 | /* | |
1324 | * Halt the channel so the transfer can be re-started | |
1325 | * from the appropriate point. This only happens in | |
1326 | * Slave mode. In DMA mode, the ping_state is cleared | |
1327 | * when the transfer is started because the core | |
1328 | * automatically executes the PING, then the transfer. | |
1329 | */ | |
1330 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK); | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | /* | |
1335 | * If the ACK occurred when _not_ in the PING state, let the channel | |
1336 | * continue transferring data after clearing the error count | |
1337 | */ | |
1338 | disable_hc_int(hsotg, chnum, HCINTMSK_ACK); | |
1339 | } | |
1340 | ||
1341 | /* | |
1342 | * Handles a host channel NYET interrupt. This interrupt should only occur on | |
1343 | * Bulk and Control OUT endpoints and for complete split transactions. If a | |
1344 | * NYET occurs at the same time as a Transfer Complete interrupt, it is | |
1345 | * handled in the xfercomp interrupt handler, not here. This handler may be | |
1346 | * called in either DMA mode or Slave mode. | |
1347 | */ | |
1348 | static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg, | |
1349 | struct dwc2_host_chan *chan, int chnum, | |
1350 | struct dwc2_qtd *qtd) | |
1351 | { | |
b49977a6 MK |
1352 | if (dbg_hc(chan)) |
1353 | dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n", | |
1354 | chnum); | |
7359d482 PZ |
1355 | |
1356 | /* | |
1357 | * NYET on CSPLIT | |
1358 | * re-do the CSPLIT immediately on non-periodic | |
1359 | */ | |
1360 | if (chan->do_split && chan->complete_split) { | |
1361 | if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC && | |
95832c00 | 1362 | hsotg->params.host_dma) { |
7359d482 PZ |
1363 | qtd->complete_split = 0; |
1364 | qtd->isoc_split_offset = 0; | |
0d012b98 | 1365 | qtd->isoc_frame_index++; |
7902c16b | 1366 | if (qtd->urb && |
0d012b98 PZ |
1367 | qtd->isoc_frame_index == qtd->urb->packet_count) { |
1368 | dwc2_host_complete(hsotg, qtd, 0); | |
7359d482 | 1369 | dwc2_release_channel(hsotg, chan, qtd, |
7902c16b | 1370 | DWC2_HC_XFER_URB_COMPLETE); |
7359d482 PZ |
1371 | } else { |
1372 | dwc2_release_channel(hsotg, chan, qtd, | |
b98866c2 | 1373 | DWC2_HC_XFER_NO_HALT_STATUS); |
7359d482 PZ |
1374 | } |
1375 | goto handle_nyet_done; | |
1376 | } | |
1377 | ||
1378 | if (chan->ep_type == USB_ENDPOINT_XFER_INT || | |
1379 | chan->ep_type == USB_ENDPOINT_XFER_ISOC) { | |
1479cb69 DA |
1380 | struct dwc2_qh *qh = chan->qh; |
1381 | bool past_end; | |
1382 | ||
95832c00 | 1383 | if (!hsotg->params.uframe_sched) { |
1479cb69 DA |
1384 | int frnum = dwc2_hcd_get_frame_number(hsotg); |
1385 | ||
1386 | /* Don't have num_hs_transfers; simple logic */ | |
1387 | past_end = dwc2_full_frame_num(frnum) != | |
1388 | dwc2_full_frame_num(qh->next_active_frame); | |
1389 | } else { | |
1390 | int end_frnum; | |
7359d482 | 1391 | |
7359d482 | 1392 | /* |
38beaec6 JY |
1393 | * Figure out the end frame based on |
1394 | * schedule. | |
1395 | * | |
1396 | * We don't want to go on trying again | |
1397 | * and again forever. Let's stop when | |
1398 | * we've done all the transfers that | |
1399 | * were scheduled. | |
1400 | * | |
1401 | * We're going to be comparing | |
1402 | * start_active_frame and | |
1403 | * next_active_frame, both of which | |
1404 | * are 1 before the time the packet | |
1405 | * goes on the wire, so that cancels | |
1406 | * out. Basically if had 1 transfer | |
1407 | * and we saw 1 NYET then we're done. | |
1408 | * We're getting a NYET here so if | |
1409 | * next >= (start + num_transfers) | |
1410 | * we're done. The complexity is that | |
1411 | * for all but ISOC_OUT we skip one | |
1412 | * slot. | |
1413 | */ | |
1479cb69 DA |
1414 | end_frnum = dwc2_frame_num_inc( |
1415 | qh->start_active_frame, | |
1416 | qh->num_hs_transfers); | |
1417 | ||
1418 | if (qh->ep_type != USB_ENDPOINT_XFER_ISOC || | |
1419 | qh->ep_is_in) | |
1420 | end_frnum = | |
1421 | dwc2_frame_num_inc(end_frnum, 1); | |
1422 | ||
1423 | past_end = dwc2_frame_num_le( | |
1424 | end_frnum, qh->next_active_frame); | |
1425 | } | |
1426 | ||
1427 | if (past_end) { | |
1428 | /* Treat this as a transaction error. */ | |
7359d482 PZ |
1429 | #if 0 |
1430 | /* | |
1431 | * Todo: Fix system performance so this can | |
1432 | * be treated as an error. Right now complete | |
1433 | * splits cannot be scheduled precisely enough | |
1434 | * due to other system activity, so this error | |
1435 | * occurs regularly in Slave mode. | |
1436 | */ | |
1437 | qtd->error_count++; | |
1438 | #endif | |
1439 | qtd->complete_split = 0; | |
1440 | dwc2_halt_channel(hsotg, chan, qtd, | |
1441 | DWC2_HC_XFER_XACT_ERR); | |
1442 | /* Todo: add support for isoc release */ | |
1443 | goto handle_nyet_done; | |
1444 | } | |
1445 | } | |
1446 | ||
1447 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET); | |
1448 | goto handle_nyet_done; | |
1449 | } | |
1450 | ||
1451 | chan->qh->ping_state = 1; | |
1452 | qtd->error_count = 0; | |
1453 | ||
1454 | dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd, | |
1455 | DWC2_HC_XFER_NYET); | |
1456 | dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); | |
1457 | ||
1458 | /* | |
1459 | * Halt the channel and re-start the transfer so the PING protocol | |
1460 | * will start | |
1461 | */ | |
1462 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET); | |
1463 | ||
1464 | handle_nyet_done: | |
1465 | disable_hc_int(hsotg, chnum, HCINTMSK_NYET); | |
1466 | } | |
1467 | ||
1468 | /* | |
1469 | * Handles a host channel babble interrupt. This handler may be called in | |
1470 | * either DMA mode or Slave mode. | |
1471 | */ | |
1472 | static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg, | |
1473 | struct dwc2_host_chan *chan, int chnum, | |
1474 | struct dwc2_qtd *qtd) | |
1475 | { | |
1476 | dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n", | |
1477 | chnum); | |
1478 | ||
0d012b98 PZ |
1479 | dwc2_hc_handle_tt_clear(hsotg, chan, qtd); |
1480 | ||
95832c00 | 1481 | if (hsotg->params.dma_desc_enable) { |
7359d482 PZ |
1482 | dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, |
1483 | DWC2_HC_XFER_BABBLE_ERR); | |
0d012b98 | 1484 | goto disable_int; |
7359d482 PZ |
1485 | } |
1486 | ||
1487 | if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) { | |
0d012b98 | 1488 | dwc2_host_complete(hsotg, qtd, -EOVERFLOW); |
7359d482 PZ |
1489 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR); |
1490 | } else { | |
1491 | enum dwc2_halt_status halt_status; | |
1492 | ||
1493 | halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum, | |
b98866c2 | 1494 | qtd, DWC2_HC_XFER_BABBLE_ERR); |
7359d482 PZ |
1495 | dwc2_halt_channel(hsotg, chan, qtd, halt_status); |
1496 | } | |
1497 | ||
0d012b98 | 1498 | disable_int: |
7359d482 PZ |
1499 | disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR); |
1500 | } | |
1501 | ||
1502 | /* | |
1503 | * Handles a host channel AHB error interrupt. This handler is only called in | |
1504 | * DMA mode. | |
1505 | */ | |
1506 | static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg, | |
1507 | struct dwc2_host_chan *chan, int chnum, | |
1508 | struct dwc2_qtd *qtd) | |
1509 | { | |
1510 | struct dwc2_hcd_urb *urb = qtd->urb; | |
1511 | char *pipetype, *speed; | |
1512 | u32 hcchar; | |
1513 | u32 hcsplt; | |
1514 | u32 hctsiz; | |
1515 | u32 hc_dma; | |
1516 | ||
1517 | dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n", | |
1518 | chnum); | |
1519 | ||
1520 | if (!urb) | |
1521 | goto handle_ahberr_halt; | |
1522 | ||
0d012b98 PZ |
1523 | dwc2_hc_handle_tt_clear(hsotg, chan, qtd); |
1524 | ||
95c8bc36 AS |
1525 | hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); |
1526 | hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum)); | |
1527 | hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); | |
1528 | hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum)); | |
7359d482 PZ |
1529 | |
1530 | dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum); | |
1531 | dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt); | |
1532 | dev_err(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma); | |
1533 | dev_err(hsotg->dev, " Device address: %d\n", | |
1534 | dwc2_hcd_get_dev_addr(&urb->pipe_info)); | |
1535 | dev_err(hsotg->dev, " Endpoint: %d, %s\n", | |
1536 | dwc2_hcd_get_ep_num(&urb->pipe_info), | |
1537 | dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"); | |
1538 | ||
1539 | switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { | |
1540 | case USB_ENDPOINT_XFER_CONTROL: | |
1541 | pipetype = "CONTROL"; | |
1542 | break; | |
1543 | case USB_ENDPOINT_XFER_BULK: | |
1544 | pipetype = "BULK"; | |
1545 | break; | |
1546 | case USB_ENDPOINT_XFER_INT: | |
1547 | pipetype = "INTERRUPT"; | |
1548 | break; | |
1549 | case USB_ENDPOINT_XFER_ISOC: | |
1550 | pipetype = "ISOCHRONOUS"; | |
1551 | break; | |
1552 | default: | |
1553 | pipetype = "UNKNOWN"; | |
1554 | break; | |
1555 | } | |
1556 | ||
1557 | dev_err(hsotg->dev, " Endpoint type: %s\n", pipetype); | |
1558 | ||
1559 | switch (chan->speed) { | |
1560 | case USB_SPEED_HIGH: | |
1561 | speed = "HIGH"; | |
1562 | break; | |
1563 | case USB_SPEED_FULL: | |
1564 | speed = "FULL"; | |
1565 | break; | |
1566 | case USB_SPEED_LOW: | |
1567 | speed = "LOW"; | |
1568 | break; | |
1569 | default: | |
1570 | speed = "UNKNOWN"; | |
1571 | break; | |
1572 | } | |
1573 | ||
1574 | dev_err(hsotg->dev, " Speed: %s\n", speed); | |
1575 | ||
1576 | dev_err(hsotg->dev, " Max packet size: %d\n", | |
1577 | dwc2_hcd_get_mps(&urb->pipe_info)); | |
1578 | dev_err(hsotg->dev, " Data buffer length: %d\n", urb->length); | |
157dfaac PZ |
1579 | dev_err(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", |
1580 | urb->buf, (unsigned long)urb->dma); | |
1581 | dev_err(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", | |
1582 | urb->setup_packet, (unsigned long)urb->setup_dma); | |
7359d482 PZ |
1583 | dev_err(hsotg->dev, " Interval: %d\n", urb->interval); |
1584 | ||
1585 | /* Core halts the channel for Descriptor DMA mode */ | |
95832c00 | 1586 | if (hsotg->params.dma_desc_enable) { |
7359d482 PZ |
1587 | dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, |
1588 | DWC2_HC_XFER_AHB_ERR); | |
1589 | goto handle_ahberr_done; | |
1590 | } | |
1591 | ||
0d012b98 | 1592 | dwc2_host_complete(hsotg, qtd, -EIO); |
7359d482 PZ |
1593 | |
1594 | handle_ahberr_halt: | |
1595 | /* | |
1596 | * Force a channel halt. Don't call dwc2_halt_channel because that won't | |
1597 | * write to the HCCHARn register in DMA mode to force the halt. | |
1598 | */ | |
1599 | dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR); | |
1600 | ||
1601 | handle_ahberr_done: | |
7359d482 PZ |
1602 | disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR); |
1603 | } | |
1604 | ||
1605 | /* | |
1606 | * Handles a host channel transaction error interrupt. This handler may be | |
1607 | * called in either DMA mode or Slave mode. | |
1608 | */ | |
1609 | static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg, | |
1610 | struct dwc2_host_chan *chan, int chnum, | |
1611 | struct dwc2_qtd *qtd) | |
1612 | { | |
1613 | dev_dbg(hsotg->dev, | |
1614 | "--Host Channel %d Interrupt: Transaction Error--\n", chnum); | |
1615 | ||
0d012b98 PZ |
1616 | dwc2_hc_handle_tt_clear(hsotg, chan, qtd); |
1617 | ||
95832c00 | 1618 | if (hsotg->params.dma_desc_enable) { |
7359d482 PZ |
1619 | dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, |
1620 | DWC2_HC_XFER_XACT_ERR); | |
1621 | goto handle_xacterr_done; | |
1622 | } | |
1623 | ||
1624 | switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { | |
1625 | case USB_ENDPOINT_XFER_CONTROL: | |
1626 | case USB_ENDPOINT_XFER_BULK: | |
1627 | qtd->error_count++; | |
1628 | if (!chan->qh->ping_state) { | |
7359d482 PZ |
1629 | dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, |
1630 | qtd, DWC2_HC_XFER_XACT_ERR); | |
1631 | dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); | |
1632 | if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH) | |
1633 | chan->qh->ping_state = 1; | |
1634 | } | |
1635 | ||
1636 | /* | |
1637 | * Halt the channel so the transfer can be re-started from | |
1638 | * the appropriate point or the PING protocol will start | |
1639 | */ | |
1640 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR); | |
1641 | break; | |
1642 | case USB_ENDPOINT_XFER_INT: | |
1643 | qtd->error_count++; | |
1644 | if (chan->do_split && chan->complete_split) | |
1645 | qtd->complete_split = 0; | |
1646 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR); | |
1647 | break; | |
1648 | case USB_ENDPOINT_XFER_ISOC: | |
1649 | { | |
1650 | enum dwc2_halt_status halt_status; | |
1651 | ||
1652 | halt_status = dwc2_update_isoc_urb_state(hsotg, chan, | |
b98866c2 | 1653 | chnum, qtd, DWC2_HC_XFER_XACT_ERR); |
7359d482 PZ |
1654 | dwc2_halt_channel(hsotg, chan, qtd, halt_status); |
1655 | } | |
1656 | break; | |
1657 | } | |
1658 | ||
1659 | handle_xacterr_done: | |
7359d482 PZ |
1660 | disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR); |
1661 | } | |
1662 | ||
1663 | /* | |
1664 | * Handles a host channel frame overrun interrupt. This handler may be called | |
1665 | * in either DMA mode or Slave mode. | |
1666 | */ | |
1667 | static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg, | |
1668 | struct dwc2_host_chan *chan, int chnum, | |
1669 | struct dwc2_qtd *qtd) | |
1670 | { | |
1671 | enum dwc2_halt_status halt_status; | |
1672 | ||
b49977a6 MK |
1673 | if (dbg_hc(chan)) |
1674 | dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n", | |
1675 | chnum); | |
7359d482 | 1676 | |
0d012b98 PZ |
1677 | dwc2_hc_handle_tt_clear(hsotg, chan, qtd); |
1678 | ||
7359d482 PZ |
1679 | switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { |
1680 | case USB_ENDPOINT_XFER_CONTROL: | |
1681 | case USB_ENDPOINT_XFER_BULK: | |
1682 | break; | |
1683 | case USB_ENDPOINT_XFER_INT: | |
1684 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN); | |
1685 | break; | |
1686 | case USB_ENDPOINT_XFER_ISOC: | |
1687 | halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum, | |
b98866c2 | 1688 | qtd, DWC2_HC_XFER_FRAME_OVERRUN); |
7359d482 PZ |
1689 | dwc2_halt_channel(hsotg, chan, qtd, halt_status); |
1690 | break; | |
1691 | } | |
1692 | ||
7359d482 PZ |
1693 | disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN); |
1694 | } | |
1695 | ||
1696 | /* | |
1697 | * Handles a host channel data toggle error interrupt. This handler may be | |
1698 | * called in either DMA mode or Slave mode. | |
1699 | */ | |
1700 | static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg, | |
1701 | struct dwc2_host_chan *chan, int chnum, | |
1702 | struct dwc2_qtd *qtd) | |
1703 | { | |
1704 | dev_dbg(hsotg->dev, | |
1705 | "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum); | |
1706 | ||
1707 | if (chan->ep_is_in) | |
1708 | qtd->error_count = 0; | |
1709 | else | |
1710 | dev_err(hsotg->dev, | |
1711 | "Data Toggle Error on OUT transfer, channel %d\n", | |
1712 | chnum); | |
1713 | ||
1714 | dwc2_hc_handle_tt_clear(hsotg, chan, qtd); | |
1715 | disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR); | |
1716 | } | |
1717 | ||
1718 | /* | |
1719 | * For debug only. It checks that a valid halt status is set and that | |
1720 | * HCCHARn.chdis is clear. If there's a problem, corrective action is | |
1721 | * taken and a warning is issued. | |
1722 | * | |
1723 | * Return: true if halt status is ok, false otherwise | |
1724 | */ | |
1725 | static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg, | |
1726 | struct dwc2_host_chan *chan, int chnum, | |
1727 | struct dwc2_qtd *qtd) | |
1728 | { | |
1729 | #ifdef DEBUG | |
1730 | u32 hcchar; | |
1731 | u32 hctsiz; | |
1732 | u32 hcintmsk; | |
1733 | u32 hcsplt; | |
1734 | ||
1735 | if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) { | |
1736 | /* | |
1737 | * This code is here only as a check. This condition should | |
1738 | * never happen. Ignore the halt if it does occur. | |
1739 | */ | |
95c8bc36 AS |
1740 | hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); |
1741 | hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); | |
1742 | hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); | |
1743 | hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum)); | |
7359d482 PZ |
1744 | dev_dbg(hsotg->dev, |
1745 | "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n", | |
1746 | __func__); | |
1747 | dev_dbg(hsotg->dev, | |
1748 | "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n", | |
1749 | chnum, hcchar, hctsiz); | |
1750 | dev_dbg(hsotg->dev, | |
1751 | "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n", | |
1752 | chan->hcint, hcintmsk, hcsplt); | |
8509f2f4 MK |
1753 | if (qtd) |
1754 | dev_dbg(hsotg->dev, "qtd->complete_split %d\n", | |
1755 | qtd->complete_split); | |
7359d482 PZ |
1756 | dev_warn(hsotg->dev, |
1757 | "%s: no halt status, channel %d, ignoring interrupt\n", | |
1758 | __func__, chnum); | |
1759 | return false; | |
1760 | } | |
1761 | ||
1762 | /* | |
1763 | * This code is here only as a check. hcchar.chdis should never be set | |
1764 | * when the halt interrupt occurs. Halt the channel again if it does | |
1765 | * occur. | |
1766 | */ | |
95c8bc36 | 1767 | hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); |
7359d482 PZ |
1768 | if (hcchar & HCCHAR_CHDIS) { |
1769 | dev_warn(hsotg->dev, | |
1770 | "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n", | |
1771 | __func__, hcchar); | |
1772 | chan->halt_pending = 0; | |
1773 | dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status); | |
1774 | return false; | |
1775 | } | |
1776 | #endif | |
1777 | ||
1778 | return true; | |
1779 | } | |
1780 | ||
1781 | /* | |
1782 | * Handles a host Channel Halted interrupt in DMA mode. This handler | |
1783 | * determines the reason the channel halted and proceeds accordingly. | |
1784 | */ | |
1785 | static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg, | |
1786 | struct dwc2_host_chan *chan, int chnum, | |
1787 | struct dwc2_qtd *qtd) | |
1788 | { | |
1789 | u32 hcintmsk; | |
1790 | int out_nak_enh = 0; | |
1791 | ||
b49977a6 MK |
1792 | if (dbg_hc(chan)) |
1793 | dev_vdbg(hsotg->dev, | |
1794 | "--Host Channel %d Interrupt: DMA Channel Halted--\n", | |
1795 | chnum); | |
7359d482 PZ |
1796 | |
1797 | /* | |
1798 | * For core with OUT NAK enhancement, the flow for high-speed | |
1799 | * CONTROL/BULK OUT is handled a little differently | |
1800 | */ | |
9badec2f | 1801 | if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) { |
7359d482 PZ |
1802 | if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in && |
1803 | (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || | |
1804 | chan->ep_type == USB_ENDPOINT_XFER_BULK)) { | |
1805 | out_nak_enh = 1; | |
1806 | } | |
1807 | } | |
1808 | ||
1809 | if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE || | |
1810 | (chan->halt_status == DWC2_HC_XFER_AHB_ERR && | |
95832c00 JY |
1811 | !hsotg->params.dma_desc_enable)) { |
1812 | if (hsotg->params.dma_desc_enable) | |
7359d482 PZ |
1813 | dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, |
1814 | chan->halt_status); | |
1815 | else | |
1816 | /* | |
1817 | * Just release the channel. A dequeue can happen on a | |
1818 | * transfer timeout. In the case of an AHB Error, the | |
1819 | * channel was forced to halt because there's no way to | |
1820 | * gracefully recover. | |
1821 | */ | |
1822 | dwc2_release_channel(hsotg, chan, qtd, | |
1823 | chan->halt_status); | |
1824 | return; | |
1825 | } | |
1826 | ||
95c8bc36 | 1827 | hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); |
7359d482 PZ |
1828 | |
1829 | if (chan->hcint & HCINTMSK_XFERCOMPL) { | |
1830 | /* | |
1831 | * Todo: This is here because of a possible hardware bug. Spec | |
1832 | * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT | |
1833 | * interrupt w/ACK bit set should occur, but I only see the | |
1834 | * XFERCOMP bit, even with it masked out. This is a workaround | |
1835 | * for that behavior. Should fix this when hardware is fixed. | |
1836 | */ | |
1837 | if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in) | |
1838 | dwc2_hc_ack_intr(hsotg, chan, chnum, qtd); | |
1839 | dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd); | |
1840 | } else if (chan->hcint & HCINTMSK_STALL) { | |
1841 | dwc2_hc_stall_intr(hsotg, chan, chnum, qtd); | |
1842 | } else if ((chan->hcint & HCINTMSK_XACTERR) && | |
95832c00 | 1843 | !hsotg->params.dma_desc_enable) { |
7359d482 PZ |
1844 | if (out_nak_enh) { |
1845 | if (chan->hcint & | |
1846 | (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) { | |
1847 | dev_vdbg(hsotg->dev, | |
1848 | "XactErr with NYET/NAK/ACK\n"); | |
1849 | qtd->error_count = 0; | |
1850 | } else { | |
1851 | dev_vdbg(hsotg->dev, | |
1852 | "XactErr without NYET/NAK/ACK\n"); | |
1853 | } | |
1854 | } | |
1855 | ||
1856 | /* | |
1857 | * Must handle xacterr before nak or ack. Could get a xacterr | |
1858 | * at the same time as either of these on a BULK/CONTROL OUT | |
1859 | * that started with a PING. The xacterr takes precedence. | |
1860 | */ | |
1861 | dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd); | |
1862 | } else if ((chan->hcint & HCINTMSK_XCS_XACT) && | |
95832c00 | 1863 | hsotg->params.dma_desc_enable) { |
7359d482 PZ |
1864 | dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd); |
1865 | } else if ((chan->hcint & HCINTMSK_AHBERR) && | |
95832c00 | 1866 | hsotg->params.dma_desc_enable) { |
7359d482 PZ |
1867 | dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd); |
1868 | } else if (chan->hcint & HCINTMSK_BBLERR) { | |
1869 | dwc2_hc_babble_intr(hsotg, chan, chnum, qtd); | |
1870 | } else if (chan->hcint & HCINTMSK_FRMOVRUN) { | |
1871 | dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd); | |
1872 | } else if (!out_nak_enh) { | |
1873 | if (chan->hcint & HCINTMSK_NYET) { | |
1874 | /* | |
1875 | * Must handle nyet before nak or ack. Could get a nyet | |
1876 | * at the same time as either of those on a BULK/CONTROL | |
1877 | * OUT that started with a PING. The nyet takes | |
1878 | * precedence. | |
1879 | */ | |
1880 | dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd); | |
1881 | } else if ((chan->hcint & HCINTMSK_NAK) && | |
1882 | !(hcintmsk & HCINTMSK_NAK)) { | |
1883 | /* | |
1884 | * If nak is not masked, it's because a non-split IN | |
1885 | * transfer is in an error state. In that case, the nak | |
1886 | * is handled by the nak interrupt handler, not here. | |
1887 | * Handle nak here for BULK/CONTROL OUT transfers, which | |
1888 | * halt on a NAK to allow rewinding the buffer pointer. | |
1889 | */ | |
1890 | dwc2_hc_nak_intr(hsotg, chan, chnum, qtd); | |
1891 | } else if ((chan->hcint & HCINTMSK_ACK) && | |
1892 | !(hcintmsk & HCINTMSK_ACK)) { | |
1893 | /* | |
1894 | * If ack is not masked, it's because a non-split IN | |
1895 | * transfer is in an error state. In that case, the ack | |
1896 | * is handled by the ack interrupt handler, not here. | |
1897 | * Handle ack here for split transfers. Start splits | |
1898 | * halt on ACK. | |
1899 | */ | |
1900 | dwc2_hc_ack_intr(hsotg, chan, chnum, qtd); | |
1901 | } else { | |
1902 | if (chan->ep_type == USB_ENDPOINT_XFER_INT || | |
1903 | chan->ep_type == USB_ENDPOINT_XFER_ISOC) { | |
1904 | /* | |
1905 | * A periodic transfer halted with no other | |
1906 | * channel interrupts set. Assume it was halted | |
1907 | * by the core because it could not be completed | |
1908 | * in its scheduled (micro)frame. | |
1909 | */ | |
1910 | dev_dbg(hsotg->dev, | |
1911 | "%s: Halt channel %d (assume incomplete periodic transfer)\n", | |
1912 | __func__, chnum); | |
1913 | dwc2_halt_channel(hsotg, chan, qtd, | |
b98866c2 | 1914 | DWC2_HC_XFER_PERIODIC_INCOMPLETE); |
7359d482 PZ |
1915 | } else { |
1916 | dev_err(hsotg->dev, | |
1917 | "%s: Channel %d - ChHltd set, but reason is unknown\n", | |
1918 | __func__, chnum); | |
1919 | dev_err(hsotg->dev, | |
1920 | "hcint 0x%08x, intsts 0x%08x\n", | |
1921 | chan->hcint, | |
95c8bc36 | 1922 | dwc2_readl(hsotg->regs + GINTSTS)); |
151d0cbd | 1923 | goto error; |
7359d482 PZ |
1924 | } |
1925 | } | |
1926 | } else { | |
1927 | dev_info(hsotg->dev, | |
1928 | "NYET/NAK/ACK/other in non-error case, 0x%08x\n", | |
1929 | chan->hcint); | |
151d0cbd NH |
1930 | error: |
1931 | /* Failthrough: use 3-strikes rule */ | |
1932 | qtd->error_count++; | |
1933 | dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, | |
1934 | qtd, DWC2_HC_XFER_XACT_ERR); | |
1935 | dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); | |
1936 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR); | |
7359d482 PZ |
1937 | } |
1938 | } | |
1939 | ||
1940 | /* | |
1941 | * Handles a host channel Channel Halted interrupt | |
1942 | * | |
1943 | * In slave mode, this handler is called only when the driver specifically | |
1944 | * requests a halt. This occurs during handling other host channel interrupts | |
1945 | * (e.g. nak, xacterr, stall, nyet, etc.). | |
1946 | * | |
1947 | * In DMA mode, this is the interrupt that occurs when the core has finished | |
1948 | * processing a transfer on a channel. Other host channel interrupts (except | |
1949 | * ahberr) are disabled in DMA mode. | |
1950 | */ | |
1951 | static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg, | |
1952 | struct dwc2_host_chan *chan, int chnum, | |
1953 | struct dwc2_qtd *qtd) | |
1954 | { | |
b49977a6 MK |
1955 | if (dbg_hc(chan)) |
1956 | dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n", | |
1957 | chnum); | |
7359d482 | 1958 | |
95832c00 | 1959 | if (hsotg->params.host_dma) { |
7359d482 PZ |
1960 | dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd); |
1961 | } else { | |
1962 | if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd)) | |
1963 | return; | |
1964 | dwc2_release_channel(hsotg, chan, qtd, chan->halt_status); | |
1965 | } | |
1966 | } | |
1967 | ||
dc873084 DA |
1968 | /* |
1969 | * Check if the given qtd is still the top of the list (and thus valid). | |
1970 | * | |
1971 | * If dwc2_hcd_qtd_unlink_and_free() has been called since we grabbed | |
1972 | * the qtd from the top of the list, this will return false (otherwise true). | |
1973 | */ | |
1974 | static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh) | |
1975 | { | |
1976 | struct dwc2_qtd *cur_head; | |
1977 | ||
9da51974 | 1978 | if (!qh) |
dc873084 DA |
1979 | return false; |
1980 | ||
1981 | cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd, | |
1982 | qtd_list_entry); | |
1983 | return (cur_head == qtd); | |
1984 | } | |
1985 | ||
7359d482 PZ |
1986 | /* Handles interrupt for a specific Host Channel */ |
1987 | static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum) | |
1988 | { | |
1989 | struct dwc2_qtd *qtd; | |
1990 | struct dwc2_host_chan *chan; | |
1991 | u32 hcint, hcintmsk; | |
1992 | ||
b49977a6 MK |
1993 | chan = hsotg->hc_ptr_array[chnum]; |
1994 | ||
95c8bc36 AS |
1995 | hcint = dwc2_readl(hsotg->regs + HCINT(chnum)); |
1996 | hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); | |
7359d482 PZ |
1997 | if (!chan) { |
1998 | dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n"); | |
95c8bc36 | 1999 | dwc2_writel(hcint, hsotg->regs + HCINT(chnum)); |
7359d482 PZ |
2000 | return; |
2001 | } | |
2002 | ||
723a2311 RK |
2003 | if (dbg_hc(chan)) { |
2004 | dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n", | |
2005 | chnum); | |
2006 | dev_vdbg(hsotg->dev, | |
2007 | " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", | |
2008 | hcint, hcintmsk, hcint & hcintmsk); | |
2009 | } | |
2010 | ||
95c8bc36 | 2011 | dwc2_writel(hcint, hsotg->regs + HCINT(chnum)); |
16e80218 DA |
2012 | |
2013 | /* | |
2014 | * If we got an interrupt after someone called | |
2015 | * dwc2_hcd_endpoint_disable() we don't want to crash below | |
2016 | */ | |
2017 | if (!chan->qh) { | |
2018 | dev_warn(hsotg->dev, "Interrupt on disabled channel\n"); | |
2019 | return; | |
2020 | } | |
2021 | ||
7359d482 PZ |
2022 | chan->hcint = hcint; |
2023 | hcint &= hcintmsk; | |
2024 | ||
8509f2f4 MK |
2025 | /* |
2026 | * If the channel was halted due to a dequeue, the qtd list might | |
2027 | * be empty or at least the first entry will not be the active qtd. | |
2028 | * In this case, take a shortcut and just release the channel. | |
2029 | */ | |
2030 | if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) { | |
2031 | /* | |
2032 | * If the channel was halted, this should be the only | |
2033 | * interrupt unmasked | |
2034 | */ | |
2035 | WARN_ON(hcint != HCINTMSK_CHHLTD); | |
95832c00 | 2036 | if (hsotg->params.dma_desc_enable) |
8509f2f4 MK |
2037 | dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, |
2038 | chan->halt_status); | |
2039 | else | |
2040 | dwc2_release_channel(hsotg, chan, NULL, | |
2041 | chan->halt_status); | |
2042 | return; | |
2043 | } | |
2044 | ||
7359d482 | 2045 | if (list_empty(&chan->qh->qtd_list)) { |
8509f2f4 MK |
2046 | /* |
2047 | * TODO: Will this ever happen with the | |
2048 | * DWC2_HC_XFER_URB_DEQUEUE handling above? | |
2049 | */ | |
7359d482 PZ |
2050 | dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n", |
2051 | chnum); | |
2052 | dev_dbg(hsotg->dev, | |
2053 | " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", | |
2054 | chan->hcint, hcintmsk, hcint); | |
2055 | chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; | |
2056 | disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD); | |
2057 | chan->hcint = 0; | |
2058 | return; | |
2059 | } | |
2060 | ||
2061 | qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd, | |
2062 | qtd_list_entry); | |
2063 | ||
95832c00 | 2064 | if (!hsotg->params.host_dma) { |
7359d482 PZ |
2065 | if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD) |
2066 | hcint &= ~HCINTMSK_CHHLTD; | |
2067 | } | |
2068 | ||
2069 | if (hcint & HCINTMSK_XFERCOMPL) { | |
2070 | dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd); | |
2071 | /* | |
2072 | * If NYET occurred at same time as Xfer Complete, the NYET is | |
2073 | * handled by the Xfer Complete interrupt handler. Don't want | |
2074 | * to call the NYET interrupt handler in this case. | |
2075 | */ | |
2076 | hcint &= ~HCINTMSK_NYET; | |
2077 | } | |
dc873084 DA |
2078 | |
2079 | if (hcint & HCINTMSK_CHHLTD) { | |
7359d482 | 2080 | dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd); |
dc873084 DA |
2081 | if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) |
2082 | goto exit; | |
2083 | } | |
2084 | if (hcint & HCINTMSK_AHBERR) { | |
7359d482 | 2085 | dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd); |
dc873084 DA |
2086 | if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) |
2087 | goto exit; | |
2088 | } | |
2089 | if (hcint & HCINTMSK_STALL) { | |
7359d482 | 2090 | dwc2_hc_stall_intr(hsotg, chan, chnum, qtd); |
dc873084 DA |
2091 | if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) |
2092 | goto exit; | |
2093 | } | |
2094 | if (hcint & HCINTMSK_NAK) { | |
7359d482 | 2095 | dwc2_hc_nak_intr(hsotg, chan, chnum, qtd); |
dc873084 DA |
2096 | if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) |
2097 | goto exit; | |
2098 | } | |
2099 | if (hcint & HCINTMSK_ACK) { | |
7359d482 | 2100 | dwc2_hc_ack_intr(hsotg, chan, chnum, qtd); |
dc873084 DA |
2101 | if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) |
2102 | goto exit; | |
2103 | } | |
2104 | if (hcint & HCINTMSK_NYET) { | |
7359d482 | 2105 | dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd); |
dc873084 DA |
2106 | if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) |
2107 | goto exit; | |
2108 | } | |
2109 | if (hcint & HCINTMSK_XACTERR) { | |
7359d482 | 2110 | dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd); |
dc873084 DA |
2111 | if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) |
2112 | goto exit; | |
2113 | } | |
2114 | if (hcint & HCINTMSK_BBLERR) { | |
7359d482 | 2115 | dwc2_hc_babble_intr(hsotg, chan, chnum, qtd); |
dc873084 DA |
2116 | if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) |
2117 | goto exit; | |
2118 | } | |
2119 | if (hcint & HCINTMSK_FRMOVRUN) { | |
7359d482 | 2120 | dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd); |
dc873084 DA |
2121 | if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) |
2122 | goto exit; | |
2123 | } | |
2124 | if (hcint & HCINTMSK_DATATGLERR) { | |
7359d482 | 2125 | dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd); |
dc873084 DA |
2126 | if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) |
2127 | goto exit; | |
2128 | } | |
7359d482 | 2129 | |
dc873084 | 2130 | exit: |
7359d482 PZ |
2131 | chan->hcint = 0; |
2132 | } | |
2133 | ||
2134 | /* | |
2135 | * This interrupt indicates that one or more host channels has a pending | |
2136 | * interrupt. There are multiple conditions that can cause each host channel | |
2137 | * interrupt. This function determines which conditions have occurred for each | |
2138 | * host channel interrupt and handles them appropriately. | |
2139 | */ | |
2140 | static void dwc2_hc_intr(struct dwc2_hsotg *hsotg) | |
2141 | { | |
2142 | u32 haint; | |
2143 | int i; | |
c9c8ac01 | 2144 | struct dwc2_host_chan *chan, *chan_tmp; |
7359d482 | 2145 | |
95c8bc36 | 2146 | haint = dwc2_readl(hsotg->regs + HAINT); |
b49977a6 MK |
2147 | if (dbg_perio()) { |
2148 | dev_vdbg(hsotg->dev, "%s()\n", __func__); | |
2149 | ||
2150 | dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint); | |
2151 | } | |
7359d482 | 2152 | |
c9c8ac01 DA |
2153 | /* |
2154 | * According to USB 2.0 spec section 11.18.8, a host must | |
2155 | * issue complete-split transactions in a microframe for a | |
2156 | * set of full-/low-speed endpoints in the same relative | |
2157 | * order as the start-splits were issued in a microframe for. | |
2158 | */ | |
2159 | list_for_each_entry_safe(chan, chan_tmp, &hsotg->split_order, | |
2160 | split_order_list_entry) { | |
2161 | int hc_num = chan->hc_num; | |
2162 | ||
2163 | if (haint & (1 << hc_num)) { | |
2164 | dwc2_hc_n_intr(hsotg, hc_num); | |
2165 | haint &= ~(1 << hc_num); | |
2166 | } | |
2167 | } | |
2168 | ||
bea8e86c | 2169 | for (i = 0; i < hsotg->params.host_channels; i++) { |
7359d482 PZ |
2170 | if (haint & (1 << i)) |
2171 | dwc2_hc_n_intr(hsotg, i); | |
2172 | } | |
2173 | } | |
2174 | ||
2175 | /* This function handles interrupts for the HCD */ | |
ca18f4a6 | 2176 | irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg) |
7359d482 | 2177 | { |
b49977a6 | 2178 | u32 gintsts, dbg_gintsts; |
6aafb003 | 2179 | irqreturn_t retval = IRQ_NONE; |
7359d482 | 2180 | |
54216ace | 2181 | if (!dwc2_is_controller_alive(hsotg)) { |
057715f2 | 2182 | dev_warn(hsotg->dev, "Controller is dead\n"); |
6aafb003 | 2183 | return retval; |
7359d482 PZ |
2184 | } |
2185 | ||
2186 | spin_lock(&hsotg->lock); | |
2187 | ||
2188 | /* Check if HOST Mode */ | |
2189 | if (dwc2_is_host_mode(hsotg)) { | |
2190 | gintsts = dwc2_read_core_intr(hsotg); | |
2191 | if (!gintsts) { | |
2192 | spin_unlock(&hsotg->lock); | |
6aafb003 | 2193 | return retval; |
7359d482 PZ |
2194 | } |
2195 | ||
6aafb003 | 2196 | retval = IRQ_HANDLED; |
7359d482 | 2197 | |
b49977a6 | 2198 | dbg_gintsts = gintsts; |
7359d482 | 2199 | #ifndef DEBUG_SOF |
b49977a6 | 2200 | dbg_gintsts &= ~GINTSTS_SOF; |
7359d482 | 2201 | #endif |
b49977a6 MK |
2202 | if (!dbg_perio()) |
2203 | dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL | | |
2204 | GINTSTS_PTXFEMP); | |
2205 | ||
2206 | /* Only print if there are any non-suppressed interrupts left */ | |
2207 | if (dbg_gintsts) | |
7359d482 PZ |
2208 | dev_vdbg(hsotg->dev, |
2209 | "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", | |
2210 | gintsts); | |
2211 | ||
2212 | if (gintsts & GINTSTS_SOF) | |
2213 | dwc2_sof_intr(hsotg); | |
2214 | if (gintsts & GINTSTS_RXFLVL) | |
2215 | dwc2_rx_fifo_level_intr(hsotg); | |
2216 | if (gintsts & GINTSTS_NPTXFEMP) | |
2217 | dwc2_np_tx_fifo_empty_intr(hsotg); | |
7359d482 PZ |
2218 | if (gintsts & GINTSTS_PRTINT) |
2219 | dwc2_port_intr(hsotg); | |
2220 | if (gintsts & GINTSTS_HCHINT) | |
2221 | dwc2_hc_intr(hsotg); | |
2222 | if (gintsts & GINTSTS_PTXFEMP) | |
2223 | dwc2_perio_tx_fifo_empty_intr(hsotg); | |
2224 | ||
b49977a6 | 2225 | if (dbg_gintsts) { |
7359d482 PZ |
2226 | dev_vdbg(hsotg->dev, |
2227 | "DWC OTG HCD Finished Servicing Interrupts\n"); | |
2228 | dev_vdbg(hsotg->dev, | |
2229 | "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n", | |
95c8bc36 AS |
2230 | dwc2_readl(hsotg->regs + GINTSTS), |
2231 | dwc2_readl(hsotg->regs + GINTMSK)); | |
7359d482 | 2232 | } |
7359d482 PZ |
2233 | } |
2234 | ||
2235 | spin_unlock(&hsotg->lock); | |
2236 | ||
2237 | return retval; | |
2238 | } |