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usb: dwc2: host: Always add to the tail of queues
[linux-2.6-block.git] / drivers / usb / dwc2 / hcd.c
CommitLineData
7359d482
PZ		 1/*
2 * hcd.c - DesignWare HS OTG Controller host-mode routines
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/*
38 * This file contains the core HCD code, and implements the Linux hc_driver
39 * API
40 */
41#include <linux/kernel.h>
42#include <linux/module.h>
43#include <linux/spinlock.h>
44#include <linux/interrupt.h>
45#include <linux/dma-mapping.h>
46#include <linux/delay.h>
47#include <linux/io.h>
48#include <linux/slab.h>
49#include <linux/usb.h>
50
51#include <linux/usb/hcd.h>
52#include <linux/usb/ch11.h>
53
54#include "core.h"
55#include "hcd.h"
56
57/**
58 * dwc2_dump_channel_info() - Prints the state of a host channel
59 *
60 * @hsotg: Programming view of DWC_otg controller
61 * @chan: Pointer to the channel to dump
62 *
63 * Must be called with interrupt disabled and spinlock held
64 *
65 * NOTE: This function will be removed once the peripheral controller code
66 * is integrated and the driver is stable
67 */
68static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
69 struct dwc2_host_chan *chan)
70{
71#ifdef VERBOSE_DEBUG
72 int num_channels = hsotg->core_params->host_channels;
73 struct dwc2_qh *qh;
74 u32 hcchar;
75 u32 hcsplt;
76 u32 hctsiz;
77 u32 hc_dma;
78 int i;
79
80 if (chan == NULL)
81 return;
82
95c8bc36
AS		 83 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
84 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
85 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
86 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
7359d482
PZ		 87
88 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
89 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
90 hcchar, hcsplt);
91 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
92 hctsiz, hc_dma);
93 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
94 chan->dev_addr, chan->ep_num, chan->ep_is_in);
95 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
96 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
97 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
98 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
99 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
100 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
101 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
102 (unsigned long)chan->xfer_dma);
103 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
104 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
105 dev_dbg(hsotg->dev, " NP inactive sched:\n");
106 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
107 qh_list_entry)
108 dev_dbg(hsotg->dev, " %p\n", qh);
109 dev_dbg(hsotg->dev, " NP active sched:\n");
110 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
111 qh_list_entry)
112 dev_dbg(hsotg->dev, " %p\n", qh);
113 dev_dbg(hsotg->dev, " Channels:\n");
114 for (i = 0; i < num_channels; i++) {
115 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
116
117 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
118 }
119#endif /* VERBOSE_DEBUG */
120}
121
122/*
123 * Processes all the URBs in a single list of QHs. Completes them with
124 * -ETIMEDOUT and frees the QTD.
125 *
126 * Must be called with interrupt disabled and spinlock held
127 */
128static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
129 struct list_head *qh_list)
130{
131 struct dwc2_qh *qh, *qh_tmp;
132 struct dwc2_qtd *qtd, *qtd_tmp;
133
134 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
135 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
136 qtd_list_entry) {
2e84da6e 137 dwc2_host_complete(hsotg, qtd, -ECONNRESET);
0d012b98 138 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
7359d482
PZ		 139 }
140 }
141}
142
143static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
144 struct list_head *qh_list)
145{
146 struct dwc2_qtd *qtd, *qtd_tmp;
147 struct dwc2_qh *qh, *qh_tmp;
148 unsigned long flags;
149
150 if (!qh_list->next)
151 /* The list hasn't been initialized yet */
152 return;
153
154 spin_lock_irqsave(&hsotg->lock, flags);
155
156 /* Ensure there are no QTDs or URBs left */
157 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
158
159 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
160 dwc2_hcd_qh_unlink(hsotg, qh);
161
162 /* Free each QTD in the QH's QTD list */
163 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
164 qtd_list_entry)
165 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
166
16e80218
DA		 167 if (qh->channel && qh->channel->qh == qh)
168 qh->channel->qh = NULL;
169
7359d482
PZ		 170 spin_unlock_irqrestore(&hsotg->lock, flags);
171 dwc2_hcd_qh_free(hsotg, qh);
172 spin_lock_irqsave(&hsotg->lock, flags);
173 }
174
175 spin_unlock_irqrestore(&hsotg->lock, flags);
176}
177
178/*
179 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
180 * and periodic schedules. The QTD associated with each URB is removed from
181 * the schedule and freed. This function may be called when a disconnect is
182 * detected or when the HCD is being stopped.
183 *
184 * Must be called with interrupt disabled and spinlock held
185 */
186static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
187{
188 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
189 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
190 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
191 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
192 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
193 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
194}
195
196/**
197 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
198 *
199 * @hsotg: Pointer to struct dwc2_hsotg
200 */
201void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
202{
203 u32 hprt0;
204
205 if (hsotg->op_state == OTG_STATE_B_HOST) {
206 /*
207 * Reset the port. During a HNP mode switch the reset
208 * needs to occur within 1ms and have a duration of at
209 * least 50ms.
210 */
211 hprt0 = dwc2_read_hprt0(hsotg);
212 hprt0 |= HPRT0_RST;
95c8bc36 213 dwc2_writel(hprt0, hsotg->regs + HPRT0);
7359d482
PZ		 214 }
215
216 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
217 msecs_to_jiffies(50));
218}
219
220/* Must be called with interrupt disabled and spinlock held */
221static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
222{
223 int num_channels = hsotg->core_params->host_channels;
224 struct dwc2_host_chan *channel;
225 u32 hcchar;
226 int i;
227
228 if (hsotg->core_params->dma_enable <= 0) {
229 /* Flush out any channel requests in slave mode */
230 for (i = 0; i < num_channels; i++) {
231 channel = hsotg->hc_ptr_array[i];
232 if (!list_empty(&channel->hc_list_entry))
233 continue;
95c8bc36 234 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
7359d482
PZ		 235 if (hcchar & HCCHAR_CHENA) {
236 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
237 hcchar |= HCCHAR_CHDIS;
95c8bc36 238 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
7359d482
PZ		 239 }
240 }
241 }
242
243 for (i = 0; i < num_channels; i++) {
244 channel = hsotg->hc_ptr_array[i];
245 if (!list_empty(&channel->hc_list_entry))
246 continue;
95c8bc36 247 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
7359d482
PZ		 248 if (hcchar & HCCHAR_CHENA) {
249 /* Halt the channel */
250 hcchar |= HCCHAR_CHDIS;
95c8bc36 251 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
7359d482
PZ		 252 }
253
254 dwc2_hc_cleanup(hsotg, channel);
255 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
256 /*
257 * Added for Descriptor DMA to prevent channel double cleanup in
258 * release_channel_ddma(), which is called from ep_disable when
259 * device disconnects
260 */
261 channel->qh = NULL;
262 }
7252f1bf
VP		 263 /* All channels have been freed, mark them available */
264 if (hsotg->core_params->uframe_sched > 0) {
265 hsotg->available_host_channels =
266 hsotg->core_params->host_channels;
267 } else {
268 hsotg->non_periodic_channels = 0;
269 hsotg->periodic_channels = 0;
270 }
7359d482
PZ		 271}
272
6a659531
DA		 273/**
274 * dwc2_hcd_connect() - Handles connect of the HCD
275 *
276 * @hsotg: Pointer to struct dwc2_hsotg
277 *
278 * Must be called with interrupt disabled and spinlock held
279 */
280void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
281{
282 if (hsotg->lx_state != DWC2_L0)
283 usb_hcd_resume_root_hub(hsotg->priv);
284
285 hsotg->flags.b.port_connect_status_change = 1;
286 hsotg->flags.b.port_connect_status = 1;
287}
288
7359d482
PZ		 289/**
290 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
291 *
292 * @hsotg: Pointer to struct dwc2_hsotg
6a659531 293 * @force: If true, we won't try to reconnect even if we see device connected.
7359d482
PZ		 294 *
295 * Must be called with interrupt disabled and spinlock held
296 */
6a659531 297void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
7359d482
PZ		 298{
299 u32 intr;
6a659531 300 u32 hprt0;
7359d482
PZ		 301
302 /* Set status flags for the hub driver */
303 hsotg->flags.b.port_connect_status_change = 1;
304 hsotg->flags.b.port_connect_status = 0;
305
306 /*
307 * Shutdown any transfers in process by clearing the Tx FIFO Empty
308 * interrupt mask and status bits and disabling subsequent host
309 * channel interrupts.
310 */
95c8bc36 311 intr = dwc2_readl(hsotg->regs + GINTMSK);
7359d482 312 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
95c8bc36 313 dwc2_writel(intr, hsotg->regs + GINTMSK);
7359d482 314 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
95c8bc36 315 dwc2_writel(intr, hsotg->regs + GINTSTS);
7359d482
PZ		 316
317 /*
318 * Turn off the vbus power only if the core has transitioned to device
319 * mode. If still in host mode, need to keep power on to detect a
320 * reconnection.
321 */
322 if (dwc2_is_device_mode(hsotg)) {
323 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
324 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
95c8bc36 325 dwc2_writel(0, hsotg->regs + HPRT0);
7359d482
PZ		 326 }
327
328 dwc2_disable_host_interrupts(hsotg);
329 }
330
331 /* Respond with an error status to all URBs in the schedule */
332 dwc2_kill_all_urbs(hsotg);
333
334 if (dwc2_is_host_mode(hsotg))
335 /* Clean up any host channels that were in use */
336 dwc2_hcd_cleanup_channels(hsotg);
337
338 dwc2_host_disconnect(hsotg);
6a659531
DA		 339
340 /*
341 * Add an extra check here to see if we're actually connected but
342 * we don't have a detection interrupt pending. This can happen if:
343 * 1. hardware sees connect
344 * 2. hardware sees disconnect
345 * 3. hardware sees connect
346 * 4. dwc2_port_intr() - clears connect interrupt
347 * 5. dwc2_handle_common_intr() - calls here
348 *
349 * Without the extra check here we will end calling disconnect
350 * and won't get any future interrupts to handle the connect.
351 */
352 if (!force) {
353 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
354 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
355 dwc2_hcd_connect(hsotg);
356 }
7359d482
PZ		 357}
358
359/**
360 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
361 *
362 * @hsotg: Pointer to struct dwc2_hsotg
363 */
364static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
365{
1fb7f12d 366 if (hsotg->bus_suspended) {
7359d482 367 hsotg->flags.b.port_suspend_change = 1;
b46146d5 368 usb_hcd_resume_root_hub(hsotg->priv);
b46146d5 369 }
1fb7f12d
DA		 370
371 if (hsotg->lx_state == DWC2_L1)
372 hsotg->flags.b.port_l1_change = 1;
7359d482
PZ		 373}
374
375/**
376 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
377 *
378 * @hsotg: Pointer to struct dwc2_hsotg
379 *
380 * Must be called with interrupt disabled and spinlock held
381 */
382void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
383{
384 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
385
386 /*
387 * The root hub should be disconnected before this function is called.
388 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
389 * and the QH lists (via ..._hcd_endpoint_disable).
390 */
391
392 /* Turn off all host-specific interrupts */
393 dwc2_disable_host_interrupts(hsotg);
394
395 /* Turn off the vbus power */
396 dev_dbg(hsotg->dev, "PortPower off\n");
95c8bc36 397 dwc2_writel(0, hsotg->regs + HPRT0);
7359d482
PZ		 398}
399
33ad261a 400/* Caller must hold driver lock */
7359d482 401static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
b58e6cee 402 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
b5a468a6 403 struct dwc2_qtd *qtd)
7359d482 404{
7359d482
PZ		 405 u32 intr_mask;
406 int retval;
9f8144c6 407 int dev_speed;
7359d482
PZ		 408
409 if (!hsotg->flags.b.port_connect_status) {
410 /* No longer connected */
411 dev_err(hsotg->dev, "Not connected\n");
412 return -ENODEV;
413 }
414
9f8144c6
NH		 415 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
416
417 /* Some configurations cannot support LS traffic on a FS root port */
418 if ((dev_speed == USB_SPEED_LOW) &&
419 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
420 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
95c8bc36 421 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
9f8144c6
NH		 422 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
423
424 if (prtspd == HPRT0_SPD_FULL_SPEED)
425 return -ENODEV;
426 }
427
7359d482 428 if (!qtd)
b5a468a6 429 return -EINVAL;
7359d482
PZ		 430
431 dwc2_hcd_qtd_init(qtd, urb);
b58e6cee 432 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
9bda1aac 433 if (retval) {
7359d482
PZ		 434 dev_err(hsotg->dev,
435 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
436 retval);
7359d482
PZ		 437 return retval;
438 }
439
95c8bc36 440 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
9bda1aac 441 if (!(intr_mask & GINTSTS_SOF)) {
7359d482
PZ		 442 enum dwc2_transaction_type tr_type;
443
444 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
445 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
446 /*
447 * Do not schedule SG transactions until qtd has
448 * URB_GIVEBACK_ASAP set
449 */
450 return 0;
451
7359d482
PZ		 452 tr_type = dwc2_hcd_select_transactions(hsotg);
453 if (tr_type != DWC2_TRANSACTION_NONE)
454 dwc2_hcd_queue_transactions(hsotg, tr_type);
7359d482
PZ		 455 }
456
9bda1aac 457 return 0;
7359d482
PZ		 458}
459
460/* Must be called with interrupt disabled and spinlock held */
461static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
462 struct dwc2_hcd_urb *urb)
463{
464 struct dwc2_qh *qh;
465 struct dwc2_qtd *urb_qtd;
466
467 urb_qtd = urb->qtd;
468 if (!urb_qtd) {
469 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
470 return -EINVAL;
471 }
472
473 qh = urb_qtd->qh;
474 if (!qh) {
475 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
476 return -EINVAL;
477 }
478
0d012b98
PZ		 479 urb->priv = NULL;
480
7359d482
PZ		 481 if (urb_qtd->in_process && qh->channel) {
482 dwc2_dump_channel_info(hsotg, qh->channel);
483
484 /* The QTD is in process (it has been assigned to a channel) */
485 if (hsotg->flags.b.port_connect_status)
486 /*
487 * If still connected (i.e. in host mode), halt the
488 * channel so it can be used for other transfers. If
489 * no longer connected, the host registers can't be
490 * written to halt the channel since the core is in
491 * device mode.
492 */
493 dwc2_hc_halt(hsotg, qh->channel,
494 DWC2_HC_XFER_URB_DEQUEUE);
495 }
496
497 /*
498 * Free the QTD and clean up the associated QH. Leave the QH in the
499 * schedule if it has any remaining QTDs.
500 */
501 if (hsotg->core_params->dma_desc_enable <= 0) {
502 u8 in_process = urb_qtd->in_process;
503
504 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
505 if (in_process) {
506 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
507 qh->channel = NULL;
508 } else if (list_empty(&qh->qtd_list)) {
509 dwc2_hcd_qh_unlink(hsotg, qh);
510 }
511 } else {
512 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
513 }
514
515 return 0;
516}
517
518/* Must NOT be called with interrupt disabled or spinlock held */
519static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
520 struct usb_host_endpoint *ep, int retry)
521{
522 struct dwc2_qtd *qtd, *qtd_tmp;
523 struct dwc2_qh *qh;
524 unsigned long flags;
525 int rc;
526
527 spin_lock_irqsave(&hsotg->lock, flags);
528
529 qh = ep->hcpriv;
530 if (!qh) {
531 rc = -EINVAL;
532 goto err;
533 }
534
535 while (!list_empty(&qh->qtd_list) && retry--) {
536 if (retry == 0) {
537 dev_err(hsotg->dev,
538 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
539 rc = -EBUSY;
540 goto err;
541 }
542
543 spin_unlock_irqrestore(&hsotg->lock, flags);
544 usleep_range(20000, 40000);
545 spin_lock_irqsave(&hsotg->lock, flags);
546 qh = ep->hcpriv;
547 if (!qh) {
548 rc = -EINVAL;
549 goto err;
550 }
551 }
552
553 dwc2_hcd_qh_unlink(hsotg, qh);
554
555 /* Free each QTD in the QH's QTD list */
556 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
557 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
558
559 ep->hcpriv = NULL;
16e80218
DA		 560
561 if (qh->channel && qh->channel->qh == qh)
562 qh->channel->qh = NULL;
563
7359d482 564 spin_unlock_irqrestore(&hsotg->lock, flags);
16e80218 565
7359d482
PZ		 566 dwc2_hcd_qh_free(hsotg, qh);
567
568 return 0;
569
570err:
571 ep->hcpriv = NULL;
572 spin_unlock_irqrestore(&hsotg->lock, flags);
573
574 return rc;
575}
576
577/* Must be called with interrupt disabled and spinlock held */
578static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
579 struct usb_host_endpoint *ep)
580{
581 struct dwc2_qh *qh = ep->hcpriv;
582
583 if (!qh)
584 return -EINVAL;
585
586 qh->data_toggle = DWC2_HC_PID_DATA0;
587
588 return 0;
589}
590
591/*
592 * Initializes dynamic portions of the DWC_otg HCD state
593 *
594 * Must be called with interrupt disabled and spinlock held
595 */
596static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
597{
598 struct dwc2_host_chan *chan, *chan_tmp;
599 int num_channels;
600 int i;
601
602 hsotg->flags.d32 = 0;
7359d482 603 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
20f2eb9c
DC		 604
605 if (hsotg->core_params->uframe_sched > 0) {
606 hsotg->available_host_channels =
607 hsotg->core_params->host_channels;
608 } else {
609 hsotg->non_periodic_channels = 0;
610 hsotg->periodic_channels = 0;
611 }
7359d482
PZ		 612
613 /*
614 * Put all channels in the free channel list and clean up channel
615 * states
616 */
617 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
618 hc_list_entry)
619 list_del_init(&chan->hc_list_entry);
620
621 num_channels = hsotg->core_params->host_channels;
622 for (i = 0; i < num_channels; i++) {
623 chan = hsotg->hc_ptr_array[i];
624 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
625 dwc2_hc_cleanup(hsotg, chan);
626 }
627
628 /* Initialize the DWC core for host mode operation */
629 dwc2_core_host_init(hsotg);
630}
631
632static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
633 struct dwc2_host_chan *chan,
634 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
635{
636 int hub_addr, hub_port;
637
638 chan->do_split = 1;
639 chan->xact_pos = qtd->isoc_split_pos;
640 chan->complete_split = qtd->complete_split;
641 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
642 chan->hub_addr = (u8)hub_addr;
643 chan->hub_port = (u8)hub_port;
644}
645
3bc04e28
DA		 646static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
647 struct dwc2_host_chan *chan,
648 struct dwc2_qtd *qtd)
7359d482
PZ		 649{
650 struct dwc2_hcd_urb *urb = qtd->urb;
651 struct dwc2_hcd_iso_packet_desc *frame_desc;
652
653 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
654 case USB_ENDPOINT_XFER_CONTROL:
655 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
656
657 switch (qtd->control_phase) {
658 case DWC2_CONTROL_SETUP:
659 dev_vdbg(hsotg->dev, " Control setup transaction\n");
660 chan->do_ping = 0;
661 chan->ep_is_in = 0;
662 chan->data_pid_start = DWC2_HC_PID_SETUP;
663 if (hsotg->core_params->dma_enable > 0)
664 chan->xfer_dma = urb->setup_dma;
665 else
666 chan->xfer_buf = urb->setup_packet;
667 chan->xfer_len = 8;
7359d482
PZ		 668 break;
669
670 case DWC2_CONTROL_DATA:
671 dev_vdbg(hsotg->dev, " Control data transaction\n");
672 chan->data_pid_start = qtd->data_toggle;
673 break;
674
675 case DWC2_CONTROL_STATUS:
676 /*
677 * Direction is opposite of data direction or IN if no
678 * data
679 */
680 dev_vdbg(hsotg->dev, " Control status transaction\n");
681 if (urb->length == 0)
682 chan->ep_is_in = 1;
683 else
684 chan->ep_is_in =
685 dwc2_hcd_is_pipe_out(&urb->pipe_info);
686 if (chan->ep_is_in)
687 chan->do_ping = 0;
688 chan->data_pid_start = DWC2_HC_PID_DATA1;
689 chan->xfer_len = 0;
690 if (hsotg->core_params->dma_enable > 0)
691 chan->xfer_dma = hsotg->status_buf_dma;
692 else
693 chan->xfer_buf = hsotg->status_buf;
7359d482
PZ		 694 break;
695 }
696 break;
697
698 case USB_ENDPOINT_XFER_BULK:
699 chan->ep_type = USB_ENDPOINT_XFER_BULK;
700 break;
701
702 case USB_ENDPOINT_XFER_INT:
703 chan->ep_type = USB_ENDPOINT_XFER_INT;
704 break;
705
706 case USB_ENDPOINT_XFER_ISOC:
707 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
708 if (hsotg->core_params->dma_desc_enable > 0)
709 break;
710
711 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
712 frame_desc->status = 0;
713
714 if (hsotg->core_params->dma_enable > 0) {
715 chan->xfer_dma = urb->dma;
716 chan->xfer_dma += frame_desc->offset +
717 qtd->isoc_split_offset;
718 } else {
719 chan->xfer_buf = urb->buf;
720 chan->xfer_buf += frame_desc->offset +
721 qtd->isoc_split_offset;
722 }
723
724 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
725
7359d482
PZ		 726 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
727 if (chan->xfer_len <= 188)
728 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
729 else
730 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
731 }
732 break;
733 }
3bc04e28
DA		 734}
735
736#define DWC2_USB_DMA_ALIGN 4
737
738struct dma_aligned_buffer {
739 void *kmalloc_ptr;
740 void *old_xfer_buffer;
741 u8 data[0];
742};
743
744static void dwc2_free_dma_aligned_buffer(struct urb *urb)
745{
746 struct dma_aligned_buffer *temp;
747
748 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
749 return;
7359d482 750
3bc04e28
DA		 751 temp = container_of(urb->transfer_buffer,
752 struct dma_aligned_buffer, data);
753
754 if (usb_urb_dir_in(urb))
755 memcpy(temp->old_xfer_buffer, temp->data,
756 urb->transfer_buffer_length);
757 urb->transfer_buffer = temp->old_xfer_buffer;
758 kfree(temp->kmalloc_ptr);
759
760 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
7359d482
PZ		 761}
762
3bc04e28 763static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
7359d482 764{
3bc04e28
DA		 765 struct dma_aligned_buffer *temp, *kmalloc_ptr;
766 size_t kmalloc_size;
7359d482 767
3bc04e28
DA		 768 if (urb->num_sgs || urb->sg ||
769 urb->transfer_buffer_length == 0 ||
770 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
771 return 0;
5dce9555 772
3bc04e28
DA		 773 /* Allocate a buffer with enough padding for alignment */
774 kmalloc_size = urb->transfer_buffer_length +
775 sizeof(struct dma_aligned_buffer) + DWC2_USB_DMA_ALIGN - 1;
7359d482 776
3bc04e28
DA		 777 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
778 if (!kmalloc_ptr)
779 return -ENOMEM;
5dce9555 780
3bc04e28
DA		 781 /* Position our struct dma_aligned_buffer such that data is aligned */
782 temp = PTR_ALIGN(kmalloc_ptr + 1, DWC2_USB_DMA_ALIGN) - 1;
783 temp->kmalloc_ptr = kmalloc_ptr;
784 temp->old_xfer_buffer = urb->transfer_buffer;
785 if (usb_urb_dir_out(urb))
786 memcpy(temp->data, urb->transfer_buffer,
787 urb->transfer_buffer_length);
788 urb->transfer_buffer = temp->data;
7359d482 789
3bc04e28 790 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
db62b9a8 791
7359d482
PZ		 792 return 0;
793}
794
3bc04e28
DA		 795static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
796 gfp_t mem_flags)
797{
798 int ret;
799
800 /* We assume setup_dma is always aligned; warn if not */
801 WARN_ON_ONCE(urb->setup_dma &&
802 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
803
804 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
805 if (ret)
806 return ret;
807
808 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
809 if (ret)
810 dwc2_free_dma_aligned_buffer(urb);
811
812 return ret;
813}
814
815static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
816{
817 usb_hcd_unmap_urb_for_dma(hcd, urb);
818 dwc2_free_dma_aligned_buffer(urb);
819}
820
7359d482
PZ		 821/**
822 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
823 * channel and initializes the host channel to perform the transactions. The
824 * host channel is removed from the free list.
825 *
826 * @hsotg: The HCD state structure
827 * @qh: Transactions from the first QTD for this QH are selected and assigned
828 * to a free host channel
829 */
20f2eb9c 830static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
7359d482
PZ		 831{
832 struct dwc2_host_chan *chan;
833 struct dwc2_hcd_urb *urb;
834 struct dwc2_qtd *qtd;
7359d482 835
b49977a6
MK		 836 if (dbg_qh(qh))
837 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
7359d482
PZ		 838
839 if (list_empty(&qh->qtd_list)) {
840 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
20f2eb9c 841 return -ENOMEM;
7359d482
PZ		 842 }
843
844 if (list_empty(&hsotg->free_hc_list)) {
845 dev_dbg(hsotg->dev, "No free channel to assign\n");
20f2eb9c 846 return -ENOMEM;
7359d482
PZ		 847 }
848
849 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
850 hc_list_entry);
851
20f2eb9c 852 /* Remove host channel from free list */
7359d482
PZ		 853 list_del_init(&chan->hc_list_entry);
854
855 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
856 urb = qtd->urb;
857 qh->channel = chan;
858 qtd->in_process = 1;
859
860 /*
861 * Use usb_pipedevice to determine device address. This address is
862 * 0 before the SET_ADDRESS command and the correct address afterward.
863 */
864 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
865 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
866 chan->speed = qh->dev_speed;
867 chan->max_packet = dwc2_max_packet(qh->maxp);
868
869 chan->xfer_started = 0;
870 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
871 chan->error_state = (qtd->error_count > 0);
872 chan->halt_on_queue = 0;
873 chan->halt_pending = 0;
874 chan->requests = 0;
875
876 /*
877 * The following values may be modified in the transfer type section
878 * below. The xfer_len value may be reduced when the transfer is
879 * started to accommodate the max widths of the XferSize and PktCnt
880 * fields in the HCTSIZn register.
881 */
882
883 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
884 if (chan->ep_is_in)
885 chan->do_ping = 0;
886 else
887 chan->do_ping = qh->ping_state;
888
889 chan->data_pid_start = qh->data_toggle;
890 chan->multi_count = 1;
891
bb6c3422
RK		 892 if (urb->actual_length > urb->length &&
893 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
84181086
PZ		 894 urb->actual_length = urb->length;
895
3bc04e28 896 if (hsotg->core_params->dma_enable > 0)
7359d482 897 chan->xfer_dma = urb->dma + urb->actual_length;
3bc04e28 898 else
7359d482 899 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
7359d482
PZ		 900
901 chan->xfer_len = urb->length - urb->actual_length;
902 chan->xfer_count = 0;
903
904 /* Set the split attributes if required */
905 if (qh->do_split)
906 dwc2_hc_init_split(hsotg, chan, qtd, urb);
907 else
908 chan->do_split = 0;
909
910 /* Set the transfer attributes */
3bc04e28 911 dwc2_hc_init_xfer(hsotg, chan, qtd);
7359d482
PZ		 912
913 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
914 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
915 /*
916 * This value may be modified when the transfer is started
917 * to reflect the actual transfer length
918 */
919 chan->multi_count = dwc2_hb_mult(qh->maxp);
920
95105a99 921 if (hsotg->core_params->dma_desc_enable > 0) {
7359d482 922 chan->desc_list_addr = qh->desc_list_dma;
95105a99
GH		 923 chan->desc_list_sz = qh->desc_list_sz;
924 }
7359d482
PZ		 925
926 dwc2_hc_init(hsotg, chan);
927 chan->qh = qh;
20f2eb9c
DC		 928
929 return 0;
7359d482
PZ		 930}
931
932/**
933 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
934 * schedule and assigns them to available host channels. Called from the HCD
935 * interrupt handler functions.
936 *
937 * @hsotg: The HCD state structure
938 *
939 * Return: The types of new transactions that were assigned to host channels
940 */
941enum dwc2_transaction_type dwc2_hcd_select_transactions(
942 struct dwc2_hsotg *hsotg)
943{
944 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
945 struct list_head *qh_ptr;
946 struct dwc2_qh *qh;
947 int num_channels;
948
949#ifdef DWC2_DEBUG_SOF
950 dev_vdbg(hsotg->dev, " Select Transactions\n");
951#endif
952
953 /* Process entries in the periodic ready list */
954 qh_ptr = hsotg->periodic_sched_ready.next;
955 while (qh_ptr != &hsotg->periodic_sched_ready) {
956 if (list_empty(&hsotg->free_hc_list))
957 break;
20f2eb9c
DC		 958 if (hsotg->core_params->uframe_sched > 0) {
959 if (hsotg->available_host_channels <= 1)
960 break;
961 hsotg->available_host_channels--;
962 }
7359d482 963 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
20f2eb9c
DC		 964 if (dwc2_assign_and_init_hc(hsotg, qh))
965 break;
7359d482
PZ		 966
967 /*
968 * Move the QH from the periodic ready schedule to the
969 * periodic assigned schedule
970 */
971 qh_ptr = qh_ptr->next;
94ef7aee
DA		 972 list_move_tail(&qh->qh_list_entry,
973 &hsotg->periodic_sched_assigned);
7359d482
PZ		 974 ret_val = DWC2_TRANSACTION_PERIODIC;
975 }
976
977 /*
978 * Process entries in the inactive portion of the non-periodic
979 * schedule. Some free host channels may not be used if they are
980 * reserved for periodic transfers.
981 */
982 num_channels = hsotg->core_params->host_channels;
983 qh_ptr = hsotg->non_periodic_sched_inactive.next;
984 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
20f2eb9c
DC		 985 if (hsotg->core_params->uframe_sched <= 0 &&
986 hsotg->non_periodic_channels >= num_channels -
7359d482
PZ		 987 hsotg->periodic_channels)
988 break;
989 if (list_empty(&hsotg->free_hc_list))
990 break;
991 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
20f2eb9c
DC		 992 if (hsotg->core_params->uframe_sched > 0) {
993 if (hsotg->available_host_channels < 1)
994 break;
995 hsotg->available_host_channels--;
996 }
997
998 if (dwc2_assign_and_init_hc(hsotg, qh))
999 break;
7359d482
PZ		 1000
1001 /*
1002 * Move the QH from the non-periodic inactive schedule to the
1003 * non-periodic active schedule
1004 */
1005 qh_ptr = qh_ptr->next;
94ef7aee
DA		 1006 list_move_tail(&qh->qh_list_entry,
1007 &hsotg->non_periodic_sched_active);
7359d482
PZ		 1008
1009 if (ret_val == DWC2_TRANSACTION_NONE)
1010 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
1011 else
1012 ret_val = DWC2_TRANSACTION_ALL;
1013
20f2eb9c
DC		 1014 if (hsotg->core_params->uframe_sched <= 0)
1015 hsotg->non_periodic_channels++;
7359d482
PZ		 1016 }
1017
1018 return ret_val;
1019}
1020
1021/**
1022 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
1023 * a host channel associated with either a periodic or non-periodic transfer
1024 *
1025 * @hsotg: The HCD state structure
1026 * @chan: Host channel descriptor associated with either a periodic or
1027 * non-periodic transfer
1028 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
1029 * for periodic transfers or the non-periodic Tx FIFO
1030 * for non-periodic transfers
1031 *
1032 * Return: 1 if a request is queued and more requests may be needed to
1033 * complete the transfer, 0 if no more requests are required for this
1034 * transfer, -1 if there is insufficient space in the Tx FIFO
1035 *
1036 * This function assumes that there is space available in the appropriate
1037 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
1038 * it checks whether space is available in the appropriate Tx FIFO.
1039 *
1040 * Must be called with interrupt disabled and spinlock held
1041 */
1042static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
1043 struct dwc2_host_chan *chan,
1044 u16 fifo_dwords_avail)
1045{
1046 int retval = 0;
1047
1048 if (hsotg->core_params->dma_enable > 0) {
1049 if (hsotg->core_params->dma_desc_enable > 0) {
1050 if (!chan->xfer_started ||
1051 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1052 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
1053 chan->qh->ping_state = 0;
1054 }
1055 } else if (!chan->xfer_started) {
1056 dwc2_hc_start_transfer(hsotg, chan);
1057 chan->qh->ping_state = 0;
1058 }
1059 } else if (chan->halt_pending) {
1060 /* Don't queue a request if the channel has been halted */
1061 } else if (chan->halt_on_queue) {
1062 dwc2_hc_halt(hsotg, chan, chan->halt_status);
1063 } else if (chan->do_ping) {
1064 if (!chan->xfer_started)
1065 dwc2_hc_start_transfer(hsotg, chan);
1066 } else if (!chan->ep_is_in ||
1067 chan->data_pid_start == DWC2_HC_PID_SETUP) {
1068 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
1069 if (!chan->xfer_started) {
1070 dwc2_hc_start_transfer(hsotg, chan);
1071 retval = 1;
1072 } else {
1073 retval = dwc2_hc_continue_transfer(hsotg, chan);
1074 }
1075 } else {
1076 retval = -1;
1077 }
1078 } else {
1079 if (!chan->xfer_started) {
1080 dwc2_hc_start_transfer(hsotg, chan);
1081 retval = 1;
1082 } else {
1083 retval = dwc2_hc_continue_transfer(hsotg, chan);
1084 }
1085 }
1086
1087 return retval;
1088}
1089
1090/*
1091 * Processes periodic channels for the next frame and queues transactions for
1092 * these channels to the DWC_otg controller. After queueing transactions, the
1093 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1094 * to queue as Periodic Tx FIFO or request queue space becomes available.
1095 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1096 *
1097 * Must be called with interrupt disabled and spinlock held
1098 */
1099static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
1100{
1101 struct list_head *qh_ptr;
1102 struct dwc2_qh *qh;
1103 u32 tx_status;
1104 u32 fspcavail;
1105 u32 gintmsk;
1106 int status;
1107 int no_queue_space = 0;
1108 int no_fifo_space = 0;
1109 u32 qspcavail;
1110
b49977a6
MK		 1111 if (dbg_perio())
1112 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
7359d482 1113
95c8bc36 1114 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
d6ec53e0
MK		 1115 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1116 TXSTS_QSPCAVAIL_SHIFT;
1117 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1118 TXSTS_FSPCAVAIL_SHIFT;
b49977a6
MK		 1119
1120 if (dbg_perio()) {
1121 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
1122 qspcavail);
1123 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
1124 fspcavail);
1125 }
7359d482
PZ		 1126
1127 qh_ptr = hsotg->periodic_sched_assigned.next;
1128 while (qh_ptr != &hsotg->periodic_sched_assigned) {
95c8bc36 1129 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
acdb9046
MK		 1130 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1131 TXSTS_QSPCAVAIL_SHIFT;
1132 if (qspcavail == 0) {
7359d482
PZ		 1133 no_queue_space = 1;
1134 break;
1135 }
1136
1137 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
1138 if (!qh->channel) {
1139 qh_ptr = qh_ptr->next;
1140 continue;
1141 }
1142
1143 /* Make sure EP's TT buffer is clean before queueing qtds */
1144 if (qh->tt_buffer_dirty) {
1145 qh_ptr = qh_ptr->next;
1146 continue;
1147 }
1148
1149 /*
1150 * Set a flag if we're queuing high-bandwidth in slave mode.
1151 * The flag prevents any halts to get into the request queue in
1152 * the middle of multiple high-bandwidth packets getting queued.
1153 */
1154 if (hsotg->core_params->dma_enable <= 0 &&
1155 qh->channel->multi_count > 1)
1156 hsotg->queuing_high_bandwidth = 1;
1157
d6ec53e0
MK		 1158 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1159 TXSTS_FSPCAVAIL_SHIFT;
7359d482
PZ		 1160 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1161 if (status < 0) {
1162 no_fifo_space = 1;
1163 break;
1164 }
1165
1166 /*
1167 * In Slave mode, stay on the current transfer until there is
1168 * nothing more to do or the high-bandwidth request count is
1169 * reached. In DMA mode, only need to queue one request. The
1170 * controller automatically handles multiple packets for
1171 * high-bandwidth transfers.
1172 */
1173 if (hsotg->core_params->dma_enable > 0 || status == 0 ||
1174 qh->channel->requests == qh->channel->multi_count) {
1175 qh_ptr = qh_ptr->next;
1176 /*
1177 * Move the QH from the periodic assigned schedule to
1178 * the periodic queued schedule
1179 */
94ef7aee
DA		 1180 list_move_tail(&qh->qh_list_entry,
1181 &hsotg->periodic_sched_queued);
7359d482
PZ		 1182
1183 /* done queuing high bandwidth */
1184 hsotg->queuing_high_bandwidth = 0;
1185 }
1186 }
1187
1188 if (hsotg->core_params->dma_enable <= 0) {
95c8bc36 1189 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
d6ec53e0
MK		 1190 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1191 TXSTS_QSPCAVAIL_SHIFT;
1192 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1193 TXSTS_FSPCAVAIL_SHIFT;
b49977a6
MK		 1194 if (dbg_perio()) {
1195 dev_vdbg(hsotg->dev,
1196 " P Tx Req Queue Space Avail (after queue): %d\n",
1197 qspcavail);
1198 dev_vdbg(hsotg->dev,
1199 " P Tx FIFO Space Avail (after queue): %d\n",
1200 fspcavail);
1201 }
7359d482
PZ		 1202
1203 if (!list_empty(&hsotg->periodic_sched_assigned) ||
1204 no_queue_space || no_fifo_space) {
1205 /*
1206 * May need to queue more transactions as the request
1207 * queue or Tx FIFO empties. Enable the periodic Tx
1208 * FIFO empty interrupt. (Always use the half-empty
1209 * level to ensure that new requests are loaded as
1210 * soon as possible.)
1211 */
95c8bc36 1212 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
7359d482 1213 gintmsk |= GINTSTS_PTXFEMP;
95c8bc36 1214 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
7359d482
PZ		 1215 } else {
1216 /*
1217 * Disable the Tx FIFO empty interrupt since there are
1218 * no more transactions that need to be queued right
1219 * now. This function is called from interrupt
1220 * handlers to queue more transactions as transfer
1221 * states change.
1222 */
95c8bc36 1223 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
7359d482 1224 gintmsk &= ~GINTSTS_PTXFEMP;
95c8bc36 1225 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
7359d482
PZ		 1226 }
1227 }
1228}
1229
1230/*
1231 * Processes active non-periodic channels and queues transactions for these
1232 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1233 * FIFO Empty interrupt is enabled if there are more transactions to queue as
1234 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1235 * FIFO Empty interrupt is disabled.
1236 *
1237 * Must be called with interrupt disabled and spinlock held
1238 */
1239static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
1240{
1241 struct list_head *orig_qh_ptr;
1242 struct dwc2_qh *qh;
1243 u32 tx_status;
1244 u32 qspcavail;
1245 u32 fspcavail;
1246 u32 gintmsk;
1247 int status;
1248 int no_queue_space = 0;
1249 int no_fifo_space = 0;
1250 int more_to_do = 0;
1251
1252 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
1253
95c8bc36 1254 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
d6ec53e0
MK		 1255 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1256 TXSTS_QSPCAVAIL_SHIFT;
1257 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1258 TXSTS_FSPCAVAIL_SHIFT;
7359d482
PZ		 1259 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
1260 qspcavail);
1261 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
1262 fspcavail);
1263
1264 /*
1265 * Keep track of the starting point. Skip over the start-of-list
1266 * entry.
1267 */
1268 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
1269 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1270 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
1271
1272 /*
1273 * Process once through the active list or until no more space is
1274 * available in the request queue or the Tx FIFO
1275 */
1276 do {
95c8bc36 1277 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
d6ec53e0
MK		 1278 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1279 TXSTS_QSPCAVAIL_SHIFT;
7359d482
PZ		 1280 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
1281 no_queue_space = 1;
1282 break;
1283 }
1284
1285 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
1286 qh_list_entry);
1287 if (!qh->channel)
1288 goto next;
1289
1290 /* Make sure EP's TT buffer is clean before queueing qtds */
1291 if (qh->tt_buffer_dirty)
1292 goto next;
1293
d6ec53e0
MK		 1294 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1295 TXSTS_FSPCAVAIL_SHIFT;
7359d482
PZ		 1296 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1297
1298 if (status > 0) {
1299 more_to_do = 1;
1300 } else if (status < 0) {
1301 no_fifo_space = 1;
1302 break;
1303 }
1304next:
1305 /* Advance to next QH, skipping start-of-list entry */
1306 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1307 if (hsotg->non_periodic_qh_ptr ==
1308 &hsotg->non_periodic_sched_active)
1309 hsotg->non_periodic_qh_ptr =
1310 hsotg->non_periodic_qh_ptr->next;
1311 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
1312
1313 if (hsotg->core_params->dma_enable <= 0) {
95c8bc36 1314 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
d6ec53e0
MK		 1315 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1316 TXSTS_QSPCAVAIL_SHIFT;
1317 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1318 TXSTS_FSPCAVAIL_SHIFT;
7359d482
PZ		 1319 dev_vdbg(hsotg->dev,
1320 " NP Tx Req Queue Space Avail (after queue): %d\n",
1321 qspcavail);
1322 dev_vdbg(hsotg->dev,
1323 " NP Tx FIFO Space Avail (after queue): %d\n",
1324 fspcavail);
1325
1326 if (more_to_do || no_queue_space || no_fifo_space) {
1327 /*
1328 * May need to queue more transactions as the request
1329 * queue or Tx FIFO empties. Enable the non-periodic
1330 * Tx FIFO empty interrupt. (Always use the half-empty
1331 * level to ensure that new requests are loaded as
1332 * soon as possible.)
1333 */
95c8bc36 1334 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
7359d482 1335 gintmsk |= GINTSTS_NPTXFEMP;
95c8bc36 1336 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
7359d482
PZ		 1337 } else {
1338 /*
1339 * Disable the Tx FIFO empty interrupt since there are
1340 * no more transactions that need to be queued right
1341 * now. This function is called from interrupt
1342 * handlers to queue more transactions as transfer
1343 * states change.
1344 */
95c8bc36 1345 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
7359d482 1346 gintmsk &= ~GINTSTS_NPTXFEMP;
95c8bc36 1347 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
7359d482
PZ		 1348 }
1349 }
1350}
1351
1352/**
1353 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
1354 * and queues transactions for these channels to the DWC_otg controller. Called
1355 * from the HCD interrupt handler functions.
1356 *
1357 * @hsotg: The HCD state structure
1358 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
1359 * or both)
1360 *
1361 * Must be called with interrupt disabled and spinlock held
1362 */
1363void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
1364 enum dwc2_transaction_type tr_type)
1365{
1366#ifdef DWC2_DEBUG_SOF
1367 dev_vdbg(hsotg->dev, "Queue Transactions\n");
1368#endif
1369 /* Process host channels associated with periodic transfers */
1370 if ((tr_type == DWC2_TRANSACTION_PERIODIC ||
1371 tr_type == DWC2_TRANSACTION_ALL) &&
1372 !list_empty(&hsotg->periodic_sched_assigned))
1373 dwc2_process_periodic_channels(hsotg);
1374
1375 /* Process host channels associated with non-periodic transfers */
1376 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
1377 tr_type == DWC2_TRANSACTION_ALL) {
1378 if (!list_empty(&hsotg->non_periodic_sched_active)) {
1379 dwc2_process_non_periodic_channels(hsotg);
1380 } else {
1381 /*
1382 * Ensure NP Tx FIFO empty interrupt is disabled when
1383 * there are no non-periodic transfers to process
1384 */
95c8bc36 1385 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
7359d482
PZ		 1386
1387 gintmsk &= ~GINTSTS_NPTXFEMP;
95c8bc36 1388 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
7359d482
PZ		 1389 }
1390 }
1391}
1392
1393static void dwc2_conn_id_status_change(struct work_struct *work)
1394{
1395 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
1396 wf_otg);
1397 u32 count = 0;
1398 u32 gotgctl;
5390d438 1399 unsigned long flags;
7359d482
PZ		 1400
1401 dev_dbg(hsotg->dev, "%s()\n", __func__);
1402
95c8bc36 1403 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
7359d482
PZ		 1404 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
1405 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
1406 !!(gotgctl & GOTGCTL_CONID_B));
1407
1408 /* B-Device connector (Device Mode) */
1409 if (gotgctl & GOTGCTL_CONID_B) {
1410 /* Wait for switch to device mode */
1411 dev_dbg(hsotg->dev, "connId B\n");
1412 while (!dwc2_is_device_mode(hsotg)) {
1413 dev_info(hsotg->dev,
1414 "Waiting for Peripheral Mode, Mode=%s\n",
1415 dwc2_is_host_mode(hsotg) ? "Host" :
1416 "Peripheral");
1417 usleep_range(20000, 40000);
1418 if (++count > 250)
1419 break;
1420 }
1421 if (count > 250)
1422 dev_err(hsotg->dev,
de9169a1 1423 "Connection id status change timed out\n");
7359d482 1424 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
0fe239bc 1425 dwc2_core_init(hsotg, false);
7359d482 1426 dwc2_enable_global_interrupts(hsotg);
5390d438 1427 spin_lock_irqsave(&hsotg->lock, flags);
1f91b4cc 1428 dwc2_hsotg_core_init_disconnected(hsotg, false);
5390d438 1429 spin_unlock_irqrestore(&hsotg->lock, flags);
1f91b4cc 1430 dwc2_hsotg_core_connect(hsotg);
7359d482
PZ		 1431 } else {
1432 /* A-Device connector (Host Mode) */
1433 dev_dbg(hsotg->dev, "connId A\n");
1434 while (!dwc2_is_host_mode(hsotg)) {
1435 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
1436 dwc2_is_host_mode(hsotg) ?
1437 "Host" : "Peripheral");
1438 usleep_range(20000, 40000);
1439 if (++count > 250)
1440 break;
1441 }
1442 if (count > 250)
1443 dev_err(hsotg->dev,
de9169a1 1444 "Connection id status change timed out\n");
7359d482
PZ		 1445 hsotg->op_state = OTG_STATE_A_HOST;
1446
1447 /* Initialize the Core for Host mode */
0fe239bc 1448 dwc2_core_init(hsotg, false);
7359d482
PZ		 1449 dwc2_enable_global_interrupts(hsotg);
1450 dwc2_hcd_start(hsotg);
1451 }
1452}
1453
1454static void dwc2_wakeup_detected(unsigned long data)
1455{
1456 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
1457 u32 hprt0;
1458
1459 dev_dbg(hsotg->dev, "%s()\n", __func__);
1460
1461 /*
1462 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
1463 * so that OPT tests pass with all PHYs.)
1464 */
1465 hprt0 = dwc2_read_hprt0(hsotg);
1466 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
1467 hprt0 &= ~HPRT0_RES;
95c8bc36 1468 dwc2_writel(hprt0, hsotg->regs + HPRT0);
7359d482 1469 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
95c8bc36 1470 dwc2_readl(hsotg->regs + HPRT0));
7359d482
PZ		 1471
1472 dwc2_hcd_rem_wakeup(hsotg);
1fb7f12d 1473 hsotg->bus_suspended = 0;
7359d482
PZ		 1474
1475 /* Change to L0 state */
1476 hsotg->lx_state = DWC2_L0;
1477}
1478
1479static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1480{
1481 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
1482
1483 return hcd->self.b_hnp_enable;
1484}
1485
1486/* Must NOT be called with interrupt disabled or spinlock held */
1487static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1488{
1489 unsigned long flags;
1490 u32 hprt0;
1491 u32 pcgctl;
1492 u32 gotgctl;
1493
1494 dev_dbg(hsotg->dev, "%s()\n", __func__);
1495
1496 spin_lock_irqsave(&hsotg->lock, flags);
1497
1498 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
95c8bc36 1499 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
7359d482 1500 gotgctl |= GOTGCTL_HSTSETHNPEN;
95c8bc36 1501 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
7359d482
PZ		 1502 hsotg->op_state = OTG_STATE_A_SUSPEND;
1503 }
1504
1505 hprt0 = dwc2_read_hprt0(hsotg);
1506 hprt0 |= HPRT0_SUSP;
95c8bc36 1507 dwc2_writel(hprt0, hsotg->regs + HPRT0);
7359d482 1508
734643df 1509 hsotg->bus_suspended = 1;
7359d482 1510
a2a23d3f
GH		 1511 /*
1512 * If hibernation is supported, Phy clock will be suspended
1513 * after registers are backuped.
1514 */
1515 if (!hsotg->core_params->hibernation) {
1516 /* Suspend the Phy Clock */
1517 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1518 pcgctl |= PCGCTL_STOPPCLK;
1519 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
1520 udelay(10);
1521 }
7359d482
PZ		 1522
1523 /* For HNP the bus must be suspended for at least 200ms */
1524 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
95c8bc36 1525 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
7359d482 1526 pcgctl &= ~PCGCTL_STOPPCLK;
95c8bc36 1527 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
7359d482
PZ		 1528
1529 spin_unlock_irqrestore(&hsotg->lock, flags);
1530
1531 usleep_range(200000, 250000);
1532 } else {
1533 spin_unlock_irqrestore(&hsotg->lock, flags);
1534 }
1535}
1536
30db103c
GH		 1537/* Must NOT be called with interrupt disabled or spinlock held */
1538static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
1539{
1540 unsigned long flags;
1541 u32 hprt0;
1542 u32 pcgctl;
1543
4d273c2a
DA		 1544 spin_lock_irqsave(&hsotg->lock, flags);
1545
a2a23d3f
GH		 1546 /*
1547 * If hibernation is supported, Phy clock is already resumed
1548 * after registers restore.
1549 */
1550 if (!hsotg->core_params->hibernation) {
1551 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1552 pcgctl &= ~PCGCTL_STOPPCLK;
1553 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
4d273c2a 1554 spin_unlock_irqrestore(&hsotg->lock, flags);
a2a23d3f 1555 usleep_range(20000, 40000);
4d273c2a 1556 spin_lock_irqsave(&hsotg->lock, flags);
a2a23d3f 1557 }
30db103c 1558
30db103c
GH		 1559 hprt0 = dwc2_read_hprt0(hsotg);
1560 hprt0 |= HPRT0_RES;
1561 hprt0 &= ~HPRT0_SUSP;
1562 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1563 spin_unlock_irqrestore(&hsotg->lock, flags);
1564
1565 msleep(USB_RESUME_TIMEOUT);
1566
1567 spin_lock_irqsave(&hsotg->lock, flags);
1568 hprt0 = dwc2_read_hprt0(hsotg);
1569 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
1570 dwc2_writel(hprt0, hsotg->regs + HPRT0);
734643df 1571 hsotg->bus_suspended = 0;
30db103c
GH		 1572 spin_unlock_irqrestore(&hsotg->lock, flags);
1573}
1574
7359d482
PZ		 1575/* Handles hub class-specific requests */
1576static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
1577 u16 wvalue, u16 windex, char *buf, u16 wlength)
1578{
1579 struct usb_hub_descriptor *hub_desc;
1580 int retval = 0;
1581 u32 hprt0;
1582 u32 port_status;
1583 u32 speed;
1584 u32 pcgctl;
1585
1586 switch (typereq) {
1587 case ClearHubFeature:
1588 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
1589
1590 switch (wvalue) {
1591 case C_HUB_LOCAL_POWER:
1592 case C_HUB_OVER_CURRENT:
1593 /* Nothing required here */
1594 break;
1595
1596 default:
1597 retval = -EINVAL;
1598 dev_err(hsotg->dev,
1599 "ClearHubFeature request %1xh unknown\n",
1600 wvalue);
1601 }
1602 break;
1603
1604 case ClearPortFeature:
1605 if (wvalue != USB_PORT_FEAT_L1)
1606 if (!windex || windex > 1)
1607 goto error;
1608 switch (wvalue) {
1609 case USB_PORT_FEAT_ENABLE:
1610 dev_dbg(hsotg->dev,
1611 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1612 hprt0 = dwc2_read_hprt0(hsotg);
1613 hprt0 |= HPRT0_ENA;
95c8bc36 1614 dwc2_writel(hprt0, hsotg->regs + HPRT0);
7359d482
PZ		 1615 break;
1616
1617 case USB_PORT_FEAT_SUSPEND:
1618 dev_dbg(hsotg->dev,
1619 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
b0bb9bb6 1620
bea78555
GH		 1621 if (hsotg->bus_suspended)
1622 dwc2_port_resume(hsotg);
7359d482
PZ		 1623 break;
1624
1625 case USB_PORT_FEAT_POWER:
1626 dev_dbg(hsotg->dev,
1627 "ClearPortFeature USB_PORT_FEAT_POWER\n");
1628 hprt0 = dwc2_read_hprt0(hsotg);
1629 hprt0 &= ~HPRT0_PWR;
95c8bc36 1630 dwc2_writel(hprt0, hsotg->regs + HPRT0);
7359d482
PZ		 1631 break;
1632
1633 case USB_PORT_FEAT_INDICATOR:
1634 dev_dbg(hsotg->dev,
1635 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1636 /* Port indicator not supported */
1637 break;
1638
1639 case USB_PORT_FEAT_C_CONNECTION:
1640 /*
1641 * Clears driver's internal Connect Status Change flag
1642 */
1643 dev_dbg(hsotg->dev,
1644 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1645 hsotg->flags.b.port_connect_status_change = 0;
1646 break;
1647
1648 case USB_PORT_FEAT_C_RESET:
1649 /* Clears driver's internal Port Reset Change flag */
1650 dev_dbg(hsotg->dev,
1651 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1652 hsotg->flags.b.port_reset_change = 0;
1653 break;
1654
1655 case USB_PORT_FEAT_C_ENABLE:
1656 /*
1657 * Clears the driver's internal Port Enable/Disable
1658 * Change flag
1659 */
1660 dev_dbg(hsotg->dev,
1661 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1662 hsotg->flags.b.port_enable_change = 0;
1663 break;
1664
1665 case USB_PORT_FEAT_C_SUSPEND:
1666 /*
1667 * Clears the driver's internal Port Suspend Change
1668 * flag, which is set when resume signaling on the host
1669 * port is complete
1670 */
1671 dev_dbg(hsotg->dev,
1672 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1673 hsotg->flags.b.port_suspend_change = 0;
1674 break;
1675
1676 case USB_PORT_FEAT_C_PORT_L1:
1677 dev_dbg(hsotg->dev,
1678 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
1679 hsotg->flags.b.port_l1_change = 0;
1680 break;
1681
1682 case USB_PORT_FEAT_C_OVER_CURRENT:
1683 dev_dbg(hsotg->dev,
1684 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1685 hsotg->flags.b.port_over_current_change = 0;
1686 break;
1687
1688 default:
1689 retval = -EINVAL;
1690 dev_err(hsotg->dev,
1691 "ClearPortFeature request %1xh unknown or unsupported\n",
1692 wvalue);
1693 }
1694 break;
1695
1696 case GetHubDescriptor:
1697 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
1698 hub_desc = (struct usb_hub_descriptor *)buf;
1699 hub_desc->bDescLength = 9;
a5dd0395 1700 hub_desc->bDescriptorType = USB_DT_HUB;
7359d482 1701 hub_desc->bNbrPorts = 1;
3d040de8
SS		 1702 hub_desc->wHubCharacteristics =
1703 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
1704 HUB_CHAR_INDV_PORT_OCPM);
7359d482
PZ		 1705 hub_desc->bPwrOn2PwrGood = 1;
1706 hub_desc->bHubContrCurrent = 0;
1707 hub_desc->u.hs.DeviceRemovable[0] = 0;
1708 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
1709 break;
1710
1711 case GetHubStatus:
1712 dev_dbg(hsotg->dev, "GetHubStatus\n");
1713 memset(buf, 0, 4);
1714 break;
1715
1716 case GetPortStatus:
b8313417
PZ		 1717 dev_vdbg(hsotg->dev,
1718 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
1719 hsotg->flags.d32);
7359d482
PZ		 1720 if (!windex || windex > 1)
1721 goto error;
1722
1723 port_status = 0;
1724 if (hsotg->flags.b.port_connect_status_change)
1725 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
1726 if (hsotg->flags.b.port_enable_change)
1727 port_status |= USB_PORT_STAT_C_ENABLE << 16;
1728 if (hsotg->flags.b.port_suspend_change)
1729 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
1730 if (hsotg->flags.b.port_l1_change)
1731 port_status |= USB_PORT_STAT_C_L1 << 16;
1732 if (hsotg->flags.b.port_reset_change)
1733 port_status |= USB_PORT_STAT_C_RESET << 16;
1734 if (hsotg->flags.b.port_over_current_change) {
1735 dev_warn(hsotg->dev, "Overcurrent change detected\n");
1736 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1737 }
1738
1739 if (!hsotg->flags.b.port_connect_status) {
1740 /*
1741 * The port is disconnected, which means the core is
1742 * either in device mode or it soon will be. Just
1743 * return 0's for the remainder of the port status
1744 * since the port register can't be read if the core
1745 * is in device mode.
1746 */
1747 *(__le32 *)buf = cpu_to_le32(port_status);
1748 break;
1749 }
1750
95c8bc36 1751 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
b8313417 1752 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
7359d482
PZ		 1753
1754 if (hprt0 & HPRT0_CONNSTS)
1755 port_status |= USB_PORT_STAT_CONNECTION;
1756 if (hprt0 & HPRT0_ENA)
1757 port_status |= USB_PORT_STAT_ENABLE;
1758 if (hprt0 & HPRT0_SUSP)
1759 port_status |= USB_PORT_STAT_SUSPEND;
1760 if (hprt0 & HPRT0_OVRCURRACT)
1761 port_status |= USB_PORT_STAT_OVERCURRENT;
1762 if (hprt0 & HPRT0_RST)
1763 port_status |= USB_PORT_STAT_RESET;
1764 if (hprt0 & HPRT0_PWR)
1765 port_status |= USB_PORT_STAT_POWER;
1766
f9234633 1767 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
7359d482
PZ		 1768 if (speed == HPRT0_SPD_HIGH_SPEED)
1769 port_status |= USB_PORT_STAT_HIGH_SPEED;
1770 else if (speed == HPRT0_SPD_LOW_SPEED)
1771 port_status |= USB_PORT_STAT_LOW_SPEED;
1772
1773 if (hprt0 & HPRT0_TSTCTL_MASK)
1774 port_status |= USB_PORT_STAT_TEST;
1775 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1776
fbb9e22b
MYK		 1777 if (hsotg->core_params->dma_desc_fs_enable) {
1778 /*
1779 * Enable descriptor DMA only if a full speed
1780 * device is connected.
1781 */
1782 if (hsotg->new_connection &&
1783 ((port_status &
1784 (USB_PORT_STAT_CONNECTION |
1785 USB_PORT_STAT_HIGH_SPEED |
1786 USB_PORT_STAT_LOW_SPEED)) ==
1787 USB_PORT_STAT_CONNECTION)) {
1788 u32 hcfg;
1789
1790 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
1791 hsotg->core_params->dma_desc_enable = 1;
1792 hcfg = dwc2_readl(hsotg->regs + HCFG);
1793 hcfg |= HCFG_DESCDMA;
1794 dwc2_writel(hcfg, hsotg->regs + HCFG);
1795 hsotg->new_connection = false;
1796 }
1797 }
1798
b8313417 1799 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
7359d482
PZ		 1800 *(__le32 *)buf = cpu_to_le32(port_status);
1801 break;
1802
1803 case SetHubFeature:
1804 dev_dbg(hsotg->dev, "SetHubFeature\n");
1805 /* No HUB features supported */
1806 break;
1807
1808 case SetPortFeature:
1809 dev_dbg(hsotg->dev, "SetPortFeature\n");
1810 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
1811 goto error;
1812
1813 if (!hsotg->flags.b.port_connect_status) {
1814 /*
1815 * The port is disconnected, which means the core is
1816 * either in device mode or it soon will be. Just
1817 * return without doing anything since the port
1818 * register can't be written if the core is in device
1819 * mode.
1820 */
1821 break;
1822 }
1823
1824 switch (wvalue) {
1825 case USB_PORT_FEAT_SUSPEND:
1826 dev_dbg(hsotg->dev,
1827 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1828 if (windex != hsotg->otg_port)
1829 goto error;
1830 dwc2_port_suspend(hsotg, windex);
1831 break;
1832
1833 case USB_PORT_FEAT_POWER:
1834 dev_dbg(hsotg->dev,
1835 "SetPortFeature - USB_PORT_FEAT_POWER\n");
1836 hprt0 = dwc2_read_hprt0(hsotg);
1837 hprt0 |= HPRT0_PWR;
95c8bc36 1838 dwc2_writel(hprt0, hsotg->regs + HPRT0);
7359d482
PZ		 1839 break;
1840
1841 case USB_PORT_FEAT_RESET:
1842 hprt0 = dwc2_read_hprt0(hsotg);
1843 dev_dbg(hsotg->dev,
1844 "SetPortFeature - USB_PORT_FEAT_RESET\n");
95c8bc36 1845 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
7359d482 1846 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
95c8bc36 1847 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
7359d482 1848 /* ??? Original driver does this */
95c8bc36 1849 dwc2_writel(0, hsotg->regs + PCGCTL);
7359d482
PZ		 1850
1851 hprt0 = dwc2_read_hprt0(hsotg);
1852 /* Clear suspend bit if resetting from suspend state */
1853 hprt0 &= ~HPRT0_SUSP;
1854
1855 /*
1856 * When B-Host the Port reset bit is set in the Start
1857 * HCD Callback function, so that the reset is started
1858 * within 1ms of the HNP success interrupt
1859 */
1860 if (!dwc2_hcd_is_b_host(hsotg)) {
1861 hprt0 |= HPRT0_PWR | HPRT0_RST;
1862 dev_dbg(hsotg->dev,
1863 "In host mode, hprt0=%08x\n", hprt0);
95c8bc36 1864 dwc2_writel(hprt0, hsotg->regs + HPRT0);
7359d482
PZ		 1865 }
1866
1867 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1868 usleep_range(50000, 70000);
1869 hprt0 &= ~HPRT0_RST;
95c8bc36 1870 dwc2_writel(hprt0, hsotg->regs + HPRT0);
7359d482
PZ		 1871 hsotg->lx_state = DWC2_L0; /* Now back to On state */
1872 break;
1873
1874 case USB_PORT_FEAT_INDICATOR:
1875 dev_dbg(hsotg->dev,
1876 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1877 /* Not supported */
1878 break;
1879
96d480e6
JL		 1880 case USB_PORT_FEAT_TEST:
1881 hprt0 = dwc2_read_hprt0(hsotg);
1882 dev_dbg(hsotg->dev,
1883 "SetPortFeature - USB_PORT_FEAT_TEST\n");
1884 hprt0 &= ~HPRT0_TSTCTL_MASK;
1885 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
95c8bc36 1886 dwc2_writel(hprt0, hsotg->regs + HPRT0);
96d480e6
JL		 1887 break;
1888
7359d482
PZ		 1889 default:
1890 retval = -EINVAL;
1891 dev_err(hsotg->dev,
1892 "SetPortFeature %1xh unknown or unsupported\n",
1893 wvalue);
1894 break;
1895 }
1896 break;
1897
1898 default:
1899error:
1900 retval = -EINVAL;
1901 dev_dbg(hsotg->dev,
1902 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
1903 typereq, windex, wvalue);
1904 break;
1905 }
1906
1907 return retval;
1908}
1909
1910static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
1911{
1912 int retval;
1913
7359d482
PZ		 1914 if (port != 1)
1915 return -EINVAL;
1916
1917 retval = (hsotg->flags.b.port_connect_status_change ||
1918 hsotg->flags.b.port_reset_change ||
1919 hsotg->flags.b.port_enable_change ||
1920 hsotg->flags.b.port_suspend_change ||
1921 hsotg->flags.b.port_over_current_change);
1922
1923 if (retval) {
1924 dev_dbg(hsotg->dev,
1925 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
1926 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
1927 hsotg->flags.b.port_connect_status_change);
1928 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
1929 hsotg->flags.b.port_reset_change);
1930 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
1931 hsotg->flags.b.port_enable_change);
1932 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
1933 hsotg->flags.b.port_suspend_change);
1934 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
1935 hsotg->flags.b.port_over_current_change);
1936 }
1937
1938 return retval;
1939}
1940
1941int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1942{
95c8bc36 1943 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
7359d482
PZ		 1944
1945#ifdef DWC2_DEBUG_SOF
1946 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
d6ec53e0 1947 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
7359d482 1948#endif
d6ec53e0 1949 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
7359d482
PZ		 1950}
1951
1952int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
1953{
6bf2e2a5 1954 return hsotg->op_state == OTG_STATE_B_HOST;
7359d482
PZ		 1955}
1956
1957static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
1958 int iso_desc_count,
1959 gfp_t mem_flags)
1960{
1961 struct dwc2_hcd_urb *urb;
1962 u32 size = sizeof(*urb) + iso_desc_count *
1963 sizeof(struct dwc2_hcd_iso_packet_desc);
1964
1965 urb = kzalloc(size, mem_flags);
1966 if (urb)
1967 urb->packet_count = iso_desc_count;
1968 return urb;
1969}
1970
1971static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
1972 struct dwc2_hcd_urb *urb, u8 dev_addr,
1973 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
1974{
b49977a6
MK		 1975 if (dbg_perio() ||
1976 ep_type == USB_ENDPOINT_XFER_BULK ||
1977 ep_type == USB_ENDPOINT_XFER_CONTROL)
1978 dev_vdbg(hsotg->dev,
1979 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
1980 dev_addr, ep_num, ep_dir, ep_type, mps);
7359d482
PZ		 1981 urb->pipe_info.dev_addr = dev_addr;
1982 urb->pipe_info.ep_num = ep_num;
1983 urb->pipe_info.pipe_type = ep_type;
1984 urb->pipe_info.pipe_dir = ep_dir;
1985 urb->pipe_info.mps = mps;
1986}
1987
1988/*
1989 * NOTE: This function will be removed once the peripheral controller code
1990 * is integrated and the driver is stable
1991 */
1992void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
1993{
1994#ifdef DEBUG
1995 struct dwc2_host_chan *chan;
1996 struct dwc2_hcd_urb *urb;
1997 struct dwc2_qtd *qtd;
1998 int num_channels;
1999 u32 np_tx_status;
2000 u32 p_tx_status;
2001 int i;
2002
2003 num_channels = hsotg->core_params->host_channels;
2004 dev_dbg(hsotg->dev, "\n");
2005 dev_dbg(hsotg->dev,
2006 "************************************************************\n");
2007 dev_dbg(hsotg->dev, "HCD State:\n");
2008 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
2009
2010 for (i = 0; i < num_channels; i++) {
2011 chan = hsotg->hc_ptr_array[i];
2012 dev_dbg(hsotg->dev, " Channel %d:\n", i);
2013 dev_dbg(hsotg->dev,
2014 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
2015 chan->dev_addr, chan->ep_num, chan->ep_is_in);
2016 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
2017 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
2018 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
2019 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
2020 chan->data_pid_start);
2021 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
2022 dev_dbg(hsotg->dev, " xfer_started: %d\n",
2023 chan->xfer_started);
2024 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
2025 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
2026 (unsigned long)chan->xfer_dma);
2027 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
2028 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
2029 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
2030 chan->halt_on_queue);
2031 dev_dbg(hsotg->dev, " halt_pending: %d\n",
2032 chan->halt_pending);
2033 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
2034 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
2035 dev_dbg(hsotg->dev, " complete_split: %d\n",
2036 chan->complete_split);
2037 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
2038 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
2039 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
2040 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
2041 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
2042
2043 if (chan->xfer_started) {
2044 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
2045
95c8bc36
AS		 2046 hfnum = dwc2_readl(hsotg->regs + HFNUM);
2047 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2048 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
2049 hcint = dwc2_readl(hsotg->regs + HCINT(i));
2050 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
7359d482
PZ		 2051 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
2052 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
2053 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
2054 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
2055 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
2056 }
2057
2058 if (!(chan->xfer_started && chan->qh))
2059 continue;
2060
2061 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
2062 if (!qtd->in_process)
2063 break;
2064 urb = qtd->urb;
2065 dev_dbg(hsotg->dev, " URB Info:\n");
2066 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
2067 qtd, urb);
2068 if (urb) {
2069 dev_dbg(hsotg->dev,
2070 " Dev: %d, EP: %d %s\n",
2071 dwc2_hcd_get_dev_addr(&urb->pipe_info),
2072 dwc2_hcd_get_ep_num(&urb->pipe_info),
2073 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
2074 "IN" : "OUT");
2075 dev_dbg(hsotg->dev,
2076 " Max packet size: %d\n",
2077 dwc2_hcd_get_mps(&urb->pipe_info));
2078 dev_dbg(hsotg->dev,
2079 " transfer_buffer: %p\n",
2080 urb->buf);
157dfaac
PZ		 2081 dev_dbg(hsotg->dev,
2082 " transfer_dma: %08lx\n",
2083 (unsigned long)urb->dma);
7359d482
PZ		 2084 dev_dbg(hsotg->dev,
2085 " transfer_buffer_length: %d\n",
2086 urb->length);
2087 dev_dbg(hsotg->dev, " actual_length: %d\n",
2088 urb->actual_length);
2089 }
2090 }
2091 }
2092
2093 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
2094 hsotg->non_periodic_channels);
2095 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
2096 hsotg->periodic_channels);
2097 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
95c8bc36 2098 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
7359d482 2099 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
d6ec53e0 2100 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
7359d482 2101 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
d6ec53e0 2102 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
95c8bc36 2103 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
7359d482 2104 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
d6ec53e0 2105 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
7359d482 2106 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
d6ec53e0 2107 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
7359d482
PZ		 2108 dwc2_hcd_dump_frrem(hsotg);
2109 dwc2_dump_global_registers(hsotg);
2110 dwc2_dump_host_registers(hsotg);
2111 dev_dbg(hsotg->dev,
2112 "************************************************************\n");
2113 dev_dbg(hsotg->dev, "\n");
2114#endif
2115}
2116
2117/*
2118 * NOTE: This function will be removed once the peripheral controller code
2119 * is integrated and the driver is stable
2120 */
2121void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
2122{
2123#ifdef DWC2_DUMP_FRREM
2124 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
2125 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2126 hsotg->frrem_samples, hsotg->frrem_accum,
2127 hsotg->frrem_samples > 0 ?
2128 hsotg->frrem_accum / hsotg->frrem_samples : 0);
2129 dev_dbg(hsotg->dev, "\n");
2130 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
2131 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2132 hsotg->hfnum_7_samples,
2133 hsotg->hfnum_7_frrem_accum,
2134 hsotg->hfnum_7_samples > 0 ?
2135 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
2136 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
2137 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2138 hsotg->hfnum_0_samples,
2139 hsotg->hfnum_0_frrem_accum,
2140 hsotg->hfnum_0_samples > 0 ?
2141 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
2142 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
2143 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2144 hsotg->hfnum_other_samples,
2145 hsotg->hfnum_other_frrem_accum,
2146 hsotg->hfnum_other_samples > 0 ?
2147 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
2148 0);
2149 dev_dbg(hsotg->dev, "\n");
2150 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
2151 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2152 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
2153 hsotg->hfnum_7_samples_a > 0 ?
2154 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
2155 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
2156 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2157 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
2158 hsotg->hfnum_0_samples_a > 0 ?
2159 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
2160 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
2161 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2162 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
2163 hsotg->hfnum_other_samples_a > 0 ?
2164 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
2165 : 0);
2166 dev_dbg(hsotg->dev, "\n");
2167 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
2168 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2169 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
2170 hsotg->hfnum_7_samples_b > 0 ?
2171 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
2172 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
2173 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2174 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
2175 (hsotg->hfnum_0_samples_b > 0) ?
2176 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
2177 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
2178 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2179 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
2180 (hsotg->hfnum_other_samples_b > 0) ?
2181 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
2182 : 0);
2183#endif
2184}
2185
2186struct wrapper_priv_data {
2187 struct dwc2_hsotg *hsotg;
2188};
2189
2190/* Gets the dwc2_hsotg from a usb_hcd */
2191static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
2192{
2193 struct wrapper_priv_data *p;
2194
2195 p = (struct wrapper_priv_data *) &hcd->hcd_priv;
2196 return p->hsotg;
2197}
2198
2199static int _dwc2_hcd_start(struct usb_hcd *hcd);
2200
2201void dwc2_host_start(struct dwc2_hsotg *hsotg)
2202{
2203 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2204
2205 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
2206 _dwc2_hcd_start(hcd);
2207}
2208
2209void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
2210{
2211 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2212
2213 hcd->self.is_b_host = 0;
2214}
2215
2216void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
2217 int *hub_port)
2218{
2219 struct urb *urb = context;
2220
2221 if (urb->dev->tt)
2222 *hub_addr = urb->dev->tt->hub->devnum;
2223 else
2224 *hub_addr = 0;
2225 *hub_port = urb->dev->ttport;
2226}
2227
2228int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
2229{
2230 struct urb *urb = context;
2231
2232 return urb->dev->speed;
2233}
2234
2235static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2236 struct urb *urb)
2237{
2238 struct usb_bus *bus = hcd_to_bus(hcd);
2239
2240 if (urb->interval)
2241 bus->bandwidth_allocated += bw / urb->interval;
2242 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2243 bus->bandwidth_isoc_reqs++;
2244 else
2245 bus->bandwidth_int_reqs++;
2246}
2247
2248static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2249 struct urb *urb)
2250{
2251 struct usb_bus *bus = hcd_to_bus(hcd);
2252
2253 if (urb->interval)
2254 bus->bandwidth_allocated -= bw / urb->interval;
2255 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2256 bus->bandwidth_isoc_reqs--;
2257 else
2258 bus->bandwidth_int_reqs--;
2259}
2260
2261/*
2262 * Sets the final status of an URB and returns it to the upper layer. Any
2263 * required cleanup of the URB is performed.
2264 *
2265 * Must be called with interrupt disabled and spinlock held
2266 */
0d012b98
PZ		 2267void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2268 int status)
7359d482 2269{
0d012b98 2270 struct urb *urb;
7359d482
PZ		 2271 int i;
2272
0d012b98
PZ		 2273 if (!qtd) {
2274 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
7359d482
PZ		 2275 return;
2276 }
2277
0d012b98
PZ		 2278 if (!qtd->urb) {
2279 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
7359d482
PZ		 2280 return;
2281 }
2282
0d012b98
PZ		 2283 urb = qtd->urb->priv;
2284 if (!urb) {
2285 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
2286 return;
2287 }
2288
2289 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
7359d482 2290
b49977a6
MK		 2291 if (dbg_urb(urb))
2292 dev_vdbg(hsotg->dev,
2293 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
2294 __func__, urb, usb_pipedevice(urb->pipe),
2295 usb_pipeendpoint(urb->pipe),
2296 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
2297 urb->actual_length);
7359d482 2298
7359d482
PZ		 2299
2300 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
0d012b98 2301 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
7359d482
PZ		 2302 for (i = 0; i < urb->number_of_packets; ++i) {
2303 urb->iso_frame_desc[i].actual_length =
2304 dwc2_hcd_urb_get_iso_desc_actual_length(
0d012b98 2305 qtd->urb, i);
7359d482 2306 urb->iso_frame_desc[i].status =
0d012b98 2307 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
7359d482
PZ		 2308 }
2309 }
2310
fe9b1773
GH		 2311 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
2312 for (i = 0; i < urb->number_of_packets; i++)
2313 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
2314 i, urb->iso_frame_desc[i].status);
2315 }
2316
7359d482 2317 urb->status = status;
7359d482
PZ		 2318 if (!status) {
2319 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
2320 urb->actual_length < urb->transfer_buffer_length)
2321 urb->status = -EREMOTEIO;
2322 }
2323
2324 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2325 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2326 struct usb_host_endpoint *ep = urb->ep;
2327
2328 if (ep)
2329 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
2330 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2331 urb);
2332 }
2333
c9e1c907 2334 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
0d012b98
PZ		 2335 urb->hcpriv = NULL;
2336 kfree(qtd->urb);
2337 qtd->urb = NULL;
7359d482
PZ		 2338
2339 spin_unlock(&hsotg->lock);
2340 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
2341 spin_lock(&hsotg->lock);
2342}
2343
2344/*
2345 * Work queue function for starting the HCD when A-Cable is connected
2346 */
2347static void dwc2_hcd_start_func(struct work_struct *work)
2348{
2349 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2350 start_work.work);
2351
2352 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
2353 dwc2_host_start(hsotg);
2354}
2355
2356/*
2357 * Reset work queue function
2358 */
2359static void dwc2_hcd_reset_func(struct work_struct *work)
2360{
2361 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2362 reset_work.work);
4a065c7b 2363 unsigned long flags;
7359d482
PZ		 2364 u32 hprt0;
2365
2366 dev_dbg(hsotg->dev, "USB RESET function called\n");
4a065c7b
DA		 2367
2368 spin_lock_irqsave(&hsotg->lock, flags);
2369
7359d482
PZ		 2370 hprt0 = dwc2_read_hprt0(hsotg);
2371 hprt0 &= ~HPRT0_RST;
95c8bc36 2372 dwc2_writel(hprt0, hsotg->regs + HPRT0);
7359d482 2373 hsotg->flags.b.port_reset_change = 1;
4a065c7b
DA		 2374
2375 spin_unlock_irqrestore(&hsotg->lock, flags);
7359d482
PZ		 2376}
2377
2378/*
2379 * =========================================================================
2380 * Linux HC Driver Functions
2381 * =========================================================================
2382 */
2383
2384/*
2385 * Initializes the DWC_otg controller and its root hub and prepares it for host
2386 * mode operation. Activates the root port. Returns 0 on success and a negative
2387 * error code on failure.
2388 */
2389static int _dwc2_hcd_start(struct usb_hcd *hcd)
2390{
2391 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2392 struct usb_bus *bus = hcd_to_bus(hcd);
2393 unsigned long flags;
2394
2395 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
2396
2397 spin_lock_irqsave(&hsotg->lock, flags);
31927b6b 2398 hsotg->lx_state = DWC2_L0;
7359d482 2399 hcd->state = HC_STATE_RUNNING;
31927b6b 2400 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
7359d482
PZ		 2401
2402 if (dwc2_is_device_mode(hsotg)) {
2403 spin_unlock_irqrestore(&hsotg->lock, flags);
2404 return 0; /* why 0 ?? */
2405 }
2406
2407 dwc2_hcd_reinit(hsotg);
2408
2409 /* Initialize and connect root hub if one is not already attached */
2410 if (bus->root_hub) {
2411 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
2412 /* Inform the HUB driver to resume */
2413 usb_hcd_resume_root_hub(hcd);
2414 }
2415
2416 spin_unlock_irqrestore(&hsotg->lock, flags);
2417 return 0;
2418}
2419
2420/*
2421 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
2422 * stopped.
2423 */
2424static void _dwc2_hcd_stop(struct usb_hcd *hcd)
2425{
2426 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2427 unsigned long flags;
2428
5bbf6ce0
GH		 2429 /* Turn off all host-specific interrupts */
2430 dwc2_disable_host_interrupts(hsotg);
2431
091473ad
GH		 2432 /* Wait for interrupt processing to finish */
2433 synchronize_irq(hcd->irq);
2434
7359d482 2435 spin_lock_irqsave(&hsotg->lock, flags);
091473ad 2436 /* Ensure hcd is disconnected */
6a659531 2437 dwc2_hcd_disconnect(hsotg, true);
7359d482 2438 dwc2_hcd_stop(hsotg);
31927b6b
GH		 2439 hsotg->lx_state = DWC2_L3;
2440 hcd->state = HC_STATE_HALT;
2441 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
7359d482
PZ		 2442 spin_unlock_irqrestore(&hsotg->lock, flags);
2443
2444 usleep_range(1000, 3000);
2445}
2446
99a65798
GH		 2447static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
2448{
2449 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
a2a23d3f
GH		 2450 unsigned long flags;
2451 int ret = 0;
2452 u32 hprt0;
2453
2454 spin_lock_irqsave(&hsotg->lock, flags);
2455
2456 if (hsotg->lx_state != DWC2_L0)
2457 goto unlock;
2458
2459 if (!HCD_HW_ACCESSIBLE(hcd))
2460 goto unlock;
2461
2462 if (!hsotg->core_params->hibernation)
2463 goto skip_power_saving;
2464
2465 /*
2466 * Drive USB suspend and disable port Power
2467 * if usb bus is not suspended.
2468 */
2469 if (!hsotg->bus_suspended) {
2470 hprt0 = dwc2_read_hprt0(hsotg);
2471 hprt0 |= HPRT0_SUSP;
2472 hprt0 &= ~HPRT0_PWR;
2473 dwc2_writel(hprt0, hsotg->regs + HPRT0);
2474 }
2475
2476 /* Enter hibernation */
2477 ret = dwc2_enter_hibernation(hsotg);
2478 if (ret) {
2479 if (ret != -ENOTSUPP)
2480 dev_err(hsotg->dev,
2481 "enter hibernation failed\n");
2482 goto skip_power_saving;
2483 }
2484
2485 /* Ask phy to be suspended */
2486 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
2487 spin_unlock_irqrestore(&hsotg->lock, flags);
2488 usb_phy_set_suspend(hsotg->uphy, true);
2489 spin_lock_irqsave(&hsotg->lock, flags);
2490 }
2491
2492 /* After entering hibernation, hardware is no more accessible */
2493 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
99a65798 2494
a2a23d3f 2495skip_power_saving:
99a65798 2496 hsotg->lx_state = DWC2_L2;
a2a23d3f
GH		 2497unlock:
2498 spin_unlock_irqrestore(&hsotg->lock, flags);
2499
2500 return ret;
99a65798
GH		 2501}
2502
2503static int _dwc2_hcd_resume(struct usb_hcd *hcd)
2504{
2505 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
a2a23d3f
GH		 2506 unsigned long flags;
2507 int ret = 0;
2508
2509 spin_lock_irqsave(&hsotg->lock, flags);
2510
2511 if (hsotg->lx_state != DWC2_L2)
2512 goto unlock;
2513
2514 if (!hsotg->core_params->hibernation) {
2515 hsotg->lx_state = DWC2_L0;
2516 goto unlock;
2517 }
2518
2519 /*
2520 * Set HW accessible bit before powering on the controller
2521 * since an interrupt may rise.
2522 */
2523 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
2524
2525 /*
2526 * Enable power if not already done.
2527 * This must not be spinlocked since duration
2528 * of this call is unknown.
2529 */
2530 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
2531 spin_unlock_irqrestore(&hsotg->lock, flags);
2532 usb_phy_set_suspend(hsotg->uphy, false);
2533 spin_lock_irqsave(&hsotg->lock, flags);
2534 }
2535
2536 /* Exit hibernation */
2537 ret = dwc2_exit_hibernation(hsotg, true);
2538 if (ret && (ret != -ENOTSUPP))
2539 dev_err(hsotg->dev, "exit hibernation failed\n");
99a65798
GH		 2540
2541 hsotg->lx_state = DWC2_L0;
a2a23d3f
GH		 2542
2543 spin_unlock_irqrestore(&hsotg->lock, flags);
2544
2545 if (hsotg->bus_suspended) {
2546 spin_lock_irqsave(&hsotg->lock, flags);
2547 hsotg->flags.b.port_suspend_change = 1;
2548 spin_unlock_irqrestore(&hsotg->lock, flags);
2549 dwc2_port_resume(hsotg);
2550 } else {
5634e016
GH		 2551 /* Wait for controller to correctly update D+/D- level */
2552 usleep_range(3000, 5000);
2553
a2a23d3f
GH		 2554 /*
2555 * Clear Port Enable and Port Status changes.
2556 * Enable Port Power.
2557 */
2558 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET |
2559 HPRT0_ENACHG, hsotg->regs + HPRT0);
2560 /* Wait for controller to detect Port Connect */
5634e016 2561 usleep_range(5000, 7000);
a2a23d3f
GH		 2562 }
2563
2564 return ret;
2565unlock:
2566 spin_unlock_irqrestore(&hsotg->lock, flags);
2567
2568 return ret;
99a65798
GH		 2569}
2570
7359d482
PZ		 2571/* Returns the current frame number */
2572static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
2573{
2574 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2575
2576 return dwc2_hcd_get_frame_number(hsotg);
2577}
2578
2579static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
2580 char *fn_name)
2581{
2582#ifdef VERBOSE_DEBUG
2583 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2584 char *pipetype;
2585 char *speed;
2586
2587 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
2588 dev_vdbg(hsotg->dev, " Device address: %d\n",
2589 usb_pipedevice(urb->pipe));
2590 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
2591 usb_pipeendpoint(urb->pipe),
2592 usb_pipein(urb->pipe) ? "IN" : "OUT");
2593
2594 switch (usb_pipetype(urb->pipe)) {
2595 case PIPE_CONTROL:
2596 pipetype = "CONTROL";
2597 break;
2598 case PIPE_BULK:
2599 pipetype = "BULK";
2600 break;
2601 case PIPE_INTERRUPT:
2602 pipetype = "INTERRUPT";
2603 break;
2604 case PIPE_ISOCHRONOUS:
2605 pipetype = "ISOCHRONOUS";
2606 break;
2607 default:
2608 pipetype = "UNKNOWN";
2609 break;
2610 }
2611
2612 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
2613 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
2614 "IN" : "OUT");
2615
2616 switch (urb->dev->speed) {
2617 case USB_SPEED_HIGH:
2618 speed = "HIGH";
2619 break;
2620 case USB_SPEED_FULL:
2621 speed = "FULL";
2622 break;
2623 case USB_SPEED_LOW:
2624 speed = "LOW";
2625 break;
2626 default:
2627 speed = "UNKNOWN";
2628 break;
2629 }
2630
2631 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
2632 dev_vdbg(hsotg->dev, " Max packet size: %d\n",
2633 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
2634 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
2635 urb->transfer_buffer_length);
157dfaac
PZ		 2636 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
2637 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
2638 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
2639 urb->setup_packet, (unsigned long)urb->setup_dma);
7359d482
PZ		 2640 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
2641
2642 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2643 int i;
2644
2645 for (i = 0; i < urb->number_of_packets; i++) {
2646 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
2647 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
2648 urb->iso_frame_desc[i].offset,
2649 urb->iso_frame_desc[i].length);
2650 }
2651 }
2652#endif
2653}
2654
2655/*
2656 * Starts processing a USB transfer request specified by a USB Request Block
2657 * (URB). mem_flags indicates the type of memory allocation to use while
2658 * processing this URB.
2659 */
2660static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
2661 gfp_t mem_flags)
2662{
2663 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2664 struct usb_host_endpoint *ep = urb->ep;
2665 struct dwc2_hcd_urb *dwc2_urb;
2666 int i;
c9e1c907 2667 int retval;
7359d482 2668 int alloc_bandwidth = 0;
7359d482
PZ		 2669 u8 ep_type = 0;
2670 u32 tflags = 0;
2671 void *buf;
2672 unsigned long flags;
b58e6cee
MYK		 2673 struct dwc2_qh *qh;
2674 bool qh_allocated = false;
b5a468a6 2675 struct dwc2_qtd *qtd;
7359d482 2676
b49977a6
MK		 2677 if (dbg_urb(urb)) {
2678 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
2679 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
2680 }
7359d482
PZ		 2681
2682 if (ep == NULL)
2683 return -EINVAL;
2684
2685 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2686 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2687 spin_lock_irqsave(&hsotg->lock, flags);
2688 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
2689 alloc_bandwidth = 1;
2690 spin_unlock_irqrestore(&hsotg->lock, flags);
2691 }
2692
2693 switch (usb_pipetype(urb->pipe)) {
2694 case PIPE_CONTROL:
2695 ep_type = USB_ENDPOINT_XFER_CONTROL;
2696 break;
2697 case PIPE_ISOCHRONOUS:
2698 ep_type = USB_ENDPOINT_XFER_ISOC;
2699 break;
2700 case PIPE_BULK:
2701 ep_type = USB_ENDPOINT_XFER_BULK;
2702 break;
2703 case PIPE_INTERRUPT:
2704 ep_type = USB_ENDPOINT_XFER_INT;
2705 break;
2706 default:
2707 dev_warn(hsotg->dev, "Wrong ep type\n");
2708 }
2709
2710 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
2711 mem_flags);
2712 if (!dwc2_urb)
2713 return -ENOMEM;
2714
2715 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
2716 usb_pipeendpoint(urb->pipe), ep_type,
2717 usb_pipein(urb->pipe),
2718 usb_maxpacket(urb->dev, urb->pipe,
2719 !(usb_pipein(urb->pipe))));
2720
2721 buf = urb->transfer_buffer;
25a49445 2722
7359d482 2723 if (hcd->self.uses_dma) {
25a49445
PZ		 2724 if (!buf && (urb->transfer_dma & 3)) {
2725 dev_err(hsotg->dev,
2726 "%s: unaligned transfer with no transfer_buffer",
2727 __func__);
2728 retval = -EINVAL;
33ad261a 2729 goto fail0;
25a49445 2730 }
7359d482
PZ		 2731 }
2732
2733 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
2734 tflags |= URB_GIVEBACK_ASAP;
2735 if (urb->transfer_flags & URB_ZERO_PACKET)
2736 tflags |= URB_SEND_ZERO_PACKET;
2737
2738 dwc2_urb->priv = urb;
2739 dwc2_urb->buf = buf;
2740 dwc2_urb->dma = urb->transfer_dma;
2741 dwc2_urb->length = urb->transfer_buffer_length;
2742 dwc2_urb->setup_packet = urb->setup_packet;
2743 dwc2_urb->setup_dma = urb->setup_dma;
2744 dwc2_urb->flags = tflags;
2745 dwc2_urb->interval = urb->interval;
2746 dwc2_urb->status = -EINPROGRESS;
2747
2748 for (i = 0; i < urb->number_of_packets; ++i)
2749 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
2750 urb->iso_frame_desc[i].offset,
2751 urb->iso_frame_desc[i].length);
2752
2753 urb->hcpriv = dwc2_urb;
b58e6cee
MYK		 2754 qh = (struct dwc2_qh *) ep->hcpriv;
2755 /* Create QH for the endpoint if it doesn't exist */
2756 if (!qh) {
2757 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
2758 if (!qh) {
2759 retval = -ENOMEM;
2760 goto fail0;
2761 }
2762 ep->hcpriv = qh;
2763 qh_allocated = true;
2764 }
c9e1c907 2765
b5a468a6
MYK		 2766 qtd = kzalloc(sizeof(*qtd), mem_flags);
2767 if (!qtd) {
2768 retval = -ENOMEM;
2769 goto fail1;
2770 }
2771
c9e1c907
PZ		 2772 spin_lock_irqsave(&hsotg->lock, flags);
2773 retval = usb_hcd_link_urb_to_ep(hcd, urb);
c9e1c907 2774 if (retval)
b5a468a6 2775 goto fail2;
c9e1c907 2776
b5a468a6 2777 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
c9e1c907 2778 if (retval)
b5a468a6 2779 goto fail3;
c9e1c907
PZ		 2780
2781 if (alloc_bandwidth) {
c9e1c907
PZ		 2782 dwc2_allocate_bus_bandwidth(hcd,
2783 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2784 urb);
7359d482
PZ		 2785 }
2786
33ad261a
GH		 2787 spin_unlock_irqrestore(&hsotg->lock, flags);
2788
c9e1c907
PZ		 2789 return 0;
2790
b5a468a6 2791fail3:
c9e1c907
PZ		 2792 dwc2_urb->priv = NULL;
2793 usb_hcd_unlink_urb_from_ep(hcd, urb);
16e80218
DA		 2794 if (qh_allocated && qh->channel && qh->channel->qh == qh)
2795 qh->channel->qh = NULL;
b5a468a6 2796fail2:
33ad261a 2797 spin_unlock_irqrestore(&hsotg->lock, flags);
c9e1c907 2798 urb->hcpriv = NULL;
b5a468a6
MYK		 2799 kfree(qtd);
2800fail1:
b58e6cee
MYK		 2801 if (qh_allocated) {
2802 struct dwc2_qtd *qtd2, *qtd2_tmp;
2803
2804 ep->hcpriv = NULL;
2805 dwc2_hcd_qh_unlink(hsotg, qh);
2806 /* Free each QTD in the QH's QTD list */
2807 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
2808 qtd_list_entry)
2809 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
2810 dwc2_hcd_qh_free(hsotg, qh);
2811 }
33ad261a 2812fail0:
c9e1c907
PZ		 2813 kfree(dwc2_urb);
2814
7359d482
PZ		 2815 return retval;
2816}
2817
2818/*
2819 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
2820 */
2821static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2822 int status)
2823{
2824 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
c9e1c907 2825 int rc;
7359d482
PZ		 2826 unsigned long flags;
2827
2828 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
2829 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
2830
2831 spin_lock_irqsave(&hsotg->lock, flags);
2832
c9e1c907
PZ		 2833 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
2834 if (rc)
2835 goto out;
2836
7359d482
PZ		 2837 if (!urb->hcpriv) {
2838 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
2839 goto out;
2840 }
2841
2842 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
2843
c9e1c907
PZ		 2844 usb_hcd_unlink_urb_from_ep(hcd, urb);
2845
7359d482
PZ		 2846 kfree(urb->hcpriv);
2847 urb->hcpriv = NULL;
2848
2849 /* Higher layer software sets URB status */
2850 spin_unlock(&hsotg->lock);
2851 usb_hcd_giveback_urb(hcd, urb, status);
2852 spin_lock(&hsotg->lock);
2853
2854 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
2855 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
2856out:
2857 spin_unlock_irqrestore(&hsotg->lock, flags);
2858
2859 return rc;
2860}
2861
2862/*
2863 * Frees resources in the DWC_otg controller related to a given endpoint. Also
2864 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
2865 * must already be dequeued.
2866 */
2867static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
2868 struct usb_host_endpoint *ep)
2869{
2870 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2871
2872 dev_dbg(hsotg->dev,
2873 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
2874 ep->desc.bEndpointAddress, ep->hcpriv);
2875 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
2876}
2877
2878/*
2879 * Resets endpoint specific parameter values, in current version used to reset
2880 * the data toggle (as a WA). This function can be called from usb_clear_halt
2881 * routine.
2882 */
2883static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
2884 struct usb_host_endpoint *ep)
2885{
2886 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
7359d482
PZ		 2887 unsigned long flags;
2888
2889 dev_dbg(hsotg->dev,
2890 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
2891 ep->desc.bEndpointAddress);
2892
7359d482 2893 spin_lock_irqsave(&hsotg->lock, flags);
7359d482 2894 dwc2_hcd_endpoint_reset(hsotg, ep);
7359d482
PZ		 2895 spin_unlock_irqrestore(&hsotg->lock, flags);
2896}
2897
2898/*
2899 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
2900 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
2901 * interrupt.
2902 *
2903 * This function is called by the USB core when an interrupt occurs
2904 */
2905static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
2906{
2907 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
7359d482 2908
ca18f4a6 2909 return dwc2_handle_hcd_intr(hsotg);
7359d482
PZ		 2910}
2911
2912/*
2913 * Creates Status Change bitmap for the root hub and root port. The bitmap is
2914 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
2915 * is the status change indicator for the single root port. Returns 1 if either
2916 * change indicator is 1, otherwise returns 0.
2917 */
2918static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
2919{
2920 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2921
2922 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
2923 return buf[0] != 0;
2924}
2925
2926/* Handles hub class-specific requests */
2927static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
2928 u16 windex, char *buf, u16 wlength)
2929{
2930 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
2931 wvalue, windex, buf, wlength);
2932 return retval;
2933}
2934
2935/* Handles hub TT buffer clear completions */
2936static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
2937 struct usb_host_endpoint *ep)
2938{
2939 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2940 struct dwc2_qh *qh;
2941 unsigned long flags;
2942
2943 qh = ep->hcpriv;
2944 if (!qh)
2945 return;
2946
2947 spin_lock_irqsave(&hsotg->lock, flags);
2948 qh->tt_buffer_dirty = 0;
2949
2950 if (hsotg->flags.b.port_connect_status)
2951 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
2952
2953 spin_unlock_irqrestore(&hsotg->lock, flags);
2954}
2955
2956static struct hc_driver dwc2_hc_driver = {
2957 .description = "dwc2_hsotg",
2958 .product_desc = "DWC OTG Controller",
2959 .hcd_priv_size = sizeof(struct wrapper_priv_data),
2960
2961 .irq = _dwc2_hcd_irq,
2962 .flags = HCD_MEMORY | HCD_USB2,
2963
2964 .start = _dwc2_hcd_start,
2965 .stop = _dwc2_hcd_stop,
2966 .urb_enqueue = _dwc2_hcd_urb_enqueue,
2967 .urb_dequeue = _dwc2_hcd_urb_dequeue,
2968 .endpoint_disable = _dwc2_hcd_endpoint_disable,
2969 .endpoint_reset = _dwc2_hcd_endpoint_reset,
2970 .get_frame_number = _dwc2_hcd_get_frame_number,
2971
2972 .hub_status_data = _dwc2_hcd_hub_status_data,
2973 .hub_control = _dwc2_hcd_hub_control,
2974 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
99a65798
GH		 2975
2976 .bus_suspend = _dwc2_hcd_suspend,
2977 .bus_resume = _dwc2_hcd_resume,
3bc04e28
DA		 2978
2979 .map_urb_for_dma = dwc2_map_urb_for_dma,
2980 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma,
7359d482
PZ		 2981};
2982
2983/*
2984 * Frees secondary storage associated with the dwc2_hsotg structure contained
2985 * in the struct usb_hcd field
2986 */
2987static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
2988{
2989 u32 ahbcfg;
2990 u32 dctl;
2991 int i;
2992
2993 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
2994
2995 /* Free memory for QH/QTD lists */
2996 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
2997 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
2998 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
2999 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
3000 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
3001 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
3002
3003 /* Free memory for the host channels */
3004 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
3005 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
3006
3007 if (chan != NULL) {
3008 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
3009 i, chan);
3010 hsotg->hc_ptr_array[i] = NULL;
3011 kfree(chan);
3012 }
3013 }
3014
3015 if (hsotg->core_params->dma_enable > 0) {
3016 if (hsotg->status_buf) {
3017 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
3018 hsotg->status_buf,
3019 hsotg->status_buf_dma);
3020 hsotg->status_buf = NULL;
3021 }
3022 } else {
3023 kfree(hsotg->status_buf);
3024 hsotg->status_buf = NULL;
3025 }
3026
95c8bc36 3027 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
7359d482
PZ		 3028
3029 /* Disable all interrupts */
3030 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
95c8bc36
AS		 3031 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
3032 dwc2_writel(0, hsotg->regs + GINTMSK);
7359d482 3033
9badec2f 3034 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
95c8bc36 3035 dctl = dwc2_readl(hsotg->regs + DCTL);
7359d482 3036 dctl |= DCTL_SFTDISCON;
95c8bc36 3037 dwc2_writel(dctl, hsotg->regs + DCTL);
7359d482
PZ		 3038 }
3039
3040 if (hsotg->wq_otg) {
3041 if (!cancel_work_sync(&hsotg->wf_otg))
3042 flush_workqueue(hsotg->wq_otg);
3043 destroy_workqueue(hsotg->wq_otg);
3044 }
3045
7359d482
PZ		 3046 del_timer(&hsotg->wkp_timer);
3047}
3048
3049static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
3050{
3051 /* Turn off all host-specific interrupts */
3052 dwc2_disable_host_interrupts(hsotg);
3053
3054 dwc2_hcd_free(hsotg);
3055}
3056
7359d482
PZ		 3057/*
3058 * Initializes the HCD. This function allocates memory for and initializes the
3059 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
3060 * USB bus with the core and calls the hc_driver->start() function. It returns
3061 * a negative error on failure.
3062 */
ecb176c6 3063int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
7359d482
PZ		 3064{
3065 struct usb_hcd *hcd;
3066 struct dwc2_host_chan *channel;
9badec2f 3067 u32 hcfg;
7359d482 3068 int i, num_channels;
9badec2f 3069 int retval;
7359d482 3070
f5500ecc
DN		 3071 if (usb_disabled())
3072 return -ENODEV;
3073
e62662c7 3074 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
7359d482 3075
9badec2f 3076 retval = -ENOMEM;
7359d482 3077
95c8bc36 3078 hcfg = dwc2_readl(hsotg->regs + HCFG);
7359d482 3079 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
7359d482
PZ		 3080
3081#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3082 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
3083 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
3084 if (!hsotg->frame_num_array)
ba0e60d1 3085 goto error1;
7359d482
PZ		 3086 hsotg->last_frame_num_array = kzalloc(
3087 sizeof(*hsotg->last_frame_num_array) *
3088 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
3089 if (!hsotg->last_frame_num_array)
ba0e60d1 3090 goto error1;
7359d482
PZ		 3091 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
3092#endif
3093
a0112f48
MK		 3094 /* Check if the bus driver or platform code has setup a dma_mask */
3095 if (hsotg->core_params->dma_enable > 0 &&
3096 hsotg->dev->dma_mask == NULL) {
3097 dev_warn(hsotg->dev,
3098 "dma_mask not set, disabling DMA\n");
3099 hsotg->core_params->dma_enable = 0;
3100 hsotg->core_params->dma_desc_enable = 0;
3101 }
3102
ba0e60d1
PZ		 3103 /* Set device flags indicating whether the HCD supports DMA */
3104 if (hsotg->core_params->dma_enable > 0) {
30885313
PZ		 3105 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
3106 dev_warn(hsotg->dev, "can't set DMA mask\n");
25a49445
PZ		 3107 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
3108 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
ba0e60d1
PZ		 3109 }
3110
3111 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
3112 if (!hcd)
3113 goto error1;
3114
7de76ee1
MK		 3115 if (hsotg->core_params->dma_enable <= 0)
3116 hcd->self.uses_dma = 0;
3117
ba0e60d1
PZ		 3118 hcd->has_tt = 1;
3119
ba0e60d1
PZ		 3120 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg;
3121 hsotg->priv = hcd;
3122
7359d482
PZ		 3123 /*
3124 * Disable the global interrupt until all the interrupt handlers are
3125 * installed
3126 */
3127 dwc2_disable_global_interrupts(hsotg);
3128
6706c721 3129 /* Initialize the DWC_otg core, and select the Phy type */
0fe239bc 3130 retval = dwc2_core_init(hsotg, true);
6706c721
MK		 3131 if (retval)
3132 goto error2;
3133
7359d482 3134 /* Create new workqueue and init work */
53510352 3135 retval = -ENOMEM;
050232a7 3136 hsotg->wq_otg = create_singlethread_workqueue("dwc2");
7359d482
PZ		 3137 if (!hsotg->wq_otg) {
3138 dev_err(hsotg->dev, "Failed to create workqueue\n");
3139 goto error2;
3140 }
3141 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
3142
7359d482
PZ		 3143 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
3144 (unsigned long)hsotg);
3145
3146 /* Initialize the non-periodic schedule */
3147 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
3148 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
3149
3150 /* Initialize the periodic schedule */
3151 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
3152 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
3153 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
3154 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
3155
3156 /*
3157 * Create a host channel descriptor for each host channel implemented
3158 * in the controller. Initialize the channel descriptor array.
3159 */
3160 INIT_LIST_HEAD(&hsotg->free_hc_list);
3161 num_channels = hsotg->core_params->host_channels;
3162 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
3163
3164 for (i = 0; i < num_channels; i++) {
3165 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
3166 if (channel == NULL)
3167 goto error3;
3168 channel->hc_num = i;
3169 hsotg->hc_ptr_array[i] = channel;
3170 }
3171
20f2eb9c
DC		 3172 if (hsotg->core_params->uframe_sched > 0)
3173 dwc2_hcd_init_usecs(hsotg);
3174
7359d482
PZ		 3175 /* Initialize hsotg start work */
3176 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
3177
3178 /* Initialize port reset work */
3179 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
3180
3181 /*
3182 * Allocate space for storing data on status transactions. Normally no
3183 * data is sent, but this space acts as a bit bucket. This must be
3184 * done after usb_add_hcd since that function allocates the DMA buffer
3185 * pool.
3186 */
3187 if (hsotg->core_params->dma_enable > 0)
3188 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
3189 DWC2_HCD_STATUS_BUF_SIZE,
3190 &hsotg->status_buf_dma, GFP_KERNEL);
3191 else
3192 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
3193 GFP_KERNEL);
3194
3195 if (!hsotg->status_buf)
3196 goto error3;
3197
3b5fcc9a
GH		 3198 /*
3199 * Create kmem caches to handle descriptor buffers in descriptor
3200 * DMA mode.
3201 * Alignment must be set to 512 bytes.
3202 */
3203 if (hsotg->core_params->dma_desc_enable ||
3204 hsotg->core_params->dma_desc_fs_enable) {
3205 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
3206 sizeof(struct dwc2_hcd_dma_desc) *
3207 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
3208 NULL);
3209 if (!hsotg->desc_gen_cache) {
3210 dev_err(hsotg->dev,
3211 "unable to create dwc2 generic desc cache\n");
3212
3213 /*
3214 * Disable descriptor dma mode since it will not be
3215 * usable.
3216 */
3217 hsotg->core_params->dma_desc_enable = 0;
3218 hsotg->core_params->dma_desc_fs_enable = 0;
3219 }
3220
3221 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
3222 sizeof(struct dwc2_hcd_dma_desc) *
3223 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
3224 if (!hsotg->desc_hsisoc_cache) {
3225 dev_err(hsotg->dev,
3226 "unable to create dwc2 hs isoc desc cache\n");
3227
3228 kmem_cache_destroy(hsotg->desc_gen_cache);
3229
3230 /*
3231 * Disable descriptor dma mode since it will not be
3232 * usable.
3233 */
3234 hsotg->core_params->dma_desc_enable = 0;
3235 hsotg->core_params->dma_desc_fs_enable = 0;
3236 }
3237 }
3238
7359d482
PZ		 3239 hsotg->otg_port = 1;
3240 hsotg->frame_list = NULL;
3241 hsotg->frame_list_dma = 0;
3242 hsotg->periodic_qh_count = 0;
3243
3244 /* Initiate lx_state to L3 disconnected state */
3245 hsotg->lx_state = DWC2_L3;
3246
3247 hcd->self.otg_port = hsotg->otg_port;
3248
3249 /* Don't support SG list at this point */
3250 hcd->self.sg_tablesize = 0;
3251
9df4ceac
MYK		 3252 if (!IS_ERR_OR_NULL(hsotg->uphy))
3253 otg_set_host(hsotg->uphy->otg, &hcd->self);
3254
7359d482
PZ		 3255 /*
3256 * Finish generic HCD initialization and start the HCD. This function
3257 * allocates the DMA buffer pool, registers the USB bus, requests the
3258 * IRQ line, and calls hcd_start method.
3259 */
66513f49 3260 retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
7359d482 3261 if (retval < 0)
3b5fcc9a 3262 goto error4;
7359d482 3263
3c9740a1
PC		 3264 device_wakeup_enable(hcd->self.controller);
3265
7359d482
PZ		 3266 dwc2_hcd_dump_state(hsotg);
3267
3268 dwc2_enable_global_interrupts(hsotg);
3269
3270 return 0;
3271
3b5fcc9a
GH		 3272error4:
3273 kmem_cache_destroy(hsotg->desc_gen_cache);
3274 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
7359d482
PZ		 3275error3:
3276 dwc2_hcd_release(hsotg);
3277error2:
ba0e60d1
PZ		 3278 usb_put_hcd(hcd);
3279error1:
7359d482
PZ		 3280 kfree(hsotg->core_params);
3281
3282#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3283 kfree(hsotg->last_frame_num_array);
3284 kfree(hsotg->frame_num_array);
3285#endif
3286
e62662c7 3287 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
7359d482
PZ		 3288 return retval;
3289}
7359d482
PZ		 3290
3291/*
3292 * Removes the HCD.
3293 * Frees memory and resources associated with the HCD and deregisters the bus.
3294 */
e62662c7 3295void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
7359d482
PZ		 3296{
3297 struct usb_hcd *hcd;
3298
e62662c7 3299 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
7359d482
PZ		 3300
3301 hcd = dwc2_hsotg_to_hcd(hsotg);
e62662c7 3302 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
7359d482
PZ		 3303
3304 if (!hcd) {
e62662c7 3305 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
7359d482
PZ		 3306 __func__);
3307 return;
3308 }
3309
9df4ceac
MYK		 3310 if (!IS_ERR_OR_NULL(hsotg->uphy))
3311 otg_set_host(hsotg->uphy->otg, NULL);
3312
7359d482
PZ		 3313 usb_remove_hcd(hcd);
3314 hsotg->priv = NULL;
3b5fcc9a
GH		 3315
3316 kmem_cache_destroy(hsotg->desc_gen_cache);
3317 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
3318
7359d482 3319 dwc2_hcd_release(hsotg);
ba0e60d1 3320 usb_put_hcd(hcd);
7359d482
PZ		 3321
3322#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3323 kfree(hsotg->last_frame_num_array);
3324 kfree(hsotg->frame_num_array);
3325#endif
7359d482 3326}
Linux 6.x block layer and io_uring tree(s)